| /* |
| * Copyright 2016 Freescale Semiconductor, Inc. |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| #ifndef __LS1012ARDB_H__ |
| #define __LS1012ARDB_H__ |
| |
| #include "ls1012a_common.h" |
| |
| /* DDR */ |
| #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| #define CONFIG_CHIP_SELECTS_PER_CTRL 1 |
| #define CONFIG_NR_DRAM_BANKS 2 |
| #define CONFIG_SYS_SDRAM_SIZE 0x40000000 |
| #define CONFIG_CMD_MEMINFO |
| #define CONFIG_CMD_MEMTEST |
| #define CONFIG_SYS_MEMTEST_START 0x80000000 |
| #define CONFIG_SYS_MEMTEST_END 0x9fffffff |
| |
| /* |
| * USB |
| */ |
| #define CONFIG_HAS_FSL_XHCI_USB |
| |
| #ifdef CONFIG_HAS_FSL_XHCI_USB |
| #define CONFIG_USB_XHCI_FSL |
| #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
| #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 |
| #endif |
| |
| /* |
| * I2C IO expander |
| */ |
| |
| #define I2C_MUX_IO1_ADDR 0x24 |
| #define __SW_BOOT_MASK 0xFC |
| #define __SW_BOOT_EMU 0x10 |
| #define __SW_BOOT_BANK1 0x00 |
| #define __SW_BOOT_BANK2 0x01 |
| #define __SW_REV_MASK 0x07 |
| #define __SW_REV_A 0xF8 |
| #define __SW_REV_B 0xF0 |
| |
| /* MMC */ |
| #ifdef CONFIG_MMC |
| #define CONFIG_FSL_ESDHC |
| #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 |
| #endif |
| |
| /* SATA */ |
| #define CONFIG_LIBATA |
| #define CONFIG_SCSI |
| #define CONFIG_SCSI_AHCI |
| #define CONFIG_SCSI_AHCI_PLAT |
| #define CONFIG_CMD_SCSI |
| |
| #define CONFIG_SYS_SATA AHCI_BASE_ADDR |
| |
| #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 |
| #define CONFIG_SYS_SCSI_MAX_LUN 1 |
| #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ |
| CONFIG_SYS_SCSI_MAX_LUN) |
| |
| #define CONFIG_PCIE1 /* PCIE controller 1 */ |
| |
| #define CONFIG_NET_MULTI |
| #define CONFIG_PCI_SCAN_SHOW |
| #define CONFIG_CMD_PCI |
| |
| #define CONFIG_CMD_MEMINFO |
| #define CONFIG_CMD_MEMTEST |
| #define CONFIG_SYS_MEMTEST_START 0x80000000 |
| #define CONFIG_SYS_MEMTEST_END 0x9fffffff |
| |
| #endif /* __LS1012ARDB_H__ */ |
