| 0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 (433 MHz) |
| 0xf8000700 0x1202 // MIO configuration |
| 0xf8000704 0x1202 |
| 0xf8000708 0x202 |
| 0xf800070c 0x202 |
| 0xf8000710 0x202 |
| 0xf8000714 0x202 |
| 0xf8000718 0x202 |
| 0xf800071c 0x200 |
| 0xf8000720 0x202 |
| 0xf8000724 0x202 |
| 0xf8000728 0x202 |
| 0xf800072c 0x202 |
| 0xf8000730 0x202 |
| 0xf8000734 0x202 |
| 0xf8000738 0x12e1 |
| 0xf800073c 0x12e0 |
| 0xf8000740 0x1202 |
| 0xf8000744 0x1202 |
| 0xf8000748 0x1202 |
| 0xf800074c 0x1202 |
| 0xf8000750 0x1202 |
| 0xf8000754 0x1202 |
| 0xf8000758 0x1203 |
| 0xf800075c 0x1203 |
| 0xf8000760 0x1203 |
| 0xf8000764 0x203 |
| 0xf8000768 0x1203 |
| 0xf800076c 0x203 |
| 0xf8000770 0x304 |
| 0xf8000774 0x305 |
| 0xf8000778 0x304 |
| 0xf800077c 0x305 |
| 0xf8000780 0x304 |
| 0xf8000784 0x304 |
| 0xf8000788 0x304 |
| 0xf800078c 0x304 |
| 0xf8000790 0x305 |
| 0xf8000794 0x304 |
| 0xf8000798 0x304 |
| 0xf800079c 0x304 |
| 0xf80007a0 0x380 |
| 0xf80007a4 0x380 |
| 0xf80007a8 0x380 |
| 0xf80007ac 0x380 |
| 0xf80007b0 0x380 |
| 0xf80007b4 0x380 |
| 0xf80007b8 0x1200 |
| 0xf80007bc 0x1201 |
| 0xf80007c0 0x1240 |
| 0xf80007c4 0x1240 |
| 0xf80007c8 0x1240 |
| 0xf80007cc 0x1240 |
| 0xf80007d0 0x1280 |
| 0xf80007d4 0x1280 |
| 0xf8000830 0x2f0037 |
| 0xf8000834 0x3a0039 |
| 0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6 |
| 0xE000D000 0x800238C1 // QSPI config - divide-by-2 |
| 0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay |
| 0xE000D0A0 0xE2FF06EB // LQSPI_CFG - Quad read, dual flash |
