| /* |
| * Copyright (C) 2016 Freescale Semiconductor, Inc. |
| * Copyright 2017 NXP |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| #include <asm/arch/clock.h> |
| #include <asm/arch/crm_regs.h> |
| #include <asm/arch/iomux.h> |
| #include <asm/arch/imx-regs.h> |
| #include <asm/arch/mx6-pins.h> |
| #include <asm/arch/sys_proto.h> |
| #include <asm/gpio.h> |
| #include <asm/imx-common/boot_mode.h> |
| #include <asm/imx-common/iomux-v3.h> |
| #include <asm/imx-common/boot_mode.h> |
| #include <asm/io.h> |
| #include <asm/imx-common/mxc_i2c.h> |
| #include <linux/sizes.h> |
| #include <common.h> |
| #include <fsl_esdhc.h> |
| #include <mmc.h> |
| #include <i2c.h> |
| #include <miiphy.h> |
| #include <netdev.h> |
| #include <power/pmic.h> |
| #include <power/pfuze100_pmic.h> |
| #include "../common/pfuze.h" |
| #include <usb.h> |
| #include <usb/ehci-ci.h> |
| #include <asm/imx-common/video.h> |
| #include <micrel.h> |
| |
| #ifdef CONFIG_IMX_RDC |
| #include <asm/imx-common/rdc-sema.h> |
| #include <asm/arch/imx-rdc.h> |
| #endif |
| |
| #ifdef CONFIG_FSL_FASTBOOT |
| #include <fsl_fastboot.h> |
| #ifdef CONFIG_ANDROID_RECOVERY |
| #include <recovery.h> |
| #endif |
| #endif /*CONFIG_FSL_FASTBOOT*/ |
| |
| DECLARE_GLOBAL_DATA_PTR; |
| #define I2C_PMIC 1 |
| |
| #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
| PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ |
| PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
| PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ |
| PAD_CTL_ODE) |
| |
| #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ |
| PAD_CTL_SPEED_HIGH | \ |
| PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) |
| |
| #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ |
| PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) |
| |
| #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) |
| |
| #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
| PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ |
| PAD_CTL_ODE) |
| |
| #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ |
| PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) |
| |
| #define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_40ohm) |
| |
| #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ |
| PAD_CTL_DSE_40ohm) |
| |
| #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ |
| PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| int dram_init(void) |
| { |
| gd->ram_size = imx_ddr_size(); |
| |
| return 0; |
| } |
| |
| static iomux_v3_cfg_t const uart3_pads[] = { |
| MX6_PAD_QSPI1B_SS0_B__UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| MX6_PAD_QSPI1B_SCLK__UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const usdhc2_pads[] = { |
| MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const usdhc3_pads[] = { |
| MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| |
| /* CD pin */ |
| MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| |
| /* RST_B, used for power reset cycle */ |
| MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const usdhc4_pads[] = { |
| MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const usdhc4_emmc_pads[] = { |
| MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_RESET_B__USDHC4_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const wdog_b_pad = { |
| MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const fec1_pads[] = { |
| MX6_PAD_GPIO1_IO04__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_GPIO1_IO05__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const peri_3v3_pads[] = { |
| MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| static iomux_v3_cfg_t const phy_control_pads[] = { |
| /* 25MHz Ethernet PHY Clock */ |
| MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | |
| MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), |
| |
| /* ENET PHY Power */ |
| MX6_PAD_QSPI1B_DATA1__GPIO4_IO_25 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| |
| /* AR8031 PHY Reset */ |
| MX6_PAD_QSPI1B_DATA2__GPIO4_IO_26 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| static void setup_iomux_uart(void) |
| { |
| imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); |
| } |
| |
| static int setup_fec(int fec_id) |
| { |
| struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
| int reg, ret; |
| |
| /* Use 125M anatop loopback REF_CLK1 for ENET1, |
| * clear gpr1[13], gpr1[17] */ |
| clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); |
| |
| ret = enable_fec_anatop_clock(fec_id, ENET_125MHZ); |
| if (ret) |
| return ret; |
| |
| imx_iomux_v3_setup_multiple_pads(phy_control_pads, |
| ARRAY_SIZE(phy_control_pads)); |
| |
| /* Enable the ENET power, active low */ |
| gpio_request(IMX_GPIO_NR(4, 25), "fec power en"); |
| gpio_direction_output(IMX_GPIO_NR(4, 25) , 0); |
| |
| /* Reset AR8031 PHY */ |
| gpio_request(IMX_GPIO_NR(4, 26), "ar8031 reset"); |
| gpio_direction_output(IMX_GPIO_NR(4, 26) , 0); |
| mdelay(10); |
| gpio_set_value(IMX_GPIO_NR(4, 26), 1); |
| |
| reg = readl(&anatop->pll_enet); |
| reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; |
| writel(reg, &anatop->pll_enet); |
| |
| return 0; |
| } |
| |
| int board_eth_init(bd_t *bis) |
| { |
| imx_iomux_v3_setup_multiple_pads(fec1_pads, |
| ARRAY_SIZE(fec1_pads)); |
| |
| return cpu_eth_init(bis); |
| } |
| |
| int mx6_rgmii_rework(struct phy_device *phydev) |
| { |
| /* add necessary delays for RGMII, |
| * there are no board skew delays added |
| * additional rx data delay = 0, rx clk delay = 0.3ns, total = 1.5ns |
| * additional tx data delay = -0.42ns, tx clk delay = 0.96ns, |
| * total = 1.38ns |
| */ |
| |
| if (ksz9031_phy_extended_write(phydev, 0x2, |
| MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, |
| MII_KSZ9031_MOD_DATA_NO_POST_INC, |
| 0x0070)) |
| return -EIO; |
| |
| if (ksz9031_phy_extended_write(phydev, 0x2, |
| MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, |
| MII_KSZ9031_MOD_DATA_NO_POST_INC, |
| 0x7777)) |
| return -EIO; |
| |
| if (ksz9031_phy_extended_write(phydev, 0x2, |
| MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, |
| MII_KSZ9031_MOD_DATA_NO_POST_INC, |
| 0x0000)) |
| return -EIO; |
| |
| if (ksz9031_phy_extended_write(phydev, 0x2, |
| MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, |
| MII_KSZ9031_MOD_DATA_NO_POST_INC, |
| 0x03f4)) |
| return -EIO; |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_SYS_I2C |
| #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) |
| /* I2C1 for PMIC */ |
| static struct i2c_pads_info i2c_pad_info1 = { |
| .scl = { |
| .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, |
| .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, |
| .gp = IMX_GPIO_NR(1, 0), |
| }, |
| .sda = { |
| .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, |
| .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, |
| .gp = IMX_GPIO_NR(1, 1), |
| }, |
| }; |
| |
| /* I2C2 */ |
| struct i2c_pads_info i2c_pad_info2 = { |
| .scl = { |
| .i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC, |
| .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC, |
| .gp = IMX_GPIO_NR(1, 2), |
| }, |
| .sda = { |
| .i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC, |
| .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC, |
| .gp = IMX_GPIO_NR(1, 3), |
| }, |
| }; |
| |
| /* I2C4 */ |
| struct i2c_pads_info i2c_pad_info4 = { |
| .scl = { |
| .i2c_mode = MX6_PAD_CSI_DATA06__I2C4_SCL | PC, |
| .gpio_mode = MX6_PAD_CSI_DATA06__GPIO1_IO_20 | PC, |
| .gp = IMX_GPIO_NR(1, 20), |
| }, |
| .sda = { |
| .i2c_mode = MX6_PAD_CSI_DATA07__I2C4_SDA | PC, |
| .gpio_mode = MX6_PAD_CSI_DATA07__GPIO1_IO_21 | PC, |
| .gp = IMX_GPIO_NR(1, 21), |
| }, |
| }; |
| #endif |
| |
| #ifdef CONFIG_POWER |
| int power_init_board(void) |
| { |
| struct pmic *pfuze; |
| unsigned int reg; |
| int ret; |
| |
| pfuze = pfuze_common_init(I2C_PMIC); |
| if (!pfuze) |
| return -ENODEV; |
| |
| ret = pfuze_mode_init(pfuze, APS_PFM); |
| if (ret < 0) |
| return ret; |
| /* set SW3A to 1.2V for LPDDR2 */ |
| pmic_reg_read(pfuze, PFUZE100_SW3AVOL, ®); |
| reg &= ~0x3f; |
| reg |= 0x20; |
| pmic_reg_write(pfuze, PFUZE100_SW3AVOL, reg); |
| |
| /* set SW3A standby volatage 1.2V */ |
| pmic_reg_read(pfuze, PFUZE100_SW3ASTBY, ®); |
| reg &= ~0x3f; |
| reg |= 0x20; |
| pmic_reg_write(pfuze, PFUZE100_SW3ASTBY, reg); |
| |
| /* set SW1AB normal volatage 1.350V */ |
| pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, ®); |
| reg &= ~0x3f; |
| reg |= PFUZE100_SW1ABC_SETP(13500); |
| pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, reg); |
| |
| /* set SW1AB standby volatage 1.10V */ |
| pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®); |
| reg &= ~0x3f; |
| reg |= PFUZE100_SW1ABC_SETP(11000); |
| pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg); |
| |
| /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ |
| pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®); |
| reg &= ~0xc0; |
| reg |= 0x40; |
| pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg); |
| |
| pmic_reg_read(pfuze, PFUZE100_VGEN3VOL, ®); |
| reg &= ~LDO_VOL_MASK; |
| reg |= (LDOB_2_80V | (1 << LDO_EN)); |
| pmic_reg_write(pfuze, PFUZE100_VGEN3VOL, reg); |
| |
| /* set SWBST boost regulator mode */ |
| pmic_reg_read(pfuze, PFUZE100_SWBSTCON1, ®); |
| reg &= ~SWBST_MODE_MASK; |
| reg |= SWBST_MODE_AUTO << SWBST_MODE_SHIFT; |
| reg |= 0x40; |
| pmic_reg_write(pfuze, PFUZE100_SWBSTCON1, reg); |
| |
| return 0; |
| } |
| #elif defined(CONFIG_DM_PMIC_PFUZE100) |
| int power_init_board(void) |
| { |
| struct udevice *dev; |
| unsigned int reg; |
| int ret; |
| |
| dev = pfuze_common_init(); |
| if (!dev) |
| return -ENODEV; |
| |
| ret = pfuze_mode_init(dev, APS_PFM); |
| if (ret < 0) |
| return ret; |
| /* set SW3A to 1.2V for LPDDR2 */ |
| reg = pmic_reg_read(dev, PFUZE100_SW3AVOL); |
| reg &= ~0x3f; |
| reg |= 0x20; |
| pmic_reg_write(dev, PFUZE100_SW3AVOL, reg); |
| |
| /* set SW3A standby volatage 1.2V */ |
| reg = pmic_reg_read(dev, PFUZE100_SW3ASTBY); |
| reg &= ~0x3f; |
| reg |= 0x20; |
| pmic_reg_write(dev, PFUZE100_SW3ASTBY, reg); |
| |
| /* set SW1AB normal volatage 1.350V */ |
| reg = pmic_reg_read(dev, PFUZE100_SW1ABVOL); |
| reg &= ~0x3f; |
| reg |= PFUZE100_SW1ABC_SETP(13500); |
| pmic_reg_write(dev, PFUZE100_SW1ABVOL, reg); |
| |
| /* set SW1AB standby volatage 1.10V */ |
| reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); |
| reg &= ~0x3f; |
| reg |= PFUZE100_SW1ABC_SETP(11000); |
| pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); |
| |
| /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ |
| reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); |
| reg &= ~0xc0; |
| reg |= 0x40; |
| pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); |
| |
| reg = pmic_reg_read(dev, PFUZE100_VGEN3VOL); |
| reg &= ~LDO_VOL_MASK; |
| reg |= (LDOB_2_80V | (1 << LDO_EN)); |
| pmic_reg_write(dev, PFUZE100_VGEN3VOL, reg); |
| |
| /* set SWBST boost regulator mode */ |
| reg = pmic_reg_read(dev, PFUZE100_SWBSTCON1); |
| reg &= ~SWBST_MODE_MASK; |
| reg |= SWBST_MODE_AUTO << SWBST_MODE_SHIFT; |
| reg |= 0x40; |
| pmic_reg_write(dev, PFUZE100_SWBSTCON1, reg); |
| |
| return 0; |
| } |
| #endif |
| |
| #ifdef CONFIG_LDO_BYPASS_CHECK |
| #ifdef CONFIG_POWER |
| void ldo_mode_set(int ldo_bypass) |
| { |
| unsigned int value; |
| int is_400M; |
| u32 vddarm; |
| struct pmic *p = pmic_get("PFUZE100"); |
| |
| if (!p) { |
| printf("No PMIC found!\n"); |
| return; |
| } |
| |
| /* switch to ldo_bypass mode */ |
| if (ldo_bypass) { |
| prep_anatop_bypass(); |
| /* decrease VDDARM to 1.275V */ |
| pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); |
| value &= ~0x3f; |
| value |= PFUZE100_SW1ABC_SETP(12750); |
| pmic_reg_write(p, PFUZE100_SW1ABVOL, value); |
| |
| /* decrease VDDSOC to 1.3V */ |
| pmic_reg_read(p, PFUZE100_SW1CVOL, &value); |
| value &= ~0x3f; |
| value |= PFUZE100_SW1ABC_SETP(13000); |
| pmic_reg_write(p, PFUZE100_SW1CVOL, value); |
| |
| is_400M = set_anatop_bypass(1); |
| if (is_400M) |
| vddarm = PFUZE100_SW1ABC_SETP(10750); |
| else |
| vddarm = PFUZE100_SW1ABC_SETP(11750); |
| |
| pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); |
| value &= ~0x3f; |
| value |= vddarm; |
| pmic_reg_write(p, PFUZE100_SW1ABVOL, value); |
| |
| pmic_reg_read(p, PFUZE100_SW1CVOL, &value); |
| value &= ~0x3f; |
| value |= PFUZE100_SW1ABC_SETP(11750); |
| pmic_reg_write(p, PFUZE100_SW1CVOL, value); |
| |
| finish_anatop_bypass(); |
| printf("switch to ldo_bypass mode!\n"); |
| } |
| } |
| #elif defined(CONFIG_DM_PMIC_PFUZE100) |
| void ldo_mode_set(int ldo_bypass) |
| { |
| struct udevice *dev; |
| int ret; |
| int is_400M; |
| u32 vddarm; |
| |
| ret = pmic_get("pfuze100", &dev); |
| |
| if (ret == -ENODEV) { |
| printf("No PMIC found!\n"); |
| return; |
| } |
| |
| /* switch to ldo_bypass mode */ |
| if (ldo_bypass) { |
| prep_anatop_bypass(); |
| /* decrease VDDARM to 1.275V */ |
| pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, |
| PFUZE100_SW1ABC_SETP(12750)); |
| |
| /* decrease VDDSOC to 1.3V */ |
| pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, |
| PFUZE100_SW1ABC_SETP(13000)); |
| |
| is_400M = set_anatop_bypass(1); |
| if (is_400M) |
| vddarm = PFUZE100_SW1ABC_SETP(10750); |
| else |
| vddarm = PFUZE100_SW1ABC_SETP(11750); |
| |
| pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); |
| |
| /* decrease VDDSOC to 1.175V */ |
| pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, |
| PFUZE100_SW1ABC_SETP(11750)); |
| |
| finish_anatop_bypass(); |
| printf("switch to ldo_bypass mode!\n"); |
| } |
| } |
| #endif |
| #endif |
| |
| #ifdef CONFIG_USB_EHCI_MX6 |
| #ifndef CONFIG_DM_USB |
| |
| #define USB_OTHERREGS_OFFSET 0x800 |
| #define UCTRL_PWR_POL (1 << 9) |
| |
| static iomux_v3_cfg_t const usb_otg_pads[] = { |
| /* OGT1 */ |
| MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), |
| /* OTG2 */ |
| MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) |
| }; |
| |
| static void setup_usb(void) |
| { |
| imx_iomux_v3_setup_multiple_pads(usb_otg_pads, |
| ARRAY_SIZE(usb_otg_pads)); |
| } |
| |
| int board_usb_phy_mode(int port) |
| { |
| if (port == 1) |
| return USB_INIT_HOST; |
| else |
| return usb_phy_mode(port); |
| } |
| |
| int board_ehci_hcd_init(int port) |
| { |
| u32 *usbnc_usb_ctrl; |
| |
| if (port > 1) |
| return -EINVAL; |
| |
| usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + |
| port * 4); |
| |
| /* Set Power polarity */ |
| setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); |
| |
| return 0; |
| } |
| #endif |
| #endif |
| |
| int board_phy_config(struct phy_device *phydev) |
| { |
| mx6_rgmii_rework(phydev); |
| |
| if (phydev->drv->config) |
| phydev->drv->config(phydev); |
| |
| return 0; |
| } |
| int board_early_init_f(void) |
| { |
| #ifdef CONFIG_IMX_RDC |
| imx_rdc_setup_peripherals(shared_resources, |
| ARRAY_SIZE(shared_resources)); |
| #endif |
| |
| #ifdef CONFIG_SYS_AUXCORE_FASTUP |
| arch_auxiliary_core_up(0, CONFIG_SYS_AUXCORE_BOOTDATA); |
| #endif |
| |
| setup_iomux_uart(); |
| |
| return 0; |
| } |
| |
| static struct fsl_esdhc_cfg usdhc_cfg[3] = { |
| {USDHC2_BASE_ADDR, 0, 4}, |
| {USDHC3_BASE_ADDR}, |
| #ifdef CONFIG_MX6SXSCM_EMMC |
| {USDHC4_BASE_ADDR, 0, 8}, |
| #else |
| {USDHC4_BASE_ADDR}, |
| #endif |
| }; |
| |
| #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10) |
| #define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11) |
| #define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21) |
| |
| int board_mmc_get_env_dev(int devno) |
| { |
| return devno - 1; |
| } |
| |
| int mmc_map_to_kernel_blk(int dev_no) |
| { |
| return dev_no + 1; |
| } |
| |
| int board_mmc_getcd(struct mmc *mmc) |
| { |
| struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| int ret = 0; |
| |
| switch (cfg->esdhc_base) { |
| case USDHC2_BASE_ADDR: |
| ret = 1; /* Assume uSDHC2 is always present */ |
| break; |
| case USDHC3_BASE_ADDR: |
| ret = 1; /* Assume uSDHC3 is always present */ |
| break; |
| case USDHC4_BASE_ADDR: |
| #ifdef CONFIG_MX6SXSCM_EMMC |
| ret = 1; |
| #else |
| ret = !gpio_get_value(USDHC4_CD_GPIO); |
| #endif |
| break; |
| } |
| |
| return ret; |
| } |
| |
| int board_mmc_init(bd_t *bis) |
| { |
| int i, ret; |
| |
| /* |
| * According to the board_mmc_init() the following map is done: |
| * (U-Boot device node) (Physical Port) |
| * mmc0 USDHC2 |
| * mmc1 USDHC3 |
| * mmc2 USDHC4 |
| */ |
| for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
| switch (i) { |
| case 0: |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
| usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| break; |
| case 1: |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
| gpio_request(USDHC3_CD_GPIO, "usdhc3 cd"); |
| gpio_request(USDHC3_PWR_GPIO, "usdhc3 pwr"); |
| gpio_direction_input(USDHC3_CD_GPIO); |
| gpio_direction_output(USDHC3_PWR_GPIO, 1); |
| usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
| break; |
| case 2: |
| #ifdef CONFIG_MX6SXSCM_EMMC |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc4_emmc_pads, ARRAY_SIZE(usdhc4_emmc_pads)); |
| #else |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); |
| gpio_request(USDHC4_CD_GPIO, "usdhc4 cd"); |
| gpio_direction_input(USDHC4_CD_GPIO); |
| #endif |
| usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
| break; |
| default: |
| printf("Warning: you configured more "); |
| printf("USDHC controllers "); |
| printf("(%d) than supported by the board\n", i + 1); |
| return -EINVAL; |
| } |
| |
| ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
| if (ret) { |
| printf("Warning: failed to initialize mmc dev %d\n", i); |
| return ret; |
| } |
| } |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_FSL_QSPI |
| |
| #ifndef CONFIG_DM_SPI |
| #define QSPI_PAD_CTRL1 \ |
| (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \ |
| PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm) |
| |
| static iomux_v3_cfg_t const quadspi_pads[] = { |
| MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_NAND_DATA05__QSPI2_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| }; |
| #endif |
| |
| int board_qspi_init(void) |
| { |
| #ifndef CONFIG_DM_SPI |
| /* Set the iomux */ |
| imx_iomux_v3_setup_multiple_pads(quadspi_pads, |
| ARRAY_SIZE(quadspi_pads)); |
| #endif |
| /* Set the clock */ |
| enable_qspi_clk(1); |
| |
| return 0; |
| } |
| #endif |
| |
| #ifdef CONFIG_CMD_BMODE |
| static const struct boot_mode board_boot_modes[] = { |
| /* 4 bit bus width */ |
| {"sd3", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)}, |
| {"sd4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, |
| {"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)}, |
| {NULL, 0}, |
| }; |
| #endif |
| |
| #ifdef CONFIG_VIDEO_MXS |
| static iomux_v3_cfg_t const lvds_ctrl_pads[] = { |
| /* CABC enable */ |
| MX6_PAD_QSPI1A_DATA2__GPIO4_IO_18 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| |
| /* Use GPIO for Brightness adjustment, duty cycle = period */ |
| MX6_PAD_NAND_DATA07__GPIO4_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const lcd_pads[] = { |
| MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| |
| /* Use GPIO for Brightness adjustment, duty cycle = period */ |
| MX6_PAD_NAND_DATA06__GPIO4_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| void do_enable_lvds(struct display_info_t const *dev) |
| { |
| int ret; |
| |
| ret = enable_lcdif_clock(dev->bus, 1); |
| if (ret) { |
| printf("Enable LCDIF clock failed, %d\n", ret); |
| return; |
| } |
| ret = enable_lvds_bridge(dev->bus); |
| if (ret) { |
| printf("Enable LVDS bridge failed, %d\n", ret); |
| return; |
| } |
| |
| imx_iomux_v3_setup_multiple_pads(lvds_ctrl_pads, |
| ARRAY_SIZE(lvds_ctrl_pads)); |
| |
| /* Enable CABC */ |
| gpio_request(IMX_GPIO_NR(4, 18), "CABC enable"); |
| gpio_direction_output(IMX_GPIO_NR(4, 18) , 1); |
| |
| /* Set Brightness to high */ |
| gpio_request(IMX_GPIO_NR(4, 11), "lvds backlight"); |
| gpio_direction_output(IMX_GPIO_NR(4, 11) , 1); |
| } |
| |
| void do_enable_parallel_lcd(struct display_info_t const *dev) |
| |
| { |
| int ret; |
| |
| ret = enable_lcdif_clock(dev->bus, 1); |
| if (ret) { |
| printf("Enable LCDIF clock failed, %d\n", ret); |
| return; |
| } |
| |
| imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); |
| |
| /* Reset the LCD */ |
| gpio_request(IMX_GPIO_NR(3, 27), "lcd reset"); |
| gpio_direction_output(IMX_GPIO_NR(3, 27) , 0); |
| udelay(500); |
| gpio_direction_output(IMX_GPIO_NR(3, 27) , 1); |
| |
| /* Set Brightness to high */ |
| gpio_request(IMX_GPIO_NR(4, 10), "lcd backlight"); |
| gpio_direction_output(IMX_GPIO_NR(4, 10) , 1); |
| } |
| |
| struct display_info_t const displays[] = {{ |
| .bus = LCDIF2_BASE_ADDR, |
| .addr = 0, |
| .pixfmt = 18, |
| .detect = NULL, |
| .enable = do_enable_lvds, |
| .mode = { |
| .name = "Hannstar-XGA", |
| .xres = 1024, |
| .yres = 768, |
| .pixclock = 15385, |
| .left_margin = 220, |
| .right_margin = 40, |
| .upper_margin = 21, |
| .lower_margin = 7, |
| .hsync_len = 60, |
| .vsync_len = 10, |
| .sync = 0, |
| .vmode = FB_VMODE_NONINTERLACED |
| } }, { |
| .bus = MX6SX_LCDIF1_BASE_ADDR, |
| .addr = 0, |
| .pixfmt = 24, |
| .detect = NULL, |
| .enable = do_enable_parallel_lcd, |
| .mode = { |
| .name = "MCIMX28LCD", |
| .xres = 800, |
| .yres = 480, |
| .pixclock = 29850, |
| .left_margin = 89, |
| .right_margin = 164, |
| .upper_margin = 23, |
| .lower_margin = 10, |
| .hsync_len = 10, |
| .vsync_len = 10, |
| .sync = 0, |
| .vmode = FB_VMODE_NONINTERLACED |
| } } }; |
| size_t display_count = ARRAY_SIZE(displays); |
| #endif |
| int board_init(void) |
| { |
| /* Address of boot parameters */ |
| gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| |
| /* |
| * Because kernel set WDOG_B mux before pad with the commone pinctrl |
| * framwork now and wdog reset will be triggered once set WDOG_B mux |
| * with default pad setting, we set pad setting here to workaround this. |
| * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set |
| * as GPIO mux firstly here to workaround it. |
| */ |
| imx_iomux_v3_setup_pad(wdog_b_pad); |
| |
| /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ |
| imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, |
| ARRAY_SIZE(peri_3v3_pads)); |
| |
| /* Active high for ncp692 */ |
| gpio_request(IMX_GPIO_NR(4, 16), "peri_3v3"); |
| gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); |
| |
| #ifdef CONFIG_SYS_I2C |
| setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); |
| setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); |
| setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4); |
| #endif |
| |
| #ifdef CONFIG_USB_EHCI_MX6 |
| #ifndef CONFIG_DM_USB |
| setup_usb(); |
| #endif |
| #endif |
| |
| #ifdef CONFIG_FSL_QSPI |
| board_qspi_init(); |
| #endif |
| |
| /* Also used for OF_CONTROL enabled */ |
| #ifdef CONFIG_FEC_MXC |
| setup_fec(CONFIG_FEC_ENET_DEV); |
| #endif |
| |
| return 0; |
| } |
| |
| int board_late_init(void) |
| { |
| #ifdef CONFIG_CMD_BMODE |
| add_board_boot_modes(board_boot_modes); |
| #endif |
| |
| #ifdef CONFIG_ENV_IS_IN_MMC |
| board_late_mmc_env_init(); |
| #endif |
| |
| return 0; |
| } |
| |
| int checkboard(void) |
| { |
| puts("Board: MX6SXSCM EVB\n"); |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_FSL_FASTBOOT |
| |
| void board_fastboot_setup(void) |
| { |
| switch (get_boot_device()) { |
| #if defined(CONFIG_FASTBOOT_STORAGE_MMC) |
| case SD2_BOOT: |
| case MMC2_BOOT: |
| if (!getenv("fastboot_dev")) |
| setenv("fastboot_dev", "mmc0"); |
| if (!getenv("bootcmd")) |
| setenv("bootcmd", "boota mmc0"); |
| break; |
| case SD3_BOOT: |
| case MMC3_BOOT: |
| if (!getenv("fastboot_dev")) |
| setenv("fastboot_dev", "mmc1"); |
| if (!getenv("bootcmd")) |
| setenv("bootcmd", "boota mmc1"); |
| break; |
| case SD4_BOOT: |
| case MMC4_BOOT: |
| if (!getenv("fastboot_dev")) |
| setenv("fastboot_dev", "mmc2"); |
| if (!getenv("bootcmd")) |
| setenv("bootcmd", "boota mmc2"); |
| break; |
| #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ |
| default: |
| printf("unsupported boot devices\n"); |
| break; |
| } |
| } |
| |
| #ifdef CONFIG_ANDROID_RECOVERY |
| |
| #define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 19) |
| iomux_v3_cfg_t const recovery_key_pads[] = { |
| (MX6_PAD_CSI_DATA05__GPIO1_IO_19 | MUX_PAD_CTRL(BUTTON_PAD_CTRL)), |
| }; |
| |
| int check_recovery_cmd_file(void) |
| { |
| int button_pressed = 0; |
| int recovery_mode = 0; |
| |
| recovery_mode = recovery_check_and_clean_flag(); |
| |
| /* Check Recovery Combo Button press or not. */ |
| imx_iomux_v3_setup_multiple_pads(recovery_key_pads, |
| ARRAY_SIZE(recovery_key_pads)); |
| |
| gpio_request(GPIO_VOL_DN_KEY, "volume_dn_key"); |
| gpio_direction_input(GPIO_VOL_DN_KEY); |
| |
| /* VOL_DN key is low assert */ |
| if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { |
| button_pressed = 1; |
| printf("Recovery key pressed\n"); |
| } |
| |
| return recovery_mode || button_pressed; |
| } |
| |
| void board_recovery_setup(void) |
| { |
| int bootdev = get_boot_device(); |
| |
| switch (bootdev) { |
| #if defined(CONFIG_FASTBOOT_STORAGE_MMC) |
| case SD2_BOOT: |
| case MMC2_BOOT: |
| if (!getenv("bootcmd_android_recovery")) |
| setenv("bootcmd_android_recovery", |
| "boota mmc0 recovery"); |
| break; |
| case SD3_BOOT: |
| case MMC3_BOOT: |
| if (!getenv("bootcmd_android_recovery")) |
| setenv("bootcmd_android_recovery", |
| "boota mmc1 recovery"); |
| break; |
| case SD4_BOOT: |
| case MMC4_BOOT: |
| if (!getenv("bootcmd_android_recovery")) |
| setenv("bootcmd_android_recovery", |
| "boota mmc2 recovery"); |
| break; |
| #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ |
| default: |
| printf("Unsupported bootup device for recovery: dev: %d\n", |
| bootdev); |
| return; |
| } |
| |
| printf("setup env for recovery..\n"); |
| setenv("bootcmd", "run bootcmd_android_recovery"); |
| } |
| #endif /*CONFIG_ANDROID_RECOVERY*/ |
| |
| #endif /*CONFIG_FSL_FASTBOOT*/ |