| /* |
| * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. |
| * Copyright 2017 nxp |
| * |
| * Author: Ye Li <ye.li@nxp.com> |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| #include <asm/arch/clock.h> |
| #include <asm/arch/crm_regs.h> |
| #include <asm/arch/iomux.h> |
| #include <asm/arch/imx-regs.h> |
| #include <asm/arch/mx6-pins.h> |
| #include <asm/arch/sys_proto.h> |
| #include <asm/gpio.h> |
| #include <asm/imx-common/iomux-v3.h> |
| #include <asm/imx-common/boot_mode.h> |
| #include <asm/io.h> |
| #include <linux/sizes.h> |
| #include <common.h> |
| #include <fsl_esdhc.h> |
| #include <miiphy.h> |
| #include <netdev.h> |
| #include <power/pmic.h> |
| #include <power/pfuze100_pmic.h> |
| #include "../common/pfuze.h" |
| #include <usb.h> |
| #include <usb/ehci-ci.h> |
| #include <pca953x.h> |
| #include <asm/imx-common/video.h> |
| #ifdef CONFIG_FSL_FASTBOOT |
| #include <fsl_fastboot.h> |
| #ifdef CONFIG_ANDROID_RECOVERY |
| #include <recovery.h> |
| #include "../common/recovery_keypad.h" |
| #endif |
| #endif /*CONFIG_FSL_FASTBOOT*/ |
| |
| DECLARE_GLOBAL_DATA_PTR; |
| |
| #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
| PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ |
| PAD_CTL_SPEED_HIGH | \ |
| PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) |
| |
| #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ |
| PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) |
| |
| #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) |
| |
| #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) |
| #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ |
| PAD_CTL_SRE_FAST) |
| #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) |
| |
| #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ |
| PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) |
| |
| #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ |
| PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| int dram_init(void) |
| { |
| gd->ram_size = imx_ddr_size(); |
| |
| return 0; |
| } |
| |
| static iomux_v3_cfg_t const uart1_pads[] = { |
| MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const fec1_pads[] = { |
| MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const fec2_pads[] = { |
| MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| }; |
| |
| static void setup_iomux_uart(void) |
| { |
| imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
| } |
| |
| static int setup_fec(int fec_id) |
| { |
| struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| |
| if (0 == fec_id) |
| /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ |
| clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); |
| else |
| /* Use 125M anatop REF_CLK1 for ENET2, clear gpr1[14], gpr1[18]*/ |
| clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0); |
| |
| return enable_fec_anatop_clock(fec_id, ENET_125MHZ); |
| } |
| |
| int board_eth_init(bd_t *bis) |
| { |
| int ret; |
| |
| if (0 == CONFIG_FEC_ENET_DEV) |
| imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); |
| else |
| imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); |
| |
| ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, |
| CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); |
| if (ret) |
| printf("FEC%d MXC: %s:failed\n", 1, __func__); |
| |
| return ret; |
| } |
| |
| int board_phy_config(struct phy_device *phydev) |
| { |
| /* |
| * Enable 1.8V(SEL_1P5_1P8_POS_REG) on |
| * Phy control debug reg 0 |
| */ |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); |
| |
| /* rgmii tx clock delay enable */ |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); |
| |
| if (phydev->drv->config) |
| phydev->drv->config(phydev); |
| |
| return 0; |
| } |
| |
| int power_init_board(void) |
| { |
| struct udevice *dev; |
| int ret; |
| |
| dev = pfuze_common_init(); |
| if (!dev) |
| return -ENODEV; |
| |
| ret = pfuze_mode_init(dev, APS_PFM); |
| if (ret < 0) |
| return ret; |
| |
| /* set SW1C staby volatage 1.10V */ |
| pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20); |
| |
| /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ |
| pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); |
| |
| /* Enable power of VGEN5 3V3, needed for SD3 */ |
| pmic_clrsetbits(dev, PFUZE100_SW1CCONF, LDO_VOL_MASK, (LDOB_3_30V | (1 << LDO_EN))); |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_LDO_BYPASS_CHECK |
| void ldo_mode_set(int ldo_bypass) |
| { |
| struct udevice *dev; |
| int ret; |
| |
| ret = pmic_get("pfuze100", &dev); |
| if (ret == -ENODEV) { |
| printf("No PMIC found!\n"); |
| return; |
| } |
| |
| /* switch to ldo_bypass mode */ |
| if (ldo_bypass) { |
| /* decrease VDDARM to 1.15V */ |
| pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, SW1x_1_150V); |
| |
| /* decrease VDDSOC to 1.15V */ |
| pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, SW1x_1_150V); |
| |
| set_anatop_bypass(1); |
| |
| printf("switch to ldo_bypass mode!\n"); |
| } |
| } |
| #endif |
| |
| #ifdef CONFIG_USB_EHCI_MX6 |
| #ifndef CONFIG_DM_USB |
| |
| #define USB_OTHERREGS_OFFSET 0x800 |
| #define UCTRL_PWR_POL (1 << 9) |
| |
| static iomux_v3_cfg_t const usb_otg_pads[] = { |
| /* OGT1 */ |
| MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), |
| /* OTG2 */ |
| MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) |
| }; |
| |
| static void setup_usb(void) |
| { |
| imx_iomux_v3_setup_multiple_pads(usb_otg_pads, |
| ARRAY_SIZE(usb_otg_pads)); |
| } |
| |
| int board_usb_phy_mode(int port) |
| { |
| if (port == 1) |
| return USB_INIT_HOST; |
| else |
| return usb_phy_mode(port); |
| } |
| |
| int board_ehci_hcd_init(int port) |
| { |
| u32 *usbnc_usb_ctrl; |
| |
| if (port > 1) |
| return -EINVAL; |
| |
| usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + |
| port * 4); |
| |
| /* Set Power polarity */ |
| setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); |
| |
| return 0; |
| } |
| #endif |
| #endif |
| |
| int board_early_init_f(void) |
| { |
| setup_iomux_uart(); |
| |
| return 0; |
| } |
| |
| int board_mmc_get_env_dev(int devno) |
| { |
| /* |
| * need subtract 2 to map to the mmc device id |
| * see the comments in board_mmc_init function |
| */ |
| return devno - 2; |
| } |
| |
| int mmc_map_to_kernel_blk(int devno) |
| { |
| return devno + 2; |
| } |
| |
| #ifdef CONFIG_VIDEO_MXS |
| static iomux_v3_cfg_t const lvds_ctrl_pads[] = { |
| /* Use GPIO for Brightness adjustment, duty cycle = period */ |
| MX6_PAD_SD1_DATA1__GPIO6_IO_3 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const lcd_pads[] = { |
| MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| void do_enable_lvds(struct display_info_t const *dev) |
| { |
| struct gpio_desc desc; |
| int ret; |
| |
| enable_lcdif_clock(dev->bus, 1); |
| enable_lvds_bridge(dev->bus); |
| |
| imx_iomux_v3_setup_multiple_pads(lvds_ctrl_pads, |
| ARRAY_SIZE(lvds_ctrl_pads)); |
| |
| /* LVDS Enable pin */ |
| ret = dm_gpio_lookup_name("gpio@30_7", &desc); |
| if (ret) |
| return; |
| |
| ret = dm_gpio_request(&desc, "lvds_en"); |
| if (ret) |
| return; |
| |
| dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); |
| dm_gpio_set_value(&desc, 1); |
| |
| /* Set Brightness to high */ |
| gpio_request(IMX_GPIO_NR(6, 3), "lcd backlight"); |
| gpio_direction_output(IMX_GPIO_NR(6, 3) , 1); |
| } |
| |
| void do_enable_parallel_lcd(struct display_info_t const *dev) |
| { |
| enable_lcdif_clock(dev->bus, 1); |
| |
| imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); |
| |
| /* Power up the LCD */ |
| gpio_request(IMX_GPIO_NR(3, 27), "lcd reset"); |
| gpio_direction_output(IMX_GPIO_NR(3, 27) , 1); |
| } |
| |
| struct display_info_t const displays[] = {{ |
| .bus = LCDIF2_BASE_ADDR, |
| .addr = 0, |
| .pixfmt = 18, |
| .detect = NULL, |
| .enable = do_enable_lvds, |
| .mode = { |
| .name = "Hannstar-XGA", |
| .xres = 1024, |
| .yres = 768, |
| .pixclock = 15385, |
| .left_margin = 220, |
| .right_margin = 40, |
| .upper_margin = 21, |
| .lower_margin = 7, |
| .hsync_len = 60, |
| .vsync_len = 10, |
| .sync = 0, |
| .vmode = FB_VMODE_NONINTERLACED |
| } }, { |
| .bus = MX6SX_LCDIF1_BASE_ADDR, |
| .addr = 0, |
| .pixfmt = 18, |
| .detect = NULL, |
| .enable = do_enable_parallel_lcd, |
| .mode = { |
| .name = "Boundary-LCD", |
| .xres = 800, |
| .yres = 480, |
| .pixclock = 29850, |
| .left_margin = 89, |
| .right_margin = 164, |
| .upper_margin = 23, |
| .lower_margin = 10, |
| .hsync_len = 10, |
| .vsync_len = 10, |
| .sync = 0, |
| .vmode = FB_VMODE_NONINTERLACED |
| } } }; |
| size_t display_count = ARRAY_SIZE(displays); |
| #endif |
| |
| #ifdef CONFIG_FSL_QSPI |
| |
| #ifndef CONFIG_DM_SPI |
| #define QSPI_PAD_CTRL1 \ |
| (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \ |
| PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm) |
| |
| static iomux_v3_cfg_t const quadspi_pads[] = { |
| MX6_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_QSPI1A_SCLK__QSPI1_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_QSPI1B_SCLK__QSPI1_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| MX6_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| }; |
| #endif |
| |
| int board_qspi_init(void) |
| { |
| #ifndef CONFIG_DM_SPI |
| /* Set the iomux */ |
| imx_iomux_v3_setup_multiple_pads(quadspi_pads, |
| ARRAY_SIZE(quadspi_pads)); |
| #endif |
| /* Set the clock */ |
| enable_qspi_clk(0); |
| |
| return 0; |
| } |
| #endif |
| |
| #ifdef CONFIG_NAND_MXS |
| iomux_v3_cfg_t gpmi_pads[] = { |
| MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0), |
| MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| }; |
| |
| static void setup_gpmi_nand(void) |
| { |
| struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| |
| /* config gpmi nand iomux */ |
| imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); |
| |
| setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) | |
| MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) | |
| MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3))); |
| |
| /* enable apbh clock gating */ |
| setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); |
| } |
| #endif |
| |
| int board_init(void) |
| { |
| struct gpio_desc desc; |
| int ret; |
| |
| /* Address of boot parameters */ |
| gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| |
| ret = dm_gpio_lookup_name("gpio@30_4", &desc); |
| if (ret) |
| return ret; |
| |
| ret = dm_gpio_request(&desc, "cpu_per_rst_b"); |
| if (ret) |
| return ret; |
| /* Reset CPU_PER_RST_B signal for enet phy and PCIE */ |
| dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); |
| udelay(500); |
| dm_gpio_set_value(&desc, 1); |
| |
| ret = dm_gpio_lookup_name("gpio@32_2", &desc); |
| if (ret) |
| return ret; |
| |
| ret = dm_gpio_request(&desc, "steer_enet"); |
| if (ret) |
| return ret; |
| |
| dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); |
| udelay(500); |
| /* Set steering signal to L for selecting B0 */ |
| dm_gpio_set_value(&desc, 0); |
| |
| #ifdef CONFIG_USB_EHCI_MX6 |
| #ifndef CONFIG_DM_USB |
| setup_usb(); |
| #endif |
| #endif |
| |
| #ifdef CONFIG_FSL_QSPI |
| board_qspi_init(); |
| #endif |
| |
| #ifdef CONFIG_NAND_MXS |
| setup_gpmi_nand(); |
| #endif |
| |
| /* Also used for OF_CONTROL enabled */ |
| #ifdef CONFIG_FEC_MXC |
| setup_fec(CONFIG_FEC_ENET_DEV); |
| #endif |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_CMD_BMODE |
| static const struct boot_mode board_boot_modes[] = { |
| {"sda", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)}, |
| {"sdb", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, |
| {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, |
| {"nand", MAKE_CFGVAL(0x82, 0x00, 0x00, 0x00)}, |
| {NULL, 0}, |
| }; |
| #endif |
| |
| int board_late_init(void) |
| { |
| #ifdef CONFIG_CMD_BMODE |
| add_board_boot_modes(board_boot_modes); |
| #endif |
| |
| setenv("tee", "no"); |
| #ifdef CONFIG_IMX_OPTEE |
| setenv("tee", "yes"); |
| #endif |
| |
| #ifdef CONFIG_ENV_IS_IN_MMC |
| board_late_mmc_env_init(); |
| #endif |
| |
| /* set WDOG_B to reset whole system */ |
| set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); |
| |
| return 0; |
| } |
| |
| int checkboard(void) |
| { |
| puts("Board: MX6SX SABRE AUTO\n"); |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_FSL_FASTBOOT |
| #ifdef CONFIG_ANDROID_RECOVERY |
| int is_recovery_key_pressing(void) |
| { |
| return is_recovery_keypad_pressing(); |
| } |
| |
| #endif /*CONFIG_ANDROID_RECOVERY*/ |
| |
| #endif /*CONFIG_FSL_FASTBOOT*/ |
| |