include/configs/imx8mm_evk.h - uboot-imx - Git at Google

 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2018 NXP
  */

 #ifndef __IMX8MM_EVK_H
 #define __IMX8MM_EVK_H

 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>

 #include "imx_env.h"

 #ifdef CONFIG_SECURE_BOOT
 #define CONFIG_CSF_SIZE			0x2000 /* 8K region */
 #endif

 #define CONFIG_SPL_MAX_SIZE		(148 * 1024)
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
 #define CONFIG_SYS_UBOOT_BASE		(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)

 #ifdef CONFIG_SPL_BUILD
 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
 #define CONFIG_SPL_WATCHDOG_SUPPORT
 #define CONFIG_SPL_POWER_SUPPORT
 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
 #define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
 #define CONFIG_SPL_STACK		0x91fff0
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_GPIO_SUPPORT
 #define CONFIG_SPL_BSS_START_ADDR      0x00910000
 #define CONFIG_SPL_BSS_MAX_SIZE        0x2000	/* 8 KB */
 #define CONFIG_SYS_SPL_MALLOC_START    0x42200000
 #define CONFIG_SYS_SPL_MALLOC_SIZE     0x80000	/* 512 KB */
 #define CONFIG_SYS_ICACHE_OFF
 #define CONFIG_SYS_DCACHE_OFF

 #define CONFIG_MALLOC_F_ADDR		0x912000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */

 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */

 #undef CONFIG_DM_MMC
 #undef CONFIG_DM_PMIC
 #undef CONFIG_DM_PMIC_PFUZE100

 #define CONFIG_POWER
 #define CONFIG_POWER_I2C
 #define CONFIG_POWER_BD71837

 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */

 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

 #if defined(CONFIG_NAND_BOOT)
 #define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_DMA_SUPPORT
 #define CONFIG_SPL_NAND_MXS
 #define CONFIG_SPL_NAND_BASE
 #define CONFIG_SPL_NAND_IDENT
 #define CONFIG_SYS_NAND_U_BOOT_OFFS 	0x4000000 /* Put the FIT out of first 64MB boot area */

 /* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */
 #define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
 	(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
 #endif

 #endif

 #define CONFIG_CMD_READ
 #define CONFIG_SERIAL_TAG
 #define CONFIG_FASTBOOT_USB_DEV 0

 #define CONFIG_REMAKE_ELF

 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_LATE_INIT

 #undef CONFIG_CMD_EXPORTENV
 #undef CONFIG_CMD_IMPORTENV
 #undef CONFIG_CMD_IMLS

 #undef CONFIG_CMD_CRC32
 #undef CONFIG_BOOTM_NETBSD

 /* ENET Config */
 /* ENET1 */
 #if defined(CONFIG_CMD_NET)
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_MII
 #define CONFIG_ETHPRIME                 "FEC"

 #define CONFIG_FEC_MXC
 #define CONFIG_FEC_XCV_TYPE             RGMII
 #define CONFIG_FEC_MXC_PHYADDR          0
 #define FEC_QUIRK_ENET_MAC

 #define CONFIG_PHY_GIGE
 #define IMX_FEC_BASE			0x30BE0000

 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 #endif

 #ifdef CONFIG_NAND_BOOT
 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs) "
 #endif

 /*
  * Another approach is add the clocks for inmates into clks_init_on
  * in clk-imx8mm.c, then clk_ingore_unused could be removed.
  */
 #define JAILHOUSE_ENV \
 	"jh_clk= \0 " \
 	"jh_mmcboot=mw 0x303d0518 0xff; setenv fdt_file fsl-imx8mm-evk-root.dtb;" \
 		"setenv jh_clk clk_ignore_unused; " \
 			   "if run loadimage; then " \
 				   "run mmcboot; " \
 			   "else run jh_netboot; fi; \0" \
 	"jh_netboot=mw 0x303d0518 0xff; setenv fdt_file fsl-imx8mm-evk-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 "


 #define CONFIG_MFG_ENV_SETTINGS \
 	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
 	"initrd_addr=0x43800000\0" \
 	"initrd_high=0xffffffffffffffff\0" \
 	"emmc_dev=2\0"\
 	"sd_dev=1\0" \

 /* Initial environment variables */
 #if defined(CONFIG_NAND_BOOT)
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	CONFIG_MFG_ENV_SETTINGS \
 	"fdt_addr=0x43000000\0"			\
 	"fdt_high=0xffffffffffffffff\0" \
 	"mtdparts=" MFG_NAND_PARTITION "\0" \
 	"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
 	"bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=5 "  \
 		"root=ubi0:nandrootfs rootfstype=ubifs "		     \
 		MFG_NAND_PARTITION \
 		"\0" \
 	"bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\
 		"nand read ${fdt_addr} 0x7000000 0x100000;"\
 		"booti ${loadaddr} - ${fdt_addr}"

 #else
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	CONFIG_MFG_ENV_SETTINGS \
 	JAILHOUSE_ENV \
 	"script=boot.scr\0" \
 	"image=Image\0" \
 	"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
 	"fdt_addr=0x43000000\0"			\
 	"fdt_high=0xffffffffffffffff\0"		\
 	"boot_fdt=try\0" \
 	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"initrd_addr=0x43800000\0"		\
 	"initrd_high=0xffffffffffffffff\0" \
 	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
 	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
 	"mmcautodetect=yes\0" \
 	"mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
 	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if run loadfdt; then " \
 				"booti ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"echo WARN: Cannot load the DT; " \
 			"fi; " \
 		"else " \
 			"echo wait for boot; " \
 		"fi;\0" \
 	"netargs=setenv bootargs ${jh_clk} console=${console} " \
 		"root=/dev/nfs " \
 		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
 	"netboot=echo Booting from net ...; " \
 		"run netargs;  " \
 		"if test ${ip_dyn} = yes; then " \
 			"setenv get_cmd dhcp; " \
 		"else " \
 			"setenv get_cmd tftp; " \
 		"fi; " \
 		"${get_cmd} ${loadaddr} ${image}; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
 				"booti ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"echo WARN: Cannot load the DT; " \
 			"fi; " \
 		"else " \
 			"booti; " \
 		"fi;\0"

 #define CONFIG_BOOTCOMMAND \
 	   "mmc dev ${mmcdev}; if mmc rescan; then " \
 		   "if run loadbootscript; then " \
 			   "run bootscript; " \
 		   "else " \
 			   "if run loadimage; then " \
 				   "run mmcboot; " \
 			   "else run netboot; " \
 			   "fi; " \
 		   "fi; " \
 	   "else booti ${loadaddr} - ${fdt_addr}; fi"
 #endif

 /* Link Definitions */
 #define CONFIG_LOADADDR			0x40480000

 #define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR

 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
 #define CONFIG_SYS_INIT_RAM_SIZE        0x80000
 #define CONFIG_SYS_INIT_SP_OFFSET \
         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR \
         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

 #define CONFIG_ENV_OVERWRITE
 #if defined(CONFIG_ENV_IS_IN_MMC)
 #define CONFIG_ENV_OFFSET               (64 * SZ_64K)
 #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
 #define CONFIG_ENV_OFFSET		(4 * 1024 * 1024)
 #define CONFIG_ENV_SECT_SIZE		(64 * 1024)
 #define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
 #define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
 #define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
 #define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
 #elif defined(CONFIG_ENV_IS_IN_NAND)
 #define CONFIG_ENV_OFFSET       (60 << 20)
 #endif
 #define CONFIG_ENV_SIZE			0x1000
 #define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
 #define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */

 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024)

 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */

 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
 					(PHYS_SDRAM_SIZE >> 1))

 #define CONFIG_BAUDRATE			115200

 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR

 /* Monitor Command Prompt */
 #undef CONFIG_SYS_PROMPT
 #define CONFIG_SYS_PROMPT		"u-boot=> "
 #define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
 #define CONFIG_SYS_CBSIZE              2048
 #define CONFIG_SYS_MAXARGS             64
 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)

 #define CONFIG_IMX_BOOTAUX

 /* USDHC */
 #define CONFIG_CMD_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC

 #ifdef CONFIG_TARGET_IMX8MM_DDR4_EVK
 #define CONFIG_SYS_FSL_USDHC_NUM	1
 #else
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #endif
 #define CONFIG_SYS_FSL_ESDHC_ADDR       0

 #define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
 #define CONFIG_SYS_MMC_IMG_LOAD_PART	1

 #ifdef CONFIG_FSL_FSPI
 #define FSL_FSPI_FLASH_SIZE		SZ_32M
 #define FSL_FSPI_FLASH_NUM		1
 #define FSPI0_BASE_ADDR			0x30bb0000
 #define FSPI0_AMBA_BASE			0x0
 #define CONFIG_FSPI_QUAD_SUPPORT

 #define CONFIG_SYS_FSL_FSPI_AHB
 #endif

 #ifdef CONFIG_NAND_MXS
 #define CONFIG_CMD_NAND_TRIMFFS

 /* NAND stuff */
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x20000000
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_ONFI_DETECTION

 #ifdef CONFIG_CMD_UBI
 #define CONFIG_MTD_DEVICE
 #endif
 #endif /* CONFIG_NAND_MXS */


 #define CONFIG_MXC_GPIO

 #define CONFIG_MXC_OCOTP
 #define CONFIG_CMD_FUSE

 #ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
 #endif
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000

 /* USB configs */
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USBD_HS

 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_GADGET_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE

 #endif

 #define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_GADGET_VBUS_DRAW 2

 #define CONFIG_CI_UDC

 #define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_USB_MAX_CONTROLLER_COUNT         2

 #ifdef CONFIG_VIDEO
 #define CONFIG_VIDEO_MXS
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
 #define CONFIG_CMD_BMP
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_VIDEO_BMP_LOGO
 #define CONFIG_IMX_VIDEO_SKIP
 #define CONFIG_RM67191
 #endif

 #define CONFIG_OF_SYSTEM_SETUP

 #endif
	/* SPDX-License-Identifier: GPL-2.0+ */
	/*
	* Copyright 2018 NXP
	*/

	#ifndef __IMX8MM_EVK_H
	#define __IMX8MM_EVK_H

	#include <linux/sizes.h>
	#include <asm/arch/imx-regs.h>

	#include "imx_env.h"

	#ifdef CONFIG_SECURE_BOOT
	#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
	#endif

	#define CONFIG_SPL_MAX_SIZE (148 * 1024)
	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
	#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)

	#ifdef CONFIG_SPL_BUILD
	/#define CONFIG_ENABLE_DDR_TRAINING_DEBUG/
	#define CONFIG_SPL_WATCHDOG_SUPPORT
	#define CONFIG_SPL_POWER_SUPPORT
	#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
	#define CONFIG_SPL_I2C_SUPPORT
	#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
	#define CONFIG_SPL_STACK 0x91fff0
	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	#define CONFIG_SPL_GPIO_SUPPORT
	#define CONFIG_SPL_BSS_START_ADDR 0x00910000
	#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
	#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
	#define CONFIG_SYS_ICACHE_OFF
	#define CONFIG_SYS_DCACHE_OFF

	#define CONFIG_MALLOC_F_ADDR 0x912000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */

	#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */

	#undef CONFIG_DM_MMC
	#undef CONFIG_DM_PMIC
	#undef CONFIG_DM_PMIC_PFUZE100

	#define CONFIG_POWER
	#define CONFIG_POWER_I2C
	#define CONFIG_POWER_BD71837

	#define CONFIG_SYS_I2C
	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */

	#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

	#if defined(CONFIG_NAND_BOOT)
	#define CONFIG_SPL_NAND_SUPPORT
	#define CONFIG_SPL_DMA_SUPPORT
	#define CONFIG_SPL_NAND_MXS
	#define CONFIG_SPL_NAND_BASE
	#define CONFIG_SPL_NAND_IDENT
	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */

	/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */
	#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
	(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
	#endif

	#endif

	#define CONFIG_CMD_READ
	#define CONFIG_SERIAL_TAG
	#define CONFIG_FASTBOOT_USB_DEV 0

	#define CONFIG_REMAKE_ELF

	#define CONFIG_BOARD_EARLY_INIT_F
	#define CONFIG_BOARD_LATE_INIT

	#undef CONFIG_CMD_EXPORTENV
	#undef CONFIG_CMD_IMPORTENV
	#undef CONFIG_CMD_IMLS

	#undef CONFIG_CMD_CRC32
	#undef CONFIG_BOOTM_NETBSD

	/* ENET Config */
	/* ENET1 */
	#if defined(CONFIG_CMD_NET)
	#define CONFIG_CMD_PING
	#define CONFIG_CMD_DHCP
	#define CONFIG_CMD_MII
	#define CONFIG_MII
	#define CONFIG_ETHPRIME "FEC"

	#define CONFIG_FEC_MXC
	#define CONFIG_FEC_XCV_TYPE RGMII
	#define CONFIG_FEC_MXC_PHYADDR 0
	#define FEC_QUIRK_ENET_MAC

	#define CONFIG_PHY_GIGE
	#define IMX_FEC_BASE 0x30BE0000

	#define CONFIG_PHYLIB
	#define CONFIG_PHY_ATHEROS
	#endif

	#ifdef CONFIG_NAND_BOOT
	#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs) "
	#endif

	/*
	* Another approach is add the clocks for inmates into clks_init_on
	* in clk-imx8mm.c, then clk_ingore_unused could be removed.
	*/
	#define JAILHOUSE_ENV \
	"jh_clk= \0 " \
	"jh_mmcboot=mw 0x303d0518 0xff; setenv fdt_file fsl-imx8mm-evk-root.dtb;" \
	"setenv jh_clk clk_ignore_unused; " \
	"if run loadimage; then " \
	"run mmcboot; " \
	"else run jh_netboot; fi; \0" \
	"jh_netboot=mw 0x303d0518 0xff; setenv fdt_file fsl-imx8mm-evk-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 "


	#define CONFIG_MFG_ENV_SETTINGS \
	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
	"initrd_addr=0x43800000\0" \
	"initrd_high=0xffffffffffffffff\0" \
	"emmc_dev=2\0"\
	"sd_dev=1\0" \

	/* Initial environment variables */
	#if defined(CONFIG_NAND_BOOT)
	#define CONFIG_EXTRA_ENV_SETTINGS \
	CONFIG_MFG_ENV_SETTINGS \
	"fdt_addr=0x43000000\0" \
	"fdt_high=0xffffffffffffffff\0" \
	"mtdparts=" MFG_NAND_PARTITION "\0" \
	"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
	"bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=5 " \
	"root=ubi0:nandrootfs rootfstype=ubifs " \
	MFG_NAND_PARTITION \
	"\0" \
	"bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\
	"nand read ${fdt_addr} 0x7000000 0x100000;"\
	"booti ${loadaddr} - ${fdt_addr}"

	#else
	#define CONFIG_EXTRA_ENV_SETTINGS \
	CONFIG_MFG_ENV_SETTINGS \
	JAILHOUSE_ENV \
	"script=boot.scr\0" \
	"image=Image\0" \
	"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
	"fdt_addr=0x43000000\0" \
	"fdt_high=0xffffffffffffffff\0" \
	"boot_fdt=try\0" \
	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
	"initrd_addr=0x43800000\0" \
	"initrd_high=0xffffffffffffffff\0" \
	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
	"mmcautodetect=yes\0" \
	"mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
	"source\0" \
	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
	"mmcboot=echo Booting from mmc ...; " \
	"run mmcargs; " \
	"if test ${boot_fdt} = yes \|\| test ${boot_fdt} = try; then " \
	"if run loadfdt; then " \
	"booti ${loadaddr} - ${fdt_addr}; " \
	"else " \
	"echo WARN: Cannot load the DT; " \
	"fi; " \
	"else " \
	"echo wait for boot; " \
	"fi;\0" \
	"netargs=setenv bootargs ${jh_clk} console=${console} " \
	"root=/dev/nfs " \
	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
	"netboot=echo Booting from net ...; " \
	"run netargs; " \
	"if test ${ip_dyn} = yes; then " \
	"setenv get_cmd dhcp; " \
	"else " \
	"setenv get_cmd tftp; " \
	"fi; " \
	"${get_cmd} ${loadaddr} ${image}; " \
	"if test ${boot_fdt} = yes \|\| test ${boot_fdt} = try; then " \
	"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
	"booti ${loadaddr} - ${fdt_addr}; " \
	"else " \
	"echo WARN: Cannot load the DT; " \
	"fi; " \
	"else " \
	"booti; " \
	"fi;\0"

	#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
	"if run loadbootscript; then " \
	"run bootscript; " \
	"else " \
	"if run loadimage; then " \
	"run mmcboot; " \
	"else run netboot; " \
	"fi; " \
	"fi; " \
	"else booti ${loadaddr} - ${fdt_addr}; fi"
	#endif

	/* Link Definitions */
	#define CONFIG_LOADADDR 0x40480000

	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR

	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
	#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
	#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

	#define CONFIG_ENV_OVERWRITE
	#if defined(CONFIG_ENV_IS_IN_MMC)
	#define CONFIG_ENV_OFFSET (64 * SZ_64K)
	#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
	#define CONFIG_ENV_OFFSET (4 * 1024 * 1024)
	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
	#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
	#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
	#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	#elif defined(CONFIG_ENV_IS_IN_NAND)
	#define CONFIG_ENV_OFFSET (60 << 20)
	#endif
	#define CONFIG_ENV_SIZE 0x1000
	#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
	#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */

	/* Size of malloc() pool */
	#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (21024) + (161024)) * 1024)

	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	#define PHYS_SDRAM 0x40000000
	#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */

	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
	(PHYS_SDRAM_SIZE >> 1))

	#define CONFIG_BAUDRATE 115200

	#define CONFIG_MXC_UART
	#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR

	/* Monitor Command Prompt */
	#undef CONFIG_SYS_PROMPT
	#define CONFIG_SYS_PROMPT "u-boot=> "
	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	#define CONFIG_SYS_CBSIZE 2048
	#define CONFIG_SYS_MAXARGS 64
	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	sizeof(CONFIG_SYS_PROMPT) + 16)

	#define CONFIG_IMX_BOOTAUX

	/* USDHC */
	#define CONFIG_CMD_MMC
	#define CONFIG_FSL_ESDHC
	#define CONFIG_FSL_USDHC

	#ifdef CONFIG_TARGET_IMX8MM_DDR4_EVK
	#define CONFIG_SYS_FSL_USDHC_NUM 1
	#else
	#define CONFIG_SYS_FSL_USDHC_NUM 2
	#endif
	#define CONFIG_SYS_FSL_ESDHC_ADDR 0

	#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
	#define CONFIG_SYS_MMC_IMG_LOAD_PART 1

	#ifdef CONFIG_FSL_FSPI
	#define FSL_FSPI_FLASH_SIZE SZ_32M
	#define FSL_FSPI_FLASH_NUM 1
	#define FSPI0_BASE_ADDR 0x30bb0000
	#define FSPI0_AMBA_BASE 0x0
	#define CONFIG_FSPI_QUAD_SUPPORT

	#define CONFIG_SYS_FSL_FSPI_AHB
	#endif

	#ifdef CONFIG_NAND_MXS
	#define CONFIG_CMD_NAND_TRIMFFS

	/* NAND stuff */
	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	#define CONFIG_SYS_NAND_BASE 0x20000000
	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	#define CONFIG_SYS_NAND_ONFI_DETECTION

	#ifdef CONFIG_CMD_UBI
	#define CONFIG_MTD_DEVICE
	#endif
	#endif /* CONFIG_NAND_MXS */


	#define CONFIG_MXC_GPIO

	#define CONFIG_MXC_OCOTP
	#define CONFIG_CMD_FUSE

	#ifndef CONFIG_DM_I2C
	#define CONFIG_SYS_I2C
	#endif
	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
	#define CONFIG_SYS_I2C_SPEED 100000

	/* USB configs */
	#ifndef CONFIG_SPL_BUILD
	#define CONFIG_CMD_USB
	#define CONFIG_USB_STORAGE
	#define CONFIG_USBD_HS

	#define CONFIG_CMD_USB_MASS_STORAGE
	#define CONFIG_USB_GADGET_MASS_STORAGE
	#define CONFIG_USB_FUNCTION_MASS_STORAGE

	#endif

	#define CONFIG_USB_GADGET_DUALSPEED
	#define CONFIG_USB_GADGET_VBUS_DRAW 2

	#define CONFIG_CI_UDC

	#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI \| PORT_PTS_PTW)
	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2

	#ifdef CONFIG_VIDEO
	#define CONFIG_VIDEO_MXS
	#define CONFIG_VIDEO_LOGO
	#define CONFIG_SPLASH_SCREEN
	#define CONFIG_SPLASH_SCREEN_ALIGN
	#define CONFIG_CMD_BMP
	#define CONFIG_BMP_16BPP
	#define CONFIG_VIDEO_BMP_RLE8
	#define CONFIG_VIDEO_BMP_LOGO
	#define CONFIG_IMX_VIDEO_SKIP
	#define CONFIG_RM67191
	#endif

	#define CONFIG_OF_SYSTEM_SETUP

	#endif