| # single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz | |
| # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz | |
| # PBL preamble and RCW header for T1024QDS | |
| aa55aa55 010e0100 | |
| # Serdes protocol 0x6F | |
| 0810000e 00000000 00000000 00000000 | |
| 37800001 00000012 e8104000 21000000 | |
| 00000000 00000000 00000000 00030810 | |
| 00000000 036c5a00 00000000 00000006 |