board/freescale/mx6sxsabreauto/imximage.cfg

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
 */

#define __ASSEMBLY__
#include <config.h>

/* image version */

IMAGE_VERSION 2

/*
 * Boot Device : one of
 * spi/sd/nand/onenand, qspi/nor
 */

#ifdef CONFIG_QSPI_BOOT
BOOT_FROM	qspi
#elif defined(CONFIG_NOR_BOOT)
BOOT_FROM	nor
#else
BOOT_FROM	sd
#endif

#ifdef CONFIG_USE_IMXIMG_PLUGIN
/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
PLUGIN  board/freescale/mx6sxsabreauto/plugin.bin 0x00907000
#else

#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif

/*
 * Device Configuration Data (DCD)
 *
 * Each entry must have the format:
 * Addr-type           Address        Value
 *
 * where:
 *	Addr-type register length (1,2 or 4 bytes)
 *	Address	  absolute address of the register
 *	value	  value to be stored in the register
 */

/* Enable all clocks */
DATA 4 0x020c4068 0xffffffff
DATA 4 0x020c406c 0xffffffff
DATA 4 0x020c4070 0xffffffff
DATA 4 0x020c4074 0xffffffff
DATA 4 0x020c4078 0xffffffff
DATA 4 0x020c407c 0xffffffff
DATA 4 0x020c4080 0xffffffff
DATA 4 0x020c4084 0xffffffff

#ifdef CONFIG_IMX_OPTEE
DATA 4 0x20e4024 0x00000001
CHECK_BITS_SET 4 0x20e4024 0x1
#endif

/* IOMUX - DDR IO Type */
DATA 4 0x020e0618 0x000c0000
DATA 4 0x020e05fc 0x00000000

/* Clock */
DATA 4 0x020e032c 0x00000030

/* Address */
DATA 4 0x020e0300 0x00000030
DATA 4 0x020e02fc 0x00000030
DATA 4 0x020e05f4 0x00000030

/* Control */
DATA 4 0x020e0340 0x00000030

DATA 4 0x020e0320 0x00000000
DATA 4 0x020e0310 0x00000030
DATA 4 0x020e0314 0x00000030
DATA 4 0x020e0614 0x00000030

/* Data Strobe */
DATA 4 0x020e05f8 0x00020000
DATA 4 0x020e0330 0x00000030
DATA 4 0x020e0334 0x00000030
DATA 4 0x020e0338 0x00000030
DATA 4 0x020e033c 0x00000030

/* Data */
DATA 4 0x020e0608 0x00020000
DATA 4 0x020e060c 0x00000030
DATA 4 0x020e0610 0x00000030
DATA 4 0x020e061c 0x00000030
DATA 4 0x020e0620 0x00000030
DATA 4 0x020e02ec 0x00000030
DATA 4 0x020e02f0 0x00000030
DATA 4 0x020e02f4 0x00000030
DATA 4 0x020e02f8 0x00000030

/* Calibrations - ZQ */
DATA 4 0x021b0800 0xa1390003

/* Write leveling */
DATA 4 0x021b080c 0x002C003D
DATA 4 0x021b0810 0x00110046

/* DQS Read Gate */
DATA 4 0x021b083c 0x4160016C
DATA 4 0x021b0840 0x013C016C

/* Read/Write Delay */
DATA 4 0x021b0848 0x46424446
DATA 4 0x021b0850 0x3A3C3C3A

DATA 4 0x021b08c0 0x2492244A

/* read data bit delay */
DATA 4 0x021b081c 0x33333333
DATA 4 0x021b0820 0x33333333
DATA 4 0x021b0824 0x33333333
DATA 4 0x021b0828 0x33333333

/* Complete calibration by forced measurement */
DATA 4 0x021b08b8 0x00000800

/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
DATA 4 0x021b0004 0x0002002d
DATA 4 0x021b0008 0x00333030
DATA 4 0x021b000c 0x676b52f3
DATA 4 0x021b0010 0xb66d8b63
DATA 4 0x021b0014 0x01ff00db
DATA 4 0x021b0018 0x00011740
DATA 4 0x021b001c 0x00008000
DATA 4 0x021b002c 0x000026d2
DATA 4 0x021b0030 0x006b1023
DATA 4 0x021b0040 0x0000007f
DATA 4 0x021b0000 0x85190000

/* Initialize MT41K256M16HA-125 - MR2 */
DATA 4 0x021b001c 0x04008032
/* MR3 */
DATA 4 0x021b001c 0x00008033
/* MR1 */
DATA 4 0x021b001c 0x00068031
/* MR0 */
DATA 4 0x021b001c 0x05208030
/* DDR device ZQ calibration */
DATA 4 0x021b001c 0x04008040

/* Final DDR setup, before operation start */
DATA 4 0x021b0020 0x00000800
DATA 4 0x021b0818 0x00022227
DATA 4 0x021b0004 0x0002556d
DATA 4 0x021b0404 0x00011006
DATA 4 0x021b001c 0x00000000
#endif