| /* SPDX-License-Identifier: GPL-2.0+ */ |
| /* |
| * |
| * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> |
| * |
| * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. |
| */ |
| |
| #ifndef __BOARD_MX35_3STACK_H |
| #define __BOARD_MX35_3STACK_H |
| |
| #define DBG_BASE_ADDR WEIM_CTRL_CS5 |
| #define DBG_CSCR_U_CONFIG 0x0000D843 |
| #define DBG_CSCR_L_CONFIG 0x22252521 |
| #define DBG_CSCR_A_CONFIG 0x22220A00 |
| |
| #define CCM_CCMR_CONFIG 0x003F4208 |
| #define CCM_PDR0_CONFIG 0x00801000 |
| |
| /* MEMORY SETTING */ |
| #define ESDCTL_0x92220000 0x92220000 |
| #define ESDCTL_0xA2220000 0xA2220000 |
| #define ESDCTL_0xB2220000 0xB2220000 |
| #define ESDCTL_0x82228080 0x82228080 |
| |
| #define ESDCTL_PRECHARGE 0x00000400 |
| |
| #define ESDCTL_MDDR_CONFIG 0x007FFC3F |
| #define ESDCTL_MDDR_MR 0x00000033 |
| #define ESDCTL_MDDR_EMR 0x02000000 |
| |
| #define ESDCTL_DDR2_CONFIG 0x007FFC3F |
| #define ESDCTL_DDR2_EMR2 0x04000000 |
| #define ESDCTL_DDR2_EMR3 0x06000000 |
| #define ESDCTL_DDR2_EN_DLL 0x02000400 |
| #define ESDCTL_DDR2_RESET_DLL 0x00000333 |
| #define ESDCTL_DDR2_MR 0x00000233 |
| #define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 |
| |
| #define ESDCTL_DELAY_LINE5 0x00F49F00 |
| #endif /* __BOARD_MX35_3STACK_H */ |
