| /* |
| * Copyright (C) 2018 MediaTek Inc. |
| * Author: Ryder Lee <ryder.lee@mediatek.com> |
| * |
| * SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| */ |
| |
| #include <dt-bindings/clock/mt7629-clk.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/power/mt7629-power.h> |
| #include <dt-bindings/reset/mtk-reset.h> |
| #include "skeleton.dtsi" |
| |
| / { |
| compatible = "mediatek,mt7629"; |
| interrupt-parent = <&sysirq>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| enable-method = "mediatek,mt6589-smp"; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a7"; |
| reg = <0x0>; |
| clock-frequency = <1250000000>; |
| }; |
| |
| cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a7"; |
| reg = <0x1>; |
| clock-frequency = <1250000000>; |
| }; |
| }; |
| |
| clk20m: oscillator@0 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <20000000>; |
| clock-output-names = "clk20m"; |
| }; |
| |
| clk40m: oscillator@1 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <40000000>; |
| clock-output-names = "clkxtal"; |
| }; |
| |
| timer { |
| compatible = "arm,armv7-timer"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| clock-frequency = <20000000>; |
| arm,cpu-registers-not-fw-configured; |
| }; |
| |
| infracfg: syscon@10000000 { |
| compatible = "mediatek,mt7629-infracfg", "syscon"; |
| reg = <0x10000000 0x1000>; |
| #clock-cells = <1>; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| pericfg: syscon@10002000 { |
| compatible = "mediatek,mt7629-pericfg", "syscon"; |
| reg = <0x10002000 0x1000>; |
| #clock-cells = <1>; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| timer0: timer@10004000 { |
| compatible = "mediatek,timer"; |
| reg = <0x10004000 0x80>; |
| interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_10M_SEL>, |
| <&topckgen CLK_TOP_CLKXTAL_D4>; |
| clock-names = "mux", "src"; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| scpsys: scpsys@10006000 { |
| compatible = "mediatek,mt7629-scpsys"; |
| reg = <0x10006000 0x1000>; |
| clocks = <&topckgen CLK_TOP_HIF_SEL>; |
| clock-names = "hif_sel"; |
| assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; |
| #power-domain-cells = <1>; |
| infracfg = <&infracfg>; |
| }; |
| |
| mcucfg: syscon@10200000 { |
| compatible = "mediatek,mt7629-mcucfg", "syscon"; |
| reg = <0x10200000 0x1000>; |
| #clock-cells = <1>; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| sysirq: interrupt-controller@10200a80 { |
| compatible = "mediatek,sysirq"; |
| reg = <0x10200a80 0x20>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupt-parent = <&gic>; |
| }; |
| |
| dramc: dramc@10203000 { |
| compatible = "mediatek,mt7629-dramc"; |
| reg = <0x10203000 0x600>, /* EMI */ |
| <0x10213000 0x1000>, /* DDRPHY */ |
| <0x10214000 0xd00>; /* DRAMC_AO */ |
| clocks = <&topckgen CLK_TOP_DDRPHYCFG_SEL>, |
| <&topckgen CLK_TOP_SYSPLL1_D8>, |
| <&topckgen CLK_TOP_MEM_SEL>, |
| <&topckgen CLK_TOP_DMPLL>; |
| clock-names = "phy", "phy_mux", "mem", "mem_mux"; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| apmixedsys: clock-controller@10209000 { |
| compatible = "mediatek,mt7629-apmixedsys"; |
| reg = <0x10209000 0x1000>; |
| #clock-cells = <1>; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| topckgen: clock-controller@10210000 { |
| compatible = "mediatek,mt7629-topckgen"; |
| reg = <0x10210000 0x1000>; |
| #clock-cells = <1>; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| watchdog: watchdog@10212000 { |
| compatible = "mediatek,wdt"; |
| reg = <0x10212000 0x600>; |
| interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_FALLING>; |
| #reset-cells = <1>; |
| status = "disabled"; |
| }; |
| |
| wdt-reboot { |
| compatible = "wdt-reboot"; |
| wdt = <&watchdog>; |
| }; |
| |
| pinctrl: pinctrl@10217000 { |
| compatible = "mediatek,mt7629-pinctrl"; |
| reg = <0x10217000 0x8000>; |
| |
| gpio: gpio-controller { |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| }; |
| |
| gic: interrupt-controller@10300000 { |
| compatible = "arm,gic-400"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupt-parent = <&gic>; |
| reg = <0x10310000 0x1000>, |
| <0x10320000 0x1000>, |
| <0x10340000 0x2000>, |
| <0x10360000 0x2000>; |
| }; |
| |
| uart0: serial@11002000 { |
| compatible = "mediatek,hsuart"; |
| reg = <0x11002000 0x400>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_UART_SEL>, |
| <&pericfg CLK_PERI_UART0_PD>; |
| clock-names = "baud", "bus"; |
| status = "disabled"; |
| assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| uart1: serial@11003000 { |
| compatible = "mediatek,hsuart"; |
| reg = <0x11003000 0x400>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_UART_SEL>, |
| <&pericfg CLK_PERI_UART1_PD>; |
| clock-names = "baud", "bus"; |
| assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@11004000 { |
| compatible = "mediatek,hsuart"; |
| reg = <0x11004000 0x400>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_UART_SEL>, |
| <&pericfg CLK_PERI_UART2_PD>; |
| clock-names = "baud", "bus"; |
| assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; |
| status = "disabled"; |
| }; |
| |
| qspi: qspi@11014000 { |
| compatible = "mediatek,mt7629-qspi"; |
| reg = <0x11014000 0xe0>, <0x30000000 0x10000000>; |
| reg-names = "reg_base", "mem_base"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| ethsys: syscon@1b000000 { |
| compatible = "mediatek,mt7629-ethsys", "syscon"; |
| reg = <0x1b000000 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| eth: ethernet@1b100000 { |
| compatible = "mediatek,mt7629-eth", "syscon"; |
| reg = <0x1b100000 0x20000>; |
| clocks = <&topckgen CLK_TOP_ETH_SEL>, |
| <&topckgen CLK_TOP_F10M_REF_SEL>, |
| <ðsys CLK_ETH_ESW_EN>, |
| <ðsys CLK_ETH_GP0_EN>, |
| <ðsys CLK_ETH_GP1_EN>, |
| <ðsys CLK_ETH_GP2_EN>, |
| <ðsys CLK_ETH_FE_EN>, |
| <&sgmiisys0 CLK_SGMII_TX_EN>, |
| <&sgmiisys0 CLK_SGMII_RX_EN>, |
| <&sgmiisys0 CLK_SGMII_CDR_REF>, |
| <&sgmiisys0 CLK_SGMII_CDR_FB>, |
| <&sgmiisys1 CLK_SGMII_TX_EN>, |
| <&sgmiisys1 CLK_SGMII_RX_EN>, |
| <&sgmiisys1 CLK_SGMII_CDR_REF>, |
| <&sgmiisys1 CLK_SGMII_CDR_FB>, |
| <&apmixedsys CLK_APMIXED_SGMIPLL>, |
| <&apmixedsys CLK_APMIXED_ETH2PLL>; |
| clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", |
| "fe", "sgmii_tx250m", "sgmii_rx250m", |
| "sgmii_cdr_ref", "sgmii_cdr_fb", |
| "sgmii2_tx250m", "sgmii2_rx250m", |
| "sgmii2_cdr_ref", "sgmii2_cdr_fb", |
| "sgmii_ck", "eth2pll"; |
| assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>, |
| <&topckgen CLK_TOP_F10M_REF_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>, |
| <&topckgen CLK_TOP_SGMIIPLL_D2>; |
| power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>; |
| resets = <ðsys ETHSYS_FE_RST>; |
| reset-names = "fe"; |
| mediatek,ethsys = <ðsys>; |
| mediatek,sgmiisys = <&sgmiisys0>; |
| mediatek,infracfg = <&infracfg>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| sgmiisys0: syscon@1b128000 { |
| compatible = "mediatek,mt7629-sgmiisys", "syscon"; |
| reg = <0x1b128000 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| sgmiisys1: syscon@1b130000 { |
| compatible = "mediatek,mt7629-sgmiisys", "syscon"; |
| reg = <0x1b130000 0x1000>; |
| #clock-cells = <1>; |
| }; |
| }; |
