arch/arm/dts/fsl-imx8mm.dtsi

/*
 * Copyright 2017-2019 NXP
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include "fsl-imx8-ca53.dtsi"
#include <dt-bindings/clock/imx8mm-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/pins-imx8mm.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "fsl,imx8mm";
	interrupt-parent = <&gpc>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		ethernet0 = &fec1;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		mmc2 = &usdhc3;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		spi0 = &flexspi;
		usb0 = &usbotg1;
		usb1 = &usbotg2;
	};

	cpus {
		idle-states {
			entry-method = "psci";

			CPU_SLEEP: cpu-sleep {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010033>;
				local-timer-stop;
				entry-latency-us = <1000>;
				exit-latency-us = <700>;
				min-residency-us = <2700>;
				wakeup-latency-us = <1500>;
			};
		};
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x80000000>;
	};

	resmem: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0 0x28000000>;
			alloc-ranges = <0 0x40000000 0 0x60000000>;
			linux,cma-default;
		};

		rpmsg_reserved: rpmsg@0xb8000000 {
			no-map;
			reg = <0 0xb8000000 0 0x400000>;
		};
	};

	gic: interrupt-controller@38800000 {
		compatible = "arm,gic-v3";
		reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
		      <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
		#interrupt-cells = <3>;
		interrupt-controller;
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
		clock-frequency = <8000000>;
		arm,no-tick-in-suspend;
		interrupt-parent = <&gic>;
	};

	pmu {
		interrupt-parent = <&gic>;
	};

	busfreq { /* BUSFREQ */
		compatible = "fsl,imx_busfreq";
		clocks = <&clk IMX8MM_DRAM_PLL_OUT>, <&clk IMX8MM_CLK_DRAM_ALT_SRC>,
			 <&clk IMX8MM_CLK_DRAM_APB_SRC>, <&clk IMX8MM_CLK_DRAM_APB_PRE_DIV>,
		         <&clk IMX8MM_CLK_DRAM_CORE>, <&clk IMX8MM_CLK_DRAM_ALT_ROOT>,
			 <&clk IMX8MM_SYS_PLL1_40M>, <&clk IMX8MM_SYS_PLL1_100M>,
			 <&clk IMX8MM_SYS_PLL2_333M>, <&clk IMX8MM_CLK_NOC_DIV>,
			 <&clk IMX8MM_CLK_AHB_DIV>, <&clk IMX8MM_CLK_MAIN_AXI_SRC>,
			 <&clk IMX8MM_CLK_24M>, <&clk IMX8MM_SYS_PLL1_800M>;
		clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div",
			      "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m",
			      "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m",
			      "sys_pll1_800m";
		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-name = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3";
	};

	ddr_pmu0: ddr_pmu@3d800000 {
		compatible = "fsl,imx8m-ddr-pmu", "fsl,imx8-ddr-pmu";
		reg = <0x0 0x3d800000 0x0 0x400000>;
		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		osc_32k: clock@0 {
			compatible = "fixed-clock";
			reg = <0>;
			#clock-cells = <0>;
			clock-frequency = <32768>;
			clock-output-names = "osc_32k";
		};

		osc_24m: clock@1 {
			compatible = "fixed-clock";
			reg = <1>;
			#clock-cells = <0>;
			clock-frequency = <24000000>;
			clock-output-names = "osc_24m";
		};

		clk_ext1: clock@2 {
			compatible = "fixed-clock";
			reg = <3>;
			#clock-cells = <0>;
			clock-frequency = <133000000>;
			clock-output-names = "clk_ext1";
		};

		clk_ext2: clock@3 {
			compatible = "fixed-clock";
			reg = <4>;
			#clock-cells = <0>;
			clock-frequency = <133000000>;
			clock-output-names = "clk_ext2";
		};

		clk_ext3: clock@4 {
			compatible = "fixed-clock";
			reg = <5>;
			#clock-cells = <0>;
			clock-frequency = <133000000>;
			clock-output-names = "clk_ext3";
		};

		clk_ext4: clock@5 {
			compatible = "fixed-clock";
			reg = <6>;
			#clock-cells = <0>;
			clock-frequency= <133000000>;
			clock-output-names = "clk_ext4";
		};
	};

	power-domains {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		/* HSIOMIX */
		hsio_pd: power-domain@0 {
			compatible = "fsl,imx8mm-pm-domain";
			#address-cells = <1>;
			#size-cells = <0>;
			domain-id = <0>;
			#power-domain-cells = <0>;
			domain-name = "HSIO_PD";
			clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>,
				 <&clk IMX8MM_CLK_SIM_HSIO>;

			pcie0_pd: power-domain@1 {
				domain-id = <1>;
				#power-domain-cells = <0>;
				domain-name = "PCIE0_PD";
				clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
			};

			usb_otg1_pd: power-domain@2 {
				domain-id = <2>;
				#power-domain-cells = <0>;
				domain-name = "USB_OTG1_PD";
			};

			usb_otg2_pd: power-domain@3 {
				domain-id = <3>;
				#power-domain-cells = <0>;
				domain-name = "USB_OTG2_PD";
			};
		};

		/* GPU2D&3D */
		gpumix_pd: power-domain@4 {
			compatible = "fsl,imx8mm-pm-domain";
			domain-id = <4>;
			#power-domain-cells = <0>;
			domain-name = "GPUMIX_PD";
			clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
				 <&clk IMX8MM_CLK_GPU2D_ROOT>,
				 <&clk IMX8MM_CLK_GPU3D_ROOT>,
				 <&clk IMX8MM_CLK_GPU_AHB_DIV>;
		};

		vpumix_pd: power-domain@5 {
			compatible = "fsl,imx8mm-pm-domain";
			#address-cells = <1>;
			#size-cells = <0>;
			domain-id = <5>;
			#power-domain-cells = <0>;
			domain-name = "VPUMIX_PD";
			clocks =  <&clk IMX8MM_CLK_VPU_DEC_ROOT>;

			vpu_g1_pd: power-domain@6 {
				domain-id = <6>;
				#power-domain-cells = <0>;
				domain-name = "VPU_G1_PD";
				clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
			};

			vpu_g2_pd: power-domain@7 {
				domain-id = <7>;
				#power-domain-cells = <0>;
				domain-name = "VPU_G2_PD";
				clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
			};

			vpu_h1_pd: power-domain@8 {
				domain-id = <8>;
				#power-domain-cells = <0>;
				domain-name = "VPU_H1_PD";
				clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>;
			};
		};

		dispmix_pd: power-domain@9 {
			compatible = "fsl,imx8mm-pm-domain";
			#address-cells = <1>;
			#size-cells = <0>;
			domain-id = <9>;
			#power-domain-cells = <0>;
			domain-name = "DISPMIX_PD";
			clocks = <&clk IMX8MM_CLK_DISP_ROOT>;

			mipi_pd: power-domain@10 {
				domain-id = <10>;
				#power-domain-cells = <0>;
				domain-name = "MIPI_PD";
			};
		};
	};

	csi1_bridge: csi1_bridge@32e20000 {
		compatible = "fsl,imx8mm-csi", "fsl,imx8mq-csi", "fsl,imx6s-csi";
		reg = <0x0 0x32e20000 0x0 0x10000>;
		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
			<&clk IMX8MM_CLK_CSI1_ROOT>,
			<&clk IMX8MM_CLK_DISP_APB_ROOT>;
		clock-names = "disp-axi", "csi_mclk", "disp_dcic";
		power-domains = <&dispmix_pd>;
		status = "disabled";
	};

	mipi_csi_1: mipi_csi@32e30000 {
		compatible = "fsl,imx8mm-mipi-csi";
		reg = <0x0 0x32e30000 0x0 0x1000>;
		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <333000000>;
		clocks = <&clk IMX8MM_CLK_CSI1_CORE_DIV>,
			<&clk IMX8MM_CLK_CSI1_PHY_REF_DIV>,
			<&clk IMX8MM_CLK_DISP_AXI_ROOT>,
			<&clk IMX8MM_CLK_DISP_APB_ROOT>;
		clock-names = "mipi_clk", "phy_clk", "disp_axi", "disp_apb";
		bus-width = <4>;
		csi-gpr = <&dispmix_gpr>;
		power-domains = <&mipi_pd>;
		status = "disabled";
	};

	gpio1: gpio@30200000 {
		compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x30200000 0x0 0x10000>;
		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpio2: gpio@30210000 {
		compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x30210000 0x0 0x10000>;
		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpio3: gpio@30220000 {
		compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x30220000 0x0 0x10000>;
		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpio4: gpio@30230000 {
		compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x30230000 0x0 0x10000>;
		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpio5: gpio@30240000 {
		compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x30240000 0x0 0x10000>;
		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	tmu: tmu@30260000 {
		compatible = "fsl,imx8mm-tmu";
		reg = <0x0 0x30260000 0x0 0x10000>;
		clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
		interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
		little-endian;
		u-boot,dm-pre-reloc;
		#thermal-sensor-cells =  <0>;
	};

	thermal-zones {
		/* cpu thermal */
		cpu-thermal {
			polling-delay-passive = <250>;
			polling-delay = <2000>;
			thermal-sensors = <&tmu>;
			trips {
				cpu_alert0: trip0 {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit0: trip1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device =
					<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	iomuxc: pinctrl@30330000 {
		compatible = "fsl,imx8mm-iomuxc";
		reg = <0x0 0x30330000 0x0 0x10000>;
	};

	gpr: iomuxc-gpr@30340000 {
		compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", "syscon";
		reg = <0x0 0x30340000 0x0 0x10000>;
	};

	anatop: anatop@30360000 {
		compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus";
		reg = <0x0 0x30360000 0x0 0x10000>;
	};

	snvs: snvs@30370000 {
		compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
		reg = <0x0 0x30370000 0x0 0x10000>;

		snvs_rtc: snvs-rtc-lp{
			compatible = "fsl,sec-v4.0-mon-rtc-lp";
			regmap =<&snvs>;
			offset = <0x34>;
			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		};

		snvs_pwrkey: snvs-powerkey {
			compatible = "fsl,sec-v4.0-pwrkey";
			regmap = <&snvs>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			linux,keycode = <KEY_POWER>;
			wakeup-source;
		};
	};

	clk: clock-controller@30380000 {
		compatible = "fsl,imx8mm-ccm";
		reg = <0x0 0x30380000 0x0 0x10000>;
		#clock-cells = <1>;
		clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
			 <&clk_ext3>, <&clk_ext4>;
		clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
			      "clk_ext3", "clk_ext4";
	};

	src: src@30390000 {
		compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
		reg = <0x0 0x30390000 0x0 0x10000>;
		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
		#reset-cells = <1>;
	};

	gpc: gpc@303a0000 {
		compatible = "fsl,imx8mm-gpc", "fsl,imx8mq-gpc", "syscon";
		reg = <0x0 0x303a0000 0x0 0x10000>;
		interrupt-controller;
		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
	};

	system_counter: timer@306a0000 {
		compatible = "nxp,sysctr-timer";
		reg = <0x0 0x306a0000 0x0 0x10000>, /* system-counter-rd base */
		      <0x0 0x306b0000 0x0 0x10000>, /* system-counter-cmp base */
		      <0x0 0x306c0000 0x0 0x10000>; /* system-counter-ctrl base */
		clock-frequency = <8000000>;
		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
	};

	uart1: serial@30860000 {
		compatible = "fsl,imx8mm-uart",
			     "fsl,imx6q-uart", "fsl,imx21-uart";
		reg = <0x0 0x30860000 0x0 0x10000>;
		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
			<&clk IMX8MM_CLK_UART1_ROOT>;
		clock-names = "ipg", "per";
		dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	uart3: serial@30880000 {
		compatible = "fsl,imx8mm-uart",
			     "fsl,imx6q-uart", "fsl,imx21-uart";
		reg = <0x0 0x30880000 0x0 0x10000>;
		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
			<&clk IMX8MM_CLK_UART3_ROOT>;
		clock-names = "ipg", "per";
		dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	uart2: serial@30890000 {
		compatible = "fsl,imx8mm-uart",
			     "fsl,imx6q-uart", "fsl,imx21-uart";
		reg = <0x0 0x30890000 0x0 0x10000>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
			<&clk IMX8MM_CLK_UART2_ROOT>;
		clock-names = "ipg", "per";
		status = "disabled";
	};

	i2c1: i2c@30a20000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
		reg = <0x0 0x30a20000 0x0 0x10000>;
		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
		status = "disabled";
	};

	i2c2: i2c@30a30000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
		reg = <0x0 0x30a30000 0x0 0x10000>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
		status = "disabled";
	};

	i2c3: i2c@30a40000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
		reg = <0x0 0x30a40000 0x0 0x10000>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
		status = "disabled";
	};

	i2c4: i2c@30a50000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
		reg = <0x0 0x30a50000 0x0 0x10000>;
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
		status = "disabled";
	};

	uart4: serial@30a60000 {
		compatible = "fsl,imx8mq-uart",
			     "fsl,imx6q-uart", "fsl,imx21-uart";
		reg = <0x0 0x30a60000 0x0 0x10000>;
		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
			<&clk IMX8MM_CLK_UART4_ROOT>;
		clock-names = "ipg", "per";
		dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
		dma-names = "rx", "tx";
		status = "disabled";
	};


	imx_rpmsg: imx_rpmsg {
		compatible = "fsl,rpmsg-bus", "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		mu: mu@30aa0000 {
			compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
			reg = <0x0 0x30aa0000 0x0 0x10000>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk IMX8MM_CLK_MU_ROOT>;
			clock-names = "mu";
			status = "disabled";
		};

		rpmsg: rpmsg{
			compatible = "fsl,imx8mq-rpmsg";
			status = "disabled";
		};
	};

	ocotp: ocotp-ctrl@30350000 {
		compatible = "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon";
		reg = <0 0x30350000 0 0x10000>;
		clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
		/* For nvmem subnodes */
		#address-cells = <1>;
		#size-cells = <1>;
	};

	dispmix_gpr: display-gpr@32e28000 {
		compatible = "fsl, imx8mm-iomuxc-gpr", "syscon";
		reg = <0x0 0x32e28000 0x0 0x100>;
	};

	usbotg1: usb@32e40000 {
		compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
		reg = <0x0 0x32e40000 0x0 0x200>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
		clock-names = "usb1_ctrl_root_clk";
		assigned-clocks = <&clk IMX8MM_CLK_USB_BUS_SRC>,
				  <&clk IMX8MM_CLK_USB_CORE_REF_SRC>;
		assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
					 <&clk IMX8MM_SYS_PLL1_100M>;
		fsl,usbphy = <&usbphynop1>;
		fsl,usbmisc = <&usbmisc1 0>;
		power-domains = <&usb_otg1_pd>;
		status = "disabled";
	};

	usbphynop1: usbphynop1 {
		compatible = "usb-nop-xceiv";
		clocks = <&clk IMX8MM_CLK_USB_PHY_REF_SRC>;
		assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF_SRC>;
		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
		clock-names = "main_clk";
	};

	usbmisc1: usbmisc@32e40200 {
		#index-cells = <1>;
		compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
		reg = <0x0 0x32e40200 0x0 0x200>;
	};

	usbotg2: usb@32e50000 {
		compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
		reg = <0x0 0x32e50000 0x0 0x200>;
		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
		clock-names = "usb1_ctrl_root_clk";
		assigned-clocks = <&clk IMX8MM_CLK_USB_BUS_SRC>,
				<&clk IMX8MM_CLK_USB_CORE_REF_SRC>;
		assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
				<&clk IMX8MM_SYS_PLL1_100M>;
		fsl,usbphy = <&usbphynop2>;
		fsl,usbmisc = <&usbmisc2 0>;
		power-domains = <&usb_otg2_pd>;
		status = "disabled";
	};

	usbphynop2: usbphynop2 {
		compatible = "usb-nop-xceiv";
		clocks = <&clk IMX8MM_CLK_USB_PHY_REF_SRC>;
		assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF_SRC>;
		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
		clock-names = "main_clk";
	};

	usbmisc2: usbmisc@32e50200 {
		#index-cells = <1>;
		compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
		reg = <0x0 0x32e50200 0x0 0x200>;
	};

	usdhc1: mmc@30b40000 {
		compatible = "fsl,imx8mq-usdhc", "fsl,imx8qm-usdhc";
		reg = <0x0 0x30b40000 0x0 0x10000>;
		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_DUMMY>,
			 <&clk IMX8MM_CLK_NAND_USDHC_BUS_DIV>,
			 <&clk IMX8MM_CLK_USDHC1_ROOT>;
		clock-names = "ipg", "ahb", "per";
		assigned-clocks = <&clk IMX8MM_CLK_USDHC1_DIV>;
		assigned-clock-rates = <400000000>;
		fsl,tuning-start-tap = <20>;
		fsl,tuning-step= <2>;
		bus-width = <4>;
		status = "disabled";
	};

	usdhc2: mmc@30b50000 {
		compatible = "fsl,imx8mq-usdhc", "fsl,imx8qm-usdhc";
		reg = <0x0 0x30b50000 0x0 0x10000>;
		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_DUMMY>,
			 <&clk IMX8MM_CLK_NAND_USDHC_BUS_DIV>,
			 <&clk IMX8MM_CLK_USDHC2_ROOT>;
		clock-names = "ipg", "ahb", "per";
		fsl,tuning-start-tap = <20>;
		fsl,tuning-step= <2>;
		bus-width = <4>;
		status = "disabled";
	};

	usdhc3: mmc@30b60000 {
		compatible = "fsl,imx8mq-usdhc", "fsl,imx8qm-usdhc";
		reg = <0x0 0x30b60000 0x0 0x10000>;
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_DUMMY>,
			 <&clk IMX8MM_CLK_NAND_USDHC_BUS_DIV>,
			 <&clk IMX8MM_CLK_USDHC3_ROOT>;
		clock-names = "ipg", "ahb", "per";
		assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
		assigned-clock-rates = <400000000>;
		fsl,tuning-start-tap = <20>;
		fsl,tuning-step= <2>;
		bus-width = <4>;
		status = "disabled";
	};

	sai1: sai@30010000 {
		compatible = "fsl,imx8mq-sai",
			     "fsl,imx6sx-sai";
		reg = <0x0 0x30010000 0x0 0x10000>;
		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
			 <&clk IMX8MM_CLK_DUMMY>,
			 <&clk IMX8MM_CLK_SAI1_ROOT>,
			 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
		dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
		dma-names = "rx", "tx";
		fsl,dataline = <0 0xff 0xff>;
		status = "disabled";
	};

	sai2: sai@30020000 {
		compatible = "fsl,imx8mq-sai",
			     "fsl,imx6sx-sai";
		reg = <0x0 0x30020000 0x0 0x10000>;
		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
			<&clk IMX8MM_CLK_DUMMY>,
			<&clk IMX8MM_CLK_SAI2_ROOT>,
			<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
		dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	sai3: sai@30030000 {
		compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai", "fsl,imx6sx-sai";
		reg = <0x0 0x30030000 0x0 0x10000>;
		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
			 <&clk IMX8MM_CLK_DUMMY>,
			 <&clk IMX8MM_CLK_SAI3_ROOT>,
			 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
		dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	sai5: sai@30050000 {
		compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai", "fsl,imx6sx-sai";
		reg = <0x0 0x30050000 0x0 0x10000>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
			 <&clk IMX8MM_CLK_DUMMY>,
			 <&clk IMX8MM_CLK_SAI5_ROOT>,
			 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
		dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
		dma-names = "rx", "tx";
		fsl,shared-interrupt;
		fsl,dataline = <0 0xf 0xf>;
		status = "disabled";
	};

	sai6: sai@30060000 {
		compatible = "fsl,imx8mq-sai",
			     "fsl,imx6sx-sai";
		reg = <0x0 0x30060000 0x0 0x10000>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
			 <&clk IMX8MM_CLK_DUMMY>,
			 <&clk IMX8MM_CLK_SAI6_ROOT>,
			 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
		dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
		dma-names = "rx", "tx";
		fsl,shared-interrupt;
		status = "disabled";
	};

	micfil: micfil@30080000 {
		compatible = "fsl,imx8mm-micfil";
		reg = <0x0 0x30080000 0x0 0x10000>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_PDM_IPG>,
			 <&clk IMX8MM_CLK_PDM_ROOT>,
			 <&clk IMX8MM_AUDIO_PLL1_OUT>,
			 <&clk IMX8MM_AUDIO_PLL2_OUT>,
			 <&clk IMX8MM_CLK_EXT3>;
		clock-names = "ipg_clk", "ipg_clk_app",
			      "pll8k", "pll11k", "clkext3";
		dmas = <&sdma2 24 26 0x80000000>;
		dma-names = "rx";
		status = "disabled";
	};

	spdif1: spdif@30090000 {
		compatible = "fsl,imx8mm-spdif";
		reg = <0x0 0x30090000 0x0 0x10000>;
		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_AUDIO_AHB_DIV>, /* core */
			 <&clk IMX8MM_CLK_24M>, /* rxtx0 */
			 <&clk IMX8MM_CLK_SPDIF1_DIV>, /* rxtx1 */
			 <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
			 <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
			 <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
			 <&clk IMX8MM_CLK_AUDIO_AHB_DIV>, /* rxtx5 */
			 <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
			 <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
			 <&clk IMX8MM_CLK_DUMMY>; /* spba */
		clock-names = "core", "rxtx0",
			      "rxtx1", "rxtx2",
			      "rxtx3", "rxtx4",
			      "rxtx5", "rxtx6",
			      "rxtx7", "spba";
		dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	sdma1: dma-controller@30bd0000 {
		compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
		reg = <0x0 0x30bd0000 0x0 0x10000>;
		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
			 <&clk IMX8MM_CLK_SDMA1_ROOT>;
		clock-names = "ipg", "ahb";
		#dma-cells = <3>;
		fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
		status = "okay";
	};

	sdma2: dma-controller@302c0000 {
		compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
		reg = <0x0 0x302c0000 0x0 0x10000>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
			 <&clk IMX8MM_CLK_SDMA2_ROOT>;
		clock-names = "ipg", "ahb";
		#dma-cells = <3>;
		fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
		fsl,ratio-1-1;
		status = "okay";
	};

	sdma3: dma-controller@302b0000 {
		compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
		reg = <0x0 0x302b0000 0x0 0x10000>;
		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
			 <&clk IMX8MM_CLK_SDMA3_ROOT>;
		clock-names = "ipg", "ahb";
		#dma-cells = <3>;
		fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
		fsl,ratio-1-1;
		status = "okay";
	};

	wdog1: wdog@30280000 {
		compatible = "fsl,imx21-wdt";
		reg = <0 0x30280000 0 0x10000>;
		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
		status = "disabled";
	};

	wdog2: wdog@30290000 {
		compatible = "fsl,imx21-wdt";
		reg = <0 0x30290000 0 0x10000>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
		status = "disabled";
	};

	wdog3: wdog@302a0000 {
		compatible = "fsl,imx21-wdt";
		reg = <0 0x302a0000 0 0x10000>;
		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
		status = "disabled";
	};

	flexspi: flexspi@30bb0000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,imx8mm-flexspi";
		reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>;
		reg-names = "FlexSPI", "FlexSPI-memory";
		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_QSPI_ROOT>;
		clock-names = "fspi";
		assigned-clock-rates = <80000000>;
		assigned-clocks = <&clk IMX8MM_CLK_QSPI_SRC>;
		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
		status = "disabled";
	};

	ecspi1: ecspi@30820000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
		reg = <0x0 0x30820000 0x0 0x10000>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
			<&clk IMX8MM_CLK_ECSPI1_ROOT>;
		clock-names = "ipg", "per";
		dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	ecspi2: ecspi@30830000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
		reg = <0x0 0x30830000 0x0 0x10000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
			<&clk IMX8MM_CLK_ECSPI2_ROOT>;
		clock-names = "ipg", "per";
		dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	ecspi3: ecspi@30840000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
		reg = <0x0 0x30840000 0x0 0x10000>;
		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
			<&clk IMX8MM_CLK_ECSPI3_ROOT>;
		clock-names = "ipg", "per";
		dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	fec1: ethernet@30be0000 {
		compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
		reg = <0x0 0x30be0000 0x0 0x10000>;
		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
			 <&clk IMX8MM_CLK_ENET1_ROOT>,
			 <&clk IMX8MM_CLK_ENET_TIMER_DIV>,
			 <&clk IMX8MM_CLK_ENET_REF_DIV>,
			 <&clk IMX8MM_CLK_ENET_PHY_REF_DIV>;
		clock-names = "ipg", "ahb", "ptp",
			"enet_clk_ref", "enet_out";
		assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI_SRC>,
				  <&clk IMX8MM_CLK_ENET_TIMER_SRC>,
				  <&clk IMX8MM_CLK_ENET_REF_SRC>,
				  <&clk IMX8MM_CLK_ENET_TIMER_DIV>;
		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
					 <&clk IMX8MM_SYS_PLL2_100M>,
					 <&clk IMX8MM_SYS_PLL2_125M>;
		assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
		stop-mode = <&gpr 0x10 3>;
		fsl,num-tx-queues=<3>;
		fsl,num-rx-queues=<3>;
		fsl,wakeup_irq = <2>;
		status = "disabled";
	};

	dma_cap: dma_cap {
		compatible = "dma-capability";
		only-dma-mask32 = <1>;
	};

	imx_ion: imx_ion {
		compatible = "fsl,mxc-ion";
		fsl,heap-id = <0>;
	};

	lcdif: lcdif@32E00000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,imx8mm-lcdif";
		reg = <0x0 0x32e00000 0x0 0x10000>;
		clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL_DIV>,
			 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
			 <&clk IMX8MM_CLK_DISP_APB_ROOT>;
		clock-names = "pix", "disp-axi", "disp-apb";
		assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL_SRC>,
				  <&clk IMX8MM_CLK_DISP_AXI_SRC>,
				  <&clk IMX8MM_CLK_DISP_APB_SRC>;
		assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
					 <&clk IMX8MM_SYS_PLL2_1000M>,
					 <&clk IMX8MM_SYS_PLL1_800M>;
		assigned-clock-rate = <594000000>, <500000000>, <200000000>;
		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		lcdif-gpr = <&dispmix_gpr>;
		power-domains = <&dispmix_pd>;
		status = "disabled";

		lcdif_disp0: port@0 {
			reg = <0>;

			lcdif_to_dsim: endpoint {
				remote-endpoint = <&dsim_from_lcdif>;
			};
		};
	};

	mipi_dsi: mipi_dsi@32E10000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,imx8mm-mipi-dsim";
		reg = <0x0 0x32e10000 0x0 0x400>;
		clocks = <&clk IMX8MM_CLK_DSI_CORE_DIV>,
			 <&clk IMX8MM_CLK_DSI_PHY_REF_DIV>;
		clock-names = "cfg", "pll-ref";
		assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE_SRC>,
				  <&clk IMX8MM_CLK_DSI_PHY_REF_SRC>;
		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
					 <&clk IMX8MM_VIDEO_PLL1_OUT>;
		assigned-clock-rates = <266000000>, <594000000>;
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
		dsi-gpr = <&dispmix_gpr>;
		power-domains = <&mipi_pd>;
		status = "disabled";

		port@0 {
			dsim_from_lcdif: endpoint {
				remote-endpoint = <&lcdif_to_dsim>;
			};
		};
	};

	display-subsystem {
		compatible = "fsl,imx-display-subsystem";
		ports = <&lcdif_disp0>;
	};

	pcie0: pcie@0x33800000 {
		compatible = "fsl,imx8mm-pcie", "snps,dw-pcie";
		reg = <0x0 0x33800000 0x0 0x400000>, <0x0 0x32f00000 0x0 0x10000>,
			<0x0 0x1ff00000 0x0 0x80000>;
		reg-names = "dbi", "phy", "config";
		reserved-region = <&rpmsg_reserved>;
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		ranges =  <0x81000000 0 0x00000000 0x0 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
			   0x82000000 0 0x18000000 0x0 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
		num-lanes = <1>;
		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
		interrupt-names = "msi";
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0x7>;
		interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
			<&clk IMX8MM_CLK_PCIE1_AUX_CG>,
			<&clk IMX8MM_CLK_PCIE1_PHY_CG>;
		clock-names = "pcie", "pcie_bus", "pcie_phy";
		fsl,max-link-speed = <2>;
		ctrl-id = <0>;
		power-domains = <&pcie0_pd>;
		status = "disabled";
	};

	pwm1: pwm@30660000 {
		compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
		reg = <0x0 0x30660000 0x0 0x10000>;
		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
			<&clk IMX8MM_CLK_PWM1_ROOT>;
		clock-names = "ipg", "per";
		#pwm-cells = <2>;
		status = "disabled";
	};

	pwm2: pwm@30670000 {
		compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
		reg = <0x0 0x30670000 0x0 0x10000>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
			<&clk IMX8MM_CLK_PWM2_ROOT>;
		clock-names = "ipg", "per";
		#pwm-cells = <2>;
		status = "disabled";
	};

	pwm3: pwm@30680000 {
		compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
		reg = <0x0 0x30680000 0x0 0x10000>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
			<&clk IMX8MM_CLK_PWM3_ROOT>;
		clock-names = "ipg", "per";
		#pwm-cells = <2>;
		status = "disabled";
	};

	pwm4: pwm@30690000 {
		compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
		reg = <0x0 0x30690000 0x0 0x10000>;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
			<&clk IMX8MM_CLK_PWM4_ROOT>;
		clock-names = "ipg", "per";
		#pwm-cells = <2>;
		status = "disabled";
	};

	vpu_h1: vpu_h1@38320000 {
		compatible = "nxp,imx8mm-hantro-h1";
		reg = <0x0 0x38320000 0x0 0x10000>;
		reg-names = "regs_hantro_h1";
		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "irq_hantro_h1";
		clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
		clock-names = "clk_hantro_h1", "clk_hantro_h1_bus";
		assigned-clocks = <&clk IMX8MM_CLK_VPU_H1_SRC>,<&clk IMX8MM_CLK_VPU_BUS_SRC>;
		assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>;
		assigned-clock-rates = <600000000>, <800000000>;
		power-domains = <&vpu_h1_pd>;
		status = "disabled";
	};

	vpu_g1: vpu_g1@38300000 {
		compatible = "nxp,imx8mm-hantro";
		reg = <0x0 0x38300000 0x0 0x100000>;
		reg-names = "regs_hantro";
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "irq_hantro";
		clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
		clock-names = "clk_hantro", "clk_hantro_bus";
		assigned-clocks = <&clk IMX8MM_CLK_VPU_G1_SRC>, <&clk IMX8MM_CLK_VPU_BUS_SRC>;
		assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>;
		assigned-clock-rates = <600000000>, <800000000>;
		power-domains = <&vpu_g1_pd>;
		status = "disabled";
	};

	vpu_g2: vpu_g2@38310000 {
		compatible = "nxp,imx8mm-hantro";
		reg = <0x0 0x38310000 0x0 0x100000>;
		reg-names = "regs_hantro";
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "irq_hantro";
		clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
		clock-names = "clk_hantro", "clk_hantro_bus";
		assigned-clocks = <&clk IMX8MM_CLK_VPU_G2_SRC>, <&clk IMX8MM_CLK_VPU_BUS_SRC>;
		assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>;
		assigned-clock-rates = <600000000>, <800000000>;
		power-domains = <&vpu_g2_pd>;
		status = "disabled";
	};

	gpu: gpu@38000000 {
		compatible ="fsl,imx8mm-gpu", "fsl,imx6q-gpu";
		reg = <0x0 0x38000000 0x0 0x8000>, <0x0 0x38008000 0x0 0x8000>,
                        <0x0 0x40000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>;
		reg-names = "iobase_3d", "iobase_2d",
                        "phys_baseaddr", "contiguous_mem";
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
                        <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "irq_3d", "irq_2d";
		clocks = <&clk IMX8MM_CLK_GPU3D_ROOT>,
			<&clk IMX8MM_CLK_DUMMY>,
			<&clk IMX8MM_CLK_GPU_BUS_ROOT>,
			<&clk IMX8MM_CLK_GPU_AHB_DIV>,
			<&clk IMX8MM_CLK_GPU2D_ROOT>,
			<&clk IMX8MM_CLK_GPU_BUS_ROOT>,
			<&clk IMX8MM_CLK_GPU_AHB_DIV>;
		clock-names = "gpu3d_clk", "gpu3d_shader_clk",
                              "gpu3d_axi_clk", "gpu3d_ahb_clk",
			      "gpu2d_clk", "gpu2d_axi_clk",
                              "gpu2d_ahb_clk";

		assigned-clocks = <&clk IMX8MM_CLK_GPU3D_SRC>, <&clk IMX8MM_CLK_GPU2D_SRC>, <&clk IMX8MM_CLK_GPU_AXI_SRC>, <&clk IMX8MM_CLK_GPU_AHB_SRC>,<&clk IMX8MM_GPU_PLL_OUT>, <&clk IMX8MM_CLK_GPU_AHB_DIV>;
		assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>,<&clk IMX8MM_GPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>, <&clk IMX8MM_SYS_PLL1_800M>;
		assigned-clock-rates = <0>, <0>, <0>,<0>,<1000000000>, <400000000>;

		power-domains = <&gpumix_pd>;

		status = "disabled";
	};

	crypto: caam@30900000 {
		compatible = "fsl,sec-v4.0";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		reg = <0 0x30900000 0 0x40000>;
		ranges = <0 0 0x30900000 0x40000>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;

		sec_jr0: jr0@1000 {
			 compatible = "fsl,sec-v4.0-job-ring";
			 reg = <0x1000 0x1000>;
			 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
		};

		sec_jr1: jr1@2000 {
			 compatible = "fsl,sec-v4.0-job-ring";
			 reg = <0x2000 0x1000>;
			 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
		};

		sec_jr2: jr2@3000 {
			 compatible = "fsl,sec-v4.0-job-ring";
			 reg = <0x3000 0x1000>;
			 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	caam_sm: caam-sm@00100000 {
		compatible = "fsl,imx6q-caam-sm";
		reg = <0 0x00100000 0 0x8000>;
	};

	caam_snvs: caam-snvs@30370000 {
		compatible = "fsl,imx6q-caam-snvs";
		reg = <0 0x30370000 0 0x10000>;
	};

	irq_sec_vio: caam_secvio {
		compatible = "fsl,imx7d-caam-secvio", "fsl,imx6q-caam-secvio";
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		jtag-tamper = "disabled";
		watchdog-tamper = "enabled";
		internal-boot-tamper = "enabled";
		external-pin-tamper = "disabled";
	};

	dma_apbh: dma-apbh@33000000 {
		compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
		reg = <0 0x33000000 0 0x2000>;
		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
		#dma-cells = <1>;
		dma-channels = <4>;
		clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
	};

	gpmi: gpmi-nand@33002000{
		compatible = "fsl,imx7d-gpmi-nand";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0 0x33002000 0 0x2000>, <0 0x33004000 0 0x4000>;
		reg-names = "gpmi-nand", "bch";
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "bch";
		clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
			<&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
		clock-names = "gpmi_io", "gpmi_bch_apb";
		dmas = <&dma_apbh 0>;
		dma-names = "rx-tx";
		status = "disabled";
	};
};

&A53_0 {
	operating-points = <
		/* kHz    uV */
		1800000 1000000
		1600000 950000
		1200000 850000
	>;
	clocks = <&clk IMX8MM_CLK_A53_DIV>, <&clk IMX8MM_CLK_A53_SRC>,
		<&clk IMX8MM_ARM_PLL>, <&clk IMX8MM_ARM_PLL_OUT>,
		<&clk IMX8MM_SYS_PLL1_800M>;
	clock-names = "a53", "arm_a53_src", "arm_pll",
		"arm_pll_out", "sys1_pll_800m";
	clock-latency = <61036>;
	#cooling-cells = <2>;
};