| /* |
| * Device Tree Include file for Marvell Armada 375 family SoC |
| * |
| * Copyright (C) 2014 Marvell |
| * |
| * Gregory CLEMENT <gregory.clement@free-electrons.com> |
| * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
| * |
| * This file is dual-licensed: you can use it either under the terms |
| * of the GPL or the X11 license, at your option. Note that this dual |
| * licensing only applies to this file, and not this project as a |
| * whole. |
| * |
| * a) This file is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; either version 2 of the |
| * License, or (at your option) any later version. |
| * |
| * This file is distributed in the hope that it will be useful |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * Or, alternatively |
| * |
| * b) Permission is hereby granted, free of charge, to any person |
| * obtaining a copy of this software and associated documentation |
| * files (the "Software"), to deal in the Software without |
| * restriction, including without limitation the rights to use |
| * copy, modify, merge, publish, distribute, sublicense, and/or |
| * sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following |
| * conditions: |
| * |
| * The above copyright notice and this permission notice shall be |
| * included in all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
| * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
| * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY |
| * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| |
| #include "skeleton.dtsi" |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/phy/phy.h> |
| |
| #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) |
| |
| / { |
| model = "Marvell Armada 375 family SoC"; |
| compatible = "marvell,armada375"; |
| |
| aliases { |
| gpio0 = &gpio0; |
| gpio1 = &gpio1; |
| gpio2 = &gpio2; |
| serial0 = &uart0; |
| serial1 = &uart1; |
| }; |
| |
| clocks { |
| /* 2 GHz fixed main PLL */ |
| mainpll: mainpll { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <1000000000>; |
| }; |
| /* 25 MHz reference crystal */ |
| refclk: oscillator { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <25000000>; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| enable-method = "marvell,armada-375-smp"; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a9"; |
| reg = <0>; |
| }; |
| cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a9"; |
| reg = <1>; |
| }; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a9-pmu"; |
| interrupts-extended = <&mpic 3>; |
| }; |
| |
| soc { |
| compatible = "marvell,armada375-mbus", "simple-bus"; |
| u-boot,dm-pre-reloc; |
| #address-cells = <2>; |
| #size-cells = <1>; |
| controller = <&mbusc>; |
| interrupt-parent = <&gic>; |
| pcie-mem-aperture = <0xe0000000 0x8000000>; |
| pcie-io-aperture = <0xe8000000 0x100000>; |
| |
| bootrom { |
| compatible = "marvell,bootrom"; |
| reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>; |
| }; |
| |
| devbus-bootcs { |
| compatible = "marvell,mvebu-devbus"; |
| reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; |
| ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| clocks = <&coreclk 0>; |
| status = "disabled"; |
| }; |
| |
| devbus-cs0 { |
| compatible = "marvell,mvebu-devbus"; |
| reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; |
| ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| clocks = <&coreclk 0>; |
| status = "disabled"; |
| }; |
| |
| devbus-cs1 { |
| compatible = "marvell,mvebu-devbus"; |
| reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; |
| ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| clocks = <&coreclk 0>; |
| status = "disabled"; |
| }; |
| |
| devbus-cs2 { |
| compatible = "marvell,mvebu-devbus"; |
| reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; |
| ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| clocks = <&coreclk 0>; |
| status = "disabled"; |
| }; |
| |
| devbus-cs3 { |
| compatible = "marvell,mvebu-devbus"; |
| reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; |
| ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| clocks = <&coreclk 0>; |
| status = "disabled"; |
| }; |
| |
| internal-regs { |
| compatible = "simple-bus"; |
| u-boot,dm-pre-reloc; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; |
| |
| L2: cache-controller@8000 { |
| compatible = "arm,pl310-cache"; |
| reg = <0x8000 0x1000>; |
| cache-unified; |
| cache-level = <2>; |
| arm,double-linefill-incr = <1>; |
| arm,double-linefill-wrap = <0>; |
| arm,double-linefill = <1>; |
| prefetch-data = <1>; |
| }; |
| |
| scu@c000 { |
| compatible = "arm,cortex-a9-scu"; |
| reg = <0xc000 0x58>; |
| }; |
| |
| timer@c600 { |
| compatible = "arm,cortex-a9-twd-timer"; |
| reg = <0xc600 0x20>; |
| interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; |
| clocks = <&coreclk 2>; |
| }; |
| |
| gic: interrupt-controller@d000 { |
| compatible = "arm,cortex-a9-gic"; |
| #interrupt-cells = <3>; |
| #size-cells = <0>; |
| interrupt-controller; |
| reg = <0xd000 0x1000>, |
| <0xc100 0x100>; |
| }; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "marvell,orion-mdio"; |
| reg = <0xc0054 0x4>; |
| clocks = <&gateclk 19>; |
| }; |
| |
| /* Network controller */ |
| ethernet@f0000 { |
| compatible = "marvell,armada-375-pp2"; |
| reg = <0xf0000 0xa000>, /* Packet Processor regs */ |
| <0xc0000 0x3060>, /* LMS regs */ |
| <0xc4000 0x100>, /* eth0 regs */ |
| <0xc5000 0x100>; /* eth1 regs */ |
| clocks = <&gateclk 3>, <&gateclk 19>; |
| clock-names = "pp_clk", "gop_clk"; |
| status = "disabled"; |
| |
| eth0: eth0@c4000 { |
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| port-id = <0>; |
| status = "disabled"; |
| }; |
| |
| eth1: eth1@c5000 { |
| interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
| port-id = <1>; |
| status = "disabled"; |
| }; |
| }; |
| |
| rtc@10300 { |
| compatible = "marvell,orion-rtc"; |
| reg = <0x10300 0x20>; |
| interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| spi0: spi@10600 { |
| compatible = "marvell,armada-375-spi", |
| "marvell,orion-spi"; |
| reg = <0x10600 0x50>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cell-index = <0>; |
| interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&coreclk 0>; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@10680 { |
| compatible = "marvell,armada-375-spi", |
| "marvell,orion-spi"; |
| reg = <0x10680 0x50>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cell-index = <1>; |
| interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&coreclk 0>; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@11000 { |
| compatible = "marvell,mv64xxx-i2c"; |
| reg = <0x11000 0x20>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
| timeout-ms = <1000>; |
| clocks = <&coreclk 0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@11100 { |
| compatible = "marvell,mv64xxx-i2c"; |
| reg = <0x11100 0x20>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
| timeout-ms = <1000>; |
| clocks = <&coreclk 0>; |
| status = "disabled"; |
| }; |
| |
| uart0: serial@12000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x12000 0x100>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| reg-io-width = <1>; |
| clocks = <&coreclk 0>; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@12100 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x12100 0x100>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| reg-io-width = <1>; |
| clocks = <&coreclk 0>; |
| status = "disabled"; |
| }; |
| |
| pinctrl { |
| compatible = "marvell,mv88f6720-pinctrl"; |
| reg = <0x18000 0x24>; |
| |
| i2c0_pins: i2c0-pins { |
| marvell,pins = "mpp14", "mpp15"; |
| marvell,function = "i2c0"; |
| }; |
| |
| i2c1_pins: i2c1-pins { |
| marvell,pins = "mpp61", "mpp62"; |
| marvell,function = "i2c1"; |
| }; |
| |
| nand_pins: nand-pins { |
| marvell,pins = "mpp0", "mpp1", "mpp2", |
| "mpp3", "mpp4", "mpp5", |
| "mpp6", "mpp7", "mpp8", |
| "mpp9", "mpp10", "mpp11", |
| "mpp12", "mpp13"; |
| marvell,function = "nand"; |
| }; |
| |
| sdio_pins: sdio-pins { |
| marvell,pins = "mpp24", "mpp25", "mpp26", |
| "mpp27", "mpp28", "mpp29"; |
| marvell,function = "sd"; |
| }; |
| |
| spi0_pins: spi0-pins { |
| marvell,pins = "mpp0", "mpp1", "mpp4", |
| "mpp5", "mpp8", "mpp9"; |
| marvell,function = "spi0"; |
| }; |
| }; |
| |
| gpio0: gpio@18100 { |
| compatible = "marvell,orion-gpio"; |
| reg = <0x18100 0x40>; |
| ngpios = <32>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| gpio1: gpio@18140 { |
| compatible = "marvell,orion-gpio"; |
| reg = <0x18140 0x40>; |
| ngpios = <32>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| gpio2: gpio@18180 { |
| compatible = "marvell,orion-gpio"; |
| reg = <0x18180 0x40>; |
| ngpios = <3>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| system-controller@18200 { |
| compatible = "marvell,armada-375-system-controller"; |
| reg = <0x18200 0x100>; |
| }; |
| |
| gateclk: clock-gating-control@18220 { |
| compatible = "marvell,armada-375-gating-clock"; |
| reg = <0x18220 0x4>; |
| clocks = <&coreclk 0>; |
| #clock-cells = <1>; |
| }; |
| |
| usbcluster: usb-cluster@18400 { |
| compatible = "marvell,armada-375-usb-cluster"; |
| reg = <0x18400 0x4>; |
| #phy-cells = <1>; |
| }; |
| |
| mbusc: mbus-controller@20000 { |
| compatible = "marvell,mbus-controller"; |
| reg = <0x20000 0x100>, <0x20180 0x20>; |
| }; |
| |
| mpic: interrupt-controller@20a00 { |
| compatible = "marvell,mpic"; |
| reg = <0x20a00 0x2d0>, <0x21070 0x58>; |
| #interrupt-cells = <1>; |
| #size-cells = <1>; |
| interrupt-controller; |
| msi-controller; |
| interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| timer@20300 { |
| compatible = "marvell,armada-375-timer", "marvell,armada-370-timer"; |
| reg = <0x20300 0x30>, <0x21040 0x30>; |
| interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, |
| <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, |
| <&mpic 5>, |
| <&mpic 6>; |
| clocks = <&coreclk 0>, <&refclk>; |
| clock-names = "nbclk", "fixed"; |
| }; |
| |
| watchdog@20300 { |
| compatible = "marvell,armada-375-wdt"; |
| reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>; |
| clocks = <&coreclk 0>, <&refclk>; |
| clock-names = "nbclk", "fixed"; |
| }; |
| |
| cpurst@20800 { |
| compatible = "marvell,armada-370-cpu-reset"; |
| reg = <0x20800 0x10>; |
| }; |
| |
| coherency-fabric@21010 { |
| compatible = "marvell,armada-375-coherency-fabric"; |
| reg = <0x21010 0x1c>; |
| }; |
| |
| usb@50000 { |
| compatible = "marvell,orion-ehci"; |
| reg = <0x50000 0x500>; |
| interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gateclk 18>; |
| phys = <&usbcluster PHY_TYPE_USB2>; |
| phy-names = "usb"; |
| status = "disabled"; |
| }; |
| |
| usb@54000 { |
| compatible = "marvell,orion-ehci"; |
| reg = <0x54000 0x500>; |
| interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gateclk 26>; |
| status = "disabled"; |
| }; |
| |
| usb3@58000 { |
| compatible = "marvell,armada-375-xhci"; |
| reg = <0x58000 0x20000>,<0x5b880 0x80>; |
| interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gateclk 16>; |
| phys = <&usbcluster PHY_TYPE_USB3>; |
| phy-names = "usb"; |
| status = "disabled"; |
| }; |
| |
| xor@60800 { |
| compatible = "marvell,orion-xor"; |
| reg = <0x60800 0x100 |
| 0x60A00 0x100>; |
| clocks = <&gateclk 22>; |
| status = "okay"; |
| |
| xor00 { |
| interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
| dmacap,memcpy; |
| dmacap,xor; |
| }; |
| xor01 { |
| interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| dmacap,memcpy; |
| dmacap,xor; |
| dmacap,memset; |
| }; |
| }; |
| |
| xor@60900 { |
| compatible = "marvell,orion-xor"; |
| reg = <0x60900 0x100 |
| 0x60b00 0x100>; |
| clocks = <&gateclk 23>; |
| status = "okay"; |
| |
| xor10 { |
| interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| dmacap,memcpy; |
| dmacap,xor; |
| }; |
| xor11 { |
| interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
| dmacap,memcpy; |
| dmacap,xor; |
| dmacap,memset; |
| }; |
| }; |
| |
| crypto@90000 { |
| compatible = "marvell,armada-375-crypto"; |
| reg = <0x90000 0x10000>; |
| reg-names = "regs"; |
| interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gateclk 30>, <&gateclk 31>, |
| <&gateclk 28>, <&gateclk 29>; |
| clock-names = "cesa0", "cesa1", |
| "cesaz0", "cesaz1"; |
| marvell,crypto-srams = <&crypto_sram0>, |
| <&crypto_sram1>; |
| marvell,crypto-sram-size = <0x800>; |
| }; |
| |
| sata@a0000 { |
| compatible = "marvell,orion-sata"; |
| reg = <0xa0000 0x5000>; |
| interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gateclk 14>, <&gateclk 20>; |
| clock-names = "0", "1"; |
| status = "disabled"; |
| }; |
| |
| nand@d0000 { |
| compatible = "marvell,armada370-nand"; |
| reg = <0xd0000 0x54>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gateclk 11>; |
| status = "disabled"; |
| }; |
| |
| mvsdio@d4000 { |
| compatible = "marvell,orion-sdio"; |
| reg = <0xd4000 0x200>; |
| interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gateclk 17>; |
| bus-width = <4>; |
| cap-sdio-irq; |
| cap-sd-highspeed; |
| cap-mmc-highspeed; |
| status = "disabled"; |
| }; |
| |
| thermal@e8078 { |
| compatible = "marvell,armada375-thermal"; |
| reg = <0xe8078 0x4>, <0xe807c 0x8>; |
| status = "okay"; |
| }; |
| |
| coreclk: mvebu-sar@e8204 { |
| compatible = "marvell,armada-375-core-clock"; |
| reg = <0xe8204 0x04>; |
| #clock-cells = <1>; |
| }; |
| |
| coredivclk: corediv-clock@e8250 { |
| compatible = "marvell,armada-375-corediv-clock"; |
| reg = <0xe8250 0xc>; |
| #clock-cells = <1>; |
| clocks = <&mainpll>; |
| clock-output-names = "nand"; |
| }; |
| }; |
| |
| pciec: pcie@82000000 { |
| compatible = "marvell,armada-370-pcie"; |
| status = "disabled"; |
| device_type = "pci"; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| msi-parent = <&mpic>; |
| bus-range = <0x00 0xff>; |
| |
| ranges = |
| <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 |
| 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 |
| 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */ |
| 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */ |
| 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */ |
| 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>; |
| |
| pcie0: pcie@1,0 { |
| device_type = "pci"; |
| assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; |
| reg = <0x0800 0 0 0 0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| #interrupt-cells = <1>; |
| ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 |
| 0x81000000 0 0 0x81000000 0x1 0 1 0>; |
| bus-range = <0x00 0xff>; |
| interrupt-map-mask = <0 0 0 0>; |
| interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
| marvell,pcie-port = <0>; |
| marvell,pcie-lane = <0>; |
| clocks = <&gateclk 5>; |
| status = "disabled"; |
| }; |
| |
| pcie1: pcie@2,0 { |
| device_type = "pci"; |
| assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; |
| reg = <0x1000 0 0 0 0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| #interrupt-cells = <1>; |
| ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 |
| 0x81000000 0 0 0x81000000 0x2 0 1 0>; |
| bus-range = <0x00 0xff>; |
| interrupt-map-mask = <0 0 0 0>; |
| interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
| marvell,pcie-port = <0>; |
| marvell,pcie-lane = <1>; |
| clocks = <&gateclk 6>; |
| status = "disabled"; |
| }; |
| |
| }; |
| |
| crypto_sram0: sa-sram0 { |
| compatible = "mmio-sram"; |
| reg = <MBUS_ID(0x09, 0x09) 0 0x800>; |
| clocks = <&gateclk 30>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>; |
| }; |
| |
| crypto_sram1: sa-sram1 { |
| compatible = "mmio-sram"; |
| reg = <MBUS_ID(0x09, 0x05) 0 0x800>; |
| clocks = <&gateclk 31>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>; |
| }; |
| }; |
| }; |
