MLK-21745-02 board: imx8mm_val: change the ddr init to the common driver
change the ddr init to use the common driver init driver as
we used on EVK board.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 2c5b74872bdc62b02a6e7c5761e27cdaeb677c8d)
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index c3f6bc9..7a0b191 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -39,11 +39,13 @@
bool "imx8mm DDR4 validation board"
select IMX8MM
select SUPPORT_SPL
+ select IMX8M_DDR4
config TARGET_IMX8MM_DDR3L_VAL
bool "imx8mm DDR3L validation board"
select IMX8MM
select SUPPORT_SPL
+ select IMX8M_DDR3L
config TARGET_IMX8MM_EVK
bool "imx8mm LPDDR4 EVK board"
diff --git a/board/freescale/imx8mm_val/Makefile b/board/freescale/imx8mm_val/Makefile
index 4911989..1871b53 100644
--- a/board/freescale/imx8mm_val/Makefile
+++ b/board/freescale/imx8mm_val/Makefile
@@ -8,5 +8,6 @@
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
-obj-y += ddr/
+obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
+obj-$(CONFIG_IMX8M_DDR3L) += ddr3l_timing.o
endif
diff --git a/board/freescale/imx8mm_val/ddr/Makefile b/board/freescale/imx8mm_val/ddr/Makefile
deleted file mode 100644
index d0a9f5a..0000000
--- a/board/freescale/imx8mm_val/ddr/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright 2018 NXP
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-y += helper.o
-obj-y += wait_ddrphy_training_complete.o
-obj-$(CONFIG_TARGET_IMX8MM_DDR4_VAL) += ddr4/
-obj-$(CONFIG_TARGET_IMX8MM_DDR3L_VAL) += ddr3l/
-endif
diff --git a/board/freescale/imx8mm_val/ddr/ddr.h b/board/freescale/imx8mm_val/ddr/ddr.h
deleted file mode 100644
index 2ccdd10..0000000
--- a/board/freescale/imx8mm_val/ddr/ddr.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright 2018 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
- * Common file for ddr code
- */
-
-#ifndef __M845S_DDR_H_
-#define __M845S_DDR_H_
-
-#ifdef DDR_DEBUG
-#define ddr_dbg(fmt, ...) printf("DDR: debug:" fmt "\n", ##__VA_ARGS__)
-#else
-#define ddr_dbg(fmt, ...)
-#endif
-
-/*******************************************************************
- Desc: prototype
-
- *******************************************************************/
-void ddr_load_train_code(enum fw_type type);
-void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(unsigned int pstate);
-void dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(void);
-void dwc_ddrphy_phyinit_userCustom_customPostTrain(void);
-void dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy(void);
-void dwc_ddrphy_phyinit_userCustom_A_bringupPower(void);
-void dwc_ddrphy_phyinit_userCustom_overrideUserInput(void);
-void dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(unsigned int run_2D);
-void dwc_ddrphy_phyinit_userCustom_G_waitFwDone(void);
-
-#endif
diff --git a/board/freescale/imx8mm_val/ddr/ddr3l/Makefile b/board/freescale/imx8mm_val/ddr/ddr3l/Makefile
deleted file mode 100644
index dac4d50..0000000
--- a/board/freescale/imx8mm_val/ddr/ddr3l/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Copyright 2018 NXP
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-y += ddr3_phyinit_task.o
-obj-y += ddr3_phyinit_train_sw_ffc_fw09.o
-obj-y += ddr3_sw_fast_freq_chg_fw09.o
-obj-y += restore_1d2d_trained_csr_ddr3_p012.o
-obj-y += save_1d2d_trained_csr_ddr3_p012.o
-endif
diff --git a/board/freescale/imx8mm_val/ddr/ddr3l/anamix_common.h b/board/freescale/imx8mm_val/ddr/ddr3l/anamix_common.h
deleted file mode 100644
index 9f1ddd3..0000000
--- a/board/freescale/imx8mm_val/ddr/ddr3l/anamix_common.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright 2018 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ANAMIX_COMMON_TMP_H
-#define ANAMIX_COMMON_TMP_H
-
-/*ANAMIX Address Definition*/
-#define ANAMIX_PLL_BASE_ADDR 0x30360000
-#define ANAMIX_OSC_BASE_ADDR 0x30270000
-#define ANAMIX_TSN_BASE_ADDR 0x30260000
-
-/* PLL TOP REG */
-#define AUDIO_PLL1_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x00)
-#define AUDIO_PLL1_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x04)
-#define AUDIO_PLL1_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x08)
-#define AUDIO_PLL1_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x0c)
-#define AUDIO_PLL1_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x10)
-#define AUDIO_PLL2_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x14)
-#define AUDIO_PLL2_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x18)
-#define AUDIO_PLL2_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x1c)
-#define AUDIO_PLL2_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x20)
-#define AUDIO_PLL2_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x24)
-#define VIDEO_PLL1_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x28)
-#define VIDEO_PLL1_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x2c)
-#define VIDEO_PLL1_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x30)
-#define VIDEO_PLL1_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x34)
-#define VIDEO_PLL1_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x38)
-#define VIDEO_PLL2_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x3c)
-#define VIDEO_PLL2_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x40)
-#define VIDEO_PLL2_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x44)
-#define VIDEO_PLL2_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x48)
-#define VIDEO_PLL2_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x4c)
-#define DRAM_PLL_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x50)
-#define DRAM_PLL_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x54)
-#define DRAM_PLL_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x58)
-#define DRAM_PLL_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x5c)
-#define DRAM_PLL_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x60)
-#define GPU_PLL_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x64)
-#define GPU_PLL_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x68)
-#define GPU_PLL_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x6c)
-#define GPU_PLL_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x70)
-#define VPU_PLL_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x74)
-#define VPU_PLL_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x78)
-#define VPU_PLL_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x7c)
-#define VPU_PLL_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x80)
-#define ARM_PLL_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x84)
-#define ARM_PLL_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x88)
-#define ARM_PLL_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x8c)
-#define ARM_PLL_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x90)
-#define SYS_PLL1_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x94)
-#define SYS_PLL1_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x98)
-#define SYS_PLL1_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x9c)
-#define SYS_PLL1_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x100)
-#define SYS_PLL2_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x104)
-#define SYS_PLL2_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x108)
-#define SYS_PLL2_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x10c)
-#define SYS_PLL2_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x110)
-#define SYS_PLL3_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x114)
-#define SYS_PLL3_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x118)
-#define SYS_PLL3_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x11c)
-#define SYS_PLL3_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x120)
-#define ANAMIX_MISC_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x124)
-#define ANAMIX_CLK_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x128)
-
-/* TMP SNSR REG */
-#define TER_ADDR (ANAMIX_TSN_BASE_ADDR + 0x00)
-#define TSR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x04)
-#define TIER_ADDR (ANAMIX_TSN_BASE_ADDR + 0x08)
-#define TIDR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x0c)
-#define TMHTITR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x10)
-#define TMHTATR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x14)
-#define TMHTACTR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x18)
-#define TSCR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x1c)
-#define TRITSR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x20)
-#define TRATSR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x24)
-#define TASR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x28)
-#define TTMC_ADDR (ANAMIX_TSN_BASE_ADDR + 0x2c)
-
-/* OSC */
-#define SYS_OSCNML_CTL0_ADDR (ANAMIX_OSC_BASE_ADDR + 0x00)
-#define SYS_OSCNML_CTL1_ADDR (ANAMIX_OSC_BASE_ADDR + 0x04)
-#define HDMI_OSCNML_CTL0_ADDR (ANAMIX_OSC_BASE_ADDR + 0x8000)
-#define HDMI_OSCNML_CTL1_ADDR (ANAMIX_OSC_BASE_ADDR + 0x8004)
-
-#endif
diff --git a/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_define.h b/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_define.h
deleted file mode 100644
index de87147..0000000
--- a/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_define.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2018 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef DDR3_DEFINE_H
-#define DDR3_DEFINE_H
-
-#include "../ddr.h"
-
-#define RUN_ON_SILICON
-
-#ifdef DDR3_1600MTS_SWFFC_RET
- #define DDR3_SW_FFC
-#endif
-
-#define SAVE_DDRPHY_TRAIN_ADDR 0x180000
-#define DDR_CSD1_BASE_ADDR 0x40000000
-#define DDR_CSD2_BASE_ADDR 0x80000000
-
-#define ANAMIX_PLL_BASE_ADDR 0x30360000
-#define HW_DRAM_PLL_CFG0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x60)
-#define HW_DRAM_PLL_CFG1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x64)
-#define HW_DRAM_PLL_CFG2_ADDR (ANAMIX_PLL_BASE_ADDR + 0x68)
-#define GPC_PU_PWRHSK 0x303A01FC
-#define GPC_TOP_CONFIG_OFFSET 0x0000
-#define AIPS1_ARB_BASE_ADDR 0x30000000
-#define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
-#define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x200000)
-#define CCM_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x180000)
-#define CCM_SRC_CTRL_OFFSET (CCM_IPS_BASE_ADDR + 0x800)
-#define CCM_SRC_CTRL(n) (CCM_SRC_CTRL_OFFSET + 0x10 * n)
-
-#define dwc_ddrphy_apb_wr(addr, data) reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data)
-#define reg32clrbit(addr, bitpos) reg32_write((addr), (reg32_read((addr)) & (0xFFFFFFFF ^ (1 << (bitpos)))))
-
-void restore_1d2d_trained_csr_ddr3_p012(unsigned int addr);
-void save_1d2d_trained_csr_ddr3_p012(unsigned int addr);
-void ddr3_phyinit_train_sw_ffc(unsigned int after_retention);
-
-#endif
diff --git a/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_phyinit_task.c b/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_phyinit_task.c
deleted file mode 100644
index 79f19ed..0000000
--- a/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_phyinit_task.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2018 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/ddr.h>
-#include <asm/arch/clock.h>
-#include "ddr3_define.h"
-
-void dwc_ddrphy_phyinit_userCustom_E_setDfiClk (unsigned int pstate) {
- if (pstate == 0) {
- ddr_dbg("C: 1 ...\n");
- dram_pll_init(MHZ(400));
- } else if (pstate == 1) {
- ddr_dbg("C: 2 ...\n");
- dram_pll_init(MHZ(266));
- } else if (pstate == 2) {
- ddr_dbg("C: 3 ...\n");
- dram_pll_init(MHZ(167));
- } else {
- printf("C: no freq match\n");
- }
-}
-
-void dwc_ddrphy_phyinit_userCustom_G_waitFwDone(void)
-{
- wait_ddrphy_training_complete();
-}
-void dwc_ddrphy_phyinit_userCustom_overrideUserInput (void) {}
-void dwc_ddrphy_phyinit_userCustom_A_bringupPower (void) {}
-void dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy (void) {}
-void dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(unsigned int Train2D) {}
-void dwc_ddrphy_phyinit_userCustom_customPostTrain(void) {}
-void dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(void) {}
-
-void ddr3_mr_write(unsigned int mr, unsigned int data, unsigned int read, unsigned int rank)
-{
- unsigned int tmp, mr_mirror, data_mirror;
-
- /* 1. Poll MRSTAT.mr_wr_busy until it is 0. This checks that there is no outstanding MR transaction. No */
- /* writes should be performed to MRCTRL0 and MRCTRL1 if MRSTAT.mr_wr_busy = 1. */
- do {
- tmp = reg32_read(DDRC_MRSTAT(0));
- } while (tmp & 0x1);
-
- /* 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and (for MRWs) */
- /* MRCTRL1.mr_data to define the MR transaction. */
- /* (A3, A4), (A5, A6), (A7, A8), (BA0, BA1),*/
- tmp = reg32_read(DDRC_DIMMCTL(0));
- if ((tmp & 0x2) && (rank == 0x2)) {
- mr_mirror = (mr & 0x4) | ((mr & 0x1) << 1) | ((mr & 0x2) >> 1);/* BA0, BA1 swap */
- data_mirror = (data & 0xfe07) | ((data & 0x8) << 1) | ((data & 0x10) >> 1) | ((data & 0x20) << 1) | ((data & 0x40) >> 1) | ((data & 0x80) << 1) | ((data & 0x100) >> 1);
- } else {
- mr_mirror = mr;
- data_mirror = data;
- }
-
- reg32_write(DDRC_MRCTRL0(0), read | (mr_mirror << 12) | (rank << 4));
- reg32_write(DDRC_MRCTRL1(0), data_mirror);
-
- /* 3. In a separate APB transaction, write the MRCTRL0.mr_wr to 1. This bit is self-clearing, and triggers */
- /* the MR transaction. The uMCTL2 then asserts the MRSTAT.mr_wr_busy while it performs the MR */
- /* transaction to SDRAM, and no further accesses can be initiated until it is deasserted. */
- reg32setbit(DDRC_MRCTRL0(0), 31);
- do {
- tmp = reg32_read(DDRC_MRSTAT(0));
- } while (tmp);
-
-}
diff --git a/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_phyinit_train_sw_ffc_fw09.c b/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_phyinit_train_sw_ffc_fw09.c
deleted file mode 100644
index c809c43..0000000
--- a/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_phyinit_train_sw_ffc_fw09.c
+++ /dev/null
@@ -1,1157 +0,0 @@
-/*
- * Copyright 2018 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/ddr.h>
-#include <asm/arch/clock.h>
-#include "../ddr.h"
-#include "ddr3_define.h"
-
-void ddr3_phyinit_train_sw_ffc(unsigned int after_retention)
-{
- /* [dwc_ddrphy_phyinit_main] Start of dwc_ddrphy_phyinit_main() */
- /* [dwc_ddrphy_phyinit_sequence] Start of dwc_ddrphy_phyinit_sequence() */
- /* [dwc_ddrphy_phyinit_initStruct] Start of dwc_ddrphy_phyinit_initStruct() */
- /* [dwc_ddrphy_phyinit_initStruct] End of dwc_ddrphy_phyinit_initStruct() */
- /* [dwc_ddrphy_phyinit_setDefault] Start of dwc_ddrphy_phyinit_setDefault() */
- /* [dwc_ddrphy_phyinit_setDefault] End of dwc_ddrphy_phyinit_setDefault() */
-
-
- /* ############################################################## */
- /* */
- /* dwc_ddrphy_phyinit_userCustom_overrideUserInput is a user-editable function. */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
-
- dwc_ddrphy_phyinit_userCustom_overrideUserInput ();
- /* */
- /* [dwc_ddrphy_phyinit_userCustom_overrideUserInput] End of dwc_ddrphy_phyinit_userCustom_overrideUserInput() */
-
-
- /* ############################################################## */
- /* */
- /* Step (A) : Bring up VDD, VDDQ, and VAA */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
-
-
- dwc_ddrphy_phyinit_userCustom_A_bringupPower ();
-
- /* [dwc_ddrphy_phyinit_userCustom_A_bringupPower] End of dwc_ddrphy_phyinit_userCustom_A_bringupPower() */
- /* [dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy] Start of dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* Step (B) Start Clocks and Reset the PHY */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- /* */
- dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy ();
-
- /* [dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy] End of dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy() */
- /* */
-
- /* ############################################################## */
- /* */
- /* Step (C) Initialize PHY Configuration */
- /* */
- /* Load the required PHY configuration registers for the appropriate mode and memory configuration */
- /* */
- /* ############################################################## */
- /* */
-
- /* [phyinit_C_initPhyConfig] Start of dwc_ddrphy_phyinit_C_initPhyConfig() */
- /* */
- /* ############################################################## */
- /* TxPreDrvMode[2] = 0 */
- /* ############################################################## */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming TxSlewRate::TxPreDrvMode to 0x3 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming TxSlewRate::TxPreP to 0xf */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming TxSlewRate::TxPreN to 0xc */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for TxSlewRate::TxPreP and TxSlewRate::TxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x1005f, 0x3cf); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p0 */
- dwc_ddrphy_apb_wr(0x1015f, 0x3cf); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p0 */
- dwc_ddrphy_apb_wr(0x1105f, 0x3cf); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p0 */
- dwc_ddrphy_apb_wr(0x1115f, 0x3cf); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p0 */
- dwc_ddrphy_apb_wr(0x1205f, 0x3cf); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p0 */
- dwc_ddrphy_apb_wr(0x1215f, 0x3cf); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p0 */
- dwc_ddrphy_apb_wr(0x1305f, 0x3cf); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p0 */
- dwc_ddrphy_apb_wr(0x1315f, 0x3cf); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming TxSlewRate::TxPreDrvMode to 0x3 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming TxSlewRate::TxPreP to 0xf */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming TxSlewRate::TxPreN to 0xc */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for TxSlewRate::TxPreP and TxSlewRate::TxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x11005f, 0x3cf); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p1 */
- dwc_ddrphy_apb_wr(0x11015f, 0x3cf); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p1 */
- dwc_ddrphy_apb_wr(0x11105f, 0x3cf); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p1 */
- dwc_ddrphy_apb_wr(0x11115f, 0x3cf); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p1 */
- dwc_ddrphy_apb_wr(0x11205f, 0x3cf); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p1 */
- dwc_ddrphy_apb_wr(0x11215f, 0x3cf); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p1 */
- dwc_ddrphy_apb_wr(0x11305f, 0x3cf); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p1 */
- dwc_ddrphy_apb_wr(0x11315f, 0x3cf); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming TxSlewRate::TxPreDrvMode to 0x3 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming TxSlewRate::TxPreP to 0xf */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming TxSlewRate::TxPreN to 0xc */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for TxSlewRate::TxPreP and TxSlewRate::TxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x21005f, 0x3cf); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p2 */
- dwc_ddrphy_apb_wr(0x21015f, 0x3cf); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p2 */
- dwc_ddrphy_apb_wr(0x21105f, 0x3cf); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p2 */
- dwc_ddrphy_apb_wr(0x21115f, 0x3cf); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p2 */
- dwc_ddrphy_apb_wr(0x21205f, 0x3cf); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p2 */
- dwc_ddrphy_apb_wr(0x21215f, 0x3cf); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p2 */
- dwc_ddrphy_apb_wr(0x21305f, 0x3cf); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p2 */
- dwc_ddrphy_apb_wr(0x21315f, 0x3cf); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p2 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=0 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=0 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x6, ANIB=0 */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x55, 0x365); /* DWC_DDRPHYA_ANIB0_ATxSlewRate */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=1 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=1 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x6, ANIB=1 */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x1055, 0x365); /* DWC_DDRPHYA_ANIB1_ATxSlewRate */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=2 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=2 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x6, ANIB=2 */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x2055, 0x365); /* DWC_DDRPHYA_ANIB2_ATxSlewRate */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=3 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=3 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x6, ANIB=3 */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x3055, 0x365); /* DWC_DDRPHYA_ANIB3_ATxSlewRate */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x0, ANIB=4 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=4 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x6, ANIB=4 */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x4055, 0x65); /* DWC_DDRPHYA_ANIB4_ATxSlewRate */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x0, ANIB=5 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=5 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x6, ANIB=5 */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x5055, 0x65); /* DWC_DDRPHYA_ANIB5_ATxSlewRate */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=6 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=6 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x6, ANIB=6 */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x6055, 0x365); /* DWC_DDRPHYA_ANIB6_ATxSlewRate */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=7 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=7 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x6, ANIB=7 */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x7055, 0x365); /* DWC_DDRPHYA_ANIB7_ATxSlewRate */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=8 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=8 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x6, ANIB=8 */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x8055, 0x365); /* DWC_DDRPHYA_ANIB8_ATxSlewRate */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=9 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=9 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x6, ANIB=9 */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x9055, 0x365); /* DWC_DDRPHYA_ANIB9_ATxSlewRate */
- dwc_ddrphy_apb_wr(0x200c5, 0xb); /* DWC_DDRPHYA_MASTER0_PllCtrl2_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming PllCtrl2 to b based on DfiClk frequency = 400. */
- dwc_ddrphy_apb_wr(0x1200c5, 0x7); /* DWC_DDRPHYA_MASTER0_PllCtrl2_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming PllCtrl2 to 7 based on DfiClk frequency = 133. */
- dwc_ddrphy_apb_wr(0x2200c5, 0x7); /* DWC_DDRPHYA_MASTER0_PllCtrl2_p2 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming PllCtrl2 to 7 based on DfiClk frequency = 83. */
- /* */
- /* ############################################################## */
- /* */
- /* Program ARdPtrInitVal based on Frequency and PLL Bypass inputs */
- /* The values programmed here assume ideal properties of DfiClk */
- /* and Pclk including: */
- /* - DfiClk skew */
- /* - DfiClk jitter */
- /* - DfiClk PVT variations */
- /* - Pclk skew */
- /* - Pclk jitter */
- /* */
- /* PLL Bypassed mode: */
- /* For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 2-6 */
- /* For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-6 */
- /* */
- /* PLL Enabled mode: */
- /* For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-6 */
- /* For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 0-6 */
- /* */
- /* ############################################################## */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming ARdPtrInitVal to 0x1 */
- dwc_ddrphy_apb_wr(0x2002e, 0x1); /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming ARdPtrInitVal to 0x1 */
- dwc_ddrphy_apb_wr(0x12002e, 0x1); /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming ARdPtrInitVal to 0x1 */
- dwc_ddrphy_apb_wr(0x22002e, 0x1); /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p2 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming DqsPreambleControl::TwoTckRxDqsPre to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming DqsPreambleControl::TwoTckTxDqsPre to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming DqsPreambleControl::PositionDfeInit to 0x2 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming DqsPreambleControl::LP4TglTwoTckTxDqsPre to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming DqsPreambleControl::LP4PostambleExt to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming DqsPreambleControl::LP4SttcPreBridgeRxEn to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming DqsPreambleControl to 0x8 */
- dwc_ddrphy_apb_wr(0x20024, 0x8); /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming DbyteDllModeCntrl to 0x0 */
- dwc_ddrphy_apb_wr(0x2003a, 0x0); /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming DqsPreambleControl::TwoTckRxDqsPre to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming DqsPreambleControl::TwoTckTxDqsPre to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming DqsPreambleControl::PositionDfeInit to 0x2 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming DqsPreambleControl::LP4TglTwoTckTxDqsPre to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming DqsPreambleControl::LP4PostambleExt to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming DqsPreambleControl::LP4SttcPreBridgeRxEn to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming DqsPreambleControl to 0x8 */
- dwc_ddrphy_apb_wr(0x120024, 0x8); /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming DbyteDllModeCntrl to 0x0 */
- dwc_ddrphy_apb_wr(0x2003a, 0x0); /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming DqsPreambleControl::TwoTckRxDqsPre to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming DqsPreambleControl::TwoTckTxDqsPre to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming DqsPreambleControl::PositionDfeInit to 0x2 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming DqsPreambleControl::LP4TglTwoTckTxDqsPre to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming DqsPreambleControl::LP4PostambleExt to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming DqsPreambleControl::LP4SttcPreBridgeRxEn to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming DqsPreambleControl to 0x8 */
- dwc_ddrphy_apb_wr(0x220024, 0x8); /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p2 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming DbyteDllModeCntrl to 0x0 */
- dwc_ddrphy_apb_wr(0x2003a, 0x0); /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming ProcOdtTimeCtl to 0xa */
- dwc_ddrphy_apb_wr(0x20056, 0xa); /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming ProcOdtTimeCtl to 0xa */
- dwc_ddrphy_apb_wr(0x120056, 0xa); /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming ProcOdtTimeCtl to 0xa */
- dwc_ddrphy_apb_wr(0x220056, 0xa); /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p2 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming TxOdtDrvStren::ODTStrenP to 0x18 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming TxOdtDrvStren::ODTStrenN to 0x18 */
- dwc_ddrphy_apb_wr(0x1004d, 0x618); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p0 */
- dwc_ddrphy_apb_wr(0x1014d, 0x618); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p0 */
- dwc_ddrphy_apb_wr(0x1104d, 0x618); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p0 */
- dwc_ddrphy_apb_wr(0x1114d, 0x618); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p0 */
- dwc_ddrphy_apb_wr(0x1204d, 0x618); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p0 */
- dwc_ddrphy_apb_wr(0x1214d, 0x618); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p0 */
- dwc_ddrphy_apb_wr(0x1304d, 0x618); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p0 */
- dwc_ddrphy_apb_wr(0x1314d, 0x618); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming TxOdtDrvStren::ODTStrenP to 0x18 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming TxOdtDrvStren::ODTStrenN to 0x18 */
- dwc_ddrphy_apb_wr(0x11004d, 0x618); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p1 */
- dwc_ddrphy_apb_wr(0x11014d, 0x618); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p1 */
- dwc_ddrphy_apb_wr(0x11104d, 0x618); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p1 */
- dwc_ddrphy_apb_wr(0x11114d, 0x618); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p1 */
- dwc_ddrphy_apb_wr(0x11204d, 0x618); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p1 */
- dwc_ddrphy_apb_wr(0x11214d, 0x618); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p1 */
- dwc_ddrphy_apb_wr(0x11304d, 0x618); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p1 */
- dwc_ddrphy_apb_wr(0x11314d, 0x618); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming TxOdtDrvStren::ODTStrenP to 0x18 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming TxOdtDrvStren::ODTStrenN to 0x18 */
- dwc_ddrphy_apb_wr(0x21004d, 0x618); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p2 */
- dwc_ddrphy_apb_wr(0x21014d, 0x618); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p2 */
- dwc_ddrphy_apb_wr(0x21104d, 0x618); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p2 */
- dwc_ddrphy_apb_wr(0x21114d, 0x618); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p2 */
- dwc_ddrphy_apb_wr(0x21204d, 0x618); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p2 */
- dwc_ddrphy_apb_wr(0x21214d, 0x618); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p2 */
- dwc_ddrphy_apb_wr(0x21304d, 0x618); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p2 */
- dwc_ddrphy_apb_wr(0x21314d, 0x618); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p2 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqP to 0x38 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqN to 0x38 */
- dwc_ddrphy_apb_wr(0x10049, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p0 */
- dwc_ddrphy_apb_wr(0x10149, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p0 */
- dwc_ddrphy_apb_wr(0x11049, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p0 */
- dwc_ddrphy_apb_wr(0x11149, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p0 */
- dwc_ddrphy_apb_wr(0x12049, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p0 */
- dwc_ddrphy_apb_wr(0x12149, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p0 */
- dwc_ddrphy_apb_wr(0x13049, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p0 */
- dwc_ddrphy_apb_wr(0x13149, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqP to 0x38 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqN to 0x38 */
- dwc_ddrphy_apb_wr(0x110049, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p1 */
- dwc_ddrphy_apb_wr(0x110149, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p1 */
- dwc_ddrphy_apb_wr(0x111049, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p1 */
- dwc_ddrphy_apb_wr(0x111149, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p1 */
- dwc_ddrphy_apb_wr(0x112049, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p1 */
- dwc_ddrphy_apb_wr(0x112149, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p1 */
- dwc_ddrphy_apb_wr(0x113049, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p1 */
- dwc_ddrphy_apb_wr(0x113149, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqP to 0x38 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqN to 0x38 */
- dwc_ddrphy_apb_wr(0x210049, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p2 */
- dwc_ddrphy_apb_wr(0x210149, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p2 */
- dwc_ddrphy_apb_wr(0x211049, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p2 */
- dwc_ddrphy_apb_wr(0x211149, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p2 */
- dwc_ddrphy_apb_wr(0x212049, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p2 */
- dwc_ddrphy_apb_wr(0x212149, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p2 */
- dwc_ddrphy_apb_wr(0x213049, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p2 */
- dwc_ddrphy_apb_wr(0x213149, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p2 */
- /* [phyinit_C_initPhyConfig] Programming ATxImpedance::ADrvStrenP to 0x3 */
- /* [phyinit_C_initPhyConfig] Programming ATxImpedance::ADrvStrenN to 0x3 */
- dwc_ddrphy_apb_wr(0x43, 0x63); /* DWC_DDRPHYA_ANIB0_ATxImpedance */
- dwc_ddrphy_apb_wr(0x1043, 0x63); /* DWC_DDRPHYA_ANIB1_ATxImpedance */
- dwc_ddrphy_apb_wr(0x2043, 0x63); /* DWC_DDRPHYA_ANIB2_ATxImpedance */
- dwc_ddrphy_apb_wr(0x3043, 0x63); /* DWC_DDRPHYA_ANIB3_ATxImpedance */
- dwc_ddrphy_apb_wr(0x4043, 0x63); /* DWC_DDRPHYA_ANIB4_ATxImpedance */
- dwc_ddrphy_apb_wr(0x5043, 0x63); /* DWC_DDRPHYA_ANIB5_ATxImpedance */
- dwc_ddrphy_apb_wr(0x6043, 0x63); /* DWC_DDRPHYA_ANIB6_ATxImpedance */
- dwc_ddrphy_apb_wr(0x7043, 0x63); /* DWC_DDRPHYA_ANIB7_ATxImpedance */
- dwc_ddrphy_apb_wr(0x8043, 0x63); /* DWC_DDRPHYA_ANIB8_ATxImpedance */
- dwc_ddrphy_apb_wr(0x9043, 0x63); /* DWC_DDRPHYA_ANIB9_ATxImpedance */
- /* [phyinit_C_initPhyConfig] Programming DfiMode to 0x5 */
- dwc_ddrphy_apb_wr(0x20018, 0x5); /* DWC_DDRPHYA_MASTER0_DfiMode */
- /* [phyinit_C_initPhyConfig] Programming DfiCAMode to 0x0 */
- dwc_ddrphy_apb_wr(0x20075, 0x0); /* DWC_DDRPHYA_MASTER0_DfiCAMode */
- /* [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPd50 to 0x0 */
- /* [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPu50 to 0x0 */
- dwc_ddrphy_apb_wr(0x20050, 0x0); /* DWC_DDRPHYA_MASTER0_CalDrvStr0 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming CalUclkInfo::CalUClkTicksPer1uS to 0x190 */
- dwc_ddrphy_apb_wr(0x20008, 0x190); /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming CalUclkInfo::CalUClkTicksPer1uS to 0x85 */
- dwc_ddrphy_apb_wr(0x120008, 0x85); /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming CalUclkInfo::CalUClkTicksPer1uS to 0x53 */
- dwc_ddrphy_apb_wr(0x220008, 0x53); /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p2 */
- /* [phyinit_C_initPhyConfig] Programming CalRate::CalInterval to 0x9 */
- /* [phyinit_C_initPhyConfig] Programming CalRate::CalOnce to 0x0 */
- dwc_ddrphy_apb_wr(0x20088, 0x9); /* DWC_DDRPHYA_MASTER0_CalRate */
- /* [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInSel to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInDAC to 0x1f */
- /* [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal to 0xf8 */
- dwc_ddrphy_apb_wr(0x200b2, 0xf8); /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl::MajorModeDbyte to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl to 0x581 */
- dwc_ddrphy_apb_wr(0x10043, 0x581); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p0 */
- dwc_ddrphy_apb_wr(0x10143, 0x581); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p0 */
- dwc_ddrphy_apb_wr(0x11043, 0x581); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p0 */
- dwc_ddrphy_apb_wr(0x11143, 0x581); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p0 */
- dwc_ddrphy_apb_wr(0x12043, 0x581); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p0 */
- dwc_ddrphy_apb_wr(0x12143, 0x581); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p0 */
- dwc_ddrphy_apb_wr(0x13043, 0x581); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p0 */
- dwc_ddrphy_apb_wr(0x13143, 0x581); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Programming VrefInGlobal::GlobalVrefInSel to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Programming VrefInGlobal::GlobalVrefInDAC to 0x1f */
- /* [phyinit_C_initPhyConfig] Pstate=1, Programming VrefInGlobal to 0xf8 */
- dwc_ddrphy_apb_wr(0x1200b2, 0xf8); /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Programming DqDqsRcvCntrl::MajorModeDbyte to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Programming DqDqsRcvCntrl to 0x581 */
- dwc_ddrphy_apb_wr(0x110043, 0x581); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p1 */
- dwc_ddrphy_apb_wr(0x110143, 0x581); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p1 */
- dwc_ddrphy_apb_wr(0x111043, 0x581); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p1 */
- dwc_ddrphy_apb_wr(0x111143, 0x581); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p1 */
- dwc_ddrphy_apb_wr(0x112043, 0x581); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p1 */
- dwc_ddrphy_apb_wr(0x112143, 0x581); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p1 */
- dwc_ddrphy_apb_wr(0x113043, 0x581); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p1 */
- dwc_ddrphy_apb_wr(0x113143, 0x581); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Programming VrefInGlobal::GlobalVrefInSel to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Programming VrefInGlobal::GlobalVrefInDAC to 0x1f */
- /* [phyinit_C_initPhyConfig] Pstate=2, Programming VrefInGlobal to 0xf8 */
- dwc_ddrphy_apb_wr(0x2200b2, 0xf8); /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p2 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Programming DqDqsRcvCntrl::MajorModeDbyte to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Programming DqDqsRcvCntrl to 0x581 */
- dwc_ddrphy_apb_wr(0x210043, 0x581); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p2 */
- dwc_ddrphy_apb_wr(0x210143, 0x581); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p2 */
- dwc_ddrphy_apb_wr(0x211043, 0x581); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p2 */
- dwc_ddrphy_apb_wr(0x211143, 0x581); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p2 */
- dwc_ddrphy_apb_wr(0x212043, 0x581); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p2 */
- dwc_ddrphy_apb_wr(0x212143, 0x581); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p2 */
- dwc_ddrphy_apb_wr(0x213043, 0x581); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p2 */
- dwc_ddrphy_apb_wr(0x213143, 0x581); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p2 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming DfiFreqRatio_p0 to 0x1 */
- dwc_ddrphy_apb_wr(0x200fa, 0x1); /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming DfiFreqRatio_p1 to 0x1 */
- dwc_ddrphy_apb_wr(0x1200fa, 0x1); /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming DfiFreqRatio_p2 to 0x1 */
- dwc_ddrphy_apb_wr(0x2200fa, 0x1); /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p2 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming TristateModeCA::DisDynAdrTri_p0 to 0x1 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming TristateModeCA::DDR2TMode_p0 to 0x0 */
- dwc_ddrphy_apb_wr(0x20019, 0x5); /* DWC_DDRPHYA_MASTER0_TristateModeCA_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming TristateModeCA::DisDynAdrTri_p1 to 0x1 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=266MHz, Programming TristateModeCA::DDR2TMode_p1 to 0x0 */
- dwc_ddrphy_apb_wr(0x120019, 0x5); /* DWC_DDRPHYA_MASTER0_TristateModeCA_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming TristateModeCA::DisDynAdrTri_p2 to 0x1 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=166MHz, Programming TristateModeCA::DDR2TMode_p2 to 0x0 */
- dwc_ddrphy_apb_wr(0x220019, 0x5); /* DWC_DDRPHYA_MASTER0_TristateModeCA_p2 */
- /* [phyinit_C_initPhyConfig] Programming DfiFreqXlat* */
- dwc_ddrphy_apb_wr(0x200f0, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat0 */
- dwc_ddrphy_apb_wr(0x200f1, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat1 */
- dwc_ddrphy_apb_wr(0x200f2, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat2 */
- dwc_ddrphy_apb_wr(0x200f3, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat3 */
- dwc_ddrphy_apb_wr(0x200f4, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat4 */
- dwc_ddrphy_apb_wr(0x200f5, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat5 */
- dwc_ddrphy_apb_wr(0x200f6, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat6 */
- dwc_ddrphy_apb_wr(0x200f7, 0xf000); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat7 */
- /* [phyinit_C_initPhyConfig] Programming MasterX4Config::X4TG to 0x0 */
- dwc_ddrphy_apb_wr(0x20025, 0x0); /* DWC_DDRPHYA_MASTER0_MasterX4Config */
- /* [phyinit_C_initPhyConfig] End of dwc_ddrphy_phyinit_C_initPhyConfig() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* dwc_ddrphy_phyihunit_userCustom_customPreTrain is a user-editable function. */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- /* [phyinit_userCustom_customPreTrain] Start of dwc_ddrphy_phyinit_userCustom_customPreTrain() */
- /* [phyinit_userCustom_customPreTrain] End of dwc_ddrphy_phyinit_userCustom_customPreTrain() */
- /* [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Start of dwc_ddrphy_phyinit_D_loadIMEM (Train2D=0) */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (D) Load the 1D IMEM image */
- /* */
- /* This function loads the training firmware IMEM image into the SRAM. */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- /* */
- /* [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Programming MemResetL to 0x2 */
- if (!after_retention) {
- dwc_ddrphy_apb_wr(0x20060, 0x2);
-
- /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr3/ddr3_pmu_train_imem.incv */
-
- /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
- /* This allows the memory controller unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x50000 size 0x4000 */
- /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x4000 */
- /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
- /* This allows the firmware unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [dwc_ddrphy_phyinit_D_loadIMEM, 1D] End of dwc_ddrphy_phyinit_D_loadIMEM() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* Step (E) Set the PHY input clocks to the desired frequency for pstate 0 */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- dwc_ddrphy_phyinit_userCustom_E_setDfiClk (0);
-
- /* */
- /* [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() */
- /* [phyinit_F_loadDMEM, 1D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=0, Train2D=0) */
-
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* for test on silicon, load 1D dmem/imem here */
- #ifdef CONFIG_SPL_VSI_FW_LOADING
- load_train_1d_code();
- #else
- ddr_load_train_code(FW_1D_IMAGE);
- #endif
- ddr_dbg("start 1d train\n");
-
-
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (F) Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr3/ddr3_pmu_train_dmem.incv */
-
- /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
- /* This allows the memory controller unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x54000 size 0x36a */
- #ifdef RUN_ON_SILICON
- dwc_ddrphy_apb_wr(0x54000, 0x0);
- #else
- dwc_ddrphy_apb_wr(0x54000, 0x600);
- #endif
- dwc_ddrphy_apb_wr(0x54001, 0x0);
- dwc_ddrphy_apb_wr(0x54002, 0x0);
- dwc_ddrphy_apb_wr(0x54003, 0x640);
- dwc_ddrphy_apb_wr(0x54004, 0x2);
- dwc_ddrphy_apb_wr(0x54005, 0x0);
- dwc_ddrphy_apb_wr(0x54006, 0x140);
- dwc_ddrphy_apb_wr(0x54007, 0x2000);
- #ifdef DDR_ONE_RANK
- dwc_ddrphy_apb_wr(0x54008, 0x101);
- dwc_ddrphy_apb_wr(0x54009, 0x0);
- #else
- dwc_ddrphy_apb_wr(0x54008, 0x303);
- dwc_ddrphy_apb_wr(0x54009, 0x200);
- #endif
- dwc_ddrphy_apb_wr(0x5400a, 0x0);
- #ifdef RUN_ON_SILICON
- dwc_ddrphy_apb_wr(0x5400b, 0x31f);
- #else
- dwc_ddrphy_apb_wr(0x5400b, 0x1);
- #endif
- dwc_ddrphy_apb_wr(0x5400c, 0xc8);
- dwc_ddrphy_apb_wr(0x5400d, 0x0);
- dwc_ddrphy_apb_wr(0x5400e, 0x0);
- dwc_ddrphy_apb_wr(0x5400f, 0x0);
- dwc_ddrphy_apb_wr(0x54010, 0x0);
- dwc_ddrphy_apb_wr(0x54011, 0x0);
- dwc_ddrphy_apb_wr(0x54012, 0x1);
- dwc_ddrphy_apb_wr(0x5402f, 0xd70);
- dwc_ddrphy_apb_wr(0x54030, 0x4);
- dwc_ddrphy_apb_wr(0x54031, 0x18);
- dwc_ddrphy_apb_wr(0x5403a, 0x1221);
- dwc_ddrphy_apb_wr(0x5403b, 0x4884);
- /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x36a */
- /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
- /* This allows the firmware unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [phyinit_F_loadDMEM, 1D] End of dwc_ddrphy_phyinit_F_loadDMEM() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (G) Execute the Training Firmware */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- /* */
- /* 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and */
- /* ResetToMicro fields to 1 (all other fields should be zero). */
- /* Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- dwc_ddrphy_apb_wr(0xd0099, 0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- /* */
- /* 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. */
- dwc_ddrphy_apb_wr(0xd0099, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- /* */
- /* 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" */
- /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] Wait for the training firmware to complete. Implement timeout fucntion or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. */
- dwc_ddrphy_phyinit_userCustom_G_waitFwDone ();
-
- /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() */
- /* 4. Halt the microcontroller." */
- dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- /* [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW () */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (H) Read the Message Block results */
- /* */
- /* The procedure is as follows: */
- /* */
- /* ############################################################## */
- /* */
- /* */
- /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* */
- /* 2. Read the Firmware Message Block to obtain the results from the training. */
- /* This can be accomplished by issuing APB read commands to the DMEM addresses. */
- /* Example: */
- /* if (Train2D) */
- /* { */
- /* _read_2d_message_block_outputs_ */
- /* } */
- /* else */
- /* { */
- /* _read_1d_message_block_outputs_ */
- /* } */
- dwc_ddrphy_phyinit_userCustom_H_readMsgBlock (0);
-
- /* [dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock () */
- /* 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* 4. If training is required at another frequency, repeat the operations starting at step (E). */
- /* [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* Step (E) Set the PHY input clocks to the desired frequency for pstate 1 */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- #ifdef DDR3_SW_FFC
- dwc_ddrphy_phyinit_userCustom_E_setDfiClk (1);
-
- /* */
- /* [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() */
- /* [phyinit_F_loadDMEM, 1D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=1, Train2D=0) */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (F) Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr3/ddr3_pmu_train_dmem.incv */
-
- /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
- /* This allows the memory controller unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x54000 size 0x36a */
- #ifdef RUN_ON_SILICON
- dwc_ddrphy_apb_wr(0x54000, 0x0);
- #else
- dwc_ddrphy_apb_wr(0x54000, 0x600);
- #endif
- dwc_ddrphy_apb_wr(0x54001, 0x0);
- dwc_ddrphy_apb_wr(0x54002, 0x1);
- dwc_ddrphy_apb_wr(0x54003, 0x214);
- dwc_ddrphy_apb_wr(0x54004, 0x2);
- dwc_ddrphy_apb_wr(0x54005, 0x0);
- dwc_ddrphy_apb_wr(0x54006, 0x140);
- dwc_ddrphy_apb_wr(0x54007, 0x2000);
- #ifdef DDR_ONE_RANK
- dwc_ddrphy_apb_wr(0x54008, 0x101);
- dwc_ddrphy_apb_wr(0x54009, 0x0);
- #else
- dwc_ddrphy_apb_wr(0x54008, 0x303);
- dwc_ddrphy_apb_wr(0x54009, 0x200);
- #endif
- dwc_ddrphy_apb_wr(0x5400a, 0x0);
- #ifdef RUN_ON_SILICON
- dwc_ddrphy_apb_wr(0x5400b, 0x21f);
- #else
- dwc_ddrphy_apb_wr(0x5400b, 0x1);
- #endif
- dwc_ddrphy_apb_wr(0x5400c, 0xc8);
- dwc_ddrphy_apb_wr(0x5400d, 0x0);
- dwc_ddrphy_apb_wr(0x5400e, 0x0);
- dwc_ddrphy_apb_wr(0x5400f, 0x0);
- dwc_ddrphy_apb_wr(0x54010, 0x0);
- dwc_ddrphy_apb_wr(0x54011, 0x0);
- dwc_ddrphy_apb_wr(0x54012, 0x1);
- dwc_ddrphy_apb_wr(0x5402f, 0x930);
- dwc_ddrphy_apb_wr(0x54030, 0x4);
- dwc_ddrphy_apb_wr(0x54031, 0x8);
- dwc_ddrphy_apb_wr(0x5403a, 0x1221);
- dwc_ddrphy_apb_wr(0x5403b, 0x4884);
- /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x36a */
- /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
- /* This allows the firmware unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [phyinit_F_loadDMEM, 1D] End of dwc_ddrphy_phyinit_F_loadDMEM() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (G) Execute the Training Firmware */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- /* */
- /* 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and */
- /* ResetToMicro fields to 1 (all other fields should be zero). */
- /* Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- dwc_ddrphy_apb_wr(0xd0099, 0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- /* */
- /* 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. */
- dwc_ddrphy_apb_wr(0xd0099, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- /* */
- /* 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" */
- /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] Wait for the training firmware to complete. Implement timeout fucntion or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. */
- dwc_ddrphy_phyinit_userCustom_G_waitFwDone ();
-
- /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() */
- /* 4. Halt the microcontroller." */
- dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- /* [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW () */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (H) Read the Message Block results */
- /* */
- /* The procedure is as follows: */
- /* */
- /* ############################################################## */
- /* */
- /* */
- /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* */
- /* 2. Read the Firmware Message Block to obtain the results from the training. */
- /* This can be accomplished by issuing APB read commands to the DMEM addresses. */
- /* Example: */
- /* if (Train2D) */
- /* { */
- /* _read_2d_message_block_outputs_ */
- /* } */
- /* else */
- /* { */
- /* _read_1d_message_block_outputs_ */
- /* } */
- dwc_ddrphy_phyinit_userCustom_H_readMsgBlock (0);
-
- /* [dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock () */
- /* 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* 4. If training is required at another frequency, repeat the operations starting at step (E). */
- /* [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* Step (E) Set the PHY input clocks to the desired frequency for pstate 2 */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- dwc_ddrphy_phyinit_userCustom_E_setDfiClk (2);
-
- /* */
- /* [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() */
- /* [phyinit_F_loadDMEM, 1D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=2, Train2D=0) */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (F) Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr3/ddr3_pmu_train_dmem.incv */
-
- /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
- /* This allows the memory controller unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x54000 size 0x36a */
- #ifdef RUN_ON_SILICON
- dwc_ddrphy_apb_wr(0x54000, 0x0);
- #else
- dwc_ddrphy_apb_wr(0x54000, 0x600);
- #endif
- dwc_ddrphy_apb_wr(0x54001, 0x0);
- dwc_ddrphy_apb_wr(0x54002, 0x2);
- dwc_ddrphy_apb_wr(0x54003, 0x14c);
- dwc_ddrphy_apb_wr(0x54004, 0x2);
- dwc_ddrphy_apb_wr(0x54005, 0x0);
- dwc_ddrphy_apb_wr(0x54006, 0x140);
- dwc_ddrphy_apb_wr(0x54007, 0x2000);
- #ifdef DDR_ONE_RANK
- dwc_ddrphy_apb_wr(0x54008, 0x101);
- dwc_ddrphy_apb_wr(0x54009, 0x0);
- #else
- dwc_ddrphy_apb_wr(0x54008, 0x303);
- dwc_ddrphy_apb_wr(0x54009, 0x200);
- #endif
- dwc_ddrphy_apb_wr(0x5400a, 0x0);
- #ifdef RUN_ON_SILICON
- dwc_ddrphy_apb_wr(0x5400b, 0x21f);
- #else
- dwc_ddrphy_apb_wr(0x5400b, 0x1);
- #endif
- dwc_ddrphy_apb_wr(0x5400c, 0xc8);
- dwc_ddrphy_apb_wr(0x5400d, 0x0);
- dwc_ddrphy_apb_wr(0x5400e, 0x0);
- dwc_ddrphy_apb_wr(0x5400f, 0x0);
- dwc_ddrphy_apb_wr(0x54010, 0x0);
- dwc_ddrphy_apb_wr(0x54011, 0x0);
- dwc_ddrphy_apb_wr(0x54012, 0x1);
- dwc_ddrphy_apb_wr(0x5402f, 0x520);
- dwc_ddrphy_apb_wr(0x54030, 0x4);
- dwc_ddrphy_apb_wr(0x54031, 0x0);
- dwc_ddrphy_apb_wr(0x5403a, 0x1221);
- dwc_ddrphy_apb_wr(0x5403b, 0x4884);
- /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x36a */
- /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
- /* This allows the firmware unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [phyinit_F_loadDMEM, 1D] End of dwc_ddrphy_phyinit_F_loadDMEM() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (G) Execute the Training Firmware */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- /* */
- /* 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and */
- /* ResetToMicro fields to 1 (all other fields should be zero). */
- /* Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- dwc_ddrphy_apb_wr(0xd0099, 0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- /* */
- /* 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. */
- dwc_ddrphy_apb_wr(0xd0099, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- /* */
- /* 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" */
- /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] Wait for the training firmware to complete. Implement timeout fucntion or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. */
- dwc_ddrphy_phyinit_userCustom_G_waitFwDone ();
-
- /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() */
- /* 4. Halt the microcontroller." */
- dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- /* [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW () */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (H) Read the Message Block results */
- /* */
- /* The procedure is as follows: */
- /* */
- /* ############################################################## */
- /* */
- /* */
- /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* */
- /* 2. Read the Firmware Message Block to obtain the results from the training. */
- /* This can be accomplished by issuing APB read commands to the DMEM addresses. */
- /* Example: */
- /* if (Train2D) */
- /* { */
- /* _read_2d_message_block_outputs_ */
- /* } */
- /* else */
- /* { */
- /* _read_1d_message_block_outputs_ */
- /* } */
- dwc_ddrphy_phyinit_userCustom_H_readMsgBlock (0);
-
- /* [dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock () */
- /* 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* 4. If training is required at another frequency, repeat the operations starting at step (E). */
- /* [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() */
- /* [phyinit_I_loadPIEImage] Start of dwc_ddrphy_phyinit_I_loadPIEImage() */
- #endif /* DDR3_SW_FFC */
- ddr_dbg("1D training done!!!!\n");
- } /* !after_retention */else {/* after_retention */
- /* restore_1d2d_trained_csr_ddr3_p0(SAVE_DDRPHY_TRAIN_ADDR); */
- restore_1d2d_trained_csr_ddr3_p012(SAVE_DDRPHY_TRAIN_ADDR);
- } /* after_retention */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (I) Load PHY Init Engine Image */
- /* */
- /* Load the PHY Initialization Engine memory with the provided initialization sequence. */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* */
- /* Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
- /* This allows the memory controller unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [phyinit_I_loadPIEImage] Programming PIE Production Code */
- dwc_ddrphy_apb_wr(0x90000, 0x10); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */
- dwc_ddrphy_apb_wr(0x90001, 0x400); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */
- dwc_ddrphy_apb_wr(0x90002, 0x10e); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */
- dwc_ddrphy_apb_wr(0x90003, 0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */
- dwc_ddrphy_apb_wr(0x90004, 0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */
- dwc_ddrphy_apb_wr(0x90005, 0x8); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */
- dwc_ddrphy_apb_wr(0x90029, 0xb); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */
- dwc_ddrphy_apb_wr(0x9002a, 0x480); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */
- dwc_ddrphy_apb_wr(0x9002b, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */
- dwc_ddrphy_apb_wr(0x9002c, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */
- dwc_ddrphy_apb_wr(0x9002d, 0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */
- dwc_ddrphy_apb_wr(0x9002e, 0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */
- dwc_ddrphy_apb_wr(0x9002f, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */
- dwc_ddrphy_apb_wr(0x90030, 0x478); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */
- dwc_ddrphy_apb_wr(0x90031, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */
- dwc_ddrphy_apb_wr(0x90032, 0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */
- dwc_ddrphy_apb_wr(0x90033, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */
- dwc_ddrphy_apb_wr(0x90034, 0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */
- dwc_ddrphy_apb_wr(0x90035, 0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */
- dwc_ddrphy_apb_wr(0x90036, 0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */
- dwc_ddrphy_apb_wr(0x90037, 0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */
- dwc_ddrphy_apb_wr(0x90038, 0x44); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */
- dwc_ddrphy_apb_wr(0x90039, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */
- dwc_ddrphy_apb_wr(0x9003a, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */
- dwc_ddrphy_apb_wr(0x9003b, 0x14f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */
- dwc_ddrphy_apb_wr(0x9003c, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */
- dwc_ddrphy_apb_wr(0x9003d, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */
- dwc_ddrphy_apb_wr(0x9003e, 0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */
- dwc_ddrphy_apb_wr(0x9003f, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */
- dwc_ddrphy_apb_wr(0x90040, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */
- dwc_ddrphy_apb_wr(0x90041, 0x4f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */
- dwc_ddrphy_apb_wr(0x90042, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */
- dwc_ddrphy_apb_wr(0x90043, 0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */
- dwc_ddrphy_apb_wr(0x90044, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */
- dwc_ddrphy_apb_wr(0x90045, 0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */
- dwc_ddrphy_apb_wr(0x90046, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */
- dwc_ddrphy_apb_wr(0x90047, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */
- dwc_ddrphy_apb_wr(0x90048, 0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */
- dwc_ddrphy_apb_wr(0x90049, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */
- dwc_ddrphy_apb_wr(0x9004a, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */
- dwc_ddrphy_apb_wr(0x9004b, 0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */
- dwc_ddrphy_apb_wr(0x9004c, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */
- dwc_ddrphy_apb_wr(0x9004d, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */
- dwc_ddrphy_apb_wr(0x9004e, 0x45a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */
- dwc_ddrphy_apb_wr(0x9004f, 0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */
- dwc_ddrphy_apb_wr(0x90050, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */
- dwc_ddrphy_apb_wr(0x90051, 0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */
- dwc_ddrphy_apb_wr(0x90052, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */
- dwc_ddrphy_apb_wr(0x90053, 0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */
- dwc_ddrphy_apb_wr(0x90054, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */
- dwc_ddrphy_apb_wr(0x90055, 0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */
- dwc_ddrphy_apb_wr(0x90056, 0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */
- dwc_ddrphy_apb_wr(0x90057, 0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */
- dwc_ddrphy_apb_wr(0x90058, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */
- dwc_ddrphy_apb_wr(0x90059, 0x40c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */
- dwc_ddrphy_apb_wr(0x9005a, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */
- dwc_ddrphy_apb_wr(0x9005b, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */
- dwc_ddrphy_apb_wr(0x9005c, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */
- dwc_ddrphy_apb_wr(0x9005d, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */
- dwc_ddrphy_apb_wr(0x9005e, 0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */
- dwc_ddrphy_apb_wr(0x9005f, 0x4040); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */
- dwc_ddrphy_apb_wr(0x90060, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */
- dwc_ddrphy_apb_wr(0x90061, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */
- dwc_ddrphy_apb_wr(0x90062, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */
- dwc_ddrphy_apb_wr(0x90063, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */
- dwc_ddrphy_apb_wr(0x90064, 0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */
- dwc_ddrphy_apb_wr(0x90065, 0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */
- dwc_ddrphy_apb_wr(0x90066, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */
- dwc_ddrphy_apb_wr(0x90067, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */
- dwc_ddrphy_apb_wr(0x90068, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */
- dwc_ddrphy_apb_wr(0x90069, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */
- dwc_ddrphy_apb_wr(0x9006a, 0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */
- dwc_ddrphy_apb_wr(0x9006b, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */
- dwc_ddrphy_apb_wr(0x9006c, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */
- dwc_ddrphy_apb_wr(0x9006d, 0x78); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */
- dwc_ddrphy_apb_wr(0x9006e, 0x549); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */
- dwc_ddrphy_apb_wr(0x9006f, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */
- dwc_ddrphy_apb_wr(0x90070, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */
- dwc_ddrphy_apb_wr(0x90071, 0xd49); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */
- dwc_ddrphy_apb_wr(0x90072, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */
- dwc_ddrphy_apb_wr(0x90073, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */
- dwc_ddrphy_apb_wr(0x90074, 0x94a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */
- dwc_ddrphy_apb_wr(0x90075, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */
- dwc_ddrphy_apb_wr(0x90076, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */
- dwc_ddrphy_apb_wr(0x90077, 0x441); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */
- dwc_ddrphy_apb_wr(0x90078, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */
- dwc_ddrphy_apb_wr(0x90079, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */
- dwc_ddrphy_apb_wr(0x9007a, 0x42); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */
- dwc_ddrphy_apb_wr(0x9007b, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */
- dwc_ddrphy_apb_wr(0x9007c, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */
- dwc_ddrphy_apb_wr(0x9007d, 0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */
- dwc_ddrphy_apb_wr(0x9007e, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */
- dwc_ddrphy_apb_wr(0x9007f, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */
- dwc_ddrphy_apb_wr(0x90080, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */
- dwc_ddrphy_apb_wr(0x90081, 0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */
- dwc_ddrphy_apb_wr(0x90082, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */
- dwc_ddrphy_apb_wr(0x90083, 0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */
- dwc_ddrphy_apb_wr(0x90084, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */
- dwc_ddrphy_apb_wr(0x90085, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */
- dwc_ddrphy_apb_wr(0x90086, 0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */
- dwc_ddrphy_apb_wr(0x90087, 0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */
- dwc_ddrphy_apb_wr(0x90088, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */
- dwc_ddrphy_apb_wr(0x90089, 0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */
- dwc_ddrphy_apb_wr(0x9008a, 0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */
- dwc_ddrphy_apb_wr(0x9008b, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */
- dwc_ddrphy_apb_wr(0x9008c, 0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */
- dwc_ddrphy_apb_wr(0x9008d, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */
- dwc_ddrphy_apb_wr(0x9008e, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */
- dwc_ddrphy_apb_wr(0x9008f, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */
- dwc_ddrphy_apb_wr(0x90090, 0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */
- dwc_ddrphy_apb_wr(0x90091, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */
- dwc_ddrphy_apb_wr(0x90092, 0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */
- dwc_ddrphy_apb_wr(0x90093, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */
- dwc_ddrphy_apb_wr(0x90094, 0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */
- dwc_ddrphy_apb_wr(0x90095, 0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */
- dwc_ddrphy_apb_wr(0x90096, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */
- dwc_ddrphy_apb_wr(0x90097, 0x58); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */
- dwc_ddrphy_apb_wr(0x90098, 0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */
- dwc_ddrphy_apb_wr(0x90099, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */
- dwc_ddrphy_apb_wr(0x9009a, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */
- dwc_ddrphy_apb_wr(0x9009b, 0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */
- dwc_ddrphy_apb_wr(0x9009c, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */
- dwc_ddrphy_apb_wr(0x9009d, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */
- dwc_ddrphy_apb_wr(0x9009e, 0x7); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */
- dwc_ddrphy_apb_wr(0x9009f, 0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */
- dwc_ddrphy_apb_wr(0x900a0, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */
- dwc_ddrphy_apb_wr(0x900a1, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */
- dwc_ddrphy_apb_wr(0x900a2, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */
- dwc_ddrphy_apb_wr(0x900a3, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */
- dwc_ddrphy_apb_wr(0x900a4, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */
- dwc_ddrphy_apb_wr(0x900a5, 0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */
- dwc_ddrphy_apb_wr(0x900a6, 0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */
- dwc_ddrphy_apb_wr(0x900a7, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */
- dwc_ddrphy_apb_wr(0x900a8, 0x8138); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */
- dwc_ddrphy_apb_wr(0x900a9, 0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */
- dwc_ddrphy_apb_wr(0x900aa, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */
- dwc_ddrphy_apb_wr(0x900ab, 0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */
- dwc_ddrphy_apb_wr(0x900ac, 0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */
- dwc_ddrphy_apb_wr(0x900ad, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */
- dwc_ddrphy_apb_wr(0x900ae, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */
- dwc_ddrphy_apb_wr(0x900af, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */
- dwc_ddrphy_apb_wr(0x900b0, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */
- dwc_ddrphy_apb_wr(0x900b1, 0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */
- dwc_ddrphy_apb_wr(0x900b2, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */
- dwc_ddrphy_apb_wr(0x900b3, 0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */
- dwc_ddrphy_apb_wr(0x900b4, 0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */
- dwc_ddrphy_apb_wr(0x900b5, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */
- dwc_ddrphy_apb_wr(0x900b6, 0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */
- dwc_ddrphy_apb_wr(0x900b7, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */
- dwc_ddrphy_apb_wr(0x900b8, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */
- dwc_ddrphy_apb_wr(0x900b9, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */
- dwc_ddrphy_apb_wr(0x900ba, 0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */
- dwc_ddrphy_apb_wr(0x900bb, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */
- dwc_ddrphy_apb_wr(0x900bc, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */
- dwc_ddrphy_apb_wr(0x900bd, 0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */
- dwc_ddrphy_apb_wr(0x900be, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */
- dwc_ddrphy_apb_wr(0x900bf, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */
- dwc_ddrphy_apb_wr(0x900c0, 0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */
- dwc_ddrphy_apb_wr(0x900c1, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */
- dwc_ddrphy_apb_wr(0x900c2, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */
- dwc_ddrphy_apb_wr(0x900c3, 0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */
- dwc_ddrphy_apb_wr(0x900c4, 0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */
- dwc_ddrphy_apb_wr(0x900c5, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */
- dwc_ddrphy_apb_wr(0x900c6, 0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */
- dwc_ddrphy_apb_wr(0x900c7, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */
- dwc_ddrphy_apb_wr(0x900c8, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */
- dwc_ddrphy_apb_wr(0x900c9, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */
- dwc_ddrphy_apb_wr(0x900ca, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */
- dwc_ddrphy_apb_wr(0x900cb, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */
- dwc_ddrphy_apb_wr(0x900cc, 0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */
- dwc_ddrphy_apb_wr(0x900cd, 0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */
- dwc_ddrphy_apb_wr(0x90006, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */
- dwc_ddrphy_apb_wr(0x90007, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */
- dwc_ddrphy_apb_wr(0x90008, 0x8); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */
- dwc_ddrphy_apb_wr(0x90009, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */
- dwc_ddrphy_apb_wr(0x9000a, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */
- dwc_ddrphy_apb_wr(0x9000b, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */
- dwc_ddrphy_apb_wr(0xd00e7, 0x400); /* DWC_DDRPHYA_APBONLY0_SequencerOverride */
- dwc_ddrphy_apb_wr(0x90017, 0x0); /* DWC_DDRPHYA_INITENG0_StartVector0b0 */
- dwc_ddrphy_apb_wr(0x90026, 0x2c); /* DWC_DDRPHYA_INITENG0_StartVector0b15 */
- /* [phyinit_I_loadPIEImage] Pstate=0, Memclk=800MHz, Programming Seq0BDLY0 to 0x32 */
- dwc_ddrphy_apb_wr(0x2000b, 0x32); /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */
- /* [phyinit_I_loadPIEImage] Pstate=0, Memclk=800MHz, Programming Seq0BDLY1 to 0x64 */
- dwc_ddrphy_apb_wr(0x2000c, 0x64); /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */
- /* [phyinit_I_loadPIEImage] Pstate=0, Memclk=800MHz, Programming Seq0BDLY2 to 0x3e8 */
- dwc_ddrphy_apb_wr(0x2000d, 0x3e8); /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */
- /* [phyinit_I_loadPIEImage] Pstate=0, Memclk=800MHz, Programming Seq0BDLY3 to 0x2c */
- dwc_ddrphy_apb_wr(0x2000e, 0x2c); /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */
- /* [phyinit_I_loadPIEImage] Pstate=1, Memclk=266MHz, Programming Seq0BDLY0 to 0x10 */
- dwc_ddrphy_apb_wr(0x12000b, 0x10); /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p1 */
- /* [phyinit_I_loadPIEImage] Pstate=1, Memclk=266MHz, Programming Seq0BDLY1 to 0x21 */
- dwc_ddrphy_apb_wr(0x12000c, 0x21); /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p1 */
- /* [phyinit_I_loadPIEImage] Pstate=1, Memclk=266MHz, Programming Seq0BDLY2 to 0x14c */
- dwc_ddrphy_apb_wr(0x12000d, 0x14c); /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p1 */
- /* [phyinit_I_loadPIEImage] Pstate=1, Memclk=266MHz, Programming Seq0BDLY3 to 0x10 */
- dwc_ddrphy_apb_wr(0x12000e, 0x10); /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p1 */
- /* [phyinit_I_loadPIEImage] Pstate=2, Memclk=166MHz, Programming Seq0BDLY0 to 0xa */
- dwc_ddrphy_apb_wr(0x22000b, 0xa); /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p2 */
- /* [phyinit_I_loadPIEImage] Pstate=2, Memclk=166MHz, Programming Seq0BDLY1 to 0x14 */
- dwc_ddrphy_apb_wr(0x22000c, 0x14); /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p2 */
- /* [phyinit_I_loadPIEImage] Pstate=2, Memclk=166MHz, Programming Seq0BDLY2 to 0xcf */
- dwc_ddrphy_apb_wr(0x22000d, 0xcf); /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p2 */
- /* [phyinit_I_loadPIEImage] Pstate=2, Memclk=166MHz, Programming Seq0BDLY3 to 0x10 */
- dwc_ddrphy_apb_wr(0x22000e, 0x10); /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p2 */
- dwc_ddrphy_apb_wr(0x9000c, 0x0); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */
- dwc_ddrphy_apb_wr(0x9000d, 0x173); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */
- dwc_ddrphy_apb_wr(0x9000e, 0x60); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */
- dwc_ddrphy_apb_wr(0x9000f, 0x6110); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */
- dwc_ddrphy_apb_wr(0x90010, 0x2152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */
- dwc_ddrphy_apb_wr(0x90011, 0xdfbd); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */
- dwc_ddrphy_apb_wr(0x90012, 0xffff); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */
- dwc_ddrphy_apb_wr(0x90013, 0x6152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */
- /* Disabling Ucclk (PMU) and Hclk (training hardware) */
- dwc_ddrphy_apb_wr(0xc0080, 0x0); /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */
- /* Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [phyinit_I_loadPIEImage] End of dwc_ddrphy_phyinit_I_loadPIEImage() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* dwc_ddrphy_phyinit_userCustom_customPostTrain is a user-editable function. */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- dwc_ddrphy_phyinit_userCustom_customPostTrain ();
-
- /* [dwc_ddrphy_phyinit_userCustom_customPostTrain] End of dwc_ddrphy_phyinit_userCustom_customPostTrain() */
- /* [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] Start of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (J) Initialize the PHY to Mission Mode through DFI Initialization */
- /* */
- /* Initialize the PHY to mission mode as follows: */
- /* */
- /* 1. Set the PHY input clocks to the desired frequency. */
- /* 2. Initialize the PHY to mission mode by performing DFI Initialization. */
- /* Please see the DFI specification for more information. See the DFI frequency bus encoding in section <XXX>. */
- /* Note: The PHY training firmware initializes the DRAM state. if skip */
- /* training is used, the DRAM state is not initialized. */
- /* */
- /* ############################################################## */
- /* */
- dwc_ddrphy_phyinit_userCustom_J_enterMissionMode ();
-
- /* */
- /* [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] End of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode() */
- /* [dwc_ddrphy_phyinit_sequence] End of dwc_ddrphy_phyinit_sequence() */
- /* [dwc_ddrphy_phyinit_main] End of dwc_ddrphy_phyinit_main() */
-
- /* ---------------------------------------------------------------------- */
- /* save 1d2d training CSR */
- /* ---------------------------------------------------------------------- */
- if (!after_retention) {
- save_1d2d_trained_csr_ddr3_p012(SAVE_DDRPHY_TRAIN_ADDR);
- }
-}
diff --git a/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_sw_fast_freq_chg_fw09.c b/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_sw_fast_freq_chg_fw09.c
deleted file mode 100644
index dae11ca..0000000
--- a/board/freescale/imx8mm_val/ddr/ddr3l/ddr3_sw_fast_freq_chg_fw09.c
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- * Copyright 2018 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/ddr.h>
-#include <asm/arch/clock.h>
-#include "anamix_common.h"
-#include "ddr3_define.h"
-
-void umctl2_cfg(void)
-{
-#ifdef DDR_ONE_RANK
- reg32_write(DDRC_MSTR(0), 0x81040001);
-#else
- reg32_write(DDRC_MSTR(0), 0x83040001);
-#endif
-
- reg32_write(DDRC_PWRCTL(0), 0x000000a8);
- reg32_write(DDRC_PWRTMG(0), 0x00532203);
-
- reg32_write(DDRC_RFSHCTL0(0), 0x00203020);
- reg32_write(DDRC_RFSHCTL1(0), 0x0001000d);
- reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
- reg32_write(DDRC_RFSHTMG(0), 0x0061008c);
- reg32_write(DDRC_CRCPARCTL0(0), 0x00000000);
- reg32_write(DDRC_CRCPARCTL1(0), 0x00000000);
- reg32_write(DDRC_INIT0(0), 0xc0030002);
- reg32_write(DDRC_INIT1(0), 0x0001000b);
- reg32_write(DDRC_INIT2(0), 0x00006303);
- reg32_write(DDRC_INIT3(0), 0x0d700004);/* MR1, MR0 */
- reg32_write(DDRC_INIT4(0), 0x00180000);/* MR2 */
- reg32_write(DDRC_INIT5(0), 0x00090071);
- reg32_write(DDRC_INIT6(0), 0x00000000);
- reg32_write(DDRC_INIT7(0), 0x00000000);
- reg32_write(DDRC_DIMMCTL(0), 0x00000032); /* [1] dimm_addr_mirr_en, it will effect the MRS if use umctl2 to initi dram. */
- reg32_write(DDRC_RANKCTL(0), 0x00000ee5);
- reg32_write(DDRC_DRAMTMG0(0), 0x0c101a0e);
- reg32_write(DDRC_DRAMTMG1(0), 0x000a0314);
- reg32_write(DDRC_DRAMTMG2(0), 0x04060509);
- reg32_write(DDRC_DRAMTMG3(0), 0x00002006);
- reg32_write(DDRC_DRAMTMG4(0), 0x06020306);
- reg32_write(DDRC_DRAMTMG5(0), 0x0b060202);
- reg32_write(DDRC_DRAMTMG6(0), 0x060a0009);
- reg32_write(DDRC_DRAMTMG7(0), 0x0000060b);
- reg32_write(DDRC_DRAMTMG8(0), 0x01017c0a);
- reg32_write(DDRC_DRAMTMG9(0), 0x4000000e);
- reg32_write(DDRC_DRAMTMG10(0), 0x00070803);
- reg32_write(DDRC_DRAMTMG11(0), 0x0101000b);
- reg32_write(DDRC_DRAMTMG12(0), 0x00000000);
- reg32_write(DDRC_DRAMTMG13(0), 0x5d000000);
- reg32_write(DDRC_DRAMTMG14(0), 0x00000b39);
- reg32_write(DDRC_DRAMTMG15(0), 0x80000000);
- reg32_write(DDRC_DRAMTMG17(0), 0x00f1006a);
- reg32_write(DDRC_ZQCTL0(0), 0x50800020);
- reg32_write(DDRC_ZQCTL1(0), 0x00000070);
- reg32_write(DDRC_ZQCTL2(0), 0x00000000);
- reg32_write(DDRC_DFITMG0(0), 0x03868203);
- reg32_write(DDRC_DFITMG1(0), 0x00020103);
- reg32_write(DDRC_DFILPCFG0(0), 0x07713021);
- reg32_write(DDRC_DFILPCFG1(0), 0x00000010);
- reg32_write(DDRC_DFIUPD0(0), 0xe0400018);
- reg32_write(DDRC_DFIUPD1(0), 0x0005003c);
- reg32_write(DDRC_DFIUPD2(0), 0x80000000);
- reg32_write(DDRC_DFIMISC(0), 0x00000011);
- reg32_write(DDRC_DFITMG2(0), 0x00000603);
- reg32_write(DDRC_DFITMG3(0), 0x00000001);
- reg32_write(DDRC_DBICTL(0), 0x00000001);
- reg32_write(DDRC_DFIPHYMSTR(0), 0x00000000);
-
- /* My test mapping in this test case, for 8Gb,(two 4Gb, x16 DDR3) (col addr:10 bits row addr: 15 bits bank addr: 3bits 2 ranks) */
- /* MEMC_BURST_LENGTH = 8 */
- /* ----------------------------------------------------------------------------------------------------------------------------------- */
- /* AXI add: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (MEM_DATWIDTH=64) */
- /* AXI add: 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (MEM_DATWIDTH=32) *** */
- /* AXI add: 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (MEM_DATWIDTH=16) */
- /* ----------------------------------------------------------------------------------------------------------------------------------- */
- /* HIF add: 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - */
- /* ----------------------------------------------------------------------------------------------------------------------------------- */
- /* **** for Full DQ bus width (X32) **** */
- /* cs r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 b2 b1 b0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 */
- /* Int base 6 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 4 3 2 9 8 7 6 5 4 3 2 - */
- /* p Value 22 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 0 0 0 0 0 0 0 0 - */
- /* ----------------------------------------------------------------------------------------------------------------------------------- */
-
- reg32_write(DDRC_ADDRMAP0(0), 0x00000016); /* [4:0] cs-bit0: 6+22=28; [12:8] cs-bit1: 7+0 */
- reg32_write(DDRC_ADDRMAP1(0), 0x00080808); /* [5:0] bank b0: 2+8; [13:8] b1: P3+8 ; [21:16] b2: 4+8 */
- reg32_write(DDRC_ADDRMAP2(0), 0x00000000); /* [3:0] col-b2: 2; [11:8] col-b3: 3; [19:16] col-b4: 4 ; [27:24] col-b5: 5 */
- reg32_write(DDRC_ADDRMAP3(0), 0x00000000); /* [3:0] col-b6: 6; [11:8] col-b7: 7; [19:16] col-b8: 8 ; [27:24] col-b9: 9 */
- reg32_write(DDRC_ADDRMAP4(0), 0x00001f1f); /* col-b10, col-b11 not used */
- reg32_write(DDRC_ADDRMAP5(0), 0x07070707); /* [3:0] row-b0: 6; [11:8] row-b1: 7; [19:16] row-b2_b10 ; [27:24] row-b11: 17 */
- reg32_write(DDRC_ADDRMAP6(0), 0x0f070707); /* [3:0] row-b12:18; [11:8] row-b13: 19; [19:16] row-b14:20 */
- reg32_write(DDRC_ADDRMAP7(0), 0x00000f0f);
- reg32_write(DDRC_ADDRMAP8(0), 0x00000000); /* [5:0] bg-b0; [13:8]bg-b1 */
- reg32_write(DDRC_ADDRMAP9(0), 0x0a020b06); /* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
- reg32_write(DDRC_ADDRMAP10(0), 0x0a0a0a0a);/* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
- reg32_write(DDRC_ADDRMAP11(0), 0x00000000);
-
-
- reg32_write(DDRC_ODTCFG(0), 0x041d0f5c);
- reg32_write(DDRC_ODTMAP(0), 0x00000201);
- reg32_write(DDRC_SCHED(0), 0x7ab50b07);
- reg32_write(DDRC_SCHED1(0), 0x00000022);
- reg32_write(DDRC_PERFHPR1(0), 0x7b00665e);
- reg32_write(DDRC_PERFLPR1(0), 0x2b00c4e1);
- reg32_write(DDRC_PERFWR1(0), 0xb700c9fe);
- reg32_write(DDRC_DBG0(0), 0x00000017);
- reg32_write(DDRC_DBG1(0), 0x00000000);
- reg32_write(DDRC_DBGCMD(0), 0x00000000);
- reg32_write(DDRC_SWCTL(0), 0x00000001);
- reg32_write(DDRC_POISONCFG(0), 0x00010000);
- reg32_write(DDRC_PCCFG(0), 0x00000100);
- reg32_write(DDRC_PCFGR_0(0), 0x00003051);
- reg32_write(DDRC_PCFGW_0(0), 0x000061d2);
- reg32_write(DDRC_PCTRL_0(0), 0x00000001);
- reg32_write(DDRC_PCFGQOS0_0(0), 0x02100b04);
- reg32_write(DDRC_PCFGQOS1_0(0), 0x003f0353);
- reg32_write(DDRC_PCFGWQOS0_0(0), 0x00000002);
- reg32_write(DDRC_PCFGWQOS1_0(0), 0x000005fd);
-}
-
-void umctl2_freq1_cfg(void)
-{
- reg32_write(DDRC_FREQ1_RFSHCTL0(0), 0x00d19034);
- reg32_write(DDRC_FREQ1_RFSHTMG(0), 0x0040805e);
- reg32_write(DDRC_FREQ1_INIT3(0), 0x09300004);
- reg32_write(DDRC_FREQ1_INIT4(0), 0x00080000);
- reg32_write(DDRC_FREQ1_INIT6(0), 0x00000000);
- reg32_write(DDRC_FREQ1_INIT7(0), 0x00000000);
- reg32_write(DDRC_FREQ1_DRAMTMG0(0), 0x090e110a);
- reg32_write(DDRC_FREQ1_DRAMTMG1(0), 0x0007020e);
- reg32_write(DDRC_FREQ1_DRAMTMG2(0), 0x03040407);
- reg32_write(DDRC_FREQ1_DRAMTMG3(0), 0x00002006);
- reg32_write(DDRC_FREQ1_DRAMTMG4(0), 0x04020304); /* tRP=6 --> 7 */
- reg32_write(DDRC_FREQ1_DRAMTMG5(0), 0x09030202);
- reg32_write(DDRC_FREQ1_DRAMTMG6(0), 0x0c020000);
- reg32_write(DDRC_FREQ1_DRAMTMG7(0), 0x00000309);
- reg32_write(DDRC_FREQ1_DRAMTMG8(0), 0x01010a06);
- reg32_write(DDRC_FREQ1_DRAMTMG9(0), 0x00000003);
- reg32_write(DDRC_FREQ1_DRAMTMG10(0), 0x00090906);
- reg32_write(DDRC_FREQ1_DRAMTMG11(0), 0x01010011);
- reg32_write(DDRC_FREQ1_DRAMTMG12(0), 0x00000000);
- reg32_write(DDRC_FREQ1_DRAMTMG13(0), 0x40000000);
- reg32_write(DDRC_FREQ1_DRAMTMG14(0), 0x000000f3);
- reg32_write(DDRC_FREQ1_DRAMTMG15(0), 0x80000000);
- reg32_write(DDRC_FREQ1_DRAMTMG17(0), 0x001a0046);
- reg32_write(DDRC_FREQ1_ZQCTL0(0), 0x50800020);
- reg32_write(DDRC_FREQ1_DFITMG0(0), 0x03828201);
- reg32_write(DDRC_FREQ1_DFITMG1(0), 0x00020103);
- reg32_write(DDRC_FREQ1_DFITMG2(0), 0x00000201);
- reg32_write(DDRC_FREQ1_DFITMG3(0), 0x00000001);
- reg32_write(DDRC_FREQ1_ODTCFG(0), 0x0a1a0768);
-
-}
-
-void umctl2_freq2_cfg(void)
-{
- reg32_write(DDRC_FREQ2_RFSHCTL0(0), 0x00208014);
- reg32_write(DDRC_FREQ2_RFSHTMG(0), 0x00308046);
- reg32_write(DDRC_FREQ2_INIT3(0), 0x05200004);
- reg32_write(DDRC_FREQ2_INIT4(0), 0x00000000);
- reg32_write(DDRC_FREQ2_INIT6(0), 0x00000000);
- reg32_write(DDRC_FREQ2_INIT7(0), 0x00000000);
- reg32_write(DDRC_FREQ2_DRAMTMG0(0), 0x070a0c07);
- reg32_write(DDRC_FREQ2_DRAMTMG1(0), 0x0005020b);
- reg32_write(DDRC_FREQ2_DRAMTMG2(0), 0x03030407);
- reg32_write(DDRC_FREQ2_DRAMTMG3(0), 0x00002006);
- reg32_write(DDRC_FREQ2_DRAMTMG4(0), 0x03020204);
- reg32_write(DDRC_FREQ2_DRAMTMG5(0), 0x04070302);
- reg32_write(DDRC_FREQ2_DRAMTMG6(0), 0x07080000);
- reg32_write(DDRC_FREQ2_DRAMTMG7(0), 0x00000704);
- reg32_write(DDRC_FREQ2_DRAMTMG8(0), 0x02026804);
- reg32_write(DDRC_FREQ2_DRAMTMG9(0), 0x40000006);
- reg32_write(DDRC_FREQ2_DRAMTMG10(0), 0x000c0b08);
- reg32_write(DDRC_FREQ2_DRAMTMG11(0), 0x01010015);
- reg32_write(DDRC_FREQ2_DRAMTMG12(0), 0x00000000);
- reg32_write(DDRC_FREQ2_DRAMTMG13(0), 0x51000000);
- reg32_write(DDRC_FREQ2_DRAMTMG14(0), 0x000002a0);
- reg32_write(DDRC_FREQ2_DRAMTMG15(0), 0x00000000);
- reg32_write(DDRC_FREQ2_DRAMTMG17(0), 0x008c0039);
- reg32_write(DDRC_FREQ2_ZQCTL0(0), 0x50800020);
- reg32_write(DDRC_FREQ2_DFITMG0(0), 0x03818200);
- reg32_write(DDRC_FREQ2_DFITMG1(0), 0x00020103);
- reg32_write(DDRC_FREQ2_DFITMG2(0), 0x00000100);
- reg32_write(DDRC_FREQ2_DFITMG3(0), 0x00000001);
- reg32_write(DDRC_FREQ2_ODTCFG(0), 0x04050800);
-
-}
-
-void ddr3_pub_train(void)
-{
- volatile unsigned int tmp_t;
-
- reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00003F); /* assert [0]ddr1_preset_n, [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n, [4]src_system_rst_b! */
- reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); /* deassert [4]src_system_rst_b! */
-
- /* change the clock source of dram_apb_clk_root */
- clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); /* to source 4 --800MHz/4 */
-
- dram_pll_init(MHZ(400));
- ddr_dbg("C: dram pll init finished\n");
-
- reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
- reg32setbit(0x303A00F8, 5);/* PU_PGC_SW_PUP_REQ */
-
- reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); /* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */
-
- reg32_write(DDRC_DBG1(0), 0x00000001);
- reg32_write(DDRC_PWRCTL(0), 0x00000001);
-
- while (0 != (0x3 & reg32_read(DDRC_STAT(0))))
- ;
-
- ddr_dbg("C: cfg umctl2 regs ...\n");
- umctl2_cfg();
-#ifdef DDR3_SW_FFC
- umctl2_freq1_cfg();
- umctl2_freq2_cfg();
-#endif
-
- reg32_write(DDRC_RFSHCTL3(0), 0x00000011);
- /* RESET: <ctn> DEASSERTED */
- /* RESET: <a Port 0 DEASSERTED(0) */
- reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); /* release all reset */
-
- reg32_write(DDRC_DBG1(0), 0x00000000);
- reg32_write(DDRC_PWRCTL(0), 0x00000a8);
- reg32_write(DDRC_SWCTL(0), 0x00000000);
-
- reg32_write(DDRC_DFIMISC(0), 0x00000000);
-
- ddr_dbg("C: phy training ...\n");
- ddr3_phyinit_train_sw_ffc(0);
-
- do {
- tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x00020097);
- ddr_dbg("C: Waiting CalBusy value = 0\n");
- } while (tmp_t != 0);
-
- reg32_write(DDRC_DFIMISC(0), 0x00000020);
-
- /* wait DFISTAT.dfi_init_complete to 1 */
- while (0 == (0x1 & reg32_read(DDRC_DFISTAT(0))))
- ;
-
- /* clear DFIMISC.dfi_init_complete_en */
- reg32_write(DDRC_DFIMISC(0), 0x00000000);
- /* set DFIMISC.dfi_init_complete_en again */
- reg32_write(DDRC_DFIMISC(0), 0x00000001);
- reg32_write(DDRC_PWRCTL(0), 0x0000088);
-
- /* set SWCTL.sw_done to enable quasi-dynamic register programming outside reset. */
- reg32_write(DDRC_SWCTL(0), 0x00000001);
- /* wait SWSTAT.sw_done_ack to 1 */
- while (0 == (0x1 & reg32_read(DDRC_SWSTAT(0))))
- ;
-
- /* wait STAT to normal state */
- while (0x1 != (0x3 & reg32_read(DDRC_STAT(0))))
- ;
-
- reg32_write(DDRC_PWRCTL(0), 0x0000088);
-
- reg32_write(DDRC_PCTRL_0(0), 0x00000001);
- reg32_write(DDRC_RFSHCTL3(0), 0x00000010); /* dis_auto-refresh is set to 0 */
-
- }
-
-void ddr_init(struct dram_timing_info *timing_info)
-{
- /* initialize DDR4-2400 (umctl2@800MHz) */
- ddr3_pub_train();
-}
diff --git a/board/freescale/imx8mm_val/ddr/ddr3l/restore_1d2d_trained_csr_ddr3_p012.c b/board/freescale/imx8mm_val/ddr/ddr3l/restore_1d2d_trained_csr_ddr3_p012.c
deleted file mode 100644
index f01ed9f..0000000
--- a/board/freescale/imx8mm_val/ddr/ddr3l/restore_1d2d_trained_csr_ddr3_p012.c
+++ /dev/null
@@ -1,969 +0,0 @@
-/*
- * Copyright 2018 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/ddr.h>
-#include <asm/arch/clock.h>
-#include "../ddr.h"
-#include "ddr3_define.h"
-
-static const unsigned int restore_csr[] = {
- 0x200b2,
- 0x1200b2,
- 0x2200b2,
- 0x200cb,
-#ifdef RUN_ON_SILICON
- 0x10043,
- 0x110043,
- 0x210043,
- 0x10143,
- 0x110143,
- 0x210143,
- 0x11043,
- 0x111043,
- 0x211043,
- 0x11143,
- 0x111143,
- 0x211143,
- 0x12043,
- 0x112043,
- 0x212043,
- 0x12143,
- 0x112143,
- 0x212143,
- 0x13043,
- 0x113043,
- 0x213043,
- 0x13143,
- 0x113143,
- 0x213143,
- 0x80,
- 0x100080,
- 0x200080,
- 0x1080,
- 0x101080,
- 0x201080,
- 0x2080,
- 0x102080,
- 0x202080,
- 0x3080,
- 0x103080,
- 0x203080,
- 0x4080,
- 0x104080,
- 0x204080,
- 0x5080,
- 0x105080,
- 0x205080,
- 0x6080,
- 0x106080,
- 0x206080,
- 0x7080,
- 0x107080,
- 0x207080,
- 0x8080,
- 0x108080,
- 0x208080,
- 0x9080,
- 0x109080,
- 0x209080,
- 0x10080,
- 0x110080,
- 0x210080,
- 0x10180,
- 0x110180,
- 0x210180,
- 0x10081,
- 0x110081,
- 0x210081,
- 0x10181,
- 0x110181,
- 0x210181,
- 0x10082,
- 0x110082,
- 0x210082,
- 0x10182,
- 0x110182,
- 0x210182,
- 0x10083,
- 0x110083,
- 0x210083,
- 0x10183,
- 0x110183,
- 0x210183,
- 0x11080,
- 0x111080,
- 0x211080,
- 0x11180,
- 0x111180,
- 0x211180,
- 0x11081,
- 0x111081,
- 0x211081,
- 0x11181,
- 0x111181,
- 0x211181,
- 0x11082,
- 0x111082,
- 0x211082,
- 0x11182,
- 0x111182,
- 0x211182,
- 0x11083,
- 0x111083,
- 0x211083,
- 0x11183,
- 0x111183,
- 0x211183,
- 0x12080,
- 0x112080,
- 0x212080,
- 0x12180,
- 0x112180,
- 0x212180,
- 0x12081,
- 0x112081,
- 0x212081,
- 0x12181,
- 0x112181,
- 0x212181,
- 0x12082,
- 0x112082,
- 0x212082,
- 0x12182,
- 0x112182,
- 0x212182,
- 0x12083,
- 0x112083,
- 0x212083,
- 0x12183,
- 0x112183,
- 0x212183,
- 0x13080,
- 0x113080,
- 0x213080,
- 0x13180,
- 0x113180,
- 0x213180,
- 0x13081,
- 0x113081,
- 0x213081,
- 0x13181,
- 0x113181,
- 0x213181,
- 0x13082,
- 0x113082,
- 0x213082,
- 0x13182,
- 0x113182,
- 0x213182,
- 0x13083,
- 0x113083,
- 0x213083,
- 0x13183,
- 0x113183,
- 0x213183,
- 0x100d0,
- 0x1100d0,
- 0x2100d0,
- 0x101d0,
- 0x1101d0,
- 0x2101d0,
- 0x100d1,
- 0x1100d1,
- 0x2100d1,
- 0x101d1,
- 0x1101d1,
- 0x2101d1,
- 0x100d2,
- 0x1100d2,
- 0x2100d2,
- 0x101d2,
- 0x1101d2,
- 0x2101d2,
- 0x100d3,
- 0x1100d3,
- 0x2100d3,
- 0x101d3,
- 0x1101d3,
- 0x2101d3,
- 0x110d0,
- 0x1110d0,
- 0x2110d0,
- 0x111d0,
- 0x1111d0,
- 0x2111d0,
- 0x110d1,
- 0x1110d1,
- 0x2110d1,
- 0x111d1,
- 0x1111d1,
- 0x2111d1,
- 0x110d2,
- 0x1110d2,
- 0x2110d2,
- 0x111d2,
- 0x1111d2,
- 0x2111d2,
- 0x110d3,
- 0x1110d3,
- 0x2110d3,
- 0x111d3,
- 0x1111d3,
- 0x2111d3,
- 0x120d0,
- 0x1120d0,
- 0x2120d0,
- 0x121d0,
- 0x1121d0,
- 0x2121d0,
- 0x120d1,
- 0x1120d1,
- 0x2120d1,
- 0x121d1,
- 0x1121d1,
- 0x2121d1,
- 0x120d2,
- 0x1120d2,
- 0x2120d2,
- 0x121d2,
- 0x1121d2,
- 0x2121d2,
- 0x120d3,
- 0x1120d3,
- 0x2120d3,
- 0x121d3,
- 0x1121d3,
- 0x2121d3,
- 0x130d0,
- 0x1130d0,
- 0x2130d0,
- 0x131d0,
- 0x1131d0,
- 0x2131d0,
- 0x130d1,
- 0x1130d1,
- 0x2130d1,
- 0x131d1,
- 0x1131d1,
- 0x2131d1,
- 0x130d2,
- 0x1130d2,
- 0x2130d2,
- 0x131d2,
- 0x1131d2,
- 0x2131d2,
- 0x130d3,
- 0x1130d3,
- 0x2130d3,
- 0x131d3,
- 0x1131d3,
- 0x2131d3,
- 0x10068,
- 0x10168,
- 0x10268,
- 0x10368,
- 0x10468,
- 0x10568,
- 0x10668,
- 0x10768,
- 0x10868,
- 0x10069,
- 0x10169,
- 0x10269,
- 0x10369,
- 0x10469,
- 0x10569,
- 0x10669,
- 0x10769,
- 0x10869,
- 0x1006a,
- 0x1016a,
- 0x1026a,
- 0x1036a,
- 0x1046a,
- 0x1056a,
- 0x1066a,
- 0x1076a,
- 0x1086a,
- 0x1006b,
- 0x1016b,
- 0x1026b,
- 0x1036b,
- 0x1046b,
- 0x1056b,
- 0x1066b,
- 0x1076b,
- 0x1086b,
- 0x11068,
- 0x11168,
- 0x11268,
- 0x11368,
- 0x11468,
- 0x11568,
- 0x11668,
- 0x11768,
- 0x11868,
- 0x11069,
- 0x11169,
- 0x11269,
- 0x11369,
- 0x11469,
- 0x11569,
- 0x11669,
- 0x11769,
- 0x11869,
- 0x1106a,
- 0x1116a,
- 0x1126a,
- 0x1136a,
- 0x1146a,
- 0x1156a,
- 0x1166a,
- 0x1176a,
- 0x1186a,
- 0x1106b,
- 0x1116b,
- 0x1126b,
- 0x1136b,
- 0x1146b,
- 0x1156b,
- 0x1166b,
- 0x1176b,
- 0x1186b,
- 0x12068,
- 0x12168,
- 0x12268,
- 0x12368,
- 0x12468,
- 0x12568,
- 0x12668,
- 0x12768,
- 0x12868,
- 0x12069,
- 0x12169,
- 0x12269,
- 0x12369,
- 0x12469,
- 0x12569,
- 0x12669,
- 0x12769,
- 0x12869,
- 0x1206a,
- 0x1216a,
- 0x1226a,
- 0x1236a,
- 0x1246a,
- 0x1256a,
- 0x1266a,
- 0x1276a,
- 0x1286a,
- 0x1206b,
- 0x1216b,
- 0x1226b,
- 0x1236b,
- 0x1246b,
- 0x1256b,
- 0x1266b,
- 0x1276b,
- 0x1286b,
- 0x13068,
- 0x13168,
- 0x13268,
- 0x13368,
- 0x13468,
- 0x13568,
- 0x13668,
- 0x13768,
- 0x13868,
- 0x13069,
- 0x13169,
- 0x13269,
- 0x13369,
- 0x13469,
- 0x13569,
- 0x13669,
- 0x13769,
- 0x13869,
- 0x1306a,
- 0x1316a,
- 0x1326a,
- 0x1336a,
- 0x1346a,
- 0x1356a,
- 0x1366a,
- 0x1376a,
- 0x1386a,
- 0x1306b,
- 0x1316b,
- 0x1326b,
- 0x1336b,
- 0x1346b,
- 0x1356b,
- 0x1366b,
- 0x1376b,
- 0x1386b,
- 0x1008c,
- 0x11008c,
- 0x21008c,
- 0x1018c,
- 0x11018c,
- 0x21018c,
- 0x1008d,
- 0x11008d,
- 0x21008d,
- 0x1018d,
- 0x11018d,
- 0x21018d,
- 0x1008e,
- 0x11008e,
- 0x21008e,
- 0x1018e,
- 0x11018e,
- 0x21018e,
- 0x1008f,
- 0x11008f,
- 0x21008f,
- 0x1018f,
- 0x11018f,
- 0x21018f,
- 0x1108c,
- 0x11108c,
- 0x21108c,
- 0x1118c,
- 0x11118c,
- 0x21118c,
- 0x1108d,
- 0x11108d,
- 0x21108d,
- 0x1118d,
- 0x11118d,
- 0x21118d,
- 0x1108e,
- 0x11108e,
- 0x21108e,
- 0x1118e,
- 0x11118e,
- 0x21118e,
- 0x1108f,
- 0x11108f,
- 0x21108f,
- 0x1118f,
- 0x11118f,
- 0x21118f,
- 0x1208c,
- 0x11208c,
- 0x21208c,
- 0x1218c,
- 0x11218c,
- 0x21218c,
- 0x1208d,
- 0x11208d,
- 0x21208d,
- 0x1218d,
- 0x11218d,
- 0x21218d,
- 0x1208e,
- 0x11208e,
- 0x21208e,
- 0x1218e,
- 0x11218e,
- 0x21218e,
- 0x1208f,
- 0x11208f,
- 0x21208f,
- 0x1218f,
- 0x11218f,
- 0x21218f,
- 0x1308c,
- 0x11308c,
- 0x21308c,
- 0x1318c,
- 0x11318c,
- 0x21318c,
- 0x1308d,
- 0x11308d,
- 0x21308d,
- 0x1318d,
- 0x11318d,
- 0x21318d,
- 0x1308e,
- 0x11308e,
- 0x21308e,
- 0x1318e,
- 0x11318e,
- 0x21318e,
- 0x1308f,
- 0x11308f,
- 0x21308f,
- 0x1318f,
- 0x11318f,
- 0x21318f,
- 0x100c0,
- 0x1100c0,
- 0x2100c0,
- 0x101c0,
- 0x1101c0,
- 0x2101c0,
- 0x102c0,
- 0x1102c0,
- 0x2102c0,
- 0x103c0,
- 0x1103c0,
- 0x2103c0,
- 0x104c0,
- 0x1104c0,
- 0x2104c0,
- 0x105c0,
- 0x1105c0,
- 0x2105c0,
- 0x106c0,
- 0x1106c0,
- 0x2106c0,
- 0x107c0,
- 0x1107c0,
- 0x2107c0,
- 0x108c0,
- 0x1108c0,
- 0x2108c0,
- 0x100c1,
- 0x1100c1,
- 0x2100c1,
- 0x101c1,
- 0x1101c1,
- 0x2101c1,
- 0x102c1,
- 0x1102c1,
- 0x2102c1,
- 0x103c1,
- 0x1103c1,
- 0x2103c1,
- 0x104c1,
- 0x1104c1,
- 0x2104c1,
- 0x105c1,
- 0x1105c1,
- 0x2105c1,
- 0x106c1,
- 0x1106c1,
- 0x2106c1,
- 0x107c1,
- 0x1107c1,
- 0x2107c1,
- 0x108c1,
- 0x1108c1,
- 0x2108c1,
- 0x100c2,
- 0x1100c2,
- 0x2100c2,
- 0x101c2,
- 0x1101c2,
- 0x2101c2,
- 0x102c2,
- 0x1102c2,
- 0x2102c2,
- 0x103c2,
- 0x1103c2,
- 0x2103c2,
- 0x104c2,
- 0x1104c2,
- 0x2104c2,
- 0x105c2,
- 0x1105c2,
- 0x2105c2,
- 0x106c2,
- 0x1106c2,
- 0x2106c2,
- 0x107c2,
- 0x1107c2,
- 0x2107c2,
- 0x108c2,
- 0x1108c2,
- 0x2108c2,
- 0x100c3,
- 0x1100c3,
- 0x2100c3,
- 0x101c3,
- 0x1101c3,
- 0x2101c3,
- 0x102c3,
- 0x1102c3,
- 0x2102c3,
- 0x103c3,
- 0x1103c3,
- 0x2103c3,
- 0x104c3,
- 0x1104c3,
- 0x2104c3,
- 0x105c3,
- 0x1105c3,
- 0x2105c3,
- 0x106c3,
- 0x1106c3,
- 0x2106c3,
- 0x107c3,
- 0x1107c3,
- 0x2107c3,
- 0x108c3,
- 0x1108c3,
- 0x2108c3,
- 0x110c0,
- 0x1110c0,
- 0x2110c0,
- 0x111c0,
- 0x1111c0,
- 0x2111c0,
- 0x112c0,
- 0x1112c0,
- 0x2112c0,
- 0x113c0,
- 0x1113c0,
- 0x2113c0,
- 0x114c0,
- 0x1114c0,
- 0x2114c0,
- 0x115c0,
- 0x1115c0,
- 0x2115c0,
- 0x116c0,
- 0x1116c0,
- 0x2116c0,
- 0x117c0,
- 0x1117c0,
- 0x2117c0,
- 0x118c0,
- 0x1118c0,
- 0x2118c0,
- 0x110c1,
- 0x1110c1,
- 0x2110c1,
- 0x111c1,
- 0x1111c1,
- 0x2111c1,
- 0x112c1,
- 0x1112c1,
- 0x2112c1,
- 0x113c1,
- 0x1113c1,
- 0x2113c1,
- 0x114c1,
- 0x1114c1,
- 0x2114c1,
- 0x115c1,
- 0x1115c1,
- 0x2115c1,
- 0x116c1,
- 0x1116c1,
- 0x2116c1,
- 0x117c1,
- 0x1117c1,
- 0x2117c1,
- 0x118c1,
- 0x1118c1,
- 0x2118c1,
- 0x110c2,
- 0x1110c2,
- 0x2110c2,
- 0x111c2,
- 0x1111c2,
- 0x2111c2,
- 0x112c2,
- 0x1112c2,
- 0x2112c2,
- 0x113c2,
- 0x1113c2,
- 0x2113c2,
- 0x114c2,
- 0x1114c2,
- 0x2114c2,
- 0x115c2,
- 0x1115c2,
- 0x2115c2,
- 0x116c2,
- 0x1116c2,
- 0x2116c2,
- 0x117c2,
- 0x1117c2,
- 0x2117c2,
- 0x118c2,
- 0x1118c2,
- 0x2118c2,
- 0x110c3,
- 0x1110c3,
- 0x2110c3,
- 0x111c3,
- 0x1111c3,
- 0x2111c3,
- 0x112c3,
- 0x1112c3,
- 0x2112c3,
- 0x113c3,
- 0x1113c3,
- 0x2113c3,
- 0x114c3,
- 0x1114c3,
- 0x2114c3,
- 0x115c3,
- 0x1115c3,
- 0x2115c3,
- 0x116c3,
- 0x1116c3,
- 0x2116c3,
- 0x117c3,
- 0x1117c3,
- 0x2117c3,
- 0x118c3,
- 0x1118c3,
- 0x2118c3,
- 0x120c0,
- 0x1120c0,
- 0x2120c0,
- 0x121c0,
- 0x1121c0,
- 0x2121c0,
- 0x122c0,
- 0x1122c0,
- 0x2122c0,
- 0x123c0,
- 0x1123c0,
- 0x2123c0,
- 0x124c0,
- 0x1124c0,
- 0x2124c0,
- 0x125c0,
- 0x1125c0,
- 0x2125c0,
- 0x126c0,
- 0x1126c0,
- 0x2126c0,
- 0x127c0,
- 0x1127c0,
- 0x2127c0,
- 0x128c0,
- 0x1128c0,
- 0x2128c0,
- 0x120c1,
- 0x1120c1,
- 0x2120c1,
- 0x121c1,
- 0x1121c1,
- 0x2121c1,
- 0x122c1,
- 0x1122c1,
- 0x2122c1,
- 0x123c1,
- 0x1123c1,
- 0x2123c1,
- 0x124c1,
- 0x1124c1,
- 0x2124c1,
- 0x125c1,
- 0x1125c1,
- 0x2125c1,
- 0x126c1,
- 0x1126c1,
- 0x2126c1,
- 0x127c1,
- 0x1127c1,
- 0x2127c1,
- 0x128c1,
- 0x1128c1,
- 0x2128c1,
- 0x120c2,
- 0x1120c2,
- 0x2120c2,
- 0x121c2,
- 0x1121c2,
- 0x2121c2,
- 0x122c2,
- 0x1122c2,
- 0x2122c2,
- 0x123c2,
- 0x1123c2,
- 0x2123c2,
- 0x124c2,
- 0x1124c2,
- 0x2124c2,
- 0x125c2,
- 0x1125c2,
- 0x2125c2,
- 0x126c2,
- 0x1126c2,
- 0x2126c2,
- 0x127c2,
- 0x1127c2,
- 0x2127c2,
- 0x128c2,
- 0x1128c2,
- 0x2128c2,
- 0x120c3,
- 0x1120c3,
- 0x2120c3,
- 0x121c3,
- 0x1121c3,
- 0x2121c3,
- 0x122c3,
- 0x1122c3,
- 0x2122c3,
- 0x123c3,
- 0x1123c3,
- 0x2123c3,
- 0x124c3,
- 0x1124c3,
- 0x2124c3,
- 0x125c3,
- 0x1125c3,
- 0x2125c3,
- 0x126c3,
- 0x1126c3,
- 0x2126c3,
- 0x127c3,
- 0x1127c3,
- 0x2127c3,
- 0x128c3,
- 0x1128c3,
- 0x2128c3,
- 0x130c0,
- 0x1130c0,
- 0x2130c0,
- 0x131c0,
- 0x1131c0,
- 0x2131c0,
- 0x132c0,
- 0x1132c0,
- 0x2132c0,
- 0x133c0,
- 0x1133c0,
- 0x2133c0,
- 0x134c0,
- 0x1134c0,
- 0x2134c0,
- 0x135c0,
- 0x1135c0,
- 0x2135c0,
- 0x136c0,
- 0x1136c0,
- 0x2136c0,
- 0x137c0,
- 0x1137c0,
- 0x2137c0,
- 0x138c0,
- 0x1138c0,
- 0x2138c0,
- 0x130c1,
- 0x1130c1,
- 0x2130c1,
- 0x131c1,
- 0x1131c1,
- 0x2131c1,
- 0x132c1,
- 0x1132c1,
- 0x2132c1,
- 0x133c1,
- 0x1133c1,
- 0x2133c1,
- 0x134c1,
- 0x1134c1,
- 0x2134c1,
- 0x135c1,
- 0x1135c1,
- 0x2135c1,
- 0x136c1,
- 0x1136c1,
- 0x2136c1,
- 0x137c1,
- 0x1137c1,
- 0x2137c1,
- 0x138c1,
- 0x1138c1,
- 0x2138c1,
- 0x130c2,
- 0x1130c2,
- 0x2130c2,
- 0x131c2,
- 0x1131c2,
- 0x2131c2,
- 0x132c2,
- 0x1132c2,
- 0x2132c2,
- 0x133c2,
- 0x1133c2,
- 0x2133c2,
- 0x134c2,
- 0x1134c2,
- 0x2134c2,
- 0x135c2,
- 0x1135c2,
- 0x2135c2,
- 0x136c2,
- 0x1136c2,
- 0x2136c2,
- 0x137c2,
- 0x1137c2,
- 0x2137c2,
- 0x138c2,
- 0x1138c2,
- 0x2138c2,
- 0x130c3,
- 0x1130c3,
- 0x2130c3,
- 0x131c3,
- 0x1131c3,
- 0x2131c3,
- 0x132c3,
- 0x1132c3,
- 0x2132c3,
- 0x133c3,
- 0x1133c3,
- 0x2133c3,
- 0x134c3,
- 0x1134c3,
- 0x2134c3,
- 0x135c3,
- 0x1135c3,
- 0x2135c3,
- 0x136c3,
- 0x1136c3,
- 0x2136c3,
- 0x137c3,
- 0x1137c3,
- 0x2137c3,
- 0x138c3,
- 0x1138c3,
- 0x2138c3,
- 0x10020,
- 0x110020,
- 0x210020,
- 0x11020,
- 0x111020,
- 0x211020,
- 0x12020,
- 0x112020,
- 0x212020,
- 0x13020,
- 0x113020,
-#endif
- 0x213020,
- 0x2007d,
- 0x12007d,
- 0x22007d,
- 0
-};
-
-void restore_1d2d_trained_csr_ddr3_p012(unsigned int addr)
-{
- unsigned int i;
-
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- for (i = 0; restore_csr[i] != 0; i++) {
- dwc_ddrphy_apb_wr(restore_csr[i], reg32_read(addr + (i << 2)));
- }
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
-
- ddr_dbg("restore 1d2d training registers done \n");
-}
diff --git a/board/freescale/imx8mm_val/ddr/ddr3l/save_1d2d_trained_csr_ddr3_p012.c b/board/freescale/imx8mm_val/ddr/ddr3l/save_1d2d_trained_csr_ddr3_p012.c
deleted file mode 100644
index 4ea62bb..0000000
--- a/board/freescale/imx8mm_val/ddr/ddr3l/save_1d2d_trained_csr_ddr3_p012.c
+++ /dev/null
@@ -1,971 +0,0 @@
-/*
- * Copyright 2018 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/ddr.h>
-#include <asm/arch/clock.h>
-#include "../ddr.h"
-#include "ddr3_define.h"
-
-static const unsigned int save_csr[] = {
- 0x200b2,
- 0x1200b2,
- 0x2200b2,
- 0x200cb,
-#ifdef RUN_ON_SILICON
- 0x10043,
- 0x110043,
- 0x210043,
- 0x10143,
- 0x110143,
- 0x210143,
- 0x11043,
- 0x111043,
- 0x211043,
- 0x11143,
- 0x111143,
- 0x211143,
- 0x12043,
- 0x112043,
- 0x212043,
- 0x12143,
- 0x112143,
- 0x212143,
- 0x13043,
- 0x113043,
- 0x213043,
- 0x13143,
- 0x113143,
- 0x213143,
- 0x80,
- 0x100080,
- 0x200080,
- 0x1080,
- 0x101080,
- 0x201080,
- 0x2080,
- 0x102080,
- 0x202080,
- 0x3080,
- 0x103080,
- 0x203080,
- 0x4080,
- 0x104080,
- 0x204080,
- 0x5080,
- 0x105080,
- 0x205080,
- 0x6080,
- 0x106080,
- 0x206080,
- 0x7080,
- 0x107080,
- 0x207080,
- 0x8080,
- 0x108080,
- 0x208080,
- 0x9080,
- 0x109080,
- 0x209080,
- 0x10080,
- 0x110080,
- 0x210080,
- 0x10180,
- 0x110180,
- 0x210180,
- 0x10081,
- 0x110081,
- 0x210081,
- 0x10181,
- 0x110181,
- 0x210181,
- 0x10082,
- 0x110082,
- 0x210082,
- 0x10182,
- 0x110182,
- 0x210182,
- 0x10083,
- 0x110083,
- 0x210083,
- 0x10183,
- 0x110183,
- 0x210183,
- 0x11080,
- 0x111080,
- 0x211080,
- 0x11180,
- 0x111180,
- 0x211180,
- 0x11081,
- 0x111081,
- 0x211081,
- 0x11181,
- 0x111181,
- 0x211181,
- 0x11082,
- 0x111082,
- 0x211082,
- 0x11182,
- 0x111182,
- 0x211182,
- 0x11083,
- 0x111083,
- 0x211083,
- 0x11183,
- 0x111183,
- 0x211183,
- 0x12080,
- 0x112080,
- 0x212080,
- 0x12180,
- 0x112180,
- 0x212180,
- 0x12081,
- 0x112081,
- 0x212081,
- 0x12181,
- 0x112181,
- 0x212181,
- 0x12082,
- 0x112082,
- 0x212082,
- 0x12182,
- 0x112182,
- 0x212182,
- 0x12083,
- 0x112083,
- 0x212083,
- 0x12183,
- 0x112183,
- 0x212183,
- 0x13080,
- 0x113080,
- 0x213080,
- 0x13180,
- 0x113180,
- 0x213180,
- 0x13081,
- 0x113081,
- 0x213081,
- 0x13181,
- 0x113181,
- 0x213181,
- 0x13082,
- 0x113082,
- 0x213082,
- 0x13182,
- 0x113182,
- 0x213182,
- 0x13083,
- 0x113083,
- 0x213083,
- 0x13183,
- 0x113183,
- 0x213183,
- 0x100d0,
- 0x1100d0,
- 0x2100d0,
- 0x101d0,
- 0x1101d0,
- 0x2101d0,
- 0x100d1,
- 0x1100d1,
- 0x2100d1,
- 0x101d1,
- 0x1101d1,
- 0x2101d1,
- 0x100d2,
- 0x1100d2,
- 0x2100d2,
- 0x101d2,
- 0x1101d2,
- 0x2101d2,
- 0x100d3,
- 0x1100d3,
- 0x2100d3,
- 0x101d3,
- 0x1101d3,
- 0x2101d3,
- 0x110d0,
- 0x1110d0,
- 0x2110d0,
- 0x111d0,
- 0x1111d0,
- 0x2111d0,
- 0x110d1,
- 0x1110d1,
- 0x2110d1,
- 0x111d1,
- 0x1111d1,
- 0x2111d1,
- 0x110d2,
- 0x1110d2,
- 0x2110d2,
- 0x111d2,
- 0x1111d2,
- 0x2111d2,
- 0x110d3,
- 0x1110d3,
- 0x2110d3,
- 0x111d3,
- 0x1111d3,
- 0x2111d3,
- 0x120d0,
- 0x1120d0,
- 0x2120d0,
- 0x121d0,
- 0x1121d0,
- 0x2121d0,
- 0x120d1,
- 0x1120d1,
- 0x2120d1,
- 0x121d1,
- 0x1121d1,
- 0x2121d1,
- 0x120d2,
- 0x1120d2,
- 0x2120d2,
- 0x121d2,
- 0x1121d2,
- 0x2121d2,
- 0x120d3,
- 0x1120d3,
- 0x2120d3,
- 0x121d3,
- 0x1121d3,
- 0x2121d3,
- 0x130d0,
- 0x1130d0,
- 0x2130d0,
- 0x131d0,
- 0x1131d0,
- 0x2131d0,
- 0x130d1,
- 0x1130d1,
- 0x2130d1,
- 0x131d1,
- 0x1131d1,
- 0x2131d1,
- 0x130d2,
- 0x1130d2,
- 0x2130d2,
- 0x131d2,
- 0x1131d2,
- 0x2131d2,
- 0x130d3,
- 0x1130d3,
- 0x2130d3,
- 0x131d3,
- 0x1131d3,
- 0x2131d3,
- 0x10068,
- 0x10168,
- 0x10268,
- 0x10368,
- 0x10468,
- 0x10568,
- 0x10668,
- 0x10768,
- 0x10868,
- 0x10069,
- 0x10169,
- 0x10269,
- 0x10369,
- 0x10469,
- 0x10569,
- 0x10669,
- 0x10769,
- 0x10869,
- 0x1006a,
- 0x1016a,
- 0x1026a,
- 0x1036a,
- 0x1046a,
- 0x1056a,
- 0x1066a,
- 0x1076a,
- 0x1086a,
- 0x1006b,
- 0x1016b,
- 0x1026b,
- 0x1036b,
- 0x1046b,
- 0x1056b,
- 0x1066b,
- 0x1076b,
- 0x1086b,
- 0x11068,
- 0x11168,
- 0x11268,
- 0x11368,
- 0x11468,
- 0x11568,
- 0x11668,
- 0x11768,
- 0x11868,
- 0x11069,
- 0x11169,
- 0x11269,
- 0x11369,
- 0x11469,
- 0x11569,
- 0x11669,
- 0x11769,
- 0x11869,
- 0x1106a,
- 0x1116a,
- 0x1126a,
- 0x1136a,
- 0x1146a,
- 0x1156a,
- 0x1166a,
- 0x1176a,
- 0x1186a,
- 0x1106b,
- 0x1116b,
- 0x1126b,
- 0x1136b,
- 0x1146b,
- 0x1156b,
- 0x1166b,
- 0x1176b,
- 0x1186b,
- 0x12068,
- 0x12168,
- 0x12268,
- 0x12368,
- 0x12468,
- 0x12568,
- 0x12668,
- 0x12768,
- 0x12868,
- 0x12069,
- 0x12169,
- 0x12269,
- 0x12369,
- 0x12469,
- 0x12569,
- 0x12669,
- 0x12769,
- 0x12869,
- 0x1206a,
- 0x1216a,
- 0x1226a,
- 0x1236a,
- 0x1246a,
- 0x1256a,
- 0x1266a,
- 0x1276a,
- 0x1286a,
- 0x1206b,
- 0x1216b,
- 0x1226b,
- 0x1236b,
- 0x1246b,
- 0x1256b,
- 0x1266b,
- 0x1276b,
- 0x1286b,
- 0x13068,
- 0x13168,
- 0x13268,
- 0x13368,
- 0x13468,
- 0x13568,
- 0x13668,
- 0x13768,
- 0x13868,
- 0x13069,
- 0x13169,
- 0x13269,
- 0x13369,
- 0x13469,
- 0x13569,
- 0x13669,
- 0x13769,
- 0x13869,
- 0x1306a,
- 0x1316a,
- 0x1326a,
- 0x1336a,
- 0x1346a,
- 0x1356a,
- 0x1366a,
- 0x1376a,
- 0x1386a,
- 0x1306b,
- 0x1316b,
- 0x1326b,
- 0x1336b,
- 0x1346b,
- 0x1356b,
- 0x1366b,
- 0x1376b,
- 0x1386b,
- 0x1008c,
- 0x11008c,
- 0x21008c,
- 0x1018c,
- 0x11018c,
- 0x21018c,
- 0x1008d,
- 0x11008d,
- 0x21008d,
- 0x1018d,
- 0x11018d,
- 0x21018d,
- 0x1008e,
- 0x11008e,
- 0x21008e,
- 0x1018e,
- 0x11018e,
- 0x21018e,
- 0x1008f,
- 0x11008f,
- 0x21008f,
- 0x1018f,
- 0x11018f,
- 0x21018f,
- 0x1108c,
- 0x11108c,
- 0x21108c,
- 0x1118c,
- 0x11118c,
- 0x21118c,
- 0x1108d,
- 0x11108d,
- 0x21108d,
- 0x1118d,
- 0x11118d,
- 0x21118d,
- 0x1108e,
- 0x11108e,
- 0x21108e,
- 0x1118e,
- 0x11118e,
- 0x21118e,
- 0x1108f,
- 0x11108f,
- 0x21108f,
- 0x1118f,
- 0x11118f,
- 0x21118f,
- 0x1208c,
- 0x11208c,
- 0x21208c,
- 0x1218c,
- 0x11218c,
- 0x21218c,
- 0x1208d,
- 0x11208d,
- 0x21208d,
- 0x1218d,
- 0x11218d,
- 0x21218d,
- 0x1208e,
- 0x11208e,
- 0x21208e,
- 0x1218e,
- 0x11218e,
- 0x21218e,
- 0x1208f,
- 0x11208f,
- 0x21208f,
- 0x1218f,
- 0x11218f,
- 0x21218f,
- 0x1308c,
- 0x11308c,
- 0x21308c,
- 0x1318c,
- 0x11318c,
- 0x21318c,
- 0x1308d,
- 0x11308d,
- 0x21308d,
- 0x1318d,
- 0x11318d,
- 0x21318d,
- 0x1308e,
- 0x11308e,
- 0x21308e,
- 0x1318e,
- 0x11318e,
- 0x21318e,
- 0x1308f,
- 0x11308f,
- 0x21308f,
- 0x1318f,
- 0x11318f,
- 0x21318f,
- 0x100c0,
- 0x1100c0,
- 0x2100c0,
- 0x101c0,
- 0x1101c0,
- 0x2101c0,
- 0x102c0,
- 0x1102c0,
- 0x2102c0,
- 0x103c0,
- 0x1103c0,
- 0x2103c0,
- 0x104c0,
- 0x1104c0,
- 0x2104c0,
- 0x105c0,
- 0x1105c0,
- 0x2105c0,
- 0x106c0,
- 0x1106c0,
- 0x2106c0,
- 0x107c0,
- 0x1107c0,
- 0x2107c0,
- 0x108c0,
- 0x1108c0,
- 0x2108c0,
- 0x100c1,
- 0x1100c1,
- 0x2100c1,
- 0x101c1,
- 0x1101c1,
- 0x2101c1,
- 0x102c1,
- 0x1102c1,
- 0x2102c1,
- 0x103c1,
- 0x1103c1,
- 0x2103c1,
- 0x104c1,
- 0x1104c1,
- 0x2104c1,
- 0x105c1,
- 0x1105c1,
- 0x2105c1,
- 0x106c1,
- 0x1106c1,
- 0x2106c1,
- 0x107c1,
- 0x1107c1,
- 0x2107c1,
- 0x108c1,
- 0x1108c1,
- 0x2108c1,
- 0x100c2,
- 0x1100c2,
- 0x2100c2,
- 0x101c2,
- 0x1101c2,
- 0x2101c2,
- 0x102c2,
- 0x1102c2,
- 0x2102c2,
- 0x103c2,
- 0x1103c2,
- 0x2103c2,
- 0x104c2,
- 0x1104c2,
- 0x2104c2,
- 0x105c2,
- 0x1105c2,
- 0x2105c2,
- 0x106c2,
- 0x1106c2,
- 0x2106c2,
- 0x107c2,
- 0x1107c2,
- 0x2107c2,
- 0x108c2,
- 0x1108c2,
- 0x2108c2,
- 0x100c3,
- 0x1100c3,
- 0x2100c3,
- 0x101c3,
- 0x1101c3,
- 0x2101c3,
- 0x102c3,
- 0x1102c3,
- 0x2102c3,
- 0x103c3,
- 0x1103c3,
- 0x2103c3,
- 0x104c3,
- 0x1104c3,
- 0x2104c3,
- 0x105c3,
- 0x1105c3,
- 0x2105c3,
- 0x106c3,
- 0x1106c3,
- 0x2106c3,
- 0x107c3,
- 0x1107c3,
- 0x2107c3,
- 0x108c3,
- 0x1108c3,
- 0x2108c3,
- 0x110c0,
- 0x1110c0,
- 0x2110c0,
- 0x111c0,
- 0x1111c0,
- 0x2111c0,
- 0x112c0,
- 0x1112c0,
- 0x2112c0,
- 0x113c0,
- 0x1113c0,
- 0x2113c0,
- 0x114c0,
- 0x1114c0,
- 0x2114c0,
- 0x115c0,
- 0x1115c0,
- 0x2115c0,
- 0x116c0,
- 0x1116c0,
- 0x2116c0,
- 0x117c0,
- 0x1117c0,
- 0x2117c0,
- 0x118c0,
- 0x1118c0,
- 0x2118c0,
- 0x110c1,
- 0x1110c1,
- 0x2110c1,
- 0x111c1,
- 0x1111c1,
- 0x2111c1,
- 0x112c1,
- 0x1112c1,
- 0x2112c1,
- 0x113c1,
- 0x1113c1,
- 0x2113c1,
- 0x114c1,
- 0x1114c1,
- 0x2114c1,
- 0x115c1,
- 0x1115c1,
- 0x2115c1,
- 0x116c1,
- 0x1116c1,
- 0x2116c1,
- 0x117c1,
- 0x1117c1,
- 0x2117c1,
- 0x118c1,
- 0x1118c1,
- 0x2118c1,
- 0x110c2,
- 0x1110c2,
- 0x2110c2,
- 0x111c2,
- 0x1111c2,
- 0x2111c2,
- 0x112c2,
- 0x1112c2,
- 0x2112c2,
- 0x113c2,
- 0x1113c2,
- 0x2113c2,
- 0x114c2,
- 0x1114c2,
- 0x2114c2,
- 0x115c2,
- 0x1115c2,
- 0x2115c2,
- 0x116c2,
- 0x1116c2,
- 0x2116c2,
- 0x117c2,
- 0x1117c2,
- 0x2117c2,
- 0x118c2,
- 0x1118c2,
- 0x2118c2,
- 0x110c3,
- 0x1110c3,
- 0x2110c3,
- 0x111c3,
- 0x1111c3,
- 0x2111c3,
- 0x112c3,
- 0x1112c3,
- 0x2112c3,
- 0x113c3,
- 0x1113c3,
- 0x2113c3,
- 0x114c3,
- 0x1114c3,
- 0x2114c3,
- 0x115c3,
- 0x1115c3,
- 0x2115c3,
- 0x116c3,
- 0x1116c3,
- 0x2116c3,
- 0x117c3,
- 0x1117c3,
- 0x2117c3,
- 0x118c3,
- 0x1118c3,
- 0x2118c3,
- 0x120c0,
- 0x1120c0,
- 0x2120c0,
- 0x121c0,
- 0x1121c0,
- 0x2121c0,
- 0x122c0,
- 0x1122c0,
- 0x2122c0,
- 0x123c0,
- 0x1123c0,
- 0x2123c0,
- 0x124c0,
- 0x1124c0,
- 0x2124c0,
- 0x125c0,
- 0x1125c0,
- 0x2125c0,
- 0x126c0,
- 0x1126c0,
- 0x2126c0,
- 0x127c0,
- 0x1127c0,
- 0x2127c0,
- 0x128c0,
- 0x1128c0,
- 0x2128c0,
- 0x120c1,
- 0x1120c1,
- 0x2120c1,
- 0x121c1,
- 0x1121c1,
- 0x2121c1,
- 0x122c1,
- 0x1122c1,
- 0x2122c1,
- 0x123c1,
- 0x1123c1,
- 0x2123c1,
- 0x124c1,
- 0x1124c1,
- 0x2124c1,
- 0x125c1,
- 0x1125c1,
- 0x2125c1,
- 0x126c1,
- 0x1126c1,
- 0x2126c1,
- 0x127c1,
- 0x1127c1,
- 0x2127c1,
- 0x128c1,
- 0x1128c1,
- 0x2128c1,
- 0x120c2,
- 0x1120c2,
- 0x2120c2,
- 0x121c2,
- 0x1121c2,
- 0x2121c2,
- 0x122c2,
- 0x1122c2,
- 0x2122c2,
- 0x123c2,
- 0x1123c2,
- 0x2123c2,
- 0x124c2,
- 0x1124c2,
- 0x2124c2,
- 0x125c2,
- 0x1125c2,
- 0x2125c2,
- 0x126c2,
- 0x1126c2,
- 0x2126c2,
- 0x127c2,
- 0x1127c2,
- 0x2127c2,
- 0x128c2,
- 0x1128c2,
- 0x2128c2,
- 0x120c3,
- 0x1120c3,
- 0x2120c3,
- 0x121c3,
- 0x1121c3,
- 0x2121c3,
- 0x122c3,
- 0x1122c3,
- 0x2122c3,
- 0x123c3,
- 0x1123c3,
- 0x2123c3,
- 0x124c3,
- 0x1124c3,
- 0x2124c3,
- 0x125c3,
- 0x1125c3,
- 0x2125c3,
- 0x126c3,
- 0x1126c3,
- 0x2126c3,
- 0x127c3,
- 0x1127c3,
- 0x2127c3,
- 0x128c3,
- 0x1128c3,
- 0x2128c3,
- 0x130c0,
- 0x1130c0,
- 0x2130c0,
- 0x131c0,
- 0x1131c0,
- 0x2131c0,
- 0x132c0,
- 0x1132c0,
- 0x2132c0,
- 0x133c0,
- 0x1133c0,
- 0x2133c0,
- 0x134c0,
- 0x1134c0,
- 0x2134c0,
- 0x135c0,
- 0x1135c0,
- 0x2135c0,
- 0x136c0,
- 0x1136c0,
- 0x2136c0,
- 0x137c0,
- 0x1137c0,
- 0x2137c0,
- 0x138c0,
- 0x1138c0,
- 0x2138c0,
- 0x130c1,
- 0x1130c1,
- 0x2130c1,
- 0x131c1,
- 0x1131c1,
- 0x2131c1,
- 0x132c1,
- 0x1132c1,
- 0x2132c1,
- 0x133c1,
- 0x1133c1,
- 0x2133c1,
- 0x134c1,
- 0x1134c1,
- 0x2134c1,
- 0x135c1,
- 0x1135c1,
- 0x2135c1,
- 0x136c1,
- 0x1136c1,
- 0x2136c1,
- 0x137c1,
- 0x1137c1,
- 0x2137c1,
- 0x138c1,
- 0x1138c1,
- 0x2138c1,
- 0x130c2,
- 0x1130c2,
- 0x2130c2,
- 0x131c2,
- 0x1131c2,
- 0x2131c2,
- 0x132c2,
- 0x1132c2,
- 0x2132c2,
- 0x133c2,
- 0x1133c2,
- 0x2133c2,
- 0x134c2,
- 0x1134c2,
- 0x2134c2,
- 0x135c2,
- 0x1135c2,
- 0x2135c2,
- 0x136c2,
- 0x1136c2,
- 0x2136c2,
- 0x137c2,
- 0x1137c2,
- 0x2137c2,
- 0x138c2,
- 0x1138c2,
- 0x2138c2,
- 0x130c3,
- 0x1130c3,
- 0x2130c3,
- 0x131c3,
- 0x1131c3,
- 0x2131c3,
- 0x132c3,
- 0x1132c3,
- 0x2132c3,
- 0x133c3,
- 0x1133c3,
- 0x2133c3,
- 0x134c3,
- 0x1134c3,
- 0x2134c3,
- 0x135c3,
- 0x1135c3,
- 0x2135c3,
- 0x136c3,
- 0x1136c3,
- 0x2136c3,
- 0x137c3,
- 0x1137c3,
- 0x2137c3,
- 0x138c3,
- 0x1138c3,
- 0x2138c3,
- 0x10020,
- 0x110020,
- 0x210020,
- 0x11020,
- 0x111020,
- 0x211020,
- 0x12020,
- 0x112020,
- 0x212020,
- 0x13020,
- 0x113020,
-#endif
- 0x213020,
- 0x2007d,
- 0x12007d,
- 0x22007d,
- 0
-};
-
-void save_1d2d_trained_csr_ddr3_p012(unsigned int addr)
-{
- unsigned int i;
-
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- dwc_ddrphy_apb_wr(0xc0080, 0x3); /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */
- for (i = 0; save_csr[i] != 0; i++) {
- reg32_write(addr + (i << 2), dwc_ddrphy_apb_rd(save_csr[i]));
- }
- dwc_ddrphy_apb_wr(0xc0080, 0x0); /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
-
- ddr_dbg("save 1d2d training registers done \n");
-}
diff --git a/board/freescale/imx8mm_val/ddr/ddr4/Makefile b/board/freescale/imx8mm_val/ddr/ddr4/Makefile
deleted file mode 100644
index c4265d5..0000000
--- a/board/freescale/imx8mm_val/ddr/ddr4/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Copyright 2018 NXP
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-y += ddr4_phyinit_task.o
-obj-y += ddr4_phyinit_2400_400_100_2r_fw09.o
-obj-y += ddr4_swffc_fw09.o
-obj-y += save_1d2d_trained_csr_ddr4_p012.o
-obj-y += restore_1d2d_trained_csr_ddr4_p012.o
-endif
diff --git a/board/freescale/imx8mm_val/ddr/ddr4/anamix_common.h b/board/freescale/imx8mm_val/ddr/ddr4/anamix_common.h
deleted file mode 100644
index 9f1ddd3..0000000
--- a/board/freescale/imx8mm_val/ddr/ddr4/anamix_common.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright 2018 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ANAMIX_COMMON_TMP_H
-#define ANAMIX_COMMON_TMP_H
-
-/*ANAMIX Address Definition*/
-#define ANAMIX_PLL_BASE_ADDR 0x30360000
-#define ANAMIX_OSC_BASE_ADDR 0x30270000
-#define ANAMIX_TSN_BASE_ADDR 0x30260000
-
-/* PLL TOP REG */
-#define AUDIO_PLL1_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x00)
-#define AUDIO_PLL1_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x04)
-#define AUDIO_PLL1_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x08)
-#define AUDIO_PLL1_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x0c)
-#define AUDIO_PLL1_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x10)
-#define AUDIO_PLL2_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x14)
-#define AUDIO_PLL2_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x18)
-#define AUDIO_PLL2_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x1c)
-#define AUDIO_PLL2_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x20)
-#define AUDIO_PLL2_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x24)
-#define VIDEO_PLL1_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x28)
-#define VIDEO_PLL1_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x2c)
-#define VIDEO_PLL1_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x30)
-#define VIDEO_PLL1_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x34)
-#define VIDEO_PLL1_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x38)
-#define VIDEO_PLL2_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x3c)
-#define VIDEO_PLL2_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x40)
-#define VIDEO_PLL2_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x44)
-#define VIDEO_PLL2_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x48)
-#define VIDEO_PLL2_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x4c)
-#define DRAM_PLL_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x50)
-#define DRAM_PLL_FDIV_CTL0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x54)
-#define DRAM_PLL_FDIV_CTL1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x58)
-#define DRAM_PLL_SSCG_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x5c)
-#define DRAM_PLL_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x60)
-#define GPU_PLL_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x64)
-#define GPU_PLL_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x68)
-#define GPU_PLL_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x6c)
-#define GPU_PLL_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x70)
-#define VPU_PLL_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x74)
-#define VPU_PLL_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x78)
-#define VPU_PLL_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x7c)
-#define VPU_PLL_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x80)
-#define ARM_PLL_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x84)
-#define ARM_PLL_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x88)
-#define ARM_PLL_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x8c)
-#define ARM_PLL_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x90)
-#define SYS_PLL1_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x94)
-#define SYS_PLL1_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x98)
-#define SYS_PLL1_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x9c)
-#define SYS_PLL1_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x100)
-#define SYS_PLL2_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x104)
-#define SYS_PLL2_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x108)
-#define SYS_PLL2_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x10c)
-#define SYS_PLL2_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x110)
-#define SYS_PLL3_GNRL_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x114)
-#define SYS_PLL3_DIV_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x118)
-#define SYS_PLL3_LOCKD_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x11c)
-#define SYS_PLL3_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x120)
-#define ANAMIX_MISC_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x124)
-#define ANAMIX_CLK_MINT_CTL_ADDR (ANAMIX_PLL_BASE_ADDR + 0x128)
-
-/* TMP SNSR REG */
-#define TER_ADDR (ANAMIX_TSN_BASE_ADDR + 0x00)
-#define TSR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x04)
-#define TIER_ADDR (ANAMIX_TSN_BASE_ADDR + 0x08)
-#define TIDR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x0c)
-#define TMHTITR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x10)
-#define TMHTATR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x14)
-#define TMHTACTR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x18)
-#define TSCR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x1c)
-#define TRITSR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x20)
-#define TRATSR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x24)
-#define TASR_ADDR (ANAMIX_TSN_BASE_ADDR + 0x28)
-#define TTMC_ADDR (ANAMIX_TSN_BASE_ADDR + 0x2c)
-
-/* OSC */
-#define SYS_OSCNML_CTL0_ADDR (ANAMIX_OSC_BASE_ADDR + 0x00)
-#define SYS_OSCNML_CTL1_ADDR (ANAMIX_OSC_BASE_ADDR + 0x04)
-#define HDMI_OSCNML_CTL0_ADDR (ANAMIX_OSC_BASE_ADDR + 0x8000)
-#define HDMI_OSCNML_CTL1_ADDR (ANAMIX_OSC_BASE_ADDR + 0x8004)
-
-#endif
diff --git a/board/freescale/imx8mm_val/ddr/ddr4/ddr4_define.h b/board/freescale/imx8mm_val/ddr/ddr4/ddr4_define.h
deleted file mode 100644
index ad8ead7..0000000
--- a/board/freescale/imx8mm_val/ddr/ddr4/ddr4_define.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright 2018 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __DDR4_CONFIG_H__
-#define __DDR4_CONFIG_H__
-
-#include "../ddr.h"
-
-#define RUN_ON_SILICON
-#define DDR4_SW_FFC
-#define ENABLE_RETENTION
-
-#define DRAM_VREF 0x1f
-
-#define SAVE_DDRPHY_TRAIN_ADDR 0x184000
-
-/* choose p2 state data rate, define just one of below macro */
-#define PLLBYPASS_400MBPS
-
-/* //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// */
-/* for DDR4 */
-/* Note:DQ SI RON=40ohm, RTT=48ohm */
-/* CA SI RON=40ohm, RTT=65ohm */
-/* //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// */
-/* for DDR RTT NOM/PARK */
-#define DDR4_ODT_DIS 0
-#define DDR4_ODT_60 1
-#define DDR4_ODT_120 2
-#define DDR4_ODT_40 3
-#define DDR4_ODT_240 4
-#define DDR4_ODT_48 5
-#define DDR4_ODT_80 6
-#define DDR4_ODT_34 7
-
-/* for DDR RON */
-#define DDR4_RON_34 0
-#define DDR4_RON_48 1
-#define DDR4_RON_40 2
-#define DDR4_RON_RES 3
-
-/* for DDR RTT write */
-#define DDR4_RTT_WR_DIS 0
-#define DDR4_RTT_WR_120 1
-#define DDR4_RTT_WR_240 2
-#define DDR4_RTT_WR_HZ 3
-#define DDR4_RTT_WR_80 4
-
-/* for DDR4 PHY data RON */
-#define DDR4_PHY_DATA_RON_34 0xeba
-#define DDR4_PHY_DATA_RON_40 0xe38
-#define DDR4_PHY_DATA_RON_48 ((0x1a << 6) | 0x1a)
-#define DDR4_PHY_DATA_RON_60 ((0x18 << 6) | 0x18)
-#define DDR4_PHY_DATA_RON_80 ((0x0a << 6) | 0x0a)
-#define DDR4_PHY_DATA_RON_120 ((0x08 << 6) | 0x08)
-#define DDR4_PHY_DATA_RON_240 ((0x02<<6)|0x02)
-
-/* for DDR4 PHY data RTT */
-#define DDR4_PHY_DATA_RTT_34 0x3a
-#define DDR4_PHY_DATA_RTT_40 0x38
-#define DDR4_PHY_DATA_RTT_48 0x1a
-#define DDR4_PHY_DATA_RTT_60 0x18
-#define DDR4_PHY_DATA_RTT_80 0x0a
-#define DDR4_PHY_DATA_RTT_120 0x08
-#define DDR4_PHY_DATA_RTT_240 0x02
-
-/* for DDR4 PHY address RON */
-#define DDR4_PHY_ADDR_RON_30 ((0x07 << 5) | 0x07)
-#define DDR4_PHY_ADDR_RON_40 0x63
-#define DDR4_PHY_ADDR_RON_60 ((0x01 << 5) | 0x01)
-#define DDR4_PHY_ADDR_RON_120 ((0x00 << 5) | 0x00)
-
-#define DDR4_PHY_ADDR_RON DDR4_PHY_ADDR_RON_40
-
-/* read DDR4 */
-#ifdef DDR_ONE_RANK
-#define DDR4_RON DDR4_RON_34
-#define DDR4_PHY_DATA_RTT DDR4_PHY_DATA_RTT_48
-#define DDR4_PHYREF_VALUE 91
-#else
-#define DDR4_RON DDR4_RON_40
-#define DDR4_PHY_DATA_RTT DDR4_PHY_DATA_RTT_48
-#define DDR4_PHYREF_VALUE 93
-#endif
-
-/* write DDR4 */
-#ifdef DDR_ONE_RANK
-/* one lank */
-#define DDR4_PHY_DATA_RON DDR4_PHY_DATA_RON_34
-#define DDR4_RTT_NOM DDR4_ODT_60
-#define DDR4_RTT_WR DDR4_RTT_WR_DIS
-#define DDR4_RTT_PARK DDR4_ODT_DIS
-#define DDR4_MR6_VALUE 0x0d
-#else
-/* two lank */
-#define DDR4_PHY_DATA_RON DDR4_PHY_DATA_RON_40
-#define DDR4_RTT_NOM DDR4_ODT_60
-#define DDR4_RTT_WR DDR4_RTT_WR_DIS
-#define DDR4_RTT_PARK DDR4_ODT_DIS
-#define DDR4_MR6_VALUE 0x10
-#endif
-
-/* voltage:delay */
-#define DDR4_2D_WEIGHT (31 << 8 | 127)
-
-#define ANAMIX_PLL_BASE_ADDR 0x30360000
-#define HW_DRAM_PLL_CFG0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x60)
-#define HW_DRAM_PLL_CFG1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x64)
-#define HW_DRAM_PLL_CFG2_ADDR (ANAMIX_PLL_BASE_ADDR + 0x68)
-#define GPC_PU_PWRHSK 0x303A01FC
-#define GPC_TOP_CONFIG_OFFSET 0x0000
-#define AIPS1_ARB_BASE_ADDR 0x30000000
-#define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
-#define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR + 0x200000)
-#define CCM_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x180000)
-#define CCM_SRC_CTRL_OFFSET (CCM_IPS_BASE_ADDR + 0x800)
-#define CCM_SRC_CTRL(n) (CCM_SRC_CTRL_OFFSET + 0x10 * n)
-
-
-#define dwc_ddrphy_apb_wr(addr, data) reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data)
-#define reg32clrbit(addr, bitpos) reg32_write((addr), (reg32_read((addr)) & (0xFFFFFFFF ^ (1 << (bitpos)))))
-#define DDR_CSD1_BASE_ADDR 0x40000000
-#define DDR_CSD2_BASE_ADDR 0x80000000
-
-void restore_1d2d_trained_csr_ddr4_p012(unsigned int addr);
-void save_1d2d_trained_csr_ddr4_p012(unsigned int addr);
-void ddr4_mr_write(unsigned int mr, unsigned int data, unsigned int read, unsigned int rank);
-void ddr4_phyinit_train_sw_ffc(unsigned int Train2D);
-
-#endif
diff --git a/board/freescale/imx8mm_val/ddr/ddr4/ddr4_phyinit_2400_400_100_2r_fw09.c b/board/freescale/imx8mm_val/ddr/ddr4/ddr4_phyinit_2400_400_100_2r_fw09.c
deleted file mode 100644
index eed33ea..0000000
--- a/board/freescale/imx8mm_val/ddr/ddr4/ddr4_phyinit_2400_400_100_2r_fw09.c
+++ /dev/null
@@ -1,1420 +0,0 @@
-/*
- * Copyright 2018 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/ddr.h>
-#include <asm/arch/clock.h>
-#include "ddr4_define.h"
-
-extern unsigned int after_retention;
-extern unsigned int mr_value[3][7];
-
-void ddr4_phyinit_train_sw_ffc(unsigned int Train2D)
-{
- /* [dwc_ddrphy_phyinit_main] Start of dwc_ddrphy_phyinit_main() */
- /* [dwc_ddrphy_phyinit_sequence] Start of dwc_ddrphy_phyinit_sequence() */
- /* [dwc_ddrphy_phyinit_initStruct] Start of dwc_ddrphy_phyinit_initStruct() */
- /* [dwc_ddrphy_phyinit_initStruct] End of dwc_ddrphy_phyinit_initStruct() */
- /* [dwc_ddrphy_phyinit_setDefault] Start of dwc_ddrphy_phyinit_setDefault() */
- /* [dwc_ddrphy_phyinit_setDefault] End of dwc_ddrphy_phyinit_setDefault() */
-
-
- /* ############################################################## */
- /* */
- /* dwc_ddrphy_phyinit_userCustom_overrideUserInput is a user-editable function. */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
-
- dwc_ddrphy_phyinit_userCustom_overrideUserInput ();
- /* */
- /* [dwc_ddrphy_phyinit_userCustom_overrideUserInput] End of dwc_ddrphy_phyinit_userCustom_overrideUserInput() */
-
-
- /* ############################################################## */
- /* */
- /* Step (A) : Bring up VDD, VDDQ, and VAA */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
-
-
- dwc_ddrphy_phyinit_userCustom_A_bringupPower ();
-
- /* [dwc_ddrphy_phyinit_userCustom_A_bringupPower] End of dwc_ddrphy_phyinit_userCustom_A_bringupPower() */
- /* [dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy] Start of dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* Step (B) Start Clocks and Reset the PHY */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- /* */
- dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy ();
-
- /* [dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy] End of dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy() */
- /* */
-
- /* ############################################################## */
- /* */
- /* Step (C) Initialize PHY Configuration */
- /* */
- /* Load the required PHY configuration registers for the appropriate mode and memory configuration */
- /* */
- /* ############################################################## */
- /* */
-
- /* [phyinit_C_initPhyConfig] Start of dwc_ddrphy_phyinit_C_initPhyConfig() */
- /* */
- /* ############################################################## */
- /* TxPreDrvMode[2] = 0 */
- /* ############################################################## */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TxSlewRate::TxPreDrvMode to 0x2 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TxSlewRate::TxPreP to 0xd */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TxSlewRate::TxPreN to 0xf */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for TxSlewRate::TxPreP and TxSlewRate::TxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x1005f, 0x2fd); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p0 */
- dwc_ddrphy_apb_wr(0x1015f, 0x2fd); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p0 */
- dwc_ddrphy_apb_wr(0x1105f, 0x2fd); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p0 */
- dwc_ddrphy_apb_wr(0x1115f, 0x2fd); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p0 */
- dwc_ddrphy_apb_wr(0x1205f, 0x2fd); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p0 */
- dwc_ddrphy_apb_wr(0x1215f, 0x2fd); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p0 */
- dwc_ddrphy_apb_wr(0x1305f, 0x2fd); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p0 */
- dwc_ddrphy_apb_wr(0x1315f, 0x2fd); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TxSlewRate::TxPreDrvMode to 0x2 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TxSlewRate::TxPreP to 0xd */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TxSlewRate::TxPreN to 0xf */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for TxSlewRate::TxPreP and TxSlewRate::TxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x11005f, 0x2fd); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p1 */
- dwc_ddrphy_apb_wr(0x11015f, 0x2fd); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p1 */
- dwc_ddrphy_apb_wr(0x11105f, 0x2fd); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p1 */
- dwc_ddrphy_apb_wr(0x11115f, 0x2fd); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p1 */
- dwc_ddrphy_apb_wr(0x11205f, 0x2fd); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p1 */
- dwc_ddrphy_apb_wr(0x11215f, 0x2fd); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p1 */
- dwc_ddrphy_apb_wr(0x11305f, 0x2fd); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p1 */
- dwc_ddrphy_apb_wr(0x11315f, 0x2fd); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TxSlewRate::TxPreDrvMode to 0x2 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TxSlewRate::TxPreP to 0xd */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TxSlewRate::TxPreN to 0xf */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for TxSlewRate::TxPreP and TxSlewRate::TxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x21005f, 0x2fd); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p2 */
- dwc_ddrphy_apb_wr(0x21015f, 0x2fd); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p2 */
- dwc_ddrphy_apb_wr(0x21105f, 0x2fd); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p2 */
- dwc_ddrphy_apb_wr(0x21115f, 0x2fd); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p2 */
- dwc_ddrphy_apb_wr(0x21205f, 0x2fd); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p2 */
- dwc_ddrphy_apb_wr(0x21215f, 0x2fd); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p2 */
- dwc_ddrphy_apb_wr(0x21305f, 0x2fd); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p2 */
- dwc_ddrphy_apb_wr(0x21315f, 0x2fd); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p2 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=0 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=0 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=0 */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x55, 0x355); /* DWC_DDRPHYA_ANIB0_ATxSlewRate */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=1 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=1 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=1 */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x1055, 0x355); /* DWC_DDRPHYA_ANIB1_ATxSlewRate */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=2 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=2 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=2 */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x2055, 0x355); /* DWC_DDRPHYA_ANIB2_ATxSlewRate */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=3 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=3 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=3 */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x3055, 0x355); /* DWC_DDRPHYA_ANIB3_ATxSlewRate */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x0, ANIB=4 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=4 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=4 */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x4055, 0x55); /* DWC_DDRPHYA_ANIB4_ATxSlewRate */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x0, ANIB=5 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=5 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=5 */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x5055, 0x55); /* DWC_DDRPHYA_ANIB5_ATxSlewRate */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=6 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=6 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=6 */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x6055, 0x355); /* DWC_DDRPHYA_ANIB6_ATxSlewRate */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=7 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=7 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=7 */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x7055, 0x355); /* DWC_DDRPHYA_ANIB7_ATxSlewRate */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=8 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=8 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=8 */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x8055, 0x355); /* DWC_DDRPHYA_ANIB8_ATxSlewRate */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreDrvMode to 0x3, ANIB=9 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreP to 0x5, ANIB=9 */
- /* [phyinit_C_initPhyConfig] Programming ATxSlewRate::ATxPreN to 0x5, ANIB=9 */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::ATxPreP and ATxSlewRate::ATxPreP are technology specific. */
- /* [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings */
-
- dwc_ddrphy_apb_wr(0x9055, 0x355); /* DWC_DDRPHYA_ANIB9_ATxSlewRate */
- dwc_ddrphy_apb_wr(0x200c5, 0xa); /* DWC_DDRPHYA_MASTER0_PllCtrl2_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming PllCtrl2 to a based on DfiClk frequency = 600. */
- dwc_ddrphy_apb_wr(0x1200c5, 0x7); /* DWC_DDRPHYA_MASTER0_PllCtrl2_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming PllCtrl2 to 7 based on DfiClk frequency = 100. */
- dwc_ddrphy_apb_wr(0x2200c5, 0x7); /* DWC_DDRPHYA_MASTER0_PllCtrl2_p2 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming PllCtrl2 to 7 based on DfiClk frequency = 25. */
- /* */
- /* ############################################################## */
- /* */
- /* Program ARdPtrInitVal based on Frequency and PLL Bypass inputs */
- /* The values programmed here assume ideal properties of DfiClk */
- /* and Pclk including: */
- /* - DfiClk skew */
- /* - DfiClk jitter */
- /* - DfiClk PVT variations */
- /* - Pclk skew */
- /* - Pclk jitter */
- /* */
- /* PLL Bypassed mode: */
- /* For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 2-6 */
- /* For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-6 */
- /* */
- /* PLL Enabled mode: */
- /* For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-6 */
- /* For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 0-6 */
- /* */
- /* ############################################################## */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming ARdPtrInitVal to 0x2 */
- dwc_ddrphy_apb_wr(0x2002e, 0x2); /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming ARdPtrInitVal to 0x2 */
- dwc_ddrphy_apb_wr(0x12002e, 0x2); /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming ARdPtrInitVal to 0x2 */
- dwc_ddrphy_apb_wr(0x22002e, 0x2); /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p2 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DqsPreambleControl::TwoTckRxDqsPre to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DqsPreambleControl::TwoTckTxDqsPre to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DqsPreambleControl::PositionDfeInit to 0x2 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DqsPreambleControl::LP4TglTwoTckTxDqsPre to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DqsPreambleControl::LP4PostambleExt to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DqsPreambleControl::LP4SttcPreBridgeRxEn to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DqsPreambleControl to 0x8 */
- dwc_ddrphy_apb_wr(0x20024, 0x8); /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DbyteDllModeCntrl to 0x2 */
- dwc_ddrphy_apb_wr(0x2003a, 0x2); /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DqsPreambleControl::TwoTckRxDqsPre to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DqsPreambleControl::TwoTckTxDqsPre to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DqsPreambleControl::PositionDfeInit to 0x2 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DqsPreambleControl::LP4TglTwoTckTxDqsPre to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DqsPreambleControl::LP4PostambleExt to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DqsPreambleControl::LP4SttcPreBridgeRxEn to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DqsPreambleControl to 0x8 */
- dwc_ddrphy_apb_wr(0x120024, 0x8); /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DbyteDllModeCntrl to 0x2 */
- dwc_ddrphy_apb_wr(0x2003a, 0x2); /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DqsPreambleControl::TwoTckRxDqsPre to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DqsPreambleControl::TwoTckTxDqsPre to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DqsPreambleControl::PositionDfeInit to 0x2 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DqsPreambleControl::LP4TglTwoTckTxDqsPre to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DqsPreambleControl::LP4PostambleExt to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DqsPreambleControl::LP4SttcPreBridgeRxEn to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DqsPreambleControl to 0x8 */
- dwc_ddrphy_apb_wr(0x220024, 0x8); /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p2 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DbyteDllModeCntrl to 0x2 */
- dwc_ddrphy_apb_wr(0x2003a, 0x2); /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming ProcOdtTimeCtl to 0x6 */
- dwc_ddrphy_apb_wr(0x20056, 0x6); /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming ProcOdtTimeCtl to 0xa */
- dwc_ddrphy_apb_wr(0x120056, 0xa); /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming ProcOdtTimeCtl to 0xa */
- dwc_ddrphy_apb_wr(0x220056, 0xa); /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p2 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TxOdtDrvStren::ODTStrenP to 0x1a */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TxOdtDrvStren::ODTStrenN to 0x0 */
- dwc_ddrphy_apb_wr(0x1004d, 0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p0 */
- dwc_ddrphy_apb_wr(0x1014d, 0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p0 */
- dwc_ddrphy_apb_wr(0x1104d, 0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p0 */
- dwc_ddrphy_apb_wr(0x1114d, 0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p0 */
- dwc_ddrphy_apb_wr(0x1204d, 0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p0 */
- dwc_ddrphy_apb_wr(0x1214d, 0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p0 */
- dwc_ddrphy_apb_wr(0x1304d, 0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p0 */
- dwc_ddrphy_apb_wr(0x1314d, 0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TxOdtDrvStren::ODTStrenP to 0x1a */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TxOdtDrvStren::ODTStrenN to 0x0 */
- dwc_ddrphy_apb_wr(0x11004d, 0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p1 */
- dwc_ddrphy_apb_wr(0x11014d, 0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p1 */
- dwc_ddrphy_apb_wr(0x11104d, 0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p1 */
- dwc_ddrphy_apb_wr(0x11114d, 0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p1 */
- dwc_ddrphy_apb_wr(0x11204d, 0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p1 */
- dwc_ddrphy_apb_wr(0x11214d, 0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p1 */
- dwc_ddrphy_apb_wr(0x11304d, 0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p1 */
- dwc_ddrphy_apb_wr(0x11314d, 0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TxOdtDrvStren::ODTStrenP to 0x1a */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TxOdtDrvStren::ODTStrenN to 0x0 */
- dwc_ddrphy_apb_wr(0x21004d, 0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p2 */
- dwc_ddrphy_apb_wr(0x21014d, 0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p2 */
- dwc_ddrphy_apb_wr(0x21104d, 0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p2 */
- dwc_ddrphy_apb_wr(0x21114d, 0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p2 */
- dwc_ddrphy_apb_wr(0x21204d, 0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p2 */
- dwc_ddrphy_apb_wr(0x21214d, 0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p2 */
- dwc_ddrphy_apb_wr(0x21304d, 0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p2 */
- dwc_ddrphy_apb_wr(0x21314d, 0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p2 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqP to 0x38 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqN to 0x38 */
- dwc_ddrphy_apb_wr(0x10049, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p0 */
- dwc_ddrphy_apb_wr(0x10149, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p0 */
- dwc_ddrphy_apb_wr(0x11049, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p0 */
- dwc_ddrphy_apb_wr(0x11149, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p0 */
- dwc_ddrphy_apb_wr(0x12049, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p0 */
- dwc_ddrphy_apb_wr(0x12149, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p0 */
- dwc_ddrphy_apb_wr(0x13049, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p0 */
- dwc_ddrphy_apb_wr(0x13149, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqP to 0x38 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqN to 0x38 */
- dwc_ddrphy_apb_wr(0x110049, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p1 */
- dwc_ddrphy_apb_wr(0x110149, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p1 */
- dwc_ddrphy_apb_wr(0x111049, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p1 */
- dwc_ddrphy_apb_wr(0x111149, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p1 */
- dwc_ddrphy_apb_wr(0x112049, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p1 */
- dwc_ddrphy_apb_wr(0x112149, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p1 */
- dwc_ddrphy_apb_wr(0x113049, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p1 */
- dwc_ddrphy_apb_wr(0x113149, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqP to 0x38 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqN to 0x38 */
- dwc_ddrphy_apb_wr(0x210049, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p2 */
- dwc_ddrphy_apb_wr(0x210149, 0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p2 */
- dwc_ddrphy_apb_wr(0x211049, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p2 */
- dwc_ddrphy_apb_wr(0x211149, 0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p2 */
- dwc_ddrphy_apb_wr(0x212049, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p2 */
- dwc_ddrphy_apb_wr(0x212149, 0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p2 */
- dwc_ddrphy_apb_wr(0x213049, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p2 */
- dwc_ddrphy_apb_wr(0x213149, 0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p2 */
- /* [phyinit_C_initPhyConfig] Programming ATxImpedance::ADrvStrenP to 0x3 */
- /* [phyinit_C_initPhyConfig] Programming ATxImpedance::ADrvStrenN to 0x3 */
- dwc_ddrphy_apb_wr(0x43, 0x63); /* DWC_DDRPHYA_ANIB0_ATxImpedance */
- dwc_ddrphy_apb_wr(0x1043, 0x63); /* DWC_DDRPHYA_ANIB1_ATxImpedance */
- dwc_ddrphy_apb_wr(0x2043, 0x63); /* DWC_DDRPHYA_ANIB2_ATxImpedance */
- dwc_ddrphy_apb_wr(0x3043, 0x63); /* DWC_DDRPHYA_ANIB3_ATxImpedance */
- dwc_ddrphy_apb_wr(0x4043, 0x63); /* DWC_DDRPHYA_ANIB4_ATxImpedance */
- dwc_ddrphy_apb_wr(0x5043, 0x63); /* DWC_DDRPHYA_ANIB5_ATxImpedance */
- dwc_ddrphy_apb_wr(0x6043, 0x63); /* DWC_DDRPHYA_ANIB6_ATxImpedance */
- dwc_ddrphy_apb_wr(0x7043, 0x63); /* DWC_DDRPHYA_ANIB7_ATxImpedance */
- dwc_ddrphy_apb_wr(0x8043, 0x63); /* DWC_DDRPHYA_ANIB8_ATxImpedance */
- dwc_ddrphy_apb_wr(0x9043, 0x63); /* DWC_DDRPHYA_ANIB9_ATxImpedance */
- /* [phyinit_C_initPhyConfig] Programming DfiMode to 0x5 */
- dwc_ddrphy_apb_wr(0x20018, 0x5); /* DWC_DDRPHYA_MASTER0_DfiMode */
- /* [phyinit_C_initPhyConfig] Programming DfiCAMode to 0x2 */
- dwc_ddrphy_apb_wr(0x20075, 0x2); /* DWC_DDRPHYA_MASTER0_DfiCAMode */
- /* [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPd50 to 0x0 */
- /* [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPu50 to 0x0 */
- dwc_ddrphy_apb_wr(0x20050, 0x0); /* DWC_DDRPHYA_MASTER0_CalDrvStr0 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming CalUclkInfo::CalUClkTicksPer1uS to 0x258 */
- dwc_ddrphy_apb_wr(0x20008, 0x258); /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming CalUclkInfo::CalUClkTicksPer1uS to 0x64 */
- dwc_ddrphy_apb_wr(0x120008, 0x64); /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming CalUclkInfo::CalUClkTicksPer1uS to 0x19 */
- dwc_ddrphy_apb_wr(0x220008, 0x19); /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p2 */
- /* [phyinit_C_initPhyConfig] Programming CalRate::CalInterval to 0x9 */
- /* [phyinit_C_initPhyConfig] Programming CalRate::CalOnce to 0x0 */
- dwc_ddrphy_apb_wr(0x20088, 0x9); /* DWC_DDRPHYA_MASTER0_CalRate */
- /* [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInSel to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInDAC to 0x4d */
- /* [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal to 0x268 */
- dwc_ddrphy_apb_wr(0x200b2, 0x268); /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl::MajorModeDbyte to 0x3 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl to 0x5b1 */
- dwc_ddrphy_apb_wr(0x10043, 0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p0 */
- dwc_ddrphy_apb_wr(0x10143, 0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p0 */
- dwc_ddrphy_apb_wr(0x11043, 0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p0 */
- dwc_ddrphy_apb_wr(0x11143, 0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p0 */
- dwc_ddrphy_apb_wr(0x12043, 0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p0 */
- dwc_ddrphy_apb_wr(0x12143, 0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p0 */
- dwc_ddrphy_apb_wr(0x13043, 0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p0 */
- dwc_ddrphy_apb_wr(0x13143, 0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Programming VrefInGlobal::GlobalVrefInSel to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Programming VrefInGlobal::GlobalVrefInDAC to 0x4d */
- /* [phyinit_C_initPhyConfig] Pstate=1, Programming VrefInGlobal to 0x268 */
- dwc_ddrphy_apb_wr(0x1200b2, 0x268); /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Programming DqDqsRcvCntrl::MajorModeDbyte to 0x3 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Programming DqDqsRcvCntrl to 0x5b1 */
- dwc_ddrphy_apb_wr(0x110043, 0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p1 */
- dwc_ddrphy_apb_wr(0x110143, 0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p1 */
- dwc_ddrphy_apb_wr(0x111043, 0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p1 */
- dwc_ddrphy_apb_wr(0x111143, 0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p1 */
- dwc_ddrphy_apb_wr(0x112043, 0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p1 */
- dwc_ddrphy_apb_wr(0x112143, 0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p1 */
- dwc_ddrphy_apb_wr(0x113043, 0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p1 */
- dwc_ddrphy_apb_wr(0x113143, 0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Programming VrefInGlobal::GlobalVrefInSel to 0x0 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Programming VrefInGlobal::GlobalVrefInDAC to 0x4d */
- /* [phyinit_C_initPhyConfig] Pstate=2, Programming VrefInGlobal to 0x268 */
- dwc_ddrphy_apb_wr(0x2200b2, 0x268); /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p2 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Programming DqDqsRcvCntrl::MajorModeDbyte to 0x3 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Programming DqDqsRcvCntrl to 0x5b1 */
- dwc_ddrphy_apb_wr(0x210043, 0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p2 */
- dwc_ddrphy_apb_wr(0x210143, 0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p2 */
- dwc_ddrphy_apb_wr(0x211043, 0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p2 */
- dwc_ddrphy_apb_wr(0x211143, 0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p2 */
- dwc_ddrphy_apb_wr(0x212043, 0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p2 */
- dwc_ddrphy_apb_wr(0x212143, 0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p2 */
- dwc_ddrphy_apb_wr(0x213043, 0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p2 */
- dwc_ddrphy_apb_wr(0x213143, 0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p2 */
- /* [phyinit_C_initPhyConfig] Programming MemAlertControl::MALERTVrefLevel to 0x29 */
- /* [phyinit_C_initPhyConfig] Programming MemAlertControl::MALERTPuStren to 0x5 */
- /* [phyinit_C_initPhyConfig] Programming MemAlertControl to 0x7529 */
- /* [phyinit_C_initPhyConfig] Programming MemAlertControl2::MALERTSyncBypass to 0x0 */
- dwc_ddrphy_apb_wr(0x2005b, 0x7529); /* DWC_DDRPHYA_MASTER0_MemAlertControl */
- dwc_ddrphy_apb_wr(0x2005c, 0x0); /* DWC_DDRPHYA_MASTER0_MemAlertControl2 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DfiFreqRatio_p0 to 0x1 */
- dwc_ddrphy_apb_wr(0x200fa, 0x1); /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DfiFreqRatio_p1 to 0x1 */
- dwc_ddrphy_apb_wr(0x1200fa, 0x1); /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DfiFreqRatio_p2 to 0x1 */
- dwc_ddrphy_apb_wr(0x2200fa, 0x1); /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p2 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TristateModeCA::DisDynAdrTri_p0 to 0x1 */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming TristateModeCA::DDR2TMode_p0 to 0x0 */
- dwc_ddrphy_apb_wr(0x20019, 0x5); /* DWC_DDRPHYA_MASTER0_TristateModeCA_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TristateModeCA::DisDynAdrTri_p1 to 0x1 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming TristateModeCA::DDR2TMode_p1 to 0x0 */
- dwc_ddrphy_apb_wr(0x120019, 0x5); /* DWC_DDRPHYA_MASTER0_TristateModeCA_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TristateModeCA::DisDynAdrTri_p2 to 0x1 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming TristateModeCA::DDR2TMode_p2 to 0x0 */
- dwc_ddrphy_apb_wr(0x220019, 0x5); /* DWC_DDRPHYA_MASTER0_TristateModeCA_p2 */
- /* [phyinit_C_initPhyConfig] Programming DfiFreqXlat* */
- dwc_ddrphy_apb_wr(0x200f0, 0x5665); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat0 */
- dwc_ddrphy_apb_wr(0x200f1, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat1 */
- dwc_ddrphy_apb_wr(0x200f2, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat2 */
- dwc_ddrphy_apb_wr(0x200f3, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat3 */
- dwc_ddrphy_apb_wr(0x200f4, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat4 */
- dwc_ddrphy_apb_wr(0x200f5, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat5 */
- dwc_ddrphy_apb_wr(0x200f6, 0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat6 */
- dwc_ddrphy_apb_wr(0x200f7, 0xf000); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat7 */
- /* [phyinit_C_initPhyConfig] Programming MasterX4Config::X4TG to 0x0 */
- dwc_ddrphy_apb_wr(0x20025, 0x0); /* DWC_DDRPHYA_MASTER0_MasterX4Config */
- /* [phyinit_C_initPhyConfig] Pstate=0, Memclk=1200MHz, Programming DMIPinPresent::RdDbiEnabled to 0x0 */
- dwc_ddrphy_apb_wr(0x2002d, 0x0); /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p0 */
- /* [phyinit_C_initPhyConfig] Pstate=1, Memclk=200MHz, Programming DMIPinPresent::RdDbiEnabled to 0x0 */
- dwc_ddrphy_apb_wr(0x12002d, 0x0); /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p1 */
- /* [phyinit_C_initPhyConfig] Pstate=2, Memclk=50MHz, Programming DMIPinPresent::RdDbiEnabled to 0x0 */
- dwc_ddrphy_apb_wr(0x22002d, 0x0); /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p2 */
- /* [phyinit_C_initPhyConfig] End of dwc_ddrphy_phyinit_C_initPhyConfig() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* dwc_ddrphy_phyihunit_userCustom_customPreTrain is a user-editable function. */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- ddr_dbg("add 845S pll setting in phyinit\n");
- /* [phyinit_userCustom_customPreTrain] Start of dwc_ddrphy_phyinit_userCustom_customPreTrain() */
- dwc_ddrphy_apb_wr(0x200c7, 0x21); /* DWC_DDRPHYA_MASTER0_PllCtrl1_p0 */
- dwc_ddrphy_apb_wr(0x200ca, 0x24); /* DWC_DDRPHYA_MASTER0_PllTestMode_p0 */
- /* [phyinit_userCustom_customPreTrain] End of dwc_ddrphy_phyinit_userCustom_customPreTrain() */
- /* [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Start of dwc_ddrphy_phyinit_D_loadIMEM (Train2D=0) */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (D) Load the 1D IMEM image */
- /* */
- /* This function loads the training firmware IMEM image into the SRAM. */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- /* */
- /* [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Programming MemResetL to 0x2 */
- if (!after_retention) {
- dwc_ddrphy_apb_wr(0x20060, 0x2);
-
- /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr4/ddr4_pmu_train_imem.incv */
-
- /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
- /* This allows the memory controller unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x50000 size 0x4000 */
- /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x4000 */
- /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
- /* This allows the firmware unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [dwc_ddrphy_phyinit_D_loadIMEM, 1D] End of dwc_ddrphy_phyinit_D_loadIMEM() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* Step (E) Set the PHY input clocks to the desired frequency for pstate 0 */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- /* dwc_ddrphy_phyinit_userCustom_E_setDfiClk (0); */
-
- /* */
- /* [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() */
- /* [phyinit_F_loadDMEM, 1D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=0, Train2D=0) */
-
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* for test on silicon, load 1D dmem/imem here */
-#ifdef CONFIG_SPL_VSI_FW_LOADING
- load_train_1d_code();
-#else
- ddr_load_train_code(FW_1D_IMAGE);
-#endif
- ddr_dbg("start 1d train\n");
-
- /* */
- /* ############################################################## */
- /* */
- /* (F) Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr4/ddr4_pmu_train_dmem.incv */
-
- /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
- /* This allows the memory controller unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x54000 size 0x36a */
-#ifdef RUN_ON_SILICON
- dwc_ddrphy_apb_wr(0x54000, 0x0);
-#else
- dwc_ddrphy_apb_wr(0x54000, 0x600);
-#endif
- dwc_ddrphy_apb_wr(0x54001, 0x0);
- dwc_ddrphy_apb_wr(0x54002, 0x0);
- dwc_ddrphy_apb_wr(0x54003, 0x960);
- dwc_ddrphy_apb_wr(0x54004, 0x2);
- dwc_ddrphy_apb_wr(0x54005, 0x0);
- dwc_ddrphy_apb_wr(0x54006, 0x25e);
- dwc_ddrphy_apb_wr(0x54007, 0x2000);
-#ifdef DDR_ONE_RANK
- dwc_ddrphy_apb_wr(0x54008, 0x101);
- dwc_ddrphy_apb_wr(0x54009, 0x0);
-#else
- dwc_ddrphy_apb_wr(0x54008, 0x303);
- dwc_ddrphy_apb_wr(0x54009, 0x200);/* no addr mirror, 0x200 addr mirror */
-#endif
- dwc_ddrphy_apb_wr(0x5400a, 0x0);
-#ifdef RUN_ON_SILICON
- dwc_ddrphy_apb_wr(0x5400b, 0x31f);
-#else
- dwc_ddrphy_apb_wr(0x5400b, 0x1);
-#endif
- dwc_ddrphy_apb_wr(0x5400c, 0xc8);
- dwc_ddrphy_apb_wr(0x5400d, 0x0);
- dwc_ddrphy_apb_wr(0x5400e, 0x0);
- dwc_ddrphy_apb_wr(0x5400f, 0x0);
- dwc_ddrphy_apb_wr(0x54010, 0x0);
- dwc_ddrphy_apb_wr(0x54011, 0x0);
- dwc_ddrphy_apb_wr(0x54012, 0x1);
- dwc_ddrphy_apb_wr(0x5402f, mr_value[0][0]);
- dwc_ddrphy_apb_wr(0x54030, mr_value[0][1]);
- dwc_ddrphy_apb_wr(0x54031, mr_value[0][2]);
- dwc_ddrphy_apb_wr(0x54032, mr_value[0][3]);
- dwc_ddrphy_apb_wr(0x54033, mr_value[0][4]);
- dwc_ddrphy_apb_wr(0x54034, mr_value[0][5]);
- dwc_ddrphy_apb_wr(0x54035, mr_value[0][6]);
-
-#ifdef DDR_ONE_RANK
- dwc_ddrphy_apb_wr(0x54036, 0x101);
-#else
- dwc_ddrphy_apb_wr(0x54036, 0x103);
-#endif
- dwc_ddrphy_apb_wr(0x54037, 0x0);
- dwc_ddrphy_apb_wr(0x54038, 0x0);
- dwc_ddrphy_apb_wr(0x54039, 0x0);
- dwc_ddrphy_apb_wr(0x5403a, 0x0);
- dwc_ddrphy_apb_wr(0x5403b, 0x0);
- dwc_ddrphy_apb_wr(0x5403c, 0x0);
- dwc_ddrphy_apb_wr(0x5403d, 0x0);
- dwc_ddrphy_apb_wr(0x5403e, 0x0);
- dwc_ddrphy_apb_wr(0x5403f, 0x1221);
- dwc_ddrphy_apb_wr(0x541fc, 0x100);
- /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x36a */
- /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
- /* This allows the firmware unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [phyinit_F_loadDMEM, 1D] End of dwc_ddrphy_phyinit_F_loadDMEM() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (G) Execute the Training Firmware */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- /* */
- /* 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and */
- /* ResetToMicro fields to 1 (all other fields should be zero). */
- /* Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- dwc_ddrphy_apb_wr(0xd0099, 0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- /* */
- /* 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. */
- dwc_ddrphy_apb_wr(0xd0099, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- /* */
- /* 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" */
- /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] Wait for the training firmware to complete. */
- /* Implement timeout fucntion or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. */
- dwc_ddrphy_phyinit_userCustom_G_waitFwDone ();
-
- /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() */
- /* 4. Halt the microcontroller." */
- dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- /* [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW () */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (H) Read the Message Block results */
- /* */
- /* The procedure is as follows: */
- /* */
- /* ############################################################## */
- /* */
- /* */
- /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* */
- /* 2. Read the Firmware Message Block to obtain the results from the training. */
- /* This can be accomplished by issuing APB read commands to the DMEM addresses. */
- /* Example: */
- /* if (Train2D) */
- /* { */
- /* _read_2d_message_block_outputs_ */
- /* } */
- /* else */
- /* { */
- /* _read_1d_message_block_outputs_ */
- /* } */
- dwc_ddrphy_phyinit_userCustom_H_readMsgBlock (0);
-
- /* [dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock () */
- /* 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* 4. If training is required at another frequency, repeat the operations starting at step (E). */
- /* [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* Step (E) Set the PHY input clocks to the desired frequency for pstate 1 */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
-#ifdef DDR4_SW_FFC
- dwc_ddrphy_phyinit_userCustom_E_setDfiClk (1);
-
- /* */
- /* [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() */
- /* [phyinit_F_loadDMEM, 1D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=1, Train2D=0) */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (F) Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr4/ddr4_pmu_train_dmem.incv */
-
- /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
- /* This allows the memory controller unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x54000 size 0x36a */
-#ifdef RUN_ON_SILICON
- dwc_ddrphy_apb_wr(0x54000, 0x0);
-#else
- dwc_ddrphy_apb_wr(0x54000, 0x600);
-#endif
- dwc_ddrphy_apb_wr(0x54001, 0x0);
- dwc_ddrphy_apb_wr(0x54002, 0x101);
- dwc_ddrphy_apb_wr(0x54003, 0x190);
- dwc_ddrphy_apb_wr(0x54004, 0x2);
- dwc_ddrphy_apb_wr(0x54005, 0x0);
- dwc_ddrphy_apb_wr(0x54006, 0x25e);
- dwc_ddrphy_apb_wr(0x54007, 0x2000);
-#ifdef DDR_ONE_RANK
- dwc_ddrphy_apb_wr(0x54008, 0x101);
- dwc_ddrphy_apb_wr(0x54009, 0x0);
-#else
- dwc_ddrphy_apb_wr(0x54008, 0x303);
- dwc_ddrphy_apb_wr(0x54009, 0x200);
-#endif
- dwc_ddrphy_apb_wr(0x5400a, 0x0);
-#ifdef RUN_ON_SILICON
- dwc_ddrphy_apb_wr(0x5400b, 0x21f);
-#else
- dwc_ddrphy_apb_wr(0x5400b, 0x5);
-#endif
- dwc_ddrphy_apb_wr(0x5400c, 0xc8);
- dwc_ddrphy_apb_wr(0x5400d, 0x0);
- dwc_ddrphy_apb_wr(0x5400e, 0x0);
- dwc_ddrphy_apb_wr(0x5400f, 0x0);
- dwc_ddrphy_apb_wr(0x54010, 0x0);
- dwc_ddrphy_apb_wr(0x54011, 0x0);
- dwc_ddrphy_apb_wr(0x54012, 0x1);
- dwc_ddrphy_apb_wr(0x5402f, mr_value[1][0]);
- dwc_ddrphy_apb_wr(0x54030, mr_value[1][1]);
- dwc_ddrphy_apb_wr(0x54031, mr_value[1][2]);
- dwc_ddrphy_apb_wr(0x54032, mr_value[1][3]);
- dwc_ddrphy_apb_wr(0x54033, mr_value[1][4]);
- dwc_ddrphy_apb_wr(0x54034, mr_value[1][5]);
- dwc_ddrphy_apb_wr(0x54035, mr_value[1][6]);
-
-#ifdef DDR_ONE_RANK
- dwc_ddrphy_apb_wr(0x54036, 0x101);
-#else
- dwc_ddrphy_apb_wr(0x54036, 0x103);
-#endif
- dwc_ddrphy_apb_wr(0x54037, 0x0);
- dwc_ddrphy_apb_wr(0x54038, 0x0);
- dwc_ddrphy_apb_wr(0x54039, 0x0);
- dwc_ddrphy_apb_wr(0x5403a, 0x0);
- dwc_ddrphy_apb_wr(0x5403b, 0x0);
- dwc_ddrphy_apb_wr(0x5403c, 0x0);
- dwc_ddrphy_apb_wr(0x5403d, 0x0);
- dwc_ddrphy_apb_wr(0x5403e, 0x0);
- dwc_ddrphy_apb_wr(0x5403f, 0x1221);
- dwc_ddrphy_apb_wr(0x541fc, 0x100);
- /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x36a */
- /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
- /* This allows the firmware unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [phyinit_F_loadDMEM, 1D] End of dwc_ddrphy_phyinit_F_loadDMEM() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (G) Execute the Training Firmware */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- /* */
- /* 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and */
- /* ResetToMicro fields to 1 (all other fields should be zero). */
- /* Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- dwc_ddrphy_apb_wr(0xd0099, 0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- /* */
- /* 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. */
- dwc_ddrphy_apb_wr(0xd0099, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- /* */
- /* 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" */
- /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] Wait for the training firmware to complete. Implement timeout fucntion or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. */
- dwc_ddrphy_phyinit_userCustom_G_waitFwDone ();
-
- /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() */
- /* 4. Halt the microcontroller." */
- dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- /* [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW () */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (H) Read the Message Block results */
- /* */
- /* The procedure is as follows: */
- /* */
- /* ############################################################## */
- /* */
- /* */
- /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* */
- /* 2. Read the Firmware Message Block to obtain the results from the training. */
- /* This can be accomplished by issuing APB read commands to the DMEM addresses. */
- /* Example: */
- /* if (Train2D) */
- /* { */
- /* _read_2d_message_block_outputs_ */
- /* } */
- /* else */
- /* { */
- /* _read_1d_message_block_outputs_ */
- /* } */
- dwc_ddrphy_phyinit_userCustom_H_readMsgBlock (0);
-
- /* [dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock () */
- /* 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* 4. If training is required at another frequency, repeat the operations starting at step (E). */
- /* [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* Step (E) Set the PHY input clocks to the desired frequency for pstate 2 */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- dwc_ddrphy_phyinit_userCustom_E_setDfiClk (2);
-
- /* */
- /* [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() */
- /* [phyinit_F_loadDMEM, 1D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=2, Train2D=0) */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (F) Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr4/ddr4_pmu_train_dmem.incv */
-
- /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
- /* This allows the memory controller unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x54000 size 0x36a */
-#ifdef RUN_ON_SILICON
- dwc_ddrphy_apb_wr(0x54000, 0x0);
-#else
- dwc_ddrphy_apb_wr(0x54000, 0x600);
-#endif
- dwc_ddrphy_apb_wr(0x54001, 0x0);
- dwc_ddrphy_apb_wr(0x54002, 0x102);
- dwc_ddrphy_apb_wr(0x54003, 0x64);
- dwc_ddrphy_apb_wr(0x54004, 0x2);
- dwc_ddrphy_apb_wr(0x54005, 0x0);
- dwc_ddrphy_apb_wr(0x54006, 0x25e);
- dwc_ddrphy_apb_wr(0x54007, 0x2000);
-#ifdef DDR_ONE_RANK
- dwc_ddrphy_apb_wr(0x54008, 0x101);
- dwc_ddrphy_apb_wr(0x54009, 0x0);
-#else
- dwc_ddrphy_apb_wr(0x54008, 0x303);
- dwc_ddrphy_apb_wr(0x54009, 0x200);
-#endif
- dwc_ddrphy_apb_wr(0x5400a, 0x0);
-#ifdef RUN_ON_SILICON
- dwc_ddrphy_apb_wr(0x5400b, 0x21f);
-#else
- dwc_ddrphy_apb_wr(0x5400b, 0x5);
-#endif
- dwc_ddrphy_apb_wr(0x5400c, 0xc8);
- dwc_ddrphy_apb_wr(0x5400d, 0x0);
- dwc_ddrphy_apb_wr(0x5400e, 0x0);
- dwc_ddrphy_apb_wr(0x5400f, 0x0);
- dwc_ddrphy_apb_wr(0x54010, 0x0);
- dwc_ddrphy_apb_wr(0x54011, 0x0);
- dwc_ddrphy_apb_wr(0x54012, 0x1);
- dwc_ddrphy_apb_wr(0x5402f, mr_value[2][0]);
- dwc_ddrphy_apb_wr(0x54030, mr_value[2][1]);
- dwc_ddrphy_apb_wr(0x54031, mr_value[2][2]);
- dwc_ddrphy_apb_wr(0x54032, mr_value[2][3]);
- dwc_ddrphy_apb_wr(0x54033, mr_value[2][4]);
- dwc_ddrphy_apb_wr(0x54034, mr_value[2][5]);
- dwc_ddrphy_apb_wr(0x54035, mr_value[2][6]);
-
-#ifdef DDR_ONE_RANK
- dwc_ddrphy_apb_wr(0x54036, 0x101);
-#else
- dwc_ddrphy_apb_wr(0x54036, 0x103);
-#endif
- dwc_ddrphy_apb_wr(0x54037, 0x0);
- dwc_ddrphy_apb_wr(0x54038, 0x0);
- dwc_ddrphy_apb_wr(0x54039, 0x0);
- dwc_ddrphy_apb_wr(0x5403a, 0x0);
- dwc_ddrphy_apb_wr(0x5403b, 0x0);
- dwc_ddrphy_apb_wr(0x5403c, 0x0);
- dwc_ddrphy_apb_wr(0x5403d, 0x0);
- dwc_ddrphy_apb_wr(0x5403e, 0x0);
- dwc_ddrphy_apb_wr(0x5403f, 0x1221);
- dwc_ddrphy_apb_wr(0x541fc, 0x100);
- /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x36a */
- /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
- /* This allows the firmware unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [phyinit_F_loadDMEM, 1D] End of dwc_ddrphy_phyinit_F_loadDMEM() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (G) Execute the Training Firmware */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- /* */
- /* 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and */
- /* ResetToMicro fields to 1 (all other fields should be zero). */
- /* Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- dwc_ddrphy_apb_wr(0xd0099, 0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- /* */
- /* 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. */
- dwc_ddrphy_apb_wr(0xd0099, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- /* */
- /* 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" */
- /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] Wait for the training firmware to complete. Implement timeout fucntion or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. */
- dwc_ddrphy_phyinit_userCustom_G_waitFwDone ();
-
- /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() */
- /* 4. Halt the microcontroller." */
- dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- /* [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW () */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (H) Read the Message Block results */
- /* */
- /* The procedure is as follows: */
- /* */
- /* ############################################################## */
- /* */
- /* */
- /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* */
- /* 2. Read the Firmware Message Block to obtain the results from the training. */
- /* This can be accomplished by issuing APB read commands to the DMEM addresses. */
- /* Example: */
- /* if (Train2D) */
- /* { */
- /* _read_2d_message_block_outputs_ */
- /* } */
- /* else */
- /* { */
- /* _read_1d_message_block_outputs_ */
- /* } */
- dwc_ddrphy_phyinit_userCustom_H_readMsgBlock (0);
-
- /* [dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock () */
- /* 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* 4. If training is required at another frequency, repeat the operations starting at step (E). */
- /* [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* Step (E) Set the PHY input clocks to the desired frequency for pstate 0 */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- dwc_ddrphy_phyinit_userCustom_E_setDfiClk (0);
-#endif /* DDR4_SW_FFC */
-
- /* */
- /* [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() */
- /* [dwc_ddrphy_phyinit_D_loadIMEM, 2D] Start of dwc_ddrphy_phyinit_D_loadIMEM (Train2D=1) */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (D) Load the 2D IMEM image */
- /* */
- /* This function loads the training firmware IMEM image into the SRAM. */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- /* */
- /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr4_2d/ddr4_2d_pmu_train_imem.incv */
-
- /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
- /* This allows the memory controller unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x50000 size 0x4000 */
- /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x4000 */
- /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
- /* This allows the firmware unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [dwc_ddrphy_phyinit_D_loadIMEM, 2D] End of dwc_ddrphy_phyinit_D_loadIMEM() */
- /* [phyinit_F_loadDMEM, 2D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=0, Train2D=1) */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (F) Load the 2D DMEM image and write the 2D Message Block parameters for the training firmware */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- /* [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: ../../../../firmware/A-2017.09/ddr4_2d/ddr4_2d_pmu_train_dmem.incv */
-
- ddr_dbg("C: 1D training done!!! \n");
-
- if (Train2D) {
- /* for test on silicon, load 2D dmem/imem here */
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
-#ifdef CONFIG_SPL_VSI_FW_LOADING
- load_train_2d_code();
-#else
- ddr_load_train_code(FW_2D_IMAGE);
-#endif
- ddr_dbg("start 2d train\n");
-
- /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
- /* This allows the memory controller unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [dwc_ddrphy_phyinit_WriteOutMem] STARTING. offset 0x54000 size 0x2d6 */
-#ifdef RUN_ON_SILICON
- dwc_ddrphy_apb_wr(0x54000, 0x0);
-#else
- dwc_ddrphy_apb_wr(0x54000, 0x600);
-#endif
- dwc_ddrphy_apb_wr(0x54001, 0x0);
- dwc_ddrphy_apb_wr(0x54002, 0x0);
- dwc_ddrphy_apb_wr(0x54003, 0x960);
- dwc_ddrphy_apb_wr(0x54004, 0x2);
- dwc_ddrphy_apb_wr(0x54005, 0x0);
- dwc_ddrphy_apb_wr(0x54006, 0x25e);
- dwc_ddrphy_apb_wr(0x54007, 0x2000);
-#ifdef DDR_ONE_RANK
- dwc_ddrphy_apb_wr(0x54008, 0x101);
- dwc_ddrphy_apb_wr(0x54009, 0x0);
-#else
- dwc_ddrphy_apb_wr(0x54008, 0x303);
- dwc_ddrphy_apb_wr(0x54009, 0x200);
-#endif
- dwc_ddrphy_apb_wr(0x5400a, 0x0);
-#ifdef RUN_ON_SILICON
- dwc_ddrphy_apb_wr(0x5400b, 0x61);
-#else
- dwc_ddrphy_apb_wr(0x5400b, 0x1);
-#endif
- dwc_ddrphy_apb_wr(0x5400c, 0xc8);
- dwc_ddrphy_apb_wr(0x5400d, 0x100);
- dwc_ddrphy_apb_wr(0x5400e, 0x1f7f);
- dwc_ddrphy_apb_wr(0x5400f, 0x0);
- dwc_ddrphy_apb_wr(0x54010, 0x0);
- dwc_ddrphy_apb_wr(0x54011, 0x0);
- dwc_ddrphy_apb_wr(0x54012, 0x1);
- dwc_ddrphy_apb_wr(0x5402f, mr_value[0][0]);
- dwc_ddrphy_apb_wr(0x54030, mr_value[0][1]);
- dwc_ddrphy_apb_wr(0x54031, mr_value[0][2]);
- dwc_ddrphy_apb_wr(0x54032, mr_value[0][3]);
- dwc_ddrphy_apb_wr(0x54033, mr_value[0][4]);
- dwc_ddrphy_apb_wr(0x54034, mr_value[0][5]);
- dwc_ddrphy_apb_wr(0x54035, mr_value[0][6]);
-#ifdef DDR_ONE_RANK
- dwc_ddrphy_apb_wr(0x54036, 0x101);
-#else
- dwc_ddrphy_apb_wr(0x54036, 0x103);
-#endif
- dwc_ddrphy_apb_wr(0x54037, 0x0);
- dwc_ddrphy_apb_wr(0x54038, 0x0);
- dwc_ddrphy_apb_wr(0x54039, 0x0);
- dwc_ddrphy_apb_wr(0x5403a, 0x0);
- dwc_ddrphy_apb_wr(0x5403b, 0x0);
- dwc_ddrphy_apb_wr(0x5403c, 0x0);
- dwc_ddrphy_apb_wr(0x5403d, 0x0);
- dwc_ddrphy_apb_wr(0x5403e, 0x0);
- dwc_ddrphy_apb_wr(0x5403f, 0x1221);
- dwc_ddrphy_apb_wr(0x541fc, 0x100);
- /* [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x2d6 */
- /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
- /* This allows the firmware unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [phyinit_F_loadDMEM, 2D] End of dwc_ddrphy_phyinit_F_loadDMEM() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (G) Execute the Training Firmware */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- /* */
- /* 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and */
- /* ResetToMicro fields to 1 (all other fields should be zero). */
- /* Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- dwc_ddrphy_apb_wr(0xd0099, 0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- /* */
- /* 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. */
- dwc_ddrphy_apb_wr(0xd0099, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- /* */
- /* 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" */
- /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] Wait for the training firmware to complete. Implement timeout fucntion or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. */
- dwc_ddrphy_phyinit_userCustom_G_waitFwDone ();
-
- /* [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() */
- /* 4. Halt the microcontroller." */
- dwc_ddrphy_apb_wr(0xd0099, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
- /* [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW () */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (H) Read the Message Block results */
- /* */
- /* The procedure is as follows: */
- /* */
- /* ############################################################## */
- /* */
- /* */
- /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* */
- /* 2. Read the Firmware Message Block to obtain the results from the training. */
- /* This can be accomplished by issuing APB read commands to the DMEM addresses. */
- /* Example: */
- /* if (Train2D) */
- /* { */
- /* _read_2d_message_block_outputs_ */
- /* } */
- /* else */
- /* { */
- /* _read_1d_message_block_outputs_ */
- /* } */
- dwc_ddrphy_phyinit_userCustom_H_readMsgBlock (1);
-
- /* [dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock () */
- /* 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* 4. If training is required at another frequency, repeat the operations starting at step (E). */
- /* [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() */
- /* [phyinit_I_loadPIEImage] Start of dwc_ddrphy_phyinit_I_loadPIEImage() */
- ddr_dbg("2D training done!!!!\n");
-
- } /* Train2D */
- } /* !after_retention */
-#ifdef ENABLE_RETENTION
- else { /* after_retention */
- restore_1d2d_trained_csr_ddr4_p012(SAVE_DDRPHY_TRAIN_ADDR);
- } /* after_retention */
-#endif
-
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (I) Load PHY Init Engine Image */
- /* */
- /* Load the PHY Initialization Engine memory with the provided initialization sequence. */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* */
- /* Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
- /* This allows the memory controller unrestricted access to the configuration CSRs. */
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [phyinit_I_loadPIEImage] Programming PIE Production Code */
- dwc_ddrphy_apb_wr(0x90000, 0x10); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */
- dwc_ddrphy_apb_wr(0x90001, 0x400); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */
- dwc_ddrphy_apb_wr(0x90002, 0x10e); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */
- dwc_ddrphy_apb_wr(0x90003, 0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */
- dwc_ddrphy_apb_wr(0x90004, 0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */
- dwc_ddrphy_apb_wr(0x90005, 0x8); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */
- dwc_ddrphy_apb_wr(0x90029, 0xb); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */
- dwc_ddrphy_apb_wr(0x9002a, 0x480); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */
- dwc_ddrphy_apb_wr(0x9002b, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */
- dwc_ddrphy_apb_wr(0x9002c, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */
- dwc_ddrphy_apb_wr(0x9002d, 0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */
- dwc_ddrphy_apb_wr(0x9002e, 0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */
- dwc_ddrphy_apb_wr(0x9002f, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */
- dwc_ddrphy_apb_wr(0x90030, 0x478); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */
- dwc_ddrphy_apb_wr(0x90031, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */
- dwc_ddrphy_apb_wr(0x90032, 0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */
- dwc_ddrphy_apb_wr(0x90033, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */
- dwc_ddrphy_apb_wr(0x90034, 0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */
- dwc_ddrphy_apb_wr(0x90035, 0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */
- dwc_ddrphy_apb_wr(0x90036, 0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */
- dwc_ddrphy_apb_wr(0x90037, 0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */
- dwc_ddrphy_apb_wr(0x90038, 0x44); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */
- dwc_ddrphy_apb_wr(0x90039, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */
- dwc_ddrphy_apb_wr(0x9003a, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */
- dwc_ddrphy_apb_wr(0x9003b, 0x14f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */
- dwc_ddrphy_apb_wr(0x9003c, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */
- dwc_ddrphy_apb_wr(0x9003d, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */
- dwc_ddrphy_apb_wr(0x9003e, 0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */
- dwc_ddrphy_apb_wr(0x9003f, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */
- dwc_ddrphy_apb_wr(0x90040, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */
- dwc_ddrphy_apb_wr(0x90041, 0x4f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */
- dwc_ddrphy_apb_wr(0x90042, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */
- dwc_ddrphy_apb_wr(0x90043, 0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */
- dwc_ddrphy_apb_wr(0x90044, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */
- dwc_ddrphy_apb_wr(0x90045, 0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */
- dwc_ddrphy_apb_wr(0x90046, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */
- dwc_ddrphy_apb_wr(0x90047, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */
- dwc_ddrphy_apb_wr(0x90048, 0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */
- dwc_ddrphy_apb_wr(0x90049, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */
- dwc_ddrphy_apb_wr(0x9004a, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */
- dwc_ddrphy_apb_wr(0x9004b, 0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */
- dwc_ddrphy_apb_wr(0x9004c, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */
- dwc_ddrphy_apb_wr(0x9004d, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */
- dwc_ddrphy_apb_wr(0x9004e, 0x45a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */
- dwc_ddrphy_apb_wr(0x9004f, 0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */
- dwc_ddrphy_apb_wr(0x90050, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */
- dwc_ddrphy_apb_wr(0x90051, 0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */
- dwc_ddrphy_apb_wr(0x90052, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */
- dwc_ddrphy_apb_wr(0x90053, 0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */
- dwc_ddrphy_apb_wr(0x90054, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */
- dwc_ddrphy_apb_wr(0x90055, 0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */
- dwc_ddrphy_apb_wr(0x90056, 0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */
- dwc_ddrphy_apb_wr(0x90057, 0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */
- dwc_ddrphy_apb_wr(0x90058, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */
- dwc_ddrphy_apb_wr(0x90059, 0x40c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */
- dwc_ddrphy_apb_wr(0x9005a, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */
- dwc_ddrphy_apb_wr(0x9005b, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */
- dwc_ddrphy_apb_wr(0x9005c, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */
- dwc_ddrphy_apb_wr(0x9005d, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */
- dwc_ddrphy_apb_wr(0x9005e, 0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */
- dwc_ddrphy_apb_wr(0x9005f, 0x4040); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */
- dwc_ddrphy_apb_wr(0x90060, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */
- dwc_ddrphy_apb_wr(0x90061, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */
- dwc_ddrphy_apb_wr(0x90062, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */
- dwc_ddrphy_apb_wr(0x90063, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */
- dwc_ddrphy_apb_wr(0x90064, 0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */
- dwc_ddrphy_apb_wr(0x90065, 0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */
- dwc_ddrphy_apb_wr(0x90066, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */
- dwc_ddrphy_apb_wr(0x90067, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */
- dwc_ddrphy_apb_wr(0x90068, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */
- dwc_ddrphy_apb_wr(0x90069, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */
- dwc_ddrphy_apb_wr(0x9006a, 0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */
- dwc_ddrphy_apb_wr(0x9006b, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */
- dwc_ddrphy_apb_wr(0x9006c, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */
- dwc_ddrphy_apb_wr(0x9006d, 0x78); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */
- dwc_ddrphy_apb_wr(0x9006e, 0x549); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */
- dwc_ddrphy_apb_wr(0x9006f, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */
- dwc_ddrphy_apb_wr(0x90070, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */
- dwc_ddrphy_apb_wr(0x90071, 0xd49); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */
- dwc_ddrphy_apb_wr(0x90072, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */
- dwc_ddrphy_apb_wr(0x90073, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */
- dwc_ddrphy_apb_wr(0x90074, 0x94a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */
- dwc_ddrphy_apb_wr(0x90075, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */
- dwc_ddrphy_apb_wr(0x90076, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */
- dwc_ddrphy_apb_wr(0x90077, 0x441); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */
- dwc_ddrphy_apb_wr(0x90078, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */
- dwc_ddrphy_apb_wr(0x90079, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */
- dwc_ddrphy_apb_wr(0x9007a, 0x42); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */
- dwc_ddrphy_apb_wr(0x9007b, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */
- dwc_ddrphy_apb_wr(0x9007c, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */
- dwc_ddrphy_apb_wr(0x9007d, 0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */
- dwc_ddrphy_apb_wr(0x9007e, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */
- dwc_ddrphy_apb_wr(0x9007f, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */
- dwc_ddrphy_apb_wr(0x90080, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */
- dwc_ddrphy_apb_wr(0x90081, 0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */
- dwc_ddrphy_apb_wr(0x90082, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */
- dwc_ddrphy_apb_wr(0x90083, 0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */
- dwc_ddrphy_apb_wr(0x90084, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */
- dwc_ddrphy_apb_wr(0x90085, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */
- dwc_ddrphy_apb_wr(0x90086, 0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */
- dwc_ddrphy_apb_wr(0x90087, 0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */
- dwc_ddrphy_apb_wr(0x90088, 0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */
- dwc_ddrphy_apb_wr(0x90089, 0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */
- dwc_ddrphy_apb_wr(0x9008a, 0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */
- dwc_ddrphy_apb_wr(0x9008b, 0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */
- dwc_ddrphy_apb_wr(0x9008c, 0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */
- dwc_ddrphy_apb_wr(0x9008d, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */
- dwc_ddrphy_apb_wr(0x9008e, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */
- dwc_ddrphy_apb_wr(0x9008f, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */
- dwc_ddrphy_apb_wr(0x90090, 0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */
- dwc_ddrphy_apb_wr(0x90091, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */
- dwc_ddrphy_apb_wr(0x90092, 0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */
- dwc_ddrphy_apb_wr(0x90093, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */
- dwc_ddrphy_apb_wr(0x90094, 0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */
- dwc_ddrphy_apb_wr(0x90095, 0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */
- dwc_ddrphy_apb_wr(0x90096, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */
- dwc_ddrphy_apb_wr(0x90097, 0x58); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */
- dwc_ddrphy_apb_wr(0x90098, 0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */
- dwc_ddrphy_apb_wr(0x90099, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */
- dwc_ddrphy_apb_wr(0x9009a, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */
- dwc_ddrphy_apb_wr(0x9009b, 0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */
- dwc_ddrphy_apb_wr(0x9009c, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */
- dwc_ddrphy_apb_wr(0x9009d, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */
- dwc_ddrphy_apb_wr(0x9009e, 0x7); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */
- dwc_ddrphy_apb_wr(0x9009f, 0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */
- dwc_ddrphy_apb_wr(0x900a0, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */
- dwc_ddrphy_apb_wr(0x900a1, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */
- dwc_ddrphy_apb_wr(0x900a2, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */
- dwc_ddrphy_apb_wr(0x900a3, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */
- dwc_ddrphy_apb_wr(0x900a4, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */
- dwc_ddrphy_apb_wr(0x900a5, 0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */
- dwc_ddrphy_apb_wr(0x900a6, 0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */
- dwc_ddrphy_apb_wr(0x900a7, 0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */
- dwc_ddrphy_apb_wr(0x900a8, 0x8138); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */
- dwc_ddrphy_apb_wr(0x900a9, 0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */
- dwc_ddrphy_apb_wr(0x900aa, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */
- dwc_ddrphy_apb_wr(0x900ab, 0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */
- dwc_ddrphy_apb_wr(0x900ac, 0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */
- dwc_ddrphy_apb_wr(0x900ad, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */
- dwc_ddrphy_apb_wr(0x900ae, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */
- dwc_ddrphy_apb_wr(0x900af, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */
- dwc_ddrphy_apb_wr(0x900b0, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */
- dwc_ddrphy_apb_wr(0x900b1, 0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */
- dwc_ddrphy_apb_wr(0x900b2, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */
- dwc_ddrphy_apb_wr(0x900b3, 0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */
- dwc_ddrphy_apb_wr(0x900b4, 0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */
- dwc_ddrphy_apb_wr(0x900b5, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */
- dwc_ddrphy_apb_wr(0x900b6, 0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */
- dwc_ddrphy_apb_wr(0x900b7, 0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */
- dwc_ddrphy_apb_wr(0x900b8, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */
- dwc_ddrphy_apb_wr(0x900b9, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */
- dwc_ddrphy_apb_wr(0x900ba, 0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */
- dwc_ddrphy_apb_wr(0x900bb, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */
- dwc_ddrphy_apb_wr(0x900bc, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */
- dwc_ddrphy_apb_wr(0x900bd, 0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */
- dwc_ddrphy_apb_wr(0x900be, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */
- dwc_ddrphy_apb_wr(0x900bf, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */
- dwc_ddrphy_apb_wr(0x900c0, 0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */
- dwc_ddrphy_apb_wr(0x900c1, 0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */
- dwc_ddrphy_apb_wr(0x900c2, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */
- dwc_ddrphy_apb_wr(0x900c3, 0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */
- dwc_ddrphy_apb_wr(0x900c4, 0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */
- dwc_ddrphy_apb_wr(0x900c5, 0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */
- dwc_ddrphy_apb_wr(0x900c6, 0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */
- dwc_ddrphy_apb_wr(0x900c7, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */
- dwc_ddrphy_apb_wr(0x900c8, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */
- dwc_ddrphy_apb_wr(0x900c9, 0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */
- dwc_ddrphy_apb_wr(0x900ca, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */
- dwc_ddrphy_apb_wr(0x900cb, 0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */
- dwc_ddrphy_apb_wr(0x900cc, 0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */
- dwc_ddrphy_apb_wr(0x900cd, 0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */
- dwc_ddrphy_apb_wr(0x90006, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */
- dwc_ddrphy_apb_wr(0x90007, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */
- dwc_ddrphy_apb_wr(0x90008, 0x8); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */
- dwc_ddrphy_apb_wr(0x90009, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */
- dwc_ddrphy_apb_wr(0x9000a, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */
- dwc_ddrphy_apb_wr(0x9000b, 0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */
- dwc_ddrphy_apb_wr(0xd00e7, 0x400); /* DWC_DDRPHYA_APBONLY0_SequencerOverride */
- dwc_ddrphy_apb_wr(0x90017, 0x0); /* DWC_DDRPHYA_INITENG0_StartVector0b0 */
- dwc_ddrphy_apb_wr(0x90026, 0x2c); /* DWC_DDRPHYA_INITENG0_StartVector0b15 */
- /* [phyinit_I_loadPIEImage] Pstate=0, Memclk=1200MHz, Programming Seq0BDLY0 to 0x4b */
- dwc_ddrphy_apb_wr(0x2000b, 0x4b); /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */
- /* [phyinit_I_loadPIEImage] Pstate=0, Memclk=1200MHz, Programming Seq0BDLY1 to 0x96 */
- dwc_ddrphy_apb_wr(0x2000c, 0x96); /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */
- /* [phyinit_I_loadPIEImage] Pstate=0, Memclk=1200MHz, Programming Seq0BDLY2 to 0x5dc */
- dwc_ddrphy_apb_wr(0x2000d, 0x5dc); /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */
- /* [phyinit_I_loadPIEImage] Pstate=0, Memclk=1200MHz, Programming Seq0BDLY3 to 0x2c */
- dwc_ddrphy_apb_wr(0x2000e, 0x2c); /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */
- /* [phyinit_I_loadPIEImage] Pstate=1, Memclk=200MHz, Programming Seq0BDLY0 to 0xc */
- dwc_ddrphy_apb_wr(0x12000b, 0xc); /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p1 */
- /* [phyinit_I_loadPIEImage] Pstate=1, Memclk=200MHz, Programming Seq0BDLY1 to 0x19 */
- dwc_ddrphy_apb_wr(0x12000c, 0x19); /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p1 */
- /* [phyinit_I_loadPIEImage] Pstate=1, Memclk=200MHz, Programming Seq0BDLY2 to 0xfa */
- dwc_ddrphy_apb_wr(0x12000d, 0xfa); /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p1 */
- /* [phyinit_I_loadPIEImage] Pstate=1, Memclk=200MHz, Programming Seq0BDLY3 to 0x10 */
- dwc_ddrphy_apb_wr(0x12000e, 0x10); /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p1 */
- /* [phyinit_I_loadPIEImage] Pstate=2, Memclk=50MHz, Programming Seq0BDLY0 to 0x3 */
- dwc_ddrphy_apb_wr(0x22000b, 0x3); /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p2 */
- /* [phyinit_I_loadPIEImage] Pstate=2, Memclk=50MHz, Programming Seq0BDLY1 to 0x6 */
- dwc_ddrphy_apb_wr(0x22000c, 0x6); /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p2 */
- /* [phyinit_I_loadPIEImage] Pstate=2, Memclk=50MHz, Programming Seq0BDLY2 to 0x3e */
- dwc_ddrphy_apb_wr(0x22000d, 0x3e); /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p2 */
- /* [phyinit_I_loadPIEImage] Pstate=2, Memclk=50MHz, Programming Seq0BDLY3 to 0x10 */
- dwc_ddrphy_apb_wr(0x22000e, 0x10); /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p2 */
- dwc_ddrphy_apb_wr(0x9000c, 0x0); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */
- dwc_ddrphy_apb_wr(0x9000d, 0x173); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */
- dwc_ddrphy_apb_wr(0x9000e, 0x60); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */
- dwc_ddrphy_apb_wr(0x9000f, 0x6110); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */
- dwc_ddrphy_apb_wr(0x90010, 0x2152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */
- dwc_ddrphy_apb_wr(0x90011, 0xdfbd); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */
- dwc_ddrphy_apb_wr(0x90012, 0xffff); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */
- dwc_ddrphy_apb_wr(0x90013, 0x6152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */
- /* Disabling Ucclk (PMU) and Hclk (training hardware) */
- dwc_ddrphy_apb_wr(0xc0080, 0x0); /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */
- /* Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- /* [phyinit_I_loadPIEImage] End of dwc_ddrphy_phyinit_I_loadPIEImage() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* dwc_ddrphy_phyinit_userCustom_customPostTrain is a user-editable function. */
- /* */
- /* See PhyInit App Note for detailed description and function usage */
- /* */
- /* ############################################################## */
- /* */
- dwc_ddrphy_phyinit_userCustom_customPostTrain ();
-
- /* [dwc_ddrphy_phyinit_userCustom_customPostTrain] End of dwc_ddrphy_phyinit_userCustom_customPostTrain() */
- /* [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] Start of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode() */
- /* */
- /* */
- /* ############################################################## */
- /* */
- /* (J) Initialize the PHY to Mission Mode through DFI Initialization */
- /* */
- /* Initialize the PHY to mission mode as follows: */
- /* */
- /* 1. Set the PHY input clocks to the desired frequency. */
- /* 2. Initialize the PHY to mission mode by performing DFI Initialization. */
- /* Please see the DFI specification for more information. See the DFI frequency bus encoding in section <XXX>. */
- /* Note: The PHY training firmware initializes the DRAM state. if skip */
- /* training is used, the DRAM state is not initialized. */
- /* */
- /* ############################################################## */
- /* */
- dwc_ddrphy_phyinit_userCustom_J_enterMissionMode ();
-
- /* */
- /* [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] End of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode() */
- /* [dwc_ddrphy_phyinit_sequence] End of dwc_ddrphy_phyinit_sequence() */
- /* [dwc_ddrphy_phyinit_main] End of dwc_ddrphy_phyinit_main() */
-
- /* ---------------------------------------------------------------------- */
- /* save 1d2d training CSR */
- /* ---------------------------------------------------------------------- */
-#ifdef ENABLE_RETENTION
- if (!after_retention) {
- save_1d2d_trained_csr_ddr4_p012(SAVE_DDRPHY_TRAIN_ADDR);
- }
-#endif
-}
diff --git a/board/freescale/imx8mm_val/ddr/ddr4/ddr4_phyinit_task.c b/board/freescale/imx8mm_val/ddr/ddr4/ddr4_phyinit_task.c
deleted file mode 100644
index 49a540a..0000000
--- a/board/freescale/imx8mm_val/ddr/ddr4/ddr4_phyinit_task.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright 2018 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/ddr.h>
-#include <asm/arch/clock.h>
-#include "ddr4_define.h"
-
-extern unsigned int mr_value[3][7];
-void dwc_ddrphy_phyinit_userCustom_E_setDfiClk (unsigned int pstate) {
- if (pstate == 1) {
- ddr_dbg("C: pstate1 ...\n");
-#ifdef PLLBYPASS_250MBPS
- dram_enable_bypass(MHZ(250));
-#endif
-#ifdef PLLBYPASS_400MBPS
- dram_enable_bypass(MHZ(400));
-#endif
- } else if (pstate == 2) {
- ddr_dbg("C: pstate2 ...\n");
- dram_enable_bypass(MHZ(100));
- } else {
- ddr_dbg("C: pstate0 ...\n");
- dram_pll_init(MHZ(600));
- dram_disable_bypass();
- }
-}
-
-void dwc_ddrphy_phyinit_userCustom_G_waitFwDone(void)
-{
- wait_ddrphy_training_complete();
-}
-void dwc_ddrphy_phyinit_userCustom_overrideUserInput (void) {}
-void dwc_ddrphy_phyinit_userCustom_A_bringupPower (void) {}
-void dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy (void) {}
-void dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(unsigned int Train2D) {}
-void dwc_ddrphy_phyinit_userCustom_customPostTrain(void) {}
-void dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(void) {}
-
-void ddr4_mr_write(unsigned int mr, unsigned int data, unsigned int read, unsigned int rank)
-{
- unsigned int tmp, mr_mirror, data_mirror;
-
- /* 1. Poll MRSTAT.mr_wr_busy until it is 0. This checks that there is no outstanding MR transaction. No */
- /* writes should be performed to MRCTRL0 and MRCTRL1 if MRSTAT.mr_wr_busy = 1. */
- do {
- tmp = reg32_read(DDRC_MRSTAT(0));
- } while (tmp & 0x1);
-
- /* 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and (for MRWs) */
- /* MRCTRL1.mr_data to define the MR transaction. */
- /* (A3, A4), (A5, A6), (A7, A8), (BA0, BA1), (A11, A13), */
- tmp = reg32_read(DDRC_DIMMCTL(0));
- if ((tmp & 0x2) && (rank == 0x2)) {
- mr_mirror = (mr & 0x4) | ((mr & 0x1) << 1) | ((mr & 0x2) >> 1);/* BA0, BA1 swap */
- data_mirror = (data & 0x1607) | ((data & 0x8) << 1) | ((data & 0x10) >> 1) | ((data & 0x20) << 1) |
- ((data & 0x40) >> 1) | ((data & 0x80) << 1) | ((data & 0x100) >> 1) | ((data & 0x800) << 2) | ((data & 0x2000) >> 2) ;
- } else {
- mr_mirror = mr;
- data_mirror = data;
- }
-
- reg32_write(DDRC_MRCTRL0(0), read | (mr_mirror << 12) | (rank << 4));
- reg32_write(DDRC_MRCTRL1(0), data_mirror);
-
- /* 3. In a separate APB transaction, write the MRCTRL0.mr_wr to 1. This bit is self-clearing, and triggers */
- /* the MR transaction. The uMCTL2 then asserts the MRSTAT.mr_wr_busy while it performs the MR */
- /* transaction to SDRAM, and no further accesses can be initiated until it is deasserted. */
- reg32setbit(DDRC_MRCTRL0(0), 31);
- do {
- tmp = reg32_read(DDRC_MRSTAT(0));
- } while (tmp);
-
-}
diff --git a/board/freescale/imx8mm_val/ddr/ddr4/ddr4_swffc_fw09.c b/board/freescale/imx8mm_val/ddr/ddr4/ddr4_swffc_fw09.c
deleted file mode 100644
index a460e43..0000000
--- a/board/freescale/imx8mm_val/ddr/ddr4/ddr4_swffc_fw09.c
+++ /dev/null
@@ -1,599 +0,0 @@
-/*
- * Copyright 2018 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/ddr.h>
-#include <asm/arch/clock.h>
-#include "anamix_common.h"
-#include "ddr4_define.h"
-
-unsigned int mr_value[3][7] = {
- {0xa34, 0x105, 0x1028, 0x240, 0x200, 0x200, 0x814}, /* pstate0 MR */
- {0x204, 0x104, 0x1000, 0x040, 0x200, 0x200, 0x014}, /* pstate1 MR */
- {0x204, 0x104, 0x1000, 0x040, 0x200, 0x200, 0x014} }; /* pstate2 MR */
-
-static unsigned int cur_pstate;
-unsigned int after_retention = 0;
-
-void ddr4_dll_change(unsigned int pstate);
-void ddr4_dll_no_change(unsigned int pstate);
-
-void umctl2_cfg(void)
-{
-#ifdef DDR_ONE_RANK
- reg32_write(DDRC_MSTR(0), 0x81040010);
-#else
- reg32_write(DDRC_MSTR(0), 0x83040010);
-#endif
-
- reg32_write(DDRC_PWRCTL(0), 0x000000aa);
- reg32_write(DDRC_PWRTMG(0), 0x00221306);
-
- reg32_write(DDRC_RFSHCTL0(0), 0x00c0a070);
- reg32_write(DDRC_RFSHCTL1(0), 0x00010008);
- reg32_write(DDRC_RFSHCTL3(0), 0x00000010);
- reg32_write(DDRC_RFSHTMG(0), 0x004980f4);
- reg32_write(DDRC_CRCPARCTL0(0), 0x00000000);
- reg32_write(DDRC_CRCPARCTL1(0), 0x00001010);
- reg32_write(DDRC_INIT0(0), 0xc0030002);
- reg32_write(DDRC_INIT1(0), 0x00020009);
- reg32_write(DDRC_INIT2(0), 0x0000350f);
- reg32_write(DDRC_INIT3(0), (mr_value[0][0]<<16) | (mr_value[0][1]));
- reg32_write(DDRC_INIT4(0), (mr_value[0][2]<<16) | (mr_value[0][3]));
- reg32_write(DDRC_INIT5(0), 0x001103cb);
- reg32_write(DDRC_INIT6(0), (mr_value[0][4]<<16) | (mr_value[0][5]));
- reg32_write(DDRC_INIT7(0), mr_value[0][6]);
- reg32_write(DDRC_DIMMCTL(0), 0x00000032);
- reg32_write(DDRC_RANKCTL(0), 0x00000fc7);
- reg32_write(DDRC_DRAMTMG0(0), 0x14132813);
- reg32_write(DDRC_DRAMTMG1(0), 0x0004051b);
- reg32_write(DDRC_DRAMTMG2(0), 0x0808030f);
- reg32_write(DDRC_DRAMTMG3(0), 0x0000400c);
- reg32_write(DDRC_DRAMTMG4(0), 0x08030409);
- reg32_write(DDRC_DRAMTMG5(0), 0x0e090504);
- reg32_write(DDRC_DRAMTMG6(0), 0x05030000);
- reg32_write(DDRC_DRAMTMG7(0), 0x0000090e);
- reg32_write(DDRC_DRAMTMG8(0), 0x0606700c);
- reg32_write(DDRC_DRAMTMG9(0), 0x0002040c);
- reg32_write(DDRC_DRAMTMG10(0), 0x000f0c07);
- reg32_write(DDRC_DRAMTMG11(0), 0x1809011d);
- reg32_write(DDRC_DRAMTMG12(0), 0x0000000d);
- reg32_write(DDRC_DRAMTMG13(0), 0x2b000000);
- reg32_write(DDRC_DRAMTMG14(0), 0x000000a4);
- reg32_write(DDRC_DRAMTMG15(0), 0x00000000);
- reg32_write(DDRC_DRAMTMG17(0), 0x00250078);
- reg32_write(DDRC_ZQCTL0(0), 0x51000040);
- reg32_write(DDRC_ZQCTL1(0), 0x00000070);
- reg32_write(DDRC_ZQCTL2(0), 0x00000000);
- reg32_write(DDRC_DFITMG0(0), 0x038b820b);
- reg32_write(DDRC_DFITMG1(0), 0x02020103);
- reg32_write(DDRC_DFILPCFG0(0), 0x07f04011); /* [8]dfi_lp_en_sr = 0 */
- reg32_write(DDRC_DFILPCFG1(0), 0x000000b0);
- reg32_write(DDRC_DFIUPD0(0), 0xe0400018);
- reg32_write(DDRC_DFIUPD1(0), 0x0048005a);
- reg32_write(DDRC_DFIUPD2(0), 0x80000000);
- reg32_write(DDRC_DFIMISC(0), 0x00000001);
- reg32_write(DDRC_DFITMG2(0), 0x00000b0b);
- reg32_write(DDRC_DFITMG3(0), 0x00000001);
- reg32_write(DDRC_DBICTL(0), 0x00000000);
- reg32_write(DDRC_DFIPHYMSTR(0), 0x00000000);
-
-#ifdef DDR_ONE_RANK
- reg32_write(DDRC_ADDRMAP0(0), 0x0000001F);
-#else
- reg32_write(DDRC_ADDRMAP0(0), 0x00000017); /* [4:0]cs0: 6+23 */
-#endif
- reg32_write(DDRC_ADDRMAP1(0), 0x003F0909); /* [5:0] bank b0: 2+9; [13:8] b1: P3+9 ; [21:16] b2: 4+, unused */
- reg32_write(DDRC_ADDRMAP2(0), 0x01010100); /* [3:0] col-b2: 2; [11:8] col-b3: 3+1; [19:16] col-b4: 4+1 ; [27:24] col-b5: 5+1 */
- reg32_write(DDRC_ADDRMAP3(0), 0x01010101); /* [3:0] col-b6: 6+1; [11:8] col-b7: 7+1; [19:16] col-b8: 8+1 ; [27:24] col-b9: 9+1 */
- reg32_write(DDRC_ADDRMAP4(0), 0x00001f1f); /* col-b10, col-b11 not used */
- reg32_write(DDRC_ADDRMAP5(0), 0x07070707); /* [3:0] row-b0: 6+7; [11:8] row-b1: 7+7; [19:16] row-b2_b10: 8~16+7; [27:24] row-b11: 17+7 */
- reg32_write(DDRC_ADDRMAP6(0), 0x07070707); /* [3:0] row-b12:18+7; [11:8] row-b13: 19+7; [19:16] row-b14:20+7; [27:24] row-b15: 21+7 */
- reg32_write(DDRC_ADDRMAP7(0), 0x00000f0f); /* col-b10, col-b11 not used */
- reg32_write(DDRC_ADDRMAP8(0), 0x00003F01); /* [5:0] bg-b0: 2+1; [13:8]bg-b1:3+, unused */
- reg32_write(DDRC_ADDRMAP9(0), 0x0a020b06); /* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
- reg32_write(DDRC_ADDRMAP10(0), 0x0a0a0a0a);/* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
- reg32_write(DDRC_ADDRMAP11(0), 0x00000000);
-
- /* FREQ0: BL8, CL=16, CWL=16, WR_PREAMBLE = 1,RD_PREAMBLE = 1, CRC_MODE = 1, so wr_odt_hold=5+1+1=7 */
- /* wr_odt_delay=DFITMG1.dfi_t_cmd_lat=0 */
- reg32_write(DDRC_ODTCFG(0), 0x07000600);
-#ifdef DDR_ONE_RANK
- reg32_write(DDRC_ODTMAP(0), 0x0001);
-#else
- reg32_write(DDRC_ODTMAP(0), 0x0201);/* disable ODT0x00001120); */
-#endif
- reg32_write(DDRC_SCHED(0), 0x317d1a07);
- reg32_write(DDRC_SCHED1(0), 0x0000000f);
- reg32_write(DDRC_PERFHPR1(0), 0x2a001b76);
- reg32_write(DDRC_PERFLPR1(0), 0x7300b473);
- reg32_write(DDRC_PERFWR1(0), 0x30000e06);
- reg32_write(DDRC_DBG0(0), 0x00000014);
- reg32_write(DDRC_DBG1(0), 0x00000000);
- reg32_write(DDRC_DBGCMD(0), 0x00000000);
- reg32_write(DDRC_SWCTL(0), 0x00000001);
- reg32_write(DDRC_POISONCFG(0), 0x00000010);
- reg32_write(DDRC_PCCFG(0), 0x00000100);/* bl_exp_mode=1 */
- reg32_write(DDRC_PCFGR_0(0), 0x00013193);
- reg32_write(DDRC_PCFGW_0(0), 0x00006096);
- reg32_write(DDRC_PCTRL_0(0), 0x00000001);
- reg32_write(DDRC_PCFGQOS0_0(0), 0x02000c00);
- reg32_write(DDRC_PCFGQOS1_0(0), 0x003c00db);
- reg32_write(DDRC_PCFGWQOS0_0(0), 0x00100009);
- reg32_write(DDRC_PCFGWQOS1_0(0), 0x00000002);
-
-}
-
-void umctl2_freq1_cfg(void)
-{
- reg32_write(DDRC_FREQ1_RFSHCTL0(0), 0x0021a0c0);
-#ifdef PLLBYPASS_250MBPS
- reg32_write(DDRC_FREQ1_RFSHTMG(0), 0x000f0011);/* tREFI=7.8us */
-#endif
-#ifdef PLLBYPASS_400MBPS
- reg32_write(DDRC_FREQ1_RFSHTMG(0), 0x0018001a);/* tREFI=7.8us */
-#endif
-
- reg32_write(DDRC_FREQ1_INIT3(0), (mr_value[1][0]<<16) | (mr_value[1][1]));
- reg32_write(DDRC_FREQ1_INIT4(0), (mr_value[1][2]<<16) | (mr_value[1][3]));
- reg32_write(DDRC_FREQ1_INIT6(0), (mr_value[1][4]<<16) | (mr_value[1][5]));
- reg32_write(DDRC_FREQ1_INIT7(0), mr_value[1][6]);
-#ifdef PLLBYPASS_250MBPS
- reg32_write(DDRC_FREQ1_DRAMTMG0(0), 0x0c0e0403);/* t_ras_max=9*7.8us, t_ras_min=35ns */
-#endif
-#ifdef PLLBYPASS_400MBPS
- reg32_write(DDRC_FREQ1_DRAMTMG0(0), 0x0c0e0604);/* t_ras_max=9*7.8us, t_ras_min=35ns */
-#endif
- reg32_write(DDRC_FREQ1_DRAMTMG1(0), 0x00030314);
- reg32_write(DDRC_FREQ1_DRAMTMG2(0), 0x0505040a);
- reg32_write(DDRC_FREQ1_DRAMTMG3(0), 0x0000400c);
- reg32_write(DDRC_FREQ1_DRAMTMG4(0), 0x06040307); /* tRP=6 --> 7 */
- reg32_write(DDRC_FREQ1_DRAMTMG5(0), 0x090d0202);
- reg32_write(DDRC_FREQ1_DRAMTMG6(0), 0x0a070008);
- reg32_write(DDRC_FREQ1_DRAMTMG7(0), 0x00000d09);
- reg32_write(DDRC_FREQ1_DRAMTMG8(0), 0x08084b09);
- reg32_write(DDRC_FREQ1_DRAMTMG9(0), 0x00020308);
- reg32_write(DDRC_FREQ1_DRAMTMG10(0), 0x000f0d06);
- reg32_write(DDRC_FREQ1_DRAMTMG11(0), 0x12060111);
- reg32_write(DDRC_FREQ1_DRAMTMG12(0), 0x00000008);
- reg32_write(DDRC_FREQ1_DRAMTMG13(0), 0x21000000);
- reg32_write(DDRC_FREQ1_DRAMTMG14(0), 0x00000000);
- reg32_write(DDRC_FREQ1_DRAMTMG15(0), 0x00000000);
- reg32_write(DDRC_FREQ1_DRAMTMG17(0), 0x00c6007d);
- reg32_write(DDRC_FREQ1_ZQCTL0(0), 0x51000040);
- reg32_write(DDRC_FREQ1_DFITMG0(0), 0x03858204);
- reg32_write(DDRC_FREQ1_DFITMG1(0), 0x00020103);
- reg32_write(DDRC_FREQ1_DFITMG2(0), 0x00000504);
- reg32_write(DDRC_FREQ1_DFITMG3(0), 0x00000001);
- /* FREQ1: BL8, CL=10, CWL=9, WR_PREAMBLE = 1,RD_PREAMBLE = 1, CRC_MODE = 1 */
- /* wr_odt_delay=DFITMG1.dfi_t_cmd_lat=0 */
- reg32_write(DDRC_FREQ1_ODTCFG(0), 0x07000601);
-}
-
-void umctl2_freq2_cfg(void)
-{
- reg32_write(DDRC_FREQ2_RFSHCTL0(0), 0x0021a0c0);
- reg32_write(DDRC_FREQ2_RFSHTMG(0), 0x0006000e);/* tREFI=7.8us */
- reg32_write(DDRC_FREQ2_INIT3(0), (mr_value[2][0]<<16) | (mr_value[2][1]));
- reg32_write(DDRC_FREQ2_INIT4(0), (mr_value[2][2]<<16) | (mr_value[2][3]));
- reg32_write(DDRC_FREQ2_INIT6(0), (mr_value[2][4]<<16) | (mr_value[2][5]));
- reg32_write(DDRC_FREQ2_INIT7(0), mr_value[2][6]);
- reg32_write(DDRC_FREQ2_DRAMTMG0(0), 0x0c0e0101);/* t_ras_max=9*7.8us, t_ras_min=35ns */
- reg32_write(DDRC_FREQ2_DRAMTMG1(0), 0x00030314);
- reg32_write(DDRC_FREQ2_DRAMTMG2(0), 0x0505040a);
- reg32_write(DDRC_FREQ2_DRAMTMG3(0), 0x0000400c);
- reg32_write(DDRC_FREQ2_DRAMTMG4(0), 0x06040307); /* tRP=6 --> 7 */
- reg32_write(DDRC_FREQ2_DRAMTMG5(0), 0x090d0202);
- reg32_write(DDRC_FREQ2_DRAMTMG6(0), 0x0a070008);
- reg32_write(DDRC_FREQ2_DRAMTMG7(0), 0x00000d09);
- reg32_write(DDRC_FREQ2_DRAMTMG8(0), 0x08084b09);
- reg32_write(DDRC_FREQ2_DRAMTMG9(0), 0x00020308);
- reg32_write(DDRC_FREQ2_DRAMTMG10(0), 0x000f0d06);
- reg32_write(DDRC_FREQ2_DRAMTMG11(0), 0x12060111);
- reg32_write(DDRC_FREQ2_DRAMTMG12(0), 0x00000008);
- reg32_write(DDRC_FREQ2_DRAMTMG13(0), 0x21000000);
- reg32_write(DDRC_FREQ2_DRAMTMG14(0), 0x00000000);
- reg32_write(DDRC_FREQ2_DRAMTMG15(0), 0x00000000);
- reg32_write(DDRC_FREQ2_DRAMTMG17(0), 0x00c6007d);
- reg32_write(DDRC_FREQ2_ZQCTL0(0), 0x51000040);
- reg32_write(DDRC_FREQ2_DFITMG0(0), 0x03858204);
- reg32_write(DDRC_FREQ2_DFITMG1(0), 0x00020103);
- reg32_write(DDRC_FREQ2_DFITMG2(0), 0x00000504);
- reg32_write(DDRC_FREQ2_DFITMG3(0), 0x00000001);
- /* FREQ1: BL8, CL=10, CWL=9, WR_PREAMBLE = 1,RD_PREAMBLE = 1, CRC_MODE = 1 */
- /* wr_odt_delay=DFITMG1.dfi_t_cmd_lat=0 */
- reg32_write(DDRC_FREQ2_ODTCFG(0), 0x07000601);
-}
-
-
-void ddr4_pub_train(void)
-{
- volatile unsigned int tmp_t;
- after_retention = 0;
-
- reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00003F); /* assert [0]ddr1_preset_n, [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n, [4]src_system_rst_b! */
- reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); /* deassert [4]src_system_rst_b! */
-
- /* change the clock source of dram_apb_clk_root */
- clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); /* to source 4 --800MHz/4 */
-
- /* DDR_PLL_CONFIG_600MHz(); */
- dram_pll_init(MHZ(600));
- ddr_dbg("C: dram pll init finished\n");
-
- reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
- reg32setbit(0x303A00F8, 5);/* PU_PGC_SW_PUP_REQ */
-
- reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); /* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */
-
- reg32_write(DDRC_DBG1(0), 0x00000001);
- reg32_write(DDRC_PWRCTL(0), 0x00000001);
-
- while (0 != (0x7 & reg32_read(DDRC_STAT(0))))
- ;
-
- ddr_dbg("C: cfg umctl2 regs ...\n");
- umctl2_cfg();
-#ifdef DDR4_SW_FFC
- umctl2_freq1_cfg();
- umctl2_freq2_cfg();
-#endif
-
- reg32_write(DDRC_RFSHCTL3(0), 0x00000011);
- /* RESET: <ctn> DEASSERTED */
- /* RESET: <a Port 0 DEASSERTED(0) */
- reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
- reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
-
- reg32_write(DDRC_DBG1(0), 0x00000000);
- reg32_write(DDRC_PWRCTL(0), 0x00000aa);
- reg32_write(DDRC_SWCTL(0), 0x00000000);
-
- reg32_write(DDRC_DFIMISC(0), 0x00000000);
-
- ddr_dbg("C: phy training ...\n");
- ddr4_phyinit_train_sw_ffc(1);/* for dvfs flow, 2D training is a must item */
-
- do {
- tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0x00020097);
- ddr_dbg("C: Waiting CalBusy value = 0\n");
- } while (tmp_t != 0);
-
- reg32_write(DDRC_DFIMISC(0), 0x00000020);
-
- /* wait DFISTAT.dfi_init_complete to 1 */
- while (0 == (0x1 & reg32_read(DDRC_DFISTAT(0))))
- ;
-
- /* clear DFIMISC.dfi_init_complete_en */
- reg32_write(DDRC_DFIMISC(0), 0x00000000);
- /* set DFIMISC.dfi_init_complete_en again */
- reg32_write(DDRC_DFIMISC(0), 0x00000001);
- reg32_write(DDRC_PWRCTL(0), 0x0000088);
-
- /* set SWCTL.sw_done to enable quasi-dynamic register programming outside reset. */
- reg32_write(DDRC_SWCTL(0), 0x00000001);
- /* wait SWSTAT.sw_done_ack to 1 */
- while (0 == (0x1 & reg32_read(DDRC_SWSTAT(0))))
- ;
-
- /* wait STAT to normal state */
- while (0x1 != (0x7 & reg32_read(DDRC_STAT(0))))
- ;
-
- reg32_write(DDRC_PWRCTL(0), 0x0000088);
- reg32_write(DDRC_PCTRL_0(0), 0x00000001);
- reg32_write(DDRC_RFSHCTL3(0), 0x00000010); /* dis_auto-refresh is set to 0 */
-}
-
-void ddr4_switch_freq(unsigned int pstate)
-{
- if ((pstate != 0 && cur_pstate == 0) || (pstate == 0 && cur_pstate != 0)) {
- ddr4_dll_change(pstate);
- } else {
- ddr4_dll_no_change(pstate);
- ddr_dbg("dll no change\n");
- }
- cur_pstate = pstate;
-}
-
-void dram_all_mr_cfg(unsigned int pstate)
-{
- unsigned int i;
- /* 15. Perform MRS commands as required to re-program timing registers in the SDRAM for the new */
- /* frequency (in particular, CL, CWL and WR may need to be changed). */
- for (i = 0; i < 7; i++)
- ddr4_mr_write(i, mr_value[pstate][i], 0, 0x1);
-
-#ifndef DDR_ONE_RANK
- for (i = 0; i < 7; i++)
- ddr4_mr_write(i, mr_value[pstate][i], 0, 0x2);
-#endif
-}
-
-void sw_pstate(unsigned int pstate)
-{
- volatile unsigned int tmp;
- unsigned int i;
- /* the the following software programming sequence to switch from DLL-on to DLL-off, or reverse: */
- reg32_write(DDRC_SWCTL(0), 0x0000);
- /* 12. Change the clock frequency to the desired value. */
- /* 13. Update any registers which may be required to change for the new frequency. This includes quasidynamic and dynamic registers. This includes both uMCTL2 registers and PHY registers. */
- reg32_write(DDRC_DFIMISC(0), 0x00000000);
- reg32_write(DDRC_MSTR2(0), pstate);/* UMCTL2_REGS_FREQ1 */
- reg32setbit(DDRC_MSTR(0), 29);
-
- /* dvfs.18. Toggle RFSHCTL3.refresh_update_level to allow the new refresh-related register values to */
- /* propagate to the refresh logic. */
- tmp = reg32_read(DDRC_RFSHCTL3(0));
- if ((tmp & 0x2) == 0x2)
- reg32_write(DDRC_RFSHCTL3(0), tmp & 0xFFFFFFFD);
- else
- reg32_write(DDRC_RFSHCTL3(0), tmp | 0x2);
-
- /* dvfs.19. If required, trigger the initialization in the PHY. If using the gen2 multiPHY, PLL initialization */
- /* should be triggered at this point. See the PHY databook for details about the frequency change */
- /* procedure. */
- reg32_write(DDRC_DFIMISC(0), 0x00000000 | (pstate<<8));/* pstate1 */
- reg32_write(DDRC_DFIMISC(0), 0x00000020 | (pstate<<8));
-
- /* wait DFISTAT.dfi_init_complete to 0 */
- do {
- tmp = 0x1 & reg32_read(DDRC_DFISTAT(0));
- } while (tmp);
-
- dwc_ddrphy_phyinit_userCustom_E_setDfiClk(pstate);
-
- reg32_write(DDRC_DFIMISC(0), 0x00000000 | (pstate<<8));
- /* wait DFISTAT.dfi_init_complete to 1 */
- do {
- tmp = 0x1 & reg32_read(DDRC_DFISTAT(0));
- } while (!tmp);
-
- /* When changing frequencies the controller may violate the JEDEC requirement that no */
- /* more than 16 refreshes should be issued within 2*tREFI. These extra refreshes are not */
- /* expected to cause a problem in the SDRAM. This issue can be avoided by waiting for at */
- /* least 2*tREFI before exiting self-refresh in step 19. */
- for (i = 20; i > 0; i--)
- ;
- ddr_dbg("C: waiting for 2*tREFI (2*7.8us)\n");
-
- /* 14. Exit the self-refresh state by setting PWRCTL.selfref_sw = 0. */
- reg32clrbit(DDRC_PWRCTL(0), 5);
- do {
- tmp = 0x3f & (reg32_read((DDRC_STAT(0))));
- ddr_dbg("C: waiting for exit Self Refresh\n");
- } while (tmp == 0x23);
-}
-
-void ddr4_dll_change(unsigned int pstate)
-{
- volatile unsigned int tmp;
- enum DLL_STATE { NO_CHANGE = 0, ON2OFF = 1, OFF2ON = 2} dll_sw; /* 0-no change, 1-on2off, 2-off2on.; */
-
- if (pstate != 0 && cur_pstate == 0) {
- dll_sw = ON2OFF;
- ddr_dbg("dll ON2OFF\n");
- } else if (pstate == 0 && cur_pstate != 0) {
- dll_sw = OFF2ON;
- ddr_dbg("dll OFF2ON\n");
- } else {
- dll_sw = NO_CHANGE;
- }
-
- /* the the following software programming sequence to switch from DLL-on to DLL-off, or reverse: */
- reg32_write(DDRC_SWCTL(0), 0x0000);
-
- /* 1. Set the DBG1.dis_hif = 1. This prevents further reads/writes being received on the HIF. */
- reg32setbit(DDRC_DBG1(0), 1);
- /* 2. Set ZQCTL0.dis_auto_zq=1, to disable automatic generation of ZQCS/MPC(ZQ calibration) */
- /* commands */
- if (pstate == 1)
- reg32setbit(DDRC_FREQ1_ZQCTL0(0), 31);
- else if (pstate == 2)
- reg32setbit(DDRC_FREQ2_ZQCTL0(0), 31);
- else
- reg32setbit(DDRC_ZQCTL0(0), 31);
-
- /* 3. Set RFSHCTL3.dis_auto_refresh=1, to disable automatic refreshes */
- reg32setbit(DDRC_RFSHCTL3(0), 0);
- /* 4. Ensure all commands have been flushed from the uMCTL2 by polling */
- /* DBGCAM.wr_data_pipeline_empty, DBGCAM.rd_data_pipeline_empty1, */
- /* DBGCAM.dbg_wr_q_depth, DBGCAM.dbg_lpr_q_depth, DBGCAM.dbg_rd_q_empty, */
- /* DBGCAM.dbg_wr_q_empty. */
- do {
- tmp = 0x06000000 & reg32_read(DDRC_DBGCAM(0));
- } while (tmp != 0x06000000);
- reg32_write(DDRC_PCTRL_0(0), 0x00000000);
- /* 5. Perform an MRS command (using MRCTRL0 and MRCTRL1 registers) to disable RTT_NOM: */
- /* a. DDR3: Write 0 to MR1[9], MR1[6] and MR1[2] */
- /* b. DDR4: Write 0 to MR1[10:8] */
- if (mr_value[pstate][1] & 0x700) {
- ddr4_mr_write(1, mr_value[pstate][1] & 0xF8FF, 0, 0x1);
-#ifndef DDR_ONE_RANK
- ddr4_mr_write(1, mr_value[pstate][1] & 0xF8FF, 0, 0x2);
-#endif
- }
- /* 6. For DDR4 only: Perform an MRS command (using MRCTRL0 and MRCTRL1 registers) to write 0 to */
- /* MR5[8:6] to disable RTT_PARK */
- if (mr_value[pstate][5] & 0x1C0) {
- ddr4_mr_write(5, mr_value[pstate][5] & 0xFE3F, 0, 0x1);
-#ifndef DDR_ONE_RANK
- ddr4_mr_write(5, mr_value[pstate][5] & 0xFE3F, 0, 0x2);
-#endif
- }
-
- if (dll_sw == ON2OFF) {
- /* 7. Perform an MRS command (using MRCTRL0 and MRCTRL1 registers) to write 0 to MR2[11:9], to */
- /* disable RTT_WR (and therefore disable dynamic ODT). This applies for both DDR3 and DDR4. */
- if (mr_value[pstate][2] & 0xE00) {
- ddr4_mr_write(2, mr_value[pstate][2] & 0xF1FF, 0, 0x1);
-#ifndef DDR_ONE_RANK
- ddr4_mr_write(2, mr_value[pstate][2] & 0xF1FF, 0, 0x2);
-#endif
- }
- /* 8. Perform an MRS command (using MRCTRL0 and MRCTRL1 registers) to disable the DLL. The */
- /* timing of this MRS is automatically handled by the uMCTL2. */
- /* a. DDR3: Write 1 to MR1[0] */
- /* b. DDR4: Write 0 to MR1[0] */
- ddr4_mr_write(1, mr_value[pstate][1] & 0xFFFE, 0, 0x1);
-#ifndef DDR_ONE_RANK
- ddr4_mr_write(1, mr_value[pstate][1] & 0xFFFE, 0, 0x2);
-#endif
- }
-
- /* 9. Put the SDRAM into self-refresh mode by setting PWRCTL.selfref_sw = 1, and polling */
- /* STAT.operating_mode to ensure the DDRC has entered self-refresh. */
- reg32setbit(DDRC_PWRCTL(0), 5);
- /* 10. Wait until STAT.operating_mode[1:0]==11 indicating that the DWC_ddr_umctl2 core is in selfrefresh mode. Ensure transition to self-refresh was due to software by checking that */
- /* STAT.selfref_type[1:0]=2`b10. */
- do {
- tmp = 0x3f & (reg32_read((DDRC_STAT(0))));
- ddr_dbg("C: wait DRAM in Self Refresh\n");
- } while (tmp != 0x23);
-
- /* 11. Set the MSTR.dll_off_mode = 1 or 0. */
- if (dll_sw == ON2OFF)
- reg32setbit(DDRC_MSTR(0), 15);
-
- if (dll_sw == OFF2ON)
- reg32clrbit(DDRC_MSTR(0), 15);
-
- sw_pstate(pstate);
-
- /* DRAM dll enable */
- if (dll_sw == OFF2ON) {
- ddr4_mr_write(1, mr_value[pstate][1] | 0x1, 0, 0x1);
-#ifndef DDR_ONE_RANK
- ddr4_mr_write(1, mr_value[pstate][1] | 0x1, 0, 0x2);
-#endif
- /* DRAM dll reset, self-clear */
- ddr4_mr_write(0, mr_value[pstate][0] | 0x100, 0, 0x1);
-#ifndef DDR_ONE_RANK
- ddr4_mr_write(0, mr_value[pstate][0] | 0x100, 0, 0x2);
-#endif
- }
-
- dram_all_mr_cfg(pstate);
-
- /* 16. Re-enable automatic generation of ZQCS/MPC(ZQ calibration) commands, by setting */
- /* ZQCTL0.dis_auto_zq=0 if they were previously disabled */
- if (pstate == 1)
- reg32clrbit(DDRC_FREQ1_ZQCTL0(0), 31);
- else if (pstate == 2)
- reg32clrbit(DDRC_FREQ2_ZQCTL0(0), 31);
- else
- reg32clrbit(DDRC_ZQCTL0(0), 31);
-
- /* 17. Re-enable automatic refreshes (RFSHCTL3.dis_auto_refresh = 0) if they have been previously */
- /* disabled. */
- reg32clrbit(DDRC_RFSHCTL3(0), 0);
- /* 18. Restore ZQCTL0.dis_srx_zqcl */
- /* 19. Write DBG1.dis_hif = 0 to re-enable reads and writes. */
- reg32clrbit(DDRC_DBG1(0), 1);
-
- reg32_write(DDRC_PCTRL_0(0), 0x00000001);
- /* 27. Write 1 to SBRCTL.scrub_en. Enable SBR if desired, only required if SBR instantiated. */
-
- /* set SWCTL.sw_done to enable quasi-dynamic register programming outside reset. */
- reg32_write(DDRC_SWCTL(0), 0x0001);
-
- /* wait SWSTAT.sw_done_ack to 1 */
- do {
- tmp = 0x1 & reg32_read(DDRC_SWSTAT(0));
- } while (!tmp);
-}
-
-void ddr4_dll_no_change(unsigned int pstate)
-{
- volatile unsigned int tmp;
- /* ------------------------------------------------------------------------------------- */
- /* change to pstate1 */
- /* ------------------------------------------------------------------------------------- */
- /* 1. Program one of UMCTL2_REGS_FREQ1/2/3, whichever you prefer, timing register-set with the */
- /* timing settings required for the alternative clock frequency. */
- /* set SWCTL.sw_done to disable quasi-dynamic register programming outside reset. */
- reg32_write(DDRC_SWCTL(0), 0x0000);
-
- /* set SWCTL.sw_done to enable quasi-dynamic register programming outside reset. */
- /* wait SWSTAT.sw_done_ack to 1 */
-
- /* 2. Write 0 to PCTRL_n.port_en. This blocks AXI port(s) from taking any transaction (blocks traffic on */
- /* AXI ports). */
- reg32_write(DDRC_PCTRL_0(0), 0x00000000);
- /* 3. Poll PSTAT.rd_port_busy_n=0 and PSTAT.wr_port_busy_n=0. Wait until all AXI ports are idle (the */
- /* uMCTL2 core has to be idle). */
- do {
- tmp = reg32_read(DDRC_PSTAT(0));
- } while (tmp & 0x10001);
-
- /* 4. Write 0 to SBRCTL.scrub_en. Disable SBR, required only if SBR instantiated. */
- /* 5. Poll SBRSTAT.scrub_busy=0. Indicates that there are no outstanding SBR read commands (required */
- /* only if SBR instantiated). */
- /* 6. Set DERATEEN.derate_enable = 0, if DERATEEN.derate_eanble = 1 and the read latency (RL) value */
- /* needs to change after the frequency change (LPDDR2/3/4 only). */
- /* 7. Set DBG1.dis_hif=1 so that no new commands will be accepted by the uMCTL2. */
- reg32setbit(DDRC_DBG1(0), 1);
- /* 8. Poll DBGCAM.dbg_wr_q_empty and DBGCAM.dbg_rd_q_empty to ensure that write and read data */
- /* buffers are empty. */
- do {
- tmp = 0x06000000 & reg32_read(DDRC_DBGCAM(0));
- } while (tmp != 0x06000000);
- /* 9. For DDR4, update MR6 with the new tDLLK value via the Mode Register Write signals */
- /* (MRCTRL0.mr_x/MRCTRL1.mr_x). */
- /* 10. Set DFILPCFG0.dfi_lp_en_sr = 0, if DFILPCFG0.dfi_lp_en_sr = 1, and wait until DFISTAT.dfi_lp_ack */
- /* = 0. */
- /* 11. If DFI PHY Master interface is active in uMCTL2 (DFIPHYMSTR.phymstr_en == 1'b1) then disable it */
- /* by programming DFIPHYMSTR.phymstr_en = 1'b0. */
- /* 12. Wait until STAT.operating_mode[1:0]!=11 indicating that the DWC_ddr_umctl2 controller is not in */
- /* self-refresh mode. */
- tmp = 0x3 & (reg32_read((DDRC_STAT(0))));
- if (tmp == 0x3) {
- ddr_dbg("C: Error DRAM should not in Self Refresh\n");
- ddr_dbg("vt_error\n");
- }
- /* 13. Assert PWRCTL.selfref_sw for the DWC_ddr_umctl2 core to enter the self-refresh mode. */
- reg32setbit(DDRC_PWRCTL(0), 5);
- /* 14. Wait until STAT.operating_mode[1:0]==11 indicating that the DWC_ddr_umctl2 core is in selfrefresh mode. Ensure transition to self-refresh was due to software by checking that STAT.selfref_type[1:0]=2'b10. */
- do {
- tmp = 0x3f & (reg32_read((DDRC_STAT(0))));
- ddr_dbg("C: DRAM in Self Refresh\n");
- } while (tmp != 0x23);
-
- sw_pstate(pstate);
- dram_all_mr_cfg(pstate);
-
-
- /* 23. Enable HIF commands by setting DBG1.dis_hif=0. */
- reg32clrbit(DDRC_DBG1(0), 1);
- /* 24. Reset DERATEEN.derate_enable = 1 if DERATEEN.derate_enable has been set to 0 in step 6. */
- /* 25. If DFI PHY Master interface was active in uMCTL2 (DFIPHYMSTR.phymstr_en == 1'b1) before the */
- /* step 11 then enable it back by programming DFIPHYMSTR.phymstr_en = 1'b1. */
- /* 26. Write 1 to PCTRL_n.port_en. AXI port(s) are no longer blocked from taking transactions (Re-enable */
- /* traffic on AXI ports). */
- reg32_write(DDRC_PCTRL_0(0), 0x00000001);
- /* 27. Write 1 to SBRCTL.scrub_en. Enable SBR if desired, only required if SBR instantiated. */
-
-
-
- /* set SWCTL.sw_done to enable quasi-dynamic register programming outside reset. */
- reg32_write(DDRC_SWCTL(0), 0x0001);
-
- /* wait SWSTAT.sw_done_ack to 1 */
- do {
- tmp = 0x1 & reg32_read(DDRC_SWSTAT(0));
- } while (!tmp);
-
-
-}
-
-void ddr_init(struct dram_timing_info *timing_info)
-{
- /* initialize DDR4-2400 (umctl2@800MHz) */
- ddr4_pub_train();
-}
diff --git a/board/freescale/imx8mm_val/ddr/ddr4/restore_1d2d_trained_csr_ddr4_p012.c b/board/freescale/imx8mm_val/ddr/ddr4/restore_1d2d_trained_csr_ddr4_p012.c
deleted file mode 100644
index c060c44..0000000
--- a/board/freescale/imx8mm_val/ddr/ddr4/restore_1d2d_trained_csr_ddr4_p012.c
+++ /dev/null
@@ -1,1042 +0,0 @@
-/*
- * Copyright 2018 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/ddr.h>
-#include <asm/arch/clock.h>
-#include "ddr4_define.h"
-
-#ifdef ENABLE_RETENTION
-static const unsigned int restore_csr[] = {
- 0x200b2,
- 0x1200b2,
- 0x2200b2,
- 0x200cb,
-#ifdef RUN_ON_SILICON
- 0x10043,
- 0x110043,
- 0x210043,
- 0x10143,
- 0x110143,
- 0x210143,
- 0x11043,
- 0x111043,
- 0x211043,
- 0x11143,
- 0x111143,
- 0x211143,
- 0x12043,
- 0x112043,
- 0x212043,
- 0x12143,
- 0x112143,
- 0x212143,
- 0x13043,
- 0x113043,
- 0x213043,
- 0x13143,
- 0x113143,
- 0x213143,
- 0x80,
- 0x100080,
- 0x200080,
- 0x1080,
- 0x101080,
- 0x201080,
- 0x2080,
- 0x102080,
- 0x202080,
- 0x3080,
- 0x103080,
- 0x203080,
- 0x4080,
- 0x104080,
- 0x204080,
- 0x5080,
- 0x105080,
- 0x205080,
- 0x6080,
- 0x106080,
- 0x206080,
- 0x7080,
- 0x107080,
- 0x207080,
- 0x8080,
- 0x108080,
- 0x208080,
- 0x9080,
- 0x109080,
- 0x209080,
- 0x10080,
- 0x110080,
- 0x210080,
- 0x10180,
- 0x110180,
- 0x210180,
- 0x10081,
- 0x110081,
- 0x210081,
- 0x10181,
- 0x110181,
- 0x210181,
- 0x10082,
- 0x110082,
- 0x210082,
- 0x10182,
- 0x110182,
- 0x210182,
- 0x10083,
- 0x110083,
- 0x210083,
- 0x10183,
- 0x110183,
- 0x210183,
- 0x11080,
- 0x111080,
- 0x211080,
- 0x11180,
- 0x111180,
- 0x211180,
- 0x11081,
- 0x111081,
- 0x211081,
- 0x11181,
- 0x111181,
- 0x211181,
- 0x11082,
- 0x111082,
- 0x211082,
- 0x11182,
- 0x111182,
- 0x211182,
- 0x11083,
- 0x111083,
- 0x211083,
- 0x11183,
- 0x111183,
- 0x211183,
- 0x12080,
- 0x112080,
- 0x212080,
- 0x12180,
- 0x112180,
- 0x212180,
- 0x12081,
- 0x112081,
- 0x212081,
- 0x12181,
- 0x112181,
- 0x212181,
- 0x12082,
- 0x112082,
- 0x212082,
- 0x12182,
- 0x112182,
- 0x212182,
- 0x12083,
- 0x112083,
- 0x212083,
- 0x12183,
- 0x112183,
- 0x212183,
- 0x13080,
- 0x113080,
- 0x213080,
- 0x13180,
- 0x113180,
- 0x213180,
- 0x13081,
- 0x113081,
- 0x213081,
- 0x13181,
- 0x113181,
- 0x213181,
- 0x13082,
- 0x113082,
- 0x213082,
- 0x13182,
- 0x113182,
- 0x213182,
- 0x13083,
- 0x113083,
- 0x213083,
- 0x13183,
- 0x113183,
- 0x213183,
- 0x100d0,
- 0x1100d0,
- 0x2100d0,
- 0x101d0,
- 0x1101d0,
- 0x2101d0,
- 0x100d1,
- 0x1100d1,
- 0x2100d1,
- 0x101d1,
- 0x1101d1,
- 0x2101d1,
- 0x100d2,
- 0x1100d2,
- 0x2100d2,
- 0x101d2,
- 0x1101d2,
- 0x2101d2,
- 0x100d3,
- 0x1100d3,
- 0x2100d3,
- 0x101d3,
- 0x1101d3,
- 0x2101d3,
- 0x110d0,
- 0x1110d0,
- 0x2110d0,
- 0x111d0,
- 0x1111d0,
- 0x2111d0,
- 0x110d1,
- 0x1110d1,
- 0x2110d1,
- 0x111d1,
- 0x1111d1,
- 0x2111d1,
- 0x110d2,
- 0x1110d2,
- 0x2110d2,
- 0x111d2,
- 0x1111d2,
- 0x2111d2,
- 0x110d3,
- 0x1110d3,
- 0x2110d3,
- 0x111d3,
- 0x1111d3,
- 0x2111d3,
- 0x120d0,
- 0x1120d0,
- 0x2120d0,
- 0x121d0,
- 0x1121d0,
- 0x2121d0,
- 0x120d1,
- 0x1120d1,
- 0x2120d1,
- 0x121d1,
- 0x1121d1,
- 0x2121d1,
- 0x120d2,
- 0x1120d2,
- 0x2120d2,
- 0x121d2,
- 0x1121d2,
- 0x2121d2,
- 0x120d3,
- 0x1120d3,
- 0x2120d3,
- 0x121d3,
- 0x1121d3,
- 0x2121d3,
- 0x130d0,
- 0x1130d0,
- 0x2130d0,
- 0x131d0,
- 0x1131d0,
- 0x2131d0,
- 0x130d1,
- 0x1130d1,
- 0x2130d1,
- 0x131d1,
- 0x1131d1,
- 0x2131d1,
- 0x130d2,
- 0x1130d2,
- 0x2130d2,
- 0x131d2,
- 0x1131d2,
- 0x2131d2,
- 0x130d3,
- 0x1130d3,
- 0x2130d3,
- 0x131d3,
- 0x1131d3,
- 0x2131d3,
- 0x10068,
- 0x10168,
- 0x10268,
- 0x10368,
- 0x10468,
- 0x10568,
- 0x10668,
- 0x10768,
- 0x10868,
- 0x10069,
- 0x10169,
- 0x10269,
- 0x10369,
- 0x10469,
- 0x10569,
- 0x10669,
- 0x10769,
- 0x10869,
- 0x1006a,
- 0x1016a,
- 0x1026a,
- 0x1036a,
- 0x1046a,
- 0x1056a,
- 0x1066a,
- 0x1076a,
- 0x1086a,
- 0x1006b,
- 0x1016b,
- 0x1026b,
- 0x1036b,
- 0x1046b,
- 0x1056b,
- 0x1066b,
- 0x1076b,
- 0x1086b,
- 0x11068,
- 0x11168,
- 0x11268,
- 0x11368,
- 0x11468,
- 0x11568,
- 0x11668,
- 0x11768,
- 0x11868,
- 0x11069,
- 0x11169,
- 0x11269,
- 0x11369,
- 0x11469,
- 0x11569,
- 0x11669,
- 0x11769,
- 0x11869,
- 0x1106a,
- 0x1116a,
- 0x1126a,
- 0x1136a,
- 0x1146a,
- 0x1156a,
- 0x1166a,
- 0x1176a,
- 0x1186a,
- 0x1106b,
- 0x1116b,
- 0x1126b,
- 0x1136b,
- 0x1146b,
- 0x1156b,
- 0x1166b,
- 0x1176b,
- 0x1186b,
- 0x12068,
- 0x12168,
- 0x12268,
- 0x12368,
- 0x12468,
- 0x12568,
- 0x12668,
- 0x12768,
- 0x12868,
- 0x12069,
- 0x12169,
- 0x12269,
- 0x12369,
- 0x12469,
- 0x12569,
- 0x12669,
- 0x12769,
- 0x12869,
- 0x1206a,
- 0x1216a,
- 0x1226a,
- 0x1236a,
- 0x1246a,
- 0x1256a,
- 0x1266a,
- 0x1276a,
- 0x1286a,
- 0x1206b,
- 0x1216b,
- 0x1226b,
- 0x1236b,
- 0x1246b,
- 0x1256b,
- 0x1266b,
- 0x1276b,
- 0x1286b,
- 0x13068,
- 0x13168,
- 0x13268,
- 0x13368,
- 0x13468,
- 0x13568,
- 0x13668,
- 0x13768,
- 0x13868,
- 0x13069,
- 0x13169,
- 0x13269,
- 0x13369,
- 0x13469,
- 0x13569,
- 0x13669,
- 0x13769,
- 0x13869,
- 0x1306a,
- 0x1316a,
- 0x1326a,
- 0x1336a,
- 0x1346a,
- 0x1356a,
- 0x1366a,
- 0x1376a,
- 0x1386a,
- 0x1306b,
- 0x1316b,
- 0x1326b,
- 0x1336b,
- 0x1346b,
- 0x1356b,
- 0x1366b,
- 0x1376b,
- 0x1386b,
- 0x1008c,
- 0x11008c,
- 0x21008c,
- 0x1018c,
- 0x11018c,
- 0x21018c,
- 0x1008d,
- 0x11008d,
- 0x21008d,
- 0x1018d,
- 0x11018d,
- 0x21018d,
- 0x1008e,
- 0x11008e,
- 0x21008e,
- 0x1018e,
- 0x11018e,
- 0x21018e,
- 0x1008f,
- 0x11008f,
- 0x21008f,
- 0x1018f,
- 0x11018f,
- 0x21018f,
- 0x1108c,
- 0x11108c,
- 0x21108c,
- 0x1118c,
- 0x11118c,
- 0x21118c,
- 0x1108d,
- 0x11108d,
- 0x21108d,
- 0x1118d,
- 0x11118d,
- 0x21118d,
- 0x1108e,
- 0x11108e,
- 0x21108e,
- 0x1118e,
- 0x11118e,
- 0x21118e,
- 0x1108f,
- 0x11108f,
- 0x21108f,
- 0x1118f,
- 0x11118f,
- 0x21118f,
- 0x1208c,
- 0x11208c,
- 0x21208c,
- 0x1218c,
- 0x11218c,
- 0x21218c,
- 0x1208d,
- 0x11208d,
- 0x21208d,
- 0x1218d,
- 0x11218d,
- 0x21218d,
- 0x1208e,
- 0x11208e,
- 0x21208e,
- 0x1218e,
- 0x11218e,
- 0x21218e,
- 0x1208f,
- 0x11208f,
- 0x21208f,
- 0x1218f,
- 0x11218f,
- 0x21218f,
- 0x1308c,
- 0x11308c,
- 0x21308c,
- 0x1318c,
- 0x11318c,
- 0x21318c,
- 0x1308d,
- 0x11308d,
- 0x21308d,
- 0x1318d,
- 0x11318d,
- 0x21318d,
- 0x1308e,
- 0x11308e,
- 0x21308e,
- 0x1318e,
- 0x11318e,
- 0x21318e,
- 0x1308f,
- 0x11308f,
- 0x21308f,
- 0x1318f,
- 0x11318f,
- 0x21318f,
- 0x100c0,
- 0x1100c0,
- 0x2100c0,
- 0x101c0,
- 0x1101c0,
- 0x2101c0,
- 0x102c0,
- 0x1102c0,
- 0x2102c0,
- 0x103c0,
- 0x1103c0,
- 0x2103c0,
- 0x104c0,
- 0x1104c0,
- 0x2104c0,
- 0x105c0,
- 0x1105c0,
- 0x2105c0,
- 0x106c0,
- 0x1106c0,
- 0x2106c0,
- 0x107c0,
- 0x1107c0,
- 0x2107c0,
- 0x108c0,
- 0x1108c0,
- 0x2108c0,
- 0x100c1,
- 0x1100c1,
- 0x2100c1,
- 0x101c1,
- 0x1101c1,
- 0x2101c1,
- 0x102c1,
- 0x1102c1,
- 0x2102c1,
- 0x103c1,
- 0x1103c1,
- 0x2103c1,
- 0x104c1,
- 0x1104c1,
- 0x2104c1,
- 0x105c1,
- 0x1105c1,
- 0x2105c1,
- 0x106c1,
- 0x1106c1,
- 0x2106c1,
- 0x107c1,
- 0x1107c1,
- 0x2107c1,
- 0x108c1,
- 0x1108c1,
- 0x2108c1,
- 0x100c2,
- 0x1100c2,
- 0x2100c2,
- 0x101c2,
- 0x1101c2,
- 0x2101c2,
- 0x102c2,
- 0x1102c2,
- 0x2102c2,
- 0x103c2,
- 0x1103c2,
- 0x2103c2,
- 0x104c2,
- 0x1104c2,
- 0x2104c2,
- 0x105c2,
- 0x1105c2,
- 0x2105c2,
- 0x106c2,
- 0x1106c2,
- 0x2106c2,
- 0x107c2,
- 0x1107c2,
- 0x2107c2,
- 0x108c2,
- 0x1108c2,
- 0x2108c2,
- 0x100c3,
- 0x1100c3,
- 0x2100c3,
- 0x101c3,
- 0x1101c3,
- 0x2101c3,
- 0x102c3,
- 0x1102c3,
- 0x2102c3,
- 0x103c3,
- 0x1103c3,
- 0x2103c3,
- 0x104c3,
- 0x1104c3,
- 0x2104c3,
- 0x105c3,
- 0x1105c3,
- 0x2105c3,
- 0x106c3,
- 0x1106c3,
- 0x2106c3,
- 0x107c3,
- 0x1107c3,
- 0x2107c3,
- 0x108c3,
- 0x1108c3,
- 0x2108c3,
- 0x110c0,
- 0x1110c0,
- 0x2110c0,
- 0x111c0,
- 0x1111c0,
- 0x2111c0,
- 0x112c0,
- 0x1112c0,
- 0x2112c0,
- 0x113c0,
- 0x1113c0,
- 0x2113c0,
- 0x114c0,
- 0x1114c0,
- 0x2114c0,
- 0x115c0,
- 0x1115c0,
- 0x2115c0,
- 0x116c0,
- 0x1116c0,
- 0x2116c0,
- 0x117c0,
- 0x1117c0,
- 0x2117c0,
- 0x118c0,
- 0x1118c0,
- 0x2118c0,
- 0x110c1,
- 0x1110c1,
- 0x2110c1,
- 0x111c1,
- 0x1111c1,
- 0x2111c1,
- 0x112c1,
- 0x1112c1,
- 0x2112c1,
- 0x113c1,
- 0x1113c1,
- 0x2113c1,
- 0x114c1,
- 0x1114c1,
- 0x2114c1,
- 0x115c1,
- 0x1115c1,
- 0x2115c1,
- 0x116c1,
- 0x1116c1,
- 0x2116c1,
- 0x117c1,
- 0x1117c1,
- 0x2117c1,
- 0x118c1,
- 0x1118c1,
- 0x2118c1,
- 0x110c2,
- 0x1110c2,
- 0x2110c2,
- 0x111c2,
- 0x1111c2,
- 0x2111c2,
- 0x112c2,
- 0x1112c2,
- 0x2112c2,
- 0x113c2,
- 0x1113c2,
- 0x2113c2,
- 0x114c2,
- 0x1114c2,
- 0x2114c2,
- 0x115c2,
- 0x1115c2,
- 0x2115c2,
- 0x116c2,
- 0x1116c2,
- 0x2116c2,
- 0x117c2,
- 0x1117c2,
- 0x2117c2,
- 0x118c2,
- 0x1118c2,
- 0x2118c2,
- 0x110c3,
- 0x1110c3,
- 0x2110c3,
- 0x111c3,
- 0x1111c3,
- 0x2111c3,
- 0x112c3,
- 0x1112c3,
- 0x2112c3,
- 0x113c3,
- 0x1113c3,
- 0x2113c3,
- 0x114c3,
- 0x1114c3,
- 0x2114c3,
- 0x115c3,
- 0x1115c3,
- 0x2115c3,
- 0x116c3,
- 0x1116c3,
- 0x2116c3,
- 0x117c3,
- 0x1117c3,
- 0x2117c3,
- 0x118c3,
- 0x1118c3,
- 0x2118c3,
- 0x120c0,
- 0x1120c0,
- 0x2120c0,
- 0x121c0,
- 0x1121c0,
- 0x2121c0,
- 0x122c0,
- 0x1122c0,
- 0x2122c0,
- 0x123c0,
- 0x1123c0,
- 0x2123c0,
- 0x124c0,
- 0x1124c0,
- 0x2124c0,
- 0x125c0,
- 0x1125c0,
- 0x2125c0,
- 0x126c0,
- 0x1126c0,
- 0x2126c0,
- 0x127c0,
- 0x1127c0,
- 0x2127c0,
- 0x128c0,
- 0x1128c0,
- 0x2128c0,
- 0x120c1,
- 0x1120c1,
- 0x2120c1,
- 0x121c1,
- 0x1121c1,
- 0x2121c1,
- 0x122c1,
- 0x1122c1,
- 0x2122c1,
- 0x123c1,
- 0x1123c1,
- 0x2123c1,
- 0x124c1,
- 0x1124c1,
- 0x2124c1,
- 0x125c1,
- 0x1125c1,
- 0x2125c1,
- 0x126c1,
- 0x1126c1,
- 0x2126c1,
- 0x127c1,
- 0x1127c1,
- 0x2127c1,
- 0x128c1,
- 0x1128c1,
- 0x2128c1,
- 0x120c2,
- 0x1120c2,
- 0x2120c2,
- 0x121c2,
- 0x1121c2,
- 0x2121c2,
- 0x122c2,
- 0x1122c2,
- 0x2122c2,
- 0x123c2,
- 0x1123c2,
- 0x2123c2,
- 0x124c2,
- 0x1124c2,
- 0x2124c2,
- 0x125c2,
- 0x1125c2,
- 0x2125c2,
- 0x126c2,
- 0x1126c2,
- 0x2126c2,
- 0x127c2,
- 0x1127c2,
- 0x2127c2,
- 0x128c2,
- 0x1128c2,
- 0x2128c2,
- 0x120c3,
- 0x1120c3,
- 0x2120c3,
- 0x121c3,
- 0x1121c3,
- 0x2121c3,
- 0x122c3,
- 0x1122c3,
- 0x2122c3,
- 0x123c3,
- 0x1123c3,
- 0x2123c3,
- 0x124c3,
- 0x1124c3,
- 0x2124c3,
- 0x125c3,
- 0x1125c3,
- 0x2125c3,
- 0x126c3,
- 0x1126c3,
- 0x2126c3,
- 0x127c3,
- 0x1127c3,
- 0x2127c3,
- 0x128c3,
- 0x1128c3,
- 0x2128c3,
- 0x130c0,
- 0x1130c0,
- 0x2130c0,
- 0x131c0,
- 0x1131c0,
- 0x2131c0,
- 0x132c0,
- 0x1132c0,
- 0x2132c0,
- 0x133c0,
- 0x1133c0,
- 0x2133c0,
- 0x134c0,
- 0x1134c0,
- 0x2134c0,
- 0x135c0,
- 0x1135c0,
- 0x2135c0,
- 0x136c0,
- 0x1136c0,
- 0x2136c0,
- 0x137c0,
- 0x1137c0,
- 0x2137c0,
- 0x138c0,
- 0x1138c0,
- 0x2138c0,
- 0x130c1,
- 0x1130c1,
- 0x2130c1,
- 0x131c1,
- 0x1131c1,
- 0x2131c1,
- 0x132c1,
- 0x1132c1,
- 0x2132c1,
- 0x133c1,
- 0x1133c1,
- 0x2133c1,
- 0x134c1,
- 0x1134c1,
- 0x2134c1,
- 0x135c1,
- 0x1135c1,
- 0x2135c1,
- 0x136c1,
- 0x1136c1,
- 0x2136c1,
- 0x137c1,
- 0x1137c1,
- 0x2137c1,
- 0x138c1,
- 0x1138c1,
- 0x2138c1,
- 0x130c2,
- 0x1130c2,
- 0x2130c2,
- 0x131c2,
- 0x1131c2,
- 0x2131c2,
- 0x132c2,
- 0x1132c2,
- 0x2132c2,
- 0x133c2,
- 0x1133c2,
- 0x2133c2,
- 0x134c2,
- 0x1134c2,
- 0x2134c2,
- 0x135c2,
- 0x1135c2,
- 0x2135c2,
- 0x136c2,
- 0x1136c2,
- 0x2136c2,
- 0x137c2,
- 0x1137c2,
- 0x2137c2,
- 0x138c2,
- 0x1138c2,
- 0x2138c2,
- 0x130c3,
- 0x1130c3,
- 0x2130c3,
- 0x131c3,
- 0x1131c3,
- 0x2131c3,
- 0x132c3,
- 0x1132c3,
- 0x2132c3,
- 0x133c3,
- 0x1133c3,
- 0x2133c3,
- 0x134c3,
- 0x1134c3,
- 0x2134c3,
- 0x135c3,
- 0x1135c3,
- 0x2135c3,
- 0x136c3,
- 0x1136c3,
- 0x2136c3,
- 0x137c3,
- 0x1137c3,
- 0x2137c3,
- 0x138c3,
- 0x1138c3,
- 0x2138c3,
- 0x10020,
- 0x110020,
- 0x210020,
- 0x11020,
- 0x111020,
- 0x211020,
- 0x12020,
- 0x112020,
- 0x212020,
- 0x13020,
- 0x113020,
- 0x213020,
- 0x2007d,
- 0x12007d,
- 0x22007d,
- 0x10040,
- 0x10140,
- 0x10240,
- 0x10340,
- 0x10440,
- 0x10540,
- 0x10640,
- 0x10740,
- 0x10840,
- 0x10030,
- 0x10130,
- 0x10230,
- 0x10330,
- 0x10430,
- 0x10530,
- 0x10630,
- 0x10730,
- 0x10830,
- 0x11040,
- 0x11140,
- 0x11240,
- 0x11340,
- 0x11440,
- 0x11540,
- 0x11640,
- 0x11740,
- 0x11840,
- 0x11030,
- 0x11130,
- 0x11230,
- 0x11330,
- 0x11430,
- 0x11530,
- 0x11630,
- 0x11730,
- 0x11830,
- 0x12040,
- 0x12140,
- 0x12240,
- 0x12340,
- 0x12440,
- 0x12540,
- 0x12640,
- 0x12740,
- 0x12840,
- 0x12030,
- 0x12130,
- 0x12230,
- 0x12330,
- 0x12430,
- 0x12530,
- 0x12630,
- 0x12730,
- 0x12830,
- 0x13040,
- 0x13140,
- 0x13240,
- 0x13340,
- 0x13440,
- 0x13540,
- 0x13640,
- 0x13740,
- 0x13840,
- 0x13030,
- 0x13130,
- 0x13230,
- 0x13330,
- 0x13430,
- 0x13530,
- 0x13630,
- 0x13730,
- 0x13830,
-#endif
- 0
-};
-
-void restore_1d2d_trained_csr_ddr4_p012(unsigned int addr)
-{
- unsigned int i;
-
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- for (i = 0; restore_csr[i] != 0; i++) {
- dwc_ddrphy_apb_wr(restore_csr[i], reg32_read(addr + (i << 2)));
- }
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
-
- ddr_dbg("restore 1d2d training registers done \n");
-}
-#endif
diff --git a/board/freescale/imx8mm_val/ddr/ddr4/save_1d2d_trained_csr_ddr4_p012.c b/board/freescale/imx8mm_val/ddr/ddr4/save_1d2d_trained_csr_ddr4_p012.c
deleted file mode 100644
index 179fabe..0000000
--- a/board/freescale/imx8mm_val/ddr/ddr4/save_1d2d_trained_csr_ddr4_p012.c
+++ /dev/null
@@ -1,1044 +0,0 @@
-/*
- * Copyright 2018 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/ddr.h>
-#include <asm/arch/clock.h>
-#include "ddr4_define.h"
-
-#ifdef ENABLE_RETENTION
-static const unsigned int save_csr[] = {
- 0x200b2,
- 0x1200b2,
- 0x2200b2,
- 0x200cb,
-#ifdef RUN_ON_SILICON
- 0x10043,
- 0x110043,
- 0x210043,
- 0x10143,
- 0x110143,
- 0x210143,
- 0x11043,
- 0x111043,
- 0x211043,
- 0x11143,
- 0x111143,
- 0x211143,
- 0x12043,
- 0x112043,
- 0x212043,
- 0x12143,
- 0x112143,
- 0x212143,
- 0x13043,
- 0x113043,
- 0x213043,
- 0x13143,
- 0x113143,
- 0x213143,
- 0x80,
- 0x100080,
- 0x200080,
- 0x1080,
- 0x101080,
- 0x201080,
- 0x2080,
- 0x102080,
- 0x202080,
- 0x3080,
- 0x103080,
- 0x203080,
- 0x4080,
- 0x104080,
- 0x204080,
- 0x5080,
- 0x105080,
- 0x205080,
- 0x6080,
- 0x106080,
- 0x206080,
- 0x7080,
- 0x107080,
- 0x207080,
- 0x8080,
- 0x108080,
- 0x208080,
- 0x9080,
- 0x109080,
- 0x209080,
- 0x10080,
- 0x110080,
- 0x210080,
- 0x10180,
- 0x110180,
- 0x210180,
- 0x10081,
- 0x110081,
- 0x210081,
- 0x10181,
- 0x110181,
- 0x210181,
- 0x10082,
- 0x110082,
- 0x210082,
- 0x10182,
- 0x110182,
- 0x210182,
- 0x10083,
- 0x110083,
- 0x210083,
- 0x10183,
- 0x110183,
- 0x210183,
- 0x11080,
- 0x111080,
- 0x211080,
- 0x11180,
- 0x111180,
- 0x211180,
- 0x11081,
- 0x111081,
- 0x211081,
- 0x11181,
- 0x111181,
- 0x211181,
- 0x11082,
- 0x111082,
- 0x211082,
- 0x11182,
- 0x111182,
- 0x211182,
- 0x11083,
- 0x111083,
- 0x211083,
- 0x11183,
- 0x111183,
- 0x211183,
- 0x12080,
- 0x112080,
- 0x212080,
- 0x12180,
- 0x112180,
- 0x212180,
- 0x12081,
- 0x112081,
- 0x212081,
- 0x12181,
- 0x112181,
- 0x212181,
- 0x12082,
- 0x112082,
- 0x212082,
- 0x12182,
- 0x112182,
- 0x212182,
- 0x12083,
- 0x112083,
- 0x212083,
- 0x12183,
- 0x112183,
- 0x212183,
- 0x13080,
- 0x113080,
- 0x213080,
- 0x13180,
- 0x113180,
- 0x213180,
- 0x13081,
- 0x113081,
- 0x213081,
- 0x13181,
- 0x113181,
- 0x213181,
- 0x13082,
- 0x113082,
- 0x213082,
- 0x13182,
- 0x113182,
- 0x213182,
- 0x13083,
- 0x113083,
- 0x213083,
- 0x13183,
- 0x113183,
- 0x213183,
- 0x100d0,
- 0x1100d0,
- 0x2100d0,
- 0x101d0,
- 0x1101d0,
- 0x2101d0,
- 0x100d1,
- 0x1100d1,
- 0x2100d1,
- 0x101d1,
- 0x1101d1,
- 0x2101d1,
- 0x100d2,
- 0x1100d2,
- 0x2100d2,
- 0x101d2,
- 0x1101d2,
- 0x2101d2,
- 0x100d3,
- 0x1100d3,
- 0x2100d3,
- 0x101d3,
- 0x1101d3,
- 0x2101d3,
- 0x110d0,
- 0x1110d0,
- 0x2110d0,
- 0x111d0,
- 0x1111d0,
- 0x2111d0,
- 0x110d1,
- 0x1110d1,
- 0x2110d1,
- 0x111d1,
- 0x1111d1,
- 0x2111d1,
- 0x110d2,
- 0x1110d2,
- 0x2110d2,
- 0x111d2,
- 0x1111d2,
- 0x2111d2,
- 0x110d3,
- 0x1110d3,
- 0x2110d3,
- 0x111d3,
- 0x1111d3,
- 0x2111d3,
- 0x120d0,
- 0x1120d0,
- 0x2120d0,
- 0x121d0,
- 0x1121d0,
- 0x2121d0,
- 0x120d1,
- 0x1120d1,
- 0x2120d1,
- 0x121d1,
- 0x1121d1,
- 0x2121d1,
- 0x120d2,
- 0x1120d2,
- 0x2120d2,
- 0x121d2,
- 0x1121d2,
- 0x2121d2,
- 0x120d3,
- 0x1120d3,
- 0x2120d3,
- 0x121d3,
- 0x1121d3,
- 0x2121d3,
- 0x130d0,
- 0x1130d0,
- 0x2130d0,
- 0x131d0,
- 0x1131d0,
- 0x2131d0,
- 0x130d1,
- 0x1130d1,
- 0x2130d1,
- 0x131d1,
- 0x1131d1,
- 0x2131d1,
- 0x130d2,
- 0x1130d2,
- 0x2130d2,
- 0x131d2,
- 0x1131d2,
- 0x2131d2,
- 0x130d3,
- 0x1130d3,
- 0x2130d3,
- 0x131d3,
- 0x1131d3,
- 0x2131d3,
- 0x10068,
- 0x10168,
- 0x10268,
- 0x10368,
- 0x10468,
- 0x10568,
- 0x10668,
- 0x10768,
- 0x10868,
- 0x10069,
- 0x10169,
- 0x10269,
- 0x10369,
- 0x10469,
- 0x10569,
- 0x10669,
- 0x10769,
- 0x10869,
- 0x1006a,
- 0x1016a,
- 0x1026a,
- 0x1036a,
- 0x1046a,
- 0x1056a,
- 0x1066a,
- 0x1076a,
- 0x1086a,
- 0x1006b,
- 0x1016b,
- 0x1026b,
- 0x1036b,
- 0x1046b,
- 0x1056b,
- 0x1066b,
- 0x1076b,
- 0x1086b,
- 0x11068,
- 0x11168,
- 0x11268,
- 0x11368,
- 0x11468,
- 0x11568,
- 0x11668,
- 0x11768,
- 0x11868,
- 0x11069,
- 0x11169,
- 0x11269,
- 0x11369,
- 0x11469,
- 0x11569,
- 0x11669,
- 0x11769,
- 0x11869,
- 0x1106a,
- 0x1116a,
- 0x1126a,
- 0x1136a,
- 0x1146a,
- 0x1156a,
- 0x1166a,
- 0x1176a,
- 0x1186a,
- 0x1106b,
- 0x1116b,
- 0x1126b,
- 0x1136b,
- 0x1146b,
- 0x1156b,
- 0x1166b,
- 0x1176b,
- 0x1186b,
- 0x12068,
- 0x12168,
- 0x12268,
- 0x12368,
- 0x12468,
- 0x12568,
- 0x12668,
- 0x12768,
- 0x12868,
- 0x12069,
- 0x12169,
- 0x12269,
- 0x12369,
- 0x12469,
- 0x12569,
- 0x12669,
- 0x12769,
- 0x12869,
- 0x1206a,
- 0x1216a,
- 0x1226a,
- 0x1236a,
- 0x1246a,
- 0x1256a,
- 0x1266a,
- 0x1276a,
- 0x1286a,
- 0x1206b,
- 0x1216b,
- 0x1226b,
- 0x1236b,
- 0x1246b,
- 0x1256b,
- 0x1266b,
- 0x1276b,
- 0x1286b,
- 0x13068,
- 0x13168,
- 0x13268,
- 0x13368,
- 0x13468,
- 0x13568,
- 0x13668,
- 0x13768,
- 0x13868,
- 0x13069,
- 0x13169,
- 0x13269,
- 0x13369,
- 0x13469,
- 0x13569,
- 0x13669,
- 0x13769,
- 0x13869,
- 0x1306a,
- 0x1316a,
- 0x1326a,
- 0x1336a,
- 0x1346a,
- 0x1356a,
- 0x1366a,
- 0x1376a,
- 0x1386a,
- 0x1306b,
- 0x1316b,
- 0x1326b,
- 0x1336b,
- 0x1346b,
- 0x1356b,
- 0x1366b,
- 0x1376b,
- 0x1386b,
- 0x1008c,
- 0x11008c,
- 0x21008c,
- 0x1018c,
- 0x11018c,
- 0x21018c,
- 0x1008d,
- 0x11008d,
- 0x21008d,
- 0x1018d,
- 0x11018d,
- 0x21018d,
- 0x1008e,
- 0x11008e,
- 0x21008e,
- 0x1018e,
- 0x11018e,
- 0x21018e,
- 0x1008f,
- 0x11008f,
- 0x21008f,
- 0x1018f,
- 0x11018f,
- 0x21018f,
- 0x1108c,
- 0x11108c,
- 0x21108c,
- 0x1118c,
- 0x11118c,
- 0x21118c,
- 0x1108d,
- 0x11108d,
- 0x21108d,
- 0x1118d,
- 0x11118d,
- 0x21118d,
- 0x1108e,
- 0x11108e,
- 0x21108e,
- 0x1118e,
- 0x11118e,
- 0x21118e,
- 0x1108f,
- 0x11108f,
- 0x21108f,
- 0x1118f,
- 0x11118f,
- 0x21118f,
- 0x1208c,
- 0x11208c,
- 0x21208c,
- 0x1218c,
- 0x11218c,
- 0x21218c,
- 0x1208d,
- 0x11208d,
- 0x21208d,
- 0x1218d,
- 0x11218d,
- 0x21218d,
- 0x1208e,
- 0x11208e,
- 0x21208e,
- 0x1218e,
- 0x11218e,
- 0x21218e,
- 0x1208f,
- 0x11208f,
- 0x21208f,
- 0x1218f,
- 0x11218f,
- 0x21218f,
- 0x1308c,
- 0x11308c,
- 0x21308c,
- 0x1318c,
- 0x11318c,
- 0x21318c,
- 0x1308d,
- 0x11308d,
- 0x21308d,
- 0x1318d,
- 0x11318d,
- 0x21318d,
- 0x1308e,
- 0x11308e,
- 0x21308e,
- 0x1318e,
- 0x11318e,
- 0x21318e,
- 0x1308f,
- 0x11308f,
- 0x21308f,
- 0x1318f,
- 0x11318f,
- 0x21318f,
- 0x100c0,
- 0x1100c0,
- 0x2100c0,
- 0x101c0,
- 0x1101c0,
- 0x2101c0,
- 0x102c0,
- 0x1102c0,
- 0x2102c0,
- 0x103c0,
- 0x1103c0,
- 0x2103c0,
- 0x104c0,
- 0x1104c0,
- 0x2104c0,
- 0x105c0,
- 0x1105c0,
- 0x2105c0,
- 0x106c0,
- 0x1106c0,
- 0x2106c0,
- 0x107c0,
- 0x1107c0,
- 0x2107c0,
- 0x108c0,
- 0x1108c0,
- 0x2108c0,
- 0x100c1,
- 0x1100c1,
- 0x2100c1,
- 0x101c1,
- 0x1101c1,
- 0x2101c1,
- 0x102c1,
- 0x1102c1,
- 0x2102c1,
- 0x103c1,
- 0x1103c1,
- 0x2103c1,
- 0x104c1,
- 0x1104c1,
- 0x2104c1,
- 0x105c1,
- 0x1105c1,
- 0x2105c1,
- 0x106c1,
- 0x1106c1,
- 0x2106c1,
- 0x107c1,
- 0x1107c1,
- 0x2107c1,
- 0x108c1,
- 0x1108c1,
- 0x2108c1,
- 0x100c2,
- 0x1100c2,
- 0x2100c2,
- 0x101c2,
- 0x1101c2,
- 0x2101c2,
- 0x102c2,
- 0x1102c2,
- 0x2102c2,
- 0x103c2,
- 0x1103c2,
- 0x2103c2,
- 0x104c2,
- 0x1104c2,
- 0x2104c2,
- 0x105c2,
- 0x1105c2,
- 0x2105c2,
- 0x106c2,
- 0x1106c2,
- 0x2106c2,
- 0x107c2,
- 0x1107c2,
- 0x2107c2,
- 0x108c2,
- 0x1108c2,
- 0x2108c2,
- 0x100c3,
- 0x1100c3,
- 0x2100c3,
- 0x101c3,
- 0x1101c3,
- 0x2101c3,
- 0x102c3,
- 0x1102c3,
- 0x2102c3,
- 0x103c3,
- 0x1103c3,
- 0x2103c3,
- 0x104c3,
- 0x1104c3,
- 0x2104c3,
- 0x105c3,
- 0x1105c3,
- 0x2105c3,
- 0x106c3,
- 0x1106c3,
- 0x2106c3,
- 0x107c3,
- 0x1107c3,
- 0x2107c3,
- 0x108c3,
- 0x1108c3,
- 0x2108c3,
- 0x110c0,
- 0x1110c0,
- 0x2110c0,
- 0x111c0,
- 0x1111c0,
- 0x2111c0,
- 0x112c0,
- 0x1112c0,
- 0x2112c0,
- 0x113c0,
- 0x1113c0,
- 0x2113c0,
- 0x114c0,
- 0x1114c0,
- 0x2114c0,
- 0x115c0,
- 0x1115c0,
- 0x2115c0,
- 0x116c0,
- 0x1116c0,
- 0x2116c0,
- 0x117c0,
- 0x1117c0,
- 0x2117c0,
- 0x118c0,
- 0x1118c0,
- 0x2118c0,
- 0x110c1,
- 0x1110c1,
- 0x2110c1,
- 0x111c1,
- 0x1111c1,
- 0x2111c1,
- 0x112c1,
- 0x1112c1,
- 0x2112c1,
- 0x113c1,
- 0x1113c1,
- 0x2113c1,
- 0x114c1,
- 0x1114c1,
- 0x2114c1,
- 0x115c1,
- 0x1115c1,
- 0x2115c1,
- 0x116c1,
- 0x1116c1,
- 0x2116c1,
- 0x117c1,
- 0x1117c1,
- 0x2117c1,
- 0x118c1,
- 0x1118c1,
- 0x2118c1,
- 0x110c2,
- 0x1110c2,
- 0x2110c2,
- 0x111c2,
- 0x1111c2,
- 0x2111c2,
- 0x112c2,
- 0x1112c2,
- 0x2112c2,
- 0x113c2,
- 0x1113c2,
- 0x2113c2,
- 0x114c2,
- 0x1114c2,
- 0x2114c2,
- 0x115c2,
- 0x1115c2,
- 0x2115c2,
- 0x116c2,
- 0x1116c2,
- 0x2116c2,
- 0x117c2,
- 0x1117c2,
- 0x2117c2,
- 0x118c2,
- 0x1118c2,
- 0x2118c2,
- 0x110c3,
- 0x1110c3,
- 0x2110c3,
- 0x111c3,
- 0x1111c3,
- 0x2111c3,
- 0x112c3,
- 0x1112c3,
- 0x2112c3,
- 0x113c3,
- 0x1113c3,
- 0x2113c3,
- 0x114c3,
- 0x1114c3,
- 0x2114c3,
- 0x115c3,
- 0x1115c3,
- 0x2115c3,
- 0x116c3,
- 0x1116c3,
- 0x2116c3,
- 0x117c3,
- 0x1117c3,
- 0x2117c3,
- 0x118c3,
- 0x1118c3,
- 0x2118c3,
- 0x120c0,
- 0x1120c0,
- 0x2120c0,
- 0x121c0,
- 0x1121c0,
- 0x2121c0,
- 0x122c0,
- 0x1122c0,
- 0x2122c0,
- 0x123c0,
- 0x1123c0,
- 0x2123c0,
- 0x124c0,
- 0x1124c0,
- 0x2124c0,
- 0x125c0,
- 0x1125c0,
- 0x2125c0,
- 0x126c0,
- 0x1126c0,
- 0x2126c0,
- 0x127c0,
- 0x1127c0,
- 0x2127c0,
- 0x128c0,
- 0x1128c0,
- 0x2128c0,
- 0x120c1,
- 0x1120c1,
- 0x2120c1,
- 0x121c1,
- 0x1121c1,
- 0x2121c1,
- 0x122c1,
- 0x1122c1,
- 0x2122c1,
- 0x123c1,
- 0x1123c1,
- 0x2123c1,
- 0x124c1,
- 0x1124c1,
- 0x2124c1,
- 0x125c1,
- 0x1125c1,
- 0x2125c1,
- 0x126c1,
- 0x1126c1,
- 0x2126c1,
- 0x127c1,
- 0x1127c1,
- 0x2127c1,
- 0x128c1,
- 0x1128c1,
- 0x2128c1,
- 0x120c2,
- 0x1120c2,
- 0x2120c2,
- 0x121c2,
- 0x1121c2,
- 0x2121c2,
- 0x122c2,
- 0x1122c2,
- 0x2122c2,
- 0x123c2,
- 0x1123c2,
- 0x2123c2,
- 0x124c2,
- 0x1124c2,
- 0x2124c2,
- 0x125c2,
- 0x1125c2,
- 0x2125c2,
- 0x126c2,
- 0x1126c2,
- 0x2126c2,
- 0x127c2,
- 0x1127c2,
- 0x2127c2,
- 0x128c2,
- 0x1128c2,
- 0x2128c2,
- 0x120c3,
- 0x1120c3,
- 0x2120c3,
- 0x121c3,
- 0x1121c3,
- 0x2121c3,
- 0x122c3,
- 0x1122c3,
- 0x2122c3,
- 0x123c3,
- 0x1123c3,
- 0x2123c3,
- 0x124c3,
- 0x1124c3,
- 0x2124c3,
- 0x125c3,
- 0x1125c3,
- 0x2125c3,
- 0x126c3,
- 0x1126c3,
- 0x2126c3,
- 0x127c3,
- 0x1127c3,
- 0x2127c3,
- 0x128c3,
- 0x1128c3,
- 0x2128c3,
- 0x130c0,
- 0x1130c0,
- 0x2130c0,
- 0x131c0,
- 0x1131c0,
- 0x2131c0,
- 0x132c0,
- 0x1132c0,
- 0x2132c0,
- 0x133c0,
- 0x1133c0,
- 0x2133c0,
- 0x134c0,
- 0x1134c0,
- 0x2134c0,
- 0x135c0,
- 0x1135c0,
- 0x2135c0,
- 0x136c0,
- 0x1136c0,
- 0x2136c0,
- 0x137c0,
- 0x1137c0,
- 0x2137c0,
- 0x138c0,
- 0x1138c0,
- 0x2138c0,
- 0x130c1,
- 0x1130c1,
- 0x2130c1,
- 0x131c1,
- 0x1131c1,
- 0x2131c1,
- 0x132c1,
- 0x1132c1,
- 0x2132c1,
- 0x133c1,
- 0x1133c1,
- 0x2133c1,
- 0x134c1,
- 0x1134c1,
- 0x2134c1,
- 0x135c1,
- 0x1135c1,
- 0x2135c1,
- 0x136c1,
- 0x1136c1,
- 0x2136c1,
- 0x137c1,
- 0x1137c1,
- 0x2137c1,
- 0x138c1,
- 0x1138c1,
- 0x2138c1,
- 0x130c2,
- 0x1130c2,
- 0x2130c2,
- 0x131c2,
- 0x1131c2,
- 0x2131c2,
- 0x132c2,
- 0x1132c2,
- 0x2132c2,
- 0x133c2,
- 0x1133c2,
- 0x2133c2,
- 0x134c2,
- 0x1134c2,
- 0x2134c2,
- 0x135c2,
- 0x1135c2,
- 0x2135c2,
- 0x136c2,
- 0x1136c2,
- 0x2136c2,
- 0x137c2,
- 0x1137c2,
- 0x2137c2,
- 0x138c2,
- 0x1138c2,
- 0x2138c2,
- 0x130c3,
- 0x1130c3,
- 0x2130c3,
- 0x131c3,
- 0x1131c3,
- 0x2131c3,
- 0x132c3,
- 0x1132c3,
- 0x2132c3,
- 0x133c3,
- 0x1133c3,
- 0x2133c3,
- 0x134c3,
- 0x1134c3,
- 0x2134c3,
- 0x135c3,
- 0x1135c3,
- 0x2135c3,
- 0x136c3,
- 0x1136c3,
- 0x2136c3,
- 0x137c3,
- 0x1137c3,
- 0x2137c3,
- 0x138c3,
- 0x1138c3,
- 0x2138c3,
- 0x10020,
- 0x110020,
- 0x210020,
- 0x11020,
- 0x111020,
- 0x211020,
- 0x12020,
- 0x112020,
- 0x212020,
- 0x13020,
- 0x113020,
- 0x213020,
- 0x2007d,
- 0x12007d,
- 0x22007d,
- 0x10040,
- 0x10140,
- 0x10240,
- 0x10340,
- 0x10440,
- 0x10540,
- 0x10640,
- 0x10740,
- 0x10840,
- 0x10030,
- 0x10130,
- 0x10230,
- 0x10330,
- 0x10430,
- 0x10530,
- 0x10630,
- 0x10730,
- 0x10830,
- 0x11040,
- 0x11140,
- 0x11240,
- 0x11340,
- 0x11440,
- 0x11540,
- 0x11640,
- 0x11740,
- 0x11840,
- 0x11030,
- 0x11130,
- 0x11230,
- 0x11330,
- 0x11430,
- 0x11530,
- 0x11630,
- 0x11730,
- 0x11830,
- 0x12040,
- 0x12140,
- 0x12240,
- 0x12340,
- 0x12440,
- 0x12540,
- 0x12640,
- 0x12740,
- 0x12840,
- 0x12030,
- 0x12130,
- 0x12230,
- 0x12330,
- 0x12430,
- 0x12530,
- 0x12630,
- 0x12730,
- 0x12830,
- 0x13040,
- 0x13140,
- 0x13240,
- 0x13340,
- 0x13440,
- 0x13540,
- 0x13640,
- 0x13740,
- 0x13840,
- 0x13030,
- 0x13130,
- 0x13230,
- 0x13330,
- 0x13430,
- 0x13530,
- 0x13630,
- 0x13730,
- 0x13830,
-#endif
- 0
-};
-
-void save_1d2d_trained_csr_ddr4_p012(unsigned int addr)
-{
- unsigned int i;
-
- dwc_ddrphy_apb_wr(0xd0000, 0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
- dwc_ddrphy_apb_wr(0xc0080, 0x3); /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */
- for (i = 0; save_csr[i] != 0; i++) {
- reg32_write(addr + (i << 2), dwc_ddrphy_apb_rd(save_csr[i]));
- }
- dwc_ddrphy_apb_wr(0xc0080, 0x0); /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */
- dwc_ddrphy_apb_wr(0xd0000, 0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
-
- ddr_dbg("save 1d2d training registers done \n");
-}
-#endif
diff --git a/board/freescale/imx8mm_val/ddr/helper.c b/board/freescale/imx8mm_val/ddr/helper.c
deleted file mode 100644
index 564f582..0000000
--- a/board/freescale/imx8mm_val/ddr/helper.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright 2018 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <asm/io.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/ddr.h>
-#include <asm/sections.h>
-
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define IMEM_LEN 32768
-#define DMEM_LEN 16384
-#define IMEM_2D_OFFSET 49152
-
-#define IMEM_OFFSET_ADDR 0x00050000
-#define DMEM_OFFSET_ADDR 0x00054000
-#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
-
-/* We need PHY iMEM PHY is 32KB padded */
-void ddr_load_train_code(enum fw_type type)
-{
- u32 tmp32, i;
- u32 error = 0;
- unsigned long pr_to32, pr_from32;
- unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
- unsigned long imem_start = (unsigned long)&_end + fw_offset;
- unsigned long dmem_start = imem_start + IMEM_LEN;
-
- pr_from32 = imem_start;
- pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
- for (i = 0x0; i < IMEM_LEN; ) {
- tmp32 = readl(pr_from32);
- writew(tmp32 & 0x0000ffff, pr_to32);
- pr_to32 += 4;
- writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
- pr_to32 += 4;
- pr_from32 += 4;
- i += 4;
- }
-
- pr_from32 = dmem_start;
- pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
- for (i = 0x0; i < DMEM_LEN;) {
- tmp32 = readl(pr_from32);
- writew(tmp32 & 0x0000ffff, pr_to32);
- pr_to32 += 4;
- writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
- pr_to32 += 4;
- pr_from32 += 4;
- i += 4;
- }
-
- printf("check ddr4_pmu_train_imem code\n");
- pr_from32 = imem_start;
- pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
- for (i = 0x0; i < IMEM_LEN;) {
- tmp32 = (readw(pr_to32) & 0x0000ffff);
- pr_to32 += 4;
- tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
-
- if (tmp32 != readl(pr_from32)) {
- printf("%lx %lx\n", pr_from32, pr_to32);
- error++;
- }
- pr_from32 += 4;
- pr_to32 += 4;
- i += 4;
- }
- if (error)
- printf("check ddr4_pmu_train_imem code fail=%d\n", error);
- else
- printf("check ddr4_pmu_train_imem code pass\n");
-
- printf("check ddr4_pmu_train_dmem code\n");
- pr_from32 = dmem_start;
- pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
- for (i = 0x0; i < DMEM_LEN;) {
- tmp32 = (readw(pr_to32) & 0x0000ffff);
- pr_to32 += 4;
- tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
- if (tmp32 != readl(pr_from32)) {
- printf("%lx %lx\n", pr_from32, pr_to32);
- error++;
- }
- pr_from32 += 4;
- pr_to32 += 4;
- i += 4;
- }
-
- if (error)
- printf("check ddr4_pmu_train_dmem code fail=%d", error);
- else
- printf("check ddr4_pmu_train_dmem code pass\n");
-}
diff --git a/board/freescale/imx8mm_val/ddr/wait_ddrphy_training_complete.c b/board/freescale/imx8mm_val/ddr/wait_ddrphy_training_complete.c
deleted file mode 100644
index e0da1be..0000000
--- a/board/freescale/imx8mm_val/ddr/wait_ddrphy_training_complete.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright 2017 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/ddr.h>
-#include <asm/arch/clock.h>
-#include "ddr.h"
-
-static inline void poll_pmu_message_ready(void)
-{
- unsigned int reg;
-
- do {
- reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
- } while (reg & 0x1);
-}
-
-static inline void ack_pmu_message_recieve(void)
-{
- unsigned int reg;
-
- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031, 0x0);
-
- do {
- reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
- } while (!(reg & 0x1));
-
- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031, 0x1);
-}
-
-static inline unsigned int get_mail(void)
-{
- unsigned int reg;
-
- poll_pmu_message_ready();
-
- reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
-
- ack_pmu_message_recieve();
-
- return reg;
-}
-
-static inline unsigned int get_stream_message(void)
-{
- unsigned int reg, reg2;
-
- poll_pmu_message_ready();
-
- reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
-
- reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034);
-
- reg2 = (reg2 << 16) | reg;
-
- ack_pmu_message_recieve();
-
- return reg2;
-}
-
-static inline void decode_major_message(unsigned int mail)
-{
- ddr_dbg("[PMU Major message = 0x%08x]\n", mail);
-}
-
-static inline void decode_streaming_message(void)
-{
- unsigned int string_index, arg __maybe_unused;
- int i = 0;
-
- string_index = get_stream_message();
- ddr_dbg(" PMU String index = 0x%08x\n", string_index);
- while (i < (string_index & 0xffff)) {
- arg = get_stream_message();
- ddr_dbg(" arg[%d] = 0x%08x\n", i, arg);
- i++;
- }
-
- ddr_dbg("\n");
-}
-
-void wait_ddrphy_training_complete(void)
-{
- unsigned int mail;
- while (1) {
- mail = get_mail();
- decode_major_message(mail);
- if (mail == 0x08) {
- decode_streaming_message();
- } else if (mail == 0x07) {
- printf("Training PASS\n");
- break;
- } else if (mail == 0xff) {
- printf("Training FAILED\n");
- break;
- }
- }
-}
diff --git a/board/freescale/imx8mm_val/ddr3l_timing.c b/board/freescale/imx8mm_val/ddr3l_timing.c
new file mode 100644
index 0000000..df3e5e1
--- /dev/null
+++ b/board/freescale/imx8mm_val/ddr3l_timing.c
@@ -0,0 +1,659 @@
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr3l_ddrc_cfg[] = {
+ { DDRC_MSTR(0), 0xa3040001 },
+ { DDRC_PWRCTL(0), 0x000000a8 },
+ { DDRC_PWRTMG(0), 0x00532203 },
+ { DDRC_RFSHCTL0(0), 0x00203020 },
+ { DDRC_RFSHCTL1(0), 0x0001000d },
+ { DDRC_RFSHCTL3(0), 0x00000000 },
+ { DDRC_RFSHTMG(0), 0x0061008c },
+ { DDRC_CRCPARCTL0(0), 0x00000000 },
+ { DDRC_CRCPARCTL1(0), 0x00000000 },
+ { DDRC_INIT0(0), 0xc0030002 },
+ { DDRC_INIT1(0), 0x0001000b },
+ { DDRC_INIT2(0), 0x00006303 },
+ { DDRC_INIT3(0), 0x0d700004 },/* MR1, MR0 */
+ { DDRC_INIT4(0), 0x00180000 },/* MR2 */
+ { DDRC_INIT5(0), 0x00090071 },
+ { DDRC_INIT6(0), 0x00000000 },
+ { DDRC_INIT7(0), 0x00000000 },
+ { DDRC_DIMMCTL(0), 0x00000032 }, /* [1] dimm_addr_mirr_en, it will effect the MRS if use umctl2 to initi dram. */
+ { DDRC_RANKCTL(0), 0x00000ee5 },
+ { DDRC_DRAMTMG0(0), 0x0c101a0e },
+ { DDRC_DRAMTMG1(0), 0x000a0314 },
+ { DDRC_DRAMTMG2(0), 0x04060509 },
+ { DDRC_DRAMTMG3(0), 0x00002006 },
+ { DDRC_DRAMTMG4(0), 0x06020306 },
+ { DDRC_DRAMTMG5(0), 0x0b060202 },
+ { DDRC_DRAMTMG6(0), 0x060a0009 },
+ { DDRC_DRAMTMG7(0), 0x0000060b },
+ { DDRC_DRAMTMG8(0), 0x01017c0a },
+ { DDRC_DRAMTMG9(0), 0x4000000e },
+ { DDRC_DRAMTMG10(0), 0x00070803 },
+ { DDRC_DRAMTMG11(0), 0x0101000b },
+ { DDRC_DRAMTMG12(0), 0x00000000 },
+ { DDRC_DRAMTMG13(0), 0x5d000000 },
+ { DDRC_DRAMTMG14(0), 0x00000b39 },
+ { DDRC_DRAMTMG15(0), 0x80000000 },
+ { DDRC_DRAMTMG17(0), 0x00f1006a },
+ { DDRC_ZQCTL0(0), 0x50800020 },
+ { DDRC_ZQCTL1(0), 0x00000070 },
+ { DDRC_ZQCTL2(0), 0x00000000 },
+ { DDRC_DFITMG0(0), 0x03868203 },
+ { DDRC_DFITMG1(0), 0x00020103 },
+ { DDRC_DFILPCFG0(0), 0x07713021 },
+ { DDRC_DFILPCFG1(0), 0x00000010 },
+ { DDRC_DFIUPD0(0), 0xe0400018 },
+ { DDRC_DFIUPD1(0), 0x0005003c },
+ { DDRC_DFIUPD2(0), 0x80000000 },
+ { DDRC_DFIMISC(0), 0x00000001 },
+ { DDRC_DFITMG2(0), 0x00000603 },
+ { DDRC_DFITMG3(0), 0x00000001 },
+ { DDRC_DBICTL(0), 0x00000001 },
+ { DDRC_DFIPHYMSTR(0), 0x00000000 },
+
+ { DDRC_ADDRMAP0(0), 0x00000016 }, /* [4:0] cs-bit0: 6+22=28; [12:8] cs-bit1: 7+0 */
+ { DDRC_ADDRMAP1(0), 0x00080808 }, /* [5:0] bank b0: 2+8; [13:8] b1: P3+8 ; [21:16] b2: 4+8 */
+ { DDRC_ADDRMAP2(0), 0x00000000 }, /* [3:0] col-b2: 2; [11:8] col-b3: 3; [19:16] col-b4: 4 ; [27:24] col-b5: 5 */
+ { DDRC_ADDRMAP3(0), 0x00000000 }, /* [3:0] col-b6: 6; [11:8] col-b7: 7; [19:16] col-b8: 8 ; [27:24] col-b9: 9 */
+ { DDRC_ADDRMAP4(0), 0x00001f1f }, /* col-b10, col-b11 not used */
+ { DDRC_ADDRMAP5(0), 0x07070707 }, /* [3:0] row-b0: 6; [11:8] row-b1: 7; [19:16] row-b2_b10 ; [27:24] row-b11: 17 */
+ { DDRC_ADDRMAP6(0), 0x0f070707 }, /* [3:0] row-b12:18; [11:8] row-b13: 19; [19:16] row-b14:20 */
+ { DDRC_ADDRMAP7(0), 0x00000f0f },
+ { DDRC_ADDRMAP8(0), 0x00000000 }, /* [5:0] bg-b0; [13:8]bg-b1 */
+ { DDRC_ADDRMAP9(0), 0x0a020b06 }, /* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
+ { DDRC_ADDRMAP10(0), 0x0a0a0a0a },/* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
+ { DDRC_ADDRMAP11(0), 0x00000000 },
+
+ { DDRC_ODTCFG(0), 0x041d0f5c },
+ { DDRC_ODTMAP(0), 0x00000201 },
+ { DDRC_SCHED(0), 0x7ab50b07 },
+ { DDRC_SCHED1(0), 0x00000022 },
+ { DDRC_PERFHPR1(0), 0x7b00665e },
+ { DDRC_PERFLPR1(0), 0x2b00c4e1 },
+ { DDRC_PERFWR1(0), 0xb700c9fe },
+ { DDRC_DBG0(0), 0x00000017 },
+ { DDRC_DBG1(0), 0x00000000 },
+ { DDRC_DBGCMD(0), 0x00000000 },
+ { DDRC_SWCTL(0), 0x00000001 },
+ { DDRC_POISONCFG(0), 0x00010000 },
+ { DDRC_PCCFG(0), 0x00000100 },
+ { DDRC_PCFGR_0(0), 0x00003051 },
+ { DDRC_PCFGW_0(0), 0x000061d2 },
+ { DDRC_PCTRL_0(0), 0x00000001 },
+ { DDRC_PCFGQOS0_0(0), 0x02100b04 },
+ { DDRC_PCFGQOS1_0(0), 0x003f0353 },
+ { DDRC_PCFGWQOS0_0(0), 0x00000002 },
+ { DDRC_PCFGWQOS1_0(0), 0x000005fd },
+
+ { DDRC_FREQ1_RFSHCTL0(0), 0x00d19034 },
+ { DDRC_FREQ1_RFSHTMG(0), 0x0040805e },
+ { DDRC_FREQ1_INIT3(0), 0x09300004 },
+ { DDRC_FREQ1_INIT4(0), 0x00080000 },
+ { DDRC_FREQ1_INIT6(0), 0x00000000 },
+ { DDRC_FREQ1_INIT7(0), 0x00000000 },
+ { DDRC_FREQ1_DRAMTMG0(0), 0x090e110a },
+ { DDRC_FREQ1_DRAMTMG1(0), 0x0007020e },
+ { DDRC_FREQ1_DRAMTMG2(0), 0x03040407 },
+ { DDRC_FREQ1_DRAMTMG3(0), 0x00002006 },
+ { DDRC_FREQ1_DRAMTMG4(0), 0x04020304 }, /* tRP=6 --> 7 */
+ { DDRC_FREQ1_DRAMTMG5(0), 0x09030202 },
+ { DDRC_FREQ1_DRAMTMG6(0), 0x0c020000 },
+ { DDRC_FREQ1_DRAMTMG7(0), 0x00000309 },
+ { DDRC_FREQ1_DRAMTMG8(0), 0x01010a06 },
+ { DDRC_FREQ1_DRAMTMG9(0), 0x00000003 },
+ { DDRC_FREQ1_DRAMTMG10(0), 0x00090906 },
+ { DDRC_FREQ1_DRAMTMG11(0), 0x01010011 },
+ { DDRC_FREQ1_DRAMTMG12(0), 0x00000000 },
+ { DDRC_FREQ1_DRAMTMG13(0), 0x40000000 },
+ { DDRC_FREQ1_DRAMTMG14(0), 0x000000f3 },
+ { DDRC_FREQ1_DRAMTMG15(0), 0x80000000 },
+ { DDRC_FREQ1_DRAMTMG17(0), 0x001a0046 },
+ { DDRC_FREQ1_ZQCTL0(0), 0x50800020 },
+ { DDRC_FREQ1_DFITMG0(0), 0x03828201 },
+ { DDRC_FREQ1_DFITMG1(0), 0x00020103 },
+ { DDRC_FREQ1_DFITMG2(0), 0x00000201 },
+ { DDRC_FREQ1_DFITMG3(0), 0x00000001 },
+ { DDRC_FREQ1_ODTCFG(0), 0x0a1a0768 },
+
+ { DDRC_FREQ2_RFSHCTL0(0), 0x00208014 },
+ { DDRC_FREQ2_RFSHTMG(0), 0x00308046 },
+ { DDRC_FREQ2_INIT3(0), 0x05200004 },
+ { DDRC_FREQ2_INIT4(0), 0x00000000 },
+ { DDRC_FREQ2_INIT6(0), 0x00000000 },
+ { DDRC_FREQ2_INIT7(0), 0x00000000 },
+ { DDRC_FREQ2_DRAMTMG0(0), 0x070a0c07 },
+ { DDRC_FREQ2_DRAMTMG1(0), 0x0005020b },
+ { DDRC_FREQ2_DRAMTMG2(0), 0x03030407 },
+ { DDRC_FREQ2_DRAMTMG3(0), 0x00002006 },
+ { DDRC_FREQ2_DRAMTMG4(0), 0x03020204 },
+ { DDRC_FREQ2_DRAMTMG5(0), 0x04070302 },
+ { DDRC_FREQ2_DRAMTMG6(0), 0x07080000 },
+ { DDRC_FREQ2_DRAMTMG7(0), 0x00000704 },
+ { DDRC_FREQ2_DRAMTMG8(0), 0x02026804 },
+ { DDRC_FREQ2_DRAMTMG9(0), 0x40000006 },
+ { DDRC_FREQ2_DRAMTMG10(0), 0x000c0b08 },
+ { DDRC_FREQ2_DRAMTMG11(0), 0x01010015 },
+ { DDRC_FREQ2_DRAMTMG12(0), 0x00000000 },
+ { DDRC_FREQ2_DRAMTMG13(0), 0x51000000 },
+ { DDRC_FREQ2_DRAMTMG14(0), 0x000002a0 },
+ { DDRC_FREQ2_DRAMTMG15(0), 0x00000000 },
+ { DDRC_FREQ2_DRAMTMG17(0), 0x008c0039 },
+ { DDRC_FREQ2_ZQCTL0(0), 0x50800020 },
+ { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
+ { DDRC_FREQ2_DFITMG1(0), 0x00020103 },
+ { DDRC_FREQ2_DFITMG2(0), 0x00000100 },
+ { DDRC_FREQ2_DFITMG3(0), 0x00000001 },
+ { DDRC_FREQ2_ODTCFG(0), 0x04050800 },
+
+ /* default start freq point */
+ { DDRC_MSTR2(0), 0x0},
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr3l_ddrphy_cfg[] = {
+ { 0x1005f, 0x3cf },
+ { 0x1015f, 0x3cf },
+ { 0x1105f, 0x3cf },
+ { 0x1115f, 0x3cf },
+ { 0x1205f, 0x3cf },
+ { 0x1215f, 0x3cf },
+ { 0x1305f, 0x3cf },
+ { 0x1315f, 0x3cf },
+
+ { 0x11005f, 0x3cf },
+ { 0x11015f, 0x3cf },
+ { 0x11105f, 0x3cf },
+ { 0x11115f, 0x3cf },
+ { 0x11205f, 0x3cf },
+ { 0x11215f, 0x3cf },
+ { 0x11305f, 0x3cf },
+ { 0x11315f, 0x3cf },
+
+ { 0x21005f, 0x3cf },
+ { 0x21015f, 0x3cf },
+ { 0x21105f, 0x3cf },
+ { 0x21115f, 0x3cf },
+ { 0x21205f, 0x3cf },
+ { 0x21215f, 0x3cf },
+ { 0x21305f, 0x3cf },
+ { 0x21315f, 0x3cf },
+
+ { 0x55, 0x365 },
+ { 0x1055, 0x365 },
+ { 0x2055, 0x365 },
+ { 0x3055, 0x365 },
+ { 0x4055, 0x65 },
+ { 0x5055, 0x65 },
+ { 0x6055, 0x365 },
+ { 0x7055, 0x365 },
+ { 0x8055, 0x365 },
+ { 0x9055, 0x365 },
+ { 0x200c5, 0xb },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x1 },
+ { 0x12002e, 0x1 },
+ { 0x22002e, 0x1 },
+ { 0x20024, 0x8 },
+ { 0x2003a, 0x0 },
+ { 0x120024, 0x8 },
+ { 0x2003a, 0x0 },
+ { 0x220024, 0x8 },
+ { 0x2003a, 0x0 },
+ { 0x20056, 0xa },
+ { 0x120056, 0xa },
+ { 0x220056, 0xa },
+ { 0x1004d, 0x618 },
+ { 0x1014d, 0x618 },
+ { 0x1104d, 0x618 },
+ { 0x1114d, 0x618 },
+ { 0x1204d, 0x618 },
+ { 0x1214d, 0x618 },
+ { 0x1304d, 0x618 },
+ { 0x1314d, 0x618 },
+ { 0x11004d, 0x618 },
+ { 0x11014d, 0x618 },
+ { 0x11104d, 0x618 },
+ { 0x11114d, 0x618 },
+ { 0x11204d, 0x618 },
+ { 0x11214d, 0x618 },
+ { 0x11304d, 0x618 },
+ { 0x11314d, 0x618 },
+ { 0x21004d, 0x618 },
+ { 0x21014d, 0x618 },
+ { 0x21104d, 0x618 },
+ { 0x21114d, 0x618 },
+ { 0x21204d, 0x618 },
+ { 0x21214d, 0x618 },
+ { 0x21304d, 0x618 },
+ { 0x21314d, 0x618 },
+ { 0x10049, 0xe38 },
+ { 0x10149, 0xe38 },
+ { 0x11049, 0xe38 },
+ { 0x11149, 0xe38 },
+ { 0x12049, 0xe38 },
+ { 0x12149, 0xe38 },
+ { 0x13049, 0xe38 },
+ { 0x13149, 0xe38 },
+ { 0x110049, 0xe38 },
+ { 0x110149, 0xe38 },
+ { 0x111049, 0xe38 },
+ { 0x111149, 0xe38 },
+ { 0x112049, 0xe38 },
+ { 0x112149, 0xe38 },
+ { 0x113049, 0xe38 },
+ { 0x113149, 0xe38 },
+ { 0x210049, 0xe38 },
+ { 0x210149, 0xe38 },
+ { 0x211049, 0xe38 },
+ { 0x211149, 0xe38 },
+ { 0x212049, 0xe38 },
+ { 0x212149, 0xe38 },
+ { 0x213049, 0xe38 },
+ { 0x213149, 0xe38 },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x5 },
+ { 0x20075, 0x0 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x190 },
+ { 0x120008, 0x85 },
+ { 0x220008, 0x53 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0xf8 },
+ { 0x10043, 0x581 },
+ { 0x10143, 0x581 },
+ { 0x11043, 0x581 },
+ { 0x11143, 0x581 },
+ { 0x12043, 0x581 },
+ { 0x12143, 0x581 },
+ { 0x13043, 0x581 },
+ { 0x13143, 0x581 },
+ { 0x1200b2, 0xf8 },
+ { 0x110043, 0x581 },
+ { 0x110143, 0x581 },
+ { 0x111043, 0x581 },
+ { 0x111143, 0x581 },
+ { 0x112043, 0x581 },
+ { 0x112143, 0x581 },
+ { 0x113043, 0x581 },
+ { 0x113143, 0x581 },
+ { 0x2200b2, 0xf8 },
+ { 0x210043, 0x581 },
+ { 0x210143, 0x581 },
+ { 0x211043, 0x581 },
+ { 0x211143, 0x581 },
+ { 0x212043, 0x581 },
+ { 0x212143, 0x581 },
+ { 0x213043, 0x581 },
+ { 0x213143, 0x581 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x5 },
+ { 0x120019, 0x5 },
+ { 0x220019, 0x5 },
+ { 0x200f0, 0x5555 },
+ { 0x200f1, 0x5555 },
+ { 0x200f2, 0x5555 },
+ { 0x200f3, 0x5555 },
+ { 0x200f4, 0x5555 },
+ { 0x200f5, 0x5555 },
+ { 0x200f6, 0x5555 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x20060, 0x2 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr3l_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x0 },
+ { 0x54003, 0x640 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x0 },
+ { 0x54006, 0x140 },
+ { 0x54007, 0x2000 },
+ { 0x54008, 0x303 },
+ { 0x54009, 0x200 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x31f },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0xd70 },
+ { 0x54030, 0x4 },
+ { 0x54031, 0x18 },
+ { 0x5403a, 0x1221 },
+ { 0x5403b, 0x4884 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr3l_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x1 },
+ { 0x54003, 0x214 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x0 },
+ { 0x54006, 0x140 },
+ { 0x54007, 0x2000 },
+ { 0x54008, 0x303 },
+ { 0x54009, 0x200 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x21f },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x930 },
+ { 0x54030, 0x4 },
+ { 0x54031, 0x8 },
+ { 0x5403a, 0x1221 },
+ { 0x5403b, 0x4884 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr3l_fsp2_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x2 },
+ { 0x54003, 0x14c },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x0 },
+ { 0x54006, 0x140 },
+ { 0x54007, 0x2000 },
+ { 0x54008, 0x303 },
+ { 0x54009, 0x200 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x21f },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x520 },
+ { 0x54030, 0x4 },
+ { 0x54031, 0x0 },
+ { 0x5403a, 0x1221 },
+ { 0x5403b, 0x4884 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr3l_phy_pie[] = {
+ { 0xd0000, 0x0 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+ { 0x90000, 0x10 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */
+ { 0x90001, 0x400 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */
+ { 0x90002, 0x10e }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */
+ { 0x90003, 0x0 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */
+ { 0x90004, 0x0 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */
+ { 0x90005, 0x8 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */
+ { 0x90029, 0xb }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */
+ { 0x9002a, 0x480 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */
+ { 0x9002b, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */
+ { 0x9002c, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */
+ { 0x9002d, 0x448 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */
+ { 0x9002e, 0x139 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */
+ { 0x9002f, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */
+ { 0x90030, 0x478 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */
+ { 0x90031, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */
+ { 0x90032, 0x2 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */
+ { 0x90033, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */
+ { 0x90034, 0x139 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */
+ { 0x90035, 0xf }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */
+ { 0x90036, 0x7c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */
+ { 0x90037, 0x139 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */
+ { 0x90038, 0x44 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */
+ { 0x90039, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */
+ { 0x9003a, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */
+ { 0x9003b, 0x14f }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */
+ { 0x9003c, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */
+ { 0x9003d, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */
+ { 0x9003e, 0x47 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */
+ { 0x9003f, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */
+ { 0x90040, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */
+ { 0x90041, 0x4f }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */
+ { 0x90042, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */
+ { 0x90043, 0x179 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */
+ { 0x90044, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */
+ { 0x90045, 0xe0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */
+ { 0x90046, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */
+ { 0x90047, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */
+ { 0x90048, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */
+ { 0x90049, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */
+ { 0x9004a, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */
+ { 0x9004b, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */
+ { 0x9004c, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */
+ { 0x9004d, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */
+ { 0x9004e, 0x45a }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */
+ { 0x9004f, 0x9 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */
+ { 0x90050, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */
+ { 0x90051, 0x448 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */
+ { 0x90052, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */
+ { 0x90053, 0x40 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */
+ { 0x90054, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */
+ { 0x90055, 0x179 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */
+ { 0x90056, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */
+ { 0x90057, 0x618 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */
+ { 0x90058, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */
+ { 0x90059, 0x40c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */
+ { 0x9005a, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */
+ { 0x9005b, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */
+ { 0x9005c, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */
+ { 0x9005d, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */
+ { 0x9005e, 0x48 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */
+ { 0x9005f, 0x4040 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */
+ { 0x90060, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */
+ { 0x90061, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */
+ { 0x90062, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */
+ { 0x90063, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */
+ { 0x90064, 0x48 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */
+ { 0x90065, 0x40 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */
+ { 0x90066, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */
+ { 0x90067, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */
+ { 0x90068, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */
+ { 0x90069, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */
+ { 0x9006a, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */
+ { 0x9006b, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */
+ { 0x9006c, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */
+ { 0x9006d, 0x78 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */
+ { 0x9006e, 0x549 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */
+ { 0x9006f, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */
+ { 0x90070, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */
+ { 0x90071, 0xd49 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */
+ { 0x90072, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */
+ { 0x90073, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */
+ { 0x90074, 0x94a }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */
+ { 0x90075, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */
+ { 0x90076, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */
+ { 0x90077, 0x441 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */
+ { 0x90078, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */
+ { 0x90079, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */
+ { 0x9007a, 0x42 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */
+ { 0x9007b, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */
+ { 0x9007c, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */
+ { 0x9007d, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */
+ { 0x9007e, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */
+ { 0x9007f, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */
+ { 0x90080, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */
+ { 0x90081, 0xe0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */
+ { 0x90082, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */
+ { 0x90083, 0xa }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */
+ { 0x90084, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */
+ { 0x90085, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */
+ { 0x90086, 0x9 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */
+ { 0x90087, 0x3c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */
+ { 0x90088, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */
+ { 0x90089, 0x9 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */
+ { 0x9008a, 0x3c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */
+ { 0x9008b, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */
+ { 0x9008c, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */
+ { 0x9008d, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */
+ { 0x9008e, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */
+ { 0x9008f, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */
+ { 0x90090, 0x3c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */
+ { 0x90091, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */
+ { 0x90092, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */
+ { 0x90093, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */
+ { 0x90094, 0x48 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */
+ { 0x90095, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */
+ { 0x90096, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */
+ { 0x90097, 0x58 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */
+ { 0x90098, 0xa }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */
+ { 0x90099, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */
+ { 0x9009a, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */
+ { 0x9009b, 0x2 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */
+ { 0x9009c, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */
+ { 0x9009d, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */
+ { 0x9009e, 0x7 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */
+ { 0x9009f, 0x7c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */
+ { 0x900a0, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */
+ { 0x900a1, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */
+ { 0x900a2, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */
+ { 0x900a3, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */
+ { 0x900a4, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */
+ { 0x900a5, 0x8140 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */
+ { 0x900a6, 0x10c }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */
+ { 0x900a7, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */
+ { 0x900a8, 0x8138 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */
+ { 0x900a9, 0x10c }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */
+ { 0x900aa, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */
+ { 0x900ab, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */
+ { 0x900ac, 0x101 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */
+ { 0x900ad, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */
+ { 0x900ae, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */
+ { 0x900af, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */
+ { 0x900b0, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */
+ { 0x900b1, 0x448 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */
+ { 0x900b2, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */
+ { 0x900b3, 0xf }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */
+ { 0x900b4, 0x7c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */
+ { 0x900b5, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */
+ { 0x900b6, 0x47 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */
+ { 0x900b7, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */
+ { 0x900b8, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */
+ { 0x900b9, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */
+ { 0x900ba, 0x618 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */
+ { 0x900bb, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */
+ { 0x900bc, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */
+ { 0x900bd, 0xe0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */
+ { 0x900be, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */
+ { 0x900bf, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */
+ { 0x900c0, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */
+ { 0x900c1, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */
+ { 0x900c2, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */
+ { 0x900c3, 0x8140 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */
+ { 0x900c4, 0x10c }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */
+ { 0x900c5, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */
+ { 0x900c6, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */
+ { 0x900c7, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */
+ { 0x900c8, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */
+ { 0x900c9, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */
+ { 0x900ca, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */
+ { 0x900cb, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */
+ { 0x900cc, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */
+ { 0x900cd, 0x101 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */
+ { 0x90006, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */
+ { 0x90007, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */
+ { 0x90008, 0x8 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */
+ { 0x90009, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */
+ { 0x9000a, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */
+ { 0x9000b, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */
+ { 0xd00e7, 0x400 }, /* DWC_DDRPHYA_APBONLY0_SequencerOverride */
+ { 0x90017, 0x0 }, /* DWC_DDRPHYA_INITENG0_StartVector0b0 */
+ { 0x90026, 0x2c }, /* DWC_DDRPHYA_INITENG0_StartVector0b15 */
+ { 0x2000b, 0x32 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */
+ { 0x2000c, 0x64 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */
+ { 0x2000d, 0x3e8 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */
+ { 0x2000e, 0x2c }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */
+ { 0x12000b, 0x10 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p1 */
+ { 0x12000c, 0x21 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p1 */
+ { 0x12000d, 0x14c }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p1 */
+ { 0x12000e, 0x10 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p1 */
+ { 0x22000b, 0xa }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p2 */
+ { 0x22000c, 0x14 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p2 */
+ { 0x22000d, 0xcf }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p2 */
+ { 0x22000e, 0x10 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p2 */
+ { 0x9000c, 0x0 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */
+ { 0x9000d, 0x173 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */
+ { 0x9000e, 0x60 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */
+ { 0x9000f, 0x6110 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */
+ { 0x90010, 0x2152 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */
+ { 0x90011, 0xdfbd }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */
+ { 0x90012, 0xffff }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */
+ { 0x90013, 0x6152 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */
+ { 0xc0080, 0x0 }, /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */
+ { 0xd0000, 0x1 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+};
+
+struct dram_fsp_msg ddr3l_dram_fsp_msg[] = {
+ {
+ /* P0 2400mts 1D */
+ .drate = 1600,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr3l_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr3l_fsp0_cfg),
+ },
+#if 0
+ {
+ /* P1 1066mts 1D */
+ .drate = 1066,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr3l_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr3l_fsp1_cfg),
+ },
+ {
+ /* P2 667mts 1D */
+ .drate = 667,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr3l_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr3l_fsp2_cfg),
+ },
+#endif
+};
+
+/* ddr3l timing config params on VAL board */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr3l_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr3l_ddrc_cfg),
+ .ddrphy_cfg = ddr3l_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr3l_ddrphy_cfg),
+ .fsp_msg = ddr3l_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr3l_dram_fsp_msg),
+ .ddrphy_pie = ddr3l_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr3l_phy_pie),
+};
diff --git a/board/freescale/imx8mm_val/ddr4_timing.c b/board/freescale/imx8mm_val/ddr4_timing.c
new file mode 100644
index 0000000..cc35112
--- /dev/null
+++ b/board/freescale/imx8mm_val/ddr4_timing.c
@@ -0,0 +1,771 @@
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr4_ddrc_cfg[] = {
+ { DDRC_MSTR(0), 0x83040010 },
+ { DDRC_PWRCTL(0), 0x000000aa },
+ { DDRC_PWRTMG(0), 0x00221306 },
+ { DDRC_RFSHCTL0(0), 0x00c0a070 },
+ { DDRC_RFSHCTL1(0), 0x00010008 },
+ { DDRC_RFSHCTL3(0), 0x00000010 },
+ { DDRC_RFSHTMG(0), 0x004980f4 },
+ { DDRC_CRCPARCTL0(0), 0x00000000 },
+ { DDRC_CRCPARCTL1(0), 0x00001010 },
+ { DDRC_INIT0(0), 0xc0030002 },
+ { DDRC_INIT1(0), 0x00020009 },
+ { DDRC_INIT2(0), 0x0000350f },
+// { DDRC_INIT3(0), (mr_value[0][0]<<16) | (mr_value[0][1]) },
+ { DDRC_INIT3(0), (0xa34 << 16) | 0x105 },
+// { DDRC_INIT4(0), (mr_value[0][2]<<16) | (mr_value[0][3]) },
+ { DDRC_INIT4(0), (0x1028 << 16) | 0x240 },
+ { DDRC_INIT5(0), 0x001103cb },
+// { DDRC_INIT6(0), (mr_value[0][4]<<16) | (mr_value[0][5]) },
+ { DDRC_INIT6(0), (0x200 << 16) | 0x200 },
+// { DDRC_INIT7(0), mr_value[0][6] },
+ { DDRC_INIT7(0), 0x814 },
+ { DDRC_DIMMCTL(0), 0x00000032 },
+ { DDRC_RANKCTL(0), 0x00000fc7 },
+ { DDRC_DRAMTMG0(0), 0x14132813 },
+ { DDRC_DRAMTMG1(0), 0x0004051b },
+ { DDRC_DRAMTMG2(0), 0x0808030f },
+ { DDRC_DRAMTMG3(0), 0x0000400c },
+ { DDRC_DRAMTMG4(0), 0x08030409 },
+ { DDRC_DRAMTMG5(0), 0x0e090504 },
+ { DDRC_DRAMTMG6(0), 0x05030000 },
+ { DDRC_DRAMTMG7(0), 0x0000090e },
+ { DDRC_DRAMTMG8(0), 0x0606700c },
+ { DDRC_DRAMTMG9(0), 0x0002040c },
+ { DDRC_DRAMTMG10(0), 0x000f0c07 },
+ { DDRC_DRAMTMG11(0), 0x1809011d },
+ { DDRC_DRAMTMG12(0), 0x0000000d },
+ { DDRC_DRAMTMG13(0), 0x2b000000 },
+ { DDRC_DRAMTMG14(0), 0x000000a4 },
+ { DDRC_DRAMTMG15(0), 0x00000000 },
+ { DDRC_DRAMTMG17(0), 0x00250078 },
+ { DDRC_ZQCTL0(0), 0x51000040 },
+ { DDRC_ZQCTL1(0), 0x00000070 },
+ { DDRC_ZQCTL2(0), 0x00000000 },
+ { DDRC_DFITMG0(0), 0x038b820b },
+ { DDRC_DFITMG1(0), 0x02020103 },
+ { DDRC_DFILPCFG0(0), 0x07f04011 }, /* [8]dfi_lp_en_sr = 0 */
+ { DDRC_DFILPCFG1(0), 0x000000b0 },
+ { DDRC_DFIUPD0(0), 0xe0400018 },
+ { DDRC_DFIUPD1(0), 0x0048005a },
+ { DDRC_DFIUPD2(0), 0x80000000 },
+ { DDRC_DFIMISC(0), 0x00000001 },
+ { DDRC_DFITMG2(0), 0x00000b0b },
+ { DDRC_DFITMG3(0), 0x00000001 },
+ { DDRC_DBICTL(0), 0x00000000 },
+ { DDRC_DFIPHYMSTR(0), 0x00000000 },
+
+ { DDRC_ADDRMAP0(0), 0x00000017 }, /* [4:0]cs0: 6+23 */
+ { DDRC_ADDRMAP1(0), 0x003F0909 }, /* [5:0] bank b0: 2+9; [13:8] b1: P3+9 ; [21:16] b2: 4+, unused */
+ { DDRC_ADDRMAP2(0), 0x01010100 }, /* [3:0] col-b2: 2; [11:8] col-b3: 3+1; [19:16] col-b4: 4+1 ; [27:24] col-b5: 5+1 */
+ { DDRC_ADDRMAP3(0), 0x01010101 }, /* [3:0] col-b6: 6+1; [11:8] col-b7: 7+1; [19:16] col-b8: 8+1 ; [27:24] col-b9: 9+1 */
+ { DDRC_ADDRMAP4(0), 0x00001f1f }, /* col-b10, col-b11 not used */
+ { DDRC_ADDRMAP5(0), 0x07070707 }, /* [3:0] row-b0: 6+7; [11:8] row-b1: 7+7; [19:16] row-b2_b10: 8~16+7; [27:24] row-b11: 17+7 */
+ { DDRC_ADDRMAP6(0), 0x07070707 }, /* [3:0] row-b12:18+7; [11:8] row-b13: 19+7; [19:16] row-b14:20+7; [27:24] row-b15: 21+7 */
+ { DDRC_ADDRMAP7(0), 0x00000f0f }, /* col-b10, col-b11 not used */
+ { DDRC_ADDRMAP8(0), 0x00003F01 }, /* [5:0] bg-b0: 2+1; [13:8]bg-b1:3+, unused */
+ { DDRC_ADDRMAP9(0), 0x0a020b06 }, /* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
+ { DDRC_ADDRMAP10(0), 0x0a0a0a0a },/* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
+ { DDRC_ADDRMAP11(0), 0x00000000 },
+
+ /* FREQ0: BL8, CL=16, CWL=16, WR_PREAMBLE = 1,RD_PREAMBLE = 1, CRC_MODE = 1, so wr_odt_hold=5+1+1=7 */
+ /* wr_odt_delay=DFITMG1.dfi_t_cmd_lat=0 */
+ { DDRC_ODTCFG(0), 0x07000600 },
+ { DDRC_ODTMAP(0), 0x0201 },/* disable ODT0x00001120 , */
+ { DDRC_SCHED(0), 0x317d1a07 },
+ { DDRC_SCHED1(0), 0x0000000f },
+ { DDRC_PERFHPR1(0), 0x2a001b76 },
+ { DDRC_PERFLPR1(0), 0x7300b473 },
+ { DDRC_PERFWR1(0), 0x30000e06 },
+ { DDRC_DBG0(0), 0x00000014 },
+ { DDRC_DBG1(0), 0x00000000 },
+ { DDRC_DBGCMD(0), 0x00000000 },
+ { DDRC_SWCTL(0), 0x00000001 },
+ { DDRC_POISONCFG(0), 0x00000010 },
+ { DDRC_PCCFG(0), 0x00000100 },/* bl_exp_mode=1 */
+ { DDRC_PCFGR_0(0), 0x00013193 },
+ { DDRC_PCFGW_0(0), 0x00006096 },
+ { DDRC_PCTRL_0(0), 0x00000001 },
+ { DDRC_PCFGQOS0_0(0), 0x02000c00 },
+ { DDRC_PCFGQOS1_0(0), 0x003c00db },
+ { DDRC_PCFGWQOS0_0(0), 0x00100009 },
+ { DDRC_PCFGWQOS1_0(0), 0x00000002 },
+
+ { DDRC_FREQ1_RFSHCTL0(0), 0x0021a0c0 },
+ { DDRC_FREQ1_RFSHTMG(0), 0x0018001a },/* tREFI=7.8us */
+// { DDRC_FREQ1_INIT3(0), (mr_value[1][0]<<16) | (mr_value[1][1]) },
+// { DDRC_FREQ1_INIT4(0), (mr_value[1][2]<<16) | (mr_value[1][3]) },
+// { DDRC_FREQ1_INIT6(0), (mr_value[1][4]<<16) | (mr_value[1][5]) },
+// { DDRC_FREQ1_INIT7(0), mr_value[1][6] },
+ { DDRC_FREQ1_INIT3(0), (0x204 << 16) | 0x104 },
+ { DDRC_FREQ1_INIT4(0), (0x1000 << 16) | 0x040 },
+ { DDRC_FREQ1_INIT6(0), (0x200 << 16) | 0x200 },
+ { DDRC_FREQ1_INIT7(0), 0x014 },
+ { DDRC_FREQ1_DRAMTMG0(0), 0x0c0e0604 },/* t_ras_max=9*7.8us, t_ras_min=35ns */
+ { DDRC_FREQ1_DRAMTMG1(0), 0x00030314 },
+ { DDRC_FREQ1_DRAMTMG2(0), 0x0505040a },
+ { DDRC_FREQ1_DRAMTMG3(0), 0x0000400c },
+ { DDRC_FREQ1_DRAMTMG4(0), 0x06040307 }, /* tRP=6 --> 7 */
+ { DDRC_FREQ1_DRAMTMG5(0), 0x090d0202 },
+ { DDRC_FREQ1_DRAMTMG6(0), 0x0a070008 },
+ { DDRC_FREQ1_DRAMTMG7(0), 0x00000d09 },
+ { DDRC_FREQ1_DRAMTMG8(0), 0x08084b09 },
+ { DDRC_FREQ1_DRAMTMG9(0), 0x00020308 },
+ { DDRC_FREQ1_DRAMTMG10(0), 0x000f0d06 },
+ { DDRC_FREQ1_DRAMTMG11(0), 0x12060111 },
+ { DDRC_FREQ1_DRAMTMG12(0), 0x00000008 },
+ { DDRC_FREQ1_DRAMTMG13(0), 0x21000000 },
+ { DDRC_FREQ1_DRAMTMG14(0), 0x00000000 },
+ { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
+ { DDRC_FREQ1_DRAMTMG17(0), 0x00c6007d },
+ { DDRC_FREQ1_ZQCTL0(0), 0x51000040 },
+ { DDRC_FREQ1_DFITMG0(0), 0x03858204 },
+ { DDRC_FREQ1_DFITMG1(0), 0x00020103 },
+ { DDRC_FREQ1_DFITMG2(0), 0x00000504 },
+ { DDRC_FREQ1_DFITMG3(0), 0x00000001 },
+ /* FREQ1: BL8, CL=10, CWL=9, WR_PREAMBLE = 1,RD_PREAMBLE = 1, CRC_MODE = 1 */
+ /* wr_odt_delay=DFITMG1.dfi_t_cmd_lat=0 */
+ { DDRC_FREQ1_ODTCFG(0), 0x07000601 },
+
+ { DDRC_FREQ2_RFSHCTL0(0), 0x0021a0c0 },
+ { DDRC_FREQ2_RFSHTMG(0), 0x0006000e },/* tREFI=7.8us */
+// { DDRC_FREQ2_INIT3(0), (mr_value[2][0]<<16) | (mr_value[2][1]) },
+// { DDRC_FREQ2_INIT4(0), (mr_value[2][2]<<16) | (mr_value[2][3]) },
+// { DDRC_FREQ2_INIT6(0), (mr_value[2][4]<<16) | (mr_value[2][5]) },
+// { DDRC_FREQ2_INIT7(0), mr_value[2][6] },
+ { DDRC_FREQ2_INIT3(0), (0x204 << 16) | 0x104 },
+ { DDRC_FREQ2_INIT4(0), (0x1000 << 16) | 0x40 },
+ { DDRC_FREQ2_INIT6(0), (0x200 << 16) | 0x200 },
+ { DDRC_FREQ2_INIT7(0), 0x14 },
+ { DDRC_FREQ2_DRAMTMG0(0), 0x0c0e0101 },/* t_ras_max=9*7.8us, t_ras_min=35ns */
+ { DDRC_FREQ2_DRAMTMG1(0), 0x00030314 },
+ { DDRC_FREQ2_DRAMTMG2(0), 0x0505040a },
+ { DDRC_FREQ2_DRAMTMG3(0), 0x0000400c },
+ { DDRC_FREQ2_DRAMTMG4(0), 0x06040307 }, /* tRP=6 --> 7 */
+ { DDRC_FREQ2_DRAMTMG5(0), 0x090d0202 },
+ { DDRC_FREQ2_DRAMTMG6(0), 0x0a070008 },
+ { DDRC_FREQ2_DRAMTMG7(0), 0x00000d09 },
+ { DDRC_FREQ2_DRAMTMG8(0), 0x08084b09 },
+ { DDRC_FREQ2_DRAMTMG9(0), 0x00020308 },
+ { DDRC_FREQ2_DRAMTMG10(0), 0x000f0d06 },
+ { DDRC_FREQ2_DRAMTMG11(0), 0x12060111 },
+ { DDRC_FREQ2_DRAMTMG12(0), 0x00000008 },
+ { DDRC_FREQ2_DRAMTMG13(0), 0x21000000 },
+ { DDRC_FREQ2_DRAMTMG14(0), 0x00000000 },
+ { DDRC_FREQ2_DRAMTMG15(0), 0x00000000 },
+ { DDRC_FREQ2_DRAMTMG17(0), 0x00c6007d },
+ { DDRC_FREQ2_ZQCTL0(0), 0x51000040 },
+ { DDRC_FREQ2_DFITMG0(0), 0x03858204 },
+ { DDRC_FREQ2_DFITMG1(0), 0x00020103 },
+ { DDRC_FREQ2_DFITMG2(0), 0x00000504 },
+ { DDRC_FREQ2_DFITMG3(0), 0x00000001 },
+ /* FREQ1: BL8, CL=10, CWL=9, WR_PREAMBLE = 1,RD_PREAMBLE = 1, CRC_MODE = 1 */
+ /* wr_odt_delay=DFITMG1.dfi_t_cmd_lat=0 */
+ { DDRC_FREQ2_ODTCFG(0), 0x07000601 },
+
+ /* default start freq point */
+ { DDRC_MSTR2(0), 0x0},
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr4_ddrphy_cfg[] = {
+ { 0x1005f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p0 */
+ { 0x1015f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p0 */
+ { 0x1105f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p0 */
+ { 0x1115f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p0 */
+ { 0x1205f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p0 */
+ { 0x1215f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p0 */
+ { 0x1305f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p0 */
+ { 0x1315f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p0 */
+
+ { 0x11005f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p1 */
+ { 0x11015f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p1 */
+ { 0x11105f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p1 */
+ { 0x11115f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p1 */
+ { 0x11205f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p1 */
+ { 0x11215f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p1 */
+ { 0x11305f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p1 */
+ { 0x11315f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p1 */
+
+ { 0x21005f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p2 */
+ { 0x21015f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p2 */
+ { 0x21105f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p2 */
+ { 0x21115f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p2 */
+ { 0x21205f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p2 */
+ { 0x21215f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p2 */
+ { 0x21305f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p2 */
+ { 0x21315f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p2 */
+
+ { 0x55, 0x355 }, /* DWC_DDRPHYA_ANIB0_ATxSlewRate */
+ { 0x1055, 0x355 }, /* DWC_DDRPHYA_ANIB1_ATxSlewRate */
+ { 0x2055, 0x355 }, /* DWC_DDRPHYA_ANIB2_ATxSlewRate */
+ { 0x3055, 0x355 }, /* DWC_DDRPHYA_ANIB3_ATxSlewRate */
+ { 0x4055, 0x55 }, /* DWC_DDRPHYA_ANIB4_ATxSlewRate */
+ { 0x5055, 0x55 }, /* DWC_DDRPHYA_ANIB5_ATxSlewRate */
+ { 0x6055, 0x355 }, /* DWC_DDRPHYA_ANIB6_ATxSlewRate */
+ { 0x7055, 0x355 }, /* DWC_DDRPHYA_ANIB7_ATxSlewRate */
+ { 0x8055, 0x355 }, /* DWC_DDRPHYA_ANIB8_ATxSlewRate */
+ { 0x9055, 0x355 }, /* DWC_DDRPHYA_ANIB9_ATxSlewRate */
+ { 0x200c5, 0xa }, /* DWC_DDRPHYA_MASTER0_PllCtrl2_p0 */
+ { 0x1200c5, 0x7 }, /* DWC_DDRPHYA_MASTER0_PllCtrl2_p1 */
+ { 0x2200c5, 0x7 }, /* DWC_DDRPHYA_MASTER0_PllCtrl2_p2 */
+ { 0x2002e, 0x2 }, /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0 */
+ { 0x12002e, 0x2 }, /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p1 */
+ { 0x22002e, 0x2 }, /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p2 */
+ { 0x20024, 0x8 }, /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p0 */
+ { 0x2003a, 0x2 }, /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */
+ { 0x120024, 0x8 }, /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p1 */
+ { 0x2003a, 0x2 }, /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */
+ { 0x220024, 0x8 }, /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p2 */
+ { 0x2003a, 0x2 }, /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */
+ { 0x20056, 0x6 }, /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p0 */
+ { 0x120056, 0xa }, /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p1 */
+ { 0x220056, 0xa }, /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p2 */
+ { 0x1004d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p0 */
+ { 0x1014d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p0 */
+ { 0x1104d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p0 */
+ { 0x1114d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p0 */
+ { 0x1204d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p0 */
+ { 0x1214d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p0 */
+ { 0x1304d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p0 */
+ { 0x1314d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p0 */
+ { 0x11004d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p1 */
+ { 0x11014d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p1 */
+ { 0x11104d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p1 */
+ { 0x11114d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p1 */
+ { 0x11204d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p1 */
+ { 0x11214d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p1 */
+ { 0x11304d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p1 */
+ { 0x11314d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p1 */
+ { 0x21004d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p2 */
+ { 0x21014d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p2 */
+ { 0x21104d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p2 */
+ { 0x21114d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p2 */
+ { 0x21204d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p2 */
+ { 0x21214d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p2 */
+ { 0x21304d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p2 */
+ { 0x21314d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p2 */
+ { 0x10049, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p0 */
+ { 0x10149, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p0 */
+ { 0x11049, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p0 */
+ { 0x11149, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p0 */
+ { 0x12049, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p0 */
+ { 0x12149, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p0 */
+ { 0x13049, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p0 */
+ { 0x13149, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p0 */
+ { 0x110049, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p1 */
+ { 0x110149, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p1 */
+ { 0x111049, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p1 */
+ { 0x111149, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p1 */
+ { 0x112049, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p1 */
+ { 0x112149, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p1 */
+ { 0x113049, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p1 */
+ { 0x113149, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p1 */
+ { 0x210049, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p2 */
+ { 0x210149, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p2 */
+ { 0x211049, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p2 */
+ { 0x211149, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p2 */
+ { 0x212049, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p2 */
+ { 0x212149, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p2 */
+ { 0x213049, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p2 */
+ { 0x213149, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p2 */
+ { 0x43, 0x63 }, /* DWC_DDRPHYA_ANIB0_ATxImpedance */
+ { 0x1043, 0x63 }, /* DWC_DDRPHYA_ANIB1_ATxImpedance */
+ { 0x2043, 0x63 }, /* DWC_DDRPHYA_ANIB2_ATxImpedance */
+ { 0x3043, 0x63 }, /* DWC_DDRPHYA_ANIB3_ATxImpedance */
+ { 0x4043, 0x63 }, /* DWC_DDRPHYA_ANIB4_ATxImpedance */
+ { 0x5043, 0x63 }, /* DWC_DDRPHYA_ANIB5_ATxImpedance */
+ { 0x6043, 0x63 }, /* DWC_DDRPHYA_ANIB6_ATxImpedance */
+ { 0x7043, 0x63 }, /* DWC_DDRPHYA_ANIB7_ATxImpedance */
+ { 0x8043, 0x63 }, /* DWC_DDRPHYA_ANIB8_ATxImpedance */
+ { 0x9043, 0x63 }, /* DWC_DDRPHYA_ANIB9_ATxImpedance */
+ { 0x20018, 0x5 }, /* DWC_DDRPHYA_MASTER0_DfiMode */
+ { 0x20075, 0x2 }, /* DWC_DDRPHYA_MASTER0_DfiCAMode */
+ { 0x20050, 0x0 }, /* DWC_DDRPHYA_MASTER0_CalDrvStr0 */
+ { 0x20008, 0x258 }, /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p0 */
+ { 0x120008, 0x64 }, /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p1 */
+ { 0x220008, 0x19 }, /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p2 */
+ { 0x20088, 0x9 }, /* DWC_DDRPHYA_MASTER0_CalRate */
+ { 0x200b2, 0x268 }, /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p0 */
+ { 0x10043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p0 */
+ { 0x10143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p0 */
+ { 0x11043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p0 */
+ { 0x11143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p0 */
+ { 0x12043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p0 */
+ { 0x12143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p0 */
+ { 0x13043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p0 */
+ { 0x13143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p0 */
+ { 0x1200b2, 0x268 }, /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p1 */
+ { 0x110043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p1 */
+ { 0x110143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p1 */
+ { 0x111043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p1 */
+ { 0x111143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p1 */
+ { 0x112043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p1 */
+ { 0x112143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p1 */
+ { 0x113043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p1 */
+ { 0x113143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p1 */
+ { 0x2200b2, 0x268 }, /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p2 */
+ { 0x210043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p2 */
+ { 0x210143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p2 */
+ { 0x211043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p2 */
+ { 0x211143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p2 */
+ { 0x212043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p2 */
+ { 0x212143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p2 */
+ { 0x213043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p2 */
+ { 0x213143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p2 */
+ { 0x2005b, 0x7529 }, /* DWC_DDRPHYA_MASTER0_MemAlertControl */
+ { 0x2005c, 0x0 }, /* DWC_DDRPHYA_MASTER0_MemAlertControl2 */
+ { 0x200fa, 0x1 }, /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p0 */
+ { 0x1200fa, 0x1 }, /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p1 */
+ { 0x2200fa, 0x1 }, /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p2 */
+ { 0x20019, 0x5 }, /* DWC_DDRPHYA_MASTER0_TristateModeCA_p0 */
+ { 0x120019, 0x5 }, /* DWC_DDRPHYA_MASTER0_TristateModeCA_p1 */
+ { 0x220019, 0x5 }, /* DWC_DDRPHYA_MASTER0_TristateModeCA_p2 */
+ { 0x200f0, 0x5665 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat0 */
+ { 0x200f1, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat1 */
+ { 0x200f2, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat2 */
+ { 0x200f3, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat3 */
+ { 0x200f4, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat4 */
+ { 0x200f5, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat5 */
+ { 0x200f6, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat6 */
+ { 0x200f7, 0xf000 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat7 */
+ { 0x20025, 0x0 }, /* DWC_DDRPHYA_MASTER0_MasterX4Config */
+ { 0x2002d, 0x0 }, /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p0 */
+ { 0x12002d, 0x0 }, /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p1 */
+ { 0x22002d, 0x0 }, /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p2 */
+ { 0x200c7, 0x21 }, /* DWC_DDRPHYA_MASTER0_PllCtrl1_p0 */
+ { 0x200ca, 0x24 }, /* DWC_DDRPHYA_MASTER0_PllTestMode_p0 */
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr4_fsp0_cfg[] = {
+ { 0x20060, 0x2 },
+ { 0xd0000, 0x0 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x0 },
+ { 0x54003, 0x960 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x0 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x2000 },
+ { 0x54008, 0x303 },
+ { 0x54009, 0x200 },/* no addr mirror, 0x200 addr mirror */
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x31f },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0xa34 },
+ { 0x54030, 0x105 },
+ { 0x54031, 0x1028 },
+ { 0x54032, 0x240 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x200 },
+ { 0x54035, 0x814 },
+ { 0x54036, 0x103 },
+ { 0x54037, 0x0 },
+ { 0x54038, 0x0 },
+ { 0x54039, 0x0 },
+ { 0x5403a, 0x0 },
+ { 0x5403b, 0x0 },
+ { 0x5403c, 0x0 },
+ { 0x5403d, 0x0 },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x1221 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr4_fsp1_cfg[] = {
+ { 0xd0000, 0x0 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x0 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x2000 },
+ { 0x54008, 0x303 },
+ { 0x54009, 0x200 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x21f },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x204 },
+ { 0x54030, 0x104 },
+ { 0x54031, 0x1000 },
+ { 0x54032, 0x40 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x200 },
+ { 0x54035, 0x14 },
+ { 0x54036, 0x103 },
+ { 0x54037, 0x0 },
+ { 0x54038, 0x0 },
+ { 0x54039, 0x0 },
+ { 0x5403a, 0x0 },
+ { 0x5403b, 0x0 },
+ { 0x5403c, 0x0 },
+ { 0x5403d, 0x0 },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x1221 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr4_fsp2_cfg[] = {
+ { 0xd0000, 0x0 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x0 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x2000 },
+ { 0x54008, 0x303 },
+ { 0x54009, 0x200 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x21f },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x204 },
+ { 0x54030, 0x104 },
+ { 0x54031, 0x1000 },
+ { 0x54032, 0x40 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x200 },
+ { 0x54035, 0x14 },
+ { 0x54036, 0x103 },
+ { 0x54037, 0x0 },
+ { 0x54038, 0x0 },
+ { 0x54039, 0x0 },
+ { 0x5403a, 0x0 },
+ { 0x5403b, 0x0 },
+ { 0x5403c, 0x0 },
+ { 0x5403d, 0x0 },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x1221 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+};
+
+struct dram_cfg_param ddr4_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x0 },
+ { 0x54003, 0x960 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x0 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x2000 },
+ { 0x54008, 0x303 },
+ { 0x54009, 0x200 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x61 },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x100 },
+ { 0x5400e, 0x1f7f },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0xa34 },
+ { 0x54030, 0x105 },
+ { 0x54031, 0x1028 },
+ { 0x54032, 0x240 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x200 },
+ { 0x54035, 0x814 },
+ { 0x54036, 0x103 },
+ { 0x54037, 0x0 },
+ { 0x54038, 0x0 },
+ { 0x54039, 0x0 },
+ { 0x5403a, 0x0 },
+ { 0x5403b, 0x0 },
+ { 0x5403c, 0x0 },
+ { 0x5403d, 0x0 },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x1221 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+};
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr4_phy_pie[] = {
+ { 0xd0000, 0x0 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+ { 0x90000, 0x10 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */
+ { 0x90001, 0x400 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */
+ { 0x90002, 0x10e }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */
+ { 0x90003, 0x0 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */
+ { 0x90004, 0x0 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */
+ { 0x90005, 0x8 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */
+ { 0x90029, 0xb }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */
+ { 0x9002a, 0x480 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */
+ { 0x9002b, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */
+ { 0x9002c, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */
+ { 0x9002d, 0x448 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */
+ { 0x9002e, 0x139 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */
+ { 0x9002f, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */
+ { 0x90030, 0x478 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */
+ { 0x90031, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */
+ { 0x90032, 0x2 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */
+ { 0x90033, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */
+ { 0x90034, 0x139 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */
+ { 0x90035, 0xf }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */
+ { 0x90036, 0x7c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */
+ { 0x90037, 0x139 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */
+ { 0x90038, 0x44 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */
+ { 0x90039, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */
+ { 0x9003a, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */
+ { 0x9003b, 0x14f }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */
+ { 0x9003c, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */
+ { 0x9003d, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */
+ { 0x9003e, 0x47 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */
+ { 0x9003f, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */
+ { 0x90040, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */
+ { 0x90041, 0x4f }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */
+ { 0x90042, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */
+ { 0x90043, 0x179 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */
+ { 0x90044, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */
+ { 0x90045, 0xe0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */
+ { 0x90046, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */
+ { 0x90047, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */
+ { 0x90048, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */
+ { 0x90049, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */
+ { 0x9004a, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */
+ { 0x9004b, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */
+ { 0x9004c, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */
+ { 0x9004d, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */
+ { 0x9004e, 0x45a }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */
+ { 0x9004f, 0x9 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */
+ { 0x90050, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */
+ { 0x90051, 0x448 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */
+ { 0x90052, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */
+ { 0x90053, 0x40 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */
+ { 0x90054, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */
+ { 0x90055, 0x179 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */
+ { 0x90056, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */
+ { 0x90057, 0x618 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */
+ { 0x90058, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */
+ { 0x90059, 0x40c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */
+ { 0x9005a, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */
+ { 0x9005b, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */
+ { 0x9005c, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */
+ { 0x9005d, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */
+ { 0x9005e, 0x48 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */
+ { 0x9005f, 0x4040 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */
+ { 0x90060, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */
+ { 0x90061, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */
+ { 0x90062, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */
+ { 0x90063, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */
+ { 0x90064, 0x48 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */
+ { 0x90065, 0x40 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */
+ { 0x90066, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */
+ { 0x90067, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */
+ { 0x90068, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */
+ { 0x90069, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */
+ { 0x9006a, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */
+ { 0x9006b, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */
+ { 0x9006c, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */
+ { 0x9006d, 0x78 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */
+ { 0x9006e, 0x549 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */
+ { 0x9006f, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */
+ { 0x90070, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */
+ { 0x90071, 0xd49 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */
+ { 0x90072, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */
+ { 0x90073, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */
+ { 0x90074, 0x94a }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */
+ { 0x90075, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */
+ { 0x90076, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */
+ { 0x90077, 0x441 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */
+ { 0x90078, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */
+ { 0x90079, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */
+ { 0x9007a, 0x42 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */
+ { 0x9007b, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */
+ { 0x9007c, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */
+ { 0x9007d, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */
+ { 0x9007e, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */
+ { 0x9007f, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */
+ { 0x90080, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */
+ { 0x90081, 0xe0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */
+ { 0x90082, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */
+ { 0x90083, 0xa }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */
+ { 0x90084, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */
+ { 0x90085, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */
+ { 0x90086, 0x9 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */
+ { 0x90087, 0x3c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */
+ { 0x90088, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */
+ { 0x90089, 0x9 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */
+ { 0x9008a, 0x3c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */
+ { 0x9008b, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */
+ { 0x9008c, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */
+ { 0x9008d, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */
+ { 0x9008e, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */
+ { 0x9008f, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */
+ { 0x90090, 0x3c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */
+ { 0x90091, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */
+ { 0x90092, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */
+ { 0x90093, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */
+ { 0x90094, 0x48 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */
+ { 0x90095, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */
+ { 0x90096, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */
+ { 0x90097, 0x58 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */
+ { 0x90098, 0xa }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */
+ { 0x90099, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */
+ { 0x9009a, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */
+ { 0x9009b, 0x2 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */
+ { 0x9009c, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */
+ { 0x9009d, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */
+ { 0x9009e, 0x7 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */
+ { 0x9009f, 0x7c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */
+ { 0x900a0, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */
+ { 0x900a1, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */
+ { 0x900a2, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */
+ { 0x900a3, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */
+ { 0x900a4, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */
+ { 0x900a5, 0x8140 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */
+ { 0x900a6, 0x10c }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */
+ { 0x900a7, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */
+ { 0x900a8, 0x8138 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */
+ { 0x900a9, 0x10c }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */
+ { 0x900aa, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */
+ { 0x900ab, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */
+ { 0x900ac, 0x101 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */
+ { 0x900ad, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */
+ { 0x900ae, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */
+ { 0x900af, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */
+ { 0x900b0, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */
+ { 0x900b1, 0x448 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */
+ { 0x900b2, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */
+ { 0x900b3, 0xf }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */
+ { 0x900b4, 0x7c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */
+ { 0x900b5, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */
+ { 0x900b6, 0x47 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */
+ { 0x900b7, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */
+ { 0x900b8, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */
+ { 0x900b9, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */
+ { 0x900ba, 0x618 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */
+ { 0x900bb, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */
+ { 0x900bc, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */
+ { 0x900bd, 0xe0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */
+ { 0x900be, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */
+ { 0x900bf, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */
+ { 0x900c0, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */
+ { 0x900c1, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */
+ { 0x900c2, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */
+ { 0x900c3, 0x8140 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */
+ { 0x900c4, 0x10c }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */
+ { 0x900c5, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */
+ { 0x900c6, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */
+ { 0x900c7, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */
+ { 0x900c8, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */
+ { 0x900c9, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */
+ { 0x900ca, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */
+ { 0x900cb, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */
+ { 0x900cc, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */
+ { 0x900cd, 0x101 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */
+ { 0x90006, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */
+ { 0x90007, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */
+ { 0x90008, 0x8 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */
+ { 0x90009, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */
+ { 0x9000a, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */
+ { 0x9000b, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */
+ { 0xd00e7, 0x400 }, /* DWC_DDRPHYA_APBONLY0_SequencerOverride */
+ { 0x90017, 0x0 }, /* DWC_DDRPHYA_INITENG0_StartVector0b0 */
+ { 0x90026, 0x2c }, /* DWC_DDRPHYA_INITENG0_StartVector0b15 */
+ { 0x2000b, 0x4b }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */
+ { 0x2000c, 0x96 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */
+ { 0x2000d, 0x5dc }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */
+ { 0x2000e, 0x2c }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */
+ { 0x12000b, 0xc }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p1 */
+ { 0x12000c, 0x19 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p1 */
+ { 0x12000d, 0xfa }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p1 */
+ { 0x12000e, 0x10 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p1 */
+ { 0x22000b, 0x3 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p2 */
+ { 0x22000c, 0x6 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p2 */
+ { 0x22000d, 0x3e }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p2 */
+ { 0x22000e, 0x10 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p2 */
+ { 0x9000c, 0x0 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */
+ { 0x9000d, 0x173 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */
+ { 0x9000e, 0x60 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */
+ { 0x9000f, 0x6110 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */
+ { 0x90010, 0x2152 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */
+ { 0x90011, 0xdfbd }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */
+ { 0x90012, 0xffff }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */
+ { 0x90013, 0x6152 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */
+ { 0xc0080, 0x0 }, /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */
+ { 0xd0000, 0x1 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+};
+
+struct dram_fsp_msg ddr4_dram_fsp_msg[] = {
+ {
+ /* P0 2400mts 1D */
+ .drate = 2400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr4_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr4_fsp0_cfg),
+ },
+#if 1
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr4_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr4_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr4_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr4_fsp2_cfg),
+ },
+ {
+ /* P0 2400mts 2D */
+ .drate = 2400,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr4_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr4_fsp0_2d_cfg),
+ },
+#endif
+};
+
+/* ddr4 timing config params on VAL board */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr4_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr4_ddrc_cfg),
+ .ddrphy_cfg = ddr4_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr4_ddrphy_cfg),
+ .fsp_msg = ddr4_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr4_dram_fsp_msg),
+ .ddrphy_pie = ddr4_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr4_phy_pie),
+};
diff --git a/board/freescale/imx8mm_val/spl.c b/board/freescale/imx8mm_val/spl.c
index a9b044f..7e92895 100644
--- a/board/freescale/imx8mm_val/spl.c
+++ b/board/freescale/imx8mm_val/spl.c
@@ -26,7 +26,7 @@
void spl_dram_init(void)
{
/* ddr train */
- ddr_init(NULL);
+ ddr_init(&dram_timing);
}
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
