include/configs/imx8qxp_arm2.h - uboot-imx - Git at Google

 /*
  * Copyright 2017 NXP
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

 #ifndef __IMX8QXP_ARM2_H
 #define __IMX8QXP_ARM2_H

 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>

 #define CONFIG_REMAKE_ELF

 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_ARCH_MISC_INIT

 /* Flat Device Tree Definitions */
 #define CONFIG_OF_BOARD_SETUP

 #undef CONFIG_CMD_EXPORTENV
 #undef CONFIG_CMD_IMPORTENV
 #undef CONFIG_CMD_IMLS

 #undef CONFIG_CMD_CRC32
 #undef CONFIG_BOOTM_NETBSD

 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
 #define USDHC1_BASE_ADDR                0x5B010000
 #define USDHC2_BASE_ADDR                0x5B020000
 #define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */

 #define CONFIG_ENV_OVERWRITE


 #define CONFIG_FSL_HSIO
 #ifdef CONFIG_FSL_HSIO
 #define CONFIG_PCIE_IMX8X
 #define CONFIG_CMD_PCI
 #define CONFIG_PCI
 #define CONFIG_PCI_PNP
 #define CONFIG_PCI_SCAN_SHOW
 #define CONFIG_CMD_PCI_ENUM
 #endif

 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

 /* FUSE command */
 #define CONFIG_CMD_FUSE

 /* GPIO configs */
 #define CONFIG_MXC_GPIO

 /* ENET Config */
 #define CONFIG_MII

 #define CONFIG_FEC_MXC
 #define CONFIG_FEC_XCV_TYPE             RGMII
 #define FEC_QUIRK_ENET_MAC

 #define CONFIG_PHY_GIGE /* Support for 1000BASE-X */
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS

 /* ENET0 connects AR8031 on CPU board, ENET1 connects to base board and MUX with ESAI, default is ESAI */
 #define CONFIG_FEC_ENET_DEV 0

 #if (CONFIG_FEC_ENET_DEV == 0)
 #define IMX_FEC_BASE			0x5B040000
 #define CONFIG_FEC_MXC_PHYADDR          0x0
 #define CONFIG_ETHPRIME                 "eth0"
 #elif (CONFIG_FEC_ENET_DEV == 1)
 #define IMX_FEC_BASE			0x5B050000
 #define CONFIG_FEC_MXC_PHYADDR          0x1
 #define CONFIG_FEC_ENABLE_MAX7322
 #define CONFIG_ETHPRIME                 "eth1"
 #endif

 /* ENET0 MDIO are shared */
 #define CONFIG_FEC_MXC_MDIO_BASE	0x5B040000

 /* MAX7322 */
 #ifdef CONFIG_FEC_ENABLE_MAX7322
 #define CONFIG_MAX7322_I2C_ADDR		0x68
 #define CONFIG_MAX7322_I2C_BUS		0 /* I2C1 */
 #endif

 /* Boot M4 */
 #define M4_BOOT_ENV \
 	"m4_0_image=m4_0.bin\0" \
 	"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
 	"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \

 #ifdef CONFIG_NAND_BOOT
 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
 #else
 #define MFG_NAND_PARTITION ""
 #endif

 #define CONFIG_MFG_ENV_SETTINGS \
 	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
 		"rdinit=/linuxrc " \
 		"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
 		"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
 		"g_mass_storage.iSerialNumber=\"\" "\
 		MFG_NAND_PARTITION \
 		"video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off "\
 		"clk_ignore_unused "\
 		"\0" \
 	"initrd_addr=0x83800000\0" \
 	"initrd_high=0xffffffff\0" \
 	"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \

 /* Initial environment variables */
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	CONFIG_MFG_ENV_SETTINGS \
 	"bootargs=console=ttyLP0,115200 ubi.mtd=5 "  \
 		"root=ubi0:rootfs rootfstype=ubifs "		     \
 		"mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs)\0"\
 	"console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200\0" \
 	"fdt_addr=0x83000000\0"
 #else
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	CONFIG_MFG_ENV_SETTINGS \
 	M4_BOOT_ENV \
 	"script=boot.scr\0" \
 	"image=Image\0" \
 	"panel=NULL\0" \
 	"console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200\0" \
 	"fdt_addr=0x83000000\0"			\
 	"fdt_high=0xffffffffffffffff\0"		\
 	"boot_fdt=try\0" \
 	"fdt_file=fsl-imx8qxp-lpddr4-arm2.dtb\0" \
 	"initrd_addr=0x83800000\0"		\
 	"initrd_high=0xffffffffffffffff\0" \
 	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
 	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
 	"mmcautodetect=yes\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} " \
 	"video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" \
 	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if run loadfdt; then " \
 				"booti ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"echo WARN: Cannot load the DT; " \
 			"fi; " \
 		"else " \
 			"echo wait for boot; " \
 		"fi;\0" \
 	"netargs=setenv bootargs console=${console} " \
 		"root=/dev/nfs " \
 		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
 		"video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" \
 	"netboot=echo Booting from net ...; " \
 		"run netargs;  " \
 		"if test ${ip_dyn} = yes; then " \
 			"setenv get_cmd dhcp; " \
 		"else " \
 			"setenv get_cmd tftp; " \
 		"fi; " \
 		"${get_cmd} ${loadaddr} ${image}; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
 				"booti ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"echo WARN: Cannot load the DT; " \
 			"fi; " \
 		"else " \
 			"booti; " \
 		"fi;\0"
 #endif

 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_BOOTCOMMAND \
 	"nand read ${loadaddr} 0x8000000 0x1400000;"\
 	"nand read ${fdt_addr} 0xA000000 0x100000;"\
 	"booti ${loadaddr} - ${fdt_addr}"
 #else
 #define CONFIG_BOOTCOMMAND \
 	   "mmc dev ${mmcdev}; if mmc rescan; then " \
 		   "if run loadbootscript; then " \
 			   "run bootscript; " \
 		   "else " \
 			   "if run loadimage; then " \
 				   "run mmcboot; " \
 			   "else run netboot; " \
 			   "fi; " \
 		   "fi; " \
 	   "else booti ${loadaddr} - ${fdt_addr}; fi"
 #endif

 /* Link Definitions */
 #define CONFIG_LOADADDR			0x80280000
 #define CONFIG_SYS_TEXT_BASE		0x80020000

 #define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR

 #define CONFIG_SYS_INIT_SP_ADDR         0x80200000


 /* Default environment is in SD */
 #define CONFIG_ENV_SIZE			0x1000

 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_OFFSET       (120 << 20)
 #elif defined(CONFIG_QSPI_BOOT)
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_OFFSET       (4 * 1024 * 1024)
 #define CONFIG_ENV_SECT_SIZE	(128 * 1024)
 #define CONFIG_ENV_SPI_BUS	CONFIG_SF_DEFAULT_BUS
 #define CONFIG_ENV_SPI_CS	CONFIG_SF_DEFAULT_CS
 #define CONFIG_ENV_SPI_MODE	CONFIG_SF_DEFAULT_MODE
 #define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
 #else
 #define CONFIG_ENV_OFFSET       (64 * SZ_64K)
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
 #endif

 #define CONFIG_SYS_MMC_IMG_LOAD_PART	1

 /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board
   */
 #define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
 #define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
 #define CONFIG_SYS_FSL_USDHC_NUM	2

 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (32*1024)) * 1024)

 #define CONFIG_SYS_SDRAM_BASE		0x80000000
 #define CONFIG_NR_DRAM_BANKS		3
 #define PHYS_SDRAM_1			0x80000000
 #define PHYS_SDRAM_2			0x880000000
 #ifdef CONFIG_TARGET_IMX8QXP_DDR3_ARM2
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1 GB */
 /* LPDDR4 board total DDR is 3GB */
 #define PHYS_SDRAM_2_SIZE		0x00000000
 #else
 #define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */
 /* LPDDR4 board total DDR is 3GB */
 #define PHYS_SDRAM_2_SIZE		0x40000000	/* 1 GB */
 #endif

 /* Serial */
 #define CONFIG_BAUDRATE			115200

 /* Monitor Command Prompt */
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE              1024
 #define CONFIG_SYS_MAXARGS             64
 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_CMDLINE_EDITING

 /* Generic Timer Definitions */
 #define COUNTER_FREQUENCY		8000000	/* 8MHz */

 #ifndef CONFIG_DM_PCA953X
 #define CONFIG_PCA953X
 #define CONFIG_CMD_PCA953X
 #define CONFIG_CMD_PCA953X_INFO
 #endif

 #define CONFIG_IMX_SMMU

 /* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */
 #ifdef CONFIG_FSL_FSPI
 #define CONFIG_SF_DEFAULT_BUS		0
 #define CONFIG_SF_DEFAULT_CS		0
 #define CONFIG_SF_DEFAULT_SPEED	40000000
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #define FSL_FSPI_FLASH_SIZE		SZ_64M
 #define FSL_FSPI_FLASH_NUM		1
 #define FSPI0_BASE_ADDR			0x5d120000
 #define FSPI0_AMBA_BASE			0
 #define CONFIG_SYS_FSL_FSPI_AHB
 #endif

 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_NAND_MXS
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NAND_TRIMFFS

 /* NAND stuff */
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x40000000
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_ONFI_DETECTION

 /* DMA stuff, needed for GPMI/MXS NAND support */
 #define CONFIG_APBH_DMA
 #define CONFIG_APBH_DMA_BURST
 #define CONFIG_APBH_DMA_BURST8
 #endif

 /* USB Config */
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2

 /* USB 3.0 controller configs */
 #ifdef CONFIG_USB_XHCI_IMX8
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
 #endif

 /* USB OTG controller configs */
 #ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
 #endif
 #endif /* CONFIG_CMD_USB */

 #ifdef CONFIG_USB_GADGET
 #define CONFIG_USBD_HS
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 #endif

 #if defined(CONFIG_ANDROID_SUPPORT)
 #include "imx8qxp_arm2_android.h"
 #endif

 /* Framebuffer */
 #ifdef CONFIG_VIDEO
 #define CONFIG_VIDEO_IMXDPUV1
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
 #define CONFIG_IMX_VIDEO_SKIP
 #endif

 #define CONFIG_OF_SYSTEM_SETUP
 #define BOOTAUX_RESERVED_MEM_BASE 0x88000000
 #define BOOTAUX_RESERVED_MEM_SIZE 0x08000000 /* Reserve from second 128MB */

 #endif /* __IMX8QXP_ARM2_H */
	/*
	* Copyright 2017 NXP
	*
	* SPDX-License-Identifier: GPL-2.0+
	*/

	#ifndef __IMX8QXP_ARM2_H
	#define __IMX8QXP_ARM2_H

	#include <linux/sizes.h>
	#include <asm/arch/imx-regs.h>

	#define CONFIG_REMAKE_ELF

	#define CONFIG_BOARD_EARLY_INIT_F
	#define CONFIG_ARCH_MISC_INIT

	/* Flat Device Tree Definitions */
	#define CONFIG_OF_BOARD_SETUP

	#undef CONFIG_CMD_EXPORTENV
	#undef CONFIG_CMD_IMPORTENV
	#undef CONFIG_CMD_IMLS

	#undef CONFIG_CMD_CRC32
	#undef CONFIG_BOOTM_NETBSD

	#define CONFIG_FSL_ESDHC
	#define CONFIG_FSL_USDHC
	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
	#define USDHC1_BASE_ADDR 0x5B010000
	#define USDHC2_BASE_ADDR 0x5B020000
	#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */

	#define CONFIG_ENV_OVERWRITE


	#define CONFIG_FSL_HSIO
	#ifdef CONFIG_FSL_HSIO
	#define CONFIG_PCIE_IMX8X
	#define CONFIG_CMD_PCI
	#define CONFIG_PCI
	#define CONFIG_PCI_PNP
	#define CONFIG_PCI_SCAN_SHOW
	#define CONFIG_CMD_PCI_ENUM
	#endif

	#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

	/* FUSE command */
	#define CONFIG_CMD_FUSE

	/* GPIO configs */
	#define CONFIG_MXC_GPIO

	/* ENET Config */
	#define CONFIG_MII

	#define CONFIG_FEC_MXC
	#define CONFIG_FEC_XCV_TYPE RGMII
	#define FEC_QUIRK_ENET_MAC

	#define CONFIG_PHY_GIGE /* Support for 1000BASE-X */
	#define CONFIG_PHYLIB
	#define CONFIG_PHY_ATHEROS

	/* ENET0 connects AR8031 on CPU board, ENET1 connects to base board and MUX with ESAI, default is ESAI */
	#define CONFIG_FEC_ENET_DEV 0

	#if (CONFIG_FEC_ENET_DEV == 0)
	#define IMX_FEC_BASE 0x5B040000
	#define CONFIG_FEC_MXC_PHYADDR 0x0
	#define CONFIG_ETHPRIME "eth0"
	#elif (CONFIG_FEC_ENET_DEV == 1)
	#define IMX_FEC_BASE 0x5B050000
	#define CONFIG_FEC_MXC_PHYADDR 0x1
	#define CONFIG_FEC_ENABLE_MAX7322
	#define CONFIG_ETHPRIME "eth1"
	#endif

	/* ENET0 MDIO are shared */
	#define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000

	/* MAX7322 */
	#ifdef CONFIG_FEC_ENABLE_MAX7322
	#define CONFIG_MAX7322_I2C_ADDR 0x68
	#define CONFIG_MAX7322_I2C_BUS 0 /* I2C1 */
	#endif

	/* Boot M4 */
	#define M4_BOOT_ENV \
	"m4_0_image=m4_0.bin\0" \
	"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
	"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \

	#ifdef CONFIG_NAND_BOOT
	#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
	#else
	#define MFG_NAND_PARTITION ""
	#endif

	#define CONFIG_MFG_ENV_SETTINGS \
	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
	"rdinit=/linuxrc " \
	"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
	"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
	"g_mass_storage.iSerialNumber=\"\" "\
	MFG_NAND_PARTITION \
	"video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off "\
	"clk_ignore_unused "\
	"\0" \
	"initrd_addr=0x83800000\0" \
	"initrd_high=0xffffffff\0" \
	"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \

	/* Initial environment variables */
	#ifdef CONFIG_NAND_BOOT
	#define CONFIG_EXTRA_ENV_SETTINGS \
	CONFIG_MFG_ENV_SETTINGS \
	"bootargs=console=ttyLP0,115200 ubi.mtd=5 " \
	"root=ubi0:rootfs rootfstype=ubifs " \
	"mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs)\0"\
	"console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200\0" \
	"fdt_addr=0x83000000\0"
	#else
	#define CONFIG_EXTRA_ENV_SETTINGS \
	CONFIG_MFG_ENV_SETTINGS \
	M4_BOOT_ENV \
	"script=boot.scr\0" \
	"image=Image\0" \
	"panel=NULL\0" \
	"console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200\0" \
	"fdt_addr=0x83000000\0" \
	"fdt_high=0xffffffffffffffff\0" \
	"boot_fdt=try\0" \
	"fdt_file=fsl-imx8qxp-lpddr4-arm2.dtb\0" \
	"initrd_addr=0x83800000\0" \
	"initrd_high=0xffffffffffffffff\0" \
	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
	"mmcautodetect=yes\0" \
	"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} " \
	"video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" \
	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
	"source\0" \
	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
	"mmcboot=echo Booting from mmc ...; " \
	"run mmcargs; " \
	"if test ${boot_fdt} = yes \|\| test ${boot_fdt} = try; then " \
	"if run loadfdt; then " \
	"booti ${loadaddr} - ${fdt_addr}; " \
	"else " \
	"echo WARN: Cannot load the DT; " \
	"fi; " \
	"else " \
	"echo wait for boot; " \
	"fi;\0" \
	"netargs=setenv bootargs console=${console} " \
	"root=/dev/nfs " \
	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
	"video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" \
	"netboot=echo Booting from net ...; " \
	"run netargs; " \
	"if test ${ip_dyn} = yes; then " \
	"setenv get_cmd dhcp; " \
	"else " \
	"setenv get_cmd tftp; " \
	"fi; " \
	"${get_cmd} ${loadaddr} ${image}; " \
	"if test ${boot_fdt} = yes \|\| test ${boot_fdt} = try; then " \
	"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
	"booti ${loadaddr} - ${fdt_addr}; " \
	"else " \
	"echo WARN: Cannot load the DT; " \
	"fi; " \
	"else " \
	"booti; " \
	"fi;\0"
	#endif

	#ifdef CONFIG_NAND_BOOT
	#define CONFIG_BOOTCOMMAND \
	"nand read ${loadaddr} 0x8000000 0x1400000;"\
	"nand read ${fdt_addr} 0xA000000 0x100000;"\
	"booti ${loadaddr} - ${fdt_addr}"
	#else
	#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
	"if run loadbootscript; then " \
	"run bootscript; " \
	"else " \
	"if run loadimage; then " \
	"run mmcboot; " \
	"else run netboot; " \
	"fi; " \
	"fi; " \
	"else booti ${loadaddr} - ${fdt_addr}; fi"
	#endif

	/* Link Definitions */
	#define CONFIG_LOADADDR 0x80280000
	#define CONFIG_SYS_TEXT_BASE 0x80020000

	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR

	#define CONFIG_SYS_INIT_SP_ADDR 0x80200000


	/* Default environment is in SD */
	#define CONFIG_ENV_SIZE 0x1000

	#ifdef CONFIG_NAND_BOOT
	#define CONFIG_ENV_IS_IN_NAND
	#define CONFIG_ENV_OFFSET (120 << 20)
	#elif defined(CONFIG_QSPI_BOOT)
	#define CONFIG_ENV_IS_IN_SPI_FLASH
	#define CONFIG_ENV_OFFSET (4 * 1024 * 1024)
	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
	#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
	#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
	#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
	#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	#else
	#define CONFIG_ENV_OFFSET (64 * SZ_64K)
	#define CONFIG_ENV_IS_IN_MMC
	#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
	#endif

	#define CONFIG_SYS_MMC_IMG_LOAD_PART 1

	/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board
	*/
	#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
	#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
	#define CONFIG_SYS_FSL_USDHC_NUM 2

	/* Size of malloc() pool */
	#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (321024)) 1024)

	#define CONFIG_SYS_SDRAM_BASE 0x80000000
	#define CONFIG_NR_DRAM_BANKS 3
	#define PHYS_SDRAM_1 0x80000000
	#define PHYS_SDRAM_2 0x880000000
	#ifdef CONFIG_TARGET_IMX8QXP_DDR3_ARM2
	#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
	/* LPDDR4 board total DDR is 3GB */
	#define PHYS_SDRAM_2_SIZE 0x00000000
	#else
	#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
	/* LPDDR4 board total DDR is 3GB */
	#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */
	#endif

	/* Serial */
	#define CONFIG_BAUDRATE 115200

	/* Monitor Command Prompt */
	#define CONFIG_SYS_LONGHELP
	#define CONFIG_HUSH_PARSER
	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	#define CONFIG_AUTO_COMPLETE
	#define CONFIG_SYS_CBSIZE 1024
	#define CONFIG_SYS_MAXARGS 64
	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	sizeof(CONFIG_SYS_PROMPT) + 16)
	#define CONFIG_CMDLINE_EDITING

	/* Generic Timer Definitions */
	#define COUNTER_FREQUENCY 8000000 /* 8MHz */

	#ifndef CONFIG_DM_PCA953X
	#define CONFIG_PCA953X
	#define CONFIG_CMD_PCA953X
	#define CONFIG_CMD_PCA953X_INFO
	#endif

	#define CONFIG_IMX_SMMU

	/* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */
	#ifdef CONFIG_FSL_FSPI
	#define CONFIG_SF_DEFAULT_BUS 0
	#define CONFIG_SF_DEFAULT_CS 0
	#define CONFIG_SF_DEFAULT_SPEED 40000000
	#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
	#define FSL_FSPI_FLASH_SIZE SZ_64M
	#define FSL_FSPI_FLASH_NUM 1
	#define FSPI0_BASE_ADDR 0x5d120000
	#define FSPI0_AMBA_BASE 0
	#define CONFIG_SYS_FSL_FSPI_AHB
	#endif

	#ifdef CONFIG_NAND_BOOT
	#define CONFIG_NAND_MXS
	#define CONFIG_CMD_NAND
	#define CONFIG_CMD_NAND_TRIMFFS

	/* NAND stuff */
	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	#define CONFIG_SYS_NAND_BASE 0x40000000
	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	#define CONFIG_SYS_NAND_ONFI_DETECTION

	/* DMA stuff, needed for GPMI/MXS NAND support */
	#define CONFIG_APBH_DMA
	#define CONFIG_APBH_DMA_BURST
	#define CONFIG_APBH_DMA_BURST8
	#endif

	/* USB Config */
	#ifdef CONFIG_CMD_USB
	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2

	/* USB 3.0 controller configs */
	#ifdef CONFIG_USB_XHCI_IMX8
	#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
	#endif

	/* USB OTG controller configs */
	#ifdef CONFIG_USB_EHCI_HCD
	#define CONFIG_USB_HOST_ETHER
	#define CONFIG_USB_ETHER_ASIX
	#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI \| PORT_PTS_PTW)
	#endif
	#endif /* CONFIG_CMD_USB */

	#ifdef CONFIG_USB_GADGET
	#define CONFIG_USBD_HS
	#define CONFIG_USB_FUNCTION_MASS_STORAGE
	#endif

	#if defined(CONFIG_ANDROID_SUPPORT)
	#include "imx8qxp_arm2_android.h"
	#endif

	/* Framebuffer */
	#ifdef CONFIG_VIDEO
	#define CONFIG_VIDEO_IMXDPUV1
	#define CONFIG_VIDEO_BMP_RLE8
	#define CONFIG_SPLASH_SCREEN
	#define CONFIG_SPLASH_SCREEN_ALIGN
	#define CONFIG_BMP_16BPP
	#define CONFIG_VIDEO_LOGO
	#define CONFIG_VIDEO_BMP_LOGO
	#define CONFIG_IMX_VIDEO_SKIP
	#endif

	#define CONFIG_OF_SYSTEM_SETUP
	#define BOOTAUX_RESERVED_MEM_BASE 0x88000000
	#define BOOTAUX_RESERVED_MEM_SIZE 0x08000000 /* Reserve from second 128MB */

	#endif /* __IMX8QXP_ARM2_H */