| /* |
| * Copyright (C) 2016 Amarula Solutions B.V. |
| * Copyright (C) 2016 Engicam S.r.l. |
| * Author: Jagan Teki <jagan@amarulasolutions.com> |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| #include <common.h> |
| |
| #include <asm/io.h> |
| #include <asm/gpio.h> |
| #include <linux/sizes.h> |
| |
| #include <asm/arch/clock.h> |
| #include <asm/arch/crm_regs.h> |
| #include <asm/arch/iomux.h> |
| #include <asm/arch/mx6-pins.h> |
| #include <asm/arch/sys_proto.h> |
| #include <asm/imx-common/iomux-v3.h> |
| #include <asm/imx-common/video.h> |
| |
| DECLARE_GLOBAL_DATA_PTR; |
| |
| #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
| PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| static iomux_v3_cfg_t const uart4_pads[] = { |
| IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
| IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
| }; |
| |
| #ifdef CONFIG_NAND_MXS |
| |
| #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) |
| #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ |
| PAD_CTL_SRE_FAST) |
| #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) |
| |
| iomux_v3_cfg_t gpmi_pads[] = { |
| IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)), |
| IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| }; |
| |
| static void setup_gpmi_nand(void) |
| { |
| struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| |
| /* config gpmi nand iomux */ |
| SETUP_IOMUX_PADS(gpmi_pads); |
| |
| /* gate ENFC_CLK_ROOT clock first,before clk source switch */ |
| clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); |
| |
| /* config gpmi and bch clock to 100 MHz */ |
| clrsetbits_le32(&mxc_ccm->cs2cdr, |
| MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | |
| MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | |
| MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, |
| MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | |
| MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | |
| MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); |
| |
| /* enable ENFC_CLK_ROOT clock */ |
| setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); |
| |
| /* enable gpmi and bch clock gating */ |
| setbits_le32(&mxc_ccm->CCGR4, |
| MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | |
| MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | |
| MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | |
| MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | |
| MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); |
| |
| /* enable apbh clock gating */ |
| setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); |
| } |
| #endif |
| |
| #if defined(CONFIG_VIDEO_IPUV3) |
| static iomux_v3_cfg_t const rgb_pads[] = { |
| IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), |
| IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), |
| IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), |
| IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), |
| IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00), |
| IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01), |
| IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02), |
| IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03), |
| IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04), |
| IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05), |
| IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06), |
| IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07), |
| IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08), |
| IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09), |
| IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10), |
| IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11), |
| IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12), |
| IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13), |
| IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14), |
| IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15), |
| IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16), |
| IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17), |
| }; |
| |
| static void enable_rgb(struct display_info_t const *dev) |
| { |
| SETUP_IOMUX_PADS(rgb_pads); |
| } |
| |
| struct display_info_t const displays[] = { |
| { |
| .bus = -1, |
| .addr = 0, |
| .pixfmt = IPU_PIX_FMT_RGB666, |
| .detect = NULL, |
| .enable = enable_rgb, |
| .mode = { |
| .name = "Amp-WD", |
| .refresh = 60, |
| .xres = 800, |
| .yres = 480, |
| .pixclock = 30000, |
| .left_margin = 30, |
| .right_margin = 30, |
| .upper_margin = 5, |
| .lower_margin = 5, |
| .hsync_len = 64, |
| .vsync_len = 20, |
| .sync = FB_SYNC_EXT, |
| .vmode = FB_VMODE_NONINTERLACED |
| } |
| }, |
| }; |
| |
| size_t display_count = ARRAY_SIZE(displays); |
| |
| static void setup_display(void) |
| { |
| struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| int reg; |
| |
| enable_ipu_clock(); |
| |
| /* Turn on LDB0,IPU,IPU DI0 clocks */ |
| reg = __raw_readl(&mxc_ccm->CCGR3); |
| reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff); |
| writel(reg, &mxc_ccm->CCGR3); |
| |
| /* set LDB0, LDB1 clk select to 011/011 */ |
| reg = readl(&mxc_ccm->cs2cdr); |
| reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | |
| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); |
| reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | |
| (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); |
| writel(reg, &mxc_ccm->cs2cdr); |
| |
| reg = readl(&mxc_ccm->cscmr2); |
| reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; |
| writel(reg, &mxc_ccm->cscmr2); |
| |
| reg = readl(&mxc_ccm->chsccdr); |
| reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << |
| MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); |
| writel(reg, &mxc_ccm->chsccdr); |
| |
| reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | |
| IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | |
| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | |
| IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | |
| IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | |
| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | |
| IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | |
| IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED | |
| IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; |
| writel(reg, &iomux->gpr[2]); |
| |
| reg = readl(&iomux->gpr[3]); |
| reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) | |
| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << |
| IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); |
| writel(reg, &iomux->gpr[3]); |
| } |
| #endif /* CONFIG_VIDEO_IPUV3 */ |
| |
| int board_early_init_f(void) |
| { |
| SETUP_IOMUX_PADS(uart4_pads); |
| |
| return 0; |
| } |
| |
| int board_init(void) |
| { |
| /* Address of boot parameters */ |
| gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| |
| #ifdef CONFIG_NAND_MXS |
| setup_gpmi_nand(); |
| #endif |
| |
| #ifdef CONFIG_VIDEO_IPUV3 |
| setup_display(); |
| #endif |
| |
| return 0; |
| } |
| |
| int dram_init(void) |
| { |
| gd->ram_size = imx_ddr_size(); |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_SPL_BUILD |
| #include <libfdt.h> |
| #include <spl.h> |
| |
| #include <asm/arch/crm_regs.h> |
| #include <asm/arch/mx6-ddr.h> |
| |
| /* MMC board initialization is needed till adding DM support in SPL */ |
| #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) |
| #include <mmc.h> |
| #include <fsl_esdhc.h> |
| |
| #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ |
| PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| static iomux_v3_cfg_t const usdhc1_pads[] = { |
| IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
| IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
| IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
| IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
| IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
| IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
| IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */ |
| }; |
| |
| #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1) |
| |
| struct fsl_esdhc_cfg usdhc_cfg[1] = { |
| {USDHC1_BASE_ADDR, 0, 4}, |
| }; |
| |
| int board_mmc_getcd(struct mmc *mmc) |
| { |
| struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| int ret = 0; |
| |
| switch (cfg->esdhc_base) { |
| case USDHC1_BASE_ADDR: |
| ret = !gpio_get_value(USDHC1_CD_GPIO); |
| break; |
| } |
| |
| return ret; |
| } |
| |
| int board_mmc_init(bd_t *bis) |
| { |
| int i, ret; |
| |
| /* |
| * According to the board_mmc_init() the following map is done: |
| * (U-boot device node) (Physical Port) |
| * mmc0 USDHC1 |
| */ |
| for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
| switch (i) { |
| case 0: |
| SETUP_IOMUX_PADS(usdhc1_pads); |
| gpio_direction_input(USDHC1_CD_GPIO); |
| usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
| break; |
| default: |
| printf("Warning - USDHC%d controller not supporting\n", |
| i + 1); |
| return 0; |
| } |
| |
| ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
| if (ret) { |
| printf("Warning: failed to initialize mmc dev %d\n", i); |
| return ret; |
| } |
| } |
| |
| return 0; |
| } |
| #endif |
| |
| /* |
| * Driving strength: |
| * 0x30 == 40 Ohm |
| * 0x28 == 48 Ohm |
| */ |
| |
| #define IMX6DQ_DRIVE_STRENGTH 0x30 |
| #define IMX6SDL_DRIVE_STRENGTH 0x28 |
| |
| /* configure MX6Q/DUAL mmdc DDR io registers */ |
| static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { |
| .dram_sdqs0 = 0x28, |
| .dram_sdqs1 = 0x28, |
| .dram_sdqs2 = 0x28, |
| .dram_sdqs3 = 0x28, |
| .dram_sdqs4 = 0x28, |
| .dram_sdqs5 = 0x28, |
| .dram_sdqs6 = 0x28, |
| .dram_sdqs7 = 0x28, |
| .dram_dqm0 = 0x28, |
| .dram_dqm1 = 0x28, |
| .dram_dqm2 = 0x28, |
| .dram_dqm3 = 0x28, |
| .dram_dqm4 = 0x28, |
| .dram_dqm5 = 0x28, |
| .dram_dqm6 = 0x28, |
| .dram_dqm7 = 0x28, |
| .dram_cas = 0x30, |
| .dram_ras = 0x30, |
| .dram_sdclk_0 = 0x30, |
| .dram_sdclk_1 = 0x30, |
| .dram_reset = 0x30, |
| .dram_sdcke0 = 0x3000, |
| .dram_sdcke1 = 0x3000, |
| .dram_sdba2 = 0x00000000, |
| .dram_sdodt0 = 0x30, |
| .dram_sdodt1 = 0x30, |
| }; |
| |
| /* configure MX6Q/DUAL mmdc GRP io registers */ |
| static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { |
| .grp_b0ds = 0x30, |
| .grp_b1ds = 0x30, |
| .grp_b2ds = 0x30, |
| .grp_b3ds = 0x30, |
| .grp_b4ds = 0x30, |
| .grp_b5ds = 0x30, |
| .grp_b6ds = 0x30, |
| .grp_b7ds = 0x30, |
| .grp_addds = 0x30, |
| .grp_ddrmode_ctl = 0x00020000, |
| .grp_ddrpke = 0x00000000, |
| .grp_ddrmode = 0x00020000, |
| .grp_ctlds = 0x30, |
| .grp_ddr_type = 0x000c0000, |
| }; |
| |
| /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ |
| struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { |
| .dram_sdclk_0 = 0x30, |
| .dram_sdclk_1 = 0x30, |
| .dram_cas = 0x30, |
| .dram_ras = 0x30, |
| .dram_reset = 0x30, |
| .dram_sdcke0 = 0x30, |
| .dram_sdcke1 = 0x30, |
| .dram_sdba2 = 0x00000000, |
| .dram_sdodt0 = 0x30, |
| .dram_sdodt1 = 0x30, |
| .dram_sdqs0 = 0x28, |
| .dram_sdqs1 = 0x28, |
| .dram_sdqs2 = 0x28, |
| .dram_sdqs3 = 0x28, |
| .dram_sdqs4 = 0x28, |
| .dram_sdqs5 = 0x28, |
| .dram_sdqs6 = 0x28, |
| .dram_sdqs7 = 0x28, |
| .dram_dqm0 = 0x28, |
| .dram_dqm1 = 0x28, |
| .dram_dqm2 = 0x28, |
| .dram_dqm3 = 0x28, |
| .dram_dqm4 = 0x28, |
| .dram_dqm5 = 0x28, |
| .dram_dqm6 = 0x28, |
| .dram_dqm7 = 0x28, |
| }; |
| |
| /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ |
| struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { |
| .grp_ddr_type = 0x000c0000, |
| .grp_ddrmode_ctl = 0x00020000, |
| .grp_ddrpke = 0x00000000, |
| .grp_addds = 0x30, |
| .grp_ctlds = 0x30, |
| .grp_ddrmode = 0x00020000, |
| .grp_b0ds = 0x28, |
| .grp_b1ds = 0x28, |
| .grp_b2ds = 0x28, |
| .grp_b3ds = 0x28, |
| .grp_b4ds = 0x28, |
| .grp_b5ds = 0x28, |
| .grp_b6ds = 0x28, |
| .grp_b7ds = 0x28, |
| }; |
| |
| /* mt41j256 */ |
| static struct mx6_ddr3_cfg mt41j256 = { |
| .mem_speed = 1066, |
| .density = 2, |
| .width = 16, |
| .banks = 8, |
| .rowaddr = 13, |
| .coladdr = 10, |
| .pagesz = 2, |
| .trcd = 1375, |
| .trcmin = 4875, |
| .trasmin = 3500, |
| .SRT = 0, |
| }; |
| |
| static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { |
| .p0_mpwldectrl0 = 0x000E0009, |
| .p0_mpwldectrl1 = 0x0018000E, |
| .p1_mpwldectrl0 = 0x00000007, |
| .p1_mpwldectrl1 = 0x00000000, |
| .p0_mpdgctrl0 = 0x43280334, |
| .p0_mpdgctrl1 = 0x031C0314, |
| .p1_mpdgctrl0 = 0x4318031C, |
| .p1_mpdgctrl1 = 0x030C0258, |
| .p0_mprddlctl = 0x3E343A40, |
| .p1_mprddlctl = 0x383C3844, |
| .p0_mpwrdlctl = 0x40404440, |
| .p1_mpwrdlctl = 0x4C3E4446, |
| }; |
| |
| /* DDR 64bit */ |
| static struct mx6_ddr_sysinfo mem_q = { |
| .ddr_type = DDR_TYPE_DDR3, |
| .dsize = 2, |
| .cs1_mirror = 0, |
| /* config for full 4GB range so that get_mem_size() works */ |
| .cs_density = 32, |
| .ncs = 1, |
| .bi_on = 1, |
| .rtt_nom = 2, |
| .rtt_wr = 2, |
| .ralat = 5, |
| .walat = 0, |
| .mif3_mode = 3, |
| .rst_to_cke = 0x23, |
| .sde_to_rst = 0x10, |
| }; |
| |
| static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { |
| .p0_mpwldectrl0 = 0x001F0024, |
| .p0_mpwldectrl1 = 0x00110018, |
| .p1_mpwldectrl0 = 0x001F0024, |
| .p1_mpwldectrl1 = 0x00110018, |
| .p0_mpdgctrl0 = 0x4230022C, |
| .p0_mpdgctrl1 = 0x02180220, |
| .p1_mpdgctrl0 = 0x42440248, |
| .p1_mpdgctrl1 = 0x02300238, |
| .p0_mprddlctl = 0x44444A48, |
| .p1_mprddlctl = 0x46484A42, |
| .p0_mpwrdlctl = 0x38383234, |
| .p1_mpwrdlctl = 0x3C34362E, |
| }; |
| |
| /* DDR 64bit 1GB */ |
| static struct mx6_ddr_sysinfo mem_dl = { |
| .dsize = 2, |
| .cs1_mirror = 0, |
| /* config for full 4GB range so that get_mem_size() works */ |
| .cs_density = 32, |
| .ncs = 1, |
| .bi_on = 1, |
| .rtt_nom = 1, |
| .rtt_wr = 1, |
| .ralat = 5, |
| .walat = 0, |
| .mif3_mode = 3, |
| .rst_to_cke = 0x23, |
| .sde_to_rst = 0x10, |
| }; |
| |
| /* DDR 32bit 512MB */ |
| static struct mx6_ddr_sysinfo mem_s = { |
| .dsize = 1, |
| .cs1_mirror = 0, |
| /* config for full 4GB range so that get_mem_size() works */ |
| .cs_density = 32, |
| .ncs = 1, |
| .bi_on = 1, |
| .rtt_nom = 1, |
| .rtt_wr = 1, |
| .ralat = 5, |
| .walat = 0, |
| .mif3_mode = 3, |
| .rst_to_cke = 0x23, |
| .sde_to_rst = 0x10, |
| }; |
| |
| static void ccgr_init(void) |
| { |
| struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| |
| writel(0x00003F3F, &ccm->CCGR0); |
| writel(0x0030FC00, &ccm->CCGR1); |
| writel(0x000FC000, &ccm->CCGR2); |
| writel(0x3F300000, &ccm->CCGR3); |
| writel(0xFF00F300, &ccm->CCGR4); |
| writel(0x0F0000C3, &ccm->CCGR5); |
| writel(0x000003CC, &ccm->CCGR6); |
| } |
| |
| static void gpr_init(void) |
| { |
| struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| |
| /* enable AXI cache for VDOA/VPU/IPU */ |
| writel(0xF00000CF, &iomux->gpr[4]); |
| /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ |
| writel(0x007F007F, &iomux->gpr[6]); |
| writel(0x007F007F, &iomux->gpr[7]); |
| } |
| |
| static void spl_dram_init(void) |
| { |
| if (is_mx6solo()) { |
| mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); |
| mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256); |
| } else if (is_mx6dl()) { |
| mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); |
| mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256); |
| } else if (is_mx6dq()) { |
| mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); |
| mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256); |
| } |
| |
| udelay(100); |
| } |
| |
| void board_init_f(ulong dummy) |
| { |
| ccgr_init(); |
| |
| /* setup AIPS and disable watchdog */ |
| arch_cpu_init(); |
| |
| gpr_init(); |
| |
| /* iomux */ |
| board_early_init_f(); |
| |
| /* setup GP timer */ |
| timer_init(); |
| |
| /* UART clocks enabled and gd valid - init serial console */ |
| preloader_console_init(); |
| |
| /* DDR initialization */ |
| spl_dram_init(); |
| |
| /* Clear the BSS. */ |
| memset(__bss_start, 0, __bss_end - __bss_start); |
| |
| /* load/boot image from boot device */ |
| board_init_r(NULL, 0); |
| } |
| #endif |