Add baseboard id detection
- Add get_baseboard_id routine, and a baseboardid console command.
Change-Id: I857dafd6ebc675406c2daf8b313437d4345f0ef6
diff --git a/board/freescale/imx8mq_phanbell/board_id.c b/board/freescale/imx8mq_phanbell/board_id.c
index 3b623c3..8d64741 100644
--- a/board/freescale/imx8mq_phanbell/board_id.c
+++ b/board/freescale/imx8mq_phanbell/board_id.c
@@ -16,18 +16,43 @@
#define BOARD_ID_GPIO2 IMX_GPIO_NR(BOARD_ID_GPIOS_PORT, BOARD_ID_GPIO2_INDEX)
#define BOARD_ID_GPIO3 IMX_GPIO_NR(BOARD_ID_GPIOS_PORT, BOARD_ID_GPIO3_INDEX)
+#define BASEBOARD_ID_GPIOS_PORT 3
+#define BASEBOARD_ID_GPIOS_BASE GPIO3_BASE_ADDR
+#define BASEBOARD_ID_GPIO1_INDEX 25
+#define BASEBOARD_ID_GPIO2_INDEX 23
+#define BASEBOARD_ID_GPIO3_INDEX 20
+#define BASEBOARD_ID_GPIO4_INDEX 21
+#define BASEBOARD_ID_GPIO1 IMX_GPIO_NR(BASEBOARD_ID_GPIOS_PORT, BASEBOARD_ID_GPIO1_INDEX)
+#define BASEBOARD_ID_GPIO2 IMX_GPIO_NR(BASEBOARD_ID_GPIOS_PORT, BASEBOARD_ID_GPIO2_INDEX)
+#define BASEBOARD_ID_GPIO3 IMX_GPIO_NR(BASEBOARD_ID_GPIOS_PORT, BASEBOARD_ID_GPIO3_INDEX)
+#define BASEBOARD_ID_GPIO4 IMX_GPIO_NR(BASEBOARD_ID_GPIOS_PORT, BASEBOARD_ID_GPIO4_INDEX)
+
static iomux_v3_cfg_t const board_id_pads[] = {
IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22 | MUX_PAD_CTRL(PAD_CTL_DSE0),
IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 | MUX_PAD_CTRL(PAD_CTL_DSE0),
IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 | MUX_PAD_CTRL(PAD_CTL_DSE0),
};
-static iomux_v3_cfg_t const default_pads[] = {
+static iomux_v3_cfg_t const board_id_default_pads[] = {
IMX8MQ_PAD_SAI5_RXD1__SAI5_RX_DATA1 | MUX_PAD_CTRL(0x1816),
IMX8MQ_PAD_SAI5_RXD3__SAI5_RX_DATA3 | MUX_PAD_CTRL(0x16),
IMX8MQ_PAD_SAI5_RXFS__SAI5_RX_SYNC | MUX_PAD_CTRL(0x16),
};
+static iomux_v3_cfg_t const baseboard_id_pads[] = {
+ IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25 | MUX_PAD_CTRL(PAD_CTL_DSE0),
+ IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23 | MUX_PAD_CTRL(PAD_CTL_DSE0),
+ IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20 | MUX_PAD_CTRL(PAD_CTL_DSE0),
+ IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21 | MUX_PAD_CTRL(PAD_CTL_DSE0),
+};
+
+static iomux_v3_cfg_t const baseboard_id_default_pads[] = {
+ IMX8MQ_PAD_SAI5_MCLK__SAI5_MCLK | MUX_PAD_CTRL(0x16),
+ IMX8MQ_PAD_SAI5_RXD2__SAI5_RX_DATA2 | MUX_PAD_CTRL(0x16),
+ IMX8MQ_PAD_SAI5_RXC__SAI5_RX_BCLK | MUX_PAD_CTRL(0x16),
+ IMX8MQ_PAD_SAI5_RXD0__SAI5_RX_DATA0 | MUX_PAD_CTRL(0x16),
+};
+
int get_board_id() {
int board_id = 0;
@@ -56,12 +81,51 @@
board_id |= (readl(®s->gpio_dr) >> (BOARD_ID_GPIO3_INDEX - 2)) & 0x04;
#endif
- imx_iomux_v3_setup_multiple_pads(default_pads,
- ARRAY_SIZE(default_pads));
+ imx_iomux_v3_setup_multiple_pads(board_id_default_pads,
+ ARRAY_SIZE(board_id_default_pads));
return board_id;
}
+int get_baseboard_id() {
+ int baseboard_id = -1;
+
+ imx_iomux_v3_setup_multiple_pads(baseboard_id_pads, ARRAY_SIZE(baseboard_id_pads));
+
+#ifdef CONFIG_SPL_BUILD
+ gpio_request(BASEBOARD_ID_GPIO1, "baseboard_id_1");
+ gpio_direction_input(BASEBOARD_ID_GPIO1);
+ gpio_request(BASEBOARD_ID_GPIO2, "baseboard_id_2");
+ gpio_direction_input(BASEBOARD_ID_GPIO2);
+ gpio_request(BASEBOARD_ID_GPIO3, "baseboard_id_3");
+ gpio_direction_input(BASEBOARD_ID_GPIO3);
+ gpio_request(BASEBOARD_ID_GPIO4, "baseboard_id_4");
+ gpio_direction_input(BASEBOARD_ID_GPIO4);
+
+ baseboard_id = gpio_get_value(BASEBOARD_ID_GPIO1);
+ baseboard_id |= gpio_get_value(BASEBOARD_ID_GPIO2) << 1;
+ baseboard_id |= gpio_get_value(BASEBOARD_ID_GPIO3) << 2;
+ baseboard_id |= gpio_get_value(BASEBOARD_ID_GPIO4) << 3;
+
+ gpio_free(BASEBOARD_ID_GPIO1);
+ gpio_free(BASEBOARD_ID_GPIO2);
+ gpio_free(BASEBOARD_ID_GPIO3);
+ gpio_free(BASEBOARD_ID_GPIO4);
+#else
+
+ struct gpio_regs *regs = (struct gpio_regs *)BASEBOARD_ID_GPIOS_BASE;
+ baseboard_id = (readl(®s->gpio_dr) >> BASEBOARD_ID_GPIO1_INDEX) & 0x01;
+ baseboard_id |= (readl(®s->gpio_dr) >> (BASEBOARD_ID_GPIO2_INDEX - 1)) & 0x02;
+ baseboard_id |= (readl(®s->gpio_dr) >> (BASEBOARD_ID_GPIO3_INDEX - 2)) & 0x04;
+ baseboard_id |= (readl(®s->gpio_dr) >> (BASEBOARD_ID_GPIO4_INDEX - 3)) & 0x08;
+#endif
+
+ imx_iomux_v3_setup_multiple_pads(baseboard_id_default_pads,
+ ARRAY_SIZE(baseboard_id_default_pads));
+
+ return baseboard_id;
+}
+
size_t get_ddr_size(void) {
const size_t k1Gb = 0x40000000;
const size_t k3Gb = 0xC0000000;
diff --git a/board/freescale/imx8mq_phanbell/board_id.h b/board/freescale/imx8mq_phanbell/board_id.h
index 48716b0..e0832eb 100644
--- a/board/freescale/imx8mq_phanbell/board_id.h
+++ b/board/freescale/imx8mq_phanbell/board_id.h
@@ -14,6 +14,7 @@
// 7 - DVT boards with 3Gb Micron (MT53E768M32D4DT) DDR
int get_board_id(void);
+int get_baseboard_id(void);
size_t get_ddr_size(void);
#endif
diff --git a/board/freescale/imx8mq_phanbell/board_id_cmd.c b/board/freescale/imx8mq_phanbell/board_id_cmd.c
index 7fbcc5c..240b030 100644
--- a/board/freescale/imx8mq_phanbell/board_id_cmd.c
+++ b/board/freescale/imx8mq_phanbell/board_id_cmd.c
@@ -18,6 +18,13 @@
"Unknown"
};
+const char* baseboard_id_names[] = {
+ "Invalid",
+ "Enterprise",
+ "Yorktown",
+ "Unknown"
+};
+
static int do_board_id(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int board_id = get_board_id();
@@ -37,9 +44,35 @@
return 0;
}
+static int do_baseboard_id(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int baseboard_id = get_baseboard_id();
+ const char* baseboard_id_name;
+
+ if (baseboard_id >= ARRAY_SIZE(baseboard_id_names)) {
+ baseboard_id_name = baseboard_id_names[ARRAY_SIZE(baseboard_id_names) - 1];
+ }
+
+ baseboard_id_name = baseboard_id_names[baseboard_id];
+
+ putc('0' + baseboard_id);
+ puts(": ");
+ puts(baseboard_id_name);
+ putc('\n');
+
+ return 0;
+}
+
U_BOOT_CMD(
boardid, 1, 0, do_board_id,
"display board ID",
"\n"
" - displays the board ID value from the GPIO pins."
);
+
+U_BOOT_CMD(
+ baseboardid, 1, 0, do_baseboard_id,
+ "display baseboard ID",
+ "\n"
+ " - displays the board ID value for the baseboard."
+);
