arch/arm/dts/imx7d-12x12-lpddr3-arm2-qspi.dts

/*
 * Copyright (C) 2015 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include "imx7d-12x12-lpddr3-arm2.dts"

/* disable epdc, conflict with qspi */
&epdc {
        status = "disabled";
};

&iomuxc {
	qspi1 {
		pinctrl_qspi1_1: qspi1grp_1 {
			fsl,pins = <
				MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51
				MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51
				MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51
				MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51
				MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x51
				MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51
				MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51
				MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x51
				MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x51
				MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x51
				MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x51
				MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x51
				MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x51
				MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x51
				MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x51
				MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x51
			>;
		};
	};
};

&qspi1 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_qspi1_1>;
	pinctrl-1 = <&pinctrl_qspi1_1>;
	status = "okay";
	fsl,qspi-has-second-chip = <1>;
	ddrsmp=<0>;

	flash0: n25q256a@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "spi-flash";
		spi-max-frequency = <29000000>;
		spi-nor,ddr-quad-read-dummy = <6>;
		reg = <0>;
	};

	flash1: n25q256a@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "spi-flash";
		spi-max-frequency = <29000000>;
		spi-nor,ddr-quad-read-dummy = <6>;
		reg = <1>;
	};

	flash2: n25q256a@2 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "spi-flash";
		spi-max-frequency = <29000000>;
		spi-nor,ddr-quad-read-dummy = <6>;
		reg = <2>;
	};

	flash3: n25q256a@3 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "spi-flash";
		spi-max-frequency = <29000000>;
		spi-nor,ddr-quad-read-dummy = <6>;
		reg = <3>;
	};
};