| /* |
| * Copyright (C) 2015 Freescale Semiconductor, Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| |
| /dts-v1/; |
| |
| #include <dt-bindings/input/input.h> |
| #include "imx6ul.dtsi" |
| |
| / { |
| model = "Freescale i.MX6 UltraLite 14X14 LPDDR2 ARM2 Board"; |
| compatible = "fsl,imx6ul-14x14-lpddr2-arm2", "fsl,imx6ul"; |
| |
| chosen { |
| stdout-path = &uart1; |
| }; |
| |
| memory { |
| reg = <0x80000000 0x20000000>; |
| }; |
| |
| reserved-memory { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| linux,cma { |
| compatible = "shared-dma-pool"; |
| reusable; |
| size = <0x14000000>; |
| linux,cma-default; |
| }; |
| }; |
| |
| pxp_v4l2 { |
| compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; |
| status = "okay"; |
| }; |
| |
| regulators { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| reg_sd1_vmmc: sd1_vmmc { |
| compatible = "regulator-fixed"; |
| regulator-name = "SD1_SPWR"; |
| regulator-min-microvolt = <3000000>; |
| regulator-max-microvolt = <3000000>; |
| gpio = <&gpio4 11 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| reg_sd2_vmmc: sd2_vmmc { |
| compatible = "regulator-fixed"; |
| regulator-name = "SD2_SPWR"; |
| regulator-min-microvolt = <3000000>; |
| regulator-max-microvolt = <3000000>; |
| gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| reg_can1_3v3: regulator@0 { |
| compatible = "regulator-fixed"; |
| reg = <0>; |
| regulator-name = "can1-3v3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio1 15 GPIO_ACTIVE_LOW>; |
| }; |
| |
| reg_vref_3v3: regulator@1 { |
| compatible = "regulator-fixed"; |
| regulator-name = "vref-3v3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| }; |
| |
| reg_usb_otg1_vbus: regulator@2 { |
| compatible = "regulator-fixed"; |
| reg = <2>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usb_otg1>; |
| regulator-name = "usb_otg1_vbus"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| }; |
| }; |
| |
| &ecspi2 { |
| fsl,spi-num-chipselects = <1>; |
| cs-gpios = <&gpio4 22 0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ecspi2_1 &pinctrl_ecspi2_cs_1>; |
| status = "disabled"; |
| |
| flash: n25q032@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "st,n25q032"; |
| spi-max-frequency = <20000000>; |
| reg = <0>; |
| }; |
| }; |
| |
| &cpu0 { |
| /* |
| * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN, |
| * to align with other platform and use the same cpufreq |
| * driver, still use the seperated OPP define for arm |
| * and soc. |
| */ |
| operating-points = < |
| /* kHz uV */ |
| 528000 1175000 |
| 396000 1175000 |
| 198000 1175000 |
| >; |
| fsl,soc-operating-points = < |
| /* KHz uV */ |
| 528000 1175000 |
| 396000 1175000 |
| 198000 1175000 |
| >; |
| arm-supply = <&sw1a_reg>; |
| soc-supply = <&sw1a_reg>; |
| fsl,arm-soc-shared = <1>; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet1>; |
| phy-mode = "mii"; |
| phy-handle = <ðphy0>; |
| status = "disabled"; |
| }; |
| |
| &fec2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet2>; |
| phy-mode = "rmii"; |
| phy-handle = <ðphy1>; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@1 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <2>; |
| }; |
| |
| ethphy1: ethernet-phy@2 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <1>; |
| }; |
| }; |
| }; |
| |
| &flexcan1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexcan1>; |
| xceiver-supply = <®_can1_3v3>; |
| status = "disabled"; |
| }; |
| |
| &gpc { |
| fsl,cpu_pupscr_sw2iso = <0x2>; |
| fsl,cpu_pupscr_sw = <0x1>; |
| fsl,cpu_pdnscr_iso2sw = <0x1>; |
| fsl,cpu_pdnscr_iso = <0x1>; |
| fsl,wdog-reset = <1>; /* watchdog select of reset source */ |
| fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ |
| }; |
| |
| &gpmi { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_gpmi_nand_1>; |
| status = "disabled"; |
| nand-on-flash-bbt; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| status = "okay"; |
| |
| pmic: pfuze100@08 { |
| compatible = "fsl,pfuze200"; |
| reg = <0x08>; |
| |
| regulators { |
| sw1a_reg: sw1ab { |
| regulator-min-microvolt = <300000>; |
| regulator-max-microvolt = <1875000>; |
| regulator-always-on; |
| regulator-ramp-delay = <6250>; |
| }; |
| |
| sw2_reg: sw2 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| sw3a_reg: sw3a { |
| regulator-min-microvolt = <400000>; |
| regulator-max-microvolt = <1975000>; |
| regulator-always-on; |
| }; |
| |
| sw3b_reg: sw3b { |
| regulator-min-microvolt = <400000>; |
| regulator-max-microvolt = <1975000>; |
| regulator-always-on; |
| }; |
| |
| swbst_reg: swbst { |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5150000>; |
| }; |
| |
| snvs_reg: vsnvs { |
| regulator-min-microvolt = <1000000>; |
| regulator-max-microvolt = <3000000>; |
| regulator-always-on; |
| }; |
| |
| vref_reg: vrefddr { |
| regulator-always-on; |
| }; |
| |
| vgen1_reg: vgen1 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1550000>; |
| }; |
| |
| vgen2_reg: vgen2 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1550000>; |
| }; |
| |
| vgen3_reg: vgen3 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| }; |
| |
| vgen4_reg: vgen4 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen5_reg: vgen5 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen6_reg: vgen6 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| }; |
| |
| &pxp { |
| status = "okay"; |
| }; |
| |
| &qspi { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_qspi>; |
| status = "disabled"; |
| fsl,qspi-has-second-chip = <1>; |
| ddrsmp=<0>; |
| |
| flash0: n25q256a@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "spi-flash"; |
| spi-max-frequency = <29000000>; |
| spi-nor,ddr-quad-read-dummy = <6>; |
| reg = <0>; |
| }; |
| |
| flash1: n25q256a@1 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "spi-flash"; |
| spi-max-frequency = <29000000>; |
| spi-nor,ddr-quad-read-dummy = <6>; |
| reg = <1>; |
| }; |
| |
| flash2: n25q256a@2 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "spi-flash"; |
| spi-max-frequency = <29000000>; |
| spi-nor,ddr-quad-read-dummy = <6>; |
| reg = <2>; |
| }; |
| |
| flash3: n25q256a@3 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "spi-flash"; |
| spi-max-frequency = <29000000>; |
| spi-nor,ddr-quad-read-dummy = <6>; |
| reg = <3>; |
| }; |
| }; |
| |
| &uart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>; |
| status = "okay"; |
| }; |
| |
| &usbotg1 { |
| vbus-supply = <®_usb_otg1_vbus>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usb_otg1_id>; |
| status = "okay"; |
| }; |
| |
| &usdhc1 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc1>; |
| pinctrl-1 = <&pinctrl_usdhc1_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc1_200mhz>; |
| cd-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; |
| wp-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; |
| keep-power-in-suspend; |
| enable-sdio-wakeup; |
| vmmc-supply = <®_sd1_vmmc>; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc2_8bit>; |
| pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; |
| keep-power-in-suspend; |
| vmmc-supply = <®_sd2_vmmc>; |
| bus-width = <8>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hog &pinctrl_hog_nand>; |
| |
| imx6ul-14x14-lpddr2-arm2 { |
| pinctrl_hog: hoggrp { |
| fsl,pins = < |
| MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* SD1 CD */ |
| MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* SD1 WP */ |
| MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ |
| MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x17059 /* SD2 VSELECT */ |
| >; |
| }; |
| |
| pinctrl_hog_nand: hoggrp_nand { |
| fsl,pins = < |
| MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x17059 /* SD1 RESET */ |
| MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x17059 /* SD2 RESET */ |
| >; |
| }; |
| |
| pinctrl_ecspi2_cs_1: ecspi2_cs_grp-1 { |
| fsl,pins = < |
| MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 |
| >; |
| }; |
| |
| pinctrl_ecspi2_1: ecspi2grp-1 { |
| fsl,pins = < |
| MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x10b0 |
| MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x10b0 |
| MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x10b0 |
| >; |
| }; |
| |
| pinctrl_enet1: enet1grp { |
| fsl,pins = < |
| MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 |
| MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 |
| MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 |
| MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 |
| MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x1b0b0 |
| MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x1b0b0 |
| MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x4b01b0a8 |
| MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 |
| MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 |
| MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x1b0b0 |
| MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x1b0b0 |
| MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x4b01b0a8 |
| MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 |
| MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x1b0b0 |
| MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x1b0b0 |
| >; |
| }; |
| |
| pinctrl_enet2: enet2grp { |
| fsl,pins = < |
| MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 |
| MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 |
| MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 |
| MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 |
| MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 |
| MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8 |
| MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 |
| MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 |
| MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 |
| MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 |
| MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x4001b0a8 |
| MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x1b0b0 |
| MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x1b0b0 |
| >; |
| }; |
| |
| pinctrl_flexcan1: flexcan1grp{ |
| fsl,pins = < |
| MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 |
| MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 |
| MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* STBY */ |
| >; |
| }; |
| |
| pinctrl_gpmi_nand_1: gpmi-nand-1 { |
| fsl,pins = < |
| MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 |
| MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 |
| MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 |
| MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 |
| MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 |
| MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 |
| MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 |
| MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 |
| MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 |
| MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 |
| MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 |
| MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 |
| MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 |
| MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 |
| MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 |
| MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 |
| >; |
| }; |
| |
| pinctrl_i2c2: i2c2grp { |
| fsl,pins = < |
| MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0 |
| MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0 |
| >; |
| }; |
| |
| pinctrl_lcdif_dat: lcdifdatgrp { |
| fsl,pins = < |
| MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 |
| MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 |
| MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 |
| MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 |
| MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 |
| MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 |
| MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 |
| MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 |
| MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 |
| MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 |
| MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 |
| MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 |
| MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 |
| MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 |
| MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 |
| MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 |
| MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 |
| MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 |
| MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 |
| MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 |
| MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 |
| MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 |
| MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 |
| MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 |
| >; |
| }; |
| |
| pinctrl_lcdif_ctrl: lcdifctrlgrp { |
| fsl,pins = < |
| MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 |
| MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 |
| MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 |
| MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 |
| MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 |
| >; |
| }; |
| |
| pinctrl_pwm1: pmw1grp { |
| fsl,pins = < |
| MX6UL_PAD_NAND_DQS__PWM5_OUT 0x110b0 |
| >; |
| }; |
| |
| pinctrl_qspi: qspigrp { |
| fsl,pins = < |
| MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 |
| MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 |
| MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 |
| MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 |
| MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 |
| MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 |
| MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x70a1 |
| MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x70a1 |
| MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x70a1 |
| MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x70a1 |
| MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x70a1 |
| MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x70a1 |
| MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x70a1 |
| MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x70a1 |
| >; |
| }; |
| |
| pinctrl_mqs: mqsgrp { |
| fsl,pins = < |
| MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x11088 |
| MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x11088 |
| >; |
| }; |
| |
| pinctrl_sai1: sai1grp { |
| fsl,pins = < |
| MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b0 |
| MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x1b0b0 |
| MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x1b0b0 |
| MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0 |
| MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0 |
| MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 |
| MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 |
| MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 |
| >; |
| }; |
| |
| pinctrl_spdif: spdifgrp { |
| fsl,pins = < |
| MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x1b0b0 |
| MX6UL_PAD_SD1_CLK__SPDIF_IN 0x1b0b0 |
| >; |
| }; |
| |
| pinctrl_tsc: tscgrp { |
| fsl,pins = < |
| MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 |
| MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 |
| MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 |
| MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 |
| >; |
| }; |
| |
| pinctrl_adc1: adc1grp { |
| fsl,pins = < |
| MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 |
| MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b1 |
| MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b1 |
| >; |
| }; |
| |
| pinctrl_uart1: uart1grp { |
| fsl,pins = < |
| MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 |
| MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_uart2: uart2grp { |
| fsl,pins = < |
| MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 |
| MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 |
| MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 |
| MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_uart2dte: uart2dtegrp { |
| fsl,pins = < |
| MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 |
| MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 |
| MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 |
| MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_usb_otg1_id: usbotg1idgrp { |
| fsl,pins = < |
| MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 |
| >; |
| }; |
| |
| pinctrl_usb_otg1: usbotg1grp { |
| fsl,pins = < |
| MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0 |
| >; |
| }; |
| |
| pinctrl_usdhc1: usdhc1grp { |
| fsl,pins = < |
| MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 |
| MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 |
| MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 |
| MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 |
| MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 |
| MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 |
| >; |
| }; |
| |
| pinctrl_usdhc1_100mhz: usdhc1grp100mhz { |
| fsl,pins = < |
| MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 |
| MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 |
| MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 |
| MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 |
| MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 |
| MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 |
| >; |
| }; |
| |
| pinctrl_usdhc1_200mhz: usdhc1grp200mhz { |
| fsl,pins = < |
| MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 |
| MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 |
| MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 |
| MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 |
| MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 |
| MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 |
| >; |
| }; |
| |
| pinctrl_usdhc1_8bit: usdhc1_8bit_grp { |
| fsl,pins = < |
| MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 |
| MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 |
| MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 |
| MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 |
| MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 |
| MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 |
| MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 |
| MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 |
| MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 |
| MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 |
| >; |
| }; |
| |
| pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp { |
| fsl,pins = < |
| MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 |
| MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 |
| MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 |
| MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 |
| MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 |
| MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 |
| MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170b9 |
| MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170b9 |
| MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170b9 |
| MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170b9 |
| >; |
| }; |
| |
| pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp { |
| fsl,pins = < |
| MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 |
| MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 |
| MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 |
| MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 |
| MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 |
| MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 |
| MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170f9 |
| MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170f9 |
| MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170f9 |
| MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170f9 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 |
| MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 |
| MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 |
| MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 |
| MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 |
| MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 |
| >; |
| }; |
| |
| pinctrl_usdhc2_100mhz: usdhc2grp100mhz { |
| fsl,pins = < |
| MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 |
| MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 |
| MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 |
| MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 |
| MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 |
| MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 |
| >; |
| }; |
| |
| pinctrl_usdhc2_200mhz: usdhc2grp200mhz { |
| fsl,pins = < |
| MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 |
| MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 |
| MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 |
| MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 |
| MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 |
| MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 |
| >; |
| }; |
| |
| pinctrl_usdhc2_8bit: usdhc2_8bit_grp { |
| fsl,pins = < |
| MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 |
| MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 |
| MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 |
| MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 |
| MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 |
| MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 |
| MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 |
| MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 |
| MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 |
| MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 |
| >; |
| }; |
| |
| pinctrl_usdhc2_8bit_100mhz: usdhc2_8bit_100mhz_grp { |
| fsl,pins = < |
| MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 |
| MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 |
| MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 |
| MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 |
| MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 |
| MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 |
| MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 |
| MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 |
| MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 |
| MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 |
| >; |
| }; |
| |
| pinctrl_usdhc2_8bit_200mhz: usdhc2_8bit_200mhz_grp { |
| fsl,pins = < |
| MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 |
| MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 |
| MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 |
| MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 |
| MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 |
| MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 |
| MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 |
| MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 |
| MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 |
| MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 |
| >; |
| }; |
| }; |
| }; |
