| /* |
| * Copyright 2017 NXP |
| * Copyright 2019 Google LLC |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| #include <common.h> |
| #include <spl.h> |
| #include <asm/io.h> |
| #include <errno.h> |
| #include <asm/io.h> |
| #include <asm/mach-imx/iomux-v3.h> |
| //#include <asm/arch/ddr_memory_map.h> |
| #include <asm/arch/ddr.h> |
| #include <asm/arch/imx8mq_pins.h> |
| #include <asm/arch/sys_proto.h> |
| #include <power/pmic.h> |
| #include <power/bd71837.h> |
| #include <asm/arch/clock.h> |
| #include <asm/mach-imx/gpio.h> |
| #include <asm/mach-imx/mxc_i2c.h> |
| #include <fsl_esdhc.h> |
| #include <mmc.h> |
| #include "board_id.h" |
| #include "ddr/ddr.h" |
| |
| DECLARE_GLOBAL_DATA_PTR; |
| |
| void spl_dram_init(void) |
| { |
| const int board_id = get_board_id(); |
| printf("Board id: %i\n", board_id); |
| switch (board_id) { |
| case 0: |
| ddr_init(&dram_timing_kingston_4gb); |
| break; |
| case 2: |
| case 6: |
| ddr_init(&dram_timing_micron_1gb); |
| break; |
| case 3: |
| ddr_init(&dram_timing_kingston_2gb); |
| break; |
| default: |
| printf("Unknown board id, No matching DDR timings!!\n"); |
| while (1) {}; |
| } |
| } |
| |
| #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) |
| #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) |
| struct i2c_pads_info i2c_pad_info1 = { |
| .scl = { |
| .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, |
| .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, |
| .gp = IMX_GPIO_NR(5, 14), |
| }, |
| .sda = { |
| .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, |
| .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, |
| .gp = IMX_GPIO_NR(5, 15), |
| }, |
| }; |
| |
| #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) |
| #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) |
| #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) |
| |
| int board_mmc_getcd(struct mmc *mmc) |
| { |
| struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| int ret = 0; |
| |
| switch (cfg->esdhc_base) { |
| case USDHC1_BASE_ADDR: |
| ret = 1; |
| break; |
| case USDHC2_BASE_ADDR: |
| ret = !gpio_get_value(USDHC2_CD_GPIO); |
| return ret; |
| } |
| |
| return 1; |
| } |
| |
| #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ |
| PAD_CTL_FSEL2) |
| #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) |
| |
| static iomux_v3_cfg_t const usdhc1_pads[] = { |
| IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const usdhc2_pads[] = { |
| IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ |
| IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ |
| IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ |
| IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ |
| IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ |
| IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ |
| IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), |
| IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), |
| }; |
| |
| static struct fsl_esdhc_cfg usdhc_cfg[2] = { |
| {USDHC1_BASE_ADDR, 0, 8}, |
| {USDHC2_BASE_ADDR, 0, 4}, |
| }; |
| |
| int board_mmc_init(bd_t *bis) |
| { |
| int i, ret; |
| /* |
| * According to the board_mmc_init() the following map is done: |
| * (U-Boot device node) (Physical Port) |
| * mmc0 USDHC1 |
| * mmc1 USDHC2 |
| */ |
| for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
| switch (i) { |
| case 0: |
| usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); |
| gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); |
| gpio_direction_output(USDHC1_PWR_GPIO, 0); |
| udelay(500); |
| gpio_direction_output(USDHC1_PWR_GPIO, 1); |
| break; |
| case 1: |
| usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
| gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); |
| gpio_direction_output(USDHC2_PWR_GPIO, 0); |
| udelay(500); |
| gpio_direction_output(USDHC2_PWR_GPIO, 1); |
| break; |
| default: |
| printf("Warning: you configured more USDHC controllers" |
| "(%d) than supported by the board\n", i + 1); |
| return -EINVAL; |
| } |
| |
| ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
| if (ret) |
| return ret; |
| } |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_POWER |
| #define I2C_PMIC 0 |
| int power_init_board(void) |
| { |
| struct pmic *p; |
| int ret; |
| |
| ret = power_bd71837_init(I2C_PMIC); |
| if (ret) |
| printf("power init failed"); |
| |
| p = pmic_get("BD71837"); |
| pmic_probe(p); |
| |
| /* Unlock reg */ |
| pmic_reg_write(p, BD71837_REGLOCK, 0x1); |
| |
| /* Set BUCK5 output for DRAM to 1.0V */ |
| /* 0.70,0.80,0.90,1.00, 1.05,1.10,1.20,1.35 */ |
| pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x3); |
| |
| /* Set BUCK3 output for VDD_GPU_0V9 to 0.90V */ |
| /* 0.7-1.3 (10mVstep) */ |
| pmic_reg_write(p, BD71837_BUCK3_VOLT_RUN, 0x14); |
| |
| /* Set BUCK4 output for VDD_VPU_0V9 to 0.90V */ |
| /* 0.7-1.3 (10mVstep) */ |
| pmic_reg_write(p, BD71837_BUCK4_VOLT_RUN, 0x14); |
| |
| /* Set BUCK2 output for VDD_ARM_0V9 to 0.90V */ |
| /* 0.7-1.3 (10mVstep) */ |
| pmic_reg_write(p, BD71837_BUCK2_VOLT_RUN, 0x14); |
| |
| /* Set BUCK1 output for VDD_SOC_0V9 to 0.90V */ |
| /* 0.7-1.3 (10mVstep) */ |
| pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x14); |
| |
| /* lock the PMIC regs */ |
| pmic_reg_write(p, BD71837_REGLOCK, 0x11); |
| |
| return 0; |
| } |
| #endif |
| void spl_board_init(void) |
| { |
| enable_tzc380(); |
| |
| /* Adjust pmic voltage to 1.0V for 800M */ |
| setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); |
| |
| power_init_board(); |
| |
| /* DDR initialization */ |
| spl_dram_init(); |
| |
| /* Serial download mode */ |
| if (is_usb_boot()) { |
| puts("Back to ROM, SDP\n"); |
| restore_boot_params(); |
| } |
| puts("Normal Boot\n"); |
| } |
| |
| #ifdef CONFIG_SPL_LOAD_FIT |
| int board_fit_config_name_match(const char *name) |
| { |
| /* Just empty function now - can't decide what to choose */ |
| debug("%s: %s\n", __func__, name); |
| |
| return 0; |
| } |
| #endif |
| |
| void board_init_f(ulong dummy) |
| { |
| /* Clear global data */ |
| memset((void *)gd, 0, sizeof(gd_t)); |
| |
| arch_cpu_init(); |
| |
| init_uart_clk(0); |
| |
| board_early_init_f(); |
| |
| timer_init(); |
| |
| preloader_console_init(); |
| |
| /* Clear the BSS. */ |
| memset(__bss_start, 0, __bss_end - __bss_start); |
| |
| board_init_r(NULL, 0); |
| } |