| /* DO NOT EDIT THIS FILE |
| * Automatically generated by generate-def-headers.xsl |
| * DO NOT EDIT THIS FILE |
| */ |
| |
| #ifndef __BFIN_DEF_ADSP_BF538_proc__ |
| #define __BFIN_DEF_ADSP_BF538_proc__ |
| |
| #include "../mach-common/ADSP-EDN-core_def.h" |
| |
| #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ |
| #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ |
| #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ |
| #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ |
| #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ |
| #define CHIPID 0xFFC00014 |
| #define SWRST 0xFFC00100 /* Software Reset Register */ |
| #define SYSCR 0xFFC00104 /* System Configuration register */ |
| #define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ |
| #define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register 0 */ |
| #define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */ |
| #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register 0 */ |
| #define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */ |
| #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register 0 */ |
| #define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */ |
| #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ |
| #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ |
| #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ |
| #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ |
| #define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */ |
| #define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */ |
| #define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */ |
| #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ |
| #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ |
| #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ |
| #define RTC_STAT 0xFFC00300 |
| #define RTC_ICTL 0xFFC00304 |
| #define RTC_ISTAT 0xFFC00308 |
| #define RTC_SWCNT 0xFFC0030C |
| #define RTC_ALARM 0xFFC00310 |
| #define RTC_PREN 0xFFC00314 |
| #define UART0_THR 0xFFC00400 |
| #define UART0_RBR 0xFFC00400 |
| #define UART0_DLL 0xFFC00400 |
| #define UART0_DLH 0xFFC00404 |
| #define UART0_IER 0xFFC00404 |
| #define UART0_IIR 0xFFC00408 |
| #define UART0_LCR 0xFFC0040C |
| #define UART0_MCR 0xFFC00410 |
| #define UART0_LSR 0xFFC00414 |
| #define UART0_SCR 0xFFC0041C |
| #define UART0_GCTL 0xFFC00424 |
| #define UART1_THR 0xFFC02000 |
| #define UART1_RBR 0xFFC02000 |
| #define UART1_DLL 0xFFC02000 |
| #define UART1_DLH 0xFFC02004 |
| #define UART1_IER 0xFFC02004 |
| #define UART1_IIR 0xFFC02008 |
| #define UART1_LCR 0xFFC0200C |
| #define UART1_MCR 0xFFC02010 |
| #define UART1_LSR 0xFFC02014 |
| #define UART1_SCR 0xFFC0201C |
| #define UART1_GCTL 0xFFC02024 |
| #define UART2_THR 0xFFC02100 |
| #define UART2_RBR 0xFFC02100 |
| #define UART2_DLL 0xFFC02100 |
| #define UART2_DLH 0xFFC02104 |
| #define UART2_IER 0xFFC02104 |
| #define UART2_IIR 0xFFC02108 |
| #define UART2_LCR 0xFFC0210C |
| #define UART2_MCR 0xFFC02110 |
| #define UART2_LSR 0xFFC02114 |
| #define UART2_SCR 0xFFC0211C |
| #define UART2_GCTL 0xFFC02124 |
| #define SPI0_CTL 0xFFC00500 |
| #define SPI0_FLG 0xFFC00504 |
| #define SPI0_STAT 0xFFC00508 |
| #define SPI0_TDBR 0xFFC0050C |
| #define SPI0_RDBR 0xFFC00510 |
| #define SPI0_BAUD 0xFFC00514 |
| #define SPI0_SHADOW 0xFFC00518 |
| #define SPI1_CTL 0xFFC02300 |
| #define SPI1_FLG 0xFFC02304 |
| #define SPI1_STAT 0xFFC02308 |
| #define SPI1_TDBR 0xFFC0230C |
| #define SPI1_RDBR 0xFFC02310 |
| #define SPI1_BAUD 0xFFC02314 |
| #define SPI1_SHADOW 0xFFC02318 |
| #define SPI2_CTL 0xFFC02400 |
| #define SPI2_FLG 0xFFC02404 |
| #define SPI2_STAT 0xFFC02408 |
| #define SPI2_TDBR 0xFFC0240C |
| #define SPI2_RDBR 0xFFC02410 |
| #define SPI2_BAUD 0xFFC02414 |
| #define SPI2_SHADOW 0xFFC02418 |
| #define TIMER0_CONFIG 0xFFC00600 |
| #define TIMER0_COUNTER 0xFFC00604 |
| #define TIMER0_PERIOD 0xFFC00608 |
| #define TIMER0_WIDTH 0xFFC0060C |
| #define TIMER1_CONFIG 0xFFC00610 |
| #define TIMER1_COUNTER 0xFFC00614 |
| #define TIMER1_PERIOD 0xFFC00618 |
| #define TIMER1_WIDTH 0xFFC0061C |
| #define TIMER2_CONFIG 0xFFC00620 |
| #define TIMER2_COUNTER 0xFFC00624 |
| #define TIMER2_PERIOD 0xFFC00628 |
| #define TIMER2_WIDTH 0xFFC0062C |
| #define TIMER_ENABLE 0xFFC00640 |
| #define TIMER_DISABLE 0xFFC00644 |
| #define TIMER_STATUS 0xFFC00648 |
| #define SPORT0_TCR1 0xFFC00800 |
| #define SPORT0_TCR2 0xFFC00804 |
| #define SPORT0_TCLKDIV 0xFFC00808 |
| #define SPORT0_TFSDIV 0xFFC0080C |
| #define SPORT0_TX 0xFFC00810 |
| #define SPORT0_RX 0xFFC00818 |
| #define SPORT0_RCR1 0xFFC00820 |
| #define SPORT0_RCR2 0xFFC00824 |
| #define SPORT0_RCLKDIV 0xFFC00828 |
| #define SPORT0_RFSDIV 0xFFC0082C |
| #define SPORT0_STAT 0xFFC00830 |
| #define SPORT0_CHNL 0xFFC00834 |
| #define SPORT0_MCMC1 0xFFC00838 |
| #define SPORT0_MCMC2 0xFFC0083C |
| #define SPORT0_MTCS0 0xFFC00840 |
| #define SPORT0_MTCS1 0xFFC00844 |
| #define SPORT0_MTCS2 0xFFC00848 |
| #define SPORT0_MTCS3 0xFFC0084C |
| #define SPORT0_MRCS0 0xFFC00850 |
| #define SPORT0_MRCS1 0xFFC00854 |
| #define SPORT0_MRCS2 0xFFC00858 |
| #define SPORT0_MRCS3 0xFFC0085C |
| #define SPORT1_TCR1 0xFFC00900 |
| #define SPORT1_TCR2 0xFFC00904 |
| #define SPORT1_TCLKDIV 0xFFC00908 |
| #define SPORT1_TFSDIV 0xFFC0090C |
| #define SPORT1_TX 0xFFC00910 |
| #define SPORT1_RX 0xFFC00918 |
| #define SPORT1_RCR1 0xFFC00920 |
| #define SPORT1_RCR2 0xFFC00924 |
| #define SPORT1_RCLKDIV 0xFFC00928 |
| #define SPORT1_RFSDIV 0xFFC0092C |
| #define SPORT1_STAT 0xFFC00930 |
| #define SPORT1_CHNL 0xFFC00934 |
| #define SPORT1_MCMC1 0xFFC00938 |
| #define SPORT1_MCMC2 0xFFC0093C |
| #define SPORT1_MTCS0 0xFFC00940 |
| #define SPORT1_MTCS1 0xFFC00944 |
| #define SPORT1_MTCS2 0xFFC00948 |
| #define SPORT1_MTCS3 0xFFC0094C |
| #define SPORT1_MRCS0 0xFFC00950 |
| #define SPORT1_MRCS1 0xFFC00954 |
| #define SPORT1_MRCS2 0xFFC00958 |
| #define SPORT1_MRCS3 0xFFC0095C |
| #define SPORT2_TCR1 0xFFC02500 |
| #define SPORT2_TCR2 0xFFC02504 |
| #define SPORT2_TCLKDIV 0xFFC02508 |
| #define SPORT2_TFSDIV 0xFFC0250C |
| #define SPORT2_TX 0xFFC02510 |
| #define SPORT2_RX 0xFFC02518 |
| #define SPORT2_RCR1 0xFFC02520 |
| #define SPORT2_RCR2 0xFFC02524 |
| #define SPORT2_RCLKDIV 0xFFC02528 |
| #define SPORT2_RFSDIV 0xFFC0252C |
| #define SPORT2_STAT 0xFFC02530 |
| #define SPORT2_CHNL 0xFFC02534 |
| #define SPORT2_MCMC1 0xFFC02538 |
| #define SPORT2_MCMC2 0xFFC0253C |
| #define SPORT2_MTCS0 0xFFC02540 |
| #define SPORT2_MTCS1 0xFFC02544 |
| #define SPORT2_MTCS2 0xFFC02548 |
| #define SPORT2_MTCS3 0xFFC0254C |
| #define SPORT2_MRCS0 0xFFC02550 |
| #define SPORT2_MRCS1 0xFFC02554 |
| #define SPORT2_MRCS2 0xFFC02558 |
| #define SPORT2_MRCS3 0xFFC0255C |
| #define SPORT3_TCR1 0xFFC02600 |
| #define SPORT3_TCR2 0xFFC02604 |
| #define SPORT3_TCLKDIV 0xFFC02608 |
| #define SPORT3_TFSDIV 0xFFC0260C |
| #define SPORT3_TX 0xFFC02610 |
| #define SPORT3_RX 0xFFC02618 |
| #define SPORT3_RCR1 0xFFC02620 |
| #define SPORT3_RCR2 0xFFC02624 |
| #define SPORT3_RCLKDIV 0xFFC02628 |
| #define SPORT3_RFSDIV 0xFFC0262C |
| #define SPORT3_STAT 0xFFC02630 |
| #define SPORT3_CHNL 0xFFC02634 |
| #define SPORT3_MCMC1 0xFFC02638 |
| #define SPORT3_MCMC2 0xFFC0263C |
| #define SPORT3_MTCS0 0xFFC02640 |
| #define SPORT3_MTCS1 0xFFC02644 |
| #define SPORT3_MTCS2 0xFFC02648 |
| #define SPORT3_MTCS3 0xFFC0264C |
| #define SPORT3_MRCS0 0xFFC02650 |
| #define SPORT3_MRCS1 0xFFC02654 |
| #define SPORT3_MRCS2 0xFFC02658 |
| #define SPORT3_MRCS3 0xFFC0265C |
| #define PORTFIO 0xFFC00700 |
| #define PORTFIO_CLEAR 0xFFC00704 |
| #define PORTFIO_SET 0xFFC00708 |
| #define PORTFIO_TOGGLE 0xFFC0070C |
| #define PORTFIO_MASKA 0xFFC00710 |
| #define PORTFIO_MASKA_CLEAR 0xFFC00714 |
| #define PORTFIO_MASKA_SET 0xFFC00718 |
| #define PORTFIO_MASKA_TOGGLE 0xFFC0071C |
| #define PORTFIO_MASKB 0xFFC00720 |
| #define PORTFIO_MASKB_CLEAR 0xFFC00724 |
| #define PORTFIO_MASKB_SET 0xFFC00728 |
| #define PORTFIO_MASKB_TOGGLE 0xFFC0072C |
| #define PORTFIO_DIR 0xFFC00730 |
| #define PORTFIO_POLAR 0xFFC00734 |
| #define PORTFIO_EDGE 0xFFC00738 |
| #define PORTFIO_BOTH 0xFFC0073C |
| #define PORTFIO_INEN 0xFFC00740 |
| #define PORTCIO_FER 0xFFC01500 |
| #define PORTCIO 0xFFC01510 |
| #define PORTCIO_CLEAR 0xFFC01520 |
| #define PORTCIO_SET 0xFFC01530 |
| #define PORTCIO_TOGGLE 0xFFC01540 |
| #define PORTCIO_DIR 0xFFC01550 |
| #define PORTCIO_INEN 0xFFC01560 |
| #define PORTDIO_FER 0xFFC01504 |
| #define PORTDIO 0xFFC01514 |
| #define PORTDIO_CLEAR 0xFFC01524 |
| #define PORTDIO_SET 0xFFC01534 |
| #define PORTDIO_TOGGLE 0xFFC01544 |
| #define PORTDIO_DIR 0xFFC01554 |
| #define PORTDIO_INEN 0xFFC01564 |
| #define PORTEIO_FER 0xFFC01508 |
| #define PORTEIO 0xFFC01518 |
| #define PORTEIO_CLEAR 0xFFC01528 |
| #define PORTEIO_SET 0xFFC01538 |
| #define PORTEIO_TOGGLE 0xFFC01548 |
| #define PORTEIO_DIR 0xFFC01558 |
| #define PORTEIO_INEN 0xFFC01568 |
| #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ |
| #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ |
| #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ |
| #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ |
| #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ |
| #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ |
| #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ |
| #define DMA0_TC_PER 0xFFC00B0C /* Traffic Control Periods */ |
| #define DMA0_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts */ |
| #define DMA0_NEXT_DESC_PTR 0xFFC00C00 |
| #define DMA0_START_ADDR 0xFFC00C04 |
| #define DMA0_CONFIG 0xFFC00C08 |
| #define DMA0_X_COUNT 0xFFC00C10 |
| #define DMA0_X_MODIFY 0xFFC00C14 |
| #define DMA0_Y_COUNT 0xFFC00C18 |
| #define DMA0_Y_MODIFY 0xFFC00C1C |
| #define DMA0_CURR_DESC_PTR 0xFFC00C20 |
| #define DMA0_CURR_ADDR 0xFFC00C24 |
| #define DMA0_IRQ_STATUS 0xFFC00C28 |
| #define DMA0_PERIPHERAL_MAP 0xFFC00C2C |
| #define DMA0_CURR_X_COUNT 0xFFC00C30 |
| #define DMA0_CURR_Y_COUNT 0xFFC00C38 |
| #define DMA1_NEXT_DESC_PTR 0xFFC00C40 |
| #define DMA1_START_ADDR 0xFFC00C44 |
| #define DMA1_CONFIG 0xFFC00C48 |
| #define DMA1_X_COUNT 0xFFC00C50 |
| #define DMA1_X_MODIFY 0xFFC00C54 |
| #define DMA1_Y_COUNT 0xFFC00C58 |
| #define DMA1_Y_MODIFY 0xFFC00C5C |
| #define DMA1_CURR_DESC_PTR 0xFFC00C60 |
| #define DMA1_CURR_ADDR 0xFFC00C64 |
| #define DMA1_IRQ_STATUS 0xFFC00C68 |
| #define DMA1_PERIPHERAL_MAP 0xFFC00C6C |
| #define DMA1_CURR_X_COUNT 0xFFC00C70 |
| #define DMA1_CURR_Y_COUNT 0xFFC00C78 |
| #define DMA2_NEXT_DESC_PTR 0xFFC00C80 |
| #define DMA2_START_ADDR 0xFFC00C84 |
| #define DMA2_CONFIG 0xFFC00C88 |
| #define DMA2_X_COUNT 0xFFC00C90 |
| #define DMA2_X_MODIFY 0xFFC00C94 |
| #define DMA2_Y_COUNT 0xFFC00C98 |
| #define DMA2_Y_MODIFY 0xFFC00C9C |
| #define DMA2_CURR_DESC_PTR 0xFFC00CA0 |
| #define DMA2_CURR_ADDR 0xFFC00CA4 |
| #define DMA2_IRQ_STATUS 0xFFC00CA8 |
| #define DMA2_PERIPHERAL_MAP 0xFFC00CAC |
| #define DMA2_CURR_X_COUNT 0xFFC00CB0 |
| #define DMA2_CURR_Y_COUNT 0xFFC00CB8 |
| #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 |
| #define DMA3_START_ADDR 0xFFC00CC4 |
| #define DMA3_CONFIG 0xFFC00CC8 |
| #define DMA3_X_COUNT 0xFFC00CD0 |
| #define DMA3_X_MODIFY 0xFFC00CD4 |
| #define DMA3_Y_COUNT 0xFFC00CD8 |
| #define DMA3_Y_MODIFY 0xFFC00CDC |
| #define DMA3_CURR_DESC_PTR 0xFFC00CE0 |
| #define DMA3_CURR_ADDR 0xFFC00CE4 |
| #define DMA3_IRQ_STATUS 0xFFC00CE8 |
| #define DMA3_PERIPHERAL_MAP 0xFFC00CEC |
| #define DMA3_CURR_X_COUNT 0xFFC00CF0 |
| #define DMA3_CURR_Y_COUNT 0xFFC00CF8 |
| #define DMA4_NEXT_DESC_PTR 0xFFC00D00 |
| #define DMA4_START_ADDR 0xFFC00D04 |
| #define DMA4_CONFIG 0xFFC00D08 |
| #define DMA4_X_COUNT 0xFFC00D10 |
| #define DMA4_X_MODIFY 0xFFC00D14 |
| #define DMA4_Y_COUNT 0xFFC00D18 |
| #define DMA4_Y_MODIFY 0xFFC00D1C |
| #define DMA4_CURR_DESC_PTR 0xFFC00D20 |
| #define DMA4_CURR_ADDR 0xFFC00D24 |
| #define DMA4_IRQ_STATUS 0xFFC00D28 |
| #define DMA4_PERIPHERAL_MAP 0xFFC00D2C |
| #define DMA4_CURR_X_COUNT 0xFFC00D30 |
| #define DMA4_CURR_Y_COUNT 0xFFC00D38 |
| #define DMA5_NEXT_DESC_PTR 0xFFC00D40 |
| #define DMA5_START_ADDR 0xFFC00D44 |
| #define DMA5_CONFIG 0xFFC00D48 |
| #define DMA5_X_COUNT 0xFFC00D50 |
| #define DMA5_X_MODIFY 0xFFC00D54 |
| #define DMA5_Y_COUNT 0xFFC00D58 |
| #define DMA5_Y_MODIFY 0xFFC00D5C |
| #define DMA5_CURR_DESC_PTR 0xFFC00D60 |
| #define DMA5_CURR_ADDR 0xFFC00D64 |
| #define DMA5_IRQ_STATUS 0xFFC00D68 |
| #define DMA5_PERIPHERAL_MAP 0xFFC00D6C |
| #define DMA5_CURR_X_COUNT 0xFFC00D70 |
| #define DMA5_CURR_Y_COUNT 0xFFC00D78 |
| #define DMA6_NEXT_DESC_PTR 0xFFC00D80 |
| #define DMA6_START_ADDR 0xFFC00D84 |
| #define DMA6_CONFIG 0xFFC00D88 |
| #define DMA6_X_COUNT 0xFFC00D90 |
| #define DMA6_X_MODIFY 0xFFC00D94 |
| #define DMA6_Y_COUNT 0xFFC00D98 |
| #define DMA6_Y_MODIFY 0xFFC00D9C |
| #define DMA6_CURR_DESC_PTR 0xFFC00DA0 |
| #define DMA6_CURR_ADDR 0xFFC00DA4 |
| #define DMA6_IRQ_STATUS 0xFFC00DA8 |
| #define DMA6_PERIPHERAL_MAP 0xFFC00DAC |
| #define DMA6_CURR_X_COUNT 0xFFC00DB0 |
| #define DMA6_CURR_Y_COUNT 0xFFC00DB8 |
| #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 |
| #define DMA7_START_ADDR 0xFFC00DC4 |
| #define DMA7_CONFIG 0xFFC00DC8 |
| #define DMA7_X_COUNT 0xFFC00DD0 |
| #define DMA7_X_MODIFY 0xFFC00DD4 |
| #define DMA7_Y_COUNT 0xFFC00DD8 |
| #define DMA7_Y_MODIFY 0xFFC00DDC |
| #define DMA7_CURR_DESC_PTR 0xFFC00DE0 |
| #define DMA7_CURR_ADDR 0xFFC00DE4 |
| #define DMA7_IRQ_STATUS 0xFFC00DE8 |
| #define DMA7_PERIPHERAL_MAP 0xFFC00DEC |
| #define DMA7_CURR_X_COUNT 0xFFC00DF0 |
| #define DMA7_CURR_Y_COUNT 0xFFC00DF8 |
| #define DMA1_TC_PER 0xFFC01B0C /* Traffic Control Periods */ |
| #define DMA1_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts */ |
| #define DMA8_NEXT_DESC_PTR 0xFFC01C00 |
| #define DMA8_START_ADDR 0xFFC01C04 |
| #define DMA8_CONFIG 0xFFC01C08 |
| #define DMA8_X_COUNT 0xFFC01C10 |
| #define DMA8_X_MODIFY 0xFFC01C14 |
| #define DMA8_Y_COUNT 0xFFC01C18 |
| #define DMA8_Y_MODIFY 0xFFC01C1C |
| #define DMA8_CURR_DESC_PTR 0xFFC01C20 |
| #define DMA8_CURR_ADDR 0xFFC01C24 |
| #define DMA8_IRQ_STATUS 0xFFC01C28 |
| #define DMA8_PERIPHERAL_MAP 0xFFC01C2C |
| #define DMA8_CURR_X_COUNT 0xFFC01C30 |
| #define DMA8_CURR_Y_COUNT 0xFFC01C38 |
| #define DMA9_NEXT_DESC_PTR 0xFFC01C40 |
| #define DMA9_START_ADDR 0xFFC01C44 |
| #define DMA9_CONFIG 0xFFC01C48 |
| #define DMA9_X_COUNT 0xFFC01C50 |
| #define DMA9_X_MODIFY 0xFFC01C54 |
| #define DMA9_Y_COUNT 0xFFC01C58 |
| #define DMA9_Y_MODIFY 0xFFC01C5C |
| #define DMA9_CURR_DESC_PTR 0xFFC01C60 |
| #define DMA9_CURR_ADDR 0xFFC01C64 |
| #define DMA9_IRQ_STATUS 0xFFC01C68 |
| #define DMA9_PERIPHERAL_MAP 0xFFC01C6C |
| #define DMA9_CURR_X_COUNT 0xFFC01C70 |
| #define DMA9_CURR_Y_COUNT 0xFFC01C78 |
| #define DMA10_NEXT_DESC_PTR 0xFFC01C80 |
| #define DMA10_START_ADDR 0xFFC01C84 |
| #define DMA10_CONFIG 0xFFC01C88 |
| #define DMA10_X_COUNT 0xFFC01C90 |
| #define DMA10_X_MODIFY 0xFFC01C94 |
| #define DMA10_Y_COUNT 0xFFC01C98 |
| #define DMA10_Y_MODIFY 0xFFC01C9C |
| #define DMA10_CURR_DESC_PTR 0xFFC01CA0 |
| #define DMA10_CURR_ADDR 0xFFC01CA4 |
| #define DMA10_IRQ_STATUS 0xFFC01CA8 |
| #define DMA10_PERIPHERAL_MAP 0xFFC01CAC |
| #define DMA10_CURR_X_COUNT 0xFFC01CB0 |
| #define DMA10_CURR_Y_COUNT 0xFFC01CB8 |
| #define DMA11_NEXT_DESC_PTR 0xFFC01CC0 |
| #define DMA11_START_ADDR 0xFFC01CC4 |
| #define DMA11_CONFIG 0xFFC01CC8 |
| #define DMA11_X_COUNT 0xFFC01CD0 |
| #define DMA11_X_MODIFY 0xFFC01CD4 |
| #define DMA11_Y_COUNT 0xFFC01CD8 |
| #define DMA11_Y_MODIFY 0xFFC01CDC |
| #define DMA11_CURR_DESC_PTR 0xFFC01CE0 |
| #define DMA11_CURR_ADDR 0xFFC01CE4 |
| #define DMA11_IRQ_STATUS 0xFFC01CE8 |
| #define DMA11_PERIPHERAL_MAP 0xFFC01CEC |
| #define DMA11_CURR_X_COUNT 0xFFC01CF0 |
| #define DMA11_CURR_Y_COUNT 0xFFC01CF8 |
| #define DMA12_NEXT_DESC_PTR 0xFFC01D00 |
| #define DMA12_START_ADDR 0xFFC01D04 |
| #define DMA12_CONFIG 0xFFC01D08 |
| #define DMA12_X_COUNT 0xFFC01D10 |
| #define DMA12_X_MODIFY 0xFFC01D14 |
| #define DMA12_Y_COUNT 0xFFC01D18 |
| #define DMA12_Y_MODIFY 0xFFC01D1C |
| #define DMA12_CURR_DESC_PTR 0xFFC01D20 |
| #define DMA12_CURR_ADDR 0xFFC01D24 |
| #define DMA12_IRQ_STATUS 0xFFC01D28 |
| #define DMA12_PERIPHERAL_MAP 0xFFC01D2C |
| #define DMA12_CURR_X_COUNT 0xFFC01D30 |
| #define DMA12_CURR_Y_COUNT 0xFFC01D38 |
| #define DMA13_NEXT_DESC_PTR 0xFFC01D40 |
| #define DMA13_START_ADDR 0xFFC01D44 |
| #define DMA13_CONFIG 0xFFC01D48 |
| #define DMA13_X_COUNT 0xFFC01D50 |
| #define DMA13_X_MODIFY 0xFFC01D54 |
| #define DMA13_Y_COUNT 0xFFC01D58 |
| #define DMA13_Y_MODIFY 0xFFC01D5C |
| #define DMA13_CURR_DESC_PTR 0xFFC01D60 |
| #define DMA13_CURR_ADDR 0xFFC01D64 |
| #define DMA13_IRQ_STATUS 0xFFC01D68 |
| #define DMA13_PERIPHERAL_MAP 0xFFC01D6C |
| #define DMA13_CURR_X_COUNT 0xFFC01D70 |
| #define DMA13_CURR_Y_COUNT 0xFFC01D78 |
| #define DMA14_NEXT_DESC_PTR 0xFFC01D80 |
| #define DMA14_START_ADDR 0xFFC01D84 |
| #define DMA14_CONFIG 0xFFC01D88 |
| #define DMA14_X_COUNT 0xFFC01D90 |
| #define DMA14_X_MODIFY 0xFFC01D94 |
| #define DMA14_Y_COUNT 0xFFC01D98 |
| #define DMA14_Y_MODIFY 0xFFC01D9C |
| #define DMA14_CURR_DESC_PTR 0xFFC01DA0 |
| #define DMA14_CURR_ADDR 0xFFC01DA4 |
| #define DMA14_IRQ_STATUS 0xFFC01DA8 |
| #define DMA14_PERIPHERAL_MAP 0xFFC01DAC |
| #define DMA14_CURR_X_COUNT 0xFFC01DB0 |
| #define DMA14_CURR_Y_COUNT 0xFFC01DB8 |
| #define DMA15_NEXT_DESC_PTR 0xFFC01DC0 |
| #define DMA15_START_ADDR 0xFFC01DC4 |
| #define DMA15_CONFIG 0xFFC01DC8 |
| #define DMA15_X_COUNT 0xFFC01DD0 |
| #define DMA15_X_MODIFY 0xFFC01DD4 |
| #define DMA15_Y_COUNT 0xFFC01DD8 |
| #define DMA15_Y_MODIFY 0xFFC01DDC |
| #define DMA15_CURR_DESC_PTR 0xFFC01DE0 |
| #define DMA15_CURR_ADDR 0xFFC01DE4 |
| #define DMA15_IRQ_STATUS 0xFFC01DE8 |
| #define DMA15_PERIPHERAL_MAP 0xFFC01DEC |
| #define DMA15_CURR_X_COUNT 0xFFC01DF0 |
| #define DMA15_CURR_Y_COUNT 0xFFC01DF8 |
| #define DMA16_NEXT_DESC_PTR 0xFFC01E00 |
| #define DMA16_START_ADDR 0xFFC01E04 |
| #define DMA16_CONFIG 0xFFC01E08 |
| #define DMA16_X_COUNT 0xFFC01E10 |
| #define DMA16_X_MODIFY 0xFFC01E14 |
| #define DMA16_Y_COUNT 0xFFC01E18 |
| #define DMA16_Y_MODIFY 0xFFC01E1C |
| #define DMA16_CURR_DESC_PTR 0xFFC01E20 |
| #define DMA16_CURR_ADDR 0xFFC01E24 |
| #define DMA16_IRQ_STATUS 0xFFC01E28 |
| #define DMA16_PERIPHERAL_MAP 0xFFC01E2C |
| #define DMA16_CURR_X_COUNT 0xFFC01E30 |
| #define DMA16_CURR_Y_COUNT 0xFFC01E38 |
| #define DMA17_NEXT_DESC_PTR 0xFFC01E40 |
| #define DMA17_START_ADDR 0xFFC01E44 |
| #define DMA17_CONFIG 0xFFC01E48 |
| #define DMA17_X_COUNT 0xFFC01E50 |
| #define DMA17_X_MODIFY 0xFFC01E54 |
| #define DMA17_Y_COUNT 0xFFC01E58 |
| #define DMA17_Y_MODIFY 0xFFC01E5C |
| #define DMA17_CURR_DESC_PTR 0xFFC01E60 |
| #define DMA17_CURR_ADDR 0xFFC01E64 |
| #define DMA17_IRQ_STATUS 0xFFC01E68 |
| #define DMA17_PERIPHERAL_MAP 0xFFC01E6C |
| #define DMA17_CURR_X_COUNT 0xFFC01E70 |
| #define DMA17_CURR_Y_COUNT 0xFFC01E78 |
| #define DMA18_NEXT_DESC_PTR 0xFFC01E80 |
| #define DMA18_START_ADDR 0xFFC01E84 |
| #define DMA18_CONFIG 0xFFC01E88 |
| #define DMA18_X_COUNT 0xFFC01E90 |
| #define DMA18_X_MODIFY 0xFFC01E94 |
| #define DMA18_Y_COUNT 0xFFC01E98 |
| #define DMA18_Y_MODIFY 0xFFC01E9C |
| #define DMA18_CURR_DESC_PTR 0xFFC01EA0 |
| #define DMA18_CURR_ADDR 0xFFC01EA4 |
| #define DMA18_IRQ_STATUS 0xFFC01EA8 |
| #define DMA18_PERIPHERAL_MAP 0xFFC01EAC |
| #define DMA18_CURR_X_COUNT 0xFFC01EB0 |
| #define DMA18_CURR_Y_COUNT 0xFFC01EB8 |
| #define DMA19_NEXT_DESC_PTR 0xFFC01EC0 |
| #define DMA19_START_ADDR 0xFFC01EC4 |
| #define DMA19_CONFIG 0xFFC01EC8 |
| #define DMA19_X_COUNT 0xFFC01ED0 |
| #define DMA19_X_MODIFY 0xFFC01ED4 |
| #define DMA19_Y_COUNT 0xFFC01ED8 |
| #define DMA19_Y_MODIFY 0xFFC01EDC |
| #define DMA19_CURR_DESC_PTR 0xFFC01EE0 |
| #define DMA19_CURR_ADDR 0xFFC01EE4 |
| #define DMA19_IRQ_STATUS 0xFFC01EE8 |
| #define DMA19_PERIPHERAL_MAP 0xFFC01EEC |
| #define DMA19_CURR_X_COUNT 0xFFC01EF0 |
| #define DMA19_CURR_Y_COUNT 0xFFC01EF8 |
| #define MDMA0_D0_NEXT_DESC_PTR 0xFFC00E00 |
| #define MDMA0_D0_START_ADDR 0xFFC00E04 |
| #define MDMA0_D0_CONFIG 0xFFC00E08 |
| #define MDMA0_D0_X_COUNT 0xFFC00E10 |
| #define MDMA0_D0_X_MODIFY 0xFFC00E14 |
| #define MDMA0_D0_Y_COUNT 0xFFC00E18 |
| #define MDMA0_D0_Y_MODIFY 0xFFC00E1C |
| #define MDMA0_D0_CURR_DESC_PTR 0xFFC00E20 |
| #define MDMA0_D0_CURR_ADDR 0xFFC00E24 |
| #define MDMA0_D0_IRQ_STATUS 0xFFC00E28 |
| #define MDMA0_D0_PERIPHERAL_MAP 0xFFC00E2C |
| #define MDMA0_D0_CURR_X_COUNT 0xFFC00E30 |
| #define MDMA0_D0_CURR_Y_COUNT 0xFFC00E38 |
| #define MDMA0_S0_NEXT_DESC_PTR 0xFFC00E40 |
| #define MDMA0_S0_START_ADDR 0xFFC00E44 |
| #define MDMA0_S0_CONFIG 0xFFC00E48 |
| #define MDMA0_S0_X_COUNT 0xFFC00E50 |
| #define MDMA0_S0_X_MODIFY 0xFFC00E54 |
| #define MDMA0_S0_Y_COUNT 0xFFC00E58 |
| #define MDMA0_S0_Y_MODIFY 0xFFC00E5C |
| #define MDMA0_S0_CURR_DESC_PTR 0xFFC00E60 |
| #define MDMA0_S0_CURR_ADDR 0xFFC00E64 |
| #define MDMA0_S0_IRQ_STATUS 0xFFC00E68 |
| #define MDMA0_S0_PERIPHERAL_MAP 0xFFC00E6C |
| #define MDMA0_S0_CURR_X_COUNT 0xFFC00E70 |
| #define MDMA0_S0_CURR_Y_COUNT 0xFFC00E78 |
| #define MDMA0_D1_NEXT_DESC_PTR 0xFFC00E80 |
| #define MDMA0_D1_START_ADDR 0xFFC00E84 |
| #define MDMA0_D1_CONFIG 0xFFC00E88 |
| #define MDMA0_D1_X_COUNT 0xFFC00E90 |
| #define MDMA0_D1_X_MODIFY 0xFFC00E94 |
| #define MDMA0_D1_Y_COUNT 0xFFC00E98 |
| #define MDMA0_D1_Y_MODIFY 0xFFC00E9C |
| #define MDMA0_D1_CURR_DESC_PTR 0xFFC00EA0 |
| #define MDMA0_D1_CURR_ADDR 0xFFC00EA4 |
| #define MDMA0_D1_IRQ_STATUS 0xFFC00EA8 |
| #define MDMA0_D1_PERIPHERAL_MAP 0xFFC00EAC |
| #define MDMA0_D1_CURR_X_COUNT 0xFFC00EB0 |
| #define MDMA0_D1_CURR_Y_COUNT 0xFFC00EB8 |
| #define MDMA0_S1_NEXT_DESC_PTR 0xFFC00EC0 |
| #define MDMA0_S1_START_ADDR 0xFFC00EC4 |
| #define MDMA0_S1_CONFIG 0xFFC00EC8 |
| #define MDMA0_S1_X_COUNT 0xFFC00ED0 |
| #define MDMA0_S1_X_MODIFY 0xFFC00ED4 |
| #define MDMA0_S1_Y_COUNT 0xFFC00ED8 |
| #define MDMA0_S1_Y_MODIFY 0xFFC00EDC |
| #define MDMA0_S1_CURR_DESC_PTR 0xFFC00EE0 |
| #define MDMA0_S1_CURR_ADDR 0xFFC00EE4 |
| #define MDMA0_S1_IRQ_STATUS 0xFFC00EE8 |
| #define MDMA0_S1_PERIPHERAL_MAP 0xFFC00EEC |
| #define MDMA0_S1_CURR_X_COUNT 0xFFC00EF0 |
| #define MDMA0_S1_CURR_Y_COUNT 0xFFC00EF8 |
| #define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 |
| #define MDMA1_D0_START_ADDR 0xFFC01F04 |
| #define MDMA1_D0_CONFIG 0xFFC01F08 |
| #define MDMA1_D0_X_COUNT 0xFFC01F10 |
| #define MDMA1_D0_X_MODIFY 0xFFC01F14 |
| #define MDMA1_D0_Y_COUNT 0xFFC01F18 |
| #define MDMA1_D0_Y_MODIFY 0xFFC01F1C |
| #define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 |
| #define MDMA1_D0_CURR_ADDR 0xFFC01F24 |
| #define MDMA1_D0_IRQ_STATUS 0xFFC01F28 |
| #define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C |
| #define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 |
| #define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 |
| #define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 |
| #define MDMA1_S0_START_ADDR 0xFFC01F44 |
| #define MDMA1_S0_CONFIG 0xFFC01F48 |
| #define MDMA1_S0_X_COUNT 0xFFC01F50 |
| #define MDMA1_S0_X_MODIFY 0xFFC01F54 |
| #define MDMA1_S0_Y_COUNT 0xFFC01F58 |
| #define MDMA1_S0_Y_MODIFY 0xFFC01F5C |
| #define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 |
| #define MDMA1_S0_CURR_ADDR 0xFFC01F64 |
| #define MDMA1_S0_IRQ_STATUS 0xFFC01F68 |
| #define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C |
| #define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 |
| #define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 |
| #define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 |
| #define MDMA1_D1_START_ADDR 0xFFC01F84 |
| #define MDMA1_D1_CONFIG 0xFFC01F88 |
| #define MDMA1_D1_X_COUNT 0xFFC01F90 |
| #define MDMA1_D1_X_MODIFY 0xFFC01F94 |
| #define MDMA1_D1_Y_COUNT 0xFFC01F98 |
| #define MDMA1_D1_Y_MODIFY 0xFFC01F9C |
| #define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 |
| #define MDMA1_D1_CURR_ADDR 0xFFC01FA4 |
| #define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 |
| #define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC |
| #define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 |
| #define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 |
| #define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 |
| #define MDMA1_S1_START_ADDR 0xFFC01FC4 |
| #define MDMA1_S1_CONFIG 0xFFC01FC8 |
| #define MDMA1_S1_X_COUNT 0xFFC01FD0 |
| #define MDMA1_S1_X_MODIFY 0xFFC01FD4 |
| #define MDMA1_S1_Y_COUNT 0xFFC01FD8 |
| #define MDMA1_S1_Y_MODIFY 0xFFC01FDC |
| #define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 |
| #define MDMA1_S1_CURR_ADDR 0xFFC01FE4 |
| #define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 |
| #define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC |
| #define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 |
| #define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 |
| #define PPI_CONTROL 0xFFC01000 |
| #define PPI_STATUS 0xFFC01004 |
| #define PPI_DELAY 0xFFC0100C |
| #define PPI_COUNT 0xFFC01008 |
| #define PPI_FRAME 0xFFC01010 |
| #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ |
| #define TWI0_CONTROL 0xFFC01404 /* TWIO Master Internal Time Reference Register */ |
| #define TWI0_SLAVE_CTRL 0xFFC01408 /* Slave Mode Control Register */ |
| #define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ |
| #define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ |
| #define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ |
| #define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ |
| #define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ |
| #define TWI0_INT_STAT 0xFFC01420 /* TWIO Master Interrupt Register */ |
| #define TWI0_INT_MASK 0xFFC01424 /* TWIO Master Interrupt Mask Register */ |
| #define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ |
| #define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ |
| #define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ |
| #define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ |
| #define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ |
| #define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ |
| #define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */ |
| #define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */ |
| #define TWI1_SLAVE_CTRL 0xFFC02208 /* Slave Mode Control Register */ |
| #define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */ |
| #define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */ |
| #define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */ |
| #define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */ |
| #define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */ |
| #define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */ |
| #define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */ |
| #define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */ |
| #define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */ |
| #define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */ |
| #define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */ |
| #define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */ |
| #define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */ |
| #define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */ |
| #define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */ |
| #define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */ |
| #define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */ |
| #define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */ |
| #define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */ |
| #define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */ |
| #define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */ |
| #define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */ |
| #define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */ |
| #define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */ |
| #define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */ |
| #define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */ |
| #define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */ |
| #define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */ |
| #define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */ |
| #define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */ |
| #define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */ |
| #define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */ |
| #define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */ |
| #define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */ |
| #define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */ |
| #define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */ |
| #define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */ |
| #define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */ |
| #define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */ |
| #define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */ |
| #define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */ |
| #define CAN_DEBUG 0xFFC02A88 /* Config register */ |
| #define CAN_STATUS 0xFFC02A8C /* Global Status Register */ |
| #define CAN_CEC 0xFFC02A90 /* Error Counter Register */ |
| #define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */ |
| #define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */ |
| #define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */ |
| #define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */ |
| #define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */ |
| #define CAN_VERSION 0xFFC02AA8 /* Version Code Register */ |
| #define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */ |
| #define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */ |
| #define CAN_ESR 0xFFC02AB4 /* Error Status Register */ |
| #define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */ |
| #define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */ |
| #define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */ |
| #define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */ |
| #define CAN_VERSION2 0xFFC02AD4 /* Version Code Register 2 */ |
| #define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */ |
| #define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */ |
| #define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */ |
| #define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */ |
| #define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */ |
| #define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */ |
| #define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */ |
| #define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */ |
| #define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */ |
| #define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */ |
| #define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */ |
| #define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */ |
| #define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */ |
| #define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */ |
| #define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */ |
| #define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */ |
| #define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */ |
| #define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */ |
| #define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */ |
| #define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */ |
| #define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */ |
| #define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */ |
| #define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */ |
| #define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */ |
| #define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */ |
| #define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */ |
| #define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */ |
| #define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */ |
| #define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */ |
| #define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */ |
| #define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */ |
| #define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */ |
| #define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */ |
| #define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */ |
| #define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */ |
| #define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */ |
| #define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */ |
| #define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */ |
| #define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */ |
| #define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */ |
| #define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */ |
| #define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */ |
| #define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */ |
| #define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */ |
| #define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */ |
| #define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */ |
| #define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */ |
| #define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */ |
| #define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */ |
| #define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */ |
| #define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */ |
| #define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */ |
| #define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */ |
| #define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */ |
| #define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */ |
| #define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */ |
| #define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */ |
| #define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */ |
| #define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */ |
| #define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */ |
| #define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */ |
| #define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */ |
| #define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */ |
| #define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */ |
| #define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */ |
| #define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */ |
| #define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */ |
| #define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */ |
| #define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */ |
| #define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */ |
| #define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */ |
| #define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */ |
| #define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */ |
| #define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */ |
| #define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */ |
| #define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */ |
| #define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */ |
| #define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */ |
| #define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */ |
| #define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */ |
| #define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */ |
| #define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */ |
| #define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */ |
| #define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */ |
| #define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */ |
| #define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */ |
| #define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */ |
| #define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */ |
| #define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */ |
| #define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */ |
| #define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */ |
| #define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */ |
| #define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */ |
| #define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */ |
| #define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */ |
| #define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */ |
| #define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */ |
| #define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */ |
| #define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */ |
| #define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */ |
| #define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */ |
| #define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */ |
| #define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */ |
| #define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */ |
| #define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */ |
| #define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */ |
| #define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */ |
| #define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */ |
| #define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */ |
| #define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */ |
| #define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */ |
| #define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */ |
| #define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */ |
| #define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */ |
| #define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */ |
| #define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */ |
| #define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */ |
| #define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */ |
| #define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */ |
| #define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */ |
| #define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */ |
| #define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */ |
| #define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */ |
| #define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */ |
| #define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */ |
| #define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */ |
| #define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */ |
| #define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */ |
| #define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */ |
| #define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */ |
| #define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */ |
| #define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */ |
| #define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */ |
| #define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */ |
| #define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */ |
| #define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */ |
| #define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */ |
| #define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */ |
| #define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */ |
| #define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */ |
| #define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */ |
| #define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */ |
| #define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */ |
| #define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */ |
| #define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */ |
| #define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */ |
| #define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */ |
| #define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */ |
| #define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */ |
| #define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */ |
| #define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */ |
| #define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */ |
| #define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */ |
| #define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */ |
| #define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */ |
| #define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */ |
| #define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */ |
| #define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */ |
| #define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */ |
| #define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */ |
| #define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */ |
| #define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */ |
| #define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */ |
| #define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */ |
| #define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */ |
| #define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */ |
| #define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */ |
| #define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */ |
| #define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */ |
| #define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */ |
| #define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */ |
| #define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */ |
| #define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */ |
| #define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */ |
| #define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */ |
| #define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */ |
| #define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */ |
| #define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */ |
| #define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */ |
| #define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */ |
| #define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */ |
| #define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */ |
| #define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */ |
| #define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */ |
| #define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */ |
| #define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */ |
| #define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */ |
| #define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */ |
| #define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */ |
| #define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */ |
| #define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */ |
| #define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */ |
| #define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */ |
| #define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */ |
| #define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */ |
| #define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */ |
| #define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */ |
| #define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */ |
| #define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */ |
| #define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */ |
| #define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */ |
| #define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */ |
| #define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */ |
| #define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */ |
| #define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */ |
| #define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */ |
| #define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */ |
| #define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */ |
| #define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */ |
| #define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */ |
| #define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */ |
| #define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */ |
| #define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */ |
| #define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */ |
| #define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */ |
| #define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */ |
| #define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */ |
| #define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */ |
| #define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */ |
| #define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */ |
| #define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */ |
| #define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */ |
| #define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */ |
| #define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */ |
| #define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */ |
| #define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */ |
| #define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */ |
| #define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */ |
| #define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */ |
| #define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */ |
| #define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */ |
| #define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */ |
| #define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */ |
| #define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */ |
| #define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */ |
| #define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */ |
| #define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */ |
| #define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */ |
| #define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */ |
| #define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */ |
| #define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */ |
| #define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */ |
| #define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */ |
| #define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */ |
| #define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */ |
| #define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */ |
| #define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */ |
| #define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */ |
| #define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */ |
| #define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */ |
| #define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */ |
| #define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */ |
| #define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */ |
| #define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */ |
| #define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */ |
| #define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */ |
| #define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */ |
| #define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */ |
| #define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */ |
| #define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */ |
| #define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */ |
| #define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */ |
| #define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */ |
| #define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */ |
| #define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */ |
| #define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */ |
| #define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */ |
| #define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */ |
| #define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */ |
| #define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */ |
| #define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */ |
| #define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */ |
| #define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */ |
| #define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */ |
| #define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */ |
| #define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */ |
| #define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */ |
| #define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */ |
| #define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */ |
| #define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */ |
| #define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */ |
| #define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */ |
| #define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */ |
| #define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */ |
| #define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */ |
| #define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */ |
| #define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */ |
| #define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */ |
| #define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */ |
| #define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */ |
| #define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */ |
| #define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */ |
| #define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */ |
| #define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */ |
| #define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */ |
| #define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */ |
| #define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */ |
| #define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */ |
| #define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */ |
| #define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */ |
| #define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */ |
| #define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */ |
| #define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */ |
| #define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */ |
| #define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */ |
| #define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */ |
| #define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */ |
| #define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */ |
| #define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */ |
| #define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */ |
| #define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */ |
| #define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */ |
| #define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */ |
| #define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */ |
| #define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */ |
| #define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */ |
| #define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */ |
| #define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */ |
| #define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */ |
| #define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */ |
| |
| #define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ |
| #define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) |
| #define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) |
| #define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ |
| #define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) |
| #define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) |
| #define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ |
| #define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) |
| #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) |
| |
| #endif /* __BFIN_DEF_ADSP_BF538_proc__ */ |
