| /* |
| * Copyright 2013-2016 Freescale Semiconductor, Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| */ |
| |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include "skeleton.dtsi" |
| #include "imx6sl-pinfunc.h" |
| #include <dt-bindings/clock/imx6sl-clock.h> |
| |
| / { |
| aliases { |
| ethernet0 = &fec; |
| gpio0 = &gpio1; |
| gpio1 = &gpio2; |
| gpio2 = &gpio3; |
| gpio3 = &gpio4; |
| gpio4 = &gpio5; |
| mmc0 = &usdhc1; |
| mmc1 = &usdhc2; |
| mmc2 = &usdhc3; |
| mmc3 = &usdhc4; |
| serial0 = &uart1; |
| serial1 = &uart2; |
| serial2 = &uart3; |
| serial3 = &uart4; |
| serial4 = &uart5; |
| spi0 = &ecspi1; |
| spi1 = &ecspi2; |
| spi2 = &ecspi3; |
| spi3 = &ecspi4; |
| usbphy0 = &usbphy1; |
| usbphy1 = &usbphy2; |
| usb0 = &usbotg1; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| compatible = "arm,cortex-a9"; |
| device_type = "cpu"; |
| reg = <0x0>; |
| next-level-cache = <&L2>; |
| operating-points = < |
| /* kHz uV */ |
| 996000 1275000 |
| 792000 1175000 |
| 396000 975000 |
| >; |
| fsl,soc-operating-points = < |
| /* ARM kHz SOC-PU uV */ |
| 996000 1225000 |
| 792000 1175000 |
| 396000 1175000 |
| >; |
| clock-latency = <61036>; /* two CLK32 periods */ |
| clocks = <&clks IMX6SL_CLK_ARM>, |
| <&clks IMX6SL_CLK_PLL2_PFD2>, |
| <&clks IMX6SL_CLK_STEP>, |
| <&clks IMX6SL_CLK_PLL1_SW>, |
| <&clks IMX6SL_CLK_PLL1_SYS>, |
| <&clks IMX6SL_CLK_PLL1>, |
| <&clks IMX6SL_PLL1_BYPASS>, |
| <&clks IMX6SL_PLL1_BYPASS_SRC>; |
| clock-names = "arm", "pll2_pfd2_396m", "step", |
| "pll1_sw", "pll1_sys", "pll1", "pll1_bypass", |
| "pll1_bypass_src"; |
| arm-supply = <®_arm>; |
| pu-supply = <®_pu>; |
| soc-supply = <®_soc>; |
| }; |
| }; |
| |
| reserved-memory { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| /* global autoconfigured region for contiguous allocations */ |
| linux,cma { |
| compatible = "shared-dma-pool"; |
| reusable; |
| size = <0x14000000>; |
| linux,cma-default; |
| }; |
| }; |
| |
| intc: interrupt-controller@00a01000 { |
| compatible = "arm,cortex-a9-gic"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0x00a01000 0x1000>, |
| <0x00a00100 0x100>; |
| interrupt-parent = <&intc>; |
| }; |
| |
| clocks { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ckil { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32768>; |
| }; |
| |
| osc { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <24000000>; |
| }; |
| }; |
| |
| reg_vbus_wakeup: usb_vbus_wakeup { |
| compatible = "fsl,imx6-dummy-ldo2p5"; |
| }; |
| |
| soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "simple-bus"; |
| interrupt-parent = <&gpc>; |
| ranges; |
| |
| busfreq { /* BUSFREQ */ |
| compatible = "fsl,imx_busfreq"; |
| clocks = <&clks IMX6SL_CLK_PLL2_BUS>, <&clks IMX6SL_CLK_PLL2_PFD2>, |
| <&clks IMX6SL_CLK_PLL2_198M>, <&clks IMX6SL_CLK_ARM>, |
| <&clks IMX6SL_CLK_PLL3_USB_OTG>, <&clks IMX6SL_CLK_PERIPH>, |
| <&clks IMX6SL_CLK_PRE_PERIPH_SEL>, <&clks IMX6SL_CLK_PERIPH_CLK2_PODF>, |
| <&clks IMX6SL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SL_CLK_OSC>, |
| <&clks IMX6SL_CLK_PLL1_SYS>, <&clks IMX6SL_CLK_PERIPH2>, |
| <&clks IMX6SL_CLK_AHB>, <&clks IMX6SL_CLK_OCRAM_PODF>, |
| <&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PRE_PERIPH2_SEL>, |
| <&clks IMX6SL_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SL_CLK_PERIPH2_CLK2_PODF>, |
| <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_PLL2_BYPASS_SRC>, <&clks IMX6SL_PLL2_BYPASS>, |
| <&clks IMX6SL_CLK_PLL2>, <&clks IMX6SL_CLK_PLL1>, <&clks IMX6SL_PLL1_BYPASS>, |
| <&clks IMX6SL_PLL1_BYPASS_SRC>; |
| clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", |
| "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb", |
| "ocram", "pll1_sw", "periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step", "pll2_bypass_src", |
| "pll2_bypass", "pll2", "pll1", "pll1_bypass", "pll1_bypass_src"; |
| fsl,max_ddr_freq = <400000000>; |
| }; |
| |
| ocrams: sram@00900000 { |
| compatible = "fsl,lpm-sram"; |
| reg = <0x00900000 0x4000>; |
| clocks = <&clks IMX6SL_CLK_OCRAM>; |
| }; |
| |
| ocrams_ddr: sram@00904000 { |
| compatible = "fsl,ddr-lpm-sram"; |
| reg = <0x00904000 0x1000>; |
| clocks = <&clks IMX6SL_CLK_OCRAM>; |
| }; |
| |
| ocram: sram@00905000 { |
| compatible = "mmio-sram"; |
| reg = <0x00905000 0x1B000>; |
| clocks = <&clks IMX6SL_CLK_OCRAM>; |
| }; |
| |
| L2: l2-cache@00a02000 { |
| compatible = "arm,pl310-cache"; |
| reg = <0x00a02000 0x1000>; |
| interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; |
| cache-unified; |
| cache-level = <2>; |
| arm,tag-latency = <4 2 3>; |
| arm,data-latency = <4 2 3>; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a9-pmu"; |
| interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| aips1: aips-bus@02000000 { |
| compatible = "fsl,aips-bus", "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x02000000 0x100000>; |
| ranges; |
| |
| spba: spba-bus@02000000 { |
| compatible = "fsl,spba-bus", "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x02000000 0x40000>; |
| ranges; |
| |
| spdif: spdif@02004000 { |
| compatible = "fsl,imx6sl-spdif", |
| "fsl,imx35-spdif"; |
| reg = <0x02004000 0x4000>; |
| interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&sdma 14 18 0>, |
| <&sdma 15 18 0>; |
| dma-names = "rx", "tx"; |
| clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>, |
| <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>, |
| <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>, |
| <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>, |
| <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>; |
| clock-names = "core", "rxtx0", |
| "rxtx1", "rxtx2", |
| "rxtx3", "rxtx4", |
| "rxtx5", "rxtx6", |
| "rxtx7", "dma"; |
| status = "disabled"; |
| }; |
| |
| ecspi1: ecspi@02008000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; |
| reg = <0x02008000 0x4000>; |
| interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_ECSPI1>, |
| <&clks IMX6SL_CLK_ECSPI1>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| ecspi2: ecspi@0200c000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; |
| reg = <0x0200c000 0x4000>; |
| interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_ECSPI2>, |
| <&clks IMX6SL_CLK_ECSPI2>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| ecspi3: ecspi@02010000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; |
| reg = <0x02010000 0x4000>; |
| interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_ECSPI3>, |
| <&clks IMX6SL_CLK_ECSPI3>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| ecspi4: ecspi@02014000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; |
| reg = <0x02014000 0x4000>; |
| interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_ECSPI4>, |
| <&clks IMX6SL_CLK_ECSPI4>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| uart5: serial@02018000 { |
| compatible = "fsl,imx6sl-uart", |
| "fsl,imx6q-uart", "fsl,imx21-uart"; |
| reg = <0x02018000 0x4000>; |
| interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_UART>, |
| <&clks IMX6SL_CLK_UART_SERIAL>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@02020000 { |
| compatible = "fsl,imx6sl-uart", |
| "fsl,imx6q-uart", "fsl,imx21-uart"; |
| reg = <0x02020000 0x4000>; |
| interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_UART>, |
| <&clks IMX6SL_CLK_UART_SERIAL>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@02024000 { |
| compatible = "fsl,imx6sl-uart", |
| "fsl,imx6q-uart", "fsl,imx21-uart"; |
| reg = <0x02024000 0x4000>; |
| interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_UART>, |
| <&clks IMX6SL_CLK_UART_SERIAL>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| ssi1: ssi@02028000 { |
| #sound-dai-cells = <0>; |
| compatible = "fsl,imx6sl-ssi", |
| "fsl,imx51-ssi"; |
| reg = <0x02028000 0x4000>; |
| interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_SSI1_IPG>, |
| <&clks IMX6SL_CLK_SSI1>; |
| clock-names = "ipg", "baud"; |
| dmas = <&sdma 37 22 0>, |
| <&sdma 38 22 0>; |
| dma-names = "rx", "tx"; |
| fsl,fifo-depth = <15>; |
| status = "disabled"; |
| }; |
| |
| ssi2: ssi@0202c000 { |
| #sound-dai-cells = <0>; |
| compatible = "fsl,imx6sl-ssi", |
| "fsl,imx51-ssi"; |
| reg = <0x0202c000 0x4000>; |
| interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_SSI2_IPG>, |
| <&clks IMX6SL_CLK_SSI2>; |
| clock-names = "ipg", "baud"; |
| dmas = <&sdma 41 22 0>, |
| <&sdma 42 22 0>; |
| dma-names = "rx", "tx"; |
| fsl,fifo-depth = <15>; |
| status = "disabled"; |
| }; |
| |
| ssi3: ssi@02030000 { |
| #sound-dai-cells = <0>; |
| compatible = "fsl,imx6sl-ssi", |
| "fsl,imx51-ssi"; |
| reg = <0x02030000 0x4000>; |
| interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_SSI3_IPG>, |
| <&clks IMX6SL_CLK_SSI3>; |
| clock-names = "ipg", "baud"; |
| dmas = <&sdma 45 22 0>, |
| <&sdma 46 22 0>; |
| dma-names = "rx", "tx"; |
| fsl,fifo-depth = <15>; |
| status = "disabled"; |
| }; |
| |
| uart3: serial@02034000 { |
| compatible = "fsl,imx6sl-uart", |
| "fsl,imx6q-uart", "fsl,imx21-uart"; |
| reg = <0x02034000 0x4000>; |
| interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_UART>, |
| <&clks IMX6SL_CLK_UART_SERIAL>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@02038000 { |
| compatible = "fsl,imx6sl-uart", |
| "fsl,imx6q-uart", "fsl,imx21-uart"; |
| reg = <0x02038000 0x4000>; |
| interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_UART>, |
| <&clks IMX6SL_CLK_UART_SERIAL>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| }; |
| |
| pwm1: pwm@02080000 { |
| #pwm-cells = <2>; |
| compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; |
| reg = <0x02080000 0x4000>; |
| interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_PWM1>, |
| <&clks IMX6SL_CLK_PWM1>; |
| clock-names = "ipg", "per"; |
| }; |
| |
| pwm2: pwm@02084000 { |
| #pwm-cells = <2>; |
| compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; |
| reg = <0x02084000 0x4000>; |
| interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_PWM2>, |
| <&clks IMX6SL_CLK_PWM2>; |
| clock-names = "ipg", "per"; |
| }; |
| |
| pwm3: pwm@02088000 { |
| #pwm-cells = <2>; |
| compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; |
| reg = <0x02088000 0x4000>; |
| interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_PWM3>, |
| <&clks IMX6SL_CLK_PWM3>; |
| clock-names = "ipg", "per"; |
| }; |
| |
| pwm4: pwm@0208c000 { |
| #pwm-cells = <2>; |
| compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; |
| reg = <0x0208c000 0x4000>; |
| interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_PWM4>, |
| <&clks IMX6SL_CLK_PWM4>; |
| clock-names = "ipg", "per"; |
| }; |
| |
| gpt: gpt@02098000 { |
| compatible = "fsl,imx6sl-gpt"; |
| reg = <0x02098000 0x4000>; |
| interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_GPT>, |
| <&clks IMX6SL_CLK_GPT_SERIAL>; |
| clock-names = "ipg", "per"; |
| }; |
| |
| gpio1: gpio@0209c000 { |
| compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; |
| reg = <0x0209c000 0x4000>; |
| interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, |
| <0 67 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio2: gpio@020a0000 { |
| compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; |
| reg = <0x020a0000 0x4000>; |
| interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, |
| <0 69 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio3: gpio@020a4000 { |
| compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; |
| reg = <0x020a4000 0x4000>; |
| interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, |
| <0 71 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio4: gpio@020a8000 { |
| compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; |
| reg = <0x020a8000 0x4000>; |
| interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, |
| <0 73 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio5: gpio@020ac000 { |
| compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; |
| reg = <0x020ac000 0x4000>; |
| interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, |
| <0 75 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| kpp: kpp@020b8000 { |
| compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp"; |
| reg = <0x020b8000 0x4000>; |
| interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_DUMMY>; |
| status = "disabled"; |
| }; |
| |
| wdog1: wdog@020bc000 { |
| compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; |
| reg = <0x020bc000 0x4000>; |
| interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_DUMMY>; |
| }; |
| |
| wdog2: wdog@020c0000 { |
| compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; |
| reg = <0x020c0000 0x4000>; |
| interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_DUMMY>; |
| status = "disabled"; |
| }; |
| |
| clks: ccm@020c4000 { |
| compatible = "fsl,imx6sl-ccm"; |
| reg = <0x020c4000 0x4000>; |
| interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, |
| <0 88 IRQ_TYPE_LEVEL_HIGH>; |
| #clock-cells = <1>; |
| }; |
| |
| anatop: anatop@020c8000 { |
| compatible = "fsl,imx6sl-anatop", |
| "fsl,imx6q-anatop", |
| "syscon", "simple-bus"; |
| reg = <0x020c8000 0x1000>; |
| interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, |
| <0 54 IRQ_TYPE_LEVEL_HIGH>, |
| <0 127 IRQ_TYPE_LEVEL_HIGH>; |
| |
| regulator-1p1@110 { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vdd1p1"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1375000>; |
| regulator-always-on; |
| anatop-reg-offset = <0x110>; |
| anatop-vol-bit-shift = <8>; |
| anatop-vol-bit-width = <5>; |
| anatop-min-bit-val = <4>; |
| anatop-min-voltage = <800000>; |
| anatop-max-voltage = <1375000>; |
| anatop-enable-bit = <0>; |
| }; |
| |
| reg_3p0: regulator-3p0@120 { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vdd3p0"; |
| regulator-min-microvolt = <2625000>; |
| regulator-max-microvolt = <3400000>; |
| anatop-reg-offset = <0x120>; |
| anatop-vol-bit-shift = <8>; |
| anatop-vol-bit-width = <5>; |
| anatop-min-bit-val = <0>; |
| anatop-min-voltage = <2625000>; |
| anatop-max-voltage = <3400000>; |
| anatop-enable-bit = <0>; |
| }; |
| |
| regulator-2p5@130 { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vdd2p5"; |
| regulator-min-microvolt = <2100000>; |
| regulator-max-microvolt = <2850000>; |
| regulator-always-on; |
| anatop-reg-offset = <0x130>; |
| anatop-vol-bit-shift = <8>; |
| anatop-vol-bit-width = <5>; |
| anatop-min-bit-val = <0>; |
| anatop-min-voltage = <2100000>; |
| anatop-max-voltage = <2850000>; |
| anatop-enable-bit = <0>; |
| }; |
| |
| reg_arm: regulator-vddcore@140 { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vddarm"; |
| regulator-min-microvolt = <725000>; |
| regulator-max-microvolt = <1450000>; |
| regulator-always-on; |
| anatop-reg-offset = <0x140>; |
| anatop-vol-bit-shift = <0>; |
| anatop-vol-bit-width = <5>; |
| anatop-delay-reg-offset = <0x170>; |
| anatop-delay-bit-shift = <24>; |
| anatop-delay-bit-width = <2>; |
| anatop-min-bit-val = <1>; |
| anatop-min-voltage = <725000>; |
| anatop-max-voltage = <1450000>; |
| regulator-allow-bypass; |
| }; |
| |
| reg_pu: regulator-vddpu@140 { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vddpu"; |
| regulator-min-microvolt = <725000>; |
| regulator-max-microvolt = <1450000>; |
| regulator-enable-ramp-delay = <150>; |
| regulator-boot-on; |
| anatop-reg-offset = <0x140>; |
| anatop-vol-bit-shift = <9>; |
| anatop-vol-bit-width = <5>; |
| anatop-delay-reg-offset = <0x170>; |
| anatop-delay-bit-shift = <26>; |
| anatop-delay-bit-width = <2>; |
| anatop-min-bit-val = <1>; |
| anatop-min-voltage = <725000>; |
| anatop-max-voltage = <1450000>; |
| regulator-allow-bypass; |
| }; |
| |
| reg_soc: regulator-vddsoc@140 { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vddsoc"; |
| regulator-min-microvolt = <725000>; |
| regulator-max-microvolt = <1450000>; |
| regulator-always-on; |
| anatop-reg-offset = <0x140>; |
| anatop-vol-bit-shift = <18>; |
| anatop-vol-bit-width = <5>; |
| anatop-delay-reg-offset = <0x170>; |
| anatop-delay-bit-shift = <28>; |
| anatop-delay-bit-width = <2>; |
| anatop-min-bit-val = <1>; |
| anatop-min-voltage = <725000>; |
| anatop-max-voltage = <1450000>; |
| regulator-allow-bypass; |
| }; |
| }; |
| |
| tempmon: tempmon { |
| compatible = "fsl,imx6q-tempmon"; |
| interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; |
| fsl,tempmon = <&anatop>; |
| fsl,tempmon-data = <&ocotp>; |
| clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; |
| }; |
| |
| usbphy1: usbphy@020c9000 { |
| compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; |
| reg = <0x020c9000 0x1000>; |
| interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_USBPHY1>; |
| phy-3p0-supply = <®_3p0>; |
| fsl,anatop = <&anatop>; |
| }; |
| |
| usbphy2: usbphy@020ca000 { |
| compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; |
| reg = <0x020ca000 0x1000>; |
| interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_USBPHY2>; |
| phy-3p0-supply = <®_3p0>; |
| fsl,anatop = <&anatop>; |
| }; |
| |
| usbphy_nop1: usbphy_nop1 { |
| compatible = "usb-nop-xceiv"; |
| clocks = <&clks IMX6SL_CLK_USBPHY1>; |
| clock-names = "main_clk"; |
| }; |
| |
| snvs: snvs@020cc000 { |
| compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; |
| reg = <0x020cc000 0x4000>; |
| |
| snvs_rtc: snvs-rtc-lp { |
| compatible = "fsl,sec-v4.0-mon-rtc-lp"; |
| regmap = <&snvs>; |
| offset = <0x34>; |
| interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, |
| <0 20 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| snvs_poweroff: snvs-poweroff { |
| compatible = "syscon-poweroff"; |
| regmap = <&snvs>; |
| offset = <0x38>; |
| mask = <0x61>; |
| status = "disabled"; |
| }; |
| }; |
| |
| epit1: epit@020d0000 { |
| reg = <0x020d0000 0x4000>; |
| interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| epit2: epit@020d4000 { |
| reg = <0x020d4000 0x4000>; |
| interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| src: src@020d8000 { |
| compatible = "fsl,imx6sl-src", "fsl,imx51-src"; |
| reg = <0x020d8000 0x4000>; |
| interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, |
| <0 96 IRQ_TYPE_LEVEL_HIGH>; |
| #reset-cells = <1>; |
| }; |
| |
| gpc: gpc@020dc000 { |
| compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; |
| reg = <0x020dc000 0x4000>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&intc>; |
| pu-supply = <®_pu>; |
| clocks = <&clks IMX6SL_CLK_GPU2D_PODF>, <&clks IMX6SL_CLK_GPU2D_OVG>, |
| <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_LCDIF_AXI>, |
| <&clks IMX6SL_CLK_LCDIF_PIX>, <&clks IMX6SL_CLK_EPDC_AXI>, |
| <&clks IMX6SL_CLK_EPDC_PIX>, <&clks IMX6SL_CLK_PXP_AXI>; |
| clock-names = "gpu2d_podf", "gpu2d_ovg", "ipg", "lcd_axi", |
| "lcd_pix", "epdc_axi", "epdc_pix", "pxp_axi"; |
| #power-domain-cells = <1>; |
| }; |
| |
| gpr: iomuxc-gpr@020e0000 { |
| compatible = "fsl,imx6sl-iomuxc-gpr", |
| "fsl,imx6q-iomuxc-gpr", "syscon"; |
| reg = <0x020e0000 0x38>; |
| }; |
| |
| iomuxc: iomuxc@020e0000 { |
| compatible = "fsl,imx6sl-iomuxc"; |
| reg = <0x020e0000 0x4000>; |
| }; |
| |
| csi: csi@020e4000 { |
| compatible = "fsl,imx6sl-csi"; |
| reg = <0x020e4000 0x4000>; |
| interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_DUMMY>, |
| <&clks IMX6SL_CLK_DUMMY>, |
| <&clks IMX6SL_CLK_DUMMY>; |
| clock-names = "disp-axi", "csi_mclk", "disp_dcic"; |
| status = "disabled"; |
| }; |
| |
| spdc: spdc@020e8000 { |
| reg = <0x020e8000 0x4000>; |
| interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| sdma: sdma@020ec000 { |
| compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma"; |
| reg = <0x020ec000 0x4000>; |
| interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_SDMA>, |
| <&clks IMX6SL_CLK_SDMA>; |
| clock-names = "ipg", "ahb"; |
| #dma-cells = <3>; |
| iram = <&ocram>; |
| /* imx6sl reuses imx6q sdma firmware */ |
| fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; |
| }; |
| |
| pxp: pxp@020f0000 { |
| compatible = "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma"; |
| reg = <0x020f0000 0x4000>; |
| interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_PXP_AXI>, <&clks IMX6SL_CLK_DUMMY>; |
| clock-names = "pxp-axi", "disp-axi"; |
| status = "disabled"; |
| }; |
| |
| epdc: epdc@020f4000 { |
| compatible = "fsl,imx6sl-epdc", "fsl,imx6dl-epdc"; |
| reg = <0x020f4000 0x4000>; |
| interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_EPDC_AXI>, <&clks IMX6SL_CLK_EPDC_PIX>; |
| clock-names = "epdc_axi", "epdc_pix"; |
| }; |
| |
| lcdif: lcdif@020f8000 { |
| compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif"; |
| reg = <0x020f8000 0x4000>; |
| interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_LCDIF_PIX>, |
| <&clks IMX6SL_CLK_LCDIF_AXI>, |
| <&clks IMX6SL_CLK_DUMMY>; |
| clock-names = "pix", "axi", "disp_axi"; |
| status = "disabled"; |
| }; |
| |
| dcp: dcp@020fc000 { |
| compatible = "fsl,imx6sl-dcp"; |
| reg = <0x020fc000 0x4000>; |
| interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>, |
| <0 100 IRQ_TYPE_LEVEL_HIGH>, |
| <0 101 IRQ_TYPE_LEVEL_HIGH>; |
| /* DCP clock always on */ |
| clocks = <&clks IMX6SL_CLK_DUMMY>; |
| clock-names = "dcp"; |
| status = "okay"; |
| }; |
| }; |
| |
| aips2: aips-bus@02100000 { |
| compatible = "fsl,aips-bus", "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x02100000 0x100000>; |
| ranges; |
| |
| usbotg1: usb@02184000 { |
| compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; |
| reg = <0x02184000 0x200>; |
| interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_USBOH3>; |
| fsl,usbphy = <&usbphy1>; |
| fsl,usbmisc = <&usbmisc 0>; |
| ahb-burst-config = <0x0>; |
| tx-burst-size-dword = <0x10>; |
| rx-burst-size-dword = <0x10>; |
| fsl,anatop = <&anatop>; |
| status = "disabled"; |
| }; |
| |
| usbotg2: usb@02184200 { |
| compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; |
| reg = <0x02184200 0x200>; |
| interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_USBOH3>; |
| fsl,usbphy = <&usbphy2>; |
| fsl,usbmisc = <&usbmisc 1>; |
| ahb-burst-config = <0x0>; |
| tx-burst-size-dword = <0x10>; |
| rx-burst-size-dword = <0x10>; |
| status = "disabled"; |
| }; |
| |
| usbh: usb@02184400 { |
| compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; |
| reg = <0x02184400 0x200>; |
| interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_USBOH3>; |
| fsl,usbmisc = <&usbmisc 2>; |
| dr_mode = "host"; |
| ahb-burst-config = <0x0>; |
| tx-burst-size-dword = <0x10>; |
| rx-burst-size-dword = <0x10>; |
| phy_type = "hsic"; |
| fsl,usbphy = <&usbphy_nop1>; |
| fsl,anatop = <&anatop>; |
| status = "disabled"; |
| }; |
| |
| usbmisc: usbmisc@02184800 { |
| #index-cells = <1>; |
| compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc"; |
| reg = <0x02184800 0x200>; |
| clocks = <&clks IMX6SL_CLK_USBOH3>; |
| vbus-wakeup-supply = <®_vbus_wakeup>; |
| }; |
| |
| fec: ethernet@02188000 { |
| compatible = "fsl,imx6sl-fec", "fsl,imx25-fec"; |
| reg = <0x02188000 0x4000>; |
| interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_ENET>, |
| <&clks IMX6SL_CLK_ENET_REF>; |
| clock-names = "ipg", "ahb"; |
| status = "disabled"; |
| }; |
| |
| usdhc1: usdhc@02190000 { |
| compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; |
| reg = <0x02190000 0x4000>; |
| interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_USDHC1>, |
| <&clks IMX6SL_CLK_USDHC1>, |
| <&clks IMX6SL_CLK_USDHC1>; |
| clock-names = "ipg", "ahb", "per"; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| usdhc2: usdhc@02194000 { |
| compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; |
| reg = <0x02194000 0x4000>; |
| interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_USDHC2>, |
| <&clks IMX6SL_CLK_USDHC2>, |
| <&clks IMX6SL_CLK_USDHC2>; |
| clock-names = "ipg", "ahb", "per"; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| usdhc3: usdhc@02198000 { |
| compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; |
| reg = <0x02198000 0x4000>; |
| interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_USDHC3>, |
| <&clks IMX6SL_CLK_USDHC3>, |
| <&clks IMX6SL_CLK_USDHC3>; |
| clock-names = "ipg", "ahb", "per"; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| usdhc4: usdhc@0219c000 { |
| compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; |
| reg = <0x0219c000 0x4000>; |
| interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_USDHC4>, |
| <&clks IMX6SL_CLK_USDHC4>, |
| <&clks IMX6SL_CLK_USDHC4>; |
| clock-names = "ipg", "ahb", "per"; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@021a0000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; |
| reg = <0x021a0000 0x4000>; |
| interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_I2C1>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@021a4000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; |
| reg = <0x021a4000 0x4000>; |
| interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_I2C2>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@021a8000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; |
| reg = <0x021a8000 0x4000>; |
| interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_I2C3>; |
| status = "disabled"; |
| }; |
| |
| mmdc: mmdc@021b0000 { |
| compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; |
| reg = <0x021b0000 0x4000>; |
| }; |
| |
| rng: rng@021b4000 { |
| compatible = "fsl,imx6sl-rng", "fsl,imx-rng", "imx-rng"; |
| reg = <0x021b4000 0x4000>; |
| interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_DUMMY>; |
| }; |
| |
| weim: weim@021b8000 { |
| reg = <0x021b8000 0x4000>; |
| interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| ocotp: ocotp@021bc000 { |
| compatible = "fsl,imx6sl-ocotp", "syscon"; |
| reg = <0x021bc000 0x4000>; |
| clocks = <&clks IMX6SL_CLK_OCOTP>; |
| }; |
| |
| audmux: audmux@021d8000 { |
| compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux"; |
| reg = <0x021d8000 0x4000>; |
| status = "disabled"; |
| }; |
| |
| gpu: gpu@02200000 { |
| compatible = "fsl,imx6sl-gpu", "fsl,imx6q-gpu"; |
| reg = <0x02200000 0x4000>, <0x02204000 0x4000>, |
| <0x80000000 0x0>, <0x0 0x8000000>; |
| reg-names = "iobase_2d", "iobase_vg", |
| "phys_baseaddr", "contiguous_mem"; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "irq_2d", "irq_vg"; |
| clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, |
| <&clks IMX6SL_CLK_MMDC_ROOT>, |
| <&clks IMX6SL_CLK_GPU2D_OVG>; |
| clock-names = "gpu2d_axi_clk", "openvg_axi_clk", |
| "gpu2d_clk"; |
| resets = <&src 3>, <&src 3>; |
| reset-names = "gpu2d", "gpuvg"; |
| power-domains = <&gpc 1>; |
| }; |
| }; |
| }; |
| }; |
