| /* SYS, CORE AND BUS CLOCKS */ |
| #define SYS_D1CPRE 0 |
| #define HCLK 1 |
| #define PCLK1 2 |
| #define PCLK2 3 |
| #define PCLK3 4 |
| #define PCLK4 5 |
| #define HSI_DIV 6 |
| #define HSE_1M 7 |
| #define I2S_CKIN 8 |
| #define CK_DSI_PHY 9 |
| #define HSE_CK 10 |
| #define LSE_CK 11 |
| #define CSI_KER_DIV122 12 |
| #define RTC_CK 13 |
| #define CPU_SYSTICK 14 |
| |
| /* OSCILLATOR BANK */ |
| #define OSC_BANK 18 |
| #define HSI_CK 18 |
| #define HSI_KER_CK 19 |
| #define CSI_CK 20 |
| #define CSI_KER_CK 21 |
| #define RC48_CK 22 |
| #define LSI_CK 23 |
| |
| /* MCLOCK BANK */ |
| #define MCLK_BANK 28 |
| #define PER_CK 28 |
| #define PLLSRC 29 |
| #define SYS_CK 30 |
| #define TRACEIN_CK 31 |
| |
| /* ODF BANK */ |
| #define ODF_BANK 32 |
| #define PLL1_P 32 |
| #define PLL1_Q 33 |
| #define PLL1_R 34 |
| #define PLL2_P 35 |
| #define PLL2_Q 36 |
| #define PLL2_R 37 |
| #define PLL3_P 38 |
| #define PLL3_Q 39 |
| #define PLL3_R 40 |
| |
| /* MCO BANK */ |
| #define MCO_BANK 41 |
| #define MCO1 41 |
| #define MCO2 42 |
| |
| /* PERIF BANK */ |
| #define PERIF_BANK 50 |
| #define D1SRAM1_CK 50 |
| #define ITCM_CK 51 |
| #define DTCM2_CK 52 |
| #define DTCM1_CK 53 |
| #define FLITF_CK 54 |
| #define JPGDEC_CK 55 |
| #define DMA2D_CK 56 |
| #define MDMA_CK 57 |
| #define USB2ULPI_CK 58 |
| #define USB1ULPI_CK 59 |
| #define ETH1RX_CK 60 |
| #define ETH1TX_CK 61 |
| #define ETH1MAC_CK 62 |
| #define ART_CK 63 |
| #define DMA2_CK 64 |
| #define DMA1_CK 65 |
| #define D2SRAM3_CK 66 |
| #define D2SRAM2_CK 67 |
| #define D2SRAM1_CK 68 |
| #define HASH_CK 69 |
| #define CRYPT_CK 70 |
| #define CAMITF_CK 71 |
| #define BKPRAM_CK 72 |
| #define HSEM_CK 73 |
| #define BDMA_CK 74 |
| #define CRC_CK 75 |
| #define GPIOK_CK 76 |
| #define GPIOJ_CK 77 |
| #define GPIOI_CK 78 |
| #define GPIOH_CK 79 |
| #define GPIOG_CK 80 |
| #define GPIOF_CK 81 |
| #define GPIOE_CK 82 |
| #define GPIOD_CK 83 |
| #define GPIOC_CK 84 |
| #define GPIOB_CK 85 |
| #define GPIOA_CK 86 |
| #define WWDG1_CK 87 |
| #define DAC12_CK 88 |
| #define WWDG2_CK 89 |
| #define TIM14_CK 90 |
| #define TIM13_CK 91 |
| #define TIM12_CK 92 |
| #define TIM7_CK 93 |
| #define TIM6_CK 94 |
| #define TIM5_CK 95 |
| #define TIM4_CK 96 |
| #define TIM3_CK 97 |
| #define TIM2_CK 98 |
| #define MDIOS_CK 99 |
| #define OPAMP_CK 100 |
| #define CRS_CK 101 |
| #define TIM17_CK 102 |
| #define TIM16_CK 103 |
| #define TIM15_CK 104 |
| #define TIM8_CK 105 |
| #define TIM1_CK 106 |
| #define TMPSENS_CK 107 |
| #define RTCAPB_CK 108 |
| #define VREF_CK 109 |
| #define COMP12_CK 110 |
| #define SYSCFG_CK 111 |
| /* must be equal to last peripheral clock index */ |
| #define LAST_PERIF_BANK SYSCFG_CK |
| |
| /* KERNEL BANK */ |
| #define KERN_BANK 120 |
| #define SDMMC1_CK 120 |
| #define QUADSPI_CK 121 |
| #define FMC_CK 122 |
| #define USB2OTG_CK 123 |
| #define USB1OTG_CK 124 |
| #define ADC12_CK 125 |
| #define SDMMC2_CK 126 |
| #define RNG_CK 127 |
| #define ADC3_CK 128 |
| #define DSI_CK 129 |
| #define LTDC_CK 130 |
| #define USART8_CK 131 |
| #define USART7_CK 132 |
| #define HDMICEC_CK 133 |
| #define I2C3_CK 134 |
| #define I2C2_CK 135 |
| #define I2C1_CK 136 |
| #define UART5_CK 137 |
| #define UART4_CK 138 |
| #define USART3_CK 139 |
| #define USART2_CK 140 |
| #define SPDIFRX_CK 141 |
| #define SPI3_CK 142 |
| #define SPI2_CK 143 |
| #define LPTIM1_CK 144 |
| #define FDCAN_CK 145 |
| #define SWP_CK 146 |
| #define HRTIM_CK 147 |
| #define DFSDM1_CK 148 |
| #define SAI3_CK 149 |
| #define SAI2_CK 150 |
| #define SAI1_CK 151 |
| #define SPI5_CK 152 |
| #define SPI4_CK 153 |
| #define SPI1_CK 154 |
| #define USART6_CK 155 |
| #define USART1_CK 156 |
| #define SAI4B_CK 157 |
| #define SAI4A_CK 158 |
| #define LPTIM5_CK 159 |
| #define LPTIM4_CK 160 |
| #define LPTIM3_CK 161 |
| #define LPTIM2_CK 162 |
| #define I2C4_CK 163 |
| #define SPI6_CK 164 |
| #define LPUART1_CK 165 |
| |
| #define STM32H7_MAX_CLKS 166 |
