| /* |
| * Copyright (C) 2016 Freescale Semiconductor, Inc. |
| * Copyright 2017 NXP |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License |
| * as published by the Free Software Foundation; either version 2 |
| * of the License, or (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include "fsl-imx8-ca35.dtsi" |
| #include <dt-bindings/soc/imx_rsrc.h> |
| #include <dt-bindings/soc/imx8_hsio.h> |
| #include <dt-bindings/soc/imx8_pd.h> |
| #include <dt-bindings/clock/imx8qxp-clock.h> |
| #include <dt-bindings/pinctrl/pads-imx8qxp.h> |
| #include <dt-bindings/gpio/gpio.h> |
| |
| / { |
| compatible = "fsl,imx8qxp"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| csi0 = &mipi_csi_0; |
| dpu0 = &dpu1; |
| ethernet0 = &fec1; |
| ethernet1 = &fec2; |
| ldb0 = &ldb1; |
| ldb1 = &ldb2; |
| isi0 = &isi_0; |
| isi1 = &isi_1; |
| isi2 = &isi_2; |
| isi3 = &isi_3; |
| isi4 = &isi_4; |
| isi5 = &isi_5; |
| isi6 = &isi_6; |
| isi7 = &isi_7; |
| serial0 = &lpuart0; |
| serial1 = &lpuart1; |
| serial2 = &lpuart2; |
| serial3 = &lpuart3; |
| mmc0 = &usdhc1; |
| gpio0 = &gpio0; |
| gpio1 = &gpio1; |
| gpio2 = &gpio2; |
| gpio3 = &gpio3; |
| gpio4 = &gpio4; |
| gpio5 = &gpio5; |
| gpio6 = &gpio6; |
| gpio7 = &gpio7; |
| i2c0 = &i2c0; |
| i2c1 = &i2c1; |
| i2c2 = &i2c2; |
| i2c3 = &i2c3; |
| i2c13 = &i2c0_mipi_lvds0; |
| i2c15 = &i2c0_mipi_lvds1; |
| mmc1 = &usdhc2; |
| mmc2 = &usdhc3; |
| spi0 = &flexspi0; |
| usb0 = &usbotg1; |
| usbphy0 = &usbphy1; |
| usb1 = &usb2; |
| usbphy1 = &usb2_phy; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0x00000000 0x80000000 0 0x40000000>; |
| /* DRAM space - 1, size : 1 GB DRAM */ |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| /* global autoconfigured region for contiguous allocations */ |
| linux,cma { |
| compatible = "shared-dma-pool"; |
| reusable; |
| size = <0 0x28000000>; |
| alloc-ranges = <0 0x80000000 0 0x80000000>; |
| linux,cma-default; |
| }; |
| }; |
| |
| gic: interrupt-controller@51a00000 { |
| compatible = "arm,gic-v3"; |
| reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ |
| <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| interrupts = <GIC_PPI 9 |
| (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; |
| }; |
| |
| mu: mu@5d1b0000 { |
| compatible = "fsl,imx8-mu"; |
| reg = <0x0 0x5d1b0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; |
| fsl,scu_ap_mu_id = <0>; |
| #mbox-cells = <4>; |
| status = "okay"; |
| }; |
| |
| mu13: mu13@5d280000 { |
| compatible = "fsl,imx8-mu-hifi"; |
| reg = <0x0 0x5d280000 0x0 0x10000>; |
| interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; |
| fsl,hifi_ap_mu_id = <13>; |
| status = "okay"; |
| }; |
| |
| clk: clk { |
| compatible = "fsl,imx8qxp-clk"; |
| #clock-cells = <1>; |
| }; |
| |
| iomuxc: iomuxc { |
| compatible = "fsl,imx8qxp-iomuxc"; |
| }; |
| |
| rtc: rtc { |
| compatible = "fsl,imx-sc-rtc"; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ |
| clock-frequency = <8000000>; |
| }; |
| |
| imx8qx-pm { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| pd_lsio: PD_LSIO { |
| compatible = "nxp,imx8-pd"; |
| reg = <SC_R_LAST>; |
| #power-domain-cells = <0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| pd_lsio_pwm0: PD_LSIO_PWM_0 { |
| reg = <SC_R_PWM_0>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_pwm1: PD_LSIO_PWM_1 { |
| reg = <SC_R_PWM_1>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_pwm2: PD_LSIO_PWM_2 { |
| reg = <SC_R_PWM_2>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_pwm3: PD_LSIO_PWM_3 { |
| reg = <SC_R_PWM_3>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_pwm4: PD_LSIO_PWM_4 { |
| reg = <SC_R_PWM_4>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_pwm5: PD_LSIO_PWM_5 { |
| reg = <SC_R_PWM_5>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_pwm6: PD_LSIO_PWM_6 { |
| reg = <SC_R_PWM_6>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_pwm7: PD_LSIO_PWM_7 { |
| reg = <SC_R_PWM_7>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_kpp: PD_LSIO_KPP { |
| reg = <SC_R_KPP>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_gpio0: PD_LSIO_GPIO_0 { |
| reg = <SC_R_GPIO_0>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_gpio1: PD_LSIO_GPIO_1 { |
| reg = <SC_R_GPIO_1>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_gpio2: PD_LSIO_GPIO_2 { |
| reg = <SC_R_GPIO_2>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_gpio3: PD_LSIO_GPIO_3 { |
| reg = <SC_R_GPIO_3>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_gpio4: PD_LSIO_GPIO_4 { |
| reg = <SC_R_GPIO_4>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_gpio5: PD_LSIO_GPIO_5{ |
| reg = <SC_R_GPIO_5>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_gpio6:PD_LSIO_GPIO_6 { |
| reg = <SC_R_GPIO_6>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_gpio7: PD_LSIO_GPIO_7 { |
| reg = <SC_R_GPIO_7>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_gpt0: PD_LSIO_GPT_0 { |
| reg = <SC_R_GPT_0>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_gpt1: PD_LSIO_GPT_1 { |
| reg = <SC_R_GPT_1>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_gpt2: PD_LSIO_GPT_2 { |
| reg = <SC_R_GPT_2>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_gpt3: PD_LSIO_GPT_3 { |
| reg = <SC_R_GPT_3>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_gpt4: PD_LSIO_GPT_4 { |
| reg = <SC_R_GPT_4>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_flexspi0: PD_LSIO_FSPI_0 { |
| reg = <SC_R_FSPI_0>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| pd_lsio_flexspi1: PD_LSIO_FSPI_1{ |
| reg = <SC_R_FSPI_1>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_lsio>; |
| }; |
| }; |
| |
| pd_conn: PD_CONN { |
| compatible = "nxp,imx8-pd"; |
| reg = <SC_R_LAST>; |
| #power-domain-cells = <0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| pd_conn_usbotg0: PD_CONN_USB_0 { |
| reg = <SC_R_USB_0>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_conn>; |
| }; |
| pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY { |
| reg = <SC_R_USB_0_PHY>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_conn>; |
| }; |
| pd_conn_usbotg1: PD_CONN_USB_1 { |
| reg = <SC_R_USB_1>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_conn>; |
| }; |
| pd_conn_usb2: PD_CONN_USB_2 { |
| reg = <SC_R_USB_2>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_conn>; |
| }; |
| pd_conn_usb2_phy: PD_CONN_USB_2_PHY { |
| reg = <SC_R_USB_2_PHY>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_conn>; |
| }; |
| pd_conn_sdch0: PD_CONN_SDHC_0 { |
| reg = <SC_R_SDHC_0>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_conn>; |
| }; |
| pd_conn_sdch1: PD_CONN_SDHC_1 { |
| reg = <SC_R_SDHC_1>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_conn>; |
| }; |
| pd_conn_sdch2: PD_CONN_SDHC_2 { |
| reg = <SC_R_SDHC_2>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_conn>; |
| }; |
| pd_conn_enet0: PD_CONN_ENET_0 { |
| reg = <SC_R_ENET_0>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_conn>; |
| }; |
| pd_conn_enet1: PD_CONN_ENET_1 { |
| reg = <SC_R_ENET_1>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_conn>; |
| }; |
| pd_conn_nand: PD_CONN_NAND { |
| reg = <SC_R_NAND>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_conn>; |
| }; |
| pd_conn_mlb0: PD_CONN_MLB_0 { |
| reg = <SC_R_MLB_0>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_conn>; |
| }; |
| pd_conn_edma_ch0: PD_CONN_DMA_4_CH0 { |
| reg = <SC_R_DMA_4_CH0>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_conn>; |
| }; |
| pd_conn_edma_ch1: PD_CONN_DMA_4_CH1 { |
| reg = <SC_R_DMA_4_CH1>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_conn>; |
| }; |
| pd_conn_edma_ch2: PD_CONN_DMA_4_CH2 { |
| reg = <SC_R_DMA_4_CH2>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_conn>; |
| }; |
| pd_conn_edma_ch3: PD_CONN_DMA_4_CH3 { |
| reg = <SC_R_DMA_4_CH3>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_conn>; |
| }; |
| pd_conn_edma_ch4: PD_CONN_DMA_4_CH4 { |
| reg = <SC_R_DMA_4_CH4>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_conn>; |
| }; |
| }; |
| |
| pd_audio: PD_AUDIO { |
| compatible = "nxp,imx8-pd"; |
| reg = <SC_R_LAST>; |
| #power-domain-cells = <0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| pd_asrc0:PD_AUD_ASRC_0 { |
| reg = <SC_R_ASRC_0>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_asrc1: PD_AUD_ASRC_1 { |
| reg = <SC_R_ASRC_1>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_esai0: PD_AUD_ESAI_0 { |
| reg = <SC_R_ESAI_0>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_spdif0: PD_AUD_SPDIF_0 { |
| reg = <SC_R_SPDIF_0>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_sai0:PD_AUD_SAI_0 { |
| reg = <SC_R_SAI_0>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_sai1: PD_AUD_SAI_1 { |
| reg = <SC_R_SAI_1>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_sai2: PD_AUD_SAI_2 { |
| reg = <SC_R_SAI_2>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_sai3: PD_AUD_SAI_3 { |
| reg = <SC_R_SAI_3>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_sai4: PD_AUD_SAI_4 { |
| reg = <SC_R_SAI_4>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_sai5: PD_AUD_SAI_5 { |
| reg = <SC_R_SAI_5>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_gpt5: PD_AUD_GPT_5 { |
| reg = <SC_R_GPT_5>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_gpt6: PD_AUD_GPT_6 { |
| reg = <SC_R_GPT_6>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_gpt7: PD_AUD_GPT_7 { |
| reg = <SC_R_GPT_7>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_gpt8: PD_AUD_GPT_8 { |
| reg = <SC_R_GPT_8>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_gpt9: PD_AUD_GPT_9 { |
| reg = <SC_R_GPT_9>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_gpt10: PD_AUD_GPT_10 { |
| reg = <SC_R_GPT_10>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_amix: PD_AUD_AMIX { |
| reg = <SC_R_AMIX>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_mqs0: PD_AUD_MQS_0 { |
| reg = <SC_R_MQS_0>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_hifi: PD_AUD_HIFI { |
| reg = <SC_R_HIFI>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_hifi_ram: PD_AUD_OCRAM { |
| reg = <SC_R_HIFI_RAM>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_mclk_out0: PD_AUD_MCLK_OUT_0 { |
| reg = <SC_R_MCLK_OUT_0>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_mclk_out1: PD_AUD_MCLK_OUT_1 { |
| reg = <SC_R_MCLK_OUT_1>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_audio_pll0: PD_AUD_AUDIO_PLL_0 { |
| reg = <SC_R_AUDIO_PLL_0>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_audio_pll1: PD_AUD_AUDIO_PLL_1 { |
| reg = <SC_R_AUDIO_PLL_1>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_audio_clk0: PD_AUD_AUDIO_CLK_0 { |
| reg = <SC_R_AUDIO_CLK_0>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| pd_audio_clk1: PD_AUD_AUDIO_CLK_1 { |
| reg = <SC_R_AUDIO_CLK_1>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_audio>; |
| }; |
| }; |
| |
| pd_dma: PD_DMA { |
| compatible = "nxp,imx8-pd"; |
| reg = <SC_R_LAST>; |
| #power-domain-cells = <0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| pd_dma_flexcan0: PD_DMA_CAN_0 { |
| reg = <SC_R_CAN_0>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_dma>; |
| }; |
| pd_dma_flexcan1: PD_DMA_CAN_1 { |
| reg = <SC_R_CAN_1>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_dma>; |
| }; |
| pd_dma_flexcan2: PD_DMA_CAN_2 { |
| reg = <SC_R_CAN_2>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_dma>; |
| }; |
| pd_dma_ftm0: PD_DMA_FTM_0 { |
| reg = <SC_R_FTM_0>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_dma>; |
| }; |
| pd_dma_ftm1: PD_DMA_FTM_1 { |
| reg = <SC_R_FTM_1>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_dma>; |
| }; |
| pd_dma_adc0: PD_DMA_ADC_0 { |
| reg = <SC_R_ADC_0>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_dma>; |
| }; |
| pd_dma_lpi2c0: PD_DMA_I2C_0 { |
| reg = <SC_R_I2C_0>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_dma>; |
| }; |
| pd_dma_lpi2c1: PD_DMA_I2C_1 { |
| reg = <SC_R_I2C_1>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_dma>; |
| }; |
| pd_dma_lpi2c2:PD_DMA_I2C_2 { |
| reg = <SC_R_I2C_2>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_dma>; |
| }; |
| pd_dma_lpi2c3: PD_DMA_I2C_3 { |
| reg = <SC_R_I2C_3>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_dma>; |
| }; |
| pd_dma_lpuart0: PD_DMA_UART0 { |
| reg = <SC_R_UART_0>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_dma>; |
| }; |
| pd_dma_lpuart1: PD_DMA_UART1 { |
| reg = <SC_R_UART_1>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_dma>; |
| }; |
| pd_dma_lpuart2: PD_DMA_UART2 { |
| reg = <SC_R_UART_2>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_dma>; |
| }; |
| pd_dma_lpuart3: PD_DMA_UART3 { |
| reg = <SC_R_UART_3>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_dma>; |
| }; |
| pd_dma_lpspi0: PD_DMA_SPI_0 { |
| reg = <SC_R_SPI_0>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_dma>; |
| }; |
| pd_dma_lpspi1: PD_DMA_SPI_1 { |
| reg = <SC_R_SPI_1>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_dma>; |
| }; |
| pd_dma_lpspi2: PD_DMA_SPI_2 { |
| reg = <SC_R_SPI_2>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_dma>; |
| }; |
| pd_dma_lpspi3: PD_DMA_SPI_3 { |
| reg = <SC_R_SPI_3>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_dma>; |
| }; |
| pd_dma_pwm0: PD_DMA_PWM_0 { |
| reg = <SC_R_LCD_0_PWM_0>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_dma>; |
| }; |
| pd_dma_lcd0: PD_DMA_LCD_0 { |
| reg = <SC_R_LCD_0>; |
| #power-domain-cells = <0>; |
| power-domains = <&pd_dma>; |
| }; |
| }; |
| |
| pd_gpu: gpu-power-domain { |
| compatible = "nxp,imx8-pd"; |
| reg = <SC_R_LAST>; |
| #power-domain-cells = <0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| pd_gpu0: gpu0 { |
| name = "gpu0"; |
| reg = <SC_R_GPU_0_PID0>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_gpu>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| pd_vpu: vpu-power-domain { |
| compatible = "nxp,imx8-pd"; |
| reg = <SC_R_VPU_PID0>; |
| #power-domain-cells = <0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| pd_vpu_core: vpu_core { |
| name = "vpu_core"; |
| reg = <SC_R_VPUCORE>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_vpu>; |
| }; |
| }; |
| |
| pd_hsio: hsio-power-domain { |
| compatible = "nxp,imx8-pd"; |
| reg = <SC_R_LAST>; |
| #power-domain-cells = <0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| pd_serdes1: PD_HSIO_SERDES_1 { |
| reg = <SC_R_SERDES_1>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_hsio>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| pd_pcie: PD_HSIO_PCIE_B { |
| reg = <SC_R_PCIE_B>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_serdes1>; |
| }; |
| }; |
| }; |
| |
| pd_cm40: PD_CM40 { |
| compatible = "nxp,imx8-pd"; |
| reg = <SC_R_LAST>; |
| #power-domain-cells = <0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| pd_cm40_i2c: PD_CM40_I2C { |
| reg = <SC_R_M4_0_I2C>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_cm40>; |
| }; |
| |
| pd_cm40_intmux: PD_CM40_INTMUX { |
| reg = <SC_R_M4_0_INTMUX>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_cm40>; |
| }; |
| }; |
| |
| |
| pd_dc0: PD_DC_0 { |
| compatible = "nxp,imx8-pd"; |
| reg = <SC_R_DC_0>; |
| #power-domain-cells = <0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| pd_mipi_dsi0: PD_MIPI_0_DSI { |
| reg = <SC_R_MIPI_0>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_dc0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| pd_mipi_dsi_0_i2c0: PD_MIPI_0_DSI_I2C0 { |
| reg = <SC_R_MIPI_0_I2C_0>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_mipi_dsi0>; |
| }; |
| pd_mipi_dsi_0_i2c1: PD_MIPI_0_DSI_I2C1 { |
| reg = <SC_R_MIPI_0_I2C_1>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_mipi_dsi0>; |
| }; |
| pd_mipi_0_pwm0: PD_MIPI_0_DSI_PWM0 { |
| reg = <SC_R_MIPI_0_PWM_0>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_mipi_dsi0>; |
| }; |
| }; |
| |
| pd_mipi_dsi1: PD_MIPI_1_DSI { |
| reg = <SC_R_MIPI_1>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_dc0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| pd_mipi_dsi_1_i2c0: PD_MIPI_1_DSI_I2C0 { |
| reg = <SC_R_MIPI_1_I2C_0>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_mipi_dsi1>; |
| }; |
| pd_mipi_dsi_1_i2c1: PD_MIPI_1_DSI_I2C1 { |
| reg = <SC_R_MIPI_1_I2C_1>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_mipi_dsi1>; |
| }; |
| pd_mipi_1_pwm0: PD_MIPI_1_DSI_PWM0 { |
| reg = <SC_R_MIPI_1_PWM_0>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_mipi_dsi1>; |
| }; |
| }; |
| }; |
| |
| pd_isi_ch0: PD_IMAGING { |
| compatible = "nxp,imx8-pd"; |
| reg = <SC_R_ISI_CH0>; |
| #power-domain-cells = <0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| pd_mipi_csi: PD_MIPI_CSI0 { |
| reg = <SC_R_CSI_0>; |
| #power-domain-cells = <0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains =<&pd_isi_ch0>; |
| |
| pd_mipi_csi_i2c0: PD_MIPI_CSI0_I2C { |
| name = "mipi_csi0_i2c"; |
| reg = <SC_R_CSI_0_I2C_0>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_mipi_csi>; |
| }; |
| |
| pd_mipi_csi_pwm0: PD_MIPI_CSI0_PWM { |
| name = "mipi_csi0_pwm"; |
| reg = <SC_R_CSI_0_PWM_0>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_mipi_csi>; |
| }; |
| }; |
| |
| pd_isi_ch1: PD_IMAGING_PDMA1 { |
| reg = <SC_R_ISI_CH1>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_isi_ch0>; |
| }; |
| |
| pd_isi_ch2: PD_IMAGING_PDMA2 { |
| reg = <SC_R_ISI_CH2>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_isi_ch0>; |
| }; |
| |
| pd_isi_ch3: PD_IMAGING_PDMA3 { |
| reg = <SC_R_ISI_CH3>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_isi_ch0>; |
| }; |
| |
| pd_isi_ch4: PD_IMAGING_PDMA4 { |
| reg = <SC_R_ISI_CH4>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_isi_ch0>; |
| }; |
| |
| pd_isi_ch5: PD_IMAGING_PDMA5 { |
| reg = <SC_R_ISI_CH5>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_isi_ch0>; |
| }; |
| |
| pd_isi_ch6: PD_IMAGING_PDMA6 { |
| reg = <SC_R_ISI_CH6>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_isi_ch0>; |
| }; |
| |
| pd_isi_ch7: PD_IMAGING_PDMA7 { |
| reg = <SC_R_ISI_CH7>; |
| #power-domain-cells = <0>; |
| power-domains =<&pd_isi_ch0>; |
| }; |
| }; |
| }; |
| |
| tsens: thermal-sensor { |
| compatible = "nxp,imx8qxp-sc-tsens"; |
| u-boot,dm-pre-reloc; |
| /* number of the temp sensor on the chip */ |
| tsens-num = <1>; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| thermal-zones { |
| /* cpu thermal */ |
| cpu-thermal0 { |
| polling-delay-passive = <250>; |
| polling-delay = <2000>; |
| /*the slope and offset of the temp sensor */ |
| thermal-sensors = <&tsens 0>; |
| trips { |
| cpu_alert0: trip0 { |
| temperature = <85000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| cpu_crit0: trip1 { |
| temperature = <127000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| }; |
| |
| gpio0: gpio@5d080000 { |
| compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; |
| reg = <0x0 0x5d080000 0x0 0x10000>; |
| interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd_lsio_gpio0>; |
| }; |
| |
| gpio1: gpio@5d090000 { |
| compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; |
| reg = <0x0 0x5d090000 0x0 0x10000>; |
| interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd_lsio_gpio1>; |
| }; |
| |
| gpio2: gpio@5d0a0000 { |
| compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; |
| reg = <0x0 0x5d0a0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd_lsio_gpio2>; |
| }; |
| |
| gpio3: gpio@5d0b0000 { |
| compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; |
| reg = <0x0 0x5d0b0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd_lsio_gpio3>; |
| }; |
| |
| gpio4: gpio@5d0c0000 { |
| compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; |
| reg = <0x0 0x5d0c0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd_lsio_gpio4>; |
| }; |
| |
| gpio5: gpio@5d0d0000 { |
| compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; |
| reg = <0x0 0x5d0d0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd_lsio_gpio5>; |
| }; |
| |
| gpio6: gpio@5d0e0000 { |
| compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; |
| reg = <0x0 0x5d0e0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd_lsio_gpio6>; |
| }; |
| |
| gpio7: gpio@5d0f0000 { |
| compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; |
| reg = <0x0 0x5d0f0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd_lsio_gpio7>; |
| }; |
| |
| irqsteer_csi: irqsteer@58220000 { |
| compatible = "nxp,imx-irqsteer"; |
| reg = <0x0 0x58220000 0x0 0x1000>; |
| interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-controller; |
| interrupt-parent = <&gic>; |
| #interrupt-cells = <2>; |
| clocks = <&clk IMX8QXP_CSI0_IPG_CLK>; |
| clock-names = "ipg"; |
| power-domains = <&pd_mipi_csi>; |
| }; |
| |
| i2c0_csi0: i2c@58226000 { |
| compatible = "fsl,imx8qm-lpi2c"; |
| reg = <0x0 0x58226000 0x0 0x1000>; |
| interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&irqsteer_csi>; |
| clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>, |
| <&clk IMX8QXP_CSI0_I2C0_IPG_CLK>; |
| clock-names = "per", "ipg"; |
| assigned-clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>; |
| assigned-clock-rates = <24000000>; |
| power-domains = <&pd_mipi_csi_i2c0>; |
| status = "disabled"; |
| }; |
| |
| intmux_cm40: intmux@37400000 { |
| compatible = "nxp,imx-intmux"; |
| reg = <0x0 0x37400000 0x0 0x1000>; |
| interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-controller; |
| interrupt-parent = <&gic>; |
| #interrupt-cells = <2>; |
| clocks = <&clk IMX8QXP_CM40_IPG_CLK>; |
| clock-names = "ipg"; |
| power-domains = <&pd_cm40_intmux>; |
| status = "disabled"; |
| }; |
| |
| i2c0_cm40: i2c@37230000 { |
| compatible = "fsl,imx8qm-lpi2c"; |
| reg = <0x0 0x37230000 0x0 0x1000>; |
| interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&intmux_cm40>; |
| clocks = <&clk IMX8QXP_CM40_I2C_CLK>, |
| <&clk IMX8QXP_CM40_I2C_IPG_CLK>; |
| clock-names = "per", "ipg"; |
| assigned-clocks = <&clk IMX8QXP_CM40_I2C_CLK>; |
| assigned-clock-rates = <24000000>; |
| power-domains = <&pd_cm40_i2c>; |
| status = "disabled"; |
| }; |
| |
| dpu_intsteer: dpu_intsteer@56000000 { |
| compatible = "fsl,imx8qxp-dpu-intsteer", "syscon"; |
| reg = <0x0 0x56000000 0x0 0x10000>; |
| }; |
| |
| dpu1: dpu@56180000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx8qxp-dpu", "fsl,imx8qm-dpu"; |
| reg = <0x0 0x56180000 0x0 0x40000>; |
| intsteer = <&dpu_intsteer>; |
| interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "irq_common", |
| "irq_stream0a", |
| "irq_stream0b", /* to M4? */ |
| "irq_stream1a", |
| "irq_stream1b", /* to M4? */ |
| "irq_reserved0", |
| "irq_reserved1", |
| "irq_blit"; |
| clocks = <&clk IMX8QXP_DC0_PLL0_CLK>, |
| <&clk IMX8QXP_DC0_PLL1_CLK>, |
| <&clk IMX8QXP_DC0_DISP0_CLK>, |
| <&clk IMX8QXP_DC0_DISP1_CLK>; |
| clock-names = "pll0", "pll1", "disp0", "disp1"; |
| power-domains = <&pd_dc0>; |
| status = "disabled"; |
| |
| dpu_disp0: port@0 { |
| reg = <0>; |
| |
| dpu_disp0_lvds0_ch0: lvds0-endpoint { |
| remote-endpoint = <&ldb1_ch0>; |
| }; |
| |
| dpu_disp0_lvds0_ch1: lvds1-endpoint { |
| remote-endpoint = <&ldb1_ch1>; |
| }; |
| |
| dpu_disp0_mipi_dsi: mipi-dsi-endpoint { |
| }; |
| }; |
| |
| dpu_disp1: port@1 { |
| reg = <1>; |
| |
| dpu_disp1_lvds1_ch0: lvds0-endpoint { |
| remote-endpoint = <&ldb2_ch0>; |
| }; |
| |
| dpu_disp1_lvds1_ch1: lvds1-endpoint { |
| remote-endpoint = <&ldb2_ch1>; |
| }; |
| |
| dpu_disp1_mipi_dsi: mipi-dsi-endpoint { |
| }; |
| }; |
| }; |
| |
| irqsteer_mipi_lvds0: irqsteer@56220000 { |
| compatible = "nxp,imx-irqsteer"; |
| reg = <0x0 0x56220000 0x0 0x1000>; |
| interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-controller; |
| interrupt-parent = <&gic>; |
| #interrupt-cells = <2>; |
| clocks = <&clk IMX8QXP_MIPI0_LIS_IPG_CLK>; |
| clock-names = "ipg"; |
| power-domains = <&pd_mipi_dsi0>; |
| }; |
| |
| lvds_region1: lvds_region@56220000 { |
| compatible = "fsl,imx8qxp-lvds-region", "syscon"; |
| reg = <0x0 0x56220000 0x0 0x10000>; |
| }; |
| |
| ldb1_phy: ldb_phy@56221000 { |
| compatible = "mixel,lvds-combo-phy"; |
| reg = <0x0 0x56221000 0x0 0x100>, <0x0 0x56228000 0x0 0x1000>; |
| #phy-cells = <0>; |
| clocks = <&clk IMX8QXP_MIPI0_LVDS_PHY_CLK>; |
| clock-names = "phy"; |
| power-domains = <&pd_mipi_dsi0>; |
| status = "disabled"; |
| }; |
| |
| ldb1: ldb@562210e0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx8qxp-ldb"; |
| clocks = <&clk IMX8QXP_MIPI0_LVDS_PIXEL_CLK>, |
| <&clk IMX8QXP_MIPI0_LVDS_BYPASS_CLK>; |
| clock-names = "pixel", "bypass"; |
| power-domains = <&pd_mipi_dsi0>; |
| gpr = <&lvds_region1>; |
| status = "disabled"; |
| |
| lvds-channel@0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0>; |
| phys = <&ldb1_phy>; |
| phy-names = "ldb_phy"; |
| status = "disabled"; |
| |
| port@0 { |
| reg = <0>; |
| |
| ldb1_ch0: endpoint { |
| remote-endpoint = <&dpu_disp0_lvds0_ch0>; |
| }; |
| }; |
| }; |
| |
| lvds-channel@1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <1>; |
| phys = <&ldb1_phy>; |
| phy-names = "ldb_phy"; |
| status = "disabled"; |
| |
| port@0 { |
| reg = <0>; |
| |
| ldb1_ch1: endpoint { |
| remote-endpoint = <&dpu_disp0_lvds0_ch1>; |
| }; |
| }; |
| }; |
| }; |
| |
| i2c0_mipi_lvds0: i2c@56226000 { |
| compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c"; |
| reg = <0x0 0x56226000 0x0 0x1000>; |
| interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&irqsteer_mipi_lvds0>; |
| clocks = <&clk IMX8QXP_MIPI0_I2C0_CLK>, |
| <&clk IMX8QXP_MIPI0_I2C0_IPG_CLK>; |
| clock-names = "per", "ipg"; |
| assigned-clocks = <&clk IMX8QXP_MIPI0_I2C0_DIV>; |
| assigned-clock-rates = <24000000>; |
| power-domains = <&pd_mipi_dsi_0_i2c0>; |
| status = "disabled"; |
| }; |
| |
| irqsteer_mipi_lvds1: irqsteer@56240000 { |
| compatible = "nxp,imx-irqsteer"; |
| reg = <0x0 0x56240000 0x0 0x1000>; |
| interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-controller; |
| interrupt-parent = <&gic>; |
| #interrupt-cells = <2>; |
| clocks = <&clk IMX8QXP_MIPI1_LIS_IPG_CLK>; |
| clock-names = "ipg"; |
| power-domains = <&pd_mipi_dsi1>; |
| }; |
| |
| lvds_region2: lvds_region@56240000 { |
| compatible = "fsl,imx8qxp-lvds-region", "syscon"; |
| reg = <0x0 0x56240000 0x0 0x10000>; |
| }; |
| |
| ldb2_phy: ldb_phy@56241000 { |
| compatible = "mixel,lvds-combo-phy"; |
| reg = <0x0 0x56241000 0x0 0x100>, <0x0 0x56248000 0x0 0x1000>; |
| #phy-cells = <0>; |
| clocks = <&clk IMX8QXP_MIPI1_LVDS_PHY_CLK>; |
| clock-names = "phy"; |
| power-domains = <&pd_mipi_dsi1>; |
| status = "disabled"; |
| }; |
| |
| ldb2: ldb@562410e0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx8qxp-ldb"; |
| clocks = <&clk IMX8QXP_MIPI1_LVDS_PIXEL_CLK>, |
| <&clk IMX8QXP_MIPI1_LVDS_BYPASS_CLK>; |
| clock-names = "pixel", "bypass"; |
| power-domains = <&pd_mipi_dsi1>; |
| gpr = <&lvds_region2>; |
| status = "disabled"; |
| |
| lvds-channel@0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0>; |
| phys = <&ldb2_phy>; |
| phy-names = "ldb_phy"; |
| status = "disabled"; |
| |
| port@0 { |
| reg = <0>; |
| |
| ldb2_ch0: endpoint { |
| remote-endpoint = <&dpu_disp1_lvds1_ch0>; |
| }; |
| }; |
| }; |
| |
| lvds-channel@1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <1>; |
| phys = <&ldb2_phy>; |
| phy-names = "ldb_phy"; |
| status = "disabled"; |
| |
| port@0 { |
| reg = <0>; |
| |
| ldb2_ch1: endpoint { |
| remote-endpoint = <&dpu_disp1_lvds1_ch1>; |
| }; |
| }; |
| }; |
| }; |
| |
| camera { |
| compatible = "fsl,mxc-md", "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| isi_0: isi@58100000 { |
| compatible = "fsl,imx8-isi"; |
| reg = <0x0 0x58100000 0x0 0x10000>; |
| interrupts = <0 297 0>; |
| interface = <2 0 2>; /* <Input MIPI_VCx Output> |
| Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM |
| VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only |
| Output: 0-DC0, 1-DC1, 2-MEM */ |
| clocks = <&clk IMX8QXP_IMG_PDMA_0_CLK>; |
| clock-names = "per"; |
| assigned-clocks = <&clk IMX8QXP_IMG_PDMA_0_CLK>; |
| assigned-clock-rates = <600000000>; |
| power-domains =<&pd_isi_ch0>; |
| status = "disabled"; |
| }; |
| |
| isi_1: isi@58110000 { |
| compatible = "fsl,imx8-isi"; |
| reg = <0x0 0x58110000 0x0 0x10000>; |
| interrupts = <0 298 0>; |
| interface = <2 1 2>; |
| clocks = <&clk IMX8QXP_IMG_PDMA_1_CLK>; |
| clock-names = "per"; |
| assigned-clocks = <&clk IMX8QXP_IMG_PDMA_1_CLK>; |
| assigned-clock-rates = <600000000>; |
| power-domains =<&pd_isi_ch1>; |
| status = "disabled"; |
| }; |
| |
| isi_2: isi@58120000 { |
| compatible = "fsl,imx8-isi"; |
| reg = <0x0 0x58120000 0x0 0x10000>; |
| interrupts = <0 299 0>; |
| interface = <2 2 2>; |
| clocks = <&clk IMX8QXP_IMG_PDMA_2_CLK>; |
| clock-names = "per"; |
| assigned-clocks = <&clk IMX8QXP_IMG_PDMA_2_CLK>; |
| assigned-clock-rates = <600000000>; |
| power-domains =<&pd_isi_ch2>; |
| status = "disabled"; |
| }; |
| |
| isi_3: isi@58130000 { |
| compatible = "fsl,imx8-isi"; |
| reg = <0x0 0x58130000 0x0 0x10000>; |
| interrupts = <0 300 0>; |
| interface = <2 3 2>; |
| clocks = <&clk IMX8QXP_IMG_PDMA_3_CLK>; |
| clock-names = "per"; |
| assigned-clocks = <&clk IMX8QXP_IMG_PDMA_3_CLK>; |
| assigned-clock-rates = <600000000>; |
| power-domains =<&pd_isi_ch3>; |
| status = "disabled"; |
| }; |
| |
| isi_4: isi@58140000 { |
| compatible = "fsl,imx8-isi"; |
| reg = <0x0 0x58140000 0x0 0x10000>; |
| interrupts = <0 301 0>; |
| interface = <3 0 2>; |
| clocks = <&clk IMX8QXP_IMG_PDMA_4_CLK>; |
| clock-names = "per"; |
| assigned-clocks = <&clk IMX8QXP_IMG_PDMA_4_CLK>; |
| assigned-clock-rates = <600000000>; |
| power-domains =<&pd_isi_ch4>; |
| status = "disabled"; |
| }; |
| |
| isi_5: isi@58150000 { |
| compatible = "fsl,imx8-isi"; |
| reg = <0x0 0x58150000 0x0 0x10000>; |
| interrupts = <0 302 0>; |
| interface = <3 1 2>; |
| clocks = <&clk IMX8QXP_IMG_PDMA_5_CLK>; |
| clock-names = "per"; |
| assigned-clocks = <&clk IMX8QXP_IMG_PDMA_5_CLK>; |
| assigned-clock-rates = <600000000>; |
| power-domains =<&pd_isi_ch5>; |
| status = "disabled"; |
| }; |
| |
| isi_6: isi@58160000 { |
| compatible = "fsl,imx8-isi"; |
| reg = <0x0 0x58160000 0x0 0x10000>; |
| interrupts = <0 303 0>; |
| interface = <3 2 2>; |
| clocks = <&clk IMX8QXP_IMG_PDMA_6_CLK>; |
| clock-names = "per"; |
| assigned-clocks = <&clk IMX8QXP_IMG_PDMA_6_CLK>; |
| assigned-clock-rates = <600000000>; |
| power-domains =<&pd_isi_ch6>; |
| status = "disabled"; |
| }; |
| |
| isi_7: isi@58170000 { |
| compatible = "fsl,imx8-isi"; |
| reg = <0x0 0x58170000 0x0 0x10000>; |
| interrupts = <0 304 0>; |
| interface = <3 3 2>; |
| clocks = <&clk IMX8QXP_IMG_PDMA_7_CLK>; |
| clock-names = "per"; |
| assigned-clocks = <&clk IMX8QXP_IMG_PDMA_7_CLK>; |
| assigned-clock-rates = <600000000>; |
| power-domains =<&pd_isi_ch7>; |
| status = "disabled"; |
| }; |
| |
| mipi_csi_0: csi@58227000 { |
| compatible = "fsl,mxc-mipi-csi2"; |
| reg = <0x0 0x58227000 0x0 0x1000>, /* CSI0 Controler base addr */ |
| <0x0 0x58221000 0x0 0x1000>; /* CSI0 Subsystem CSR base addr */ |
| interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&irqsteer_csi>; |
| clocks = <&clk IMX8QXP_CSI0_APB_CLK>, |
| <&clk IMX8QXP_CSI0_CORE_CLK>, |
| <&clk IMX8QXP_CSI0_ESC_CLK>, |
| <&clk IMX8QXP_IMG_PXL_LINK_CSI0_CLK>; |
| clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl"; |
| assigned-clocks = <&clk IMX8QXP_CSI0_CORE_CLK>, |
| <&clk IMX8QXP_CSI0_ESC_CLK>; |
| assigned-clock-rates = <360000000>, <72000000>; |
| power-domains = <&pd_mipi_csi>; |
| status = "disabled"; |
| }; |
| }; |
| |
| i2c0_mipi_lvds1: i2c@56246000 { |
| compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c"; |
| reg = <0x0 0x56246000 0x0 0x1000>; |
| interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&irqsteer_mipi_lvds1>; |
| clocks = <&clk IMX8QXP_MIPI1_I2C0_CLK>, |
| <&clk IMX8QXP_MIPI1_I2C0_IPG_CLK>; |
| clock-names = "per", "ipg"; |
| assigned-clocks = <&clk IMX8QXP_MIPI1_I2C0_DIV>; |
| assigned-clock-rates = <24000000>; |
| power-domains = <&pd_mipi_dsi_1_i2c0>; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@5a800000 { |
| compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; |
| reg = <0x0 0x5a800000 0x0 0x4000>; |
| interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| clocks = <&clk IMX8QXP_I2C0_CLK>; |
| clock-names = "per"; |
| assigned-clocks = <&clk IMX8QXP_I2C0_CLK>; |
| assigned-clock-rates = <24000000>; |
| power-domains = <&pd_dma_lpi2c0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@5a810000 { |
| compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; |
| reg = <0x0 0x5a810000 0x0 0x4000>; |
| interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| clocks = <&clk IMX8QXP_I2C1_CLK>, |
| <&clk IMX8QXP_I2C1_IPG_CLK>; |
| clock-names = "per", "ipg"; |
| assigned-clocks = <&clk IMX8QXP_I2C1_CLK>; |
| assigned-clock-rates = <24000000>; |
| power-domains = <&pd_dma_lpi2c1>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@5a820000 { |
| compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; |
| reg = <0x0 0x5a820000 0x0 0x4000>; |
| interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| clocks = <&clk IMX8QXP_I2C2_CLK>; |
| clock-names = "per"; |
| assigned-clocks = <&clk IMX8QXP_I2C2_CLK>; |
| assigned-clock-rates = <24000000>; |
| power-domains = <&pd_dma_lpi2c2>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@5a830000 { |
| compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; |
| reg = <0x0 0x5a830000 0x0 0x4000>; |
| interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| clocks = <&clk IMX8QXP_I2C3_CLK>, |
| <&clk IMX8QXP_I2C3_IPG_CLK>; |
| clock-names = "per", "ipg"; |
| assigned-clocks = <&clk IMX8QXP_I2C3_CLK>; |
| assigned-clock-rates = <24000000>; |
| power-domains = <&pd_dma_lpi2c3>; |
| status = "disabled"; |
| }; |
| |
| usbmisc1: usbmisc@5b0d0200 { |
| #index-cells = <1>; |
| compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; |
| reg = <0x0 0x5b0d0200 0x0 0x200>; |
| }; |
| |
| usbphy1: usbphy@0x5b100000 { |
| compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; |
| reg = <0x0 0x5b100000 0x0 0x200>; |
| clocks = <&clk IMX8QXP_USB2_PHY_IPG_CLK>; |
| power-domains = <&pd_conn_usbotg0_phy>; |
| }; |
| |
| usbotg1: usb@5b0d0000 { |
| compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; |
| reg = <0x0 0x5b0d0000 0x0 0x200>; |
| interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; |
| fsl,usbphy = <&usbphy1>; |
| fsl,usbmisc = <&usbmisc1 0>; |
| clocks = <&clk IMX8QXP_USB2_OH_AHB_CLK>; |
| phy-clkgate-delay-us = <400>; |
| status = "disabled"; |
| #stream-id-cells = <1>; |
| power-domains = <&pd_conn_usbotg0>; |
| }; |
| |
| usb2_phy: phy@0x5b160000 { |
| compatible = "fsl,imx8-usb-phy"; |
| reg = <0x0 0x5b160000 0x0 0x10000>; |
| power-domains = <&pd_conn_usb2_phy>; |
| }; |
| |
| usb2: usb@0x5b110000 { |
| compatible = "fsl,imx8-usb3"; |
| reg = <0x0 0x5b110000 0x0 0x38000>; |
| fsl,usbphy = <&usb2_phy>; |
| status = "disabled"; |
| power-domains = <&pd_conn_usb2>; |
| }; |
| |
| flexcan1: can@5a8d0000 { |
| compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; |
| reg = <0x0 0x5a8d0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, |
| <&clk IMX8QXP_CAN0_CLK>; |
| clock-names = "ipg", "per"; |
| assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; |
| assigned-clock-rates = <40000000>; |
| power-domains = <&pd_dma_flexcan0>; |
| status = "disabled"; |
| }; |
| |
| flexcan2: can@5a8e0000 { |
| compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; |
| reg = <0x0 0x5a8e0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; |
| /* CAN0 clock and PD is shared among all CAN instances */ |
| clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, |
| <&clk IMX8QXP_CAN0_CLK>; |
| clock-names = "ipg", "per"; |
| assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; |
| assigned-clock-rates = <40000000>; |
| power-domains = <&pd_dma_flexcan0>; |
| status = "disabled"; |
| }; |
| |
| flexcan3: can@5a8f0000 { |
| compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; |
| reg = <0x0 0x5a8f0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; |
| /* CAN0 clock and PD is shared among all CAN instances */ |
| clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, |
| <&clk IMX8QXP_CAN0_CLK>; |
| clock-names = "ipg", "per"; |
| assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; |
| assigned-clock-rates = <40000000>; |
| power-domains = <&pd_dma_flexcan0>; |
| status = "disabled"; |
| }; |
| |
| dma_apbh: dma-apbh@5b810000 { |
| compatible = "fsl,imx28-dma-apbh"; |
| reg = <0x0 0x5b810000 0x0 0x2000>; |
| interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; |
| #dma-cells = <1>; |
| dma-channels = <4>; |
| clocks = <&clk IMX8QXP_APBHDMA_CLK>; |
| power-domains = <&pd_conn_nand>; |
| }; |
| |
| gpmi: gpmi-nand@5b812000{ |
| compatible = "fsl,imx8qxp-gpmi-nand"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x0 0x5b812000 0x0 0x2000>, <0x0 0x5b814000 0x0 0x2000>; |
| reg-names = "gpmi-nand", "bch"; |
| interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "bch"; |
| clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>, |
| <&clk IMX8QXP_GPMI_APB_CLK>, |
| <&clk IMX8QXP_GPMI_BCH_CLK>, |
| <&clk IMX8QXP_GPMI_APB_BCH_CLK>; |
| clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_apb_bch"; |
| dmas = <&dma_apbh 0>; |
| dma-names = "rx-tx"; |
| power-domains = <&pd_conn_nand>; |
| status = "disabled"; |
| }; |
| |
| gpu_3d0: gpu@53100000 { |
| compatible = "fsl,imx8-gpu"; |
| reg = <0x0 0x53100000 0 0x40000>; |
| interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>; |
| clock-names = "core", "shader"; |
| assigned-clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>; |
| assigned-clock-rates = <600000000>, <850000000>; |
| power-domains = <&pd_gpu0>; |
| status = "disabled"; |
| }; |
| |
| imx8_gpu_ss: imx8_gpu_ss { |
| compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss"; |
| cores = <&gpu_3d0>; |
| reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>; |
| reg-names = "phys_baseaddr", "contiguous_mem"; |
| status = "disabled"; |
| }; |
| |
| ddr_pmu0: ddr_pmu@5c020000 { |
| compatible = "fsl,imx8-ddr-pmu"; |
| reg = <0x0 0x5c020000 0x0 0x10000>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| lpuart0: serial@5a060000 { |
| compatible = "fsl,imx8qm-lpuart"; |
| reg = <0x0 0x5a060000 0x0 0x1000>; |
| interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| clocks = <&clk IMX8QXP_UART0_CLK>, |
| <&clk IMX8QXP_UART0_IPG_CLK>; |
| clock-names = "per", "ipg"; |
| assigned-clocks = <&clk IMX8QXP_UART0_CLK>; |
| assigned-clock-rates = <80000000>; |
| power-domains = <&pd_dma_lpuart0>; |
| status = "disabled"; |
| }; |
| |
| lpuart1: serial@5a070000 { |
| compatible = "fsl,imx8qm-lpuart"; |
| reg = <0x0 0x5a070000 0x0 0x1000>; |
| interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| clocks = <&clk IMX8QXP_UART1_CLK>, |
| <&clk IMX8QXP_UART1_IPG_CLK>; |
| clock-names = "per", "ipg"; |
| assigned-clocks = <&clk IMX8QXP_UART1_CLK>; |
| assigned-clock-rates = <80000000>; |
| power-domains = <&pd_dma_lpuart1>; |
| dma-names = "tx","rx"; |
| dmas = <&edma0 11 0 0>, |
| <&edma0 10 0 1>; |
| status = "disabled"; |
| }; |
| |
| lpuart2: serial@5a080000 { |
| compatible = "fsl,imx8qm-lpuart"; |
| reg = <0x0 0x5a080000 0x0 0x1000>; |
| interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| clocks = <&clk IMX8QXP_UART2_CLK>, |
| <&clk IMX8QXP_UART2_IPG_CLK>; |
| clock-names = "per", "ipg"; |
| assigned-clocks = <&clk IMX8QXP_UART2_CLK>; |
| assigned-clock-rates = <80000000>; |
| power-domains = <&pd_dma_lpuart2>; |
| dma-names = "tx","rx"; |
| dmas = <&edma0 13 0 0>, |
| <&edma0 12 0 1>; |
| status = "disabled"; |
| }; |
| |
| lpuart3: serial@5a090000 { |
| compatible = "fsl,imx8qm-lpuart"; |
| reg = <0x0 0x5a090000 0x0 0x1000>; |
| interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| clocks = <&clk IMX8QXP_UART3_CLK>, |
| <&clk IMX8QXP_UART3_IPG_CLK>; |
| clock-names = "per", "ipg"; |
| assigned-clocks = <&clk IMX8QXP_UART3_CLK>; |
| assigned-clock-rates = <80000000>; |
| power-domains = <&pd_dma_lpuart3>; |
| dma-names = "tx","rx"; |
| dmas = <&edma0 15 0 0>, |
| <&edma0 14 0 1>; |
| status = "disabled"; |
| }; |
| |
| edma0: dma-controller@5a1f0000 { |
| compatible = "fsl,imx8qm-edma"; |
| reg = <0x0 0x5a280000 0x0 0x10000>, /* channel8 UART0 rx */ |
| <0x0 0x5a290000 0x0 0x10000>, /* channel9 UART0 tx */ |
| <0x0 0x5a2a0000 0x0 0x10000>, /* channel10 UART1 rx */ |
| <0x0 0x5a2b0000 0x0 0x10000>, /* channel11 UART1 tx */ |
| <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART2 rx */ |
| <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART2 tx */ |
| <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART3 rx */ |
| <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART3 tx */ |
| #dma-cells = <3>; |
| dma-channels = <8>; |
| interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "edma-chan8-tx", "edma-chan9-tx", |
| "edma-chan10-tx", "edma-chan11-tx", |
| "edma-chan12-tx", "edma-chan13-tx", |
| "edma-chan14-tx", "edma-chan15-tx"; |
| status = "okay"; |
| }; |
| |
| edma2: dma-controller@591F0000 { |
| compatible = "fsl,imx8qm-edma"; |
| reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */ |
| <0x0 0x59210000 0x0 0x10000>, |
| <0x0 0x59220000 0x0 0x10000>, |
| <0x0 0x59230000 0x0 0x10000>, |
| <0x0 0x59240000 0x0 0x10000>, |
| <0x0 0x59250000 0x0 0x10000>, |
| <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */ |
| <0x0 0x59270000 0x0 0x10000>, /* esai0 tx */ |
| <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */ |
| <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */ |
| <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ |
| <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */ |
| <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */ |
| <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */ |
| <0x0 0x59350000 0x0 0x10000>, |
| <0x0 0x59370000 0x0 0x10000>; |
| #dma-cells = <3>; |
| shared-interrupt; |
| dma-channels = <16>; |
| interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */ |
| <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */ |
| <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ |
| <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ |
| <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ |
| <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "edma-chan0-tx", "edma-chan1-tx", /* asrc0 */ |
| "edma-chan2-tx", "edma-chan3-tx", |
| "edma-chan4-tx", "edma-chan5-tx", |
| "edma-chan6-tx", "edma-chan7-tx", /* esai0 */ |
| "edma-chan8-tx", "edma-chan9-tx", /* spdif0 */ |
| "edma-chan12-tx", "edma-chan13-tx", /* sai0 */ |
| "edma-chan14-tx", "edma-chan15-tx", /* sai1 */ |
| "edma-chan21-tx", /* gpt5 */ |
| "edma-chan23-tx"; /* gpt7 */ |
| status = "okay"; |
| }; |
| |
| edma3: dma-controller@599F0000 { |
| compatible = "fsl,imx8qm-edma"; |
| reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */ |
| <0x0 0x59A10000 0x0 0x10000>, |
| <0x0 0x59A20000 0x0 0x10000>, |
| <0x0 0x59A30000 0x0 0x10000>, |
| <0x0 0x59A40000 0x0 0x10000>, |
| <0x0 0x59A50000 0x0 0x10000>, |
| <0x0 0x59A80000 0x0 0x10000>, /* sai4 rx */ |
| <0x0 0x59A90000 0x0 0x10000>, /* sai4 tx */ |
| <0x0 0x59AA0000 0x0 0x10000>; /* sai5 tx */ |
| #dma-cells = <3>; |
| shared-interrupt; |
| dma-channels = <9>; |
| interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc 1 */ |
| <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */ |
| <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */ |
| interrupt-names = "edma-chan0-tx", "edma-chan1-tx", /* asrc1 */ |
| "edma-chan2-tx", "edma-chan3-tx", |
| "edma-chan4-tx", "edma-chan5-tx", |
| "edma-chan8-tx", "edma-chan9-tx", /* sai4 */ |
| "edma-chan10-tx"; /* sai5 */ |
| status = "okay"; |
| }; |
| |
| acm: acm@59e00000 { |
| compatible = "nxp,imx8qm-acm"; |
| reg = <0x0 0x59e00000 0x0 0x1D0000>; |
| status = "disabled"; |
| }; |
| |
| sai0: sai@59040000 { |
| compatible = "fsl,imx8qm-sai"; |
| reg = <0x0 0x59040000 0x0 0x10000>; |
| interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8QXP_AUD_SAI_0_IPG>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_AUD_SAI_0_MCLK>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>; |
| clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; |
| dma-names = "rx", "tx"; |
| dmas = <&edma2 12 0 1>, <&edma2 13 0 0>; |
| status = "disabled"; |
| power-domains = <&pd_sai0>; |
| }; |
| |
| sai1: sai@59050000 { |
| compatible = "fsl,imx8qm-sai"; |
| reg = <0x0 0x59050000 0x0 0x10000>; |
| interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8QXP_AUD_SAI_1_IPG>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_AUD_SAI_1_MCLK>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>; |
| clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; |
| dma-names = "rx", "tx"; |
| dmas = <&edma2 14 0 1>, <&edma2 15 0 0>; |
| status = "disabled"; |
| power-domains = <&pd_sai1>; |
| }; |
| |
| sai4: sai@59820000 { |
| compatible = "fsl,imx8qm-sai"; |
| reg = <0x0 0x59820000 0x0 0x10000>; |
| interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8QXP_AUD_SAI_4_IPG>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_AUD_SAI_4_MCLK>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>; |
| dmas = <&edma3 8 0 1>, <&edma3 9 0 0>; |
| clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| power-domains = <&pd_sai4>; |
| }; |
| |
| sai5: sai@59830000 { |
| compatible = "fsl,imx8qm-sai"; |
| reg = <0x0 0x59830000 0x0 0x10000>; |
| interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8QXP_AUD_SAI_5_IPG>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_AUD_SAI_5_MCLK>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>; |
| clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; |
| dma-names = "tx"; |
| dmas = <&edma3 10 0 0>; |
| status = "disabled"; |
| power-domains = <&pd_sai5>; |
| }; |
| |
| amix: amix@59840000 { |
| compatible = "fsl,imx8qm-amix"; |
| reg = <0x0 0x59840000 0x0 0x10000>; |
| clocks = <&clk IMX8QXP_AUD_AMIX_IPG>; |
| clock-names = "ipg"; |
| power-domains = <&pd_amix>; |
| status = "disabled"; |
| }; |
| |
| asrc0: asrc@59000000 { |
| compatible = "fsl,imx8qm-asrc0"; |
| reg = <0x0 0x59000000 0x0 0x10000>; |
| interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8QXP_AUD_ASRC_0_IPG>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, |
| <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>; |
| clock-names = "ipg", "mem", |
| "asrck_0", "asrck_1", "asrck_2", "asrck_3", |
| "asrck_4", "asrck_5", "asrck_6", "asrck_7", |
| "asrck_8", "asrck_9", "asrck_a", "asrck_b", |
| "asrck_c", "asrck_d", "asrck_e", "asrck_f", |
| "spba"; |
| dmas = <&edma2 0 0 0>, <&edma2 1 0 0>, <&edma2 2 0 0>, |
| <&edma2 3 0 1>, <&edma2 4 0 1>, <&edma2 5 0 1>; |
| dma-names = "rxa", "rxb", "rxc", |
| "txa", "txb", "txc"; |
| fsl,asrc-rate = <8000>; |
| fsl,asrc-width = <16>; |
| power-domains = <&pd_asrc0>; |
| status = "disabled"; |
| }; |
| |
| asrc1: asrc@59800000 { |
| compatible = "fsl,imx8qm-asrc1"; |
| reg = <0x0 0x59800000 0x0 0x10000>; |
| interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8QXP_AUD_ASRC_1_IPG>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, |
| <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>, |
| <&clk IMX8QXP_CLK_DUMMY>; |
| clock-names = "ipg", "mem", |
| "asrck_0", "asrck_1", "asrck_2", "asrck_3", |
| "asrck_4", "asrck_5", "asrck_6", "asrck_7", |
| "asrck_8", "asrck_9", "asrck_a", "asrck_b", |
| "asrck_c", "asrck_d", "asrck_e", "asrck_f", |
| "spba"; |
| dmas = <&edma3 0 0 0>, <&edma3 1 0 0>, <&edma3 2 0 0>, |
| <&edma3 3 0 1>, <&edma3 4 0 1>, <&edma3 5 0 1>; |
| dma-names = "rxa", "rxb", "rxc", |
| "txa", "txb", "txc"; |
| fsl,asrc-rate = <8000>; |
| fsl,asrc-width = <16>; |
| power-domains = <&pd_asrc1>; |
| status = "disabled"; |
| }; |
| |
| mqs: mqs@59850000 { |
| compatible = "fsl,imx8qm-mqs"; |
| reg = <0x0 0x59850000 0x0 0x10000>; |
| clocks = <&clk IMX8QXP_AUD_MQS_IPG>, |
| <&clk IMX8QXP_AUD_MQS_HMCLK>; |
| clock-names = "core", "mclk"; |
| power-domains = <&pd_mqs0>; |
| status = "disabled"; |
| }; |
| |
| usdhc1: usdhc@5b010000 { |
| compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0 0x5b010000 0x0 0x10000>; |
| clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>, |
| <&clk IMX8QXP_SDHC0_CLK>, |
| <&clk IMX8QXP_CLK_DUMMY>; |
| clock-names = "ipg", "per", "ahb"; |
| assigned-clocks = <&clk IMX8QXP_SDHC0_DIV>; |
| assigned-clock-rates = <400000000>; |
| power-domains = <&pd_conn_sdch0>; |
| fsl,tuning-start-tap = <20>; |
| fsl,tuning-step= <2>; |
| status = "disabled"; |
| }; |
| |
| usdhc2: usdhc@5b020000 { |
| compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0 0x5b020000 0x0 0x10000>; |
| clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>, |
| <&clk IMX8QXP_SDHC1_CLK>, |
| <&clk IMX8QXP_CLK_DUMMY>; |
| clock-names = "ipg", "per", "ahb"; |
| assigned-clocks = <&clk IMX8QXP_SDHC1_DIV>; |
| assigned-clock-rates = <200000000>; |
| power-domains = <&pd_conn_sdch1>; |
| fsl,tuning-start-tap = <20>; |
| fsl,tuning-step= <2>; |
| status = "disabled"; |
| }; |
| |
| usdhc3: usdhc@5b030000 { |
| compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0 0x5b030000 0x0 0x10000>; |
| clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>, |
| <&clk IMX8QXP_SDHC2_CLK>, |
| <&clk IMX8QXP_CLK_DUMMY>; |
| clock-names = "ipg", "per", "ahb"; |
| assigned-clocks = <&clk IMX8QXP_SDHC2_DIV>; |
| assigned-clock-rates = <200000000>; |
| power-domains = <&pd_conn_sdch2>; |
| fsl,tuning-start-tap = <20>; |
| fsl,tuning-step = <2>; |
| status = "disabled"; |
| }; |
| |
| fec1: ethernet@5b040000 { |
| compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec"; |
| reg = <0x0 0x5b040000 0x0 0x10000>; |
| interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, <&clk IMX8QXP_ENET0_RGMII_TX_CLK>, |
| <&clk IMX8QXP_ENET0_PTP_CLK>, <&clk IMX8QXP_ENET0_TX_CLK>; |
| clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; |
| assigned-clocks = <&clk IMX8QXP_ENET0_ROOT_DIV>, |
| <&clk IMX8QXP_ENET0_REF_DIV>, |
| <&clk IMX8QXP_ENET0_PTP_CLK>; |
| assigned-clock-rates = <250000000>, <125000000>, <125000000>; |
| fsl,num-tx-queues=<3>; |
| fsl,num-rx-queues=<3>; |
| power-domains = <&pd_conn_enet0>; |
| status = "disabled"; |
| }; |
| |
| fec2: ethernet@5b050000 { |
| compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec"; |
| reg = <0x0 0x5b050000 0x0 0x10000>; |
| interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>, <&clk IMX8QXP_ENET1_RGMII_TX_CLK>, |
| <&clk IMX8QXP_ENET1_PTP_CLK>, <&clk IMX8QXP_ENET1_TX_CLK>; |
| clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; |
| assigned-clocks = <&clk IMX8QXP_ENET1_ROOT_DIV>, |
| <&clk IMX8QXP_ENET1_REF_DIV>, |
| <&clk IMX8QXP_ENET1_PTP_CLK>; |
| assigned-clock-rates = <250000000>, <125000000>, <125000000>; |
| fsl,num-tx-queues=<3>; |
| fsl,num-rx-queues=<3>; |
| power-domains = <&pd_conn_enet1>; |
| status = "disabled"; |
| }; |
| |
| mlb: mlb@5B060000 { |
| compatible = "fsl,imx6q-mlb150"; |
| reg = <0x0 0x5B060000 0x0 0x10000>; |
| interrupt-parent = <&gic>; |
| interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>, |
| <0 266 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8QXP_MLB_CLK>, |
| <&clk IMX8QXP_MLB_HCLK>, |
| <&clk IMX8QXP_MLB_IPG_CLK>; |
| clock-names = "mlb", "hclk", "ipg"; |
| assigned-clocks = <&clk IMX8QXP_MLB_CLK>, |
| <&clk IMX8QXP_MLB_HCLK>, |
| <&clk IMX8QXP_MLB_IPG_CLK>; |
| assigned-clock-rates = <333333333>, <333333333>, <83333333>; |
| power-domains = <&pd_conn_mlb0>; |
| status = "disabled"; |
| }; |
| |
| hifi4: hifi4@586e8000 { |
| compatible = "fsl,imx8qxp-hifi4"; |
| reg = <0x0 0x596e8000 0x0 0x88000>; |
| clocks = <&clk IMX8QXP_AUD_HIFI_IPG>, |
| <&clk IMX8QXP_AUD_OCRAM_IPG>, |
| <&clk IMX8QXP_AUD_HIFI_CORE_CLK>; |
| clock-names = "ipg", "ocram", "core"; |
| fsl,hifi4-firmware = "imx/hifi/hifi4.bin"; |
| power-domains = <&pd_hifi>; |
| }; |
| |
| esai0: esai@59010000 { |
| compatible = "fsl,imx6ull-esai"; |
| reg = <0x0 0x59010000 0x0 0x10000>; |
| interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8QXP_AUD_ESAI_0_IPG>, |
| <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>, |
| <&clk IMX8QXP_AUD_ESAI_0_IPG>; |
| clock-names = "core", "extal", "fsys"; |
| dmas = <&edma2 6 0 1>, <&edma2 7 0 0>; |
| dma-names = "rx", "tx"; |
| power-domains = <&pd_esai0>; |
| status = "disabled"; |
| }; |
| |
| spdif0: spdif@59020000 { |
| compatible = "fsl,imx8qm-spdif"; |
| reg = <0x0 0x59020000 0x0 0x10000>; |
| interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */ |
| <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */ |
| clocks = <&clk IMX8QXP_AUD_SPDIF_0_GCLKW>, /* core */ |
| <&clk IMX8QXP_CLK_DUMMY>, /* rxtx0 */ |
| <&clk IMX8QXP_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */ |
| <&clk IMX8QXP_CLK_DUMMY>, /* rxtx2 */ |
| <&clk IMX8QXP_CLK_DUMMY>, /* rxtx3 */ |
| <&clk IMX8QXP_CLK_DUMMY>, /* rxtx4 */ |
| <&clk IMX8QXP_IPG_AUD_CLK_ROOT>, /* rxtx5 */ |
| <&clk IMX8QXP_CLK_DUMMY>, /* rxtx6 */ |
| <&clk IMX8QXP_CLK_DUMMY>, /* rxtx7 */ |
| <&clk IMX8QXP_CLK_DUMMY>; /* spba */ |
| clock-names = "core", "rxtx0", |
| "rxtx1", "rxtx2", |
| "rxtx3", "rxtx4", |
| "rxtx5", "rxtx6", |
| "rxtx7", "spba"; |
| dmas = <&edma2 8 0 5>, <&edma2 9 0 4>; |
| dma-names = "rx", "tx"; |
| power-domains = <&pd_spdif0>; |
| status = "disabled"; |
| }; |
| |
| flexspi0: flexspi@05d120000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx8qm-flexspi"; |
| reg = <0x0 0x5d120000 0x0 0x10000>, <0x0 0x08000000 0x0 0x19ffffff>; |
| reg-names = "FlexSPI", "FlexSPI-memory"; |
| interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8QXP_LSIO_FSPI0_CLK>, |
| <&clk IMX8QXP_LSIO_FSPI0_CLK>; |
| assigned-clock-rates = <29000000>,<29000000>; |
| clock-names = "qspi_en", "qspi"; |
| power-domains = <&pd_lsio_flexspi0>; |
| status = "disabled"; |
| }; |
| |
| display-subsystem { |
| compatible = "fsl,imx-display-subsystem"; |
| ports = <&dpu_disp0>, <&dpu_disp1>; |
| }; |
| |
| dma_cap: dma_cap { |
| compatible = "dma-capability"; |
| only-dma-mask32 = <1>; |
| }; |
| |
| hsio: hsio@5f080000 { |
| compatible = "fsl,imx8qm-hsio", "syscon"; |
| reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */ |
| }; |
| |
| pcieb: pcie@0x5f010000 { |
| /* |
| * pcieb phyx1 lane1 in default, adjust it refer to the |
| * exact hw design. |
| */ |
| compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; |
| reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg*/ |
| <0x0 0x7ff00000 0x0 0x10000>; /* PCI cfg space */ |
| reg-names = "dbi", "config"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */ |
| 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ |
| num-lanes = <1>; |
| |
| #interrupt-cells = <1>; |
| interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "msi"; |
| |
| /* |
| * Set these clocks in default, then clocks should be |
| * refined for exact hw design of imx8 pcie. |
| */ |
| clocks = <&clk IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK>, |
| <&clk IMX8QXP_HSIO_PCIE_SLV_AXI_CLK>, |
| <&clk IMX8QXP_HSIO_PHY_X1_PCLK>, |
| <&clk IMX8QXP_HSIO_PCIE_DBI_AXI_CLK>; |
| clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; |
| |
| interrupt-map-mask = <0 0 0 0x7>; |
| interrupt-map = <0 0 0 1 &gic 0 105 4>, |
| <0 0 0 2 &gic 0 106 4>, |
| <0 0 0 3 &gic 0 107 4>, |
| <0 0 0 4 &gic 0 108 4>; |
| power-domains = <&pd_pcie>; |
| fsl,max-link-speed = <3>; |
| hsio-cfg = <PCIEAX2PCIEBX1>; |
| hsio = <&hsio>; |
| ctrl-id = <1>; /* pcieb */ |
| cpu-base-addr = <0x80000000>; |
| status = "disabled"; |
| }; |
| |
| imx_ion { |
| compatible = "fsl,mxc-ion"; |
| fsl,heap-id = <0>; |
| }; |
| }; |
| |
| &A35_0 { |
| operating-points = < |
| /* kHz uV */ |
| 1200000 1150000 |
| >; |
| clocks = <&clk IMX8QXP_A35_DIV>; |
| }; |
