ddr: Add training workaround to new timing data
Apply the workarounds from the previous changes to 1 Gb timings:
- Increase MR4 poll interval.
- Disable periodic dqs/read dq calibration.
Change-Id: Ic6ff515f72d555a9663547a381317a7a77188053
diff --git a/board/freescale/imx8mq_phanbell/ddr/lpddr4_timing_hynix_1gb.c b/board/freescale/imx8mq_phanbell/ddr/lpddr4_timing_hynix_1gb.c
index 99026bb..8d058ac 100644
--- a/board/freescale/imx8mq_phanbell/ddr/lpddr4_timing_hynix_1gb.c
+++ b/board/freescale/imx8mq_phanbell/ddr/lpddr4_timing_hynix_1gb.c
@@ -18,7 +18,7 @@
{0x3d400000,0xa1080020},
{0x3d400028,0x0},
{0x3d400020,0x203},
- {0x3d400024,0x3e800},
+ {0x3d400024,0x186a000},
{0x3d400064,0x610090},
{0x3d4000d0,0xc003061c},
{0x3d4000d4,0x9e0000},
@@ -48,7 +48,7 @@
{0x3d4001b0,0x11},
{0x3d4001b4,0x170a},
{0x3d4001c0,0x1},
- {0x3d4001c4,0x1},
+ {0x3d4001c4,0x0},
{0x3d4000f4,0x639},
{0x3d400108,0x70e1617},
{0x3d400200,0x1f},
@@ -58,7 +58,7 @@
{0x3d400214,0x7070707},
{0x3d400218,0xf070707},
{0x3d402020,0x1},
- {0x3d402024,0xd0c0},
+ {0x3d402024,0x518b00},
{0x3d402050,0x20d040},
{0x3d402064,0x14001f},
{0x3d4020dc,0x940009},
diff --git a/board/freescale/imx8mq_phanbell/ddr/lpddr4_timing_micron_1gb.c b/board/freescale/imx8mq_phanbell/ddr/lpddr4_timing_micron_1gb.c
index 30fd578..b9f3df5 100644
--- a/board/freescale/imx8mq_phanbell/ddr/lpddr4_timing_micron_1gb.c
+++ b/board/freescale/imx8mq_phanbell/ddr/lpddr4_timing_micron_1gb.c
@@ -18,7 +18,7 @@
{0x3d400000,0xa1080020},
{0x3d400028,0x0},
{0x3d400020,0x203},
- {0x3d400024,0x3e800},
+ {0x3d400024,0x186a000},
{0x3d400064,0x610090},
{0x3d4000d0,0xc003061c},
{0x3d4000d4,0x9e0000},
@@ -48,7 +48,7 @@
{0x3d4001b0,0x11},
{0x3d4001b4,0x170a},
{0x3d4001c0,0x1},
- {0x3d4001c4,0x1},
+ {0x3d4001c4,0x0},
{0x3d4000f4,0x639},
{0x3d400108,0x70e1617},
{0x3d400200,0x1f},
@@ -58,7 +58,7 @@
{0x3d400214,0x7070707},
{0x3d400218,0xf070707},
{0x3d402020,0x1},
- {0x3d402024,0xd0c0},
+ {0x3d402024,0x518b00},
{0x3d402050,0x20d040},
{0x3d402064,0x14001f},
{0x3d4020dc,0x940009},
