439d47bc651c623459e44b399c0e23ff56999a2b - uboot-imx

commit: 439d47bc651c623459e44b399c0e23ff56999a2b
[log] [tgz]
author: Peter Nordström <pnordstrom@google.com>
Fri Jan 31 14:37:51 2020 -0800
committer: Peter Nordström <pnordstrom@google.com>
Wed Feb 05 17:16:01 2020 -0800
tree: 1b09658dd8f1cc7376f14d1d5d4b9758083819d3
parent: 0ffebcc1209862bc50335b79a5ab6513f1960ce1 [diff]

ddr: Add training workaround to new timing data

Apply the workarounds from the previous changes to 1 Gb timings:
    - Increase MR4 poll interval.
    - Disable periodic dqs/read dq calibration.

Change-Id: Ic6ff515f72d555a9663547a381317a7a77188053

board/freescale/imx8mq_phanbell/ddr/lpddr4_timing_hynix_1gb.c[diff]
board/freescale/imx8mq_phanbell/ddr/lpddr4_timing_micron_1gb.c[diff]

2 files changed

tree: 1b09658dd8f1cc7376f14d1d5d4b9758083819d3