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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
#include <common.h>
#include <malloc.h>
#include <errno.h>
#include <asm/io.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm-generic/gpio.h>
#include <fsl_esdhc.h>
#include <mmc.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/video.h>
#include <asm/arch/video_common.h>
#include <spl.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "../common/tcpc.h"
#include "../common/pfuze.h"
#include <usb.h>
#include <dwc3-uboot.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
static iomux_v3_cfg_t const uart_pads[] = {
IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
return 0;
}
#ifdef CONFIG_FSL_QSPI
int board_qspi_init(void)
{
set_clk_qspi();
return 0;
}
#endif
int dram_init(void)
{
/* rom_pointer[1] contains the size of TEE occupies */
if (rom_pointer[1])
gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
else
gd->ram_size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_FEC_MXC
#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
static iomux_v3_cfg_t const fec1_rst_pads[] = {
IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_fec(void)
{
imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
ARRAY_SIZE(fec1_rst_pads));
gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
udelay(500);
gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
}
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
setup_iomux_fec();
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
clrsetbits_le32(&gpr->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 0);
return set_clk_enet(ENET_125MHZ);
}
int board_phy_config(struct phy_device *phydev)
{
/* enable rgmii rxc skew and phy mode select to RGMII copper */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
#ifdef CONFIG_USB_DWC3
#define USB_PHY_CTRL0 0xF0040
#define USB_PHY_CTRL0_REF_SSP_EN BIT(2)
#define USB_PHY_CTRL1 0xF0044
#define USB_PHY_CTRL1_RESET BIT(0)
#define USB_PHY_CTRL1_COMMONONN BIT(1)
#define USB_PHY_CTRL1_ATERESET BIT(3)
#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19)
#define USB_PHY_CTRL1_VDATDETENB0 BIT(20)
#define USB_PHY_CTRL2 0xF0048
#define USB_PHY_CTRL2_TXENABLEN0 BIT(8)
static struct dwc3_device dwc3_device_data = {
#ifdef CONFIG_SPL_BUILD
.maximum_speed = USB_SPEED_HIGH,
#else
.maximum_speed = USB_SPEED_SUPER,
#endif
.base = USB1_BASE_ADDR,
.dr_mode = USB_DR_MODE_PERIPHERAL,
.index = 0,
.power_down_scale = 2,
};
int usb_gadget_handle_interrupts(void)
{
dwc3_uboot_handle_interrupt(0);
return 0;
}
static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
{
u32 RegData;
RegData = readl(dwc3->base + USB_PHY_CTRL1);
RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
USB_PHY_CTRL1_COMMONONN);
RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
writel(RegData, dwc3->base + USB_PHY_CTRL1);
RegData = readl(dwc3->base + USB_PHY_CTRL0);
RegData |= USB_PHY_CTRL0_REF_SSP_EN;
writel(RegData, dwc3->base + USB_PHY_CTRL0);
RegData = readl(dwc3->base + USB_PHY_CTRL2);
RegData |= USB_PHY_CTRL2_TXENABLEN0;
writel(RegData, dwc3->base + USB_PHY_CTRL2);
RegData = readl(dwc3->base + USB_PHY_CTRL1);
RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
writel(RegData, dwc3->base + USB_PHY_CTRL1);
}
#endif
#ifdef CONFIG_USB_TCPC
struct tcpc_port port;
struct tcpc_port_config port_config = {
.i2c_bus = 0,
.addr = 0x50,
.port_type = TYPEC_PORT_UFP,
.max_snk_mv = 20000,
.max_snk_ma = 3000,
.max_snk_mw = 15000,
.op_snk_mv = 9000,
};
#define USB_TYPEC_SEL IMX_GPIO_NR(3, 15)
static iomux_v3_cfg_t ss_mux_gpio[] = {
IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
void ss_mux_select(enum typec_cc_polarity pol)
{
if (pol == TYPEC_POLARITY_CC1)
gpio_direction_output(USB_TYPEC_SEL, 1);
else
gpio_direction_output(USB_TYPEC_SEL, 0);
}
static int setup_typec(void)
{
int ret;
imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
gpio_request(USB_TYPEC_SEL, "typec_sel");
ret = tcpc_init(&port, port_config, &ss_mux_select);
if (ret) {
printf("%s: tcpc init failed, err=%d\n",
__func__, ret);
}
return ret;
}
#endif
#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
int board_usb_init(int index, enum usb_init_type init)
{
int ret = 0;
imx8m_usb_power(index, true);
if (index == 0 && init == USB_INIT_DEVICE) {
#ifdef CONFIG_USB_TCPC
ret = tcpc_setup_ufp_mode(&port);
#endif
dwc3_nxp_usb_phy_init(&dwc3_device_data);
return dwc3_uboot_init(&dwc3_device_data);
} else if (index == 0 && init == USB_INIT_HOST) {
#ifdef CONFIG_USB_TCPC
ret = tcpc_setup_dfp_mode(&port);
#endif
return ret;
}
return 0;
}
int board_usb_cleanup(int index, enum usb_init_type init)
{
int ret = 0;
if (index == 0 && init == USB_INIT_DEVICE) {
dwc3_uboot_exit(index);
} else if (index == 0 && init == USB_INIT_HOST) {
#ifdef CONFIG_USB_TCPC
ret = tcpc_disable_src_vbus(&port);
#endif
}
imx8m_usb_power(index, false);
return ret;
}
#endif
int board_init(void)
{
#ifdef CONFIG_FSL_QSPI
board_qspi_init();
#endif
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
init_usb_clk();
#endif
#ifdef CONFIG_USB_TCPC
setup_typec();
#endif
return 0;
}
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
env_set("board_name", "EVK");
env_set("board_rev", "iMX8MQ");
#endif
#ifdef CONFIG_ENV_IS_IN_MMC
board_late_mmc_env_init();
#endif
return 0;
}
#if defined(CONFIG_VIDEO_IMXDCSS)
struct display_info_t const displays[] = {{
.bus = 0, /* Unused */
.addr = 0, /* Unused */
.pixfmt = GDF_32BIT_X888RGB,
.detect = NULL,
.enable = NULL,
#ifndef CONFIG_VIDEO_IMXDCSS_1080P
.mode = {
.name = "HDMI", /* 720P60 */
.refresh = 60,
.xres = 1280,
.yres = 720,
.pixclock = 13468, /* 74250 kHz */
.left_margin = 110,
.right_margin = 220,
.upper_margin = 5,
.lower_margin = 20,
.hsync_len = 40,
.vsync_len = 5,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
}
#else
.mode = {
.name = "HDMI", /* 1080P60 */
.refresh = 60,
.xres = 1920,
.yres = 1080,
.pixclock = 6734, /* 148500 kHz */
.left_margin = 148,
.right_margin = 88,
.upper_margin = 36,
.lower_margin = 4,
.hsync_len = 44,
.vsync_len = 5,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
}
#endif
} };
size_t display_count = ARRAY_SIZE(displays);
#endif /* CONFIG_VIDEO_IMXDCSS */