| /* |
| * Copyright 2010-2012 Freescale Semiconductor, Inc. |
| * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> |
| * Timur Tabi <timur@freescale.com> |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| #ifndef __CONFIG_H |
| #define __CONFIG_H |
| |
| #include "../board/freescale/common/ics307_clk.h" |
| |
| #ifdef CONFIG_SDCARD |
| #define CONFIG_SPL_MMC_MINIMAL |
| #define CONFIG_SPL_FLUSH_IMAGE |
| #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
| #define CONFIG_SYS_TEXT_BASE 0x11001000 |
| #define CONFIG_SPL_TEXT_BASE 0xf8f81000 |
| #define CONFIG_SPL_PAD_TO 0x20000 |
| #define CONFIG_SPL_MAX_SIZE (128 * 1024) |
| #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) |
| #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) |
| #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) |
| #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) |
| #define CONFIG_SYS_MPC85XX_NO_RESETVEC |
| #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" |
| #define CONFIG_SPL_MMC_BOOT |
| #ifdef CONFIG_SPL_BUILD |
| #define CONFIG_SPL_COMMON_INIT_DDR |
| #endif |
| #endif |
| |
| #ifdef CONFIG_SPIFLASH |
| #define CONFIG_SPL_SPI_FLASH_MINIMAL |
| #define CONFIG_SPL_FLUSH_IMAGE |
| #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
| #define CONFIG_SYS_TEXT_BASE 0x11001000 |
| #define CONFIG_SPL_TEXT_BASE 0xf8f81000 |
| #define CONFIG_SPL_PAD_TO 0x20000 |
| #define CONFIG_SPL_MAX_SIZE (128 * 1024) |
| #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) |
| #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) |
| #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) |
| #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) |
| #define CONFIG_SYS_MPC85XX_NO_RESETVEC |
| #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" |
| #define CONFIG_SPL_SPI_BOOT |
| #ifdef CONFIG_SPL_BUILD |
| #define CONFIG_SPL_COMMON_INIT_DDR |
| #endif |
| #endif |
| |
| #define CONFIG_NAND_FSL_ELBC |
| #define CONFIG_SYS_NAND_MAX_ECCPOS 56 |
| #define CONFIG_SYS_NAND_MAX_OOBFREE 5 |
| |
| #ifdef CONFIG_NAND |
| #ifdef CONFIG_TPL_BUILD |
| #define CONFIG_SPL_NAND_BOOT |
| #define CONFIG_SPL_FLUSH_IMAGE |
| #define CONFIG_SPL_NAND_INIT |
| #define CONFIG_SPL_COMMON_INIT_DDR |
| #define CONFIG_SPL_MAX_SIZE (128 << 10) |
| #define CONFIG_SPL_TEXT_BASE 0xf8f81000 |
| #define CONFIG_SYS_MPC85XX_NO_RESETVEC |
| #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) |
| #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) |
| #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) |
| #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) |
| #elif defined(CONFIG_SPL_BUILD) |
| #define CONFIG_SPL_INIT_MINIMAL |
| #define CONFIG_SPL_FLUSH_IMAGE |
| #define CONFIG_SPL_TEXT_BASE 0xff800000 |
| #define CONFIG_SPL_MAX_SIZE 4096 |
| #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) |
| #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 |
| #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 |
| #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) |
| #endif |
| #define CONFIG_SPL_PAD_TO 0x20000 |
| #define CONFIG_TPL_PAD_TO 0x20000 |
| #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
| #define CONFIG_SYS_TEXT_BASE 0x11001000 |
| #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" |
| #endif |
| |
| /* High Level Configuration Options */ |
| #define CONFIG_MP /* support multiple processors */ |
| |
| #ifndef CONFIG_SYS_TEXT_BASE |
| #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
| #endif |
| |
| #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc |
| #endif |
| |
| #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ |
| #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ |
| #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ |
| #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
| #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ |
| #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ |
| |
| #define CONFIG_ENABLE_36BIT_PHYS |
| |
| #ifdef CONFIG_PHYS_64BIT |
| #define CONFIG_ADDR_MAP |
| #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ |
| #endif |
| |
| #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() |
| #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() |
| #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
| |
| /* |
| * These can be toggled for performance analysis, otherwise use default. |
| */ |
| #define CONFIG_L2_CACHE |
| #define CONFIG_BTB |
| |
| #define CONFIG_SYS_MEMTEST_START 0x00000000 |
| #define CONFIG_SYS_MEMTEST_END 0x7fffffff |
| |
| #define CONFIG_SYS_CCSRBAR 0xffe00000 |
| #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
| |
| /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k |
| SPL code*/ |
| #ifdef CONFIG_SPL_BUILD |
| #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
| #endif |
| |
| /* DDR Setup */ |
| #define CONFIG_DDR_SPD |
| #define CONFIG_VERY_BIG_RAM |
| |
| #ifdef CONFIG_DDR_ECC |
| #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
| #define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
| #endif |
| |
| #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| |
| #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
| |
| /* I2C addresses of SPD EEPROMs */ |
| #define CONFIG_SYS_SPD_BUS_NUM 1 |
| #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
| |
| /* These are used when DDR doesn't use SPD. */ |
| #define CONFIG_SYS_SDRAM_SIZE 2048 |
| #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G |
| #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F |
| #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 |
| #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F |
| #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 |
| #define CONFIG_SYS_DDR_TIMING_3 0x00010000 |
| #define CONFIG_SYS_DDR_TIMING_0 0x40110104 |
| #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 |
| #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca |
| #define CONFIG_SYS_DDR_MODE_1 0x00441221 |
| #define CONFIG_SYS_DDR_MODE_2 0x00000000 |
| #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 |
| #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
| #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 |
| #define CONFIG_SYS_DDR_CONTROL 0xc7000008 |
| #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 |
| #define CONFIG_SYS_DDR_TIMING_4 0x00220001 |
| #define CONFIG_SYS_DDR_TIMING_5 0x02401400 |
| #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 |
| #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 |
| |
| /* |
| * Memory map |
| * |
| * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable |
| * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable |
| * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable |
| * |
| * Localbus cacheable (TBD) |
| * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable |
| * |
| * Localbus non-cacheable |
| * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable |
| * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable |
| * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable |
| * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
| * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 |
| * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable |
| */ |
| |
| /* |
| * Local Bus Definitions |
| */ |
| #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ |
| #ifdef CONFIG_PHYS_64BIT |
| #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull |
| #else |
| #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| #endif |
| |
| #define CONFIG_FLASH_BR_PRELIM \ |
| (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) |
| #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) |
| |
| #ifdef CONFIG_NAND |
| #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ |
| #else |
| #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ |
| #endif |
| |
| #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |
| #define CONFIG_SYS_FLASH_QUIET_TEST |
| #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| |
| #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| #define CONFIG_SYS_MAX_FLASH_SECT 1024 |
| |
| #ifndef CONFIG_SYS_MONITOR_BASE |
| #ifdef CONFIG_SPL_BUILD |
| #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE |
| #else |
| #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| #endif |
| #endif |
| |
| #define CONFIG_FLASH_CFI_DRIVER |
| #define CONFIG_SYS_FLASH_CFI |
| #define CONFIG_SYS_FLASH_EMPTY_INFO |
| |
| /* Nand Flash */ |
| #if defined(CONFIG_NAND_FSL_ELBC) |
| #define CONFIG_SYS_NAND_BASE 0xff800000 |
| #ifdef CONFIG_PHYS_64BIT |
| #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull |
| #else |
| #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| #endif |
| |
| #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} |
| #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| #define CONFIG_CMD_NAND 1 |
| #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) |
| #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE |
| |
| /* NAND flash config */ |
| #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| | BR_PS_8 /* Port Size = 8 bit */ \ |
| | BR_MS_FCM /* MSEL = FCM */ \ |
| | BR_V) /* valid */ |
| #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ |
| | OR_FCM_PGS /* Large Page*/ \ |
| | OR_FCM_CSCT \ |
| | OR_FCM_CST \ |
| | OR_FCM_CHT \ |
| | OR_FCM_SCY_1 \ |
| | OR_FCM_TRLX \ |
| | OR_FCM_EHTR) |
| #ifdef CONFIG_NAND |
| #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
| #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
| #else |
| #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
| #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
| #endif |
| |
| #endif /* CONFIG_NAND_FSL_ELBC */ |
| |
| #define CONFIG_BOARD_EARLY_INIT_R |
| #define CONFIG_MISC_INIT_R |
| #define CONFIG_HWCONFIG |
| |
| #define CONFIG_FSL_NGPIXIS |
| #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ |
| #ifdef CONFIG_PHYS_64BIT |
| #define PIXIS_BASE_PHYS 0xfffdf0000ull |
| #else |
| #define PIXIS_BASE_PHYS PIXIS_BASE |
| #endif |
| |
| #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) |
| #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) |
| |
| #define PIXIS_LBMAP_SWITCH 7 |
| #define PIXIS_LBMAP_MASK 0xF0 |
| #define PIXIS_LBMAP_ALTBANK 0x20 |
| #define PIXIS_SPD 0x07 |
| #define PIXIS_SPD_SYSCLK_MASK 0x07 |
| #define PIXIS_ELBC_SPI_MASK 0xc0 |
| #define PIXIS_SPI 0x80 |
| |
| #define CONFIG_SYS_INIT_RAM_LOCK |
| #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ |
| #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
| |
| #define CONFIG_SYS_GBL_DATA_OFFSET \ |
| (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| |
| #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
| #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
| |
| /* |
| * Config the L2 Cache as L2 SRAM |
| */ |
| #if defined(CONFIG_SPL_BUILD) |
| #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) |
| #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
| #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
| #define CONFIG_SYS_L2_SIZE (256 << 10) |
| #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
| #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 |
| #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) |
| #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) |
| #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) |
| #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) |
| #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) |
| #elif defined(CONFIG_NAND) |
| #ifdef CONFIG_TPL_BUILD |
| #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
| #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
| #define CONFIG_SYS_L2_SIZE (256 << 10) |
| #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
| #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 |
| #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) |
| #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) |
| #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) |
| #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) |
| #else |
| #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
| #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
| #define CONFIG_SYS_L2_SIZE (256 << 10) |
| #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
| #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) |
| #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) |
| #endif |
| #endif |
| #endif |
| |
| /* |
| * Serial Port |
| */ |
| #define CONFIG_CONS_INDEX 1 |
| #define CONFIG_SYS_NS16550_SERIAL |
| #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
| #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) |
| #define CONFIG_NS16550_MIN_FUNCTIONS |
| #endif |
| |
| #define CONFIG_SYS_BAUDRATE_TABLE \ |
| {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
| |
| #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
| |
| /* Video */ |
| |
| #ifdef CONFIG_FSL_DIU_FB |
| #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) |
| #define CONFIG_CMD_BMP |
| #define CONFIG_VIDEO_LOGO |
| #define CONFIG_VIDEO_BMP_LOGO |
| #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS |
| /* |
| * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so |
| * disable empty flash sector detection, which is I/O-intensive. |
| */ |
| #undef CONFIG_SYS_FLASH_EMPTY_INFO |
| #endif |
| |
| #ifndef CONFIG_FSL_DIU_FB |
| #endif |
| |
| #ifdef CONFIG_ATI |
| #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT |
| #define CONFIG_BIOSEMU |
| #define CONFIG_ATI_RADEON_FB |
| #define CONFIG_VIDEO_LOGO |
| #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
| #endif |
| |
| /* I2C */ |
| #define CONFIG_SYS_I2C |
| #define CONFIG_SYS_I2C_FSL |
| #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
| #define CONFIG_SYS_FSL_I2C2_SPEED 400000 |
| #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
| #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 |
| #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} |
| |
| /* |
| * I2C2 EEPROM |
| */ |
| #define CONFIG_ID_EEPROM |
| #define CONFIG_SYS_I2C_EEPROM_NXID |
| #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| #define CONFIG_SYS_EEPROM_BUS_NUM 1 |
| |
| /* |
| * eSPI - Enhanced SPI |
| */ |
| |
| #define CONFIG_HARD_SPI |
| |
| #define CONFIG_SF_DEFAULT_SPEED 10000000 |
| #define CONFIG_SF_DEFAULT_MODE 0 |
| |
| /* |
| * General PCI |
| * Memory space is mapped 1-1, but I/O space must start from 0. |
| */ |
| |
| /* controller 1, Slot 2, tgtid 1, Base address a000 */ |
| #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 |
| #ifdef CONFIG_PHYS_64BIT |
| #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
| #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull |
| #else |
| #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 |
| #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 |
| #endif |
| #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
| #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 |
| #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| #ifdef CONFIG_PHYS_64BIT |
| #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull |
| #else |
| #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 |
| #endif |
| #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
| |
| /* controller 2, direct to uli, tgtid 2, Base address 9000 */ |
| #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
| #ifdef CONFIG_PHYS_64BIT |
| #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
| #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
| #else |
| #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 |
| #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 |
| #endif |
| #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
| #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 |
| #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
| #ifdef CONFIG_PHYS_64BIT |
| #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull |
| #else |
| #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 |
| #endif |
| #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
| |
| /* controller 3, Slot 1, tgtid 3, Base address b000 */ |
| #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 |
| #ifdef CONFIG_PHYS_64BIT |
| #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
| #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull |
| #else |
| #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 |
| #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 |
| #endif |
| #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
| #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 |
| #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
| #ifdef CONFIG_PHYS_64BIT |
| #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull |
| #else |
| #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 |
| #endif |
| #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
| |
| #ifdef CONFIG_PCI |
| #define CONFIG_PCI_INDIRECT_BRIDGE |
| #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| #endif |
| |
| /* SATA */ |
| #define CONFIG_LIBATA |
| #define CONFIG_FSL_SATA |
| #define CONFIG_FSL_SATA_V2 |
| |
| #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
| #define CONFIG_SATA1 |
| #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR |
| #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA |
| #define CONFIG_SATA2 |
| #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR |
| #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA |
| |
| #ifdef CONFIG_FSL_SATA |
| #define CONFIG_LBA48 |
| #define CONFIG_CMD_SATA |
| #endif |
| |
| #ifdef CONFIG_MMC |
| #define CONFIG_FSL_ESDHC |
| #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
| #endif |
| |
| #define CONFIG_TSEC_ENET |
| #ifdef CONFIG_TSEC_ENET |
| |
| #define CONFIG_TSECV2 |
| |
| #define CONFIG_MII /* MII PHY management */ |
| #define CONFIG_TSEC1 1 |
| #define CONFIG_TSEC1_NAME "eTSEC1" |
| #define CONFIG_TSEC2 1 |
| #define CONFIG_TSEC2_NAME "eTSEC2" |
| |
| #define TSEC1_PHY_ADDR 1 |
| #define TSEC2_PHY_ADDR 2 |
| |
| #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| |
| #define TSEC1_PHYIDX 0 |
| #define TSEC2_PHYIDX 0 |
| |
| #define CONFIG_ETHPRIME "eTSEC1" |
| |
| #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ |
| #endif |
| |
| /* |
| * Dynamic MTD Partition support with mtdparts |
| */ |
| #define CONFIG_MTD_DEVICE |
| #define CONFIG_MTD_PARTITIONS |
| #define CONFIG_CMD_MTDPARTS |
| #define CONFIG_FLASH_CFI_MTD |
| #ifdef CONFIG_PHYS_64BIT |
| #define MTDIDS_DEFAULT "nor0=fe8000000.nor" |
| #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \ |
| "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ |
| "512k(dtb),768k(u-boot)" |
| #else |
| #define MTDIDS_DEFAULT "nor0=e8000000.nor" |
| #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ |
| "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ |
| "512k(dtb),768k(u-boot)" |
| #endif |
| |
| /* |
| * Environment |
| */ |
| #ifdef CONFIG_SPIFLASH |
| #define CONFIG_ENV_IS_IN_SPI_FLASH |
| #define CONFIG_ENV_SPI_BUS 0 |
| #define CONFIG_ENV_SPI_CS 0 |
| #define CONFIG_ENV_SPI_MAX_HZ 10000000 |
| #define CONFIG_ENV_SPI_MODE 0 |
| #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
| #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ |
| #define CONFIG_ENV_SECT_SIZE 0x10000 |
| #elif defined(CONFIG_SDCARD) |
| #define CONFIG_ENV_IS_IN_MMC |
| #define CONFIG_FSL_FIXED_MMC_LOCATION |
| #define CONFIG_ENV_SIZE 0x2000 |
| #define CONFIG_SYS_MMC_ENV_DEV 0 |
| #elif defined(CONFIG_NAND) |
| #ifdef CONFIG_TPL_BUILD |
| #define CONFIG_ENV_SIZE 0x2000 |
| #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) |
| #else |
| #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
| #endif |
| #define CONFIG_ENV_IS_IN_NAND |
| #define CONFIG_ENV_OFFSET (1024 * 1024) |
| #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) |
| #elif defined(CONFIG_SYS_RAMBOOT) |
| #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
| #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
| #define CONFIG_ENV_SIZE 0x2000 |
| #else |
| #define CONFIG_ENV_IS_IN_FLASH |
| #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
| #define CONFIG_ENV_SIZE 0x2000 |
| #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
| #endif |
| |
| #define CONFIG_LOADS_ECHO |
| #define CONFIG_SYS_LOADS_BAUD_CHANGE |
| |
| /* |
| * Command line configuration. |
| */ |
| #define CONFIG_CMD_ERRATA |
| #define CONFIG_CMD_IRQ |
| #define CONFIG_CMD_REGINFO |
| |
| #ifdef CONFIG_PCI |
| #define CONFIG_CMD_PCI |
| #endif |
| |
| /* |
| * USB |
| */ |
| #define CONFIG_HAS_FSL_DR_USB |
| #ifdef CONFIG_HAS_FSL_DR_USB |
| #define CONFIG_USB_EHCI |
| |
| #ifdef CONFIG_USB_EHCI |
| #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| #define CONFIG_USB_EHCI_FSL |
| #endif |
| #endif |
| |
| /* |
| * Miscellaneous configurable options |
| */ |
| #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
| #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
| #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| #ifdef CONFIG_CMD_KGDB |
| #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| #else |
| #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| #endif |
| /* Print Buffer Size */ |
| #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
| #define CONFIG_SYS_MAXARGS 16 |
| #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| |
| /* |
| * For booting Linux, the board info and command line data |
| * have to be in the first 64 MB of memory, since this is |
| * the maximum mapped by the Linux kernel during initialization. |
| */ |
| #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
| #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
| |
| #ifdef CONFIG_CMD_KGDB |
| #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| #endif |
| |
| /* |
| * Environment Configuration |
| */ |
| |
| #define CONFIG_HOSTNAME p1022ds |
| #define CONFIG_ROOTPATH "/opt/nfsroot" |
| #define CONFIG_BOOTFILE "uImage" |
| #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
| |
| #define CONFIG_LOADADDR 1000000 |
| |
| |
| #define CONFIG_BAUDRATE 115200 |
| |
| #define CONFIG_EXTRA_ENV_SETTINGS \ |
| "netdev=eth0\0" \ |
| "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ |
| "tftpflash=tftpboot $loadaddr $uboot && " \ |
| "protect off $ubootaddr +$filesize && " \ |
| "erase $ubootaddr +$filesize && " \ |
| "cp.b $loadaddr $ubootaddr $filesize && " \ |
| "protect on $ubootaddr +$filesize && " \ |
| "cmp.b $loadaddr $ubootaddr $filesize\0" \ |
| "consoledev=ttyS0\0" \ |
| "ramdiskaddr=2000000\0" \ |
| "ramdiskfile=rootfs.ext2.gz.uboot\0" \ |
| "fdtaddr=1e00000\0" \ |
| "fdtfile=p1022ds.dtb\0" \ |
| "bdev=sda3\0" \ |
| "hwconfig=esdhc;audclk:12\0" |
| |
| #define CONFIG_HDBOOT \ |
| "setenv bootargs root=/dev/$bdev rw " \ |
| "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ |
| "tftp $loadaddr $bootfile;" \ |
| "tftp $fdtaddr $fdtfile;" \ |
| "bootm $loadaddr - $fdtaddr" |
| |
| #define CONFIG_NFSBOOTCOMMAND \ |
| "setenv bootargs root=/dev/nfs rw " \ |
| "nfsroot=$serverip:$rootpath " \ |
| "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ |
| "tftp $loadaddr $bootfile;" \ |
| "tftp $fdtaddr $fdtfile;" \ |
| "bootm $loadaddr - $fdtaddr" |
| |
| #define CONFIG_RAMBOOTCOMMAND \ |
| "setenv bootargs root=/dev/ram rw " \ |
| "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ |
| "tftp $ramdiskaddr $ramdiskfile;" \ |
| "tftp $loadaddr $bootfile;" \ |
| "tftp $fdtaddr $fdtfile;" \ |
| "bootm $loadaddr $ramdiskaddr $fdtaddr" |
| |
| #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND |
| |
| #endif |
