| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (C) 2016 MediaTek Inc. |
| * |
| * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> |
| */ |
| |
| #include <asm/io.h> |
| #include <clk.h> |
| #include <common.h> |
| #include <dm.h> |
| #include <dm/of_access.h> |
| #include <generic-phy.h> |
| #include <power/regulator.h> |
| |
| #include <linux/iopoll.h> |
| #include <linux/ioport.h> |
| #include <linux/kernel.h> |
| |
| #include "mtu3.h" |
| #include "mtu3_dr.h" |
| |
| |
| /* u2-port0 should be powered on and enabled; */ |
| int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks) |
| { |
| void __iomem *ibase = ssusb->ippc_base; |
| u32 value, check_val; |
| int ret; |
| |
| check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE | |
| SSUSB_REF_RST_B_STS; |
| |
| ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value, |
| (check_val == (value & check_val)), 20000); |
| if (ret) |
| dev_err(ssusb->dev, "clks of sts1 are not stable!\n"); |
| |
| ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value, |
| (value & SSUSB_U2_MAC_SYS_RST_B_STS), 10000); |
| if (ret) { |
| dev_err(ssusb->dev, "mac2 clock is not stable\n"); |
| return ret; |
| } |
| |
| return 0; |
| } |
| |
| void ssusb_set_force_vbus(struct ssusb_mtk *ssusb, bool vbus_on) |
| { |
| u32 u2ctl; |
| u32 misc; |
| |
| if (!ssusb->force_vbus) |
| return; |
| |
| u2ctl = mtu3_readl(ssusb->ippc_base, SSUSB_U2_CTRL(0)); |
| misc = mtu3_readl(ssusb->mac_base, U3D_MISC_CTRL); |
| if (vbus_on) { |
| u2ctl &= ~SSUSB_U2_PORT_OTG_SEL; |
| misc |= VBUS_FRC_EN | VBUS_ON; |
| } else { |
| u2ctl |= SSUSB_U2_PORT_OTG_SEL; |
| misc &= ~(VBUS_FRC_EN | VBUS_ON); |
| } |
| mtu3_writel(ssusb->ippc_base, SSUSB_U2_CTRL(0), u2ctl); |
| mtu3_writel(ssusb->mac_base, U3D_MISC_CTRL, misc); |
| } |
| |
| static int ssusb_phy_init(struct ssusb_mtk *ssusb) |
| { |
| int i; |
| int ret; |
| |
| for (i = 0; i < ssusb->num_phys; i++) { |
| ret = generic_phy_init(ssusb->phys[i]); |
| if (ret) |
| goto exit_phy; |
| } |
| return 0; |
| |
| exit_phy: |
| for (; i > 0; i--) |
| generic_phy_exit(ssusb->phys[i - 1]); |
| |
| return ret; |
| } |
| |
| static int ssusb_phy_exit(struct ssusb_mtk *ssusb) |
| { |
| int i; |
| |
| for (i = 0; i < ssusb->num_phys; i++) |
| generic_phy_exit(ssusb->phys[i]); |
| |
| return 0; |
| } |
| |
| static int ssusb_phy_power_on(struct ssusb_mtk *ssusb) |
| { |
| int i; |
| int ret; |
| |
| for (i = 0; i < ssusb->num_phys; i++) { |
| ret = generic_phy_power_on(ssusb->phys[i]); |
| if (ret) |
| goto power_off_phy; |
| } |
| return 0; |
| |
| power_off_phy: |
| for (; i > 0; i--) |
| generic_phy_power_off(ssusb->phys[i - 1]); |
| |
| return ret; |
| } |
| |
| static void ssusb_phy_power_off(struct ssusb_mtk *ssusb) |
| { |
| unsigned int i; |
| |
| for (i = 0; i < ssusb->num_phys; i++) |
| generic_phy_power_off(ssusb->phys[i]); |
| } |
| |
| static int ssusb_clks_enable(struct ssusb_mtk *ssusb) |
| { |
| int ret; |
| |
| ret = clk_prepare_enable(ssusb->sys_clk); |
| if (ret) { |
| dev_err(ssusb->dev, "failed to enable sys_clk\n"); |
| goto sys_clk_err; |
| } |
| |
| ret = clk_prepare_enable(ssusb->ref_clk); |
| if (ret) { |
| dev_err(ssusb->dev, "failed to enable ref_clk\n"); |
| goto ref_clk_err; |
| } |
| |
| ret = clk_prepare_enable(ssusb->mcu_clk); |
| if (ret) { |
| dev_err(ssusb->dev, "failed to enable mcu_clk\n"); |
| goto mcu_clk_err; |
| } |
| |
| ret = clk_prepare_enable(ssusb->dma_clk); |
| if (ret) { |
| dev_err(ssusb->dev, "failed to enable dma_clk\n"); |
| goto dma_clk_err; |
| } |
| |
| return 0; |
| |
| dma_clk_err: |
| clk_disable_unprepare(ssusb->mcu_clk); |
| mcu_clk_err: |
| clk_disable_unprepare(ssusb->ref_clk); |
| ref_clk_err: |
| clk_disable_unprepare(ssusb->sys_clk); |
| sys_clk_err: |
| return ret; |
| } |
| |
| static void ssusb_clks_disable(struct ssusb_mtk *ssusb) |
| { |
| clk_disable_unprepare(ssusb->dma_clk); |
| clk_disable_unprepare(ssusb->mcu_clk); |
| clk_disable_unprepare(ssusb->ref_clk); |
| clk_disable_unprepare(ssusb->sys_clk); |
| } |
| |
| static int ssusb_rscs_init(struct ssusb_mtk *ssusb) |
| { |
| int ret = 0; |
| |
| ret = ssusb_clks_enable(ssusb); |
| if (ret) |
| goto clks_err; |
| |
| ret = ssusb_phy_init(ssusb); |
| if (ret) { |
| dev_err(ssusb->dev, "failed to init phy\n"); |
| goto phy_init_err; |
| } |
| |
| ret = ssusb_phy_power_on(ssusb); |
| if (ret) { |
| dev_err(ssusb->dev, "failed to power on phy\n"); |
| goto phy_err; |
| } |
| |
| return 0; |
| |
| phy_err: |
| ssusb_phy_exit(ssusb); |
| phy_init_err: |
| ssusb_clks_disable(ssusb); |
| clks_err: |
| return ret; |
| } |
| |
| static void ssusb_rscs_exit(struct ssusb_mtk *ssusb) |
| { |
| ssusb_clks_disable(ssusb); |
| ssusb_phy_power_off(ssusb); |
| ssusb_phy_exit(ssusb); |
| } |
| |
| static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb) |
| { |
| /* reset whole ip (xhci & u3d) */ |
| mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST); |
| udelay(1); |
| mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST); |
| |
| /* |
| * device ip may be powered on in firmware/BROM stage before entering |
| * kernel stage; |
| * power down device ip, otherwise ip-sleep will fail when working as |
| * host only mode |
| */ |
| mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); |
| } |
| |
| /* ignore the error if the clock does not exist */ |
| static struct clk *get_optional_clk(struct udevice *dev, const char *id) |
| { |
| struct clk *opt_clk; |
| |
| opt_clk = devm_clk_get(dev, id); |
| /* ignore error number except EPROBE_DEFER */ |
| if (IS_ERR(opt_clk) && (PTR_ERR(opt_clk) != -EPROBE_DEFER)) |
| opt_clk = NULL; |
| |
| return opt_clk; |
| } |
| |
| static int get_ssusb_rscs(struct udevice *dev, struct ssusb_mtk *ssusb) |
| { |
| const struct device_node *node = ofnode_to_np(dev->node); |
| struct otg_switch_mtk *otg_sx = &ssusb->otg_switch; |
| struct resource res; |
| int i; |
| int ret; |
| |
| ssusb->sys_clk = devm_clk_get(dev, "sys_ck"); |
| if (IS_ERR(ssusb->sys_clk)) { |
| dev_err(dev, "failed to get sys clock\n"); |
| return PTR_ERR(ssusb->sys_clk); |
| } |
| |
| ssusb->ref_clk = get_optional_clk(dev, "ref_ck"); |
| if (IS_ERR(ssusb->ref_clk)) |
| return PTR_ERR(ssusb->ref_clk); |
| |
| ssusb->mcu_clk = get_optional_clk(dev, "mcu_ck"); |
| if (IS_ERR(ssusb->mcu_clk)) |
| return PTR_ERR(ssusb->mcu_clk); |
| |
| ssusb->dma_clk = get_optional_clk(dev, "dma_ck"); |
| if (IS_ERR(ssusb->dma_clk)) |
| return PTR_ERR(ssusb->dma_clk); |
| |
| ssusb->num_phys = of_count_phandle_with_args(node, |
| "phys", "#phy-cells"); |
| if (ssusb->num_phys > 0) { |
| ssusb->phys = devm_kcalloc(dev, ssusb->num_phys, |
| sizeof(*ssusb->phys), GFP_KERNEL); |
| if (!ssusb->phys) |
| return -ENOMEM; |
| } else { |
| ssusb->num_phys = 0; |
| } |
| |
| for (i = 0; i < ssusb->num_phys; i++) { |
| ssusb->phys[i] = devm_kzalloc(dev, sizeof(struct phy), GFP_KERNEL); |
| ret = generic_phy_get_by_index(dev, i, ssusb->phys[i]); |
| if (ret) { |
| dev_err(dev, "failed to get phy-%d\n", i); |
| return ret; |
| } |
| } |
| |
| dev_read_resource_byname(dev, "ippc", &res); |
| ssusb->ippc_base = devm_ioremap(dev, res.start, resource_size(&res)); |
| if (IS_ERR(ssusb->ippc_base)) |
| return PTR_ERR(ssusb->ippc_base); |
| |
| dev_read_resource_byname(dev, "mac", &res); |
| ssusb->mac_base = devm_ioremap(dev, res.start, resource_size(&res)); |
| if (IS_ERR(ssusb->mac_base)) |
| return PTR_ERR(ssusb->mac_base); |
| |
| ssusb->force_vbus = ofnode_read_bool(dev->node, "mediatek,force-vbus"); |
| |
| /* FIXME: usb_get_dr_mode doesn't work, assume peripheral */ |
| ssusb->dr_mode = USB_DR_MODE_PERIPHERAL; |
| if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL) |
| return 0; |
| |
| /* optional property, ignore the error if it does not exist */ |
| ofnode_read_u32(dev->node, "mediatek,u3p-dis-msk", |
| (u32 *)&ssusb->u3p_dis_msk); |
| |
| if (ssusb->dr_mode == USB_DR_MODE_HOST) |
| return 0; |
| |
| /* if dual-role mode is supported */ |
| otg_sx->is_u3_drd = ofnode_read_bool(dev->node, "mediatek,usb3-drd"); |
| otg_sx->manual_drd_enabled = |
| ofnode_read_bool(dev->node, "enable-manual-drd"); |
| |
| dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk: %x, drd: %s\n", |
| ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk, |
| otg_sx->manual_drd_enabled ? "manual" : "auto"); |
| |
| return 0; |
| } |
| |
| static int mtu3_probe(struct udevice *udev) |
| { |
| struct ssusb_mtk *ssusb; |
| int ret = -ENOMEM; |
| |
| /* all elements are set to ZERO as default value */ |
| ssusb = dev_get_platdata(udev); |
| if (!ssusb) |
| return -ENOMEM; |
| ssusb->dev = udev; |
| |
| ret = get_ssusb_rscs(udev, ssusb); |
| if (ret) |
| return ret; |
| |
| ret = ssusb_rscs_init(ssusb); |
| if (ret) |
| goto comm_init_err; |
| ssusb_ip_sw_reset(ssusb); |
| if (IS_ENABLED(CONFIG_USB_MTU3_HOST)) |
| ssusb->dr_mode = USB_DR_MODE_HOST; |
| else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET)) |
| ssusb->dr_mode = USB_DR_MODE_PERIPHERAL; |
| |
| /* default as host */ |
| ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL); |
| switch (ssusb->dr_mode) { |
| case USB_DR_MODE_PERIPHERAL: |
| ret = ssusb_gadget_init(ssusb); |
| if (ret) { |
| dev_err(dev, "failed to initialize gadget\n"); |
| goto comm_exit; |
| } |
| break; |
| default: |
| dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode); |
| ret = -EINVAL; |
| goto comm_exit; |
| } |
| |
| return 0; |
| |
| comm_exit: |
| ssusb_rscs_exit(ssusb); |
| comm_init_err: |
| |
| return ret; |
| } |
| |
| static int mtu3_remove(struct udevice *udev) |
| { |
| struct ssusb_mtk *ssusb = dev_get_platdata(udev); |
| |
| switch (ssusb->dr_mode) { |
| case USB_DR_MODE_PERIPHERAL: |
| ssusb_gadget_exit(ssusb); |
| break; |
| default: |
| return -EINVAL; |
| } |
| |
| ssusb_rscs_exit(ssusb); |
| |
| return 0; |
| } |
| |
| static const struct udevice_id mtk_mtu3_ids[] = { |
| { .compatible = "mediatek,mt8183-mtu3" }, |
| { } |
| }; |
| |
| U_BOOT_DRIVER(mtk_musb) = { |
| .name = "mtu3", |
| .id = UCLASS_USB_GADGET_GENERIC, |
| .of_match = mtk_mtu3_ids, |
| .probe = mtu3_probe, |
| .remove = mtu3_remove, |
| .platdata_auto_alloc_size = sizeof(struct ssusb_mtk), |
| }; |