| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Copyright 2018 NXP |
| */ |
| |
| #include <common.h> |
| #include <env.h> |
| #include <errno.h> |
| #include <linux/libfdt.h> |
| #include <fsl_esdhc_imx.h> |
| #include <asm/io.h> |
| #include <asm/gpio.h> |
| #include <asm/arch/clock.h> |
| #include <asm/arch/sci/sci.h> |
| #include <asm/arch/imx8-pins.h> |
| #include <asm/arch/iomux.h> |
| #include <asm/arch/sys_proto.h> |
| |
| DECLARE_GLOBAL_DATA_PTR; |
| |
| #define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ |
| (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ |
| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ |
| (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) |
| |
| #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ |
| (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ |
| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ |
| (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) |
| |
| static iomux_cfg_t uart0_pads[] = { |
| SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| }; |
| |
| static void setup_iomux_uart(void) |
| { |
| imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); |
| } |
| |
| int board_early_init_f(void) |
| { |
| sc_pm_clock_rate_t rate = SC_80MHZ; |
| int ret; |
| |
| /* Set UART0 clock root to 80 MHz */ |
| ret = sc_pm_setup_uart(SC_R_UART_0, rate); |
| if (ret) |
| return ret; |
| |
| setup_iomux_uart(); |
| |
| return 0; |
| } |
| |
| #if IS_ENABLED(CONFIG_DM_GPIO) |
| static void board_gpio_init(void) |
| { |
| struct gpio_desc desc; |
| int ret; |
| |
| ret = dm_gpio_lookup_name("gpio@1a_3", &desc); |
| if (ret) |
| return; |
| |
| ret = dm_gpio_request(&desc, "bb_per_rst_b"); |
| if (ret) |
| return; |
| |
| dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); |
| dm_gpio_set_value(&desc, 0); |
| udelay(50); |
| dm_gpio_set_value(&desc, 1); |
| } |
| #else |
| static inline void board_gpio_init(void) {} |
| #endif |
| |
| #if IS_ENABLED(CONFIG_FEC_MXC) |
| #include <miiphy.h> |
| |
| int board_phy_config(struct phy_device *phydev) |
| { |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); |
| |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); |
| |
| if (phydev->drv->config) |
| phydev->drv->config(phydev); |
| |
| return 0; |
| } |
| #endif |
| |
| int checkboard(void) |
| { |
| puts("Board: iMX8QXP MEK\n"); |
| |
| build_info(); |
| print_bootinfo(); |
| |
| return 0; |
| } |
| |
| int board_init(void) |
| { |
| board_gpio_init(); |
| |
| return 0; |
| } |
| |
| void detail_board_ddr_info(void) |
| { |
| puts("\nDDR "); |
| } |
| |
| /* |
| * Board specific reset that is system reset. |
| */ |
| void reset_cpu(ulong addr) |
| { |
| /* TODO */ |
| } |
| |
| #ifdef CONFIG_OF_BOARD_SETUP |
| int ft_board_setup(void *blob, bd_t *bd) |
| { |
| return 0; |
| } |
| #endif |
| |
| int board_mmc_get_env_dev(int devno) |
| { |
| return devno; |
| } |
| |
| int board_late_init(void) |
| { |
| #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
| env_set("board_name", "MEK"); |
| env_set("board_rev", "iMX8QXP"); |
| #endif |
| |
| return 0; |
| } |