clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data
1. pcwibits: The integer bits of pcw for PLLs has been extended
to 8 bits, add a variable to indicate this change in a
backward-compatible way.
2. fmin: The PLL frequency lower-bound can vary from 1GHz to
1.5GHz, add a variable to indicate the platform specific value.
This is a port of commit 9d7e1a82b7d195f901c2a18dd5602a1c11e9eefb from
Linux.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index a3b1f81..bdb1cb2 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -83,12 +83,16 @@
u32 fin, u32 pcw, int postdiv)
{
int pcwbits = pll->pcwbits;
- int pcwfbits;
+ int pcwfbits = 0;
+ int ibits;
u64 vco;
u8 c = 0;
/* The fractional part of the PLL divider. */
pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
+ ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
+ if (pcwbits > ibits)
+ pcwfbits = pcwbits - ibits;
vco = (u64)fin * pcw;
@@ -150,8 +154,9 @@
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
- unsigned long fmin = 1000 * MHZ;
+ unsigned long fmin = pll->fmin ? pll->fmin : (1000 * MHZ);
u64 _pcw;
+ int ibits;
u32 val;
if (freq > pll->fmax)
@@ -164,7 +169,8 @@
}
/* _pcw = freq * postdiv / xtal_rate * 2^pcwfbits */
- _pcw = ((u64)freq << val) << (pll->pcwbits - INTEGER_BITS);
+ ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
+ _pcw = ((u64)freq << val) << (pll->pcwbits - ibits);
do_div(_pcw, priv->tree->xtal2_rate);
*pcw = (u32)_pcw;
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index dce9325..7f9d709 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -35,8 +35,10 @@
int pd_shift;
u32 flags;
u32 rst_bar_mask;
+ u64 fmin;
u64 fmax;
int pcwbits;
+ int pcwibits;
u32 pcw_reg;
int pcw_shift;
};
