| /* |
| * Basic platform for gdsys mpc8308 based devices |
| * |
| * (C) Copyright 2014 |
| * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
| * |
| * based on mpc8308rdb |
| * Copyright 2009 Freescale Semiconductor Inc. |
| * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com |
| * |
| * This program is free software; you can redistribute it and/or modify it |
| * under the terms of the GNU General Public License as published by the |
| * Free Software Foundation; either version 2 of the License, or (at your |
| * option) any later version. |
| */ |
| |
| /dts-v1/; |
| |
| #include <dt-bindings/memory/mpc83xx-sdram.h> |
| |
| / { |
| compatible = "fsl,mpc8308rdb"; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| aliases { |
| serial0 = &serial0; |
| serial1 = &serial1; |
| }; |
| |
| memory { |
| device_type = "memory"; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| PowerPC,8308@0 { |
| device_type = "cpu"; |
| reg = <0x0>; |
| d-cache-line-size = <32>; |
| i-cache-line-size = <32>; |
| d-cache-size = <16384>; |
| i-cache-size = <16384>; |
| timebase-frequency = <0>; // from bootloader |
| bus-frequency = <0>; // from bootloader |
| clock-frequency = <0>; // from bootloader |
| }; |
| }; |
| |
| board_lbc: localbus@e0005000 { |
| #address-cells = <2>; |
| #size-cells = <1>; |
| compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus"; |
| reg = <0xe0005000 0x1000>; |
| interrupts = <77 0x8>; |
| interrupt-parent = <&ipic>; |
| }; |
| |
| board_soc: immr@e0000000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| device_type = "soc"; |
| compatible = "fsl,mpc8308-immr", "simple-bus"; |
| ranges = <0 0xe0000000 0x00100000>; |
| reg = <0xe0000000 0x00000200>; |
| bus-frequency = <0>; |
| |
| wdt@200 { |
| device_type = "watchdog"; |
| compatible = "mpc83xx_wdt"; |
| reg = <0x200 0x100>; |
| }; |
| |
| memory@2000 { |
| #address-cells = <2>; |
| #size-cells = <1>; |
| compatible = "fsl,mpc83xx-mem-controller"; |
| reg = <0x2000 0x1000>; |
| device_type = "memory"; |
| |
| driver_software_override = <DSO_ENABLE>; |
| p_impedance_override = <DSO_P_IMPEDANCE_NOMINAL>; |
| n_impedance_override = <DSO_N_IMPEDANCE_NOMINAL>; |
| odt_termination_value = <ODT_TERMINATION_150_OHM>; |
| ddr_type = <DDR_TYPE_DDR2_1_8_VOLT>; |
| |
| clock_adjust = <CLOCK_ADJUST_05>; |
| |
| read_to_write = <0>; |
| write_to_read = <0>; |
| read_to_read = <0>; |
| write_to_write = <0>; |
| active_powerdown_exit = <2>; |
| precharge_powerdown_exit = <6>; |
| odt_powerdown_exit = <8>; |
| mode_reg_set_cycle = <2>; |
| |
| precharge_to_activate = <2>; |
| activate_to_precharge = <6>; |
| activate_to_readwrite = <2>; |
| mcas_latency = <CASLAT_40>; |
| refresh_recovery = <17>; |
| last_data_to_precharge = <2>; |
| activate_to_activate = <2>; |
| last_write_data_to_read = <2>; |
| |
| additive_latency = <0>; |
| mcas_to_preamble_override = <READ_LAT_PLUS_1_2>; |
| write_latency = <3>; |
| read_to_precharge = <2>; |
| write_cmd_to_write_data = <CLOCK_DELAY_1_2>; |
| minimum_cke_pulse_width = <3>; |
| four_activates_window = <5>; |
| |
| self_refresh = <SREN_ENABLE>; |
| sdram_type = <TYPE_DDR2>; |
| databus_width = <DATA_BUS_WIDTH_32>; |
| |
| force_self_refresh = <MODE_NORMAL>; |
| dll_reset = <DLL_RESET_ENABLE>; |
| dqs_config = <DQS_TRUE>; |
| odt_config = <ODT_ASSERT_READS>; |
| posted_refreshes = <1>; |
| |
| refresh_interval = <2084>; |
| precharge_interval = <256>; |
| |
| sdmode = <0x0242>; |
| esdmode = <0x0440>; |
| |
| ram@0 { |
| reg = <0x0 0x0 0x8000000>; |
| compatible = "nanya,nt5tu64m16hg"; |
| |
| odt_rd_cfg = <ODT_RD_NEVER>; |
| odt_wr_cfg = <ODT_WR_ONLY_CURRENT>; |
| bank_bits = <3>; |
| row_bits = <13>; |
| col_bits = <10>; |
| }; |
| }; |
| |
| IIC:i2c@3000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cell-index = <0>; |
| compatible = "fsl-i2c"; |
| reg = <0x3000 0x100>; |
| interrupts = <14 0x8>; |
| interrupt-parent = <&ipic>; |
| dfsrr; |
| }; |
| |
| IIC2: i2c@3100 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl-i2c"; |
| reg = <0x3100 0x100>; |
| interrupts = <15 0x8>; |
| interrupt-parent = <&ipic>; |
| dfsrr; |
| status = "disabled"; |
| }; |
| |
| SPI:spi@7000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cell-index = <0>; |
| compatible = "fsl,spi"; |
| reg = <0x7000 0x1000>; |
| interrupts = <16 0x8>; |
| interrupt-parent = <&ipic>; |
| mode = "cpu"; |
| }; |
| |
| sdhc@2e000 { |
| compatible = "fsl,esdhc", "fsl,mpc8308-esdhc"; |
| reg = <0x2e000 0x1000>; |
| interrupts = <42 0x8>; |
| interrupt-parent = <&ipic>; |
| sdhci,auto-cmd12; |
| /* Filled in by U-Boot */ |
| clock-frequency = <0>; |
| }; |
| |
| serial0: serial@4500 { |
| cell-index = <0>; |
| device_type = "serial"; |
| compatible = "fsl,ns16550", "ns16550"; |
| reg = <0x4500 0x100>; |
| clock-frequency = <133333333>; |
| interrupts = <9 0x8>; |
| interrupt-parent = <&ipic>; |
| }; |
| |
| serial1: serial@4600 { |
| cell-index = <1>; |
| device_type = "serial"; |
| compatible = "fsl,ns16550", "ns16550"; |
| reg = <0x4600 0x100>; |
| clock-frequency = <133333333>; |
| interrupts = <10 0x8>; |
| interrupt-parent = <&ipic>; |
| }; |
| |
| gpio0: gpio@c00 { |
| #gpio-cells = <2>; |
| device_type = "gpio"; |
| compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio"; |
| reg = <0xc00 0x18>; |
| interrupts = <74 0x8>; |
| interrupt-parent = <&ipic>; |
| gpio-controller; |
| }; |
| |
| /* IPIC |
| * interrupts cell = <intr #, sense> |
| * sense values match linux IORESOURCE_IRQ_* defines: |
| * sense == 8: Level, low assertion |
| * sense == 2: Edge, high-to-low change |
| */ |
| ipic: interrupt-controller@700 { |
| compatible = "fsl,ipic"; |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <2>; |
| reg = <0x700 0x100>; |
| device_type = "ipic"; |
| }; |
| |
| ipic-msi@7c0 { |
| compatible = "fsl,ipic-msi"; |
| reg = <0x7c0 0x40>; |
| msi-available-ranges = <0x0 0x100>; |
| interrupts = < 0x43 0x8 |
| 0x4 0x8 |
| 0x51 0x8 |
| 0x52 0x8 |
| 0x56 0x8 |
| 0x57 0x8 |
| 0x58 0x8 |
| 0x59 0x8 >; |
| interrupt-parent = < &ipic >; |
| }; |
| |
| dma@2c000 { |
| compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma"; |
| reg = <0x2c000 0x1800>; |
| interrupts = <3 0x8 |
| 94 0x8>; |
| interrupt-parent = < &ipic >; |
| }; |
| |
| enet0: ethernet@24000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x24000 0x1000>; |
| |
| cell-index = <0>; |
| device_type = "network"; |
| model = "eTSEC"; |
| compatible = "gianfar", "fsl,tsec"; |
| reg = <0x24000 0x1000>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| interrupts = <32 0x8 33 0x8 34 0x8>; |
| interrupt-parent = <&ipic>; |
| tbi-handle = < &tbi0 >; |
| phy-handle = < &phy1 >; |
| fsl,magic-packet; |
| |
| mdio@520 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,gianfar-mdio"; |
| reg = <0x520 0x20>; |
| phy1: ethernet-phy@1 { |
| reg = <0x1>; |
| }; |
| phy2: ethernet-phy@0 { |
| reg = <0x0>; |
| device_type = "ethernet-phy"; |
| }; |
| tbi0: tbi-phy@11 { |
| reg = <0x11>; |
| device_type = "tbi-phy"; |
| }; |
| }; |
| }; |
| |
| enet1: ethernet@25000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| cell-index = <1>; |
| device_type = "network"; |
| model = "eTSEC"; |
| compatible = "gianfar", "fsl,tsec"; |
| reg = <0x25000 0x1000>; |
| ranges = <0x0 0x25000 0x1000>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| interrupts = <35 0x8 36 0x8 37 0x8>; |
| interrupt-parent = <&ipic>; |
| phy-handle = < &phy2 >; |
| status = "disabled"; |
| |
| mdio@520 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,gianfar-tbi"; |
| reg = <0x520 0x20>; |
| tbi1: tbi-phy@11 { |
| reg = <0x11>; |
| device_type = "tbi-phy"; |
| }; |
| }; |
| }; |
| }; |
| |
| pci0: pcie@e0009000 { |
| #address-cells = <3>; |
| #size-cells = <2>; |
| #interrupt-cells = <1>; |
| device_type = "pci"; |
| compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie"; |
| reg = <0xe0009000 0x00001000 |
| 0xb0000000 0x01000000>; |
| ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 |
| 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; |
| bus-range = <0 0>; |
| interrupt-map-mask = <0xf800 0 0 7>; |
| interrupt-map = <0 0 0 1 &ipic 1 8 |
| 0 0 0 2 &ipic 1 8 |
| 0 0 0 3 &ipic 1 8 |
| 0 0 0 4 &ipic 1 8>; |
| interrupts = <0x1 0x8>; |
| interrupt-parent = <&ipic>; |
| clock-frequency = <0>; |
| |
| pcie@0 { |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| reg = <0 0 0 0 0>; |
| ranges = <0x02000000 0 0xa0000000 |
| 0x02000000 0 0xa0000000 |
| 0 0x10000000 |
| 0x01000000 0 0x00000000 |
| 0x01000000 0 0x00000000 |
| 0 0x00800000>; |
| }; |
| }; |
| }; |
