| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * SPL/U-Boot mux functions for CompuLab CL-SOM-iMX7 module |
| * |
| * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com |
| * |
| * Author: Uri Mashiach <uri.mashiach@compulab.co.il> |
| */ |
| |
| #include <common.h> |
| #include <asm/mach-imx/iomux-v3.h> |
| #include <asm/arch-mx7/mx7-pins.h> |
| |
| #define PADS_SET(pads_array) \ |
| void cl_som_imx7_##pads_array##_set(void) \ |
| { \ |
| imx_iomux_v3_setup_multiple_pads(pads_array, ARRAY_SIZE(pads_array)); \ |
| } |
| |
| #ifdef CONFIG_FSL_ESDHC_IMX |
| |
| #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ |
| PAD_CTL_HYS | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_PU47KOHM) |
| |
| static iomux_v3_cfg_t const usdhc1_pads[] = { |
| MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| |
| MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| }; |
| |
| PADS_SET(usdhc1_pads) |
| |
| #endif /* CONFIG_FSL_ESDHC_IMX */ |
| |
| #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ |
| PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) |
| |
| static iomux_v3_cfg_t const uart1_pads[] = { |
| MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| }; |
| |
| PADS_SET(uart1_pads) |
| |
| #ifdef CONFIG_SPI |
| |
| #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SRE_SLOW | \ |
| PAD_CTL_DSE_3P3V_32OHM) |
| |
| #define GPIO_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_PUE | \ |
| PAD_CTL_SRE_SLOW) |
| |
| static iomux_v3_cfg_t const espi1_pads[] = { |
| MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL), |
| }; |
| |
| PADS_SET(espi1_pads) |
| |
| #endif /* CONFIG_SPI */ |
| |
| #ifndef CONFIG_SPL_BUILD |
| |
| #ifdef CONFIG_FSL_ESDHC_IMX |
| |
| static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { |
| MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| |
| MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| }; |
| |
| PADS_SET(usdhc3_emmc_pads) |
| |
| #endif /* CONFIG_FSL_ESDHC_IMX */ |
| |
| #ifdef CONFIG_FEC_MXC |
| |
| #define ENET_PAD_CTRL (PAD_CTL_PUS_PD100KOHM | PAD_CTL_DSE_3P3V_49OHM) |
| #define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU5KOHM) |
| |
| static iomux_v3_cfg_t const phy1_rst_pads[] = { |
| /* PHY1 RST */ |
| MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(GPIO_PAD_CTRL), |
| }; |
| |
| PADS_SET(phy1_rst_pads) |
| |
| static iomux_v3_cfg_t const fec1_pads[] = { |
| MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | |
| MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | |
| MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), |
| MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), |
| }; |
| |
| PADS_SET(fec1_pads) |
| |
| #endif /* CONFIG_FEC_MXC */ |
| |
| static iomux_v3_cfg_t const usb_otg1_pads[] = { |
| MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| PADS_SET(usb_otg1_pads) |
| |
| static iomux_v3_cfg_t const wdog_pads[] = { |
| MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| PADS_SET(wdog_pads) |
| |
| #endif /* !CONFIG_SPL_BUILD */ |
