| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Copyright (C) Stefano Babic <sbabic@denx.de> |
| * |
| * Based on other i.MX6 boards |
| */ |
| |
| #include <asm/arch/clock.h> |
| #include <asm/arch/imx-regs.h> |
| #include <asm/arch/iomux.h> |
| #include <asm/arch/mx6-pins.h> |
| #include <env.h> |
| #include <linux/errno.h> |
| #include <asm/gpio.h> |
| #include <asm/mach-imx/mxc_i2c.h> |
| #include <asm/mach-imx/iomux-v3.h> |
| #include <asm/mach-imx/boot_mode.h> |
| #include <asm/mach-imx/video.h> |
| #include <mmc.h> |
| #include <fsl_esdhc_imx.h> |
| #include <miiphy.h> |
| #include <netdev.h> |
| #include <asm/arch/mxc_hdmi.h> |
| #include <asm/arch/crm_regs.h> |
| #include <asm/io.h> |
| #include <asm/arch/sys_proto.h> |
| #include <i2c.h> |
| #include <input.h> |
| #include <power/pmic.h> |
| #include <power/pfuze100_pmic.h> |
| #include <asm/arch/mx6-ddr.h> |
| |
| DECLARE_GLOBAL_DATA_PTR; |
| |
| #define OPEN_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_DISABLE | (0 << 12)) |
| |
| #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
| PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ |
| PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ |
| PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ |
| PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
| PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
| |
| #define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \ |
| PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
| |
| #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ |
| PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) |
| |
| #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ |
| PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) |
| |
| #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
| PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ |
| PAD_CTL_ODE | PAD_CTL_SRE_FAST) |
| |
| #define I2C_PMIC 1 |
| |
| #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) |
| |
| #define ETH_PHY_RESET IMX_GPIO_NR(2, 4) |
| |
| int dram_init(void) |
| { |
| gd->ram_size = imx_ddr_size(); |
| |
| return 0; |
| } |
| |
| iomux_v3_cfg_t const uart2_pads[] = { |
| MX6_PAD_SD3_DAT5__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
| MX6_PAD_SD3_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
| }; |
| |
| static void setup_iomux_uart(void) |
| { |
| imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); |
| } |
| |
| #ifdef CONFIG_TARGET_ZC5202 |
| iomux_v3_cfg_t const enet_pads[] = { |
| MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK), |
| MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), |
| /* Switch Reset */ |
| MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), |
| /* Switch Interrupt */ |
| MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| /* use CRS and COL pads as GPIOs */ |
| MX6_PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(OPEN_PAD_CTRL), |
| MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(OPEN_PAD_CTRL), |
| |
| }; |
| |
| #define BOARD_NAME "EL6x-ZC5202" |
| #else |
| iomux_v3_cfg_t const enet_pads[] = { |
| MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK), |
| MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| #define BOARD_NAME "EL6x-ZC5601" |
| #endif |
| |
| static void setup_iomux_enet(void) |
| { |
| imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); |
| |
| #ifdef CONFIG_TARGET_ZC5202 |
| /* set CRS and COL to input */ |
| gpio_direction_input(IMX_GPIO_NR(4, 9)); |
| gpio_direction_input(IMX_GPIO_NR(4, 12)); |
| |
| /* Reset Switch */ |
| gpio_direction_output(ETH_PHY_RESET , 0); |
| mdelay(2); |
| gpio_set_value(ETH_PHY_RESET, 1); |
| #endif |
| } |
| |
| int board_phy_config(struct phy_device *phydev) |
| { |
| if (phydev->drv->config) |
| phydev->drv->config(phydev); |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_MXC_SPI |
| #ifdef CONFIG_TARGET_ZC5202 |
| iomux_v3_cfg_t const ecspi1_pads[] = { |
| MX6_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| MX6_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| MX6_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT15__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| iomux_v3_cfg_t const ecspi3_pads[] = { |
| MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| MX6_PAD_DISP0_DAT7__GPIO4_IO28 | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| MX6_PAD_DISP0_DAT9__GPIO4_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| MX6_PAD_DISP0_DAT10__GPIO4_IO31 | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| }; |
| #endif |
| |
| iomux_v3_cfg_t const ecspi4_pads[] = { |
| MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| int board_spi_cs_gpio(unsigned bus, unsigned cs) |
| { |
| return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS) |
| ? (IMX_GPIO_NR(3, 20)) : -1; |
| } |
| |
| static void setup_spi(void) |
| { |
| #ifdef CONFIG_TARGET_ZC5202 |
| gpio_request(IMX_GPIO_NR(5, 17), "spi_cs0"); |
| gpio_request(IMX_GPIO_NR(5, 9), "spi_cs1"); |
| gpio_direction_output(IMX_GPIO_NR(5, 17), 1); |
| gpio_direction_output(IMX_GPIO_NR(5, 9), 1); |
| imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); |
| #endif |
| |
| gpio_request(IMX_GPIO_NR(3, 20), "spi4_cs0"); |
| gpio_direction_output(IMX_GPIO_NR(3, 20), 1); |
| imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads)); |
| |
| enable_spi_clk(true, 3); |
| } |
| #endif |
| |
| static struct i2c_pads_info i2c_pad_info1 = { |
| .scl = { |
| .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | I2C_PAD, |
| .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | I2C_PAD, |
| .gp = IMX_GPIO_NR(2, 30) |
| }, |
| .sda = { |
| .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, |
| .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, |
| .gp = IMX_GPIO_NR(4, 13) |
| } |
| }; |
| |
| static struct i2c_pads_info i2c_pad_info2 = { |
| .scl = { |
| .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD, |
| .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD, |
| .gp = IMX_GPIO_NR(1, 5) |
| }, |
| .sda = { |
| .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | I2C_PAD, |
| .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | I2C_PAD, |
| .gp = IMX_GPIO_NR(7, 11) |
| } |
| }; |
| |
| iomux_v3_cfg_t const usdhc2_pads[] = { |
| MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_GPIO_4__SD2_CD_B | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
| }; |
| |
| iomux_v3_cfg_t const usdhc4_pads[] = { |
| MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| }; |
| |
| #ifdef CONFIG_FSL_ESDHC_IMX |
| struct fsl_esdhc_cfg usdhc_cfg[2] = { |
| {USDHC2_BASE_ADDR}, |
| {USDHC4_BASE_ADDR}, |
| }; |
| |
| #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) |
| |
| int board_mmc_getcd(struct mmc *mmc) |
| { |
| struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| int ret = 0; |
| |
| switch (cfg->esdhc_base) { |
| case USDHC2_BASE_ADDR: |
| ret = !gpio_get_value(USDHC2_CD_GPIO); |
| break; |
| case USDHC4_BASE_ADDR: |
| ret = 1; /* eMMC/uSDHC4 is always present */ |
| break; |
| } |
| |
| return ret; |
| } |
| |
| int board_mmc_init(bd_t *bis) |
| { |
| #ifndef CONFIG_SPL_BUILD |
| int ret; |
| int i; |
| |
| /* |
| * According to the board_mmc_init() the following map is done: |
| * (U-boot device node) (Physical Port) |
| * mmc0 SD2 |
| * mmc1 SD3 |
| * mmc2 eMMC |
| */ |
| for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
| switch (i) { |
| case 0: |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
| gpio_direction_input(USDHC2_CD_GPIO); |
| usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| break; |
| case 1: |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); |
| usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
| break; |
| default: |
| printf("Warning: you configured more USDHC controllers" |
| "(%d) then supported by the board (%d)\n", |
| i + 1, CONFIG_SYS_FSL_USDHC_NUM); |
| return -EINVAL; |
| } |
| |
| ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
| if (ret) |
| return ret; |
| } |
| |
| return 0; |
| #else |
| struct src *psrc = (struct src *)SRC_BASE_ADDR; |
| unsigned reg = readl(&psrc->sbmr1) >> 11; |
| |
| /* |
| * Upon reading BOOT_CFG register the following map is done: |
| * Bit 11 and 12 of BOOT_CFG register can determine the current |
| * mmc port |
| * 0x1 SD1 |
| * 0x2 SD2 |
| * 0x3 SD4 |
| */ |
| |
| switch (reg & 0x3) { |
| case 0x1: |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
| usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; |
| usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; |
| break; |
| case 0x3: |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); |
| usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; |
| usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
| gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; |
| break; |
| } |
| |
| return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); |
| #endif |
| |
| } |
| #endif |
| |
| |
| /* |
| * Do not overwrite the console |
| * Use always serial for U-Boot console |
| */ |
| int overwrite_console(void) |
| { |
| return 1; |
| } |
| |
| int board_eth_init(bd_t *bis) |
| { |
| setup_iomux_enet(); |
| enable_enet_clk(1); |
| |
| return cpu_eth_init(bis); |
| } |
| |
| int board_early_init_f(void) |
| { |
| |
| setup_iomux_uart(); |
| setup_spi(); |
| |
| return 0; |
| } |
| |
| int board_init(void) |
| { |
| /* address of boot parameters */ |
| gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| |
| setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); |
| setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); |
| |
| return 0; |
| } |
| |
| int power_init_board(void) |
| { |
| struct pmic *p; |
| int ret; |
| unsigned int reg; |
| |
| ret = power_pfuze100_init(I2C_PMIC); |
| if (ret) |
| return ret; |
| |
| p = pmic_get("PFUZE100"); |
| ret = pmic_probe(p); |
| if (ret) |
| return ret; |
| |
| pmic_reg_read(p, PFUZE100_DEVICEID, ®); |
| printf("PMIC: PFUZE100 ID=0x%02x\n", reg); |
| |
| /* Increase VGEN3 from 2.5 to 2.8V */ |
| pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); |
| reg &= ~LDO_VOL_MASK; |
| reg |= LDOB_2_80V; |
| pmic_reg_write(p, PFUZE100_VGEN3VOL, reg); |
| |
| /* Increase VGEN5 from 2.8 to 3V */ |
| pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); |
| reg &= ~LDO_VOL_MASK; |
| reg |= LDOB_3_00V; |
| pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); |
| |
| /* Set SW1AB stanby volage to 0.975V */ |
| pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); |
| reg &= ~SW1x_STBY_MASK; |
| reg |= SW1x_0_975V; |
| pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); |
| |
| /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ |
| pmic_reg_read(p, PFUZE100_SW1ABCONF, ®); |
| reg &= ~SW1xCONF_DVSSPEED_MASK; |
| reg |= SW1xCONF_DVSSPEED_4US; |
| pmic_reg_write(p, PFUZE100_SW1ABCONF, reg); |
| |
| /* Set SW1C standby voltage to 0.975V */ |
| pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); |
| reg &= ~SW1x_STBY_MASK; |
| reg |= SW1x_0_975V; |
| pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); |
| |
| /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ |
| pmic_reg_read(p, PFUZE100_SW1CCONF, ®); |
| reg &= ~SW1xCONF_DVSSPEED_MASK; |
| reg |= SW1xCONF_DVSSPEED_4US; |
| pmic_reg_write(p, PFUZE100_SW1CCONF, reg); |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_CMD_BMODE |
| static const struct boot_mode board_boot_modes[] = { |
| /* 4 bit bus width */ |
| {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, |
| /* 8 bit bus width */ |
| {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, |
| {NULL, 0}, |
| }; |
| #endif |
| |
| int board_late_init(void) |
| { |
| #ifdef CONFIG_CMD_BMODE |
| add_board_boot_modes(board_boot_modes); |
| #endif |
| |
| env_set("board_name", BOARD_NAME); |
| return 0; |
| } |
| |
| int checkboard(void) |
| { |
| puts("Board: "); |
| puts(BOARD_NAME "\n"); |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_SPL_BUILD |
| #include <spl.h> |
| #include <linux/libfdt.h> |
| |
| const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { |
| .dram_sdclk_0 = 0x00020030, |
| .dram_sdclk_1 = 0x00020030, |
| .dram_cas = 0x00020030, |
| .dram_ras = 0x00020030, |
| .dram_reset = 0x00020030, |
| .dram_sdcke0 = 0x00003000, |
| .dram_sdcke1 = 0x00003000, |
| .dram_sdba2 = 0x00000000, |
| .dram_sdodt0 = 0x00003030, |
| .dram_sdodt1 = 0x00003030, |
| .dram_sdqs0 = 0x00000030, |
| .dram_sdqs1 = 0x00000030, |
| .dram_sdqs2 = 0x00000030, |
| .dram_sdqs3 = 0x00000030, |
| .dram_sdqs4 = 0x00000030, |
| .dram_sdqs5 = 0x00000030, |
| .dram_sdqs6 = 0x00000030, |
| .dram_sdqs7 = 0x00000030, |
| .dram_dqm0 = 0x00020030, |
| .dram_dqm1 = 0x00020030, |
| .dram_dqm2 = 0x00020030, |
| .dram_dqm3 = 0x00020030, |
| .dram_dqm4 = 0x00020030, |
| .dram_dqm5 = 0x00020030, |
| .dram_dqm6 = 0x00020030, |
| .dram_dqm7 = 0x00020030, |
| }; |
| |
| const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { |
| .grp_ddr_type = 0x000C0000, |
| .grp_ddrmode_ctl = 0x00020000, |
| .grp_ddrpke = 0x00000000, |
| .grp_addds = 0x00000030, |
| .grp_ctlds = 0x00000030, |
| .grp_ddrmode = 0x00020000, |
| .grp_b0ds = 0x00000030, |
| .grp_b1ds = 0x00000030, |
| .grp_b2ds = 0x00000030, |
| .grp_b3ds = 0x00000030, |
| .grp_b4ds = 0x00000030, |
| .grp_b5ds = 0x00000030, |
| .grp_b6ds = 0x00000030, |
| .grp_b7ds = 0x00000030, |
| }; |
| |
| const struct mx6_mmdc_calibration mx6_mmcd_calib = { |
| .p0_mpwldectrl0 = 0x001F001F, |
| .p0_mpwldectrl1 = 0x001F001F, |
| .p1_mpwldectrl0 = 0x00440044, |
| .p1_mpwldectrl1 = 0x00440044, |
| .p0_mpdgctrl0 = 0x434B0350, |
| .p0_mpdgctrl1 = 0x034C0359, |
| .p1_mpdgctrl0 = 0x434B0350, |
| .p1_mpdgctrl1 = 0x03650348, |
| .p0_mprddlctl = 0x4436383B, |
| .p1_mprddlctl = 0x39393341, |
| .p0_mpwrdlctl = 0x35373933, |
| .p1_mpwrdlctl = 0x48254A36, |
| }; |
| |
| /* MT41K128M16JT-125 */ |
| static struct mx6_ddr3_cfg mem_ddr = { |
| .mem_speed = 1600, |
| .density = 2, |
| .width = 16, |
| .banks = 8, |
| .rowaddr = 14, |
| .coladdr = 10, |
| .pagesz = 2, |
| .trcd = 1375, |
| .trcmin = 4875, |
| .trasmin = 3500, |
| }; |
| |
| static void ccgr_init(void) |
| { |
| struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| |
| writel(0x00C03F3F, &ccm->CCGR0); |
| writel(0x0030FC03, &ccm->CCGR1); |
| writel(0x0FFFC000, &ccm->CCGR2); |
| writel(0x3FF00000, &ccm->CCGR3); |
| writel(0x00FFF300, &ccm->CCGR4); |
| writel(0x0F0000C3, &ccm->CCGR5); |
| writel(0x000003FF, &ccm->CCGR6); |
| } |
| |
| /* |
| * This section requires the differentiation between iMX6 Sabre boards, but |
| * for now, it will configure only for the mx6q variant. |
| */ |
| static void spl_dram_init(void) |
| { |
| struct mx6_ddr_sysinfo sysinfo = { |
| /* width of data bus:0=16,1=32,2=64 */ |
| .dsize = 2, |
| /* config for full 4GB range so that get_mem_size() works */ |
| .cs_density = 32, /* 32Gb per CS */ |
| /* single chip select */ |
| .ncs = 1, |
| .cs1_mirror = 0, |
| .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ |
| .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ |
| .walat = 1, /* Write additional latency */ |
| .ralat = 5, /* Read additional latency */ |
| .mif3_mode = 3, /* Command prediction working mode */ |
| .bi_on = 1, /* Bank interleaving enabled */ |
| .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ |
| .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ |
| .ddr_type = DDR_TYPE_DDR3, |
| .refsel = 1, /* Refresh cycles at 32KHz */ |
| .refr = 7, /* 8 refresh commands per refresh cycle */ |
| }; |
| |
| mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); |
| mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); |
| } |
| |
| void board_init_f(ulong dummy) |
| { |
| /* setup AIPS and disable watchdog */ |
| arch_cpu_init(); |
| |
| ccgr_init(); |
| gpr_init(); |
| |
| /* iomux and setup of i2c */ |
| board_early_init_f(); |
| |
| /* setup GP timer */ |
| timer_init(); |
| |
| /* UART clocks enabled and gd valid - init serial console */ |
| preloader_console_init(); |
| |
| /* DDR initialization */ |
| spl_dram_init(); |
| |
| /* Clear the BSS. */ |
| memset(__bss_start, 0, __bss_end - __bss_start); |
| |
| /* load/boot image from boot device */ |
| board_init_r(NULL, 0); |
| } |
| |
| #endif |
