| Memory Layout on Armada-8k SoC's |
| ================================ |
| |
| The below desribes the physical memory layout for Marvell's Armada-8k SoC's. |
| |
| This assumes that the SoC includes Dual CP configuration, in case the flavor is using |
| a single CP configuration, then all secondary-CP mappings are invalid. |
| |
| All "Reserved" areas below, are kept for future usage. |
| |
| Start End Use |
| -------------------------------------------------------------------------- |
| 0x00000000 0xEFFFFFFF DRAM |
| |
| 0xF0000000 0xF0FFFFFF AP Internal registers space |
| |
| 0xF1000000 0xF1FFFFFF Reserved. |
| |
| 0xF2000000 0xF3FFFFFF CP-0 Internal (configuration) registers |
| space. |
| |
| 0xF4000000 0xF5FFFFFF CP-1 Internal (configuration) registers |
| space. |
| |
| 0xF6000000 0xF6FFFFFF CP-0 / PCIe#0 Memory space. |
| |
| 0xF7000000 0xF7FFFFFF CP-0 / PCIe#1 Memory space. |
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| 0xF8000000 0xF8FFFFFF CP-0 / PCIe#2 Memory space. |
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| 0xF9000000 0xF900FFFF CP-0 / PCIe#0 IO space. |
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| 0xF9010000 0xF901FFFF CP-0 / PCIe#1 IO space. |
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| 0xF9020000 0xF902FFFF CP-0 / PCIe#2 IO space. |
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| 0xF9030000 0xF9FFFFFF Reserved. |
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| 0xFA000000 0xFAFFFFFF CP-1 / PCIe#0 Memory space. |
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| 0xFB000000 0xFBFFFFFF CP-1 / PCIe#1 Memory space. |
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| 0xFC000000 0xFCFFFFFF CP-1 / PCIe#2 Memory space. |
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| 0xFD000000 0xFD00FFFF CP-1 / PCIe#0 IO space. |
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| 0xFD010000 0xFD01FFFF CP-1 / PCIe#1 IO space. |
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| 0xFD020000 0xFD02FFFF CP-1 / PCIe#2 IO space. |
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| 0xFD030000 0xFFEFFFFF Reserved. |
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| 0xFFF00000 0xFFFFFFFF Bootrom |
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| 0x100000000 <DRAM Size>-1 DRAM |
| |
