| * Marvell Armada 37xx SoC pin and GPIO controller |
| |
| Each Armada 37xx SoC comes with two pin and GPIO controllers, one for the |
| South Bridge and the other for the North Bridge. |
| |
| GPIO and pin controller: |
| ------------------------ |
| |
| Main node: |
| |
| Refer to pinctrl-bindings.txt in this directory for details of the |
| common pinctrl bindings used by client devices, including the meaning |
| of the phrase "pin configuration node". |
| |
| Required properties for pinctrl driver: |
| |
| - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd" |
| for the South Bridge |
| "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd" |
| for the North Bridge |
| - reg: The first set of registers is for pinctrl/GPIO and the second |
| set is for the interrupt controller |
| - interrupts: list of interrupts used by the GPIO |
| |
| Available groups and functions for the North Bridge: |
| |
| group: jtag |
| - pins 20-24 |
| - functions jtag, gpio |
| |
| group sdio0 |
| - pins 8-10 |
| - functions sdio, gpio |
| |
| group emmc_nb |
| - pins 27-35 |
| - functions emmc, gpio |
| |
| group pwm0 |
| - pin 11 (GPIO1-11) |
| - functions pwm, gpio |
| |
| group pwm1 |
| - pin 12 |
| - functions pwm, gpio |
| |
| group pwm2 |
| - pin 13 |
| - functions pwm, gpio |
| |
| group pwm3 |
| - pin 14 |
| - functions pwm, gpio |
| |
| group pmic1 |
| - pin 7 |
| - functions pmic, gpio |
| |
| group pmic0 |
| - pin 6 |
| - functions pmic, gpio |
| |
| group i2c2 |
| - pins 2-3 |
| - functions i2c, gpio |
| |
| group i2c1 |
| - pins 0-1 |
| - functions i2c, gpio |
| |
| group spi_cs1 |
| - pin 17 |
| - functions spi, gpio |
| |
| group spi_cs2 |
| - pin 18 |
| - functions spi, gpio |
| |
| group spi_cs3 |
| - pin 19 |
| - functions spi, gpio |
| |
| group onewire |
| - pin 4 |
| - functions onewire, gpio |
| |
| group uart1 |
| - pins 25-26 |
| - functions uart, gpio |
| |
| group spi_quad |
| - pins 15-16 |
| - functions spi, gpio |
| |
| group uart_2 |
| - pins 9-10 |
| - functions uart, gpio |
| |
| Available groups and functions for the South Bridge: |
| |
| group usb32_drvvbus0 |
| - pin 36 |
| - functions drvbus, gpio |
| |
| group usb2_drvvbus1 |
| - pin 37 |
| - functions drvbus, gpio |
| |
| group sdio_sb |
| - pins 60-65 |
| - functions sdio, gpio |
| |
| group rgmii |
| - pins 42-53 |
| - functions mii, gpio |
| |
| group pcie1 |
| - pins 39-41 |
| - functions pcie, gpio |
| |
| group smi |
| - pins 54-55 |
| - functions smi, gpio |
| |
| group ptp |
| - pins 56-58 |
| - functions ptp, gpio |
| |
| group ptp_clk |
| - pin 57 |
| - functions ptp, mii |
| |
| group ptp_trig |
| - pin 58 |
| - functions ptp, mii |
| |
| group mii_col |
| - pin 59 |
| - functions mii, mii_err |
| |
| GPIO subnode: |
| |
| Please refer to gpio.txt in "gpio" directory for details of gpio-ranges property |
| and the common GPIO bindings used by client devices. |
| |
| Required properties for the GPIO driver under the gpio subnode: |
| - interrupts: List of interrupt specifiers for the controllers interrupt. |
| - gpio-controller: Marks the device node as a GPIO controller. |
| - #gpio-cells: Should be 2. The first cell is the GPIO number and the |
| second cell specifies GPIO flags, as defined in |
| <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH and |
| GPIO_ACTIVE_LOW flags are supported. |
| - gpio-ranges: Range of pins managed by the GPIO controller. |
| |
| Example: |
| pinctrl_sb: pinctrl-sb@18800 { |
| compatible = "marvell,armada3710-sb-pinctrl", |
| "syscon", "simple-mfd"; |
| reg = <0x18800 0x100>, <0x18C00 0x20>; |
| gpiosb: gpiosb { |
| #gpio-cells = <2>; |
| gpio-ranges = <&pinctrl_sb 0 0 30>; |
| gpio-controller; |
| interrupts = |
| <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| rgmii_pins: mii-pins { |
| groups = "rgmii"; |
| function = "mii"; |
| }; |
| |
| sdio_pins: sdio-pins { |
| groups = "sdio_sb"; |
| function = "sdio"; |
| }; |
| |
| pcie_pins: pcie-pins { |
| groups = "pcie1"; |
| function = "pcie"; |
| }; |
| }; |