| /* SPDX-License-Identifier: GPL-2.0+ */ |
| /* |
| * Copyright 2004, 2011 Freescale Semiconductor. |
| */ |
| |
| /* |
| * mpc8555cds board configuration file |
| * |
| * Please refer to doc/README.mpc85xxcds for more info. |
| * |
| */ |
| #ifndef __CONFIG_H |
| #define __CONFIG_H |
| |
| /* High Level Configuration Options */ |
| #define CONFIG_CPM2 1 /* has CPM2 */ |
| |
| #define CONFIG_PCI_INDIRECT_BRIDGE |
| #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
| #define CONFIG_ENV_OVERWRITE |
| |
| #define CONFIG_FSL_VIA |
| |
| #ifndef __ASSEMBLY__ |
| extern unsigned long get_clock_freq(void); |
| #endif |
| #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ |
| |
| /* |
| * These can be toggled for performance analysis, otherwise use default. |
| */ |
| #define CONFIG_L2_CACHE /* toggle L2 cache */ |
| #define CONFIG_BTB /* toggle branch predition */ |
| |
| #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
| #define CONFIG_SYS_MEMTEST_END 0x00400000 |
| |
| #define CONFIG_SYS_CCSRBAR 0xe0000000 |
| #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
| |
| /* DDR Setup */ |
| #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
| #define CONFIG_DDR_SPD |
| |
| #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| |
| #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
| #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| |
| #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
| |
| /* I2C addresses of SPD EEPROMs */ |
| #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
| |
| /* Make sure required options are set */ |
| #ifndef CONFIG_SPD_EEPROM |
| #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") |
| #endif |
| |
| #undef CONFIG_CLOCKS_IN_MHZ |
| |
| /* |
| * Local Bus Definitions |
| */ |
| |
| /* |
| * FLASH on the Local Bus |
| * Two banks, 8M each, using the CFI driver. |
| * Boot from BR0/OR0 bank at 0xff00_0000 |
| * Alternate BR1/OR1 bank at 0xff80_0000 |
| * |
| * BR0, BR1: |
| * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 |
| * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 |
| * Port Size = 16 bits = BRx[19:20] = 10 |
| * Use GPCM = BRx[24:26] = 000 |
| * Valid = BRx[31] = 1 |
| * |
| * 0 4 8 12 16 20 24 28 |
| * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 |
| * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 |
| * |
| * OR0, OR1: |
| * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 |
| * Reserved ORx[17:18] = 11, confusion here? |
| * CSNT = ORx[20] = 1 |
| * ACS = half cycle delay = ORx[21:22] = 11 |
| * SCY = 6 = ORx[24:27] = 0110 |
| * TRLX = use relaxed timing = ORx[29] = 1 |
| * EAD = use external address latch delay = OR[31] = 1 |
| * |
| * 0 4 8 12 16 20 24 28 |
| * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx |
| */ |
| |
| #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ |
| |
| #define CONFIG_SYS_BR0_PRELIM 0xff801001 |
| #define CONFIG_SYS_BR1_PRELIM 0xff001001 |
| |
| #define CONFIG_SYS_OR0_PRELIM 0xff806e65 |
| #define CONFIG_SYS_OR1_PRELIM 0xff806e65 |
| |
| #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} |
| #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ |
| #undef CONFIG_SYS_FLASH_CHECKSUM |
| #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| |
| #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| |
| #define CONFIG_SYS_FLASH_EMPTY_INFO |
| |
| /* |
| * SDRAM on the Local Bus |
| */ |
| #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
| #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
| |
| /* |
| * Base Register 2 and Option Register 2 configure SDRAM. |
| * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
| * |
| * For BR2, need: |
| * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 |
| * port-size = 32-bits = BR2[19:20] = 11 |
| * no parity checking = BR2[21:22] = 00 |
| * SDRAM for MSEL = BR2[24:26] = 011 |
| * Valid = BR[31] = 1 |
| * |
| * 0 4 8 12 16 20 24 28 |
| * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
| * |
| * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
| * FIXME: the top 17 bits of BR2. |
| */ |
| |
| #define CONFIG_SYS_BR2_PRELIM 0xf0001861 |
| |
| /* |
| * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
| * |
| * For OR2, need: |
| * 64MB mask for AM, OR2[0:7] = 1111 1100 |
| * XAM, OR2[17:18] = 11 |
| * 9 columns OR2[19-21] = 010 |
| * 13 rows OR2[23-25] = 100 |
| * EAD set for extra time OR[31] = 1 |
| * |
| * 0 4 8 12 16 20 24 28 |
| * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
| */ |
| |
| #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
| |
| #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
| #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ |
| #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ |
| #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ |
| |
| /* |
| * Common settings for all Local Bus SDRAM commands. |
| * At run time, either BSMA1516 (for CPU 1.1) |
| * or BSMA1617 (for CPU 1.0) (old) |
| * is OR'ed in too. |
| */ |
| #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ |
| | LSDMR_PRETOACT7 \ |
| | LSDMR_ACTTORW7 \ |
| | LSDMR_BL8 \ |
| | LSDMR_WRC4 \ |
| | LSDMR_CL3 \ |
| | LSDMR_RFEN \ |
| ) |
| |
| /* |
| * The CADMUS registers are connected to CS3 on CDS. |
| * The new memory map places CADMUS at 0xf8000000. |
| * |
| * For BR3, need: |
| * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 |
| * port-size = 8-bits = BR[19:20] = 01 |
| * no parity checking = BR[21:22] = 00 |
| * GPMC for MSEL = BR[24:26] = 000 |
| * Valid = BR[31] = 1 |
| * |
| * 0 4 8 12 16 20 24 28 |
| * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 |
| * |
| * For OR3, need: |
| * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 |
| * disable buffer ctrl OR[19] = 0 |
| * CSNT OR[20] = 1 |
| * ACS OR[21:22] = 11 |
| * XACS OR[23] = 1 |
| * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe |
| * SETA OR[28] = 0 |
| * TRLX OR[29] = 1 |
| * EHTR OR[30] = 1 |
| * EAD extra time OR[31] = 1 |
| * |
| * 0 4 8 12 16 20 24 28 |
| * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 |
| */ |
| |
| #define CONFIG_FSL_CADMUS |
| |
| #define CADMUS_BASE_ADDR 0xf8000000 |
| #define CONFIG_SYS_BR3_PRELIM 0xf8000801 |
| #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 |
| |
| #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
| #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
| |
| #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| |
| #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
| |
| /* Serial Port */ |
| #define CONFIG_SYS_NS16550_SERIAL |
| #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
| |
| #define CONFIG_SYS_BAUDRATE_TABLE \ |
| {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| |
| #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
| |
| /* |
| * I2C |
| */ |
| #define CONFIG_SYS_I2C |
| #define CONFIG_SYS_I2C_FSL |
| #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
| #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } |
| |
| /* EEPROM */ |
| #define CONFIG_ID_EEPROM |
| #define CONFIG_SYS_I2C_EEPROM_CCID |
| #define CONFIG_SYS_ID_EEPROM |
| #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
| |
| /* |
| * General PCI |
| * Addresses are mapped 1-1. |
| */ |
| #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
| #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
| #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
| #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
| #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
| #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
| #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
| #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ |
| |
| #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 |
| #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 |
| #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 |
| #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ |
| #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 |
| #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 |
| #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 |
| #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ |
| |
| #ifdef CONFIG_LEGACY |
| #define BRIDGE_ID 17 |
| #define VIA_ID 2 |
| #else |
| #define BRIDGE_ID 28 |
| #define VIA_ID 4 |
| #endif |
| |
| #if defined(CONFIG_PCI) |
| |
| #define CONFIG_MPC85XX_PCI2 |
| |
| #undef CONFIG_EEPRO100 |
| #undef CONFIG_TULIP |
| |
| #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
| |
| #endif /* CONFIG_PCI */ |
| |
| #if defined(CONFIG_TSEC_ENET) |
| |
| #define CONFIG_TSEC1 1 |
| #define CONFIG_TSEC1_NAME "TSEC0" |
| #define CONFIG_TSEC2 1 |
| #define CONFIG_TSEC2_NAME "TSEC1" |
| #define TSEC1_PHY_ADDR 0 |
| #define TSEC2_PHY_ADDR 1 |
| #define TSEC1_PHYIDX 0 |
| #define TSEC2_PHYIDX 0 |
| #define TSEC1_FLAGS TSEC_GIGABIT |
| #define TSEC2_FLAGS TSEC_GIGABIT |
| |
| /* Options are: TSEC[0-1] */ |
| #define CONFIG_ETHPRIME "TSEC0" |
| |
| #endif /* CONFIG_TSEC_ENET */ |
| |
| /* |
| * Environment |
| */ |
| #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
| #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
| #define CONFIG_ENV_SIZE 0x2000 |
| |
| #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| |
| /* |
| * BOOTP options |
| */ |
| #define CONFIG_BOOTP_BOOTFILESIZE |
| |
| #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| |
| /* |
| * Miscellaneous configurable options |
| */ |
| #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| |
| /* |
| * For booting Linux, the board info and command line data |
| * have to be in the first 64 MB of memory, since this is |
| * the maximum mapped by the Linux kernel during initialization. |
| */ |
| #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
| #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
| |
| #if defined(CONFIG_CMD_KGDB) |
| #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| #endif |
| |
| /* |
| * Environment Configuration |
| */ |
| #if defined(CONFIG_TSEC_ENET) |
| #define CONFIG_HAS_ETH0 |
| #define CONFIG_HAS_ETH1 |
| #define CONFIG_HAS_ETH2 |
| #endif |
| |
| #define CONFIG_IPADDR 192.168.1.253 |
| |
| #define CONFIG_HOSTNAME "unknown" |
| #define CONFIG_ROOTPATH "/nfsroot" |
| #define CONFIG_BOOTFILE "your.uImage" |
| |
| #define CONFIG_SERVERIP 192.168.1.1 |
| #define CONFIG_GATEWAYIP 192.168.1.1 |
| #define CONFIG_NETMASK 255.255.255.0 |
| |
| #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ |
| |
| #define CONFIG_EXTRA_ENV_SETTINGS \ |
| "netdev=eth0\0" \ |
| "consoledev=ttyS1\0" \ |
| "ramdiskaddr=600000\0" \ |
| "ramdiskfile=your.ramdisk.u-boot\0" \ |
| "fdtaddr=400000\0" \ |
| "fdtfile=your.fdt.dtb\0" |
| |
| #define CONFIG_NFSBOOTCOMMAND \ |
| "setenv bootargs root=/dev/nfs rw " \ |
| "nfsroot=$serverip:$rootpath " \ |
| "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| "console=$consoledev,$baudrate $othbootargs;" \ |
| "tftp $loadaddr $bootfile;" \ |
| "tftp $fdtaddr $fdtfile;" \ |
| "bootm $loadaddr - $fdtaddr" |
| |
| #define CONFIG_RAMBOOTCOMMAND \ |
| "setenv bootargs root=/dev/ram rw " \ |
| "console=$consoledev,$baudrate $othbootargs;" \ |
| "tftp $ramdiskaddr $ramdiskfile;" \ |
| "tftp $loadaddr $bootfile;" \ |
| "bootm $loadaddr $ramdiskaddr" |
| |
| #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
| |
| #endif /* __CONFIG_H */ |
