| /* |
| * Gazerbeam CON Device Tree Source |
| * |
| * (C) Copyright 2015 |
| * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
| * |
| * This program is free software; you can redistribute it and/or modify it |
| * under the terms of the GNU General Public License as published by the |
| * Free Software Foundation; either version 2 of the License, or (at your |
| * option) any later version. |
| */ |
| |
| #include "gdsys/mpc8308.dtsi" |
| |
| /include/ "gdsys/gazerbeam-base.dtsi" |
| |
| /include/ "gdsys/soc/i2c/cirrus-audio-codec.dtsi" |
| /include/ "gdsys/soc/i2c/dallas-rtc.dtsi" |
| /include/ "gdsys/soc/lbc/gazerbeam.dtsi" |
| /include/ "gdsys/soc/nor/flash-80k-partition.dtsi" |
| |
| &board_lbc { |
| FPGA0:iocon_uart@1,0 { |
| reg = <0x1 0x0 0x100000>; |
| little-endian; |
| interrupts = <48 0x8>; |
| interrupt-parent = <&ipic>; |
| }; |
| |
| FPGA1:iocon_uart@2,0 { |
| reg = <0x2 0x0 0x100000>; |
| little-endian; |
| interrupts = <17 0x8>; |
| interrupt-parent = <&ipic>; |
| }; |
| }; |
| |
| &FPGA0 { |
| compatible = "gdsys,iocon_fpga"; |
| #gpio-cells = <2>; |
| gpio-controller; |
| bus = <&FPGA0BUS>; |
| unit_id = <0>; |
| fpga-type = <1>; |
| usb_base = <0x0080>; |
| audio_base = <0x0040>; |
| timebase_base = <0x013c>; |
| |
| /* |
| * for every interrupt source there must be a dataset specifying |
| * 1. type (1: standard) |
| * 2. status register offset |
| * 3. mask register offset |
| * 4. default mask |
| */ |
| fpga_interrupt_sources = |
| <1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */ |
| <1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */ |
| /* |
| * for every interrupt there must be a dataset specifying |
| * 1. type (1: status, 2: event) |
| * 2. interrupt source index |
| * 3. interrupt register bit |
| * 4. mask register bit |
| */ |
| #fpga_interrupt_map-cells = <4>; |
| fpga_interrupt_map = |
| <1 0 14 14>, /* 0: EXTENDED_INTERRUPT */ |
| <1 0 0 0>, /* 1: VIDEO 0 */ |
| <1 0 1 1>, /* 2: VIDEO 1 */ |
| <1 0 2 2>, /* 3: VIDEO IC 0 */ |
| <1 0 3 3>, /* 4: VIDEO IC 1 */ |
| <1 0 4 4>, /* 5: IIC MAIN */ |
| <1 0 6 6>, /* 6: IIC VIDEO 0 */ |
| <1 0 7 7>, /* 7: IIC VIDEO 1 */ |
| <1 1 0 0>, /* 8: OSD 0 */ |
| <1 1 1 1>, /* 9: OSD 1 */ |
| <1 1 2 2>, /* 10: SPDIF 0 */ |
| <1 1 3 3>, /* 11: SPDIF 1 */ |
| <1 0 12 12>, /* 12: COMM 0 */ |
| <1 0 13 13>, /* 13: COMM 1 */ |
| <1 0 10 10>, /* 14: COMM 2 */ |
| <1 0 11 11>, /* 15: COMM 3 */ |
| <2 0 5 5>, /* 16: MDIO */ |
| <1 0 8 8>, /* 17: PHY */ |
| <1 1 4 4>, /* 18: RS232 */ |
| <1 1 5 5>, /* 19: AUDIO */ |
| <1 1 8 8>, /* 20: PROC_AUDIO */ |
| <1 1 7 7>, /* 21: USB/ETH-UART INT */ |
| <2 1 10 10>, /* 22: AXI Bridge 0 */ |
| <2 1 11 11>, /* 23: AXI Bridge 1 */ |
| <2 1 9 9>, /* 24: USB/ETH-Secondary IIC */ |
| <>; |
| }; |
| |
| &FPGA1 { |
| compatible = "gdsys,iocon_fpga"; |
| #gpio-cells = <2>; |
| gpio-controller; |
| bus = <&FPGA1BUS>; |
| unit_id = <1>; |
| fpga-type = <1>; |
| usb_base = <0x0070>; |
| audio_base = <0x0040>; |
| timebase_base = <0x013c>; |
| |
| /* |
| * for every interrupt source there must be a dataset specifying |
| * 1. type (1: standard) |
| * 2. status register offset |
| * 3. mask register offset |
| * 4. default mask |
| */ |
| fpga_interrupt_sources = |
| <1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */ |
| <1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */ |
| /* |
| * for every interrupt there must be a dataset specifying |
| * 1. type (1: status, 2: event) |
| * 2. interrupt source index |
| * 3. interrupt register bit |
| * 4. mask register bit |
| */ |
| #fpga_interrupt_map-cells = <4>; |
| fpga_interrupt_map = |
| <1 0 14 14>, /* 0: EXTENDED_INTERRUPT */ |
| <1 0 0 0>, /* 1: VIDEO 0 */ |
| <1 0 1 1>, /* 2: VIDEO 1 */ |
| <1 0 2 2>, /* 3: VIDEO IC 0 */ |
| <1 0 3 3>, /* 4: VIDEO IC 1 */ |
| <1 0 4 4>, /* 5: IIC MAIN */ |
| <1 0 6 6>, /* 6: IIC VIDEO 0 */ |
| <1 0 7 7>, /* 7: IIC VIDEO 1 */ |
| <1 1 0 0>, /* 8: OSD 0 */ |
| <1 1 1 1>, /* 9: OSD 1 */ |
| <1 1 2 2>, /* 10: SPDIF 0 */ |
| <1 1 3 3>, /* 11: SPDIF 1 */ |
| <1 0 12 12>, /* 12: COMM 0 */ |
| <1 0 13 13>, /* 13: COMM 1 */ |
| <1 0 10 10>, /* 14: COMM 2 */ |
| <1 0 11 11>, /* 15: COMM 3 */ |
| <2 0 5 5>, /* 16: MDIO */ |
| <1 0 8 8>, /* 17: PHY */ |
| <1 1 4 4>, /* 18: RS232 */ |
| <1 1 5 5>, /* 19: AUDIO */ |
| <1 1 8 8>, /* 20: PROC_AUDIO */ |
| <1 1 7 7>, /* 21: USB/ETH-UART INT */ |
| <2 1 10 10>, /* 22: AXI Bridge 0 */ |
| <2 1 11 11>, /* 23: AXI Bridge 1 */ |
| <2 1 9 9>, /* 24: USB/ETH-Secondary IIC */ |
| <>; |
| }; |
| |
| / { |
| FPGA0BUS: fpga0bus { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0x00002000>; |
| |
| compatible = "gdsys,soc"; |
| |
| fpga0_rs232 { |
| compatible = "gdsys,ihs_trans_rs232"; |
| reg = <0x50 0x08>; |
| little-endian; |
| }; |
| |
| fpga0_uart_usb { |
| compatible = "gdsys,ihs_simple_uart"; |
| reg = <0xa0 0x08>; |
| little-endian; |
| fpga_interrupts = <21>; |
| line = <0>; |
| }; |
| |
| fpga0_iic_main { |
| compatible = "gdsys,ihs_i2cmaster"; |
| reg = <0x60 0x10>; |
| little-endian; |
| fpga_interrupts = <5>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| fpga0_dp_video0_redriver: fpga0_dp_video0_redriver { |
| compatible = "ti,sn75dp130"; |
| reg = <0x2c>; |
| eq-i2c-enable = <3 2 1 0 |
| 3 2 1 0 |
| 3 2 1 0 |
| 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */ |
| }; |
| fpga0_dp_video1_redriver: fpga0_dp_video1_redriver { |
| compatible = "ti,sn75dp130"; |
| reg = <0x2e>; |
| eq-i2c-enable = <3 2 1 0 |
| 3 2 1 0 |
| 3 2 1 0 |
| 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */ |
| }; |
| lm77@48 { |
| compatible = "national,lm77"; |
| reg = <0x48>; |
| }; |
| ads1015@49 { |
| compatible = "ti,ads1015"; |
| reg = <0x49>; |
| }; |
| ads1015@4b { |
| compatible = "ti,ads1015"; |
| reg = <0x4b>; |
| }; |
| }; |
| |
| fpga0_video0 { |
| compatible = "gdsys,ihs_video_out"; |
| reg = <0x100 0x40>; |
| little-endian; |
| fpga_interrupts = <1 8>; /* VIDEO OSD */ |
| osd_base = <0x180>; |
| osd_buffer_base = <0x1000>; |
| spdif_audio_base = <0x1e0>; |
| video_index = <0>; |
| video_id = <0>; |
| fpga-force-pos-pol; |
| sync-source; |
| fpga-pb-pixels = <2730>; /* 8192 / 3 */ |
| fpga-ra-lines = <2>; |
| video_tx = <&fpga0_dp_video0>; |
| clk_gen = <&fpga0_video0_clkgen>; |
| ddc_ci = <&fpga0_dp_video0>; |
| }; |
| |
| fpga0_iic_video0 { |
| compatible = "gdsys,ihs_i2cmaster"; |
| reg = <0x1c0 0x10>; |
| little-endian; |
| fpga_interrupts = <6>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| fpga0_video0_clkgen: fpga0_video0_clkgen { |
| compatible = "idt,ics8n3qv01"; |
| reg = <0x6e>; |
| channel = <0>; |
| }; |
| }; |
| |
| fpga0_axi_video0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "gdsys,ihs_axi"; |
| reg = <0x170 0x10>; |
| little-endian; |
| fpga_interrupts = <22>; |
| |
| fpga0_dp_video0: fpga0_dp_video0 { |
| compatible = "gdsys,logicore_dp_tx"; |
| reg = <0x44a10000 0x1000>; |
| little-endian; |
| redriver = <&fpga0_dp_video0_redriver>; |
| video_id = <0>; |
| }; |
| }; |
| |
| fpga0_video1 { |
| compatible = "gdsys,ihs_video_out"; |
| reg = <0x200 0x40>; |
| little-endian; |
| fpga_interrupts = <2 9>; /* VIDEO OSD */ |
| osd_base = <0x280>; |
| osd_buffer_base = <0x2000>; |
| spdif_audio_base = <0x2e0>; |
| video_index = <1>; |
| video_id = <1>; |
| fpga-force-pos-pol; |
| sync-source; |
| fpga-pb-pixels = <2730>; /* 8192 / 3 */ |
| fpga-ra-lines = <2>; |
| video_tx = <&fpga0_dp_video1>; |
| clk_gen = <&fpga0_video1_clkgen>; |
| ddc_ci = <&fpga0_dp_video1>; |
| }; |
| |
| fpga0_iic_video1 { |
| compatible = "gdsys,ihs_i2cmaster"; |
| reg = <0x2c0 0x10>; |
| little-endian; |
| fpga_interrupts = <7>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| fpga0_video1_clkgen: fpga0_video1_clkgen { |
| compatible = "idt,ics8n3qv01"; |
| reg = <0x6e>; |
| channel = <1>; |
| }; |
| }; |
| |
| fpga0_axi_video1 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "gdsys,ihs_axi"; |
| reg = <0x270 0x10>; |
| little-endian; |
| fpga_interrupts = <23>; |
| |
| fpga0_dp_video1: fpga0_dp_video1 { |
| compatible = "gdsys,logicore_dp_tx"; |
| reg = <0x44a10000 0x1000>; |
| little-endian; |
| redriver = <&fpga0_dp_video1_redriver>; |
| video_id = <1>; |
| }; |
| }; |
| |
| fpga0_iic_usb { |
| compatible = "gdsys,ihs_i2cmaster"; |
| reg = <0xb0 0x10>; |
| little-endian; |
| fpga_interrupts = <24>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| pca9555@20 { |
| compatible = "nxp,pca9555"; |
| reg = <0x20>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| }; |
| }; |
| |
| fpga0_ep0 { |
| compatible = "gdsys,io-endpoint"; |
| reg = < 0x020 0x10 |
| 0x320 0x10 |
| 0x340 0x10 |
| 0x360 0x10>; |
| little-endian; |
| irq-model-local; |
| fpga_interrupts = <12 13 14 15>; |
| pollcycle = <200>; |
| nprot_channel = <16>; |
| uart_line = <0>; |
| ep_index = <0>; |
| line_protocol = <1>; |
| }; |
| |
| fpga0_mdio { |
| compatible = "gdsys,ihs_mdiomaster"; |
| reg = <0x0058 0x10>; |
| little-endian; |
| fpga_interrupts = <16>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| fpga0_phy0 { |
| compatible = "ethernet-phy-ieee802.3-c45"; |
| device_type ="ethernet-phy"; |
| reg = <0>; |
| }; |
| fpga0_phy1 { |
| compatible = "ethernet-phy-ieee802.3-c45"; |
| device_type ="ethernet-phy"; |
| reg = <1>; |
| }; |
| fpga0_phy2 { |
| compatible = "ethernet-phy-ieee802.3-c45"; |
| device_type ="ethernet-phy"; |
| reg = <2>; |
| }; |
| fpga0_phy3 { |
| compatible = "ethernet-phy-ieee802.3-c45"; |
| device_type ="ethernet-phy"; |
| reg = <3>; |
| }; |
| }; |
| |
| }; |
| |
| |
| FPGA1BUS: fpga1bus { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0x00002000>; |
| |
| compatible = "gdsys,soc"; |
| |
| fpga1_uart_usb { |
| compatible = "gdsys,ihs_simple_uart"; |
| reg = <0xa0 0x08>; |
| little-endian; |
| fpga_interrupts = <21>; |
| line = <4>; /* TODO check and FIX */ |
| }; |
| |
| fpga1_iic_main { |
| compatible = "gdsys,ihs_i2cmaster"; |
| reg = <0x60 0x10>; |
| little-endian; |
| fpga_interrupts = <5>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| fpga1_dp_video0_redriver: fpga1_dp_video0_redriver { |
| compatible = "ti,sn75dp130"; |
| reg = <0x2c>; |
| eq-i2c-enable = <3 2 1 0 |
| 3 2 1 0 |
| 3 2 1 0 |
| 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */ |
| }; |
| fpga1_dp_video1_redriver: fpga1_dp_video1_redriver { |
| compatible = "ti,sn75dp130"; |
| reg = <0x2e>; |
| eq-i2c-enable = <3 2 1 0 |
| 3 2 1 0 |
| 3 2 1 0 |
| 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */ |
| }; |
| lm77@48 { |
| compatible = "national,lm77"; |
| reg = <0x48>; |
| }; |
| ads1015@49 { |
| compatible = "ti,ads1015"; |
| reg = <0x49>; |
| }; |
| ads1015@4b { |
| compatible = "ti,ads1015"; |
| reg = <0x4b>; |
| }; |
| }; |
| |
| fpga1_video0 { |
| compatible = "gdsys,ihs_video_out"; |
| reg = <0x100 0x40>; |
| little-endian; |
| fpga_interrupts = <1 8>; /* VIDEO OSD */ |
| osd_base = <0x180>; |
| osd_buffer_base = <0x1000>; |
| spdif_audio_base = <0x1e0>; |
| video_index = <0>; |
| video_id = <4>; |
| fpga-force-pos-pol; |
| sync-source; |
| fpga-pb-pixels = <2730>; /* 8192 / 3 */ |
| fpga-ra-lines = <2>; |
| video_tx = <&fpga1_dp_video0>; |
| clk_gen = <&fpga1_video0_clkgen>; |
| ddc_ci = <&fpga1_dp_video0>; |
| }; |
| |
| fpga1_iic_video0 { |
| compatible = "gdsys,ihs_i2cmaster"; |
| reg = <0x1c0 0x10>; |
| little-endian; |
| fpga_interrupts = <6>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| fpga1_video0_clkgen: fpga1_video0_clkgen { |
| compatible = "idt,ics8n3qv01"; |
| reg = <0x6e>; |
| channel = <4>; |
| }; |
| }; |
| |
| fpga1_axi_video0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "gdsys,ihs_axi"; |
| reg = <0x170 0x10>; |
| little-endian; |
| fpga_interrupts = <22>; |
| |
| fpga1_dp_video0: fpga1_dp_video0 { |
| compatible = "gdsys,logicore_dp_tx"; |
| reg = <0x44a10000 0x1000>; |
| little-endian; |
| redriver = <&fpga1_dp_video0_redriver>; |
| video_id = <4>; |
| }; |
| }; |
| |
| fpga1_video1 { |
| compatible = "gdsys,ihs_video_out"; |
| reg = <0x200 0x40>; |
| little-endian; |
| fpga_interrupts = <2 9>; /* VIDEO OSD */ |
| osd_base = <0x280>; |
| osd_buffer_base = <0x2000>; |
| spdif_audio_base = <0x2e0>; |
| video_index = <1>; |
| video_id = <5>; |
| fpga-force-pos-pol; |
| sync-source; |
| fpga-pb-pixels = <2730>; /* 8192 / 3 */ |
| fpga-ra-lines = <2>; |
| video_tx = <&fpga1_dp_video1>; |
| clk_gen = <&fpga1_video1_clkgen>; |
| ddc_ci = <&fpga1_dp_video1>; |
| }; |
| |
| fpga1_iic_video1 { |
| compatible = "gdsys,ihs_i2cmaster"; |
| reg = <0x2c0 0x10>; |
| little-endian; |
| fpga_interrupts = <7>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| fpga1_video1_clkgen: fpga1_video1_clkgen { |
| compatible = "idt,ics8n3qv01"; |
| reg = <0x6e>; |
| channel = <5>; |
| }; |
| }; |
| |
| fpga1_axi_video1 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "gdsys,ihs_axi"; |
| reg = <0x270 0x10>; |
| little-endian; |
| fpga_interrupts = <23>; |
| |
| fpga1_dp_video1: fpga1_dp_video1 { |
| compatible = "gdsys,logicore_dp_tx"; |
| reg = <0x44a10000 0x1000>; |
| little-endian; |
| redriver = <&fpga1_dp_video1_redriver>; |
| video_id = <5>; |
| }; |
| }; |
| |
| fpga1_iic_usb { |
| compatible = "gdsys,ihs_i2cmaster"; |
| reg = <0xb0 0x10>; |
| little-endian; |
| fpga_interrupts = <24>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| pca9555@20 { |
| compatible = "nxp,pca9555"; |
| reg = <0x20>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| }; |
| }; |
| |
| fpga1_ep0 { |
| compatible = "gdsys,io-endpoint"; |
| reg = < 0x020 0x10 |
| 0x320 0x10 |
| 0x340 0x10 |
| 0x360 0x10>; |
| little-endian; |
| irq-model-local; |
| fpga_interrupts = <12 13 14 15>; |
| pollcycle = <200>; |
| nprot_channel = <17>; |
| uart_line = <1>; |
| ep_index = <0>; |
| line_protocol = <1>; |
| }; |
| |
| fpga1_mdio { |
| compatible = "gdsys,ihs_mdiomaster"; |
| reg = <0x0058 0x10>; |
| little-endian; |
| fpga_interrupts = <16>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| fpga1_phy0 { |
| compatible = "ethernet-phy-ieee802.3-c45"; |
| device_type ="ethernet-phy"; |
| reg = <0>; |
| }; |
| fpga1_phy1 { |
| compatible = "ethernet-phy-ieee802.3-c45"; |
| device_type ="ethernet-phy"; |
| reg = <1>; |
| }; |
| fpga1_phy2 { |
| compatible = "ethernet-phy-ieee802.3-c45"; |
| device_type ="ethernet-phy"; |
| reg = <2>; |
| }; |
| fpga1_phy3 { |
| compatible = "ethernet-phy-ieee802.3-c45"; |
| device_type ="ethernet-phy"; |
| reg = <3>; |
| }; |
| }; |
| |
| }; |
| |
| }; |
| |
| #include "gdsys/gazerbeam-uboot.dtsi" |
