mediatek: mt8183: configure MCUSYS DCM
Configure MCUSYS DCM.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: Ib810125b514cbcc43c770377bc71a29a05a19320
diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c
index 337470a..fcf3093 100644
--- a/plat/mediatek/mt8183/bl31_plat_setup.c
+++ b/plat/mediatek/mt8183/bl31_plat_setup.c
@@ -32,15 +32,49 @@
{
mmio_write_32((uintptr_t)&mt8183_mcucfg->mp0_rw_rsvd0, 0x00000001);
- VERBOSE("addr of cci_adb400_dcm_config: 0x%x\n",
- mmio_read_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config));
- VERBOSE("addr of sync_dcm_config: 0x%x\n",
- mmio_read_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config));
-
- VERBOSE("mp0_spmc: 0x%x\n",
- mmio_read_32((uintptr_t)&mt8183_mcucfg->mp0_cputop_spmc_ctl));
- VERBOSE("mp1_spmc: 0x%x\n",
- mmio_read_32((uintptr_t)&mt8183_mcucfg->mp1_cputop_spmc_ctl));
+ /* Mcusys dcm control */
+ /* Enable pll plldiv dcm */
+ mmio_setbits_32((uintptr_t)&mt8183_mcucfg->bus_pll_divider_cfg,
+ BUS_PLLDIV_DCM);
+ mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_pll_divider_cfg,
+ MP0_PLLDIV_DCM);
+ mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp2_pll_divider_cfg,
+ MP2_PLLDIV_DCM);
+ /* Enable mscib dcm */
+ mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en,
+ MCSIB_CACTIVE_SEL_MASK, MCSIB_CACTIVE_SEL);
+ mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en,
+ MCSIB_DCM_MASK, MCSIB_DCM);
+ /* Enable adb400 dcm */
+ mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config,
+ CCI_ADB400_DCM_MASK, CCI_ADB400_DCM);
+ /* Enable bus clock dcm */
+ mmio_setbits_32((uintptr_t)&mt8183_mcucfg->cci_clk_ctrl,
+ MCU_BUS_DCM);
+ /* Enable bus fabric dcm */
+ mmio_clrsetbits_32(
+ (uintptr_t)&mt8183_mcucfg->mcusys_bus_fabric_dcm_ctrl,
+ MCUSYS_BUS_FABRIC_DCM_MASK,
+ MCUSYS_BUS_FABRIC_DCM);
+ /* Enable l2c sram dcm */
+ mmio_setbits_32((uintptr_t)&mt8183_mcucfg->l2c_sram_ctrl,
+ L2C_SRAM_DCM);
+ /* Enable busmp0 sync dcm */
+ mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config,
+ SYNC_DCM_MASK, SYNC_DCM);
+ /* Enable cntvalue dcm */
+ mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mcu_misc_dcm_ctrl,
+ CNTVALUEB_DCM);
+ /* Enable dcm cluster stall */
+ mmio_clrsetbits_32(
+ (uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config,
+ MCUSYS_MAX_ACCESS_LATENCY_MASK,
+ MCUSYS_MAX_ACCESS_LATENCY);
+ mmio_setbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config,
+ MCU0_SYNC_DCM_STALL_WR_EN);
+ /* Enable rgu dcm */
+ mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_rgu_dcm_config,
+ CPUSYS_RGU_DCM_CINFIG);
}
/*******************************************************************************
diff --git a/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h b/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h
index 613d471..2228e63 100644
--- a/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h
+++ b/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h
@@ -136,8 +136,7 @@
/*
* MCU configuration registers
*/
-#define MCUCFG_MP0_AXI_CONFIG ((uintptr_t)&mt8183_mcucfg->mp0_axi_config)
-#define MCUCFG_MP1_AXI_CONFIG ((uintptr_t)&mt8183_mcucfg->mp1_axi_config)
+
/* bit-fields of MCUCFG_MP?_AXI_CONFIG */
#define MCUCFG_AXI_CONFIG_BROADCASTINNER (1 << 0)
#define MCUCFG_AXI_CONFIG_BROADCASTOUTER (1 << 1)
@@ -146,11 +145,6 @@
#define MCUCFG_AXI_CONFIG_ACINACTM (1 << 4)
#define MCUCFG_AXI_CONFIG_AINACTS (1 << 5)
-/* per_cpu registers for MCUCFG_MP?_AXI_CONFIG */
-static const struct per_cpu_reg MCUCFG_SCUCTRL[] = {
- [0] = { .cluster_addr = MCUCFG_MP0_AXI_CONFIG },
- [1] = { .cluster_addr = MCUCFG_MP1_AXI_CONFIG },
-};
#define MCUCFG_MP0_MISC_CONFIG2 ((uintptr_t)&mt8183_mcucfg->mp0_misc_config[2])
#define MCUCFG_MP0_MISC_CONFIG3 ((uintptr_t)&mt8183_mcucfg->mp0_misc_config[3])
diff --git a/plat/mediatek/mt8183/include/mcucfg.h b/plat/mediatek/mt8183/include/mcucfg.h
index 83ee88f..6b03818 100644
--- a/plat/mediatek/mt8183/include/mcucfg.h
+++ b/plat/mediatek/mt8183/include/mcucfg.h
@@ -28,51 +28,141 @@
uint32_t mp0_rw_rsvd0; /* 0x6C */
uint32_t mp0_rw_rsvd1; /* 0x70 */
uint32_t mp0_ro_rsvd; /* 0x74 */
- uint32_t reserved0_0[98]; /* 0x78 */
- uint32_t mp1_ca7l_cache_config; /* 0x200 */
- uint32_t mp1_miscdbg; /* 0x204 */
- uint32_t reserved0_1[9]; /* 0x208 */
- uint32_t mp1_axi_config; /* 0x22C */
- uint32_t mp1_misc_config[10]; /* 0x230 */
- uint32_t reserved0_2[3]; /* 0x258 */
- uint32_t mp1_ca7l_misc_config; /* 0x264 */
- uint32_t reserved0_3[310]; /* 0x268 */
+ uint32_t reserved0_0; /* 0x78 */
+ uint32_t mp0_l2_cache_parity1_rdata; /* 0x7C */
+ uint32_t mp0_l2_cache_parity2_rdata; /* 0x80 */
+ uint32_t reserved0_1; /* 0x84 */
+ uint32_t mp0_rgu_dcm_config; /* 0x88 */
+ uint32_t mp0_ca53_specific_ctrl; /* 0x8C */
+ uint32_t mp0_esr_case; /* 0x90 */
+ uint32_t mp0_esr_mask; /* 0x94 */
+ uint32_t mp0_esr_trig_en; /* 0x98 */
+ uint32_t reserved_0_2; /* 0x9C */
+ uint32_t mp0_ses_cg_en; /* 0xA0 */
+ uint32_t reserved0_3[216]; /* 0xA4 */
+ uint32_t mp_dbg_ctrl; /* 0x404 */
+ uint32_t reserved0_4[34]; /* 0x408 */
+ uint32_t mp_dfd_ctrl; /* 0x490 */
+ uint32_t dfd_cnt_l; /* 0x494 */
+ uint32_t dfd_cnt_h; /* 0x498 */
+ uint32_t misccfg_ro_rsvd; /* 0x49C */
+ uint32_t reserved0_5[24]; /* 0x4A0 */
+ uint32_t mp1_rst_status; /* 0x500 */
+ uint32_t mp1_dbg_ctrl; /* 0x504 */
+ uint32_t mp1_dbg_flag; /* 0x508 */
+ uint32_t mp1_ca7l_ir_mon; /* 0x50C */
+ uint32_t reserved0_6[32]; /* 0x510 */
+ uint32_t mcusys_dbg_mon_sel_a; /* 0x590 */
+ uint32_t mcucys_dbg_mon; /* 0x594 */
+ uint32_t misccfg_sec_voi_status0; /* 0x598 */
+ uint32_t misccfg_sec_vio_status1; /* 0x59C */
+ uint32_t reserved0_7[18]; /* 0x5A0 */
+ uint32_t gic500_int_mask; /* 0x5E8 */
+ uint32_t core_rst_en_latch; /* 0x5EC */
+ uint32_t reserved0_8[3]; /* 0x5F0 */
+ uint32_t dbg_core_ret; /* 0x5FC */
+ uint32_t mcusys_config_a; /* 0x600 */
+ uint32_t mcusys_config1_a; /* 0x604 */
+ uint32_t mcusys_gic_prebase_a; /* 0x608 */
+ uint32_t mcusys_pinmux; /* 0x60C */
+ uint32_t sec_range0_start; /* 0x610 */
+ uint32_t sec_range0_end; /* 0x614 */
+ uint32_t sec_range_enable; /* 0x618 */
+ uint32_t l2c_mm_base; /* 0x61C */
+ uint32_t reserved0_9[8]; /* 0x620 */
+ uint32_t aclken_div; /* 0x640 */
+ uint32_t pclken_div; /* 0x644 */
+ uint32_t l2c_sram_ctrl; /* 0x648 */
+ uint32_t armpll_jit_ctrl; /* 0x64C */
+ uint32_t cci_addrmap; /* 0x650 */
+ uint32_t cci_config; /* 0x654 */
+ uint32_t cci_periphbase; /* 0x658 */
+ uint32_t cci_nevntcntovfl; /* 0x65C */
+ uint32_t cci_clk_ctrl; /* 0x660 */
+ uint32_t cci_acel_s1_ctrl; /* 0x664 */
+ uint32_t mcusys_bus_fabric_dcm_ctrl; /* 0x668 */
+ uint32_t mcu_misc_dcm_ctrl; /* 0x66C */
+ uint32_t xgpt_ctl; /* 0x670 */
+ uint32_t xgpt_idx; /* 0x674 */
+ uint32_t reserved0_10[3]; /* 0x678 */
+ uint32_t mcusys_rw_rsvd0; /* 0x684 */
+ uint32_t mcusys_rw_rsvd1; /* 0x688 */
+ uint32_t reserved0_11[13]; /* 0x68C */
+ uint32_t gic_500_delsel_ctl; /* 0x6C0 */
+ uint32_t etb_delsel_ctl; /* 0x6C4 */
+ uint32_t etb_rst_ctl; /* 0x6C8 */
+ uint32_t reserved0_12[29]; /* 0x6CC */
uint32_t cci_adb400_dcm_config; /* 0x740 */
uint32_t sync_dcm_config; /* 0x744 */
- uint32_t reserved0_4[16]; /* 0x748 */
- uint32_t mp0_cputop_spmc_ctl; /* 0x788 */
- uint32_t mp1_cputop_spmc_ctl; /* 0x78C */
- uint32_t mp1_cputop_spmc_sram_ctl; /* 0x790 */
- uint32_t reserved0_5[23]; /* 0x794 */
+ uint32_t reserved0_13; /* 0x748 */
+ uint32_t sync_dcm_cluster_config; /* 0x74C */
+ uint32_t sw_udi; /* 0x750 */
+ uint32_t reserved0_14; /* 0x754 */
+ uint32_t gic_sync_dcm; /* 0x758 */
+ uint32_t big_dbg_pwr_ctrl; /* 0x75C */
+ uint32_t gic_cpu_periphbase; /* 0x760 */
+ uint32_t axi_cpu_config; /* 0x764 */
+ uint32_t reserved0_15[2]; /* 0x768 */
+ uint32_t mcsib_sys_ctrl1; /* 0x770 */
+ uint32_t mcsib_sys_ctrl2; /* 0x774 */
+ uint32_t mcsib_sys_ctrl3; /* 0x778 */
+ uint32_t mcsib_sys_ctrl4; /* 0x77C */
+ uint32_t mcsib_dbg_ctrl1; /* 0x780 */
+ uint32_t pwrmcu_apb2to1; /* 0x784 */
+ uint32_t mp0_spmc; /* 0x788 */
+ uint32_t reserved0_16; /* 0x78C */
+ uint32_t mp0_spmc_sram_ctl; /* 0x790 */
+ uint32_t reserved0_17; /* 0x794 */
+ uint32_t mp0_sw_rst_wait_cycle; /* 0x798 */
+ uint32_t reserved0_18; /* 0x79C */
+ uint32_t mp0_pll_divider_cfg; /* 0x7A0 */
+ uint32_t reserved0_19; /* 0x7A4 */
+ uint32_t mp2_pll_divider_cfg; /* 0x7A8 */
+ uint32_t reserved0_20[5]; /* 0x7AC */
+ uint32_t bus_pll_divider_cfg; /* 0x7C0 */
+ uint32_t reserved0_21[7]; /* 0x7C4 */
+ uint32_t clusterid_aff1; /* 0x7E0 */
+ uint32_t clusterid_aff2; /* 0x7E4 */
+ uint32_t reserved0_22[2]; /* 0x7E8 */
uint32_t l2_cfg_mp0; /* 0x7F0 */
uint32_t l2_cfg_mp1; /* 0x7F4 */
- uint32_t reserved0_6[1282]; /* 0x7F8 */
+ uint32_t reserved0_23[218]; /* 0x7F8 */
+ uint32_t mscib_dcm_en; /* 0xB60 */
+ uint32_t reserved0_24[1063]; /* 0xB64 */
uint32_t cpusys0_sparkvretcntrl; /* 0x1C00 */
uint32_t cpusys0_sparken; /* 0x1C04 */
uint32_t cpusys0_amuxsel; /* 0x1C08 */
- uint32_t reserved0_7[9]; /* 0x1C0C */
+ uint32_t reserved0_25[9]; /* 0x1C0C */
uint32_t cpusys0_cpu0_spmc_ctl; /* 0x1C30 */
uint32_t cpusys0_cpu1_spmc_ctl; /* 0x1C34 */
uint32_t cpusys0_cpu2_spmc_ctl; /* 0x1C38 */
uint32_t cpusys0_cpu3_spmc_ctl; /* 0x1C3C */
- uint32_t reserved0_8[370]; /* 0x1C40 */
+ uint32_t reserved0_26[8]; /* 0x1C40 */
+ uint32_t mp0_sync_dcm_cgavg_ctrl; /* 0x1C60 */
+ uint32_t mp0_sync_dcm_cgavg_fact; /* 0x1C64 */
+ uint32_t mp0_sync_dcm_cgavg_rfact; /* 0x1C68 */
+ uint32_t mp0_sync_dcm_cgavg; /* 0x1C6C */
+ uint32_t mp0_l2_parity_clr; /* 0x1C70 */
+ uint32_t reserved0_27[357]; /* 0x1C74 */
uint32_t mp2_cpucfg; /* 0x2208 */
uint32_t mp2_axi_config; /* 0x220C */
- uint32_t reserved0_9[36]; /* 0x2210 */
- uint32_t mp2_cputop_spm_ctl; /* 0x22A0 */
- uint32_t mp2_cputop_spm_sta; /* 0x22A4 */
- uint32_t reserved0_10[98]; /* 0x22A8 */
- uint32_t cpusys2_cpu0_spmc_ctl; /* 0x2430 */
- uint32_t cpusys2_cpu0_spmc_sta; /* 0x2434 */
- uint32_t cpusys2_cpu1_spmc_ctl; /* 0x2438 */
- uint32_t cpusys2_cpu1_spmc_sta; /* 0x243C */
- uint32_t reserved0_11[176]; /* 0x2440 */
+ uint32_t reserved0_28[25]; /* 0x2210 */
+ uint32_t mp2_sync_dcm; /* 0x2274 */
+ uint32_t reserved0_29[10]; /* 0x2278 */
+ uint32_t ptp3_cputop_spmc0; /* 0x22A0 */
+ uint32_t ptp3_cputop_spmc1; /* 0x22A4 */
+ uint32_t reserved0_30[98]; /* 0x22A8 */
+ uint32_t ptp3_cpu0_spmc0; /* 0x2430 */
+ uint32_t ptp3_cpu0_spmc1; /* 0x2434 */
+ uint32_t ptp3_cpu1_spmc0; /* 0x2438 */
+ uint32_t ptp3_cpu1_spmc1; /* 0x243C */
+ uint32_t ptp3_cpu2_spmc0; /* 0x2440 */
+ uint32_t ptp3_cpu2_spmc1; /* 0x2444 */
+ uint32_t ptp3_cpu3_spmc0; /* 0x2448 */
+ uint32_t ptp3_cpu3_spmc1; /* 0x244C */
+ uint32_t ptp3_cpux_spmc; /* 0x2450 */
+ uint32_t reserved0_31[171]; /* 0x2454 */
uint32_t spark2ld0; /* 0x2700 */
- uint32_t reserved0_12[1355]; /* 0x2704 */
- uint32_t cpusys1_cpu0_spmc_ctl; /* 0x3C30 */
- uint32_t cpusys1_cpu1_spmc_ctl; /* 0x3C34 */
- uint32_t cpusys1_cpu2_spmc_ctl; /* 0x3C38 */
- uint32_t cpusys1_cpu3_spmc_ctl; /* 0x3C3C */
};
static struct mt8183_mcucfg_regs *const mt8183_mcucfg = (void *)MCUCFG_BASE;
@@ -244,4 +334,235 @@
MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT
};
+/* bus pll divider dcm related */
+enum {
+ BUS_PLLDIVIDER_DCM_DBC_CNT_0_SHIFT = 11,
+ BUS_PLLDIV_ARMWFI_DCM_EN_SHIFT = 24,
+ BUS_PLLDIV_ARMWFE_DCM_EN_SHIFT = 25,
+
+ BUS_PLLDIV_DCM = (1 << BUS_PLLDIVIDER_DCM_DBC_CNT_0_SHIFT) |
+ (1 << BUS_PLLDIV_ARMWFI_DCM_EN_SHIFT) |
+ (1 << BUS_PLLDIV_ARMWFE_DCM_EN_SHIFT)
+};
+
+/* mp0 pll divider dcm related */
+enum {
+ MP0_PLLDIV_DCM_DBC_CNT_0_SHIFT = 11,
+ MP0_PLLDIV_ARMWFI_DCM_EN_SHIFT = 24,
+ MP0_PLLDIV_ARMWFE_DCM_EN_SHIFT = 25,
+ MP0_PLLDIV_LASTCORE_IDLE_EN_SHIFT = 31,
+ MP0_PLLDIV_DCM = (1 << MP0_PLLDIV_DCM_DBC_CNT_0_SHIFT) |
+ (1 << MP0_PLLDIV_ARMWFI_DCM_EN_SHIFT) |
+ (1 << MP0_PLLDIV_ARMWFE_DCM_EN_SHIFT) |
+ (1u << MP0_PLLDIV_LASTCORE_IDLE_EN_SHIFT)
+};
+
+/* mp2 pll divider dcm related */
+enum {
+ MP2_PLLDIV_DCM_DBC_CNT_0_SHIFT = 11,
+ MP2_PLLDIV_ARMWFI_DCM_EN_SHIFT = 24,
+ MP2_PLLDIV_ARMWFE_DCM_EN_SHIFT = 25,
+ MP2_PLLDIV_LASTCORE_IDLE_EN_SHIFT = 31,
+ MP2_PLLDIV_DCM = (1 << MP2_PLLDIV_DCM_DBC_CNT_0_SHIFT) |
+ (1 << MP2_PLLDIV_ARMWFI_DCM_EN_SHIFT) |
+ (1 << MP2_PLLDIV_ARMWFE_DCM_EN_SHIFT) |
+ (1u << MP2_PLLDIV_LASTCORE_IDLE_EN_SHIFT)
+};
+
+/* mcsib dcm related */
+enum {
+ MCSIB_CACTIVE_SEL_SHIFT = 0,
+ MCSIB_DCM_EN_SHIFT = 16,
+
+ MCSIB_CACTIVE_SEL_MASK = 0xffff << MCSIB_CACTIVE_SEL_SHIFT,
+ MCSIB_CACTIVE_SEL = 0xffff << MCSIB_CACTIVE_SEL_SHIFT,
+
+ MCSIB_DCM_MASK = 0xffffu << MCSIB_DCM_EN_SHIFT,
+ MCSIB_DCM = 0xffffu << MCSIB_DCM_EN_SHIFT,
+};
+
+/* cci adb400 dcm related */
+enum {
+ CCI_M0_ADB400_DCM_EN_SHIFT = 0,
+ CCI_M1_ADB400_DCM_EN_SHIFT = 1,
+ CCI_M2_ADB400_DCM_EN_SHIFT = 2,
+ CCI_S2_ADB400_DCM_EN_SHIFT = 3,
+ CCI_S3_ADB400_DCM_EN_SHIFT = 4,
+ CCI_S4_ADB400_DCM_EN_SHIFT = 5,
+ CCI_S5_ADB400_DCM_EN_SHIFT = 6,
+ ACP_S3_ADB400_DCM_EN_SHIFT = 11,
+
+ CCI_ADB400_DCM_MASK = (1 << CCI_M0_ADB400_DCM_EN_SHIFT) |
+ (1 << CCI_M1_ADB400_DCM_EN_SHIFT) |
+ (1 << CCI_M2_ADB400_DCM_EN_SHIFT) |
+ (1 << CCI_S2_ADB400_DCM_EN_SHIFT) |
+ (1 << CCI_S4_ADB400_DCM_EN_SHIFT) |
+ (1 << CCI_S4_ADB400_DCM_EN_SHIFT) |
+ (1 << CCI_S5_ADB400_DCM_EN_SHIFT) |
+ (1 << ACP_S3_ADB400_DCM_EN_SHIFT),
+ CCI_ADB400_DCM = (1 << CCI_M0_ADB400_DCM_EN_SHIFT) |
+ (1 << CCI_M1_ADB400_DCM_EN_SHIFT) |
+ (1 << CCI_M2_ADB400_DCM_EN_SHIFT) |
+ (0 << CCI_S2_ADB400_DCM_EN_SHIFT) |
+ (0 << CCI_S4_ADB400_DCM_EN_SHIFT) |
+ (0 << CCI_S4_ADB400_DCM_EN_SHIFT) |
+ (0 << CCI_S5_ADB400_DCM_EN_SHIFT) |
+ (1 << ACP_S3_ADB400_DCM_EN_SHIFT)
+};
+
+/* sync dcm related */
+enum {
+ CCI_SYNC_DCM_DIV_EN_SHIFT = 0,
+ CCI_SYNC_DCM_UPDATE_TOG_SHIFT = 1,
+ CCI_SYNC_DCM_DIV_SEL_SHIFT = 2,
+ MP0_SYNC_DCM_DIV_EN_SHIFT = 10,
+ MP0_SYNC_DCM_UPDATE_TOG_SHIFT = 11,
+ MP0_SYNC_DCM_DIV_SEL_SHIFT = 12,
+
+ SYNC_DCM_MASK = (1 << CCI_SYNC_DCM_DIV_EN_SHIFT) |
+ (1 << CCI_SYNC_DCM_UPDATE_TOG_SHIFT) |
+ (0x7f << CCI_SYNC_DCM_DIV_SEL_SHIFT) |
+ (1 << MP0_SYNC_DCM_DIV_EN_SHIFT) |
+ (1 << MP0_SYNC_DCM_UPDATE_TOG_SHIFT) |
+ (0x7f << MP0_SYNC_DCM_DIV_SEL_SHIFT),
+ SYNC_DCM = (1 << CCI_SYNC_DCM_DIV_EN_SHIFT) |
+ (1 << CCI_SYNC_DCM_UPDATE_TOG_SHIFT) |
+ (0 << CCI_SYNC_DCM_DIV_SEL_SHIFT) |
+ (1 << MP0_SYNC_DCM_DIV_EN_SHIFT) |
+ (1 << MP0_SYNC_DCM_UPDATE_TOG_SHIFT) |
+ (0 << MP0_SYNC_DCM_DIV_SEL_SHIFT)
+};
+
+/* mcu bus dcm related */
+enum {
+ MCU_BUS_DCM_EN_SHIFT = 8,
+ MCU_BUS_DCM = 1 << MCU_BUS_DCM_EN_SHIFT
+};
+
+/* mcusys bus fabric dcm related */
+enum {
+ ACLK_INFRA_DYNAMIC_CG_EN_SHIFT = 0,
+ EMI2_ADB400_S_DCM_CTRL_SHIFT = 1,
+ ACLK_GPU_DYNAMIC_CG_EN_SHIFT = 2,
+ ACLK_PSYS_DYNAMIC_CG_EN_SHIFT = 3,
+ MP0_ADB400_S_DCM_CTRL_SHIFT = 4,
+ MP0_ADB400_M_DCM_CTRL_SHIFT = 5,
+ MP1_ADB400_S_DCM_CTRL_SHIFT = 6,
+ MP1_ADB400_M_DCM_CTRL_SHIFT = 7,
+ EMICLK_EMI_DYNAMIC_CG_EN_SHIFT = 8,
+ INFRACLK_INFRA_DYNAMIC_CG_EN_SHIFT = 9,
+ EMICLK_GPU_DYNAMIC_CG_EN_SHIFT = 10,
+ INFRACLK_PSYS_DYNAMIC_CG_EN_SHIFT = 11,
+ EMICLK_EMI1_DYNAMIC_CG_EN_SHIFT = 12,
+ EMI1_ADB400_S_DCM_CTRL_SHIFT = 16,
+ MP2_ADB400_M_DCM_CTRL_SHIFT = 17,
+ MP0_ICC_AXI_STREAM_ARCH_CG_SHIFT = 18,
+ MP1_ICC_AXI_STREAM_ARCH_CG_SHIFT = 19,
+ MP2_ICC_AXI_STREAM_ARCH_CG_SHIFT = 20,
+ L2_SHARE_ADB400_DCM_CTRL_SHIFT = 21,
+ MP1_AGGRESS_DCM_CTRL_SHIFT = 22,
+ MP0_AGGRESS_DCM_CTRL_SHIFT = 23,
+ MP0_ADB400_ACP_S_DCM_CTRL_SHIFT = 24,
+ MP0_ADB400_ACP_M_DCM_CTRL_SHIFT = 25,
+ MP1_ADB400_ACP_S_DCM_CTRL_SHIFT = 26,
+ MP1_ADB400_ACP_M_DCM_CTRL_SHIFT = 27,
+ MP3_ADB400_M_DCM_CTRL_SHIFT = 28,
+ MP3_ICC_AXI_STREAM_ARCH_CG_SHIFT = 29,
+
+ MCUSYS_BUS_FABRIC_DCM_MASK = (1 << ACLK_INFRA_DYNAMIC_CG_EN_SHIFT) |
+ (1 << EMI2_ADB400_S_DCM_CTRL_SHIFT) |
+ (1 << ACLK_GPU_DYNAMIC_CG_EN_SHIFT) |
+ (1 << ACLK_PSYS_DYNAMIC_CG_EN_SHIFT) |
+ (1 << MP0_ADB400_S_DCM_CTRL_SHIFT) |
+ (1 << MP0_ADB400_M_DCM_CTRL_SHIFT) |
+ (1 << MP1_ADB400_S_DCM_CTRL_SHIFT) |
+ (1 << MP1_ADB400_M_DCM_CTRL_SHIFT) |
+ (1 << EMICLK_EMI_DYNAMIC_CG_EN_SHIFT) |
+ (1 << INFRACLK_INFRA_DYNAMIC_CG_EN_SHIFT) |
+ (1 << EMICLK_GPU_DYNAMIC_CG_EN_SHIFT) |
+ (1 << INFRACLK_PSYS_DYNAMIC_CG_EN_SHIFT) |
+ (1 << EMICLK_EMI1_DYNAMIC_CG_EN_SHIFT) |
+ (1 << EMI1_ADB400_S_DCM_CTRL_SHIFT) |
+ (1 << MP2_ADB400_M_DCM_CTRL_SHIFT) |
+ (1 << MP0_ICC_AXI_STREAM_ARCH_CG_SHIFT) |
+ (1 << MP1_ICC_AXI_STREAM_ARCH_CG_SHIFT) |
+ (1 << MP2_ICC_AXI_STREAM_ARCH_CG_SHIFT) |
+ (1 << L2_SHARE_ADB400_DCM_CTRL_SHIFT) |
+ (1 << MP1_AGGRESS_DCM_CTRL_SHIFT) |
+ (1 << MP0_AGGRESS_DCM_CTRL_SHIFT) |
+ (1 << MP0_ADB400_ACP_S_DCM_CTRL_SHIFT) |
+ (1 << MP0_ADB400_ACP_M_DCM_CTRL_SHIFT) |
+ (1 << MP1_ADB400_ACP_S_DCM_CTRL_SHIFT) |
+ (1 << MP1_ADB400_ACP_M_DCM_CTRL_SHIFT) |
+ (1 << MP3_ADB400_M_DCM_CTRL_SHIFT) |
+ (1 << MP3_ICC_AXI_STREAM_ARCH_CG_SHIFT),
+
+ MCUSYS_BUS_FABRIC_DCM = (1 << ACLK_INFRA_DYNAMIC_CG_EN_SHIFT) |
+ (1 << EMI2_ADB400_S_DCM_CTRL_SHIFT) |
+ (1 << ACLK_GPU_DYNAMIC_CG_EN_SHIFT) |
+ (1 << ACLK_PSYS_DYNAMIC_CG_EN_SHIFT) |
+ (0 << MP0_ADB400_S_DCM_CTRL_SHIFT) |
+ (0 << MP0_ADB400_M_DCM_CTRL_SHIFT) |
+ (1 << MP1_ADB400_S_DCM_CTRL_SHIFT) |
+ (1 << MP1_ADB400_M_DCM_CTRL_SHIFT) |
+ (1 << EMICLK_EMI_DYNAMIC_CG_EN_SHIFT) |
+ (1 << INFRACLK_INFRA_DYNAMIC_CG_EN_SHIFT) |
+ (1 << EMICLK_GPU_DYNAMIC_CG_EN_SHIFT) |
+ (1 << INFRACLK_PSYS_DYNAMIC_CG_EN_SHIFT) |
+ (1 << EMICLK_EMI1_DYNAMIC_CG_EN_SHIFT) |
+ (1 << EMI1_ADB400_S_DCM_CTRL_SHIFT) |
+ (0 << MP2_ADB400_M_DCM_CTRL_SHIFT) |
+ (1 << MP0_ICC_AXI_STREAM_ARCH_CG_SHIFT) |
+ (1 << MP1_ICC_AXI_STREAM_ARCH_CG_SHIFT) |
+ (1 << MP2_ICC_AXI_STREAM_ARCH_CG_SHIFT) |
+ (1 << L2_SHARE_ADB400_DCM_CTRL_SHIFT) |
+ (1 << MP1_AGGRESS_DCM_CTRL_SHIFT) |
+ (1 << MP0_AGGRESS_DCM_CTRL_SHIFT) |
+ (1 << MP0_ADB400_ACP_S_DCM_CTRL_SHIFT) |
+ (1 << MP0_ADB400_ACP_M_DCM_CTRL_SHIFT) |
+ (1 << MP1_ADB400_ACP_S_DCM_CTRL_SHIFT) |
+ (1 << MP1_ADB400_ACP_M_DCM_CTRL_SHIFT) |
+ (1 << MP3_ADB400_M_DCM_CTRL_SHIFT) |
+ (1 << MP3_ICC_AXI_STREAM_ARCH_CG_SHIFT)
+};
+
+/* l2c_sram dcm related */
+enum {
+ L2C_SRAM_DCM_EN_SHIFT = 0,
+ L2C_SRAM_DCM = 1 << L2C_SRAM_DCM_EN_SHIFT
+};
+
+/* mcu misc dcm related */
+enum {
+ MP0_CNTVALUEB_DCM_EN_SHIFT = 0,
+ MP_CNTVALUEB_DCM_EN = 8,
+
+ CNTVALUEB_DCM = (1 << MP0_CNTVALUEB_DCM_EN_SHIFT) |
+ (1 << MP_CNTVALUEB_DCM_EN)
+};
+
+/* sync dcm cluster config related */
+enum {
+ MP0_SYNC_DCM_STALL_WR_EN_SHIFT = 7,
+ MCUSYS_MAX_ACCESS_LATENCY_SHIFT = 24,
+
+ MCU0_SYNC_DCM_STALL_WR_EN = 1 << MP0_SYNC_DCM_STALL_WR_EN_SHIFT,
+
+ MCUSYS_MAX_ACCESS_LATENCY_MASK = 0xf << MCUSYS_MAX_ACCESS_LATENCY_SHIFT,
+ MCUSYS_MAX_ACCESS_LATENCY = 0x5 << MCUSYS_MAX_ACCESS_LATENCY_SHIFT
+};
+
+/* cpusys rgu dcm related */
+enum {
+ CPUSYS_RGU_DCM_CONFIG_SHIFT = 0,
+
+ CPUSYS_RGU_DCM_CINFIG = 1 << CPUSYS_RGU_DCM_CONFIG_SHIFT
+};
+
+/* mp2 sync dcm related */
+enum {
+ MP2_DCM_EN_SHIFT = 0,
+
+ MP2_DCM_EN = 1 << MP2_DCM_EN_SHIFT
+};
#endif /* MT8183_MCUCFG_H */
