blob: 5396ec61ccc906448968fb966c7c1c9bf700fd45 [file] [log] [blame]
/*
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/generic_delay_timer.h>
#include <lib/mmio.h>
#include <plat/common/common_def.h>
#include <plat/common/platform.h>
#include <pmic_wrap_init.h>
#include <drivers/ti/uart/uart_16550.h>
#include <mcucfg.h>
#include <mtcmos.h>
#include <mtk_plat_common.h>
#include <plat_arm.h>
#include <plat_private.h>
#include <spm.h>
#include <mtspmc.h>
#define MT6392_DIGLDO_CON28 (0x0530)
#define MT6392_DIGLDO_CON7 (0x050A)
void plat_mt_gic_driver_init(void);
void plat_mt_gic_init(void);
static entry_point_info_t bl32_ep_info;
static entry_point_info_t bl33_ep_info;
static void platform_setup_cpu(void)
{
/* set LITTLE cores arm64 boot mode */
mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw,
MP0_CPUCFG_64BIT);
spmc_init();
}
static void platform_setup_sram(void)
{
/* protect BL31 memory from non-secure read/write access */
mmio_write_32(SRAMROM_SEC_ADDR, (uint32_t)(BL31_END + 0x3ff) & 0x3fc00);
mmio_write_32(SRAMROM_SEC_CTRL, 0x10000ff9);
}
/*******************************************************************************
* Return a pointer to the 'entry_point_info' structure of the next image for
* the security state specified. BL33 corresponds to the non-secure image type
* while BL32 corresponds to the secure image type. A NULL pointer is returned
* if the image does not exist.
******************************************************************************/
entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
{
entry_point_info_t *next_image_info;
next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
/* None of the images on this platform can have 0x0 as the entrypoint */
if (next_image_info->pc)
return next_image_info;
else
return NULL;
}
uint32_t plat_get_spsr_for_bl32_entry(void)
{
/*
* The Secure Payload Dispatcher service is responsible for
* setting the SPSR prior to entry into the BL3-2 image.
*/
return 0;
}
#define LINUX_KERNEL_32 0
#define HRID_SIZE 2
#define DEVINFO_SIZE 4
typedef struct {
unsigned int atf_magic;
unsigned int tee_support;
unsigned int tee_entry;
unsigned int tee_boot_arg_addr;
unsigned int hwuid[4]; // HW Unique id for t-base used
unsigned int HRID[HRID_SIZE]; // HW random id for t-base used
unsigned int atf_log_port;
unsigned int atf_log_baudrate;
unsigned int atf_log_buf_start;
unsigned int atf_log_buf_size;
unsigned int atf_irq_num;
unsigned int devinfo[DEVINFO_SIZE];
unsigned int atf_aee_debug_buf_start;
unsigned int atf_aee_debug_buf_size;
} atf_arg_t, *atf_arg_t_ptr;
/*******************************************************************************
* Perform any BL3-1 early platform setup. Here is an opportunity to copy
* parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they
* are lost (potentially). This needs to be done before the MMU is initialized
* so that the memory layout can be used while creating page tables.
* BL2 has flushed this information to memory, so we are guaranteed to pick up
* good data.
******************************************************************************/
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
static console_16550_t console;
console_16550_register(MT8516_UART0_BASE, MT8516_UART_CLOCK, MT8516_BAUDRATE, &console);
/* Populate entry point information for BL3-2 and BL3-3 */
SET_PARAM_HEAD(&bl32_ep_info,
PARAM_EP,
VERSION_1,
0);
SET_SECURITY_STATE(bl32_ep_info.h.attr, SECURE);
bl32_ep_info.pc = BL32_BASE;
bl32_ep_info.spsr = plat_get_spsr_for_bl32_entry();
SET_PARAM_HEAD(&bl33_ep_info,
PARAM_EP,
VERSION_1,
0);
/*
* Tell BL3-1 where the non-trusted software image
* is located and the entry state information
*/
bl33_ep_info.pc = BL33_BASE;
bl33_ep_info.spsr = plat_get_spsr_for_bl33_entry();
SET_SECURITY_STATE(bl33_ep_info.h.attr, NON_SECURE);
}
/*******************************************************************************
* Perform any BL3-1 platform setup code
******************************************************************************/
void bl31_platform_setup(void)
{
platform_setup_cpu();
platform_setup_sram();
generic_delay_timer_init();
/* Initialize the gic cpu and distributor interfaces */
plat_mt_gic_driver_init();
plat_mt_gic_init();
// Enable VGP1 regulator at 3.3V
pwrap_write(MT6392_DIGLDO_CON28, 0xE0);
pwrap_write(MT6392_DIGLDO_CON7, (1 << 15));
// plat_arm_gic_driver_init();
// plat_arm_gic_init();
/* Initialize spm at boot time */
// spm_boot_init();
}
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way.
******************************************************************************/
void bl31_plat_arch_setup(void)
{
plat_cci_init();
plat_cci_enable();
plat_configure_mmu_el3(BL_CODE_BASE,
BL_COHERENT_RAM_END - BL_CODE_BASE,
BL_CODE_BASE,
BL_CODE_END,
BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END);
}