mediatek: mt8183: add MTK MCDI driver
Add MCDI driver for power saving.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I93ecff4d7581f678be09dd8fb5dfaaccd5f2c22c
diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c
index fd3a5b0..ec387f4 100644
--- a/plat/mediatek/mt8183/bl31_plat_setup.c
+++ b/plat/mediatek/mt8183/bl31_plat_setup.c
@@ -16,6 +16,7 @@
#include <mt_gic_v3.h>
#include <lib/coreboot.h>
#include <lib/mmio.h>
+#include <mtk_mcdi.h>
#include <mtk_plat_common.h>
#include <mtspmc.h>
#include <plat_debug.h>
@@ -148,6 +149,7 @@
spmc_init();
#endif
spm_boot_init();
+ mcdi_init();
}
/*******************************************************************************
diff --git a/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.c b/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.c
new file mode 100644
index 0000000..29eebcb
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <sspm_reg.h>
+#include <mtk_mcdi.h>
+
+static inline uint32_t mcdi_mbox_read(uint32_t id)
+{
+ return mmio_read_32(SSPM_MBOX_3_BASE + (id << 2));
+}
+
+static inline void mcdi_mbox_write(uint32_t id, uint32_t val)
+{
+ mmio_write_32(SSPM_MBOX_3_BASE + (id << 2), val);
+}
+
+void sspm_set_bootaddr(uint32_t bootaddr)
+{
+ mcdi_mbox_write(MCDI_MBOX_BOOTADDR, bootaddr);
+}
+
+void sspm_cluster_pwr_off_notify(uint32_t cluster)
+{
+ mcdi_mbox_write(MCDI_MBOX_CLUSTER_0_ATF_ACTION_DONE + cluster, 1);
+}
+
+void sspm_cluster_pwr_on_notify(uint32_t cluster)
+{
+ mcdi_mbox_write(MCDI_MBOX_CLUSTER_0_ATF_ACTION_DONE + cluster, 0);
+}
+
+void sspm_standbywfi_irq_enable(uint32_t cpu_idx)
+{
+ mmio_write_32(SSPM_CFGREG_ACAO_INT_SET, STANDBYWFI_EN(cpu_idx));
+}
+
+uint32_t mcdi_avail_cpu_mask_read(void)
+{
+ return mcdi_mbox_read(MCDI_MBOX_AVAIL_CPU_MASK);
+}
+
+uint32_t mcdi_avail_cpu_mask_write(uint32_t mask)
+{
+ mcdi_mbox_write(MCDI_MBOX_AVAIL_CPU_MASK, mask);
+
+ return mask;
+}
+
+uint32_t mcdi_avail_cpu_mask_set(uint32_t mask)
+{
+ uint32_t m;
+
+ m = mcdi_mbox_read(MCDI_MBOX_AVAIL_CPU_MASK);
+ m |= mask;
+ mcdi_mbox_write(MCDI_MBOX_AVAIL_CPU_MASK, m);
+
+ return m;
+}
+
+uint32_t mcdi_avail_cpu_mask_clr(uint32_t mask)
+{
+ uint32_t m;
+
+ m = mcdi_mbox_read(MCDI_MBOX_AVAIL_CPU_MASK);
+ m &= ~mask;
+ mcdi_mbox_write(MCDI_MBOX_AVAIL_CPU_MASK, m);
+
+ return m;
+}
+
+uint32_t mcdi_cpu_cluster_pwr_stat_read(void)
+{
+ return mcdi_mbox_read(MCDI_MBOX_CPU_CLUSTER_PWR_STAT);
+}
+
+#define PAUSE_BIT 1
+#define CLUSTER_OFF_OFS 20
+#define CPU_OFF_OFS 24
+#define CLUSTER_ON_OFS 4
+#define CPU_ON_OFS 8
+
+static uint32_t target_mask(int cluster, int cpu_idx, bool on)
+{
+ uint32_t t = 0;
+
+ if (on) {
+ if (cluster >= 0)
+ t |= BIT(cluster + CLUSTER_ON_OFS);
+
+ if (cpu_idx >= 0)
+ t |= BIT(cpu_idx + CPU_ON_OFS);
+ } else {
+ if (cluster >= 0)
+ t |= BIT(cluster + CLUSTER_OFF_OFS);
+
+ if (cpu_idx >= 0)
+ t |= BIT(cpu_idx + CPU_OFF_OFS);
+ }
+
+ return t;
+}
+
+void mcdi_pause_clr(int cluster, int cpu_idx, bool on)
+{
+ uint32_t tgt = target_mask(cluster, cpu_idx, on);
+ uint32_t m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION);
+
+ m &= ~tgt;
+ mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m);
+}
+
+void mcdi_pause_set(int cluster, int cpu_idx, bool on)
+{
+ uint32_t tgt = target_mask(cluster, cpu_idx, on);
+ uint32_t m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION);
+ uint32_t tgtn = target_mask(-1, cpu_idx, !on);
+
+ /* request on and off at the same time to ensure it can be paused */
+ m |= tgt | tgtn;
+ mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m);
+
+ /* wait pause_ack */
+ while (!mcdi_mbox_read(MCDI_MBOX_PAUSE_ACK))
+ ;
+
+ /* clear non-requested operation */
+ m &= ~tgtn;
+ mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m);
+}
+
+void mcdi_pause(void)
+{
+ uint32_t m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION) | BIT(PAUSE_BIT);
+
+ mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m);
+
+ /* wait pause_ack */
+ while (!mcdi_mbox_read(MCDI_MBOX_PAUSE_ACK))
+ ;
+}
+
+void mcdi_unpause(void)
+{
+ uint32_t m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION) & ~BIT(PAUSE_BIT);
+
+ mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m);
+}
+
+void mcdi_hotplug_wait_ack(int cluster, int cpu_idx, bool on)
+{
+ uint32_t tgt = target_mask(cluster, cpu_idx, on);
+ uint32_t ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK);
+
+ /* wait until ack */
+ while (!(ack & tgt))
+ ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK);
+}
+
+void mcdi_hotplug_clr(int cluster, int cpu_idx, bool on)
+{
+ uint32_t tgt = target_mask(cluster, cpu_idx, on);
+ uint32_t tgt_cpu = target_mask(-1, cpu_idx, on);
+ uint32_t cmd = mcdi_mbox_read(MCDI_MBOX_HP_CMD);
+ uint32_t ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK);
+
+ if (!(cmd & tgt))
+ return;
+
+ /* wait until ack */
+ while (!(ack & tgt_cpu))
+ ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK);
+
+ cmd &= ~tgt;
+ mcdi_mbox_write(MCDI_MBOX_HP_CMD, cmd);
+}
+
+void mcdi_hotplug_set(int cluster, int cpu_idx, bool on)
+{
+ uint32_t tgt = target_mask(cluster, cpu_idx, on);
+ uint32_t tgt_cpu = target_mask(-1, cpu_idx, on);
+ uint32_t cmd = mcdi_mbox_read(MCDI_MBOX_HP_CMD);
+ uint32_t ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK);
+
+ if ((cmd & tgt) == tgt)
+ return;
+
+ /* wait until ack clear */
+ while (ack & tgt_cpu)
+ ack = mcdi_mbox_read(MCDI_MBOX_HP_ACK);
+
+ cmd |= tgt;
+ mcdi_mbox_write(MCDI_MBOX_HP_CMD, cmd);
+}
+
+bool check_mcdi_ctl_stat(void)
+{
+ uint32_t clk_regs[] = {0x100010ac, 0x100010c8};
+ uint32_t clk_mask[] = {0x00028000, 0x00000018};
+ uint32_t tgt = target_mask(0, 0, true);
+ uint32_t m;
+ int i;
+
+ /* check clk status */
+ for (i = 0; i < ARRAY_SIZE(clk_regs); i++) {
+ if (mmio_read_32(clk_regs[i]) & clk_mask[i]) {
+ WARN("mcdi: clk check fail.\n");
+ return false;
+ }
+ }
+
+ /* check mcdi cmd handling */
+ m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION) | BIT(PAUSE_BIT);
+ mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m);
+
+ i = 500;
+ while (!mcdi_mbox_read(MCDI_MBOX_PAUSE_ACK) && --i > 0)
+ udelay(10);
+
+ m = mcdi_mbox_read(MCDI_MBOX_PAUSE_ACTION) & ~BIT(PAUSE_BIT);
+ mcdi_mbox_write(MCDI_MBOX_PAUSE_ACTION, m);
+
+ if (i == 0) {
+ WARN("mcdi: pause_action fail.\n");
+ return false;
+ }
+
+ /* check mcdi cmd handling */
+ if (mcdi_mbox_read(MCDI_MBOX_HP_CMD) ||
+ mcdi_mbox_read(MCDI_MBOX_HP_ACK)) {
+ WARN("mcdi: hp_cmd fail.\n");
+ return false;
+ }
+
+ mcdi_mbox_write(MCDI_MBOX_HP_CMD, tgt);
+
+ i = 500;
+ while ((mcdi_mbox_read(MCDI_MBOX_HP_ACK) & tgt) != tgt && --i > 0)
+ udelay(10);
+
+ mcdi_mbox_write(MCDI_MBOX_HP_CMD, 0);
+
+ if (i == 0) {
+ WARN("mcdi: hp_ack fail.\n");
+ return false;
+ }
+
+ return true;
+}
+
+void mcdi_init(void)
+{
+ mcdi_avail_cpu_mask_write(0x01); /* cpu0 default on */
+}
diff --git a/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.h b/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.h
new file mode 100644
index 0000000..9a40df1
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __MTK_MCDI_H__
+#define __MTK_MCDI_H__
+
+#include <stdbool.h>
+
+void sspm_set_bootaddr(uint32_t bootaddr);
+void sspm_standbywfi_irq_enable(uint32_t cpu_idx);
+void sspm_cluster_pwr_off_notify(uint32_t cluster);
+void sspm_cluster_pwr_on_notify(uint32_t cluster);
+
+uint32_t mcdi_avail_cpu_mask_read(void);
+uint32_t mcdi_avail_cpu_mask_write(uint32_t mask);
+uint32_t mcdi_avail_cpu_mask_set(uint32_t mask);
+uint32_t mcdi_avail_cpu_mask_clr(uint32_t mask);
+uint32_t mcdi_cpu_cluster_pwr_stat_read(void);
+
+void mcdi_pause(void);
+void mcdi_unpause(void);
+void mcdi_pause_set(int cluster, int cpu_idx, bool on);
+void mcdi_pause_clr(int cluster, int cpu_idx, bool on);
+void mcdi_hotplug_set(int cluster, int cpu_idx, bool on);
+void mcdi_hotplug_clr(int cluster, int cpu_idx, bool on);
+void mcdi_hotplug_wait_ack(int cluster, int cpu_idx, bool on);
+
+bool check_mcdi_ctl_stat(void);
+void mcdi_init(void);
+
+#endif /* __MTK_MCDI_H__ */
diff --git a/plat/mediatek/mt8183/include/sspm_reg.h b/plat/mediatek/mt8183/include/sspm_reg.h
new file mode 100644
index 0000000..3f1ac86
--- /dev/null
+++ b/plat/mediatek/mt8183/include/sspm_reg.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SSPM_REG_H__
+#define __SSPM_REG_H__
+
+#include "platform_def.h"
+
+#define SSPM_CFGREG_RSV_RW_REG0 (SSPM_CFGREG_BASE + 0x0100)
+#define SSPM_CFGREG_ACAO_INT_SET (SSPM_CFGREG_BASE + 0x00D8)
+#define SSPM_CFGREG_ACAO_INT_CLR (SSPM_CFGREG_BASE + 0x00DC)
+#define SSPM_CFGREG_ACAO_WAKEUP_EN (SSPM_CFGREG_BASE + 0x0204)
+
+#define STANDBYWFI_EN(n) (1 << (n + 8))
+#define GIC_IRQOUT_EN(n) (1 << (n + 0))
+
+#define NF_MCDI_MBOX 19
+#define MCDI_MBOX_CLUSTER_0_CAN_POWER_OFF 0
+#define MCDI_MBOX_CLUSTER_1_CAN_POWER_OFF 1
+#define MCDI_MBOX_BUCK_POWER_OFF_MASK 2
+#define MCDI_MBOX_CLUSTER_0_ATF_ACTION_DONE 3
+#define MCDI_MBOX_CLUSTER_1_ATF_ACTION_DONE 4
+#define MCDI_MBOX_BOOTADDR 5
+#define MCDI_MBOX_PAUSE_ACTION 6
+#define MCDI_MBOX_AVAIL_CPU_MASK 7
+#define MCDI_MBOX_CPU_CLUSTER_PWR_STAT 8
+#define MCDI_MBOX_ACTION_STAT 9
+#define MCDI_MBOX_CLUSTER_0_CNT 10
+#define MCDI_MBOX_CLUSTER_1_CNT 11
+#define MCDI_MBOX_CPU_ISOLATION_MASK 12
+#define MCDI_MBOX_PAUSE_ACK 13
+#define MCDI_MBOX_PENDING_ON_EVENT 14
+#define MCDI_MBOX_PROF_CMD 15
+#define MCDI_MBOX_DRCC_CALI_DONE 16
+#define MCDI_MBOX_HP_CMD 17
+#define MCDI_MBOX_HP_ACK 18
+
+#endif /* __SSPM_REG_H__ */
diff --git a/plat/mediatek/mt8183/plat_pm.c b/plat/mediatek/mt8183/plat_pm.c
index 9e0a920..555b389 100644
--- a/plat/mediatek/mt8183/plat_pm.c
+++ b/plat/mediatek/mt8183/plat_pm.c
@@ -16,6 +16,7 @@
#include <platform_def.h>
#include <scu.h>
#include <mt_gic_v3.h>
+#include <mtk_mcdi.h>
#include <mtk_plat_common.h>
#include <mtgpio.h>
#include <mtspmc.h>
@@ -27,9 +28,101 @@
#include <pmic.h>
#include <spm.h>
#include <spm_suspend.h>
+#include <sspm.h>
#include <rtc.h>
-#define MTK_LOCAL_STATE_OFF 2
+/* Local power state for power domains in Run state. */
+#define MTK_LOCAL_STATE_RUN 0
+/* Local power state for retention. */
+#define MTK_LOCAL_STATE_RET 1
+/* Local power state for OFF/power-down. */
+#define MTK_LOCAL_STATE_OFF 2
+
+#if PSCI_EXTENDED_STATE_ID
+/*
+ * Macros used to parse state information from State-ID if it is using the
+ * recommended encoding for State-ID.
+ */
+#define MTK_LOCAL_PSTATE_WIDTH 4
+#define MTK_LOCAL_PSTATE_MASK ((1 << MTK_LOCAL_PSTATE_WIDTH) - 1)
+
+/* Macros to construct the composite power state */
+
+/* Make composite power state parameter till power level 0 */
+
+#define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
+ (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT))
+
+#else /* !PSCI_EXTENDED_STATE_ID */
+
+#define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
+ (((lvl0_state) << PSTATE_ID_SHIFT) | \
+ ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \
+ ((type) << PSTATE_TYPE_SHIFT))
+
+#endif /* PSCI_EXTENDED_STATE_ID */
+
+/* Make composite power state parameter till power level 1 */
+#define mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \
+ (((lvl1_state) << MTK_LOCAL_PSTATE_WIDTH) | \
+ mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
+
+/* Make composite power state parameter till power level 2 */
+#define mtk_make_pwrstate_lvl2( \
+ lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \
+ (((lvl2_state) << (MTK_LOCAL_PSTATE_WIDTH * 2)) | \
+ mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type))
+
+#define MTK_PWR_LVL0 0
+#define MTK_PWR_LVL1 1
+#define MTK_PWR_LVL2 2
+
+/* Macros to read the MTK power domain state */
+#define MTK_CORE_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL0]
+#define MTK_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL1]
+#define MTK_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) ? \
+ (state)->pwr_domain_state[MTK_PWR_LVL2] : 0)
+
+#if PSCI_EXTENDED_STATE_ID
+/*
+ * The table storing the valid idle power states. Ensure that the
+ * array entries are populated in ascending order of state-id to
+ * enable us to use binary search during power state validation.
+ * The table must be terminated by a NULL entry.
+ */
+const unsigned int mtk_pm_idle_states[] = {
+ /* State-id - 0x001 */
+ mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_RUN, MTK_LOCAL_STATE_RUN,
+ MTK_LOCAL_STATE_RET, MTK_PWR_LVL0, PSTATE_TYPE_STANDBY),
+ /* State-id - 0x002 */
+ mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_RUN, MTK_LOCAL_STATE_RUN,
+ MTK_LOCAL_STATE_OFF, MTK_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
+ /* State-id - 0x022 */
+ mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_RUN, MTK_LOCAL_STATE_OFF,
+ MTK_LOCAL_STATE_OFF, MTK_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
+#if PLAT_MAX_PWR_LVL > MTK_PWR_LVL1
+ /* State-id - 0x222 */
+ mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_OFF, MTK_LOCAL_STATE_OFF,
+ MTK_LOCAL_STATE_OFF, MTK_PWR_LVL2, PSTATE_TYPE_POWERDOWN),
+#endif
+ 0,
+};
+#endif
+
+#define CPU_IDX(cluster, cpu) ((cluster << 2) + cpu)
+#define ON true
+#define OFF false
+
+/* Pause MCDI when CPU hotplug */
+static bool HP_SSPM_PAUSE;
+/* CPU Hotplug by SSPM */
+static bool HP_SSPM_CTRL = true;
+/* Turn off cluster when CPU hotplug off */
+static bool HP_CLUSTER_OFF = true;
+/* Turn off cluster when CPU MCDI off */
+static bool MCDI_C2 = true;
+/* Enable MCDI */
+static bool MCDI_SSPM = true;
static uintptr_t secure_entrypoint;
@@ -40,30 +133,171 @@
dsb();
}
+static bool clst_single_pwr(int cluster, int cpu)
+{
+ uint32_t cpu_mask[2] = {0x00001e00, 0x000f0000};
+ uint32_t cpu_pwr_bit[] = {9, 10, 11, 12, 16, 17, 18, 19};
+ int my_idx = (cluster << 2) + cpu;
+ uint32_t pwr_stat = mmio_read_32(0x10006180);
+
+ return !(pwr_stat & (cpu_mask[cluster] & ~BIT(cpu_pwr_bit[my_idx])));
+}
+
+static bool clst_single_on(int cluster, int cpu)
+{
+ uint32_t cpu_mask[2] = {0x0f, 0xf0};
+ int my_idx = (cluster << 2) + cpu;
+ uint32_t on_stat = mcdi_avail_cpu_mask_read();
+
+ return !(on_stat & (cpu_mask[cluster] & ~BIT(my_idx)));
+}
+
+static void plat_cluster_pwrdwn_common(uint64_t mpidr, int cluster)
+{
+ if (cluster > 0)
+ mt_gic_sync_dcm_enable();
+
+ /* Disable coherency */
+ plat_mtk_cci_disable();
+ disable_scu(mpidr);
+}
+
+static void plat_cluster_pwron_common(uint64_t mpidr, int cluster)
+{
+ if (cluster > 0) {
+ l2c_parity_check_setup();
+ circular_buffer_setup();
+ mp1_L2_desel_config();
+ mt_gic_sync_dcm_disable();
+ }
+
+ /* Enable coherency */
+ enable_scu(mpidr);
+ plat_mtk_cci_enable();
+ /* Enable big core dcm */
+ plat_dcm_restore_cluster_on(mpidr);
+ /* Enable rgu dcm */
+ plat_dcm_rgu_enable();
+}
+
+static void plat_cpu_standby(plat_local_state_t cpu_state)
+{
+ unsigned int scr;
+
+ scr = read_scr_el3();
+ write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
+
+ isb();
+ dsb();
+ wfi();
+
+ write_scr_el3(scr);
+}
+
+static void mcdi_ctrl_before_hotplug_on(int cluster, int cpu)
+{
+ if (!HP_SSPM_CTRL && HP_SSPM_PAUSE && MCDI_SSPM) {
+ mcdi_pause_clr(cluster, CPU_IDX(cluster, cpu), OFF);
+ mcdi_pause_set(cluster, CPU_IDX(cluster, cpu), ON);
+ }
+}
+
+static void mcdi_ctrl_before_hotplug_off(int cluster, int cpu, bool cluster_off)
+{
+ if (!HP_SSPM_CTRL && HP_SSPM_PAUSE && MCDI_SSPM)
+ mcdi_pause_set(cluster_off ? cluster : -1,
+ CPU_IDX(cluster, cpu), OFF);
+}
+
+static void mcdi_ctrl_cluster_cpu_off(int cluster, int cpu, bool cluster_off)
+{
+ if (MCDI_SSPM) {
+ sspm_set_bootaddr(secure_entrypoint);
+
+ sspm_standbywfi_irq_enable(CPU_IDX(cluster, cpu));
+
+ if (cluster_off)
+ sspm_cluster_pwr_off_notify(cluster);
+ else
+ sspm_cluster_pwr_on_notify(cluster);
+ }
+}
+
+static void mcdi_ctrl_suspend(void)
+{
+ if (MCDI_SSPM)
+ mcdi_pause();
+}
+
+static void mcdi_ctrl_resume(void)
+{
+ if (MCDI_SSPM)
+ mcdi_unpause();
+}
+
+static void hotplug_ctrl_cluster_on(int cluster, int cpu)
+{
+ if (HP_SSPM_CTRL && MCDI_SSPM) {
+ mcdi_hotplug_clr(cluster, CPU_IDX(cluster, cpu), OFF);
+ mcdi_hotplug_set(cluster, -1, ON);
+ mcdi_hotplug_wait_ack(cluster, -1, ON);
+ } else {
+ /* power on cluster */
+ if (!spm_get_cluster_powerstate(cluster))
+ spm_poweron_cluster(cluster);
+ }
+}
+
+static void hotplug_ctrl_cpu_on(int cluster, int cpu)
+{
+ if (HP_SSPM_CTRL && MCDI_SSPM)
+ mcdi_hotplug_set(cluster, CPU_IDX(cluster, cpu), ON);
+ else
+ spm_poweron_cpu(cluster, cpu);
+}
+
+static void hotplug_ctrl_cpu_on_finish(int cluster, int cpu)
+{
+ spm_disable_cpu_auto_off(cluster, cpu);
+
+ if (HP_SSPM_CTRL && MCDI_SSPM)
+ mcdi_hotplug_clr(cluster, CPU_IDX(cluster, cpu), ON);
+ else if (HP_SSPM_PAUSE && MCDI_SSPM)
+ mcdi_pause_clr(cluster, CPU_IDX(cluster, cpu), ON);
+
+ mcdi_avail_cpu_mask_set(BIT(CPU_IDX(cluster, cpu)));
+}
+
+static void hotplug_ctrl_cluster_cpu_off(int cluster, int cpu, bool cluster_off)
+{
+ mcdi_avail_cpu_mask_clr(BIT(CPU_IDX(cluster, cpu)));
+
+ if (HP_SSPM_CTRL && MCDI_SSPM) {
+ mcdi_hotplug_set(cluster_off ? cluster : -1,
+ CPU_IDX(cluster, cpu), OFF);
+ } else {
+ spm_enable_cpu_auto_off(cluster, cpu);
+
+ if (cluster_off)
+ spm_enable_cluster_auto_off(cluster);
+
+ spm_set_cpu_power_off(cluster, cpu);
+ }
+}
+
static int plat_mtk_power_domain_on(unsigned long mpidr)
{
int cpu = MPIDR_AFFLVL0_VAL(mpidr);
int cluster = MPIDR_AFFLVL1_VAL(mpidr);
- INFO("%s():%d: mpidr: %lx, c.c: %d.%d\n",
- __func__, __LINE__, mpidr, cluster, cpu);
-
- /* power on cluster */
- if (!spm_get_cluster_powerstate(cluster)) {
- spm_poweron_cluster(cluster);
- if (cluster == 1) {
- l2c_parity_check_setup();
- circular_buffer_setup();
- mp1_L2_desel_config();
- mt_gic_sync_dcm_disable();
- }
- }
+ mcdi_ctrl_before_hotplug_on(cluster, cpu);
+ hotplug_ctrl_cluster_on(cluster, cpu);
/* init cpu reset arch as AARCH64 */
mcucfg_init_archstate(cluster, cpu, 1);
mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint);
- spm_poweron_cpu(cluster, cpu);
+ hotplug_ctrl_cpu_on(cluster, cpu);
return PSCI_E_SUCCESS;
}
@@ -73,23 +307,18 @@
uint64_t mpidr = read_mpidr();
int cpu = MPIDR_AFFLVL0_VAL(mpidr);
int cluster = MPIDR_AFFLVL1_VAL(mpidr);
+ const plat_local_state_t *pds = state->pwr_domain_state;
+ bool afflvl1 = (pds[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF);
+ bool cluster_off = (HP_CLUSTER_OFF && afflvl1 &&
+ clst_single_on(cluster, cpu));
- INFO("%s():%d: c.c: %d.%d\n", __func__, __LINE__, cluster, cpu);
-
- /* Prevent interrupts from spuriously waking up this cpu */
mt_gic_cpuif_disable();
- spm_enable_cpu_auto_off(cluster, cpu);
+ if (cluster_off)
+ plat_cluster_pwrdwn_common(mpidr, cluster);
- if (state->pwr_domain_state[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF) {
- if (cluster == 1)
- mt_gic_sync_dcm_enable();
-
- plat_mtk_cci_disable();
- spm_enable_cluster_auto_off(cluster);
- }
-
- spm_set_cpu_power_off(cluster, cpu);
+ mcdi_ctrl_before_hotplug_off(cluster, cpu, cluster_off);
+ hotplug_ctrl_cluster_cpu_off(cluster, cpu, cluster_off);
}
static void plat_mtk_power_domain_on_finish(const psci_power_state_t *state)
@@ -97,29 +326,170 @@
uint64_t mpidr = read_mpidr();
int cpu = MPIDR_AFFLVL0_VAL(mpidr);
int cluster = MPIDR_AFFLVL1_VAL(mpidr);
+ const plat_local_state_t *pds = state->pwr_domain_state;
+ bool afflvl1 = (pds[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF);
- INFO("%s():%d: c.c: %d.%d\n", __func__, __LINE__, cluster, cpu);
+ if (afflvl1)
+ plat_cluster_pwron_common(mpidr, cluster);
- assert(state->pwr_domain_state[MPIDR_AFFLVL0] == MTK_LOCAL_STATE_OFF);
-
- if (state->pwr_domain_state[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF) {
- enable_scu(mpidr);
-
- /* Enable coherency if this cluster was off */
- plat_mtk_cci_enable();
- /* Enable big core dcm if this cluster was on */
- plat_dcm_restore_cluster_on(mpidr);
- /* Enable rgu dcm if this cluster was off */
- plat_dcm_rgu_enable();
- }
-
- spm_disable_cpu_auto_off(cluster, cpu);
-
- /* Enable the gic cpu interface */
mt_gic_pcpu_init();
mt_gic_cpuif_enable();
+
+ hotplug_ctrl_cpu_on_finish(cluster, cpu);
}
+static void plat_mtk_power_domain_suspend(const psci_power_state_t *state)
+{
+ uint64_t mpidr = read_mpidr();
+ int cpu = MPIDR_AFFLVL0_VAL(mpidr);
+ int cluster = MPIDR_AFFLVL1_VAL(mpidr);
+ const plat_local_state_t *pds = state->pwr_domain_state;
+ bool afflvl1 = (pds[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF);
+ bool afflvl2 = (pds[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF);
+ bool cluster_off = MCDI_C2 && afflvl1 && clst_single_pwr(cluster, cpu);
+
+ /* init cpu reset arch as AARCH64 */
+ mcucfg_init_archstate(cluster, cpu, 1);
+ mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint);
+
+ mt_gic_cpuif_disable();
+ mt_gic_irq_save();
+ plat_dcm_mcsi_a_backup();
+
+ if (cluster_off || afflvl2)
+ plat_cluster_pwrdwn_common(mpidr, cluster);
+
+ if (afflvl2) {
+ spm_data_t spm_d = { .cmd = SPM_SUSPEND };
+ uint32_t *d = (uint32_t *)&spm_d;
+ uint32_t l = sizeof(spm_d) / sizeof(uint32_t);
+
+ mcdi_ctrl_suspend();
+
+ spm_set_bootaddr(secure_entrypoint);
+
+ if (MCDI_SSPM)
+ sspm_ipi_send_non_blocking(IPI_ID_SUSPEND, d);
+
+ spm_system_suspend();
+
+ if (MCDI_SSPM)
+ while (sspm_ipi_recv_non_blocking(IPI_ID_SUSPEND, d, l))
+ ;
+ } else {
+ mcdi_ctrl_cluster_cpu_off(cluster, cpu, cluster_off);
+ }
+}
+
+static void plat_mtk_power_domain_suspend_finish(const psci_power_state_t *state)
+{
+ uint64_t mpidr = read_mpidr();
+ int cluster = MPIDR_AFFLVL1_VAL(mpidr);
+ const plat_local_state_t *pds = state->pwr_domain_state;
+ bool afflvl2 = (pds[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF);
+
+ if (afflvl2) {
+ spm_data_t spm_d = { .cmd = SPM_RESUME };
+ uint32_t *d = (uint32_t *)&spm_d;
+ uint32_t l = sizeof(spm_d) / sizeof(uint32_t);
+
+ mt_gic_init();
+ mt_gic_irq_restore();
+ mmio_write_32(EMI_WFIFO, 0xf);
+
+ if (MCDI_SSPM)
+ sspm_ipi_send_non_blocking(IPI_ID_SUSPEND, d);
+
+ spm_system_suspend_finish();
+
+ if (MCDI_SSPM)
+ while (sspm_ipi_recv_non_blocking(IPI_ID_SUSPEND, d, l))
+ ;
+
+ mcdi_ctrl_resume();
+ }
+
+ plat_cluster_pwron_common(mpidr, cluster);
+
+ plat_dcm_mcsi_a_restore();
+}
+
+#if PSCI_EXTENDED_STATE_ID
+
+static int plat_mtk_validate_power_state(unsigned int power_state,
+ psci_power_state_t *req_state)
+{
+ unsigned int state_id;
+ int i;
+
+ assert(req_state);
+
+ if (!MCDI_SSPM)
+ return PSCI_E_INVALID_PARAMS;
+
+ /*
+ * Currently we are using a linear search for finding the matching
+ * entry in the idle power state array. This can be made a binary
+ * search if the number of entries justify the additional complexity.
+ */
+ for (i = 0; !!mtk_pm_idle_states[i]; i++) {
+ if (power_state == mtk_pm_idle_states[i])
+ break;
+ }
+
+ /* Return error if entry not found in the idle state array */
+ if (!mtk_pm_idle_states[i])
+ return PSCI_E_INVALID_PARAMS;
+
+ i = 0;
+ state_id = psci_get_pstate_id(power_state);
+
+ /* Parse the State ID and populate the state info parameter */
+ while (state_id) {
+ req_state->pwr_domain_state[i++] = state_id &
+ MTK_LOCAL_PSTATE_MASK;
+ state_id >>= MTK_LOCAL_PSTATE_WIDTH;
+ }
+
+ return PSCI_E_SUCCESS;
+}
+
+#else /* if !PSCI_EXTENDED_STATE_ID */
+
+static int plat_mtk_validate_power_state(unsigned int power_state,
+ psci_power_state_t *req_state)
+{
+ int pstate = psci_get_pstate_type(power_state);
+ int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
+ int i;
+
+ assert(req_state);
+
+ if (pwr_lvl > PLAT_MAX_PWR_LVL)
+ return PSCI_E_INVALID_PARAMS;
+
+ /* Sanity check the requested state */
+ if (pstate == PSTATE_TYPE_STANDBY) {
+ /*
+ * It's possible to enter standby only on power level 0
+ * Ignore any other power level.
+ */
+ if (pwr_lvl != 0)
+ return PSCI_E_INVALID_PARAMS;
+
+ req_state->pwr_domain_state[MTK_PWR_LVL0] = MTK_LOCAL_STATE_RET;
+ } else if (!MCDI_SSPM) {
+ return PSCI_E_INVALID_PARAMS;
+ } else {
+ for (i = 0; i <= pwr_lvl; i++)
+ req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF;
+ }
+
+ return PSCI_E_SUCCESS;
+}
+
+#endif /* PSCI_EXTENDED_STATE_ID */
+
/*******************************************************************************
* MTK handlers to shutdown/reboot the system
******************************************************************************/
@@ -149,46 +519,6 @@
panic();
}
-static void plat_mtk_power_domain_suspend(const psci_power_state_t *state)
-{
- uint64_t mpidr = read_mpidr();
- int cpu = MPIDR_AFFLVL0_VAL(mpidr);
- int cluster = MPIDR_AFFLVL1_VAL(mpidr);
-
- spm_system_suspend();
-
- /* init cpu reset arch as AARCH64 */
- mcucfg_init_archstate(cluster, cpu, 1);
- mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint);
- spm_set_bootaddr(secure_entrypoint);
-
- /* Prevent interrupts from spuriously waking up this cpu */
- mt_gic_cpuif_disable();
- mt_gic_irq_save();
-
- if (state->pwr_domain_state[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF) {
- plat_mtk_cci_disable();
- disable_scu(mpidr);
- }
-}
-
-static void plat_mtk_power_domain_suspend_finish(const psci_power_state_t *state)
-{
- uint64_t mpidr = read_mpidr();
-
- mt_gic_init();
- mt_gic_irq_restore();
-
- if (state->pwr_domain_state[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF) {
- enable_scu(mpidr);
- plat_mtk_cci_enable();
- plat_dcm_restore_cluster_on(mpidr);
- }
-
- mmio_write_32(EMI_WFIFO, 0xf);
- spm_system_suspend_finish();
-}
-
static void plat_mtk_get_sys_suspend_power_state(psci_power_state_t *req_state)
{
assert(PLAT_MAX_PWR_LVL >= 2);
@@ -202,7 +532,7 @@
* on. The level and mpidr determine the affinity instance.
******************************************************************************/
static const plat_psci_ops_t plat_plat_pm_ops = {
- .cpu_standby = NULL,
+ .cpu_standby = plat_cpu_standby,
.pwr_domain_on = plat_mtk_power_domain_on,
.pwr_domain_on_finish = plat_mtk_power_domain_on_finish,
.pwr_domain_off = plat_mtk_power_domain_off,
@@ -210,7 +540,7 @@
.pwr_domain_suspend_finish = plat_mtk_power_domain_suspend_finish,
.system_off = plat_mtk_system_off,
.system_reset = plat_mtk_system_reset,
- .validate_power_state = NULL,
+ .validate_power_state = plat_mtk_validate_power_state,
.get_sys_suspend_power_state = plat_mtk_get_sys_suspend_power_state,
};
@@ -219,5 +549,11 @@
{
*psci_ops = &plat_plat_pm_ops;
secure_entrypoint = sec_entrypoint;
+
+ if (!check_mcdi_ctl_stat()) {
+ HP_SSPM_CTRL = false;
+ MCDI_SSPM = false;
+ }
+
return 0;
}
diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk
index 5bf504b..efa7e9e 100644
--- a/plat/mediatek/mt8183/platform.mk
+++ b/plat/mediatek/mt8183/platform.mk
@@ -9,6 +9,7 @@
PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
-I${MTK_PLAT_SOC}/drivers/ \
+ -I${MTK_PLAT_SOC}/drivers/mcdi/ \
-I${MTK_PLAT_SOC}/drivers/spmc/ \
-I${MTK_PLAT_SOC}/drivers/gpio/ \
-I${MTK_PLAT_SOC}/drivers/pmic/ \
@@ -48,6 +49,7 @@
${MTK_PLAT_SOC}/drivers/mcsi/mcsi.c \
${MTK_PLAT_SOC}/drivers/pmic/pmic.c \
${MTK_PLAT_SOC}/drivers/rtc/rtc.c \
+ ${MTK_PLAT_SOC}/drivers/mcdi/mtk_mcdi.c \
${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \
${MTK_PLAT_SOC}/drivers/spm/spm.c \
${MTK_PLAT_SOC}/drivers/spm/spm_pmic_wrap.c \
