Merge "stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver" into integration
diff --git a/.editorconfig b/.editorconfig
index 928c307..b14e025 100644
--- a/.editorconfig
+++ b/.editorconfig
@@ -11,6 +11,8 @@
# [CONT] contributing.rst
# [LCS] Linux Coding Style
# (https://www.kernel.org/doc/html/v4.10/process/coding-style.html)
+# [PEP8] Style Guide for Python Code
+# (https://www.python.org/dev/peps/pep-0008)
root = true
@@ -60,3 +62,14 @@
# 180 only selected to prevent changes to existing text.
tab_width = 4
+
+# Adjustment for python which prefers a different style
+[*.py]
+# [PEP8] Indentation
+# "Use 4 spaces per indentation level."
+indent_size = 4
+indent_style = space
+
+# [PEP8] Maximum Line Length
+# "Limit all lines to a maximum of 79 characters."
+max_line_length = 79
diff --git a/.gitignore b/.gitignore
index 6b1e057..2abfffb 100644
--- a/.gitignore
+++ b/.gitignore
@@ -22,7 +22,7 @@
tools/cert_create/cert_create
tools/cert_create/cert_create.exe
tools/marvell/doimage/doimage
-tools/meson/doimage
+tools/amlogic/doimage
tools/stm32image/*.o
tools/stm32image/stm32image
tools/stm32image/stm32image.exe
diff --git a/Makefile b/Makefile
index 43ff8d2..32918c3 100644
--- a/Makefile
+++ b/Makefile
@@ -278,6 +278,14 @@
-ffreestanding -fno-builtin -Wall -std=gnu99 \
-Os -ffunction-sections -fdata-sections
+ifeq (${SANITIZE_UB},on)
+TF_CFLAGS += -fsanitize=undefined -fno-sanitize-recover
+endif
+ifeq (${SANITIZE_UB},trap)
+TF_CFLAGS += -fsanitize=undefined -fno-sanitize-recover \
+ -fsanitize-undefined-trap-on-error
+endif
+
GCC_V_OUTPUT := $(shell $(CC) -v 2>&1)
ifneq ($(findstring armlink,$(notdir $(LD))),)
@@ -313,6 +321,10 @@
BL_COMMON_SOURCES += lib/${ARCH}/armclang_printf.S
endif
+ifeq (${SANITIZE_UB},on)
+BL_COMMON_SOURCES += plat/common/ubsan.c
+endif
+
INCLUDES += -Iinclude \
-Iinclude/arch/${ARCH} \
-Iinclude/lib/cpus/${ARCH} \
@@ -510,6 +522,14 @@
$(info Branch Protection is an experimental feature)
endif
+ifeq ($(CTX_INCLUDE_MTE_REGS),1)
+ ifneq (${ARCH},aarch64)
+ $(error CTX_INCLUDE_MTE_REGS requires AArch64)
+ else
+ $(info CTX_INCLUDE_MTE_REGS is an experimental feature)
+ endif
+endif
+
################################################################################
# Process platform overrideable behaviour
################################################################################
@@ -631,6 +651,7 @@
$(eval $(call assert_boolean,CTX_INCLUDE_AARCH32_REGS))
$(eval $(call assert_boolean,CTX_INCLUDE_FPREGS))
$(eval $(call assert_boolean,CTX_INCLUDE_PAUTH_REGS))
+$(eval $(call assert_boolean,CTX_INCLUDE_MTE_REGS))
$(eval $(call assert_boolean,DEBUG))
$(eval $(call assert_boolean,DYN_DISABLE_AUTH))
$(eval $(call assert_boolean,EL3_EXCEPTION_HANDLING))
@@ -668,11 +689,20 @@
$(eval $(call assert_boolean,WARMBOOT_ENABLE_DCACHE_EARLY))
$(eval $(call assert_boolean,BL2_AT_EL3))
$(eval $(call assert_boolean,BL2_IN_XIP_MEM))
+$(eval $(call assert_boolean,BL2_INV_DCACHE))
$(eval $(call assert_numeric,ARM_ARCH_MAJOR))
$(eval $(call assert_numeric,ARM_ARCH_MINOR))
$(eval $(call assert_numeric,BRANCH_PROTECTION))
+ifdef KEY_SIZE
+ $(eval $(call assert_numeric,KEY_SIZE))
+endif
+
+ifeq ($(filter $(SANITIZE_UB), on off trap),)
+ $(error "Invalid value for SANITIZE_UB: can be one of on, off, trap")
+endif
+
################################################################################
# Add definitions to the cpp preprocessor based on the current build options.
# This is done after including the platform specific makefile to allow the
@@ -686,6 +716,7 @@
$(eval $(call add_define,CTX_INCLUDE_FPREGS))
$(eval $(call add_define,CTX_INCLUDE_PAUTH_REGS))
$(eval $(call add_define,EL3_EXCEPTION_HANDLING))
+$(eval $(call add_define,CTX_INCLUDE_MTE_REGS))
$(eval $(call add_define,ENABLE_AMU))
$(eval $(call add_define,ENABLE_ASSERTIONS))
$(eval $(call add_define,ENABLE_BTI))
@@ -723,6 +754,11 @@
$(eval $(call add_define,WARMBOOT_ENABLE_DCACHE_EARLY))
$(eval $(call add_define,BL2_AT_EL3))
$(eval $(call add_define,BL2_IN_XIP_MEM))
+$(eval $(call add_define,BL2_INV_DCACHE))
+
+ifeq (${SANITIZE_UB},trap)
+ $(eval $(call add_define,MONITOR_TRAPS))
+endif
# Define the EL3_PAYLOAD_BASE flag only if it is provided.
ifdef EL3_PAYLOAD_BASE
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index fd7656e2..1cbec8f 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -220,6 +220,19 @@
* ---------------------------------------------------------------------
*/
vector_entry sync_exception_sp_el0
+#ifdef MONITOR_TRAPS
+ stp x29, x30, [sp, #-16]!
+
+ mrs x30, esr_el3
+ ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
+
+ /* Check for BRK */
+ cmp x30, #EC_BRK
+ b.eq brk_handler
+
+ ldp x29, x30, [sp], #16
+#endif /* MONITOR_TRAPS */
+
/* We don't expect any synchronous exceptions from EL3 */
b report_unhandled_exception
end_vector_entry sync_exception_sp_el0
@@ -328,6 +341,14 @@
b enter_lower_el_async_ea
end_vector_entry serror_aarch32
+#ifdef MONITOR_TRAPS
+ .section .rodata.brk_string, "aS"
+brk_location:
+ .asciz "Error at instruction 0x"
+brk_message:
+ .asciz "Unexpected BRK instruction with value 0x"
+#endif /* MONITOR_TRAPS */
+
/* ---------------------------------------------------------------------
* The following code handles secure monitor calls.
* Depending upon the execution state from where the SMC has been
@@ -455,3 +476,39 @@
msr spsel, #1
no_ret report_unhandled_exception
endfunc smc_handler
+
+ /* ---------------------------------------------------------------------
+ * The following code handles exceptions caused by BRK instructions.
+ * Following a BRK instruction, the only real valid cause of action is
+ * to print some information and panic, as the code that caused it is
+ * likely in an inconsistent internal state.
+ *
+ * This is initially intended to be used in conjunction with
+ * __builtin_trap.
+ * ---------------------------------------------------------------------
+ */
+#ifdef MONITOR_TRAPS
+func brk_handler
+ /* Extract the ISS */
+ mrs x10, esr_el3
+ ubfx x10, x10, #ESR_ISS_SHIFT, #ESR_ISS_LENGTH
+
+ /* Ensure the console is initialized */
+ bl plat_crash_console_init
+
+ adr x4, brk_location
+ bl asm_print_str
+ mrs x4, elr_el3
+ bl asm_print_hex
+ bl asm_print_newline
+
+ adr x4, brk_message
+ bl asm_print_str
+ mov x4, x10
+ mov x5, #28
+ bl asm_print_hex_bits
+ bl asm_print_newline
+
+ no_ret plat_panic_handler
+endfunc brk_handler
+#endif /* MONITOR_TRAPS */
diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c
index 30bf6ff..0a81735 100644
--- a/bl32/tsp/tsp_main.c
+++ b/bl32/tsp/tsp_main.c
@@ -386,6 +386,14 @@
*/
tsp_get_magic(service_args);
+#if CTX_INCLUDE_MTE_REGS
+ /*
+ * Write a dummy value to an MTE register, to simulate usage in the
+ * secure world
+ */
+ write_gcr_el1(0x99);
+#endif
+
/* Determine the function to perform based on the function ID */
switch (TSP_BARE_FID(func)) {
case TSP_ADD:
diff --git a/docs/design/auth-framework.rst b/docs/design/auth-framework.rst
index da958b7..7de8ee1 100644
--- a/docs/design/auth-framework.rst
+++ b/docs/design/auth-framework.rst
@@ -704,7 +704,7 @@
In the ``tbbr_cot.c`` file, a set of buffers are allocated to store the parameters
extracted from the certificates. In the case of the TBBR CoT, these parameters
-are hashes and public keys. In DER format, an RSA-2048 public key requires 294
+are hashes and public keys. In DER format, an RSA-4096 public key requires 550
bytes, and a hash requires 51 bytes. Depending on the CoT and the authentication
process, some of the buffers may be reused at different stages during the boot.
@@ -946,12 +946,16 @@
int verify_hash(void *data_ptr, unsigned int data_len,
void *digest_info_ptr, unsigned int digest_info_len);
-The mbedTLS library algorithm support is configured by the
-``TF_MBEDTLS_KEY_ALG`` variable which can take in 3 values: `rsa`, `ecdsa` or
-`rsa+ecdsa`. This variable allows the Makefile to include the corresponding
-sources in the build for the various algorithms. Setting the variable to
-`rsa+ecdsa` enables support for both rsa and ecdsa algorithms in the mbedTLS
-library.
+The mbedTLS library algorithm support is configured by both the
+``TF_MBEDTLS_KEY_ALG`` and ``TF_MBEDTLS_KEY_SIZE`` variables.
+
+- ``TF_MBEDTLS_KEY_ALG`` can take in 3 values: `rsa`, `ecdsa` or `rsa+ecdsa`.
+ This variable allows the Makefile to include the corresponding sources in
+ the build for the various algorithms. Setting the variable to `rsa+ecdsa`
+ enables support for both rsa and ecdsa algorithms in the mbedTLS library.
+
+- ``TF_MBEDTLS_KEY_SIZE`` sets the supported RSA key size for TFA. Valid values
+ include 1024, 2048, 3072 and 4096.
.. note::
If code size is a concern, the build option ``MBEDTLS_SHA256_SMALLER`` can
diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst
index 00e199a..dc08208 100644
--- a/docs/design/firmware-design.rst
+++ b/docs/design/firmware-design.rst
@@ -2581,7 +2581,16 @@
~~~~~~~~~
- Branch Target Identification feature is selected by ``BRANCH_PROTECTION``
- option set to 1. This option defaults to 0 and this is an experimental feature.
+ option set to 1. This option defaults to 0 and this is an experimental
+ feature.
+
+- Memory Tagging Extension feature is unconditionally enabled for both worlds
+ (at EL0 and S-EL0) if it is only supported at EL0. If instead it is
+ implemented at all ELs, it is unconditionally enabled for only the normal
+ world. To enable it for the secure world as well, the build option
+ ``CTX_INCLUDE_MTE_REGS`` is required. If the hardware does not implement
+ MTE support at all, it is always disabled, no matter what build options
+ are used.
Armv7-A
~~~~~~~
diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst
index b447f14..015de9a 100644
--- a/docs/getting_started/user-guide.rst
+++ b/docs/getting_started/user-guide.rst
@@ -287,6 +287,12 @@
enable this use-case. For now, this option is only supported when BL2_AT_EL3
is set to '1'.
+- ``BL2_INV_DCACHE``: This is an optional build option which control dcache
+ invalidation upon BL2 entry. Some platform cannot handle cache operations
+ during entry as the coherency unit is not yet initialized. This may cause
+ crashing. Leaving this option to '1' (default) will allow the operation.
+ This option is only relevant when BL2_AT_EL3 is set to '1'.
+
- ``BL31``: This is an optional build option which specifies the path to
BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
be built.
@@ -383,6 +389,13 @@
registers to be included when saving and restoring the CPU context. Default
is 0.
+- ``CTX_INCLUDE_MTE_REGS``: Enables register saving/reloading support for
+ ARMv8.5 Memory Tagging Extension. A value of 0 will disable
+ saving/reloading and restrict the use of MTE to the normal world if the
+ CPU has support, while a value of 1 enables the saving/reloading, allowing
+ the use of MTE in both the secure and non-secure worlds. Default is 0
+ (disabled) and this feature is experimental.
+
- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables
Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth
registers to be included when saving and restoring the CPU context as
@@ -581,10 +594,20 @@
- ``KEY_ALG``: This build flag enables the user to select the algorithm to be
used for generating the PKCS keys and subsequent signing of the certificate.
- It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option
- ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR
- compliant and is retained only for compatibility. The default value of this
- flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
+ It accepts 2 values: ``rsa`` and ``ecdsa``. The default value of this flag
+ is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
+
+- ``KEY_SIZE``: This build flag enables the user to select the key size for
+ the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE``
+ depend on the chosen algorithm.
+
+ +-----------+------------------------------------+
+ | KEY_ALG | Possible key sizes |
+ +===========+====================================+
+ | rsa | 1024, 2048 (default), 3072, 4096 |
+ +-----------+------------------------------------+
+ | ecdsa | unavailable |
+ +-----------+------------------------------------+
- ``HASH_ALG``: This build flag enables the user to select the secure hash
algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``.
@@ -684,6 +707,21 @@
file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
file name will be used to save the key.
+- ``SANITIZE_UB``: This option enables the Undefined Behaviour sanitizer. It
+ can take 3 values: 'off' (default), 'on' and 'trap'. When using 'trap',
+ gcc and clang will insert calls to ``__builtin_trap`` on detected
+ undefined behaviour, which defaults to a ``brk`` instruction. When using
+ 'on', undefined behaviour is translated to a call to special handlers which
+ prints the exact location of the problem and its cause and then panics.
+
+ .. note::
+ Because of the space penalty of the Undefined Behaviour sanitizer,
+ this option will increase the size of the binary. Depending on the
+ memory constraints of the target platform, it may not be possible to
+ enable the sanitizer for all images (BL1 and BL2 are especially
+ likely to be memory constrained). We recommend that the
+ sanitizer is enabled only in debug builds.
+
- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
certificate generation tool to save the keys used to establish the Chain of
Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
@@ -798,6 +836,7 @@
cluster platforms). If this option is enabled, then warm boot path
enables D-caches immediately after enabling MMU. This option defaults to 0.
+
Arm development platform specific build options
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -1154,7 +1193,7 @@
is important to use a version that is compatible with TF-A and fixes any
known security vulnerabilities. See `mbed TLS Security Center`_ for more
information. The latest version of TF-A is tested with tag
- ``mbedtls-2.16.0``.
+ ``mbedtls-2.16.2``.
The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
source files the modules depend upon.
diff --git a/docs/maintainers.rst b/docs/maintainers.rst
index cbfc652..7731c72 100644
--- a/docs/maintainers.rst
+++ b/docs/maintainers.rst
@@ -37,16 +37,16 @@
:M: Andre Przywara <andre.przywara@arm.com>
:G: `Andre-ARM`_
:F: docs/plat/meson-gxbb.rst
-:F: drivers/meson/
-:F: plat/meson/gxbb/
+:F: drivers/amlogic/
+:F: plat/amlogic/gxbb/
Amlogic Meson S905x (GXL) platform port
---------------------------------------
:M: Remi Pommarel <repk@triplefau.lt>
:G: `remi-triplefault`_
:F: docs/plat/meson-gxl.rst
-:F: drivers/meson/gxl
-:F: plat/meson/gxl/
+:F: drivers/amlogic/gxl
+:F: plat/amlogic/gxl/
Armv7-A architecture port
-------------------------
diff --git a/drivers/meson/console/aarch64/meson_console.S b/drivers/amlogic/console/aarch64/meson_console.S
similarity index 98%
rename from drivers/meson/console/aarch64/meson_console.S
rename to drivers/amlogic/console/aarch64/meson_console.S
index 22d0773..e645cba 100644
--- a/drivers/meson/console/aarch64/meson_console.S
+++ b/drivers/amlogic/console/aarch64/meson_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,7 +7,7 @@
#include <asm_macros.S>
#include <assert_macros.S>
#include <console_macros.S>
-#include <drivers/meson/meson_console.h>
+#include <drivers/amlogic/meson_console.h>
.globl console_meson_register
.globl console_meson_init
diff --git a/drivers/meson/gxl/crypto/sha_dma.c b/drivers/amlogic/crypto/sha_dma.c
similarity index 99%
rename from drivers/meson/gxl/crypto/sha_dma.c
rename to drivers/amlogic/crypto/sha_dma.c
index a969dea..d48ded9 100644
--- a/drivers/meson/gxl/crypto/sha_dma.c
+++ b/drivers/amlogic/crypto/sha_dma.c
@@ -4,10 +4,10 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <assert.h>
#include <arch_helpers.h>
-#include <lib/mmio.h>
+#include <assert.h>
#include <crypto/sha_dma.h>
+#include <lib/mmio.h>
#define AML_SHA_DMA_BASE 0xc883e000
diff --git a/drivers/auth/mbedtls/mbedtls_common.mk b/drivers/auth/mbedtls/mbedtls_common.mk
index 63e65bd..4b83015 100644
--- a/drivers/auth/mbedtls/mbedtls_common.mk
+++ b/drivers/auth/mbedtls/mbedtls_common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -48,9 +48,9 @@
)
# The platform may define the variable 'TF_MBEDTLS_KEY_ALG' to select the key
-# algorithm to use. If the variable is not defined, select it based on algorithm
-# used for key generation `KEY_ALG`. If `KEY_ALG` is not defined or is
-# defined to `rsa`/`rsa_1_5`, then set the variable to `rsa`.
+# algorithm to use. If the variable is not defined, select it based on
+# algorithm used for key generation `KEY_ALG`. If `KEY_ALG` is not defined,
+# then it is set to `rsa`.
ifeq (${TF_MBEDTLS_KEY_ALG},)
ifeq (${KEY_ALG}, ecdsa)
TF_MBEDTLS_KEY_ALG := ecdsa
@@ -59,6 +59,16 @@
endif
endif
+ifeq (${TF_MBEDTLS_KEY_SIZE},)
+ ifneq ($(findstring rsa,${TF_MBEDTLS_KEY_ALG}),)
+ ifeq (${KEY_SIZE},)
+ TF_MBEDTLS_KEY_SIZE := 2048
+ else
+ TF_MBEDTLS_KEY_SIZE := ${KEY_SIZE}
+ endif
+ endif
+endif
+
ifeq (${HASH_ALG}, sha384)
TF_MBEDTLS_HASH_ALG_ID := TF_MBEDTLS_SHA384
else ifeq (${HASH_ALG}, sha512)
@@ -79,6 +89,7 @@
# Needs to be set to drive mbed TLS configuration correctly
$(eval $(call add_define,TF_MBEDTLS_KEY_ALG_ID))
+$(eval $(call add_define,TF_MBEDTLS_KEY_SIZE))
$(eval $(call add_define,TF_MBEDTLS_HASH_ALG_ID))
diff --git a/drivers/auth/tbbr/tbbr_cot.c b/drivers/auth/tbbr/tbbr_cot.c
index da3631b..6dd4ae2 100644
--- a/drivers/auth/tbbr/tbbr_cot.c
+++ b/drivers/auth/tbbr/tbbr_cot.c
@@ -7,6 +7,7 @@
#include <stddef.h>
#include <platform_def.h>
+#include <drivers/auth/mbedtls/mbedtls_config.h>
#include <drivers/auth/auth_mod.h>
#if USE_TBBR_DEFS
@@ -19,7 +20,22 @@
/*
* Maximum key and hash sizes (in DER format)
*/
+#if TF_MBEDTLS_USE_RSA
+#if TF_MBEDTLS_KEY_SIZE == 1024
+#define PK_DER_LEN 162
+#elif TF_MBEDTLS_KEY_SIZE == 2048
#define PK_DER_LEN 294
+#elif TF_MBEDTLS_KEY_SIZE == 3072
+#define PK_DER_LEN 422
+#elif TF_MBEDTLS_KEY_SIZE == 4096
+#define PK_DER_LEN 550
+#else
+#error "Invalid value for TF_MBEDTLS_KEY_SIZE"
+#endif
+#else
+#define PK_DER_LEN 294
+#endif
+
#define HASH_DER_LEN 83
/*
diff --git a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
index e300fd5..43d21d7 100644
--- a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
+++ b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
@@ -12,7 +12,7 @@
#include "../qos_reg.h"
#include "qos_init_m3_v30.h"
-#define RCAR_QOS_VERSION "rev.0.03"
+#define RCAR_QOS_VERSION "rev.0.04"
#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
diff --git a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h
index cd820e8..2ab14da 100644
--- a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h
+++ b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h
@@ -32,8 +32,8 @@
/* 0x00c0, */ 0x000C04020000FFFFUL,
/* 0x00c8, */ 0x000C04010000FFFFUL,
/* 0x00d0, */ 0x000C04010000FFFFUL,
- /* 0x00d8, */ 0x000C100D0000FFFFUL,
- /* 0x00e0, */ 0x000C1C1B0000FFFFUL,
+ /* 0x00d8, */ 0x000C08050000FFFFUL,
+ /* 0x00e0, */ 0x000C10100000FFFFUL,
/* 0x00e8, */ 0x0000000000000000UL,
/* 0x00f0, */ 0x001024090000FFFFUL,
/* 0x00f8, */ 0x0000000000000000UL,
@@ -41,7 +41,7 @@
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x00100C090000FFFFUL,
/* 0x0118, */ 0x0000000000000000UL,
- /* 0x0120, */ 0x000C1C1B0000FFFFUL,
+ /* 0x0120, */ 0x000C10100000FFFFUL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,
/* 0x0138, */ 0x00100C0B0000FFFFUL,
diff --git a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h
index e9037e1..faac3d9 100644
--- a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h
+++ b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h
@@ -32,8 +32,8 @@
/* 0x00c0, */ 0x000C08040000FFFFUL,
/* 0x00c8, */ 0x000C04020000FFFFUL,
/* 0x00d0, */ 0x000C04020000FFFFUL,
- /* 0x00d8, */ 0x000C1C1A0000FFFFUL,
- /* 0x00e0, */ 0x000C38360000FFFFUL,
+ /* 0x00d8, */ 0x000C0C0A0000FFFFUL,
+ /* 0x00e0, */ 0x000C201F0000FFFFUL,
/* 0x00e8, */ 0x0000000000000000UL,
/* 0x00f0, */ 0x001044110000FFFFUL,
/* 0x00f8, */ 0x0000000000000000UL,
@@ -41,7 +41,7 @@
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x001014110000FFFFUL,
/* 0x0118, */ 0x0000000000000000UL,
- /* 0x0120, */ 0x000C38360000FFFFUL,
+ /* 0x0120, */ 0x000C201F0000FFFFUL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,
/* 0x0138, */ 0x001018150000FFFFUL,
diff --git a/drivers/staging/renesas/rcar/ddr/boot_init_dram.h b/drivers/staging/renesas/rcar/ddr/boot_init_dram.h
index 4b0a9eb..ac237b2 100644
--- a/drivers/staging/renesas/rcar/ddr/boot_init_dram.h
+++ b/drivers/staging/renesas/rcar/ddr/boot_init_dram.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,10 +9,10 @@
extern int32_t rcar_dram_init(void);
-#define INITDRAM_OK (0)
-#define INITDRAM_NG (0xffffffff)
-#define INITDRAM_ERR_I (0xffffffff)
-#define INITDRAM_ERR_O (0xfffffffe)
-#define INITDRAM_ERR_T (0xfffffff0)
+#define INITDRAM_OK 0
+#define INITDRAM_NG 0xffffffff
+#define INITDRAM_ERR_I 0xffffffff
+#define INITDRAM_ERR_O 0xfffffffe
+#define INITDRAM_ERR_T 0xfffffff0
#endif /* BOOT_INIT_DRAM_H */
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h
index 397bde0..0f89b43 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h
@@ -5,287 +5,4 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef BOOT_INIT_DRAM_REGDEF_H_
-#define BOOT_INIT_DRAM_REGDEF_H_
-
-/* DBSC registers */
-#define DBSC_DBSYSCONF0 0xE6790000U
-#define DBSC_DBSYSCONF1 0xE6790004U
-#define DBSC_DBPHYCONF0 0xE6790010U
-#define DBSC_DBKIND 0xE6790020U
-#define DBSC_DBMEMCONF00 0xE6790030U
-#define DBSC_DBMEMCONF01 0xE6790034U
-#define DBSC_DBMEMCONF02 0xE6790038U
-#define DBSC_DBMEMCONF03 0xE679003CU
-#define DBSC_DBMEMCONF10 0xE6790040U
-#define DBSC_DBMEMCONF11 0xE6790044U
-#define DBSC_DBMEMCONF12 0xE6790048U
-#define DBSC_DBMEMCONF13 0xE679004CU
-#define DBSC_DBMEMCONF20 0xE6790050U
-#define DBSC_DBMEMCONF21 0xE6790054U
-#define DBSC_DBMEMCONF22 0xE6790058U
-#define DBSC_DBMEMCONF23 0xE679005CU
-#define DBSC_DBMEMCONF30 0xE6790060U
-#define DBSC_DBMEMCONF31 0xE6790064U
-#define DBSC_DBMEMCONF32 0xE6790068U
-#define DBSC_DBMEMCONF33 0xE679006CU
-#define DBSC_DBSYSCNT0 0xE6790100U
-#define DBSC_DBSVCR1 0xE6790104U
-#define DBSC_DBSTATE0 0xE6790108U
-#define DBSC_DBSTATE1 0xE679010CU
-#define DBSC_DBINTEN 0xE6790180U
-#define DBSC_DBINTSTAT0 0xE6790184U
-#define DBSC_DBACEN 0xE6790200U
-#define DBSC_DBRFEN 0xE6790204U
-#define DBSC_DBCMD 0xE6790208U
-#define DBSC_DBWAIT 0xE6790210U
-#define DBSC_DBSYSCTRL0 0xE6790280U
-#define DBSC_DBTR0 0xE6790300U
-#define DBSC_DBTR1 0xE6790304U
-#define DBSC_DBTR2 0xE6790308U
-#define DBSC_DBTR3 0xE679030CU
-#define DBSC_DBTR4 0xE6790310U
-#define DBSC_DBTR5 0xE6790314U
-#define DBSC_DBTR6 0xE6790318U
-#define DBSC_DBTR7 0xE679031CU
-#define DBSC_DBTR8 0xE6790320U
-#define DBSC_DBTR9 0xE6790324U
-#define DBSC_DBTR10 0xE6790328U
-#define DBSC_DBTR11 0xE679032CU
-#define DBSC_DBTR12 0xE6790330U
-#define DBSC_DBTR13 0xE6790334U
-#define DBSC_DBTR14 0xE6790338U
-#define DBSC_DBTR15 0xE679033CU
-#define DBSC_DBTR16 0xE6790340U
-#define DBSC_DBTR17 0xE6790344U
-#define DBSC_DBTR18 0xE6790348U
-#define DBSC_DBTR19 0xE679034CU
-#define DBSC_DBTR20 0xE6790350U
-#define DBSC_DBTR21 0xE6790354U
-#define DBSC_DBTR22 0xE6790358U
-#define DBSC_DBTR23 0xE679035CU
-#define DBSC_DBTR24 0xE6790360U
-#define DBSC_DBTR25 0xE6790364U
-#define DBSC_DBBL 0xE6790400U
-#define DBSC_DBRFCNF1 0xE6790414U
-#define DBSC_DBRFCNF2 0xE6790418U
-#define DBSC_DBTSPCNF 0xE6790420U
-#define DBSC_DBCALCNF 0xE6790424U
-#define DBSC_DBRNK2 0xE6790438U
-#define DBSC_DBRNK3 0xE679043CU
-#define DBSC_DBRNK4 0xE6790440U
-#define DBSC_DBRNK5 0xE6790444U
-#define DBSC_DBPDNCNF 0xE6790450U
-#define DBSC_DBODT0 0xE6790460U
-#define DBSC_DBODT1 0xE6790464U
-#define DBSC_DBODT2 0xE6790468U
-#define DBSC_DBODT3 0xE679046CU
-#define DBSC_DBODT4 0xE6790470U
-#define DBSC_DBODT5 0xE6790474U
-#define DBSC_DBODT6 0xE6790478U
-#define DBSC_DBODT7 0xE679047CU
-#define DBSC_DBADJ0 0xE6790500U
-#define DBSC_DBDBICNT 0xE6790518U
-#define DBSC_DBDFIPMSTRCNF 0xE6790520U
-#define DBSC_DBDFIPMSTRSTAT 0xE6790524U
-#define DBSC_DBDFILPCNF 0xE6790528U
-#define DBSC_DBDFICUPDCNF 0xE679052CU
-#define DBSC_DBDFISTAT0 0xE6790600U
-#define DBSC_DBDFICNT0 0xE6790604U
-#define DBSC_DBPDCNT00 0xE6790610U
-#define DBSC_DBPDCNT01 0xE6790614U
-#define DBSC_DBPDCNT02 0xE6790618U
-#define DBSC_DBPDCNT03 0xE679061CU
-#define DBSC_DBPDLK0 0xE6790620U
-#define DBSC_DBPDRGA0 0xE6790624U
-#define DBSC_DBPDRGD0 0xE6790628U
-#define DBSC_DBPDSTAT00 0xE6790630U
-#define DBSC_DBDFISTAT1 0xE6790640U
-#define DBSC_DBDFICNT1 0xE6790644U
-#define DBSC_DBPDCNT10 0xE6790650U
-#define DBSC_DBPDCNT11 0xE6790654U
-#define DBSC_DBPDCNT12 0xE6790658U
-#define DBSC_DBPDCNT13 0xE679065CU
-#define DBSC_DBPDLK1 0xE6790660U
-#define DBSC_DBPDRGA1 0xE6790664U
-#define DBSC_DBPDRGD1 0xE6790668U
-#define DBSC_DBPDSTAT10 0xE6790670U
-#define DBSC_DBDFISTAT2 0xE6790680U
-#define DBSC_DBDFICNT2 0xE6790684U
-#define DBSC_DBPDCNT20 0xE6790690U
-#define DBSC_DBPDCNT21 0xE6790694U
-#define DBSC_DBPDCNT22 0xE6790698U
-#define DBSC_DBPDCNT23 0xE679069CU
-#define DBSC_DBPDLK2 0xE67906A0U
-#define DBSC_DBPDRGA2 0xE67906A4U
-#define DBSC_DBPDRGD2 0xE67906A8U
-#define DBSC_DBPDSTAT20 0xE67906B0U
-#define DBSC_DBDFISTAT3 0xE67906C0U
-#define DBSC_DBDFICNT3 0xE67906C4U
-#define DBSC_DBPDCNT30 0xE67906D0U
-#define DBSC_DBPDCNT31 0xE67906D4U
-#define DBSC_DBPDCNT32 0xE67906D8U
-#define DBSC_DBPDCNT33 0xE67906DCU
-#define DBSC_DBPDLK3 0xE67906E0U
-#define DBSC_DBPDRGA3 0xE67906E4U
-#define DBSC_DBPDRGD3 0xE67906E8U
-#define DBSC_DBPDSTAT30 0xE67906F0U
-#define DBSC_DBBUS0CNF0 0xE6790800U
-#define DBSC_DBBUS0CNF1 0xE6790804U
-#define DBSC_DBCAM0CNF1 0xE6790904U
-#define DBSC_DBCAM0CNF2 0xE6790908U
-#define DBSC_DBCAM0CNF3 0xE679090CU
-#define DBSC_DBCAM0CTRL0 0xE6790940U
-#define DBSC_DBCAM0STAT0 0xE6790980U
-#define DBSC_DBCAM1STAT0 0xE6790990U
-#define DBSC_DBBCAMSWAP 0xE67909F0U
-#define DBSC_DBBCAMDIS 0xE67909FCU
-#define DBSC_DBSCHCNT0 0xE6791000U
-#define DBSC_DBSCHCNT1 0xE6791004U
-#define DBSC_DBSCHSZ0 0xE6791010U
-#define DBSC_DBSCHRW0 0xE6791020U
-#define DBSC_DBSCHRW1 0xE6791024U
-#define DBSC_DBSCHQOS00 0xE6791030U
-#define DBSC_DBSCHQOS01 0xE6791034U
-#define DBSC_DBSCHQOS02 0xE6791038U
-#define DBSC_DBSCHQOS03 0xE679103CU
-#define DBSC_DBSCHQOS10 0xE6791040U
-#define DBSC_DBSCHQOS11 0xE6791044U
-#define DBSC_DBSCHQOS12 0xE6791048U
-#define DBSC_DBSCHQOS13 0xE679104CU
-#define DBSC_DBSCHQOS20 0xE6791050U
-#define DBSC_DBSCHQOS21 0xE6791054U
-#define DBSC_DBSCHQOS22 0xE6791058U
-#define DBSC_DBSCHQOS23 0xE679105CU
-#define DBSC_DBSCHQOS30 0xE6791060U
-#define DBSC_DBSCHQOS31 0xE6791064U
-#define DBSC_DBSCHQOS32 0xE6791068U
-#define DBSC_DBSCHQOS33 0xE679106CU
-#define DBSC_DBSCHQOS40 0xE6791070U
-#define DBSC_DBSCHQOS41 0xE6791074U
-#define DBSC_DBSCHQOS42 0xE6791078U
-#define DBSC_DBSCHQOS43 0xE679107CU
-#define DBSC_DBSCHQOS50 0xE6791080U
-#define DBSC_DBSCHQOS51 0xE6791084U
-#define DBSC_DBSCHQOS52 0xE6791088U
-#define DBSC_DBSCHQOS53 0xE679108CU
-#define DBSC_DBSCHQOS60 0xE6791090U
-#define DBSC_DBSCHQOS61 0xE6791094U
-#define DBSC_DBSCHQOS62 0xE6791098U
-#define DBSC_DBSCHQOS63 0xE679109CU
-#define DBSC_DBSCHQOS70 0xE67910A0U
-#define DBSC_DBSCHQOS71 0xE67910A4U
-#define DBSC_DBSCHQOS72 0xE67910A8U
-#define DBSC_DBSCHQOS73 0xE67910ACU
-#define DBSC_DBSCHQOS80 0xE67910B0U
-#define DBSC_DBSCHQOS81 0xE67910B4U
-#define DBSC_DBSCHQOS82 0xE67910B8U
-#define DBSC_DBSCHQOS83 0xE67910BCU
-#define DBSC_DBSCHQOS90 0xE67910C0U
-#define DBSC_DBSCHQOS91 0xE67910C4U
-#define DBSC_DBSCHQOS92 0xE67910C8U
-#define DBSC_DBSCHQOS93 0xE67910CCU
-#define DBSC_DBSCHQOS100 0xE67910D0U
-#define DBSC_DBSCHQOS101 0xE67910D4U
-#define DBSC_DBSCHQOS102 0xE67910D8U
-#define DBSC_DBSCHQOS103 0xE67910DCU
-#define DBSC_DBSCHQOS110 0xE67910E0U
-#define DBSC_DBSCHQOS111 0xE67910E4U
-#define DBSC_DBSCHQOS112 0xE67910E8U
-#define DBSC_DBSCHQOS113 0xE67910ECU
-#define DBSC_DBSCHQOS120 0xE67910F0U
-#define DBSC_DBSCHQOS121 0xE67910F4U
-#define DBSC_DBSCHQOS122 0xE67910F8U
-#define DBSC_DBSCHQOS123 0xE67910FCU
-#define DBSC_DBSCHQOS130 0xE6791100U
-#define DBSC_DBSCHQOS131 0xE6791104U
-#define DBSC_DBSCHQOS132 0xE6791108U
-#define DBSC_DBSCHQOS133 0xE679110CU
-#define DBSC_DBSCHQOS140 0xE6791110U
-#define DBSC_DBSCHQOS141 0xE6791114U
-#define DBSC_DBSCHQOS142 0xE6791118U
-#define DBSC_DBSCHQOS143 0xE679111CU
-#define DBSC_DBSCHQOS150 0xE6791120U
-#define DBSC_DBSCHQOS151 0xE6791124U
-#define DBSC_DBSCHQOS152 0xE6791128U
-#define DBSC_DBSCHQOS153 0xE679112CU
-#define DBSC_SCFCTST0 0xE6791700U
-#define DBSC_SCFCTST1 0xE6791708U
-#define DBSC_SCFCTST2 0xE679170CU
-#define DBSC_DBMRRDR0 0xE6791800U
-#define DBSC_DBMRRDR1 0xE6791804U
-#define DBSC_DBMRRDR2 0xE6791808U
-#define DBSC_DBMRRDR3 0xE679180CU
-#define DBSC_DBMRRDR4 0xE6791810U
-#define DBSC_DBMRRDR5 0xE6791814U
-#define DBSC_DBMRRDR6 0xE6791818U
-#define DBSC_DBMRRDR7 0xE679181CU
-#define DBSC_DBDTMP0 0xE6791820U
-#define DBSC_DBDTMP1 0xE6791824U
-#define DBSC_DBDTMP2 0xE6791828U
-#define DBSC_DBDTMP3 0xE679182CU
-#define DBSC_DBDTMP4 0xE6791830U
-#define DBSC_DBDTMP5 0xE6791834U
-#define DBSC_DBDTMP6 0xE6791838U
-#define DBSC_DBDTMP7 0xE679183CU
-#define DBSC_DBDQSOSC00 0xE6791840U
-#define DBSC_DBDQSOSC01 0xE6791844U
-#define DBSC_DBDQSOSC10 0xE6791848U
-#define DBSC_DBDQSOSC11 0xE679184CU
-#define DBSC_DBDQSOSC20 0xE6791850U
-#define DBSC_DBDQSOSC21 0xE6791854U
-#define DBSC_DBDQSOSC30 0xE6791858U
-#define DBSC_DBDQSOSC31 0xE679185CU
-#define DBSC_DBDQSOSC40 0xE6791860U
-#define DBSC_DBDQSOSC41 0xE6791864U
-#define DBSC_DBDQSOSC50 0xE6791868U
-#define DBSC_DBDQSOSC51 0xE679186CU
-#define DBSC_DBDQSOSC60 0xE6791870U
-#define DBSC_DBDQSOSC61 0xE6791874U
-#define DBSC_DBDQSOSC70 0xE6791878U
-#define DBSC_DBDQSOSC71 0xE679187CU
-#define DBSC_DBOSCTHH00 0xE6791880U
-#define DBSC_DBOSCTHH01 0xE6791884U
-#define DBSC_DBOSCTHH10 0xE6791888U
-#define DBSC_DBOSCTHH11 0xE679188CU
-#define DBSC_DBOSCTHH20 0xE6791890U
-#define DBSC_DBOSCTHH21 0xE6791894U
-#define DBSC_DBOSCTHH30 0xE6791898U
-#define DBSC_DBOSCTHH31 0xE679189CU
-#define DBSC_DBOSCTHH40 0xE67918A0U
-#define DBSC_DBOSCTHH41 0xE67918A4U
-#define DBSC_DBOSCTHH50 0xE67918A8U
-#define DBSC_DBOSCTHH51 0xE67918ACU
-#define DBSC_DBOSCTHH60 0xE67918B0U
-#define DBSC_DBOSCTHH61 0xE67918B4U
-#define DBSC_DBOSCTHH70 0xE67918B8U
-#define DBSC_DBOSCTHH71 0xE67918BCU
-#define DBSC_DBOSCTHL00 0xE67918C0U
-#define DBSC_DBOSCTHL01 0xE67918C4U
-#define DBSC_DBOSCTHL10 0xE67918C8U
-#define DBSC_DBOSCTHL11 0xE67918CCU
-#define DBSC_DBOSCTHL20 0xE67918D0U
-#define DBSC_DBOSCTHL21 0xE67918D4U
-#define DBSC_DBOSCTHL30 0xE67918D8U
-#define DBSC_DBOSCTHL31 0xE67918DCU
-#define DBSC_DBOSCTHL40 0xE67918E0U
-#define DBSC_DBOSCTHL41 0xE67918E4U
-#define DBSC_DBOSCTHL50 0xE67918E8U
-#define DBSC_DBOSCTHL51 0xE67918ECU
-#define DBSC_DBOSCTHL60 0xE67918F0U
-#define DBSC_DBOSCTHL61 0xE67918F4U
-#define DBSC_DBOSCTHL70 0xE67918F8U
-#define DBSC_DBOSCTHL71 0xE67918FCU
-#define DBSC_DBMEMSWAPCONF0 0xE6792000U
-
-/* CPG registers */
-#define CPG_SRCR4 0xE61500BCU
-#define CPG_PLLECR 0xE61500D0U
-#define CPG_CPGWPR 0xE6150900U
-#define CPG_CPGWPCR 0xE6150904U
-#define CPG_SRSTCLR4 0xE6150950U
-
-/* MODE Monitor registers */
-#define RST_MODEMR 0xE6160060U
-
-#endif /* BOOT_INIT_DRAM_REGDEF_H_*/
+#include "../ddr_regs.h"
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
index d03b1b9..a49510e 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
@@ -8,8 +8,8 @@
#include <stdint.h>
#include <lib/mmio.h>
#include <common/debug.h>
-
-#include "boot_init_dram_regdef.h"
+#include "rcar_def.h"
+#include "../ddr_regs.h"
#define RCAR_DDR_VERSION "rev.0.01"
@@ -23,7 +23,7 @@
mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
mmio_write_32(DBSC_DBKIND, 0x00000007);
- mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a01);
+ mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01);
mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
mmio_write_32(DBSC_DBTR0, 0x0000000D);
mmio_write_32(DBSC_DBTR1, 0x00000009);
@@ -51,249 +51,249 @@
mmio_write_32(DBSC_DBODT0, 0x00000001);
mmio_write_32(DBSC_DBADJ0, 0x00000001);
mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
- mmio_write_32(DBSC_DBDFICNT0, 0x00000010);
+ mmio_write_32(DBSC_DBDFICNT_0, 0x00000010);
mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
mmio_write_32(DBSC_SCFCTST0, 0x0D020D04);
mmio_write_32(DBSC_SCFCTST1, 0x0306040C);
- mmio_write_32(DBSC_DBPDLK0, 0x0000A55A);
+ mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A);
mmio_write_32(DBSC_DBCMD, 0x01000001);
mmio_write_32(DBSC_DBCMD, 0x08000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x80010000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x80010000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGD0, 0x000B8000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
- mmio_write_32(DBSC_DBPDRGD0, 0x04058A04);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000091);
- mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000095);
- mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000099);
- mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
- mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
- mmio_write_32(DBSC_DBPDRGD0, 0x0024641E);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010073);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x04058A04);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000091);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000095);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000099);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010073);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
- mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
- mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
- mmio_write_32(DBSC_DBPDRGD0, 0x0780C700);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000004);
- mmio_write_32(DBSC_DBPDRGD0, 0x0A206F89);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000022);
- mmio_write_32(DBSC_DBPDRGD0, 0x1000040B);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000023);
- mmio_write_32(DBSC_DBPDRGD0, 0x35A00D77);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000024);
- mmio_write_32(DBSC_DBPDRGD0, 0x2A8A2C28);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000025);
- mmio_write_32(DBSC_DBPDRGD0, 0x30005E00);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000026);
- mmio_write_32(DBSC_DBPDRGD0, 0x0014CB49);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000027);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000F14);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000028);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000046);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000029);
- mmio_write_32(DBSC_DBPDRGD0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
- mmio_write_32(DBSC_DBPDRGD0, 0x81003047);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000020);
- mmio_write_32(DBSC_DBPDRGD0, 0x00181884);
- mmio_write_32(DBSC_DBPDRGA0, 0x0000001A);
- mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000004);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0A206F89);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000022);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000023);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x35A00D77);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000024);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x2A8A2C28);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000025);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x30005E00);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000026);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0014CB49);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000027);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000F14);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000028);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000046);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000029);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x81003047);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000020);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00181884);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A7);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A8);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A9);
- mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C7);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C8);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C9);
- mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x0000000E);
- r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x9;
+ mmio_write_32(DBSC_DBPDRGA_0, 0x0000000E);
+ r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x0000FF00) >> 0x9;
r3 = (r2 << 16) + (r2 << 8) + r2;
r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000011);
- mmio_write_32(DBSC_DBPDRGD0, r3);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000012);
- mmio_write_32(DBSC_DBPDRGD0, r3);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000016);
- mmio_write_32(DBSC_DBPDRGD0, r6);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000017);
- mmio_write_32(DBSC_DBPDRGD0, r6);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000018);
- mmio_write_32(DBSC_DBPDRGD0, r6);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000019);
- mmio_write_32(DBSC_DBPDRGD0, r6);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000011);
+ mmio_write_32(DBSC_DBPDRGD_0, r3);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000012);
+ mmio_write_32(DBSC_DBPDRGD_0, r3);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000016);
+ mmio_write_32(DBSC_DBPDRGD_0, r6);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000017);
+ mmio_write_32(DBSC_DBPDRGD_0, r6);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000018);
+ mmio_write_32(DBSC_DBPDRGD_0, r6);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000019);
+ mmio_write_32(DBSC_DBPDRGD_0, r6);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010181);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010181);
mmio_write_32(DBSC_DBCMD, 0x08000001);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010601);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010601);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
for (i = 0; i < 2; i++) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
- r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
- r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
- mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
- r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+ r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
+ r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
+ r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
if (r6 > 0) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | r6);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | r6);
} else {
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | r7);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | r7);
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 |
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 |
((r6 + (r5 << 1)) & 0xFF));
}
}
- mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
- mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010801);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
+ mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010801);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
- mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x0001F001);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
+ mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x000000AF);
- r2 = mmio_read_32(DBSC_DBPDRGD0);
- mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
- mmio_write_32(DBSC_DBPDRGA0, 0x000000CF);
- r2 = mmio_read_32(DBSC_DBPDRGD0);
- mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0);
+ mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0);
+ mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
- mmio_write_32(DBSC_DBPDRGD0, 0x81003087);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010401);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x81003087);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010401);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
for (i = 0; i < 2; i++) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
- r5 = ((mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8);
- mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
- r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+ r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
+ r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
- mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
- r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
+ r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
r12 = (r5 >> 0x2);
if (r12 < r6) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF));
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF));
} else {
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7));
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 |
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7));
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 |
((r6 + r5 +
(r5 >> 1) + r12) & 0xFF));
}
}
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00015001);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00015001);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
- mmio_write_32(DBSC_DBPDRGD0, 0x0380C700);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
- while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
+ while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
- mmio_write_32(DBSC_DBPDRGD0, 0x0024643E);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E);
mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
mmio_write_32(DBSC_DBCALCNF, 0x0100401B);
@@ -302,7 +302,7 @@
mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
mmio_write_32(DBSC_DBRFEN, 0x00000001);
mmio_write_32(DBSC_DBACEN, 0x00000001);
- mmio_write_32(DBSC_DBPDLK0, 0x00000000);
+ mmio_write_32(DBSC_DBPDLK_0, 0x00000000);
mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
#ifdef ddr_qos_init_setting // only for non qos_init
@@ -348,7 +348,7 @@
mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
mmio_write_32(DBSC_DBKIND, 0x00000007);
- mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a01);
+ mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01);
mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
mmio_write_32(DBSC_DBTR0, 0x0000000B);
mmio_write_32(DBSC_DBTR1, 0x00000008);
@@ -376,248 +376,248 @@
mmio_write_32(DBSC_DBODT0, 0x00000001);
mmio_write_32(DBSC_DBADJ0, 0x00000001);
mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
- mmio_write_32(DBSC_DBDFICNT0, 0x00000010);
+ mmio_write_32(DBSC_DBDFICNT_0, 0x00000010);
mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
mmio_write_32(DBSC_SCFCTST0, 0x0D020C04);
mmio_write_32(DBSC_SCFCTST1, 0x0305040C);
- mmio_write_32(DBSC_DBPDLK0, 0x0000A55A);
+ mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A);
mmio_write_32(DBSC_DBCMD, 0x01000001);
mmio_write_32(DBSC_DBCMD, 0x08000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x80010000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x80010000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGD0, 0x000B8000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
- mmio_write_32(DBSC_DBPDRGD0, 0x04058904);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000091);
- mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000095);
- mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000099);
- mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
- mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
- mmio_write_32(DBSC_DBPDRGD0, 0x0024641E);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010073);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x04058904);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000091);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000095);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000099);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010073);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
- mmio_write_32(DBSC_DBPDRGD0, 0x0C058900);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
- mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
- mmio_write_32(DBSC_DBPDRGD0, 0x0780C700);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000004);
- mmio_write_32(DBSC_DBPDRGD0, 0x08C05FF0);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000022);
- mmio_write_32(DBSC_DBPDRGD0, 0x1000040B);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000023);
- mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000024);
- mmio_write_32(DBSC_DBPDRGD0, 0x2A88C400);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000025);
- mmio_write_32(DBSC_DBPDRGD0, 0x30005200);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000026);
- mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000027);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000D70);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000028);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000046);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000029);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000098);
- mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
- mmio_write_32(DBSC_DBPDRGD0, 0x81003047);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000020);
- mmio_write_32(DBSC_DBPDRGD0, 0x00181884);
- mmio_write_32(DBSC_DBPDRGA0, 0x0000001A);
- mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000004);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x08C05FF0);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000022);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000023);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000024);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x2A88C400);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000025);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x30005200);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000026);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000027);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000028);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000046);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000029);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000098);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x81003047);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000020);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00181884);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A7);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A8);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A9);
- mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C7);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C8);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C9);
- mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x0000000E);
- r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x9;
+ mmio_write_32(DBSC_DBPDRGA_0, 0x0000000E);
+ r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x0000FF00) >> 0x9;
r3 = (r2 << 16) + (r2 << 8) + r2;
r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000011);
- mmio_write_32(DBSC_DBPDRGD0, r3);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000012);
- mmio_write_32(DBSC_DBPDRGD0, r3);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000016);
- mmio_write_32(DBSC_DBPDRGD0, r6);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000017);
- mmio_write_32(DBSC_DBPDRGD0, r6);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000018);
- mmio_write_32(DBSC_DBPDRGD0, r6);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000019);
- mmio_write_32(DBSC_DBPDRGD0, r6);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000011);
+ mmio_write_32(DBSC_DBPDRGD_0, r3);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000012);
+ mmio_write_32(DBSC_DBPDRGD_0, r3);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000016);
+ mmio_write_32(DBSC_DBPDRGD_0, r6);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000017);
+ mmio_write_32(DBSC_DBPDRGD_0, r6);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000018);
+ mmio_write_32(DBSC_DBPDRGD_0, r6);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000019);
+ mmio_write_32(DBSC_DBPDRGD_0, r6);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010181);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010181);
mmio_write_32(DBSC_DBCMD, 0x08000001);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010601);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010601);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
for (i = 0; i < 2; i++) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
- r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
- r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
- mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
- r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+ r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
+ r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
+ r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
if (r6 > 0) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | r6);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | r6);
} else {
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | r7);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | r7);
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 |
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 |
((r6 + (r5 << 1)) & 0xFF));
}
}
- mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
- mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010801);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
+ mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010801);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
- mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x0001F001);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
+ mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x000000AF);
- r2 = mmio_read_32(DBSC_DBPDRGD0);
- mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
- mmio_write_32(DBSC_DBPDRGA0, 0x000000CF);
- r2 = mmio_read_32(DBSC_DBPDRGD0);
- mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0);
+ mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0);
+ mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
- mmio_write_32(DBSC_DBPDRGD0, 0x81003087);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010401);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x81003087);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010401);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
for (i = 0; i < 2; i++) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
- r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
- r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+ r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
+ r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
- mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
- r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
+ r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
r12 = (r5 >> 0x2);
if (r12 < r6) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF));
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF));
} else {
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7));
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 |
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7));
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 |
((r6 + r5 +
(r5 >> 1) + r12) & 0xFF));
}
}
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00015001);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00015001);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
- mmio_write_32(DBSC_DBPDRGD0, 0x0380C700);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
- while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
+ while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
- mmio_write_32(DBSC_DBPDRGD0, 0x0024643E);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E);
mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
mmio_write_32(DBSC_DBCALCNF, 0x0100401B);
@@ -626,7 +626,7 @@
mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
mmio_write_32(DBSC_DBRFEN, 0x00000001);
mmio_write_32(DBSC_DBACEN, 0x00000001);
- mmio_write_32(DBSC_DBPDLK0, 0x00000000);
+ mmio_write_32(DBSC_DBPDLK_0, 0x00000000);
mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
#ifdef ddr_qos_init_setting // only for non qos_init
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
index 7aedc88..fc278ef 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
@@ -11,7 +11,8 @@
#include <common/debug.h>
#include "boot_init_dram.h"
-#include "boot_init_dram_regdef.h"
+#include "rcar_def.h"
+#include "../ddr_regs.h"
#include "../dram_sub_func.h"
@@ -78,9 +79,9 @@
mmio_write_32(DBSC_DBKIND, 0x00000007);
#if RCAR_DRAM_DDR3L_MEMCONF == 0
- mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a02); /* 1GB */
+ mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02); /* 1GB */
#else
- mmio_write_32(DBSC_DBMEMCONF00, 0x10030a02); /* 2GB(default) */
+ mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02); /* 2GB(default) */
#endif
#if RCAR_DRAM_DDR3L_MEMDUAL == 1
@@ -157,7 +158,7 @@
mmio_write_32(DBSC_DBODT0, 0x00000001);
mmio_write_32(DBSC_DBADJ0, 0x00000001);
mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
- mmio_write_32(DBSC_DBDFICNT0, 0x00000010);
+ mmio_write_32(DBSC_DBDFICNT_0, 0x00000010);
mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
@@ -173,231 +174,231 @@
/*
* Initial_Step0( INITBYP )
*/
- mmio_write_32(DBSC_DBPDLK0, 0x0000A55A);
+ mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A);
mmio_write_32(DBSC_DBCMD, 0x01840001);
mmio_write_32(DBSC_DBCMD, 0x08840000);
NOTICE("BL2: [COLD_BOOT]\n");
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x80010000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x80010000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
/*
* Initial_Step1( ZCAL,PLLINIT,DCAL,PHYRST training )
*/
- mmio_write_32(DBSC_DBPDRGA0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGD0, 0x000B8000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
/* Select setting value in bps */
if (ddr_md == 0) /* 1584Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x04058904);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x04058904);
else /* 1856Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x04058A04);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x04058A04);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000091);
- mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000095);
- mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000099);
- mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000091);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000095);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000099);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
/* Select setting value in bps */
if (ddr_md == 0) /* 1584Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
else /* 1856Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
- mmio_write_32(DBSC_DBPDRGD0, 0x0024641E);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010073);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010073);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
/*
* Initial_Step2( DRAMRST/DRAMINT training )
*/
- mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
/* Select setting value in bps */
if (ddr_md == 0) /* 1584Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x0C058900);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900);
else /* 1856Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
/* Select setting value in bps */
if (ddr_md == 0) /* 1584Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
else /* 1856Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
if (byp_ctl == 1)
- mmio_write_32(DBSC_DBPDRGD0, 0x0780C720);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0780C720);
else
- mmio_write_32(DBSC_DBPDRGD0, 0x0780C700);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000004);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000004);
/* Select setting value in bps */
if (ddr_md == 0) { /* 1584Mbps */
- mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 792 / 125) -
+ mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 792 / 125) -
400 + 0x08B00000);
} else { /* 1856Mbps */
- mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 928 / 125) -
+ mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 928 / 125) -
400 + 0x0A300000);
}
- mmio_write_32(DBSC_DBPDRGA0, 0x00000022);
- mmio_write_32(DBSC_DBPDRGD0, 0x1000040B);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000023);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000022);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000023);
/* Select setting value in bps */
if (ddr_md == 0) /* 1584Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66);
else /* 1856Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x35A00D77);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x35A00D77);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000024);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000024);
/* Select setting value in bps */
if (ddr_md == 0) /* 1584Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x2A88B400);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x2A88B400);
else /* 1856Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x2A8A2C28);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x2A8A2C28);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000025);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000025);
/* Select setting value in bps */
if (ddr_md == 0) /* 1584Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x30005200);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x30005200);
else /* 1856Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x30005E00);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x30005E00);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000026);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000026);
/* Select setting value in bps */
if (ddr_md == 0) /* 1584Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9);
else /* 1856Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x0014CB49);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0014CB49);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000027);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000027);
/* Select setting value in bps */
if (ddr_md == 0) /* 1584Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x00000D70);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70);
else /* 1856Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x00000F14);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000F14);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000028);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000046);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000029);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000028);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000046);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000029);
/* Select setting value in bps */
if (ddr_md == 0) { /* 1584Mbps */
if (REFRESH_RATE > 3900) /* [7]SRT=0 */
- mmio_write_32(DBSC_DBPDRGD0, 0x18);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x18);
else /* [7]SRT=1 */
- mmio_write_32(DBSC_DBPDRGD0, 0x98);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x98);
} else { /* 1856Mbps */
if (REFRESH_RATE > 3900) /* [7]SRT=0 */
- mmio_write_32(DBSC_DBPDRGD0, 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x20);
else /* [7]SRT=1 */
- mmio_write_32(DBSC_DBPDRGD0, 0xA0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0xA0);
}
- mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
- mmio_write_32(DBSC_DBPDRGD0, 0x81003047);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000020);
- mmio_write_32(DBSC_DBPDRGD0, 0x00181884);
- mmio_write_32(DBSC_DBPDRGA0, 0x0000001A);
- mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x81003047);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000020);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00181884);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A7);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A8);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A9);
- mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C7);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C8);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C9);
- mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E7);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E8);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E9);
- mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000107);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000108);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000109);
- mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E7);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E8);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E9);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000107);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000108);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000109);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010181);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010181);
mmio_write_32(DBSC_DBCMD, 0x08840001);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
/*
* Initial_Step3( WL/QSG training )
*/
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010601);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010601);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
for (i = 0; i < 4; i++) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
- r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
- r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
- mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
- r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+ r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
+ r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
+ r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
if (r6 > 0) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | r6);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | r6);
} else {
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | r7);
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 |
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | r7);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 |
((r6 + ((r5) << 1)) &
0xFF));
}
@@ -406,191 +407,191 @@
/*
* Initial_Step4( WLADJ training )
*/
- mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
- mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
+ mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0);
if (pdqsr_ctl == 0) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
}
/* PDR always off */
if (pdr_ctl == 1) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
}
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010801);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010801);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
/*
* Initial_Step5(Read Data Bit Deskew)
*/
- mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
- mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
+ mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00011001);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00011001);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
if (pdqsr_ctl == 1) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
}
/* PDR dynamic */
if (pdr_ctl == 1) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
}
/*
* Initial_Step6(Write Data Bit Deskew)
*/
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00012001);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00012001);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
/*
* Initial_Step7(Read Data Eye Training)
*/
if (pdqsr_ctl == 1) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
}
/* PDR always off */
if (pdr_ctl == 1) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
}
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00014001);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00014001);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
if (pdqsr_ctl == 1) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
}
/* PDR dynamic */
if (pdr_ctl == 1) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
}
/*
* Initial_Step8(Write Data Eye Training)
*/
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00018001);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00018001);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
/*
* Initial_Step3_2( DQS Gate Training )
*/
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
- mmio_write_32(DBSC_DBPDRGD0, 0x81003087);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010401);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x81003087);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010401);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
for (i = 0; i < 4; i++) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
- r5 = ((mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8);
- mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
- r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
- mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
- r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+ r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
+ r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
+ r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
r12 = (r5 >> 0x2);
if (r12 < r6) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF));
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF));
} else {
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7));
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 + r5 +
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7));
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + r5 +
(r5 >> 1) + r12) & 0xFF));
}
}
@@ -599,40 +600,40 @@
* Initial_Step5-2_7-2( Rd bit Rd eye )
*/
if (pdqsr_ctl == 0) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
}
/* PDR always off */
if (pdr_ctl == 1) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
}
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00015001);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00015001);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
if (lcdl_ctl == 1) {
for (i = 0; i < 4; i++) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- dqsgd_0c = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
- mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
- bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >>
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ dqsgd_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+ bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >>
8;
bdlcount_0c_div2 = bdlcount_0c >> 1;
bdlcount_0c_div4 = bdlcount_0c >> 2;
@@ -657,43 +658,43 @@
continue;
if (dqsgd_0c <= lcdl_judge2) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- regval = mmio_read_32(DBSC_DBPDRGD0) &
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD_0) &
0xFFFFFF00;
- mmio_write_32(DBSC_DBPDRGD0,
+ mmio_write_32(DBSC_DBPDRGD_0,
(dqsgd_0c - bdlcount_0c_div8) |
regval);
} else {
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- regval = mmio_read_32(DBSC_DBPDRGD0) &
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD_0) &
0xFFFFFF00;
- mmio_write_32(DBSC_DBPDRGD0, regval);
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- gatesl_0c = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- regval = mmio_read_32(DBSC_DBPDRGD0) &
+ mmio_write_32(DBSC_DBPDRGD_0, regval);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ gatesl_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD_0) &
0xFFFFFFF8;
- mmio_write_32(DBSC_DBPDRGD0, regval |
+ mmio_write_32(DBSC_DBPDRGD_0, regval |
(gatesl_0c + 1));
- mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20);
- regval = (mmio_read_32(DBSC_DBPDRGD0));
+ mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20);
+ regval = (mmio_read_32(DBSC_DBPDRGD_0));
rdqsd_0c = (regval & 0xFF00) >> 8;
rdqsnd_0c = (regval & 0xFF0000) >> 16;
- mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0,
+ mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0,
(regval & 0xFF0000FF) |
((rdqsd_0c +
bdlcount_0c_div4) << 8) |
((rdqsnd_0c +
bdlcount_0c_div4) << 16));
- mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20);
- regval = (mmio_read_32(DBSC_DBPDRGD0));
+ mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20);
+ regval = (mmio_read_32(DBSC_DBPDRGD_0));
rbd_0c[0] = (regval) & 0x1f;
rbd_0c[1] = (regval >> 8) & 0x1f;
rbd_0c[2] = (regval >> 16) & 0x1f;
rbd_0c[3] = (regval >> 24) & 0x1f;
- mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20);
- regval = mmio_read_32(DBSC_DBPDRGD0) &
+ mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD_0) &
0xE0E0E0E0;
for (j = 0; j < 4; j++) {
rbd_0c[j] = rbd_0c[j] +
@@ -702,15 +703,15 @@
rbd_0c[j] = 0x1F;
regval = regval | (rbd_0c[j] << 8 * j);
}
- mmio_write_32(DBSC_DBPDRGD0, regval);
- mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20);
- regval = (mmio_read_32(DBSC_DBPDRGD0));
+ mmio_write_32(DBSC_DBPDRGD_0, regval);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20);
+ regval = (mmio_read_32(DBSC_DBPDRGD_0));
rbd_0c[0] = (regval) & 0x1f;
rbd_0c[1] = (regval >> 8) & 0x1f;
rbd_0c[2] = (regval >> 16) & 0x1f;
rbd_0c[3] = (regval >> 24) & 0x1f;
- mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20);
- regval = mmio_read_32(DBSC_DBPDRGD0) &
+ mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD_0) &
0xE0E0E0E0;
for (j = 0; j < 4; j++) {
rbd_0c[j] = rbd_0c[j] +
@@ -719,25 +720,25 @@
rbd_0c[j] = 0x1F;
regval = regval | (rbd_0c[j] << 8 * j);
}
- mmio_write_32(DBSC_DBPDRGD0, regval);
+ mmio_write_32(DBSC_DBPDRGD_0, regval);
}
}
- mmio_write_32(DBSC_DBPDRGA0, 0x2);
- mmio_write_32(DBSC_DBPDRGD0, 0x7D81E37);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x2);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7D81E37);
}
- mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
if (byp_ctl == 1)
- mmio_write_32(DBSC_DBPDRGD0, 0x0380C720);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0380C720);
else
- mmio_write_32(DBSC_DBPDRGD0, 0x0380C700);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
- while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
+ while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
- mmio_write_32(DBSC_DBPDRGD0, 0x0024643E);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E);
mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
mmio_write_32(DBSC_DBCALCNF, (64000000 / REFRESH_RATE) + 0x01000000);
@@ -758,34 +759,34 @@
if (pdqsr_ctl == 1) {
mmio_write_32(0xE67F0018, 0x00000001);
regval = mmio_read_32(0x40000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000000);
- mmio_write_32(DBSC_DBPDRGD0, regval);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGD_0, regval);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
}
/* PDR dynamic */
if (pdr_ctl == 1) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
}
/*
* Initial_Step9( Initial End )
*/
- mmio_write_32(DBSC_DBPDLK0, 0x00000000);
+ mmio_write_32(DBSC_DBPDLK_0, 0x00000000);
mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
#ifdef ddr_qos_init_setting /* only for non qos_init */
@@ -881,9 +882,9 @@
mmio_write_32(DBSC_DBKIND, 0x00000007);
#if RCAR_DRAM_DDR3L_MEMCONF == 0
- mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a02);
+ mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02);
#else
- mmio_write_32(DBSC_DBMEMCONF00, 0x10030a02);
+ mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02);
#endif
#if RCAR_DRAM_DDR3L_MEMDUAL == 1
@@ -960,7 +961,7 @@
mmio_write_32(DBSC_DBODT0, 0x00000001);
mmio_write_32(DBSC_DBADJ0, 0x00000001);
mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
- mmio_write_32(DBSC_DBDFICNT0, 0x00000010);
+ mmio_write_32(DBSC_DBDFICNT_0, 0x00000010);
mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
@@ -976,143 +977,143 @@
/*
* recovery_Step1(PHY setting 1)
*/
- mmio_write_32(DBSC_DBPDLK0, 0x0000A55A);
+ mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A);
mmio_write_32(DBSC_DBCMD, 0x01840001);
mmio_write_32(DBSC_DBCMD, 0x0A840000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000008); /* DDR_PLLCR */
- mmio_write_32(DBSC_DBPDRGD0, 0x000B8000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000003); /* DDR_PGCR1 */
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000008); /* DDR_PLLCR */
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); /* DDR_PGCR1 */
if (byp_ctl == 1)
- mmio_write_32(DBSC_DBPDRGD0, 0x0780C720);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0780C720);
else
- mmio_write_32(DBSC_DBPDRGD0, 0x0780C700);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000020); /* DDR_DXCCR */
- mmio_write_32(DBSC_DBPDRGD0, 0x00181884);
- mmio_write_32(DBSC_DBPDRGA0, 0x0000001A); /* DDR_ACIOCR0 */
- mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); /* DDR_DXCCR */
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00181884);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A); /* DDR_ACIOCR0 */
+ mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000004);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000004);
/* Select setting value in bps */
if (ddr_md == 0) { /* 1584Mbps */
- mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 792 / 125) -
+ mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 792 / 125) -
400 + 0x08B00000);
} else { /* 1856Mbps */
- mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 928 / 125) -
+ mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 928 / 125) -
400 + 0x0A300000);
}
- mmio_write_32(DBSC_DBPDRGA0, 0x00000022);
- mmio_write_32(DBSC_DBPDRGD0, 0x1000040B);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000023);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000022);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000023);
/* Select setting value in bps */
if (ddr_md == 0) /* 1584Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66);
else /* 1856Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x35A00D77);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x35A00D77);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000024);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000024);
/* Select setting value in bps */
if (ddr_md == 0) /* 1584Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x2A88B400);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x2A88B400);
else /* 1856Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x2A8A2C28);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x2A8A2C28);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000025);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000025);
/* Select setting value in bps */
if (ddr_md == 0) /* 1584Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x30005200);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x30005200);
else /* 1856Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x30005E00);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x30005E00);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000026);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000026);
/* Select setting value in bps */
if (ddr_md == 0) /* 1584Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9);
else /* 1856Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x0014CB49);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0014CB49);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000027);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000027);
/* Select setting value in bps */
if (ddr_md == 0) /* 1584Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x00000D70);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70);
else /* 1856Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x00000F14);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000F14);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000028);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000046);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000029);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000028);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000046);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000029);
/* Select setting value in bps */
if (ddr_md == 0) { /* 1584Mbps */
if (REFRESH_RATE > 3900)
- mmio_write_32(DBSC_DBPDRGD0, 0x18); /* [7]SRT=0 */
+ mmio_write_32(DBSC_DBPDRGD_0, 0x18); /* [7]SRT=0 */
else
- mmio_write_32(DBSC_DBPDRGD0, 0x98); /* [7]SRT=1 */
+ mmio_write_32(DBSC_DBPDRGD_0, 0x98); /* [7]SRT=1 */
} else { /* 1856Mbps */
if (REFRESH_RATE > 3900)
- mmio_write_32(DBSC_DBPDRGD0, 0x20); /* [7]SRT=0 */
+ mmio_write_32(DBSC_DBPDRGD_0, 0x20); /* [7]SRT=0 */
else
- mmio_write_32(DBSC_DBPDRGD0, 0xA0); /* [7]SRT=1 */
+ mmio_write_32(DBSC_DBPDRGD_0, 0xA0); /* [7]SRT=1 */
}
- mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
- mmio_write_32(DBSC_DBPDRGD0, 0x81003047);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000091);
- mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000095);
- mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000099);
- mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000021); /* DDR_DSGCR */
- mmio_write_32(DBSC_DBPDRGD0, 0x0024641E);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x81003047);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000091);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000095);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000099);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); /* DDR_DSGCR */
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */
- mmio_write_32(DBSC_DBPDRGD0, 0x40010000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */
+ mmio_write_32(DBSC_DBPDRGD_0, 0x40010000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000092); /* DDR_ZQ0DR */
- mmio_write_32(DBSC_DBPDRGD0, 0xC2C59AB5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000096); /* DDR_ZQ1DR */
- mmio_write_32(DBSC_DBPDRGD0, 0xC4285FBF);
- mmio_write_32(DBSC_DBPDRGA0, 0x0000009A); /* DDR_ZQ2DR */
- mmio_write_32(DBSC_DBPDRGD0, 0xC2C59AB5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000090); /* DDR_ZQCR */
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000092); /* DDR_ZQ0DR */
+ mmio_write_32(DBSC_DBPDRGD_0, 0xC2C59AB5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000096); /* DDR_ZQ1DR */
+ mmio_write_32(DBSC_DBPDRGD_0, 0xC4285FBF);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x0000009A); /* DDR_ZQ2DR */
+ mmio_write_32(DBSC_DBPDRGD_0, 0xC2C59AB5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* DDR_ZQCR */
/* Select setting value in bps */
if (ddr_md == 0) /* 1584Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x0C058900);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900);
else /* 1856Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000090); /* DDR_ZQCR */
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* DDR_ZQCR */
/* Select setting value in bps */
if (ddr_md == 0) /* 1584Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
else /* 1856Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */
- mmio_write_32(DBSC_DBPDRGD0, 0x00050001);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00050001);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
/* ddr backupmode end */
@@ -1127,87 +1128,87 @@
return INITDRAM_ERR_I;
}
- mmio_write_32(DBSC_DBPDRGA0, 0x00000092); /* DDR_ZQ0DR */
- mmio_write_32(DBSC_DBPDRGD0, 0x02C59AB5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000096); /* DDR_ZQ1DR */
- mmio_write_32(DBSC_DBPDRGD0, 0x04285FBF);
- mmio_write_32(DBSC_DBPDRGA0, 0x0000009A); /* DDR_ZQ2DR */
- mmio_write_32(DBSC_DBPDRGD0, 0x02C59AB5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000092); /* DDR_ZQ0DR */
+ mmio_write_32(DBSC_DBPDRGD_0, 0x02C59AB5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000096); /* DDR_ZQ1DR */
+ mmio_write_32(DBSC_DBPDRGD_0, 0x04285FBF);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x0000009A); /* DDR_ZQ2DR */
+ mmio_write_32(DBSC_DBPDRGD_0, 0x02C59AB5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */
- mmio_write_32(DBSC_DBPDRGD0, 0x08000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */
+ mmio_write_32(DBSC_DBPDRGD_0, 0x08000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */
- mmio_write_32(DBSC_DBPDRGD0, 0x00000003);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000003);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */
- mmio_write_32(DBSC_DBPDRGD0, 0x80010000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */
+ mmio_write_32(DBSC_DBPDRGD_0, 0x80010000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */
- mmio_write_32(DBSC_DBPDRGD0, 0x00010073);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010073);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000090); /* DDR_ZQCR */
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* DDR_ZQCR */
/* Select setting value in bps */
if (ddr_md == 0) /* 1584Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x0C058900);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900);
else /* 1856Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000090); /* DDR_ZQCR */
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* DDR_ZQCR */
/* Select setting value in bps */
if (ddr_md == 0) /* 1584Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
else /* 1856Mbps */
- mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00);
- mmio_write_32(DBSC_DBPDRGA0, 0x0000000C);
- mmio_write_32(DBSC_DBPDRGD0, 0x18000040);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x0000000C);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x18000040);
/*
* recovery_Step2(PHY setting 2)
*/
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A7);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A8);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A9);
- mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C7);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C8);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C9);
- mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E7);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E8);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E9);
- mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000107);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000108);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000109);
- mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E7);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E8);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E9);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000107);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000108);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000109);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
mmio_write_32(DBSC_DBCALCNF, (64000000 / REFRESH_RATE) + 0x01000000);
mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
@@ -1233,258 +1234,258 @@
while (mmio_read_32(DBSC_DBWAIT) & BIT(0))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */
- mmio_write_32(DBSC_DBPDRGD0, 0x00010701);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010701);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
for (i = 0; i < 4; i++) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
- r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
- r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
- mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
- r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+ r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
+ r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
+ r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
if (r6 > 0) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | r6);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | r6);
} else {
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | r7);
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0,
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | r7);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0,
r2 | ((r6 + (r5 << 1)) & 0xFF));
}
}
- mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
- mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
+ mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0);
if (pdqsr_ctl == 0) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
}
/* PDR always off */
if (pdr_ctl == 1) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
}
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010801);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010801);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
- mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
+ mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00011001);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00011001);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
if (pdqsr_ctl == 1) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
}
/* PDR dynamic */
if (pdr_ctl == 1) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
}
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00012001);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00012001);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
if (pdqsr_ctl == 1) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
}
/* PDR always off */
if (pdr_ctl == 1) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
}
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00014001);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00014001);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
if (pdqsr_ctl == 1) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
}
/* PDR dynamic */
if (pdr_ctl == 1) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
}
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00018001);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00018001);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
- mmio_write_32(DBSC_DBPDRGD0, 0x81003087);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010401);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x81003087);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010401);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
for (i = 0; i < 4; i++) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
- r5 = ((mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8);
- mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
- r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
- mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
- r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+ r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
+ r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
+ r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
r12 = r5 >> 0x2;
if (r12 < r6) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF));
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF));
} else {
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7));
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0,
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7));
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0,
r2 |
((r6 + r5 + (r5 >> 1) + r12) & 0xFF));
}
}
if (pdqsr_ctl == 0) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
}
/* PDR always off */
if (pdr_ctl == 1) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
}
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00015001);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00015001);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
if (lcdl_ctl == 1) {
for (i = 0; i < 4; i++) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
- dqsgd_0c = mmio_read_32(DBSC_DBPDRGD0) & 0x000000FF;
- mmio_write_32(DBSC_DBPDRGA0, 0x000000B1 + i * 0x20);
- bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD0) &
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000B0 + i * 0x20);
+ dqsgd_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0x000000FF;
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000B1 + i * 0x20);
+ bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD_0) &
0x0000FF00) >> 8;
bdlcount_0c_div2 = (bdlcount_0c >> 1);
bdlcount_0c_div4 = (bdlcount_0c >> 2);
@@ -1509,43 +1510,43 @@
continue;
if (dqsgd_0c <= lcdl_judge2) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- regval = mmio_read_32(DBSC_DBPDRGD0) &
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD_0) &
0xFFFFFF00;
- mmio_write_32(DBSC_DBPDRGD0,
+ mmio_write_32(DBSC_DBPDRGD_0,
(dqsgd_0c - bdlcount_0c_div8) |
regval);
} else {
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- regval = mmio_read_32(DBSC_DBPDRGD0) &
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD_0) &
0xFFFFFF00;
- mmio_write_32(DBSC_DBPDRGD0, regval);
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- gatesl_0c = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- regval = mmio_read_32(DBSC_DBPDRGD0) &
+ mmio_write_32(DBSC_DBPDRGD_0, regval);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ gatesl_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD_0) &
0xFFFFFFF8;
- mmio_write_32(DBSC_DBPDRGD0,
+ mmio_write_32(DBSC_DBPDRGD_0,
regval | (gatesl_0c + 1));
- mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20);
- regval = mmio_read_32(DBSC_DBPDRGD0);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD_0);
rdqsd_0c = (regval & 0xFF00) >> 8;
rdqsnd_0c = (regval & 0xFF0000) >> 16;
- mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0,
+ mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0,
(regval & 0xFF0000FF) |
((rdqsd_0c +
bdlcount_0c_div4) << 8) |
((rdqsnd_0c +
bdlcount_0c_div4) << 16));
- mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20);
- regval = (mmio_read_32(DBSC_DBPDRGD0));
+ mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20);
+ regval = (mmio_read_32(DBSC_DBPDRGD_0));
rbd_0c[0] = (regval) & 0x1f;
rbd_0c[1] = (regval >> 8) & 0x1f;
rbd_0c[2] = (regval >> 16) & 0x1f;
rbd_0c[3] = (regval >> 24) & 0x1f;
- mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20);
- regval = mmio_read_32(DBSC_DBPDRGD0) &
+ mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD_0) &
0xE0E0E0E0;
for (j = 0; j < 4; j++) {
rbd_0c[j] = rbd_0c[j] +
@@ -1554,15 +1555,15 @@
rbd_0c[j] = 0x1F;
regval = regval | (rbd_0c[j] << 8 * j);
}
- mmio_write_32(DBSC_DBPDRGD0, regval);
- mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20);
- regval = (mmio_read_32(DBSC_DBPDRGD0));
+ mmio_write_32(DBSC_DBPDRGD_0, regval);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20);
+ regval = (mmio_read_32(DBSC_DBPDRGD_0));
rbd_0c[0] = regval & 0x1f;
rbd_0c[1] = (regval >> 8) & 0x1f;
rbd_0c[2] = (regval >> 16) & 0x1f;
rbd_0c[3] = (regval >> 24) & 0x1f;
- mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20);
- regval = mmio_read_32(DBSC_DBPDRGD0) &
+ mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD_0) &
0xE0E0E0E0;
for (j = 0; j < 4; j++) {
rbd_0c[j] = rbd_0c[j] +
@@ -1571,24 +1572,24 @@
rbd_0c[j] = 0x1F;
regval = regval | (rbd_0c[j] << 8 * j);
}
- mmio_write_32(DBSC_DBPDRGD0, regval);
+ mmio_write_32(DBSC_DBPDRGD_0, regval);
}
}
- mmio_write_32(DBSC_DBPDRGA0, 0x00000002);
- mmio_write_32(DBSC_DBPDRGD0, 0x07D81E37);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000002);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x07D81E37);
}
- mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
if (byp_ctl == 1)
- mmio_write_32(DBSC_DBPDRGD0, 0x0380C720);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0380C720);
else
- mmio_write_32(DBSC_DBPDRGD0, 0x0380C700);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
- while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
+ while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
- mmio_write_32(DBSC_DBPDRGD0, 0x0024643E);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E);
/*
* recovery_Step3(DBSC Setting 2)
@@ -1599,31 +1600,31 @@
if (pdqsr_ctl == 1) {
mmio_write_32(0xE67F0018, 0x00000001);
regval = mmio_read_32(0x40000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000000);
- mmio_write_32(DBSC_DBPDRGD0, regval);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGD_0, regval);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
}
/* PDR dynamic */
if (pdr_ctl == 1) {
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
}
- mmio_write_32(DBSC_DBPDLK0, 0x00000000);
+ mmio_write_32(DBSC_DBPDLK_0, 0x00000000);
mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
#ifdef ddr_qos_init_setting /* only for non qos_init */
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
index 00e1903..5410771 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
@@ -9,7 +9,8 @@
#include <lib/utils_def.h>
#include <stdint.h>
#include "boot_init_dram.h"
-#include "boot_init_dram_regdef.h"
+#include "rcar_def.h"
+#include "../ddr_regs.h"
static uint32_t init_ddr_v3m_1600(void)
{
@@ -18,9 +19,9 @@
mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
mmio_write_32(DBSC_DBKIND, 0x00000007);
#if RCAR_DRAM_DDR3L_MEMCONF == 0
- mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a02); // 1GB: Eagle
+ mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02); // 1GB: Eagle
#else
- mmio_write_32(DBSC_DBMEMCONF00, 0x10030a02); // 2GB: V3MSK
+ mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02); // 2GB: V3MSK
#endif
mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
mmio_write_32(DBSC_DBTR0, 0x0000000B);
@@ -79,243 +80,243 @@
mmio_write_32(DBSC_DBCAM0CNF2, 0x000001c4);
mmio_write_32(DBSC_DBSCHSZ0, 0x00000003);
mmio_write_32(DBSC_DBSCHRW1, 0x001a0080);
- mmio_write_32(DBSC_DBDFICNT0, 0x00000010);
+ mmio_write_32(DBSC_DBDFICNT_0, 0x00000010);
- mmio_write_32(DBSC_DBPDLK0, 0x0000A55A);
+ mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A);
mmio_write_32(DBSC_DBCMD, 0x01000001);
mmio_write_32(DBSC_DBCMD, 0x08000000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x80010000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x80010000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000008);
- mmio_write_32(DBSC_DBPDRGD0, 0x000B8000);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
- mmio_write_32(DBSC_DBPDRGD0, 0x04058904);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000091);
- mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6D);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000095);
- mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000099);
- mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6D);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
- mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
- mmio_write_32(DBSC_DBPDRGD0, 0x0024641E);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010073);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x04058904);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000091);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000095);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000099);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010073);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
- mmio_write_32(DBSC_DBPDRGD0, 0x0C058900);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
- mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
- mmio_write_32(DBSC_DBPDRGD0, 0x0780C700);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000004);
- mmio_write_32(DBSC_DBPDRGD0, 0x08C0C170);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000022);
- mmio_write_32(DBSC_DBPDRGD0, 0x1000040B);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000023);
- mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000024);
- mmio_write_32(DBSC_DBPDRGD0, 0x2A88C400);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000025);
- mmio_write_32(DBSC_DBPDRGD0, 0x30005200);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000026);
- mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000027);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000D70);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000028);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000004);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000029);
- mmio_write_32(DBSC_DBPDRGD0, 0x00000018);
- mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
- mmio_write_32(DBSC_DBPDRGD0, 0x81003047);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000020);
- mmio_write_32(DBSC_DBPDRGD0, 0x00181884);
- mmio_write_32(DBSC_DBPDRGA0, 0x0000001A);
- mmio_write_32(DBSC_DBPDRGD0, 0x13C03C10);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000004);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x08C0C170);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000022);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000023);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000024);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x2A88C400);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000025);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x30005200);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000026);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000027);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000028);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000004);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000029);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00000018);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x81003047);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000020);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00181884);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x13C03C10);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A7);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A8);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A9);
- mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C7);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C8);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C9);
- mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E7);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E8);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E9);
- mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000107);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000108);
- mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000109);
- mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010181);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E7);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E8);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E9);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000107);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000108);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000109);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010181);
mmio_write_32(DBSC_DBCMD, 0x08000001);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010601);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010601);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
for (i = 0; i < 4; i++) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
- r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
- r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
- mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
- r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+ r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
+ r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
+ r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
if (r6 > 0) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8);
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, ((r7 + 1) & 0x7) | r2);
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | r6);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, ((r7 + 1) & 0x7) | r2);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | r6);
} else {
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 | r7);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 | r7);
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 |
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 |
(((r5 << 1) + r6) & 0xFF));
}
}
- mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
- mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00A0);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010801);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
+ mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00A0);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010801);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
- mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00B8);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x0001F001);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
+ mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00B8);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
- mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
- mmio_write_32(DBSC_DBPDRGD0, 0x81003087);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00010401);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x81003087);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00010401);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
for (i = 0; i < 4; i++) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
- r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 8;
- mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
- r6 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+ r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8;
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
+ r6 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF);
- mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
- r7 = (mmio_read_32(DBSC_DBPDRGD0) & 0x7);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
+ r7 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x7);
r12 = (r5 >> 2);
if (r6 - r12 > 0) {
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8);
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, ((r7 + 1) & 0x7) | r2);
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, ((r7 + 1) & 0x7) | r2);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00);
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, ((r6 - r12) & 0xFF) | r2);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, ((r6 - r12) & 0xFF) | r2);
} else {
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
- mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, (r7 & 0x7) | r2);
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
- mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
- mmio_write_32(DBSC_DBPDRGD0, r2 |
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, (r7 & 0x7) | r2);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00);
+ mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD_0, r2 |
((r6 + r5 +
(r5 >> 1) + r12) & 0xFF));
}
}
- mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
- mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
- mmio_write_32(DBSC_DBPDRGD0, 0x00015001);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
- while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x00015001);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
- mmio_write_32(DBSC_DBPDRGD0, 0x0380C700);
- mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
- while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30))
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
+ while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))
;
- mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
- mmio_write_32(DBSC_DBPDRGD0, 0x0024643E);
+ mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
+ mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E);
mmio_write_32(DBSC_DBBUS0CNF1, 0x00000000);
mmio_write_32(DBSC_DBBUS0CNF0, 0x00010001);
@@ -325,7 +326,7 @@
mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
mmio_write_32(DBSC_DBRFEN, 0x00000001);
mmio_write_32(DBSC_DBACEN, 0x00000001);
- mmio_write_32(DBSC_DBPDLK0, 0x00000000);
+ mmio_write_32(DBSC_DBPDLK_0, 0x00000000);
mmio_write_32(0xE67F0024, 0x00000001);
mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
index 2cce653..9f7c954 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
@@ -1,5 +1,6 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,16 +26,14 @@
#define DDR_BACKUPMODE
#define FATAL_MSG(x) NOTICE(x)
-/*******************************************************************************
- * variables
- ******************************************************************************/
+/* variables */
#ifdef RCAR_DDR_FIXED_LSI_TYPE
#ifndef RCAR_AUTO
#define RCAR_AUTO 99
-#define RCAR_H3 0
-#define RCAR_M3 1
+#define RCAR_H3 0
+#define RCAR_M3 1
#define RCAR_M3N 2
-#define RCAR_E3 3 /* NON */
+#define RCAR_E3 3 /* NON */
#define RCAR_H3N 4
#define RCAR_CUT_10 0
@@ -45,42 +44,41 @@
#ifndef RCAR_LSI
#define RCAR_LSI RCAR_AUTO
#endif
-#if(RCAR_LSI==RCAR_AUTO)
-static uint32_t Prr_Product;
-static uint32_t Prr_Cut;
+
+#if (RCAR_LSI == RCAR_AUTO)
+static uint32_t prr_product;
+static uint32_t prr_cut;
#else
-#if(RCAR_LSI==RCAR_H3)
-static const uint32_t Prr_Product = PRR_PRODUCT_H3;
-#elif(RCAR_LSI==RCAR_M3)
-static const uint32_t Prr_Product = PRR_PRODUCT_M3;
-#elif(RCAR_LSI==RCAR_M3N)
-static const uint32_t Prr_Product = PRR_PRODUCT_M3N;
-#elif(RCAR_LSI==RCAR_H3N)
-static const uint32_t Prr_Product = PRR_PRODUCT_H3;
+#if (RCAR_LSI == RCAR_H3)
+static const uint32_t prr_product = PRR_PRODUCT_H3;
+#elif(RCAR_LSI == RCAR_M3)
+static const uint32_t prr_product = PRR_PRODUCT_M3;
+#elif(RCAR_LSI == RCAR_M3N)
+static const uint32_t prr_product = PRR_PRODUCT_M3N;
+#elif(RCAR_LSI == RCAR_H3N)
+static const uint32_t prr_product = PRR_PRODUCT_H3;
#endif /* RCAR_LSI */
#ifndef RCAR_LSI_CUT
-static uint32_t Prr_Cut;
+static uint32_t prr_cut;
#else /* RCAR_LSI_CUT */
-#if(RCAR_LSI_CUT==RCAR_CUT_10)
-static const uint32_t Prr_Cut = PRR_PRODUCT_10;
-#elif(RCAR_LSI_CUT==RCAR_CUT_11)
-static const uint32_t Prr_Cut = PRR_PRODUCT_11;
-#elif(RCAR_LSI_CUT==RCAR_CUT_20)
-static const uint32_t Prr_Cut = PRR_PRODUCT_20;
-#elif(RCAR_LSI_CUT==RCAR_CUT_30)
-static const uint32_t Prr_Cut = PRR_PRODUCT_30;
+#if (RCAR_LSI_CUT == RCAR_CUT_10)
+static const uint32_t prr_cut = PRR_PRODUCT_10;
+#elif(RCAR_LSI_CUT == RCAR_CUT_11)
+static const uint32_t prr_cut = PRR_PRODUCT_11;
+#elif(RCAR_LSI_CUT == RCAR_CUT_20)
+static const uint32_t prr_cut = PRR_PRODUCT_20;
+#elif(RCAR_LSI_CUT == RCAR_CUT_30)
+static const uint32_t prr_cut = PRR_PRODUCT_30;
#endif /* RCAR_LSI_CUT */
#endif /* RCAR_LSI_CUT */
#endif /* RCAR_AUTO_NON */
#else /* RCAR_DDR_FIXED_LSI_TYPE */
-static uint32_t Prr_Product;
-static uint32_t Prr_Cut;
+static uint32_t prr_product;
+static uint32_t prr_cut;
#endif /* RCAR_DDR_FIXED_LSI_TYPE */
-char *pRCAR_DDR_VERSION;
-uint32_t _cnf_BOARDTYPE;
-static const uint32_t *pDDR_REGDEF_TBL;
+static const uint32_t *p_ddr_regdef_tbl;
static uint32_t brd_clk;
static uint32_t brd_clkdiv;
static uint32_t brd_clkdiva;
@@ -88,11 +86,11 @@
static uint32_t ddr_mbpsdiv;
static uint32_t ddr_tccd;
static uint32_t ddr_phycaslice;
-static const struct _boardcnf *Boardcnf;
+static const struct _boardcnf *board_cnf;
static uint32_t ddr_phyvalid;
static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT];
-static uint32_t ch_have_this_cs[CS_CNT] __attribute__ ((aligned(64)));
-static uint32_t rdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
+static uint32_t ch_have_this_cs[CS_CNT] __aligned(64);
+static uint32_t rdqdm_dly[DRAM_CH_CNT][CSAB_CNT][SLICE_CNT * 2][9];
static uint32_t max_density;
static uint32_t ddr0800_mul;
static uint32_t ddr_mul;
@@ -119,10 +117,10 @@
static uint32_t _cnf_DDR_PHY_ADR_I_REGSET[DDR_PHY_REGSET_MAX];
static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX];
static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX];
-static uint32_t Pll3Mode;
+static uint32_t pll3_mode;
static uint32_t loop_max;
#ifdef DDR_BACKUPMODE
-uint32_t ddrBackup;
+uint32_t ddr_backup;
/* #define DDR_BACKUPMODE_HALF //for Half channel(ch0,1 only) */
#endif
@@ -130,7 +128,9 @@
#define OPERATING_FREQ (400U) /* Mhz */
#define BASE_SUB_SLOT_NUM (0x6U)
#define SUB_SLOT_CYCLE (0x7EU) /* 126 */
-#define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
+#define QOSWT_WTSET0_CYCLE \
+ ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / \
+ OPERATING_FREQ) /* unit:ns */
uint32_t get_refperiod(void)
{
@@ -156,8 +156,8 @@
};
#define _reg_PHY_CLK_WRX_SLAVE_DELAY_NUM 10
-static const uint32_t
- _reg_PHY_CLK_WRX_SLAVE_DELAY[_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = {
+static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY
+ [_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = {
_reg_PHY_CLK_WRDQ0_SLAVE_DELAY,
_reg_PHY_CLK_WRDQ1_SLAVE_DELAY,
_reg_PHY_CLK_WRDQ2_SLAVE_DELAY,
@@ -171,8 +171,8 @@
};
#define _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM 9
-static const uint32_t
- _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = {
+static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY
+ [_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = {
_reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY,
_reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY,
_reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY,
@@ -185,8 +185,8 @@
};
#define _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM 9
-static const uint32_t
- _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = {
+static const uint32_t _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY
+ [_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = {
_reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY,
_reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY,
_reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY,
@@ -211,8 +211,8 @@
};
#define _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM 10
-static const uint32_t
- _reg_PHY_CLK_CACS_SLAVE_DELAY_X[_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = {
+static const uint32_t _reg_PHY_CLK_CACS_SLAVE_DELAY_X
+ [_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = {
_reg_PHY_ADR0_CLK_WR_SLAVE_DELAY,
_reg_PHY_ADR1_CLK_WR_SLAVE_DELAY,
_reg_PHY_ADR2_CLK_WR_SLAVE_DELAY,
@@ -226,9 +226,7 @@
_reg_PHY_GRP_SLAVE_DELAY_3
};
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
+/* Prototypes */
static inline uint32_t vch_nxt(uint32_t pos);
static void cpg_write_32(uint32_t a, uint32_t v);
static void pll3_control(uint32_t high);
@@ -249,21 +247,21 @@
static void ddr_setval_ach(uint32_t regdef, uint32_t val);
static void ddr_setval_ach_as(uint32_t regdef, uint32_t val);
static uint32_t ddr_getval(uint32_t ch, uint32_t regdef);
-static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t * p);
-static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t * p);
-static void _tblcopy(uint32_t * to, const uint32_t * from, uint32_t size);
-static void ddrtbl_setval(uint32_t * tbl, uint32_t _regdef, uint32_t val);
-static uint32_t ddrtbl_getval(uint32_t * tbl, uint32_t _regdef);
+static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p);
+static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p);
+static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size);
+static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val);
+static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef);
static uint32_t ddrphy_regif_chk(void);
-static inline void ddrphy_regif_idle();
+static inline void ddrphy_regif_idle(void);
static uint16_t _f_scale(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint32_t ps,
uint16_t cyc);
static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv,
- uint16_t * js2);
+ uint16_t *js2);
static int16_t _f_scale_adj(int16_t ps);
static void ddrtbl_load(void);
static void ddr_config_sub(void);
-static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t * p_swz);
+static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz);
static void ddr_config_sub_h3v1x(void);
static void ddr_config(void);
static void dbsc_regset(void);
@@ -292,20 +290,19 @@
static void adjust_rddqs_latency(void);
static void adjust_wpath_latency(void);
-struct DdrtData {
- int32_t init_temp; /* Initial Temperature (do) */
- uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */
- uint32_t tcomp_cal[4]; /* Temperature compensated io-code (4 is for H3) */
+struct ddrt_data {
+ int32_t init_temp; /* Initial Temperature (do) */
+ uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */
+ uint32_t tcomp_cal[4]; /* Temp. compensated io-code (4 is for H3) */
};
-struct DdrtData tcal;
+
+static struct ddrt_data tcal;
static void pvtcode_update(void);
static void pvtcode_update2(void);
static void ddr_padcal_tcompensate_getinit(uint32_t override);
-/*******************************************************************************
- * load board configuration
- ******************************************************************************/
+/* load board configuration */
#include "boot_init_dram_config.c"
#ifndef DDR_FAST_INIT
@@ -326,9 +323,7 @@
static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
#endif/* DDR_FAST_INIT */
-/*******************************************************************************
- * macro for channel selection loop
- ******************************************************************************/
+/* macro for channel selection loop */
static inline uint32_t vch_nxt(uint32_t pos)
{
uint32_t posn;
@@ -341,19 +336,15 @@
}
#define foreach_vch(ch) \
-for(ch=vch_nxt(0);ch<DRAM_CH_CNT;ch=vch_nxt(ch+1))
+for (ch = vch_nxt(0); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1))
#define foreach_ech(ch) \
-for(ch=0;ch<DRAM_CH_CNT;ch++)
+for (ch = 0; ch < DRAM_CH_CNT; ch++)
-/*******************************************************************************
- * Printing functions
- ******************************************************************************/
+/* Printing functions */
#define MSG_LF(...)
-/*******************************************************************************
- * clock settings, reset control
- ******************************************************************************/
+/* clock settings, reset control */
static void cpg_write_32(uint32_t a, uint32_t v)
{
mmio_write_32(CPG_CPGWPR, ~v);
@@ -362,155 +353,151 @@
static void pll3_control(uint32_t high)
{
- uint32_t dataL, dataDIV, dataMUL, tmpDIV;
+ uint32_t data_l, data_div, data_mul, tmp_div;
if (high) {
- tmpDIV = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
+ tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
(brd_clk * ddr_mul) / 2;
- dataMUL = (((ddr_mul * tmpDIV) - 1) << 24) |
- (brd_clkdiva << 7);
- Pll3Mode = 1;
+ data_mul = ((ddr_mul * tmp_div) - 1) << 24;
+ pll3_mode = 1;
loop_max = 2;
} else {
- tmpDIV = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
+ tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
(brd_clk * ddr0800_mul) / 2;
- dataMUL = (((ddr0800_mul * tmpDIV) - 1) << 24) |
- (brd_clkdiva << 7);
- Pll3Mode = 0;
+ data_mul = ((ddr0800_mul * tmp_div) - 1) << 24;
+ pll3_mode = 0;
loop_max = 8;
}
- switch (tmpDIV) {
+ switch (tmp_div) {
case 1:
- dataDIV = 0;
+ data_div = 0;
break;
case 2:
case 3:
case 4:
- dataDIV = tmpDIV;
+ data_div = tmp_div;
break;
default:
- dataDIV = 6;
- dataMUL = (dataMUL * tmpDIV) / 3;
+ data_div = 6;
+ data_mul = (data_mul * tmp_div) / 3;
break;
}
- dataMUL = dataMUL | (brd_clkdiva << 7);
+ data_mul = data_mul | (brd_clkdiva << 7);
/* PLL3 disable */
- dataL = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT;
- cpg_write_32(CPG_PLLECR, dataL);
+ data_l = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT;
+ cpg_write_32(CPG_PLLECR, data_l);
dsb_sev();
- if ((Prr_Product == PRR_PRODUCT_M3) ||
- ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_20))) {
+ if ((prr_product == PRR_PRODUCT_M3) ||
+ ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_20))) {
/* PLL3 DIV resetting(Lowest value:3) */
- dataL = 0x00030003 | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
- cpg_write_32(CPG_FRQCRD, dataL);
+ data_l = 0x00030003 | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
+ cpg_write_32(CPG_FRQCRD, data_l);
dsb_sev();
/* zb3 clk stop */
- dataL = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR);
- cpg_write_32(CPG_ZB3CKCR, dataL);
+ data_l = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR);
+ cpg_write_32(CPG_ZB3CKCR, data_l);
dsb_sev();
/* PLL3 enable */
- dataL = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
- cpg_write_32(CPG_PLLECR, dataL);
+ data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
+ cpg_write_32(CPG_PLLECR, data_l);
dsb_sev();
do {
- dataL = mmio_read_32(CPG_PLLECR);
- } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
+ data_l = mmio_read_32(CPG_PLLECR);
+ } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
dsb_sev();
/* PLL3 DIV resetting (Highest value:0) */
- dataL = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
- cpg_write_32(CPG_FRQCRD, dataL);
+ data_l = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
+ cpg_write_32(CPG_FRQCRD, data_l);
dsb_sev();
/* DIV SET KICK */
- dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
- cpg_write_32(CPG_FRQCRB, dataL);
+ data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
+ cpg_write_32(CPG_FRQCRB, data_l);
dsb_sev();
/* PLL3 multiplie set */
- cpg_write_32(CPG_PLL3CR, dataMUL);
+ cpg_write_32(CPG_PLL3CR, data_mul);
dsb_sev();
do {
- dataL = mmio_read_32(CPG_PLLECR);
- } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
+ data_l = mmio_read_32(CPG_PLLECR);
+ } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
dsb_sev();
/* PLL3 DIV resetting(Target value) */
- dataL = (dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
- cpg_write_32(CPG_FRQCRD, dataL);
+ data_l = (data_div << 16) | data_div |
+ (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80);
+ cpg_write_32(CPG_FRQCRD, data_l);
dsb_sev();
/* DIV SET KICK */
- dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
- cpg_write_32(CPG_FRQCRB, dataL);
+ data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
+ cpg_write_32(CPG_FRQCRB, data_l);
dsb_sev();
do {
- dataL = mmio_read_32(CPG_PLLECR);
- } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
+ data_l = mmio_read_32(CPG_PLLECR);
+ } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
dsb_sev();
/* zb3 clk start */
- dataL = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR);
- cpg_write_32(CPG_ZB3CKCR, dataL);
+ data_l = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR);
+ cpg_write_32(CPG_ZB3CKCR, data_l);
dsb_sev();
} else { /* H3Ver.3.0/M3N/V3H */
/* PLL3 multiplie set */
- cpg_write_32(CPG_PLL3CR, dataMUL);
+ cpg_write_32(CPG_PLL3CR, data_mul);
dsb_sev();
/* PLL3 DIV set(Target value) */
- dataL = (dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
- cpg_write_32(CPG_FRQCRD, dataL);
+ data_l = (data_div << 16) | data_div |
+ (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80);
+ cpg_write_32(CPG_FRQCRD, data_l);
/* DIV SET KICK */
- dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
- cpg_write_32(CPG_FRQCRB, dataL);
+ data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
+ cpg_write_32(CPG_FRQCRB, data_l);
dsb_sev();
/* PLL3 enable */
- dataL = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
- cpg_write_32(CPG_PLLECR, dataL);
+ data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
+ cpg_write_32(CPG_PLLECR, data_l);
dsb_sev();
do {
- dataL = mmio_read_32(CPG_PLLECR);
- } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
+ data_l = mmio_read_32(CPG_PLLECR);
+ } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
dsb_sev();
}
}
-/*******************************************************************************
- * barrier
- ******************************************************************************/
+/* barrier */
static inline void dsb_sev(void)
{
__asm__ __volatile__("dsb sy");
}
-/*******************************************************************************
- * DDR memory register access
- ******************************************************************************/
+/* DDR memory register access */
static void wait_dbcmd(void)
{
- uint32_t dataL;
+ uint32_t data_l;
/* dummy read */
- dataL = mmio_read_32(DBSC_DBCMD);
+ data_l = mmio_read_32(DBSC_DBCMD);
dsb_sev();
while (1) {
/* wait DBCMD 1=busy, 0=ready */
- dataL = mmio_read_32(DBSC_DBWAIT);
+ data_l = mmio_read_32(DBSC_DBWAIT);
dsb_sev();
- if ((dataL & 0x00000001) == 0x00)
+ if ((data_l & 0x00000001) == 0x00)
break;
}
}
@@ -523,17 +510,15 @@
dsb_sev();
}
-/*******************************************************************************
- * DDRPHY register access (raw)
- ******************************************************************************/
+/* DDRPHY register access (raw) */
static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd)
{
uint32_t val;
uint32_t loop;
val = 0;
- if ((PRR_PRODUCT_M3N != Prr_Product)
- && (PRR_PRODUCT_V3H != Prr_Product)) {
+ if ((prr_product != PRR_PRODUCT_M3N) &&
+ (prr_product != PRR_PRODUCT_V3H)) {
mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
dsb_sev();
@@ -579,8 +564,8 @@
uint32_t val;
uint32_t loop;
- if ((PRR_PRODUCT_M3N != Prr_Product)
- && (PRR_PRODUCT_V3H != Prr_Product)) {
+ if ((prr_product != PRR_PRODUCT_M3N) &&
+ (prr_product != PRR_PRODUCT_V3H)) {
mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
dsb_sev();
for (loop = 0; loop < loop_max; loop++) {
@@ -628,8 +613,8 @@
uint32_t val;
uint32_t loop;
- if ((PRR_PRODUCT_M3N != Prr_Product)
- && (PRR_PRODUCT_V3H != Prr_Product)) {
+ if ((prr_product != PRR_PRODUCT_M3N) &&
+ (prr_product != PRR_PRODUCT_V3H)) {
foreach_vch(ch) {
mmio_write_32(DBSC_DBPDRGA(ch), regadd);
dsb_sev();
@@ -653,7 +638,7 @@
}
}
-static inline void ddrphy_regif_idle()
+static inline void ddrphy_regif_idle(void)
{
uint32_t val;
@@ -662,22 +647,20 @@
(void)val;
}
-/*******************************************************************************
- * DDRPHY register access (field modify)
- ******************************************************************************/
+/* DDRPHY register access (field modify) */
static inline uint32_t ddr_regdef(uint32_t _regdef)
{
- return pDDR_REGDEF_TBL[_regdef];
+ return p_ddr_regdef_tbl[_regdef];
}
static inline uint32_t ddr_regdef_adr(uint32_t _regdef)
{
- return DDR_REGDEF_ADR(pDDR_REGDEF_TBL[_regdef]);
+ return DDR_REGDEF_ADR(p_ddr_regdef_tbl[_regdef]);
}
static inline uint32_t ddr_regdef_lsb(uint32_t _regdef)
{
- return DDR_REGDEF_LSB(pDDR_REGDEF_TBL[_regdef]);
+ return DDR_REGDEF_LSB(p_ddr_regdef_tbl[_regdef]);
}
static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
@@ -759,7 +742,7 @@
return ddr_getval_s(ch, 0, regdef);
}
-static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t * p)
+static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p)
{
uint32_t ch;
@@ -768,22 +751,20 @@
return p[0];
}
-static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t * p)
+static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p)
{
uint32_t ch, slice;
uint32_t *pp;
pp = p;
foreach_vch(ch)
- for (slice = 0; slice < SLICE_CNT; slice++)
- *pp++ = ddr_getval_s(ch, slice, regdef);
+ for (slice = 0; slice < SLICE_CNT; slice++)
+ *pp++ = ddr_getval_s(ch, slice, regdef);
return p[0];
}
-/*******************************************************************************
- * handling functions for setteing ddrphy value table
- ******************************************************************************/
-static void _tblcopy(uint32_t * to, const uint32_t * from, uint32_t size)
+/* handling functions for setteing ddrphy value table */
+static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size)
{
uint32_t i;
@@ -792,7 +773,7 @@
}
}
-static void ddrtbl_setval(uint32_t * tbl, uint32_t _regdef, uint32_t val)
+static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val)
{
uint32_t adr;
uint32_t lsb;
@@ -822,7 +803,7 @@
tbl[adr & adrmsk] = tmp;
}
-static uint32_t ddrtbl_getval(uint32_t * tbl, uint32_t _regdef)
+static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef)
{
uint32_t adr;
uint32_t lsb;
@@ -853,9 +834,7 @@
return tmp;
}
-/*******************************************************************************
- * DDRPHY register access handling
- ******************************************************************************/
+/* DDRPHY register access handling */
static uint32_t ddrphy_regif_chk(void)
{
uint32_t tmp_ach[DRAM_CH_CNT];
@@ -863,49 +842,56 @@
uint32_t err;
uint32_t PI_VERSION_CODE;
- if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
- || (Prr_Product == PRR_PRODUCT_M3)) {
- PI_VERSION_CODE = 0x2041; /* H3 Ver.1.x/M3-W */
+ if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) ||
+ (prr_product == PRR_PRODUCT_M3)) {
+ PI_VERSION_CODE = 0x2041; /* H3 Ver.1.x/M3-W */
} else {
- PI_VERSION_CODE = 0x2040; /* H3 Ver.2.0 or later/M3-N/V3H */
+ PI_VERSION_CODE = 0x2040; /* H3 Ver.2.0 or later/M3-N/V3H */
}
- ddr_getval_ach(_reg_PI_VERSION, (uint32_t *) tmp_ach);
+ ddr_getval_ach(_reg_PI_VERSION, (uint32_t *)tmp_ach);
err = 0;
foreach_vch(ch) {
- if (PI_VERSION_CODE != tmp_ach[ch])
+ if (tmp_ach[ch] != PI_VERSION_CODE)
err = 1;
}
return err;
}
-/*******************************************************************************
- * functions and parameters for timing setting
- ******************************************************************************/
+/* functions and parameters for timing setting */
struct _jedec_spec1 {
uint16_t fx3;
- uint8_t RLwoDBI;
- uint8_t RLwDBI;
+ uint8_t rlwodbi;
+ uint8_t rlwdbi;
uint8_t WL;
- uint8_t nWR;
- uint8_t nRTP;
+ uint8_t nwr;
+ uint8_t nrtp;
uint8_t MR1;
uint8_t MR2;
};
+
#define JS1_USABLEC_SPEC_LO 2
#define JS1_USABLEC_SPEC_HI 5
#define JS1_FREQ_TBL_NUM 8
-#define JS1_MR1(f) (0x04 | ((f)<<4))
-#define JS1_MR2(f) (0x00 | ((f)<<3) | (f))
+#define JS1_MR1(f) (0x04 | ((f) << 4))
+#define JS1_MR2(f) (0x00 | ((f) << 3) | (f))
const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = {
- { 800, 6, 6, 4, 6, 8, JS1_MR1(0), JS1_MR2(0)|0x40 }, /* 533.333Mbps */
- { 1600, 10, 12, 8, 10, 8, JS1_MR1(1), JS1_MR2(1)|0x40 }, /* 1066.666Mbps */
- { 2400, 14, 16, 12, 16, 8, JS1_MR1(2), JS1_MR2(2)|0x40 }, /* 1600.000Mbps */
- { 3200, 20, 22, 10, 20, 8, JS1_MR1(3), JS1_MR2(3) }, /* 2133.333Mbps */
- { 4000, 24, 28, 12, 24, 10, JS1_MR1(4), JS1_MR2(4) }, /* 2666.666Mbps */
- { 4800, 28, 32, 14, 30, 12, JS1_MR1(5), JS1_MR2(5) }, /* 3200.000Mbps */
- { 5600, 32, 36, 16, 34, 14, JS1_MR1(6), JS1_MR2(6) }, /* 3733.333Mbps */
- { 6400, 36, 40, 18, 40, 16, JS1_MR1(7), JS1_MR2(7) } /* 4266.666Mbps */
+ /* 533.333Mbps */
+ { 800, 6, 6, 4, 6, 8, JS1_MR1(0), JS1_MR2(0) | 0x40 },
+ /* 1066.666Mbps */
+ { 1600, 10, 12, 8, 10, 8, JS1_MR1(1), JS1_MR2(1) | 0x40 },
+ /* 1600.000Mbps */
+ { 2400, 14, 16, 12, 16, 8, JS1_MR1(2), JS1_MR2(2) | 0x40 },
+ /* 2133.333Mbps */
+ { 3200, 20, 22, 10, 20, 8, JS1_MR1(3), JS1_MR2(3) },
+ /* 2666.666Mbps */
+ { 4000, 24, 28, 12, 24, 10, JS1_MR1(4), JS1_MR2(4) },
+ /* 3200.000Mbps */
+ { 4800, 28, 32, 14, 30, 12, JS1_MR1(5), JS1_MR2(5) },
+ /* 3733.333Mbps */
+ { 5600, 32, 36, 16, 34, 14, JS1_MR1(6), JS1_MR2(6) },
+ /* 4266.666Mbps */
+ { 6400, 36, 40, 18, 40, 16, JS1_MR1(7), JS1_MR2(7) }
};
struct _jedec_spec2 {
@@ -913,34 +899,34 @@
uint16_t cyc;
};
-#define JS2_tSR 0
-#define JS2_tXP 1
-#define JS2_tRTP 2
-#define JS2_tRCD 3
-#define JS2_tRPpb 4
-#define JS2_tRPab 5
-#define JS2_tRAS 6
-#define JS2_tWR 7
-#define JS2_tWTR 8
-#define JS2_tRRD 9
-#define JS2_tPPD 10
-#define JS2_tFAW 11
-#define JS2_tDQSCK 12
-#define JS2_tCKEHCMD 13
-#define JS2_tCKELCMD 14
-#define JS2_tCKELPD 15
-#define JS2_tMRR 16
-#define JS2_tMRW 17
-#define JS2_tMRD 18
-#define JS2_tZQCALns 19
-#define JS2_tZQLAT 20
-#define JS2_tIEdly 21
+#define js2_tsr 0
+#define js2_txp 1
+#define js2_trtp 2
+#define js2_trcd 3
+#define js2_trppb 4
+#define js2_trpab 5
+#define js2_tras 6
+#define js2_twr 7
+#define js2_twtr 8
+#define js2_trrd 9
+#define js2_tppd 10
+#define js2_tfaw 11
+#define js2_tdqsck 12
+#define js2_tckehcmd 13
+#define js2_tckelcmd 14
+#define js2_tckelpd 15
+#define js2_tmrr 16
+#define js2_tmrw 17
+#define js2_tmrd 18
+#define js2_tzqcalns 19
+#define js2_tzqlat 20
+#define js2_tiedly 21
#define JS2_TBLCNT 22
-#define JS2_tRCpb (JS2_TBLCNT)
-#define JS2_tRCab (JS2_TBLCNT+1)
-#define JS2_tRFCab (JS2_TBLCNT+2)
-#define JS2_CNT (JS2_TBLCNT+3)
+#define js2_trcpb (JS2_TBLCNT)
+#define js2_trcab (JS2_TBLCNT + 1)
+#define js2_trfcab (JS2_TBLCNT + 2)
+#define JS2_CNT (JS2_TBLCNT + 3)
#ifndef JS2_DERATE
#define JS2_DERATE 0
@@ -992,10 +978,10 @@
/*tZQCALns*/ {1000 * 10, 0},
/*tZQLAT*/ {30000, 10},
/*tIEdly*/ {12500, 0}
- }
+ }
};
-const uint16_t jedec_spec2_tRFC_ab[7] = {
+const uint16_t jedec_spec2_trfc_ab[7] = {
/* 4Gb, 6Gb, 8Gb,12Gb, 16Gb, 24Gb(non), 32Gb(non) */
130, 180, 180, 280, 280, 560, 560
};
@@ -1011,18 +997,18 @@
uint32_t tmp;
uint32_t div;
- tmp = (((uint32_t) (ps) + 9) / 10) * ddr_mbps;
+ tmp = (((uint32_t)(ps) + 9) / 10) * ddr_mbps;
div = tmp / (200000 * ddr_mbpsdiv);
if (tmp != (div * 200000 * ddr_mbpsdiv))
div = div + 1;
if (div > cyc)
- return (uint16_t) div;
+ return (uint16_t)div;
return cyc;
}
static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv,
- uint16_t * js2)
+ uint16_t *js2)
{
int i;
@@ -1032,8 +1018,8 @@
jedec_spec2[JS2_DERATE][i].cyc);
}
- js2[JS2_tRCpb] = js2[JS2_tRAS] + js2[JS2_tRPpb];
- js2[JS2_tRCab] = js2[JS2_tRAS] + js2[JS2_tRPab];
+ js2[js2_trcpb] = js2[js2_tras] + js2[js2_trppb];
+ js2[js2_trcab] = js2[js2_tras] + js2[js2_trpab];
}
/* scaler for DELAY value */
@@ -1041,19 +1027,19 @@
{
int32_t tmp;
/*
- tmp = (int32_t)512 * ps * ddr_mbps /2 / ddr_mbpsdiv / 1000 / 1000;
- = ps * ddr_mbps /2 / ddr_mbpsdiv *512 / 8 / 8 / 125 / 125
- = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125
+ * tmp = (int32_t)512 * ps * ddr_mbps /2 / ddr_mbpsdiv / 1000 / 1000;
+ * = ps * ddr_mbps /2 / ddr_mbpsdiv *512 / 8 / 8 / 125 / 125
+ * = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125
*/
tmp =
- (int32_t) 4 *(int32_t) ps *(int32_t) ddr_mbps /
- (int32_t) ddr_mbpsdiv;
- tmp = (int32_t) tmp / (int32_t) 15625;
+ (int32_t)4 * (int32_t)ps * (int32_t)ddr_mbps /
+ (int32_t)ddr_mbpsdiv;
+ tmp = (int32_t)tmp / (int32_t)15625;
- return (int16_t) tmp;
+ return (int16_t)tmp;
}
-const uint32_t _reg_PI_MR1_DATA_Fx_CSx[2][CSAB_CNT] = {
+static const uint32_t reg_pi_mr1_data_fx_csx[2][CSAB_CNT] = {
{
_reg_PI_MR1_DATA_F0_0,
_reg_PI_MR1_DATA_F0_1,
@@ -1066,7 +1052,7 @@
_reg_PI_MR1_DATA_F1_3}
};
-const uint32_t _reg_PI_MR2_DATA_Fx_CSx[2][CSAB_CNT] = {
+static const uint32_t reg_pi_mr2_data_fx_csx[2][CSAB_CNT] = {
{
_reg_PI_MR2_DATA_F0_0,
_reg_PI_MR2_DATA_F0_1,
@@ -1079,7 +1065,7 @@
_reg_PI_MR2_DATA_F1_3}
};
-const uint32_t _reg_PI_MR3_DATA_Fx_CSx[2][CSAB_CNT] = {
+static const uint32_t reg_pi_mr3_data_fx_csx[2][CSAB_CNT] = {
{
_reg_PI_MR3_DATA_F0_0,
_reg_PI_MR3_DATA_F0_1,
@@ -1092,7 +1078,7 @@
_reg_PI_MR3_DATA_F1_3}
};
-const uint32_t _reg_PI_MR11_DATA_Fx_CSx[2][CSAB_CNT] = {
+const uint32_t reg_pi_mr11_data_fx_csx[2][CSAB_CNT] = {
{
_reg_PI_MR11_DATA_F0_0,
_reg_PI_MR11_DATA_F0_1,
@@ -1105,7 +1091,7 @@
_reg_PI_MR11_DATA_F1_3}
};
-const uint32_t _reg_PI_MR12_DATA_Fx_CSx[2][CSAB_CNT] = {
+const uint32_t reg_pi_mr12_data_fx_csx[2][CSAB_CNT] = {
{
_reg_PI_MR12_DATA_F0_0,
_reg_PI_MR12_DATA_F0_1,
@@ -1118,7 +1104,7 @@
_reg_PI_MR12_DATA_F1_3}
};
-const uint32_t _reg_PI_MR14_DATA_Fx_CSx[2][CSAB_CNT] = {
+const uint32_t reg_pi_mr14_data_fx_csx[2][CSAB_CNT] = {
{
_reg_PI_MR14_DATA_F0_0,
_reg_PI_MR14_DATA_F0_1,
@@ -1131,14 +1117,14 @@
_reg_PI_MR14_DATA_F1_3}
};
-/*******************************************************************************
+/*
* regif pll w/a ( REGIF H3 Ver.2.0 or later/M3-N/V3H WA )
- *******************************************************************************/
+ */
static void regif_pll_wa(void)
{
uint32_t ch;
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
// PLL setting for PHY : H3 Ver.1.x
reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT),
(0x0064U <<
@@ -1176,17 +1162,20 @@
reg_ddrphy_write_a(ddr_regdef_adr
(_reg_PHY_LP4_BOOT_TOP_PLL_CTRL),
ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_LP4_BOOT_TOP_PLL_CTRL));
+ _reg_PHY_LP4_BOOT_TOP_PLL_CTRL
+ ));
}
reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS),
- _cnf_DDR_PHY_ADR_G_REGSET[ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - DDR_PHY_ADR_G_REGSET_OFS]);
+ _cnf_DDR_PHY_ADR_G_REGSET
+ [ddr_regdef_adr(_reg_PHY_LPDDR3_CS) -
+ DDR_PHY_ADR_G_REGSET_OFS]);
/* protect register interface */
ddrphy_regif_idle();
pll3_control(0);
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
/* non */
} else {
reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_DLL_RST_EN),
@@ -1195,9 +1184,7 @@
ddrphy_regif_idle();
}
- /***********************************************************************
- init start
- ***********************************************************************/
+ /* init start */
/* dbdficnt0:
* dfi_dram_clk_disable=1
* dfi_frequency = 0
@@ -1219,52 +1206,47 @@
dsb_sev();
foreach_ech(ch)
- if (((Boardcnf->phyvalid) & (1U << ch)))
- while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f) ;
+ if ((board_cnf->phyvalid) & BIT(ch))
+ while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f)
+ ;
dsb_sev();
}
-/*******************************************************************************
- * load table data into DDR registers
- ******************************************************************************/
+/* load table data into DDR registers */
static void ddrtbl_load(void)
{
uint32_t i;
uint32_t slice;
uint32_t csab;
uint32_t adr;
- uint32_t dataL;
+ uint32_t data_l;
uint32_t tmp[3];
uint16_t dataS;
- /***********************************************************************
- TIMING REGISTERS
- ***********************************************************************/
+ /* TIMING REGISTERS */
/* search jedec_spec1 index */
for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1; i++) {
if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U)
break;
}
- if (JS1_USABLEC_SPEC_HI < i)
+ if (i > JS1_USABLEC_SPEC_HI)
js1_ind = JS1_USABLEC_SPEC_HI;
else
js1_ind = i;
- if (Boardcnf->dbi_en)
- RL = js1[js1_ind].RLwDBI;
+ if (board_cnf->dbi_en)
+ RL = js1[js1_ind].rlwdbi;
else
- RL = js1[js1_ind].RLwoDBI;
+ RL = js1[js1_ind].rlwodbi;
WL = js1[js1_ind].WL;
/* calculate jedec_spec2 */
_f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2);
- /***********************************************************************
- PREPARE TBL
- ***********************************************************************/
- if (Prr_Product == PRR_PRODUCT_H3) {
- if (Prr_Cut <= PRR_PRODUCT_11) {
+ /* PREPARE TBL */
+ if (prr_product == PRR_PRODUCT_H3) {
+ if (prr_cut <= PRR_PRODUCT_11) {
/* H3 Ver.1.x */
_tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
DDR_PHY_SLICE_REGSET_H3,
@@ -1340,7 +1322,7 @@
DDR_PHY_ADR_I_NUM = 0;
}
- } else if (Prr_Product == PRR_PRODUCT_M3) {
+ } else if (prr_product == PRR_PRODUCT_M3) {
/* M3-W */
_tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
DDR_PHY_SLICE_REGSET_M3, DDR_PHY_SLICE_REGSET_NUM_M3);
@@ -1403,32 +1385,26 @@
DDR_PHY_ADR_I_NUM = 2;
}
- /***********************************************************************
- PLL CODE CHANGE
- ***********************************************************************/
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_11)) {
+ /* PLL CODE CHANGE */
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) {
ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL,
0x1142);
ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET,
_reg_PHY_LP4_BOOT_PLL_CTRL, 0x1142);
}
- /***********************************************************************
- on fly gate adjust
- ***********************************************************************/
- if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut == PRR_PRODUCT_10)) {
+ /* on fly gate adjust */
+ if ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10)) {
ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
_reg_ON_FLY_GATE_ADJUST_EN, 0x00);
}
- /***********************************************************************
- Adjust PI parameters
- ***********************************************************************/
+ /* Adjust PI parameters */
#ifdef _def_LPDDR4_ODT
for (i = 0; i < 2; i++) {
for (csab = 0; csab < CSAB_CNT; csab++) {
ddrtbl_setval(_cnf_DDR_PI_REGSET,
- _reg_PI_MR11_DATA_Fx_CSx[i][csab],
+ reg_pi_mr11_data_fx_csx[i][csab],
_def_LPDDR4_ODT);
}
}
@@ -1438,43 +1414,43 @@
for (i = 0; i < 2; i++) {
for (csab = 0; csab < CSAB_CNT; csab++) {
ddrtbl_setval(_cnf_DDR_PI_REGSET,
- _reg_PI_MR12_DATA_Fx_CSx[i][csab],
+ reg_pi_mr12_data_fx_csx[i][csab],
_def_LPDDR4_VREFCA);
}
}
#endif /* _def_LPDDR4_VREFCA */
- if ((Prr_Product == PRR_PRODUCT_M3N)
- || (Prr_Product == PRR_PRODUCT_V3H)) {
- js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U;
- if (js2[JS2_tIEdly] > (RL))
- js2[JS2_tIEdly] = RL;
- } else if ((Prr_Product == PRR_PRODUCT_H3)
- && (Prr_Cut > PRR_PRODUCT_11)) {
- js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U;
- } else if ((Prr_Product == PRR_PRODUCT_H3)
- && (Prr_Cut <= PRR_PRODUCT_11)) {
- js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0);
+ if ((prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
+ js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U;
+ if (js2[js2_tiedly] > (RL))
+ js2[js2_tiedly] = RL;
+ } else if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut > PRR_PRODUCT_11)) {
+ js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U;
+ } else if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) {
+ js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0);
}
- if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
- || (Prr_Product == PRR_PRODUCT_M3N)
- || (Prr_Product == PRR_PRODUCT_V3H)) {
- if ((js2[JS2_tIEdly]) >= 0x1e)
+ if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) ||
+ (prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
+ if ((js2[js2_tiedly]) >= 0x1e)
dataS = 0x1e;
else
- dataS = js2[JS2_tIEdly];
+ dataS = js2[js2_tiedly];
} else {
- if ((js2[JS2_tIEdly]) >= 0x0e)
+ if ((js2[js2_tiedly]) >= 0x0e)
dataS = 0x0e;
else
- dataS = js2[JS2_tIEdly];
+ dataS = js2[js2_tiedly];
}
ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS);
ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY,
(dataS - 2));
- if ((Prr_Product == PRR_PRODUCT_M3N)
- || (Prr_Product == PRR_PRODUCT_V3H)) {
+ if ((prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
_reg_PHY_RDDATA_EN_OE_DLY, dataS);
}
@@ -1482,14 +1458,14 @@
if (ddrtbl_getval
(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) {
- dataL = WL - 1;
+ data_l = WL - 1;
} else {
- dataL = WL;
+ data_l = WL;
}
- ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, dataL - 2);
- ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, dataL);
+ ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, data_l - 2);
+ ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, data_l);
- if (Boardcnf->dbi_en) {
+ if (board_cnf->dbi_en) {
ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE,
0x01);
ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
@@ -1503,42 +1479,36 @@
tmp[0] = js1[js1_ind].MR1;
tmp[1] = js1[js1_ind].MR2;
- dataL = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0);
- if (Boardcnf->dbi_en)
- tmp[2] = dataL | 0xc0;
+ data_l = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0);
+ if (board_cnf->dbi_en)
+ tmp[2] = data_l | 0xc0;
else
- tmp[2] = dataL & (~0xc0);
+ tmp[2] = data_l & (~0xc0);
for (i = 0; i < 2; i++) {
for (csab = 0; csab < CSAB_CNT; csab++) {
ddrtbl_setval(_cnf_DDR_PI_REGSET,
- _reg_PI_MR1_DATA_Fx_CSx[i][csab], tmp[0]);
+ reg_pi_mr1_data_fx_csx[i][csab], tmp[0]);
ddrtbl_setval(_cnf_DDR_PI_REGSET,
- _reg_PI_MR2_DATA_Fx_CSx[i][csab], tmp[1]);
+ reg_pi_mr2_data_fx_csx[i][csab], tmp[1]);
ddrtbl_setval(_cnf_DDR_PI_REGSET,
- _reg_PI_MR3_DATA_Fx_CSx[i][csab], tmp[2]);
+ reg_pi_mr3_data_fx_csx[i][csab], tmp[2]);
}
}
- /***********************************************************************
- DDRPHY INT START
- ***********************************************************************/
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+ /* DDRPHY INT START */
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
/* non */
} else {
regif_pll_wa();
}
- /***********************************************************************
- FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety)
- ***********************************************************************/
+ /* FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) */
reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
- (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
+ BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01);
- /***********************************************************************
- SET DATA SLICE TABLE
- ***********************************************************************/
+ /* SET DATA SLICE TABLE */
for (slice = 0; slice < SLICE_CNT; slice++) {
adr =
DDR_PHY_SLICE_REGSET_OFS +
@@ -1549,24 +1519,23 @@
}
}
- /***********************************************************************
- SET ADR SLICE TABLE
- ***********************************************************************/
+ /* SET ADR SLICE TABLE */
adr = DDR_PHY_ADR_V_REGSET_OFS;
for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) {
reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]);
}
- if (((Prr_Product == PRR_PRODUCT_M3)
- || (Prr_Product == PRR_PRODUCT_M3N)) &&
- ((0x00ffffff & (uint32_t)((Boardcnf->ch[0].ca_swap) >> 40))
+ if (((prr_product == PRR_PRODUCT_M3) ||
+ (prr_product == PRR_PRODUCT_M3N)) &&
+ ((0x00ffffff & (uint32_t)((board_cnf->ch[0].ca_swap) >> 40))
!= 0x00)) {
adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE;
for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) {
reg_ddrphy_write_a(adr + i,
_cnf_DDR_PHY_ADR_V_REGSET[i]);
}
- ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_ADR_DISABLE, 0x02);
+ ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_ADR_DISABLE, 0x02);
DDR_PHY_ADR_I_NUM -= 1;
ddr_phycaslice = 1;
@@ -1574,7 +1543,7 @@
for (i = 0; i < 2; i++) {
for (csab = 0; csab < CSAB_CNT; csab++) {
ddrtbl_setval(_cnf_DDR_PI_REGSET,
- _reg_PI_MR11_DATA_Fx_CSx[i][csab],
+ reg_pi_mr11_data_fx_csx[i][csab],
0x66);
}
}
@@ -1596,45 +1565,38 @@
}
}
- /***********************************************************************
- SET ADRCTRL SLICE TABLE
- ***********************************************************************/
+ /* SET ADRCTRL SLICE TABLE */
adr = DDR_PHY_ADR_G_REGSET_OFS;
for (i = 0; i < DDR_PHY_ADR_G_REGSET_NUM; i++) {
reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_G_REGSET[i]);
}
- /***********************************************************************
- SET PI REGISTERS
- ***********************************************************************/
+ /* SET PI REGISTERS */
adr = DDR_PI_REGSET_OFS;
for (i = 0; i < DDR_PI_REGSET_NUM; i++) {
reg_ddrphy_write_a(adr + i, _cnf_DDR_PI_REGSET[i]);
}
}
-/*******************************************************************************
- * CONFIGURE DDR REGISTERS
- ******************************************************************************/
+/* CONFIGURE DDR REGISTERS */
static void ddr_config_sub(void)
{
uint32_t i;
uint32_t ch, slice;
- uint32_t dataL;
+ uint32_t data_l;
uint32_t tmp;
uint8_t high_byte[SLICE_CNT];
const uint32_t _par_CALVL_DEVICE_MAP = 1;
+
foreach_vch(ch) {
- /***********************************************************************
- BOARD SETTINGS (DQ,DM,VREF_DRIVING)
- ***********************************************************************/
+ /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */
for (slice = 0; slice < SLICE_CNT; slice++) {
high_byte[slice] =
- (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) % 2;
+ (board_cnf->ch[ch].dqs_swap >> (4 * slice)) % 2;
ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0,
- Boardcnf->ch[ch].dq_swap[slice]);
+ board_cnf->ch[ch].dq_swap[slice]);
ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1,
- Boardcnf->ch[ch].dm_swap[slice]);
+ board_cnf->ch[ch].dm_swap[slice]);
if (high_byte[slice]) {
/* HIGHER 16 BYTE */
ddr_setval_s(ch, slice,
@@ -1648,110 +1610,118 @@
}
}
- /***********************************************************************
- BOARD SETTINGS (CA,ADDR_SEL)
- ***********************************************************************/
- dataL = (0x00ffffff & (uint32_t)(Boardcnf->ch[ch].ca_swap)) |
+ /* BOARD SETTINGS (CA,ADDR_SEL) */
+ data_l = (0x00ffffff & (uint32_t)(board_cnf->ch[ch].ca_swap)) |
0x00888888;
/* --- ADR_CALVL_SWIZZLE --- */
- if (Prr_Product == PRR_PRODUCT_M3) {
- ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, dataL);
+ if (prr_product == PRR_PRODUCT_M3) {
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l);
ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0,
0x00000000);
- ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, dataL);
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l);
ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1,
0x00000000);
ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP,
_par_CALVL_DEVICE_MAP);
} else {
- ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, dataL);
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l);
ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000);
ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP,
_par_CALVL_DEVICE_MAP);
}
/* --- ADR_ADDR_SEL --- */
- if ((Prr_Product == PRR_PRODUCT_H3)
- && (Prr_Cut > PRR_PRODUCT_11)) {
- dataL = 0x00FFFFFF & Boardcnf->ch[ch].ca_swap;
+ if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut > PRR_PRODUCT_11)) {
+ data_l = 0x00FFFFFF & board_cnf->ch[ch].ca_swap;
} else {
- dataL = 0;
- tmp = Boardcnf->ch[ch].ca_swap;
+ data_l = 0;
+ tmp = board_cnf->ch[ch].ca_swap;
for (i = 0; i < 6; i++) {
- dataL |= ((tmp & 0x0f) << (i * 5));
+ data_l |= ((tmp & 0x0f) << (i * 5));
tmp = tmp >> 4;
}
}
- ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, dataL);
+ ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, data_l);
if (ddr_phycaslice == 1) {
/* ----------- adr slice2 swap ----------- */
- tmp = (uint32_t)((Boardcnf->ch[ch].ca_swap) >> 40);
- dataL = (tmp & 0x00ffffff) | 0x00888888;
+ tmp = (uint32_t)((board_cnf->ch[ch].ca_swap) >> 40);
+ data_l = (tmp & 0x00ffffff) | 0x00888888;
/* --- ADR_CALVL_SWIZZLE --- */
- if (Prr_Product == PRR_PRODUCT_M3) {
- ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_0, dataL);
- ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_0,
+ if (prr_product == PRR_PRODUCT_M3) {
+ ddr_setval_s(ch, 2,
+ _reg_PHY_ADR_CALVL_SWIZZLE0_0,
+ data_l);
+ ddr_setval_s(ch, 2,
+ _reg_PHY_ADR_CALVL_SWIZZLE1_0,
0x00000000);
- ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_1, dataL);
- ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_1,
+ ddr_setval_s(ch, 2,
+ _reg_PHY_ADR_CALVL_SWIZZLE0_1,
+ data_l);
+ ddr_setval_s(ch, 2,
+ _reg_PHY_ADR_CALVL_SWIZZLE1_1,
0x00000000);
- ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_DEVICE_MAP,
+ ddr_setval_s(ch, 2,
+ _reg_PHY_ADR_CALVL_DEVICE_MAP,
_par_CALVL_DEVICE_MAP);
} else {
- ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0, dataL);
- ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1,
+ ddr_setval_s(ch, 2,
+ _reg_PHY_ADR_CALVL_SWIZZLE0,
+ data_l);
+ ddr_setval_s(ch, 2,
+ _reg_PHY_ADR_CALVL_SWIZZLE1,
0x00000000);
- ddr_setval_s(ch, 2, _reg_PHY_CALVL_DEVICE_MAP,
+ ddr_setval_s(ch, 2,
+ _reg_PHY_CALVL_DEVICE_MAP,
_par_CALVL_DEVICE_MAP);
}
/* --- ADR_ADDR_SEL --- */
- dataL = 0;
+ data_l = 0;
for (i = 0; i < 6; i++) {
- dataL |= ((tmp & 0x0f) << (i * 5));
+ data_l |= ((tmp & 0x0f) << (i * 5));
tmp = tmp >> 4;
}
- ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, dataL);
+ ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, data_l);
}
- /***********************************************************************
- BOARD SETTINGS (BYTE_ORDER_SEL)
- ***********************************************************************/
- if (Prr_Product == PRR_PRODUCT_M3) {
+ /* BOARD SETTINGS (BYTE_ORDER_SEL) */
+ if (prr_product == PRR_PRODUCT_M3) {
/* --- DATA_BYTE_SWAP --- */
- dataL = 0;
- tmp = Boardcnf->ch[ch].dqs_swap;
+ data_l = 0;
+ tmp = board_cnf->ch[ch].dqs_swap;
for (i = 0; i < 4; i++) {
- dataL |= ((tmp & 0x03) << (i * 2));
+ data_l |= ((tmp & 0x03) << (i * 2));
tmp = tmp >> 4;
}
} else {
/* --- DATA_BYTE_SWAP --- */
- dataL = Boardcnf->ch[ch].dqs_swap;
+ data_l = board_cnf->ch[ch].dqs_swap;
ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01);
ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0,
- (dataL) & 0x0f);
+ (data_l) & 0x0f);
ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1,
- (dataL >> 4 * 1) & 0x0f);
+ (data_l >> 4 * 1) & 0x0f);
ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE2,
- (dataL >> 4 * 2) & 0x0f);
+ (data_l >> 4 * 2) & 0x0f);
ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3,
- (dataL >> 4 * 3) & 0x0f);
+ (data_l >> 4 * 3) & 0x0f);
ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x00);
}
- ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, dataL);
+ ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, data_l);
}
}
-static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t * p_swz)
+static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz)
{
uint32_t slice;
uint32_t tmp;
uint32_t tgt;
+
if (ddr_csn / 2) {
tgt = 3;
} else {
@@ -1759,11 +1729,11 @@
}
for (slice = 0; slice < SLICE_CNT; slice++) {
- tmp = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+ tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
if (tgt == tmp)
break;
}
- tmp = 0x00FFFFFF & Boardcnf->ch[ch].ca_swap;
+ tmp = 0x00FFFFFF & board_cnf->ch[ch].ca_swap;
if (slice % 2)
tmp |= 0x00888888;
*p_swz = tmp;
@@ -1772,7 +1742,7 @@
static void ddr_config_sub_h3v1x(void)
{
uint32_t ch, slice;
- uint32_t dataL;
+ uint32_t data_l;
uint32_t tmp;
uint8_t high_byte[SLICE_CNT];
uint32_t ca_swizzle;
@@ -1789,19 +1759,18 @@
const uint16_t o_mr32_mr40 = 0x5a3c;
foreach_vch(ch) {
- /***********************************************************************
- BOARD SETTINGS (DQ,DM,VREF_DRIVING)
- ***********************************************************************/
+ /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */
csmap = 0;
for (slice = 0; slice < SLICE_CNT; slice++) {
- tmp = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+ tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) &
+ 0x0f;
high_byte[slice] = tmp % 2;
if (tmp == 1 && (slice >= 2))
csmap |= 0x05;
if (tmp == 3 && (slice >= 2))
csmap |= 0x50;
ddr_setval_s(ch, slice, _reg_PHY_DQ_SWIZZLING,
- Boardcnf->ch[ch].dq_swap[slice]);
+ board_cnf->ch[ch].dq_swap[slice]);
if (high_byte[slice]) {
/* HIGHER 16 BYTE */
ddr_setval_s(ch, slice,
@@ -1814,10 +1783,8 @@
0x01);
}
}
- /***********************************************************************
- BOARD SETTINGS (CA,ADDR_SEL)
- ***********************************************************************/
- ca = 0x00FFFFFF & Boardcnf->ch[ch].ca_swap;
+ /* BOARD SETTINGS (CA,ADDR_SEL) */
+ ca = 0x00FFFFFF & board_cnf->ch[ch].ca_swap;
ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, ca);
ddr_setval(ch, _reg_PHY_CALVL_CS_MAP, csmap);
@@ -1840,7 +1807,7 @@
else
o_inv = o_mr15;
- tmp = Boardcnf->ch[ch].dq_swap[slice];
+ tmp = board_cnf->ch[ch].dq_swap[slice];
inv = 0;
j = 0;
for (bit_soc = 0; bit_soc < 8; bit_soc++) {
@@ -1849,13 +1816,13 @@
if (o_inv & (1U << bit_mem))
inv |= (1U << bit_soc);
}
- dataL = o_mr32_mr40;
+ data_l = o_mr32_mr40;
if (!high_byte[slice])
- dataL |= (inv << 24);
+ data_l |= (inv << 24);
if (high_byte[slice])
- dataL |= (inv << 16);
+ data_l |= (inv << 16);
ddr_setval_s(ch, slice, _reg_PHY_LP4_RDLVL_PATT8,
- dataL);
+ data_l);
}
}
}
@@ -1864,7 +1831,7 @@
{
int32_t i;
uint32_t ch, slice;
- uint32_t dataL;
+ uint32_t data_l;
uint32_t tmp;
int8_t _adj;
int16_t adj;
@@ -1875,23 +1842,19 @@
} patt;
uint16_t patm;
- /***********************************************************************
- configure ddrphy registers
- ***********************************************************************/
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+ /* configure ddrphy registers */
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
ddr_config_sub_h3v1x();
- } else {
- ddr_config_sub(); /* H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */
+ } else { /* H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */
+ ddr_config_sub();
}
- /***********************************************************************
- WDQ_USER_PATT
- ***********************************************************************/
+ /* WDQ_USER_PATT */
foreach_vch(ch) {
for (slice = 0; slice < SLICE_CNT; slice++) {
patm = 0;
for (i = 0; i < 16; i++) {
- tmp = Boardcnf->ch[ch].wdqlvl_patt[i];
+ tmp = board_cnf->ch[ch].wdqlvl_patt[i];
patt.ui8[i] = tmp & 0xff;
if (tmp & 0x100)
patm |= (1U << i);
@@ -1908,119 +1871,112 @@
}
}
- /***********************************************************************
- CACS DLY
- ***********************************************************************/
- dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj);
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 0x00U);
+ /* CACS DLY */
+ data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj);
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
+ 0x00U);
foreach_vch(ch) {
- for (i = 0; i < (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4); i++) {
- adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]);
+ for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4; i++) {
+ adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET,
_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
- dataL + adj);
+ data_l + adj);
reg_ddrphy_write(ch,
- ddr_regdef_adr(
- _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]),
- _cnf_DDR_PHY_ADR_V_REGSET[
- ddr_regdef_adr(
- _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
+ ddr_regdef_adr
+ (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]),
+ _cnf_DDR_PHY_ADR_V_REGSET
+ [ddr_regdef_adr
+ (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
DDR_PHY_ADR_V_REGSET_OFS]);
}
for (i = (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4);
i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
- adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]);
+ adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET,
_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
- dataL + adj);
+ data_l + adj);
reg_ddrphy_write(ch,
- ddr_regdef_adr(
- _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]),
- _cnf_DDR_PHY_ADR_G_REGSET[
- ddr_regdef_adr(
- _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
+ ddr_regdef_adr
+ (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]),
+ _cnf_DDR_PHY_ADR_G_REGSET
+ [ddr_regdef_adr
+ (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
DDR_PHY_ADR_G_REGSET_OFS]);
}
if (ddr_phycaslice == 1) {
for (i = 0; i < 6; i++) {
- adj = _f_scale_adj(
- Boardcnf->ch[ch].cacs_adj[
- i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
+ adj = _f_scale_adj
+ (board_cnf->ch[ch].cacs_adj
+ [i +
+ _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET,
- _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
- dataL + adj);
+ _reg_PHY_CLK_CACS_SLAVE_DELAY_X
+ [i],
+ data_l + adj);
reg_ddrphy_write(ch,
- ddr_regdef_adr(
- _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) +
+ ddr_regdef_adr
+ (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) +
0x0100,
- _cnf_DDR_PHY_ADR_V_REGSET[
- ddr_regdef_adr(
- _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
+ _cnf_DDR_PHY_ADR_V_REGSET
+ [ddr_regdef_adr
+ (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
DDR_PHY_ADR_V_REGSET_OFS]);
}
}
}
reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
- (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
+ BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
- /***********************************************************************
- WDQDM DLY
- ***********************************************************************/
- dataL = Boardcnf->dqdm_dly_w;
+ /* WDQDM DLY */
+ data_l = board_cnf->dqdm_dly_w;
foreach_vch(ch) {
for (slice = 0; slice < SLICE_CNT; slice++) {
for (i = 0; i <= 8; i++) {
dq = slice * 8 + i;
if (i == 8)
- _adj = Boardcnf->ch[ch].dm_adj_w[slice];
+ _adj = board_cnf->ch[ch].dm_adj_w[slice];
else
- _adj = Boardcnf->ch[ch].dq_adj_w[dq];
+ _adj = board_cnf->ch[ch].dq_adj_w[dq];
adj = _f_scale_adj(_adj);
ddr_setval_s(ch, slice,
_reg_PHY_CLK_WRX_SLAVE_DELAY[i],
- dataL + adj);
+ data_l + adj);
}
}
}
- /***********************************************************************
- RDQDM DLY
- ***********************************************************************/
- dataL = Boardcnf->dqdm_dly_r;
+ /* RDQDM DLY */
+ data_l = board_cnf->dqdm_dly_r;
foreach_vch(ch) {
for (slice = 0; slice < SLICE_CNT; slice++) {
for (i = 0; i <= 8; i++) {
dq = slice * 8 + i;
if (i == 8)
- _adj = Boardcnf->ch[ch].dm_adj_r[slice];
+ _adj = board_cnf->ch[ch].dm_adj_r[slice];
else
- _adj = Boardcnf->ch[ch].dq_adj_r[dq];
+ _adj = board_cnf->ch[ch].dq_adj_r[dq];
adj = _f_scale_adj(_adj);
ddr_setval_s(ch, slice,
_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY
- [i], dataL + adj);
+ [i], data_l + adj);
ddr_setval_s(ch, slice,
_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY
- [i], dataL + adj);
+ [i], data_l + adj);
}
}
}
}
-/*******************************************************************************
- * DBSC register setting functions
- ******************************************************************************/
+/* DBSC register setting functions */
static void dbsc_regset_pre(void)
{
uint32_t ch, csab;
- uint32_t dataL;
+ uint32_t data_l;
- /***********************************************************************
- PRIMARY SETTINGS
- ***********************************************************************/
+ /* PRIMARY SETTINGS */
/* LPDDR4, BL=16, DFI interface */
mmio_write_32(DBSC_DBKIND, 0x0000000a);
mmio_write_32(DBSC_DBBL, 0x00000002);
@@ -2030,30 +1986,33 @@
mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
/* Chanel map (H3 Ver.1.x) */
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11))
mmio_write_32(DBSC_DBSCHCNT1, 0x00001010);
/* DRAM SIZE REGISTER:
* set all ranks as density=0(4Gb) for PHY initialization
*/
- foreach_vch(ch)
- for (csab = 0; csab < 4; csab++)
- mmio_write_32(DBSC_DBMEMCONF(ch, csab), DBMEMCONF_REGD(0));
+ foreach_vch(ch) {
+ for (csab = 0; csab < 4; csab++) {
+ mmio_write_32(DBSC_DBMEMCONF(ch, csab),
+ DBMEMCONF_REGD(0));
+ }
+ }
- if (Prr_Product == PRR_PRODUCT_M3) {
- dataL = 0xe4e4e4e4;
+ if (prr_product == PRR_PRODUCT_M3) {
+ data_l = 0xe4e4e4e4;
foreach_ech(ch) {
if ((ddr_phyvalid & (1U << ch)))
- dataL = (dataL & (~(0x000000FF << (ch * 8))))
- | (((Boardcnf->ch[ch].dqs_swap & 0x0003)
- | ((Boardcnf->ch[ch].dqs_swap & 0x0030)
+ data_l = (data_l & (~(0x000000FF << (ch * 8))))
+ | (((board_cnf->ch[ch].dqs_swap & 0x0003)
+ | ((board_cnf->ch[ch].dqs_swap & 0x0030)
>> 2)
- | ((Boardcnf->ch[ch].dqs_swap & 0x0300)
+ | ((board_cnf->ch[ch].dqs_swap & 0x0300)
>> 4)
- | ((Boardcnf->ch[ch].dqs_swap & 0x3000)
+ | ((board_cnf->ch[ch].dqs_swap & 0x3000)
>> 6)) << (ch * 8));
}
- mmio_write_32(DBSC_DBBSWAP, dataL);
+ mmio_write_32(DBSC_DBBSWAP, data_l);
}
}
@@ -2061,20 +2020,20 @@
{
int32_t i;
uint32_t ch;
- uint32_t dataL;
- uint32_t dataL2;
+ uint32_t data_l;
+ uint32_t data_l2;
uint32_t tmp[4];
/* RFC */
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_20)
- && (max_density == 0)) {
- js2[JS2_tRFCab] =
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_20) &&
+ (max_density == 0)) {
+ js2[js2_trfcab] =
_f_scale(ddr_mbps, ddr_mbpsdiv,
- 1UL * jedec_spec2_tRFC_ab[1] * 1000, 0);
+ 1UL * jedec_spec2_trfc_ab[1] * 1000, 0);
} else {
- js2[JS2_tRFCab] =
+ js2[js2_trfcab] =
_f_scale(ddr_mbps, ddr_mbpsdiv,
- 1UL * jedec_spec2_tRFC_ab[max_density] *
+ 1UL * jedec_spec2_trfc_ab[max_density] *
1000, 0);
}
@@ -2088,46 +2047,46 @@
mmio_write_32(DBSC_DBTR(2), 0);
/* DBTR3.TRCD: tRCD */
- mmio_write_32(DBSC_DBTR(3), js2[JS2_tRCD]);
+ mmio_write_32(DBSC_DBTR(3), js2[js2_trcd]);
/* DBTR4.TRPA,TRP: tRPab,tRPpb */
- mmio_write_32(DBSC_DBTR(4), (js2[JS2_tRPab] << 16) | js2[JS2_tRPpb]);
+ mmio_write_32(DBSC_DBTR(4), (js2[js2_trpab] << 16) | js2[js2_trppb]);
/* DBTR5.TRC : use tRCpb */
- mmio_write_32(DBSC_DBTR(5), js2[JS2_tRCpb]);
+ mmio_write_32(DBSC_DBTR(5), js2[js2_trcpb]);
/* DBTR6.TRAS : tRAS */
- mmio_write_32(DBSC_DBTR(6), js2[JS2_tRAS]);
+ mmio_write_32(DBSC_DBTR(6), js2[js2_tras]);
/* DBTR7.TRRD : tRRD */
- mmio_write_32(DBSC_DBTR(7), (js2[JS2_tRRD] << 16) | js2[JS2_tRRD]);
+ mmio_write_32(DBSC_DBTR(7), (js2[js2_trrd] << 16) | js2[js2_trrd]);
/* DBTR8.TFAW : tFAW */
- mmio_write_32(DBSC_DBTR(8), js2[JS2_tFAW]);
+ mmio_write_32(DBSC_DBTR(8), js2[js2_tfaw]);
/* DBTR9.TRDPR : tRTP */
- mmio_write_32(DBSC_DBTR(9), js2[JS2_tRTP]);
+ mmio_write_32(DBSC_DBTR(9), js2[js2_trtp]);
- /* DBTR10.TWR : nWR */
- mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nWR);
+ /* DBTR10.TWR : nwr */
+ mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nwr);
/* DBTR11.TRDWR : RL + tDQSCK + BL/2 + Rounddown(tRPST) - WL + tWPRE */
mmio_write_32(DBSC_DBTR(11),
- RL + js2[JS2_tDQSCK] + (16 / 2) + 1 - WL + 2 + 2);
+ RL + js2[js2_tdqsck] + (16 / 2) + 1 - WL + 2 + 2);
/* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */
- dataL = WL + 1 + (16 / 2) + js2[JS2_tWTR];
- mmio_write_32(DBSC_DBTR(12), (dataL << 16) | dataL);
+ data_l = WL + 1 + (16 / 2) + js2[js2_twtr];
+ mmio_write_32(DBSC_DBTR(12), (data_l << 16) | data_l);
/* DBTR13.TRFCAB : tRFCab */
- mmio_write_32(DBSC_DBTR(13), (js2[JS2_tRFCab]));
+ mmio_write_32(DBSC_DBTR(13), (js2[js2_trfcab]));
/* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */
mmio_write_32(DBSC_DBTR(14),
- (js2[JS2_tCKEHCMD] << 16) | (js2[JS2_tCKEHCMD]));
+ (js2[js2_tckehcmd] << 16) | (js2[js2_tckehcmd]));
/* DBTR15.TCKESR,TCKEL : tSR,tCKELPD */
- mmio_write_32(DBSC_DBTR(15), (js2[JS2_tSR] << 16) | (js2[JS2_tCKELPD]));
+ mmio_write_32(DBSC_DBTR(15), (js2[js2_tsr] << 16) | (js2[js2_tckelpd]));
/* DBTR16 */
/* WDQL : tphy_wrlat + tphy_wrdata */
@@ -2150,13 +2109,13 @@
/* WRCSGAP = 5 */
tmp[1] = 5;
/* RDCSLAT = RDLAT_ADJ +2 */
- if (Prr_Product == PRR_PRODUCT_M3) {
+ if (prr_product == PRR_PRODUCT_M3) {
tmp[2] = tmp[3];
} else {
tmp[2] = tmp[3] + 2;
}
/* RDCSGAP = 6 */
- if (Prr_Product == PRR_PRODUCT_M3) {
+ if (prr_product == PRR_PRODUCT_M3) {
tmp[3] = 4;
} else {
tmp[3] = 6;
@@ -2166,7 +2125,7 @@
/* DBTR17.TMODRD,TMOD,TRDMR: tMRR,tMRD,(0) */
mmio_write_32(DBSC_DBTR(17),
- (js2[JS2_tMRR] << 24) | (js2[JS2_tMRD] << 16));
+ (js2[js2_tmrr] << 24) | (js2[js2_tmrd] << 16));
/* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */
mmio_write_32(DBSC_DBTR(18), 0);
@@ -2175,32 +2134,32 @@
mmio_write_32(DBSC_DBTR(19), 0);
/* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */
- dataL = js2[JS2_tRFCab] + js2[JS2_tCKEHCMD];
- mmio_write_32(DBSC_DBTR(20), (dataL << 16) | dataL);
+ data_l = js2[js2_trfcab] + js2[js2_tckehcmd];
+ mmio_write_32(DBSC_DBTR(20), (data_l << 16) | data_l);
/* DBTR21.TCCD */
/* DBTR23.TCCD */
/* H3 Ver.1.0 cannot use TBTR23 feature */
if (ddr_tccd == 8 &&
- !((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_10))
+ !((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_10))
) {
- dataL = 8;
- mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL);
+ data_l = 8;
+ mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
mmio_write_32(DBSC_DBTR(23), 0x00000002);
} else if (ddr_tccd <= 11) {
- dataL = 11;
- mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL);
+ data_l = 11;
+ mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
mmio_write_32(DBSC_DBTR(23), 0x00000000);
} else {
- dataL = ddr_tccd;
- mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL);
+ data_l = ddr_tccd;
+ mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
mmio_write_32(DBSC_DBTR(23), 0x00000000);
}
/* DBTR22.ZQLAT : */
- dataL = js2[JS2_tZQCALns] * 100; /* 1000 * 1000 ps */
- dataL = (dataL << 16) | (js2[JS2_tZQLAT] + 24 + 20);
- mmio_write_32(DBSC_DBTR(22), dataL);
+ data_l = js2[js2_tzqcalns] * 100; /* 1000 * 1000 ps */
+ data_l = (data_l << 16) | (js2[js2_tzqlat] + 24 + 20);
+ mmio_write_32(DBSC_DBTR(22), data_l);
/* DBTR25 : do not use in LPDDR4 */
mmio_write_32(DBSC_DBTR(25), 0);
@@ -2215,35 +2174,33 @@
#define _par_DBRNK_VAL (0x7007)
for (i = 0; i < 4; i++) {
- dataL = (_par_DBRNK_VAL >> (i * 4)) & 0x0f;
- if ((Prr_Product == PRR_PRODUCT_H3)
- && (Prr_Cut > PRR_PRODUCT_11) && (i == 0)) {
- dataL += 1;
+ data_l = (_par_DBRNK_VAL >> (i * 4)) & 0x0f;
+ if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut > PRR_PRODUCT_11) && (i == 0)) {
+ data_l += 1;
}
- dataL2 = 0;
+ data_l2 = 0;
foreach_vch(ch) {
- dataL2 = dataL2 | (dataL << (4 * ch));
+ data_l2 = data_l2 | (data_l << (4 * ch));
}
- mmio_write_32(DBSC_DBRNK(2 + i), dataL2);
+ mmio_write_32(DBSC_DBRNK(2 + i), data_l2);
}
mmio_write_32(DBSC_DBADJ0, 0x00000000);
- /***********************************************************************
- timing registers for Scheduler
- ***********************************************************************/
+ /* timing registers for Scheduler */
/* SCFCTST0 */
/* SCFCTST0 ACT-ACT */
- tmp[3] = 1UL * js2[JS2_tRCpb] * 800 * ddr_mbpsdiv / ddr_mbps;
+ tmp[3] = 1UL * js2[js2_trcpb] * 800 * ddr_mbpsdiv / ddr_mbps;
/* SCFCTST0 RDA-ACT */
tmp[2] =
- 1UL * ((16 / 2) + js2[JS2_tRTP] - 8 +
- js2[JS2_tRPpb]) * 800 * ddr_mbpsdiv / ddr_mbps;
+ 1UL * ((16 / 2) + js2[js2_trtp] - 8 +
+ js2[js2_trppb]) * 800 * ddr_mbpsdiv / ddr_mbps;
/* SCFCTST0 WRA-ACT */
tmp[1] =
1UL * (WL + 1 + (16 / 2) +
- js1[js1_ind].nWR) * 800 * ddr_mbpsdiv / ddr_mbps;
+ js1[js1_ind].nwr) * 800 * ddr_mbpsdiv / ddr_mbps;
/* SCFCTST0 PRE-ACT */
- tmp[0] = 1UL * js2[JS2_tRPpb];
+ tmp[0] = 1UL * js2[js2_trppb];
mmio_write_32(DBSC_SCFCTST0,
(tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]);
@@ -2257,7 +2214,7 @@
1UL * (mmio_read_32(DBSC_DBTR(12)) & 0xff) * 800 * ddr_mbpsdiv /
ddr_mbps;
/* SCFCTST1 ACT-RD/WR */
- tmp[1] = 1UL * js2[JS2_tRCD] * 800 * ddr_mbpsdiv / ddr_mbps;
+ tmp[1] = 1UL * js2[js2_trcd] * 800 * ddr_mbpsdiv / ddr_mbps;
/* SCFCTST1 ASYNCOFS */
tmp[0] = 12;
mmio_write_32(DBSC_SCFCTST1,
@@ -2265,26 +2222,26 @@
/* DBSCHRW1 */
/* DBSCHRW1 SCTRFCAB */
- tmp[0] = 1UL * js2[JS2_tRFCab] * 800 * ddr_mbpsdiv / ddr_mbps;
- dataL = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000) >> 16)
+ tmp[0] = 1UL * js2[js2_trfcab] * 800 * ddr_mbpsdiv / ddr_mbps;
+ data_l = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000) >> 16)
+ (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
+ (0x28 * 2)) * 400 * 2 * ddr_mbpsdiv / ddr_mbps + 7;
- if (tmp[0] < dataL)
- tmp[0] = dataL;
+ if (tmp[0] < data_l)
+ tmp[0] = data_l;
- if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) {
+ if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) {
mmio_write_32(DBSC_DBSCHRW1, tmp[0]
+ ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
- * 400 * 2 * ddr_mbpsdiv +(ddr_mbps-1))/ddr_mbps - 3);
+ * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) /
+ ddr_mbps - 3);
} else {
mmio_write_32(DBSC_DBSCHRW1, tmp[0]
+ ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
- * 400 * 2 * ddr_mbpsdiv +(ddr_mbps-1))/ddr_mbps);
+ * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) /
+ ddr_mbps);
}
- /***********************************************************************
- QOS and CAM
- ***********************************************************************/
+ /* QOS and CAM */
#ifdef ddr_qos_init_setting /* only for non qos_init */
/*wbkwait(0004), wbkmdhi(4,2),wbkmdlo(1,8) */
mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218);
@@ -2330,18 +2287,18 @@
mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
#endif /* ddr_qos_init_setting */
/* H3 Ver.1.1 need to set monitor function */
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_11)) {
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) {
mmio_write_32(DBSC_DBMONCONF4, 0x00700000);
}
- if (Prr_Product == PRR_PRODUCT_H3) {
- if (Prr_Cut == PRR_PRODUCT_10) {
+ if (prr_product == PRR_PRODUCT_H3) {
+ if (prr_cut == PRR_PRODUCT_10) {
/* resrdis, simple mode, sc off */
mmio_write_32(DBSC_DBBCAMDIS, 0x00000007);
- } else if (Prr_Cut == PRR_PRODUCT_11) {
+ } else if (prr_cut == PRR_PRODUCT_11) {
/* resrdis, simple mode */
mmio_write_32(DBSC_DBBCAMDIS, 0x00000005);
- } else if (Prr_Cut < PRR_PRODUCT_30) {
+ } else if (prr_cut < PRR_PRODUCT_30) {
/* H3 Ver.2.0 */
/* resrdis */
mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
@@ -2358,7 +2315,7 @@
static void dbsc_regset_post(void)
{
uint32_t ch, cs;
- uint32_t dataL;
+ uint32_t data_l;
uint32_t slice, rdlat_max, rdlat_min;
rdlat_max = 0;
@@ -2370,18 +2327,17 @@
ddr_setval_s(ch, slice,
_reg_PHY_PER_CS_TRAINING_INDEX,
cs);
- dataL =
- ddr_getval_s(ch, slice,
- _reg_PHY_RDDQS_LATENCY_ADJUST);
- if (dataL > rdlat_max)
- rdlat_max = dataL;
- if (dataL < rdlat_min)
- rdlat_min = dataL;
+ data_l = ddr_getval_s(ch, slice,
+ _reg_PHY_RDDQS_LATENCY_ADJUST);
+ if (data_l > rdlat_max)
+ rdlat_max = data_l;
+ if (data_l < rdlat_min)
+ rdlat_min = data_l;
}
}
}
}
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) {
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) {
mmio_write_32(DBSC_DBTR(24),
((rdlat_max * 2 - rdlat_min + 4) << 24) +
((rdlat_min + 2) << 16) +
@@ -2411,24 +2367,26 @@
mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
/*set DBI */
- if (Boardcnf->dbi_en)
+ if (board_cnf->dbi_en)
mmio_write_32(DBSC_DBDBICNT, 0x00000003);
/* H3 Ver.2.0 or later/M3-N/V3H DBI wa */
- if ((((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
- || (Prr_Product == PRR_PRODUCT_M3N)
- || (Prr_Product == PRR_PRODUCT_V3H)) && (Boardcnf->dbi_en))
+ if ((((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut > PRR_PRODUCT_11)) ||
+ (prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) &&
+ board_cnf->dbi_en)
reg_ddrphy_write_a(0x00001010, 0x01000000);
/*set REFCYCLE */
- dataL = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv;
- mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (dataL & 0x0000ffff));
+ data_l = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv;
+ mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (data_l & 0x0000ffff));
mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS);
#ifdef DDR_BACKUPMODE
- if (ddrBackup == DRAM_BOOT_STATUS_WARM) {
+ if (ddr_backup == DRAM_BOOT_STATUS_WARM) {
#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0,1 only) */
- PutStr(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1);
+ DEBUG(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1);
send_dbcmd(0x08040001);
wait_dbcmd();
send_dbcmd(0x0A040001);
@@ -2436,7 +2394,7 @@
send_dbcmd(0x04040010);
wait_dbcmd();
- if (Prr_Product == PRR_PRODUCT_H3) {
+ if (prr_product == PRR_PRODUCT_H3) {
send_dbcmd(0x08140001);
wait_dbcmd();
send_dbcmd(0x0A140001);
@@ -2458,11 +2416,16 @@
#if RCAR_REWT_TRAINING != 0
/* Periodic-WriteDQ Training seeting */
- if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
- || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut == PRR_PRODUCT_10))) {
+ if (((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) ||
+ ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut == PRR_PRODUCT_10))) {
/* non : H3 Ver.1.x/M3-W Ver.1.0 not support */
} else {
- /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H -> Periodic-WriteDQ Training seeting */
+ /*
+ * H3 Ver.2.0 or later/M3-W Ver.1.1 or
+ * later/M3-N/V3H -> Periodic-WriteDQ Training seeting
+ */
/* Periodic WriteDQ Training seeting */
mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000);
@@ -2483,7 +2446,7 @@
ddr_setval_ach(_reg_PI_TREF_F1, 0x0000);
ddr_setval_ach(_reg_PI_TREF_F2, 0x0000);
- if (Prr_Product == PRR_PRODUCT_M3) {
+ if (prr_product == PRR_PRODUCT_M3) {
ddr_setval_ach(_reg_PI_WDQLVL_EN, 0x02);
} else {
ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x02);
@@ -2491,18 +2454,21 @@
ddr_setval_ach(_reg_PI_WDQLVL_PERIODIC, 0x01);
/* DFI_PHYMSTR_ACK , WTmode setting */
- mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011); /* DFI_PHYMSTR_ACK: WTmode =b'01 */
+ /* DFI_PHYMSTR_ACK: WTmode =b'01 */
+ mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011);
}
#endif /* RCAR_REWT_TRAINING */
/* periodic dram zqcal and phy ctrl update enable */
mmio_write_32(DBSC_DBCALCNF, 0x01000010);
- if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
- || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) {
+ if (((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) ||
+ ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut < PRR_PRODUCT_30))) {
/* non : H3 Ver.1.x/M3-W Ver.1.x not support */
} else {
#if RCAR_DRAM_SPLIT == 2
- if ((Prr_Product == PRR_PRODUCT_H3)
- && (Boardcnf->phyvalid == 0x05))
+ if ((prr_product == PRR_PRODUCT_H3) &&
+ (board_cnf->phyvalid == 0x05))
mmio_write_32(DBSC_DBDFICUPDCNF, 0x2a240001);
else
mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001);
@@ -2515,33 +2481,26 @@
/* dram access enable */
mmio_write_32(DBSC_DBACEN, 0x00000001);
- MSG_LF("dbsc_regset_post(done)");
-
+ MSG_LF(__func__ "(done)");
}
-/*******************************************************************************
- * DFI_INIT_START
- ******************************************************************************/
+/* DFI_INIT_START */
static uint32_t dfi_init_start(void)
{
uint32_t ch;
uint32_t phytrainingok;
uint32_t retry;
- uint32_t dataL;
+ uint32_t data_l;
const uint32_t RETRY_MAX = 0x10000;
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
- /***********************************************************************
- PLL3 Disable
- ***********************************************************************/
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
+ /* PLL3 Disable */
/* protect register interface */
ddrphy_regif_idle();
pll3_control(0);
- /***********************************************************************
- init start
- ***********************************************************************/
+ /* init start */
/* dbdficnt0:
* dfi_dram_clk_disable=1
* dfi_frequency = 0
@@ -2573,15 +2532,13 @@
mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01);
dsb_sev();
- /***********************************************************************
- wait init_complete
- ***********************************************************************/
+ /* wait init_complete */
phytrainingok = 0;
retry = 0;
while (retry++ < RETRY_MAX) {
foreach_vch(ch) {
- dataL = mmio_read_32(DBSC_DBDFISTAT(ch));
- if (dataL & 0x00000001)
+ data_l = mmio_read_32(DBSC_DBDFISTAT(ch));
+ if (data_l & 0x00000001)
phytrainingok |= (1U << ch);
}
dsb_sev();
@@ -2591,12 +2548,10 @@
ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01);
}
- /***********************************************************************
- all ch ok?
- ***********************************************************************/
- if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid) {
- return (0xff);
- }
+ /* all ch ok? */
+ if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid)
+ return 0xff;
+
/* dbdficnt0:
* dfi_dram_clk_disable=0
* dfi_frequency = 0
@@ -2610,14 +2565,12 @@
return 0;
}
-/*******************************************************************************
- * drivablity setting : CMOS MODE ON/OFF
- ******************************************************************************/
+/* drivablity setting : CMOS MODE ON/OFF */
static void change_lpddr4_en(uint32_t mode)
{
uint32_t ch;
uint32_t i;
- uint32_t dataL;
+ uint32_t data_l;
const uint32_t _reg_PHY_PAD_DRIVE_X[3] = {
_reg_PHY_PAD_ADDR_DRIVE,
_reg_PHY_PAD_CLK_DRIVE,
@@ -2626,31 +2579,30 @@
foreach_vch(ch) {
for (i = 0; i < 3; i++) {
- dataL = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]);
+ data_l = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]);
if (mode) {
- dataL |= (1U << 14);
+ data_l |= (1U << 14);
} else {
- dataL &= ~(1U << 14);
+ data_l &= ~(1U << 14);
}
- ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], dataL);
+ ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], data_l);
}
}
}
-/*******************************************************************************
- * drivablity setting
- ******************************************************************************/
+/* drivablity setting */
static uint32_t set_term_code(void)
{
int32_t i;
uint32_t ch, index;
- uint32_t dataL;
+ uint32_t data_l;
uint32_t chip_id[2];
uint32_t term_code;
uint32_t override;
uint32_t pvtr;
uint32_t pvtp;
uint32_t pvtn;
+
term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
_reg_PHY_PAD_DATA_TERM);
override = 0;
@@ -2659,12 +2611,12 @@
index = 0;
while (1) {
- if (TermcodeBySample[index][0] == 0xffffffff) {
+ if (termcode_by_sample[index][0] == 0xffffffff) {
break;
}
- if ((TermcodeBySample[index][0] == chip_id[0])
- && (TermcodeBySample[index][1] == chip_id[1])) {
- term_code = TermcodeBySample[index][2];
+ if ((termcode_by_sample[index][0] == chip_id[0]) &&
+ (termcode_by_sample[index][1] == chip_id[1])) {
+ term_code = termcode_by_sample[index][2];
override = 1;
break;
}
@@ -2673,14 +2625,14 @@
if (override) {
for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) {
- dataL =
+ data_l =
ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
_reg_PHY_PAD_TERM_X[index]);
- dataL = (dataL & 0xfffe0000) | term_code;
- ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], dataL);
+ data_l = (data_l & 0xfffe0000) | term_code;
+ ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], data_l);
}
- } else if ((Prr_Product == PRR_PRODUCT_M3)
- && (Prr_Cut == PRR_PRODUCT_10)) {
+ } else if ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut == PRR_PRODUCT_10)) {
/* non */
} else {
ddr_setval_ach(_reg_PHY_PAD_TERM_X[0],
@@ -2691,139 +2643,148 @@
ddr_setval_ach(_reg_PHY_CAL_START_0, 0x01);
foreach_vch(ch) {
do {
- dataL =
+ data_l =
ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0);
- } while (!(dataL & 0x00800000));
+ } while (!(data_l & 0x00800000));
}
- if ((Prr_Product == PRR_PRODUCT_H3)
- && (Prr_Cut <= PRR_PRODUCT_11)) {
+ if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) {
foreach_vch(ch) {
- dataL = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]);
- pvtr = (dataL >> 12) & 0x1f;
+ data_l = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]);
+ pvtr = (data_l >> 12) & 0x1f;
pvtr += 8;
if (pvtr > 0x1f)
pvtr = 0x1f;
- dataL =
+ data_l =
ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0);
- pvtn = (dataL >> 6) & 0x03f;
- pvtp = (dataL >> 0) & 0x03f;
+ pvtn = (data_l >> 6) & 0x03f;
+ pvtp = (data_l >> 0) & 0x03f;
for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM;
index++) {
- dataL =
+ data_l =
ddrtbl_getval
(_cnf_DDR_PHY_ADR_G_REGSET,
_reg_PHY_PAD_TERM_X[index]);
- dataL = (dataL & 0xfffe0000)
+ data_l = (data_l & 0xfffe0000)
| (pvtr << 12)
| (pvtn << 6)
| (pvtp);
ddr_setval(ch,
_reg_PHY_PAD_TERM_X[index],
- dataL);
+ data_l);
}
}
- } else { /* M3-W Ver.1.1 or later/H3 Ver.2.0 or later/M3-N/V3H */
+ } else {
+ /* M3-W Ver.1.1 or later/H3 Ver.2.0 or later/M3-N/V3H */
foreach_vch(ch) {
for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM;
index++) {
- dataL =
+ data_l =
ddr_getval(ch,
_reg_PHY_PAD_TERM_X
[index]);
ddr_setval(ch,
_reg_PHY_PAD_TERM_X[index],
- (dataL & 0xFFFE0FFF) |
+ (data_l & 0xFFFE0FFF) |
0x00015000);
}
}
}
}
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
- /* non */
+
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
+ /* non */
} else {
ddr_padcal_tcompensate_getinit(override);
}
+
return 0;
}
-/*******************************************************************************
- * DDR mode register setting
- ******************************************************************************/
+/* DDR mode register setting */
static void ddr_register_set(void)
{
int32_t fspwp;
uint32_t tmp;
for (fspwp = 1; fspwp >= 0; fspwp--) {
- /*MR13,fspwp */
- send_dbcmd(0x0e840d08 | (fspwp << 6));
+ /*MR13, fspwp */
+ send_dbcmd(0x0e840d08 | ((2 - fspwp) << 6));
tmp =
ddrtbl_getval(_cnf_DDR_PI_REGSET,
- _reg_PI_MR1_DATA_Fx_CSx[fspwp][0]);
+ reg_pi_mr1_data_fx_csx[fspwp][0]);
send_dbcmd(0x0e840100 | tmp);
tmp =
ddrtbl_getval(_cnf_DDR_PI_REGSET,
- _reg_PI_MR2_DATA_Fx_CSx[fspwp][0]);
+ reg_pi_mr2_data_fx_csx[fspwp][0]);
send_dbcmd(0x0e840200 | tmp);
tmp =
ddrtbl_getval(_cnf_DDR_PI_REGSET,
- _reg_PI_MR3_DATA_Fx_CSx[fspwp][0]);
+ reg_pi_mr3_data_fx_csx[fspwp][0]);
send_dbcmd(0x0e840300 | tmp);
tmp =
ddrtbl_getval(_cnf_DDR_PI_REGSET,
- _reg_PI_MR11_DATA_Fx_CSx[fspwp][0]);
+ reg_pi_mr11_data_fx_csx[fspwp][0]);
send_dbcmd(0x0e840b00 | tmp);
tmp =
ddrtbl_getval(_cnf_DDR_PI_REGSET,
- _reg_PI_MR12_DATA_Fx_CSx[fspwp][0]);
+ reg_pi_mr12_data_fx_csx[fspwp][0]);
send_dbcmd(0x0e840c00 | tmp);
tmp =
ddrtbl_getval(_cnf_DDR_PI_REGSET,
- _reg_PI_MR14_DATA_Fx_CSx[fspwp][0]);
+ reg_pi_mr14_data_fx_csx[fspwp][0]);
send_dbcmd(0x0e840e00 | tmp);
/* MR22 */
send_dbcmd(0x0e841616);
+
+ /* ZQCAL start */
+ send_dbcmd(0x0d84004F);
+
+ /* ZQLAT */
+ send_dbcmd(0x0d840051);
}
+
+ /* MR13, fspwp */
+ send_dbcmd(0x0e840d08);
}
-/*******************************************************************************
- * Training handshake functions
- ******************************************************************************/
+/* Training handshake functions */
static inline uint32_t wait_freqchgreq(uint32_t assert)
{
- uint32_t dataL;
+ uint32_t data_l;
uint32_t count;
uint32_t ch;
+
count = 100000;
/* H3 Ver.1.x cannot see frqchg_req */
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
return 0;
}
if (assert) {
do {
- dataL = 1;
+ data_l = 1;
foreach_vch(ch) {
- dataL &= mmio_read_32(DBSC_DBPDSTAT(ch));
+ data_l &= mmio_read_32(DBSC_DBPDSTAT(ch));
}
count = count - 1;
- } while (((dataL & 0x01) != 0x01) & (count != 0));
+ } while (((data_l & 0x01) != 0x01) & (count != 0));
} else {
do {
- dataL = 0;
+ data_l = 0;
foreach_vch(ch) {
- dataL |= mmio_read_32(DBSC_DBPDSTAT(ch));
+ data_l |= mmio_read_32(DBSC_DBPDSTAT(ch));
}
count = count - 1;
- } while (((dataL & 0x01) != 0x00) & (count != 0));
+ } while (((data_l & 0x01) != 0x00) & (count != 0));
}
return (count == 0);
@@ -2832,20 +2793,22 @@
static inline void set_freqchgack(uint32_t assert)
{
uint32_t ch;
- uint32_t dataL;
+ uint32_t data_l;
+
if (assert)
- dataL = 0x0CF20000;
+ data_l = 0x0CF20000;
else
- dataL = 0x00000000;
+ data_l = 0x00000000;
foreach_vch(ch)
- mmio_write_32(DBSC_DBPDCNT2(ch), dataL);
+ mmio_write_32(DBSC_DBPDCNT2(ch), data_l);
}
static inline void set_dfifrequency(uint32_t freq)
{
uint32_t ch;
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
foreach_vch(ch)
mmio_clrsetbits_32(DBSC_DBPDCNT1(ch), 0x1fU, freq);
} else {
@@ -2864,7 +2827,7 @@
timeout = wait_freqchgreq(1);
if (timeout) {
- return (1);
+ return 1;
}
pll3_control(on);
@@ -2876,27 +2839,23 @@
if (timeout) {
FATAL_MSG("BL2: Time out[2]\n");
- return (1);
+ return 1;
}
- return (0);
+ return 0;
}
-/*******************************************************************************
- * update dly
- ******************************************************************************/
+/* update dly */
static void update_dly(void)
{
ddr_setval_ach(_reg_SC_PHY_MANUAL_UPDATE, 0x01);
ddr_setval_ach(_reg_PHY_ADRCTL_MANUAL_UPDATE, 0x01);
}
-/*******************************************************************************
- * training by pi
- ******************************************************************************/
+/* training by pi */
static uint32_t pi_training_go(void)
{
uint32_t flag;
- uint32_t dataL;
+ uint32_t data_l;
uint32_t retry;
const uint32_t RETRY_MAX = 4096 * 16;
uint32_t ch;
@@ -2906,11 +2865,7 @@
uint32_t complete;
uint32_t frqchg_req;
- /* ********************************************************************* */
-
- /***********************************************************************
- pi_start
- ***********************************************************************/
+ /* pi_start */
ddr_setval_ach(_reg_PI_START, 0x01);
foreach_vch(ch)
ddr_getval(ch, _reg_PI_INT_STATUS);
@@ -2919,9 +2874,7 @@
mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001);
dsb_sev();
- /***********************************************************************
- wait pi_int_status[0]
- ***********************************************************************/
+ /* wait pi_int_status[0] */
mst_ch = 0;
flag = 0;
complete = 0;
@@ -2931,8 +2884,8 @@
frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01;
/* H3 Ver.1.x cannot see frqchg_req */
- if ((Prr_Product == PRR_PRODUCT_H3)
- && (Prr_Cut <= PRR_PRODUCT_11)) {
+ if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) {
if ((retry % 4096) == 1) {
frqchg_req = 1;
} else {
@@ -2957,9 +2910,9 @@
foreach_vch(ch) {
if (complete & (1U << ch))
continue;
- dataL =
+ data_l =
ddr_getval(ch, _reg_PI_INT_STATUS);
- if (dataL & 0x01) {
+ if (data_l & 0x01) {
complete |= (1U << ch);
}
}
@@ -2970,194 +2923,153 @@
} while (--retry);
foreach_vch(ch) {
/* dummy read */
- dataL = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0);
- dataL = ddr_getval(ch, _reg_PI_INT_STATUS);
- ddr_setval(ch, _reg_PI_INT_ACK, dataL);
+ data_l = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0);
+ data_l = ddr_getval(ch, _reg_PI_INT_STATUS);
+ ddr_setval(ch, _reg_PI_INT_ACK, data_l);
}
if (ddrphy_regif_chk()) {
- return (0xfd);
+ return 0xfd;
}
return complete;
}
-/*******************************************************************************
- * Initialize ddr
- ******************************************************************************/
+/* Initialize DDR */
static uint32_t init_ddr(void)
{
int32_t i;
- uint32_t dataL;
+ uint32_t data_l;
uint32_t phytrainingok;
uint32_t ch, slice;
uint32_t err;
int16_t adj;
- MSG_LF("init_ddr:0\n");
+ MSG_LF(__func__ ":0\n");
#ifdef DDR_BACKUPMODE
- rcar_dram_get_boot_status(&ddrBackup);
+ rcar_dram_get_boot_status(&ddr_backup);
#endif
- /***********************************************************************
- unlock phy
- ***********************************************************************/
+ /* unlock phy */
/* Unlock DDRPHY register(AGAIN) */
foreach_vch(ch)
mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55A);
dsb_sev();
- if ((((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
- || (Prr_Product == PRR_PRODUCT_M3N)
- || (Prr_Product == PRR_PRODUCT_V3H)) && (Boardcnf->dbi_en))
+ if ((((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut > PRR_PRODUCT_11)) ||
+ (prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) && board_cnf->dbi_en)
reg_ddrphy_write_a(0x00001010, 0x01000001);
else
reg_ddrphy_write_a(0x00001010, 0x00000001);
- /***********************************************************************
- dbsc register pre-setting
- ***********************************************************************/
+ /* DBSC register pre-setting */
dbsc_regset_pre();
- /***********************************************************************
- load ddrphy registers
- ***********************************************************************/
+ /* load ddrphy registers */
ddrtbl_load();
- /***********************************************************************
- configure ddrphy registers
- ***********************************************************************/
+ /* configure ddrphy registers */
ddr_config();
- /***********************************************************************
- dfi_reset assert
- ***********************************************************************/
+ /* dfi_reset assert */
foreach_vch(ch)
mmio_write_32(DBSC_DBPDCNT0(ch), 0x01);
dsb_sev();
- /***********************************************************************
- dbsc register set
- ***********************************************************************/
+ /* dbsc register set */
dbsc_regset();
- MSG_LF("init_ddr:1\n");
+ MSG_LF(__func__ ":1\n");
- /***********************************************************************
- dfi_reset negate
- ***********************************************************************/
+ /* dfi_reset negate */
foreach_vch(ch)
mmio_write_32(DBSC_DBPDCNT0(ch), 0x00);
dsb_sev();
- /***********************************************************************
- dfi_init_start (start ddrphy)
- ***********************************************************************/
+ /* dfi_init_start (start ddrphy) */
err = dfi_init_start();
if (err) {
return INITDRAM_ERR_I;
}
- MSG_LF("init_ddr:2\n");
+ MSG_LF(__func__ ":2\n");
- /***********************************************************************
- ddr backupmode end
- ***********************************************************************/
+ /* ddr backupmode end */
#ifdef DDR_BACKUPMODE
- if (ddrBackup) {
+ if (ddr_backup) {
NOTICE("BL2: [WARM_BOOT]\n");
} else {
NOTICE("BL2: [COLD_BOOT]\n");
}
- err = rcar_dram_update_boot_status(ddrBackup);
+ err = rcar_dram_update_boot_status(ddr_backup);
if (err) {
NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n");
return INITDRAM_ERR_I;
}
#endif
- MSG_LF("init_ddr:3\n");
+ MSG_LF(__func__ ":3\n");
- /***********************************************************************
- override term code after dfi_init_complete
- ***********************************************************************/
+ /* override term code after dfi_init_complete */
err = set_term_code();
if (err) {
return INITDRAM_ERR_I;
}
- MSG_LF("init_ddr:4\n");
+ MSG_LF(__func__ ":4\n");
- /***********************************************************************
- rx offset calibration
- ***********************************************************************/
- if ((Prr_Cut > PRR_PRODUCT_11) || (Prr_Product == PRR_PRODUCT_M3N)
- || (Prr_Product == PRR_PRODUCT_V3H)) {
+ /* rx offset calibration */
+ if ((prr_cut > PRR_PRODUCT_11) || (prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
err = rx_offset_cal_hw();
} else {
err = rx_offset_cal();
}
if (err)
- return (INITDRAM_ERR_O);
- MSG_LF("init_ddr:5\n");
+ return INITDRAM_ERR_O;
+ MSG_LF(__func__ ":5\n");
/* PDX */
send_dbcmd(0x08840001);
- /***********************************************************************
- check register i/f is alive
- ***********************************************************************/
+ /* check register i/f is alive */
err = ddrphy_regif_chk();
if (err) {
- return (INITDRAM_ERR_O);
+ return INITDRAM_ERR_O;
}
- MSG_LF("init_ddr:6\n");
+ MSG_LF(__func__ ":6\n");
- /***********************************************************************
- phy initialize end
- ***********************************************************************/
+ /* phy initialize end */
- /***********************************************************************
- setup DDR mode registers
- ***********************************************************************/
+ /* setup DDR mode registers */
/* CMOS MODE */
change_lpddr4_en(0);
/* MRS */
ddr_register_set();
- /* ZQCAL start */
- send_dbcmd(0x0d84004F);
-
- /* ZQLAT */
- send_dbcmd(0x0d840051);
-
- /***********************************************************************
- Thermal sensor setting
- ***********************************************************************/
+ /* Thermal sensor setting */
/* THCTR Bit6: PONM=0 , Bit0: THSST=1 */
- dataL = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001;
- mmio_write_32(THS1_THCTR, dataL);
+ data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001;
+ mmio_write_32(THS1_THCTR, data_l);
/* LPDDR4 MODE */
change_lpddr4_en(1);
- MSG_LF("init_ddr:7\n");
+ MSG_LF(__func__ ":7\n");
- /***********************************************************************
- mask CS_MAP if RANKx is not found
- ***********************************************************************/
+ /* mask CS_MAP if RANKx is not found */
foreach_vch(ch) {
- dataL = ddr_getval(ch, _reg_PI_CS_MAP);
+ data_l = ddr_getval(ch, _reg_PI_CS_MAP);
if (!(ch_have_this_cs[1] & (1U << ch)))
- dataL = dataL & 0x05;
- ddr_setval(ch, _reg_PI_CS_MAP, dataL);
+ data_l = data_l & 0x05;
+ ddr_setval(ch, _reg_PI_CS_MAP, data_l);
}
- /***********************************************************************
- exec pi_training
- ***********************************************************************/
+ /* exec pi_training */
reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00);
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
- ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01);
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
+ ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01);
} else {
foreach_vch(ch) {
for (slice = 0; slice < SLICE_CNT; slice++) {
@@ -3172,101 +3084,88 @@
phytrainingok = pi_training_go();
if (ddr_phyvalid != (phytrainingok & ddr_phyvalid)) {
- return (INITDRAM_ERR_T | phytrainingok);
+ return INITDRAM_ERR_T | phytrainingok;
}
- MSG_LF("init_ddr:8\n");
+ MSG_LF(__func__ ":8\n");
- /***********************************************************************
- CACS DLY ADJUST
- ***********************************************************************/
- dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj);
+ /* CACS DLY ADJUST */
+ data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj);
foreach_vch(ch) {
for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
- adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]);
+ adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
- dataL + adj);
+ data_l + adj);
}
if (ddr_phycaslice == 1) {
for (i = 0; i < 6; i++) {
- adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
- ddr_setval_s(ch, 2, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
- dataL + adj
+ adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj
+ [i +
+ _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
+ ddr_setval_s(ch, 2,
+ _reg_PHY_CLK_CACS_SLAVE_DELAY_X
+ [i],
+ data_l + adj
);
}
}
}
update_dly();
- MSG_LF("init_ddr:9\n");
+ MSG_LF(__func__ ":9\n");
- /***********************************************************************
- H3 fix rd latency to avoid bug in elasitic buffe
- ***********************************************************************/
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+ /* H3 fix rd latency to avoid bug in elasitic buffer */
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11))
adjust_rddqs_latency();
- }
- /***********************************************************************
- Adjust Write path latency
- ***********************************************************************/
+ /* Adjust Write path latency */
if (ddrtbl_getval
(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD))
adjust_wpath_latency();
- /***********************************************************************
- RDQLVL Training
- ***********************************************************************/
- if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0x00) {
+ /* RDQLVL Training */
+ if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE))
ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01);
- }
err = rdqdm_man();
- if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0x00) {
+ if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE))
ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00);
- }
if (err) {
- return (INITDRAM_ERR_T);
+ return INITDRAM_ERR_T;
}
update_dly();
- MSG_LF("init_ddr:10\n");
+ MSG_LF(__func__ ":10\n");
- /***********************************************************************
- WDQLVL Training
- ***********************************************************************/
+ /* WDQLVL Training */
err = wdqdm_man();
if (err) {
- return (INITDRAM_ERR_T);
+ return INITDRAM_ERR_T;
}
update_dly();
- MSG_LF("init_ddr:11\n");
+ MSG_LF(__func__ ":11\n");
- /***********************************************************************
- training complete, setup dbsc
- ***********************************************************************/
- if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
- || (Prr_Product == PRR_PRODUCT_M3N)
- || (Prr_Product == PRR_PRODUCT_V3H)) {
+ /* training complete, setup DBSC */
+ if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) ||
+ (prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
ddr_setval_ach_as(_reg_PHY_DFI40_POLARITY, 0x00);
ddr_setval_ach(_reg_PI_DFI40_POLARITY, 0x00);
}
dbsc_regset_post();
- MSG_LF("init_ddr:12\n");
+ MSG_LF(__func__ ":12\n");
return phytrainingok;
}
-/*******************************************************************************
- * SW LEVELING COMMON
- ******************************************************************************/
+/* SW LEVELING COMMON */
static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick)
{
uint32_t ch;
- uint32_t dataL;
+ uint32_t data_l;
uint32_t retry;
uint32_t waiting;
uint32_t err;
@@ -3295,8 +3194,8 @@
foreach_vch(ch) {
if (!(waiting & (1U << ch)))
continue;
- dataL = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
- if (dataL & 0x01)
+ data_l = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
+ if (data_l & 0x01)
waiting &= ~(1U << ch);
}
retry--;
@@ -3313,23 +3212,19 @@
return err;
}
-/*******************************************************************************
- * WDQ TRAINING
- ******************************************************************************/
+/* WDQ TRAINING */
#ifndef DDR_FAST_INIT
static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
{
int32_t i, k;
uint32_t cs, slice;
- uint32_t dataL;
+ uint32_t data_l;
- /***********************************************************************
- clr of training results buffer
- ***********************************************************************/
+ /* clr of training results buffer */
cs = ddr_csn % 2;
- dataL = Boardcnf->dqdm_dly_w;
+ data_l = board_cnf->dqdm_dly_w;
for (slice = 0; slice < SLICE_CNT; slice++) {
- k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+ k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
continue;
@@ -3338,7 +3233,7 @@
wdqdm_dly[ch][cs][slice][i] =
wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i];
else
- wdqdm_dly[ch][cs][slice][i] = dataL;
+ wdqdm_dly[ch][cs][slice][i] = data_l;
wdqdm_le[ch][cs][slice][i] = 0;
wdqdm_te[ch][cs][slice][i] = 0;
}
@@ -3351,7 +3246,7 @@
{
int32_t i, k;
uint32_t cs, slice;
- uint32_t dataL;
+ uint32_t data_l;
uint32_t err;
const uint32_t _par_WDQLVL_RETRY_THRES = 0x7c0;
@@ -3361,12 +3256,10 @@
int16_t adj;
uint32_t dq;
- /***********************************************************************
- analysis of training results
- ***********************************************************************/
+ /* analysis of training results */
err = 0;
for (slice = 0; slice < SLICE_CNT; slice += 1) {
- k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+ k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
continue;
@@ -3375,45 +3268,47 @@
for (i = 0; i < 9; i++) {
dq = slice * 8 + i;
if (i == 8)
- _adj = Boardcnf->ch[ch].dm_adj_w[slice];
+ _adj = board_cnf->ch[ch].dm_adj_w[slice];
else
- _adj = Boardcnf->ch[ch].dq_adj_w[dq];
+ _adj = board_cnf->ch[ch].dq_adj_w[dq];
adj = _f_scale_adj(_adj);
- dataL =
+ data_l =
ddr_getval_s(ch, slice,
_reg_PHY_CLK_WRX_SLAVE_DELAY[i]) + adj;
ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i],
- dataL);
- wdqdm_dly[ch][cs][slice][i] = dataL;
+ data_l);
+ wdqdm_dly[ch][cs][slice][i] = data_l;
}
ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00);
- dataL = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS);
- wdqdm_st[ch][cs][slice] = dataL;
+ data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS);
+ wdqdm_st[ch][cs][slice] = data_l;
min_win = INT_LEAST32_MAX;
for (i = 0; i <= 8; i++) {
ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT,
i);
- dataL =
+ data_l =
ddr_getval_s(ch, slice,
_reg_PHY_WDQLVL_DQDM_TE_DLY_OBS);
- wdqdm_te[ch][cs][slice][i] = dataL;
- dataL =
+ wdqdm_te[ch][cs][slice][i] = data_l;
+ data_l =
ddr_getval_s(ch, slice,
_reg_PHY_WDQLVL_DQDM_LE_DLY_OBS);
- wdqdm_le[ch][cs][slice][i] = dataL;
+ wdqdm_le[ch][cs][slice][i] = data_l;
win =
- (int32_t) wdqdm_te[ch][cs][slice][i] -
+ (int32_t)wdqdm_te[ch][cs][slice][i] -
wdqdm_le[ch][cs][slice][i];
if (min_win > win)
min_win = win;
- if (dataL >= _par_WDQLVL_RETRY_THRES)
+ if (data_l >= _par_WDQLVL_RETRY_THRES)
err = 2;
}
wdqdm_win[ch][cs][slice] = min_win;
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
- ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x01);
+ if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) {
+ ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN,
+ 0x01);
} else {
ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN,
((ch_have_this_cs[1]) >> ch) & 0x01);
@@ -3430,9 +3325,7 @@
uint32_t tgt_cs, src_cs;
uint32_t tmp_r;
- /***********************************************************************
- copy of training results
- ***********************************************************************/
+ /* copy of training results */
foreach_vch(ch) {
for (tgt_cs = 0; tgt_cs < CS_CNT; tgt_cs++) {
for (slice = 0; slice < SLICE_CNT; slice++) {
@@ -3466,7 +3359,7 @@
int32_t k;
uint32_t ch, cs, slice;
uint32_t ddr_csn;
- uint32_t dataL;
+ uint32_t data_l;
uint32_t err;
uint32_t high_dq[DRAM_CH_CNT];
uint32_t mr14_csab0_bak[DRAM_CH_CNT];
@@ -3474,14 +3367,13 @@
uint32_t err_flg;
#endif/* DDR_FAST_INIT */
- /***********************************************************************
- manual execution of training
- ***********************************************************************/
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+ /* manual execution of training */
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
foreach_vch(ch) {
high_dq[ch] = 0;
for (slice = 0; slice < SLICE_CNT; slice++) {
- k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+ k = (board_cnf->ch[ch].dqs_swap >>
+ (4 * slice)) & 0x0f;
if (k >= 2)
high_dq[ch] |= (1U << slice);
}
@@ -3492,10 +3384,10 @@
/* CLEAR PREV RESULT */
for (cs = 0; cs < CS_CNT; cs++) {
ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs);
- if (((Prr_Product == PRR_PRODUCT_H3)
- && (Prr_Cut > PRR_PRODUCT_11))
- || (Prr_Product == PRR_PRODUCT_M3N)
- || (Prr_Product == PRR_PRODUCT_V3H)) {
+ if (((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut > PRR_PRODUCT_11)) ||
+ (prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
ddr_setval_ach_as(_reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS,
0x01);
} else {
@@ -3509,33 +3401,33 @@
err_flg = 0;
#endif/* DDR_FAST_INIT */
for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
- if ((Prr_Product == PRR_PRODUCT_H3)
- && (Prr_Cut <= PRR_PRODUCT_11)) {
+ if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) {
foreach_vch(ch) {
- dataL = mmio_read_32(DBSC_DBDFICNT(ch));
- dataL &= ~(0x00ffU << 16);
+ data_l = mmio_read_32(DBSC_DBDFICNT(ch));
+ data_l &= ~(0x00ffU << 16);
if (ddr_csn >= 2)
k = (high_dq[ch] ^ 0x0f);
else
k = high_dq[ch];
- dataL |= (k << 16);
- mmio_write_32(DBSC_DBDFICNT(ch), dataL);
+ data_l |= (k << 16);
+ mmio_write_32(DBSC_DBDFICNT(ch), data_l);
ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, k);
}
}
- if (((Prr_Product == PRR_PRODUCT_H3)
- && (Prr_Cut <= PRR_PRODUCT_11))
- || ((Prr_Product == PRR_PRODUCT_M3)
- && (Prr_Cut == PRR_PRODUCT_10))) {
+ if (((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) ||
+ ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut == PRR_PRODUCT_10))) {
wdqdm_cp(ddr_csn, 0);
}
foreach_vch(ch) {
- dataL =
+ data_l =
ddr_getval(ch,
- _reg_PI_MR14_DATA_Fx_CSx[1][ddr_csn]);
- ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0], dataL);
+ reg_pi_mr14_data_fx_csx[1][ddr_csn]);
+ ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], data_l);
}
/* KICK WDQLVL */
@@ -3546,10 +3438,10 @@
if (ddr_csn == 0)
foreach_vch(ch) {
mr14_csab0_bak[ch] =
- ddr_getval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0]);
+ ddr_getval(ch, reg_pi_mr14_data_fx_csx[1][0]);
} else
foreach_vch(ch) {
- ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0],
+ ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0],
mr14_csab0_bak[ch]);
}
#ifndef DDR_FAST_INIT
@@ -3569,16 +3461,16 @@
#ifndef DDR_FAST_INIT
err |= err_flg;
#endif/* DDR_FAST_INIT */
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x01);
foreach_vch(ch) {
- dataL = mmio_read_32(DBSC_DBDFICNT(ch));
- dataL &= ~(0x00ffU << 16);
- mmio_write_32(DBSC_DBDFICNT(ch), dataL);
+ data_l = mmio_read_32(DBSC_DBDFICNT(ch));
+ data_l &= ~(0x00ffU << 16);
+ mmio_write_32(DBSC_DBDFICNT(ch), data_l);
ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, 0x00);
}
}
- return (err);
+ return err;
}
static uint32_t wdqdm_man(void)
@@ -3587,30 +3479,34 @@
const uint32_t retry_max = 0x10;
uint32_t ch, ddr_csn, mr14_bkup[4][4];
- ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, (DBSC_DBTR(11) & 0xFF) + 12);
- if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
- || (Prr_Product == PRR_PRODUCT_M3N)
- || (Prr_Product == PRR_PRODUCT_V3H)) {
+ ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW,
+ (mmio_read_32(DBSC_DBTR(11)) & 0xFF) + 19);
+ if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) ||
+ (prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
+ ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F0,
+ (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1,
- (DBSC_DBTR(12) & 0xFF) + 1);
+ (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
} else {
ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR,
- (DBSC_DBTR(12) & 0xFF) + 1);
+ (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
}
- ddr_setval_ach(_reg_PI_TRFC_F1, (DBSC_DBTR(13) & 0x1FF));
+ ddr_setval_ach(_reg_PI_TRFC_F0, mmio_read_32(DBSC_DBTR(13)) & 0x1FF);
+ ddr_setval_ach(_reg_PI_TRFC_F1, mmio_read_32(DBSC_DBTR(13)) & 0x1FF);
retry_cnt = 0;
err = 0;
do {
- if ((Prr_Product == PRR_PRODUCT_H3)
- && (Prr_Cut <= PRR_PRODUCT_11)) {
+ if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) {
err = wdqdm_man1();
} else {
ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01);
ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE,
0x01);
- if ((Prr_Product == PRR_PRODUCT_M3N)
- || (Prr_Product == PRR_PRODUCT_V3H)) {
+ if ((prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1,
0x0C);
} else {
@@ -3622,14 +3518,14 @@
for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
mr14_bkup[ch][ddr_csn] =
ddr_getval(ch,
- _reg_PI_MR14_DATA_Fx_CSx
+ reg_pi_mr14_data_fx_csx
[1][ddr_csn]);
dsb_sev();
}
}
- if ((Prr_Product == PRR_PRODUCT_M3N)
- || (Prr_Product == PRR_PRODUCT_V3H)) {
+ if ((prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1,
0x04);
} else {
@@ -3642,10 +3538,10 @@
mr14_bkup[ch][ddr_csn] =
(mr14_bkup[ch][ddr_csn] +
ddr_getval(ch,
- _reg_PI_MR14_DATA_Fx_CSx
+ reg_pi_mr14_data_fx_csx
[1][ddr_csn])) / 2;
ddr_setval(ch,
- _reg_PI_MR14_DATA_Fx_CSx[1]
+ reg_pi_mr14_data_fx_csx[1]
[ddr_csn],
mr14_bkup[ch][ddr_csn]);
}
@@ -3653,8 +3549,8 @@
ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE,
0x00);
- if ((Prr_Product == PRR_PRODUCT_M3N)
- || (Prr_Product == PRR_PRODUCT_V3H)) {
+ if ((prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1,
0x00);
ddr_setval_ach
@@ -3681,31 +3577,27 @@
}
} while (err && (++retry_cnt < retry_max));
- if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
- || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_10))) {
+ if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) ||
+ ((prr_product == PRR_PRODUCT_M3) && (prr_cut <= PRR_PRODUCT_10))) {
wdqdm_cp(0, 1);
}
return (retry_cnt >= retry_max);
}
-/*******************************************************************************
- * RDQ TRAINING
- ******************************************************************************/
+/* RDQ TRAINING */
#ifndef DDR_FAST_INIT
static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
{
int32_t i, k;
uint32_t cs, slice;
- uint32_t dataL;
+ uint32_t data_l;
- /***********************************************************************
- clr of training results buffer
- ***********************************************************************/
+ /* clr of training results buffer */
cs = ddr_csn % 2;
- dataL = Boardcnf->dqdm_dly_r;
+ data_l = board_cnf->dqdm_dly_r;
for (slice = 0; slice < SLICE_CNT; slice++) {
- k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+ k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
continue;
@@ -3718,8 +3610,9 @@
SLICE_CNT]
[i];
} else {
- rdqdm_dly[ch][cs][slice][i] = dataL;
- rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = dataL;
+ rdqdm_dly[ch][cs][slice][i] = data_l;
+ rdqdm_dly[ch][cs][slice + SLICE_CNT][i] =
+ data_l;
}
rdqdm_le[ch][cs][slice][i] = 0;
rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0;
@@ -3737,7 +3630,7 @@
{
int32_t i, k;
uint32_t cs, slice;
- uint32_t dataL;
+ uint32_t data_l;
uint32_t err;
int8_t _adj;
int16_t adj;
@@ -3746,12 +3639,10 @@
int32_t win;
uint32_t rdq_status_obs_select;
- /***********************************************************************
- analysis of training results
- ***********************************************************************/
+ /* analysis of training results */
err = 0;
for (slice = 0; slice < SLICE_CNT; slice++) {
- k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+ k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
continue;
@@ -3765,36 +3656,36 @@
for (i = 0; i <= 8; i++) {
dq = slice * 8 + i;
if (i == 8)
- _adj = Boardcnf->ch[ch].dm_adj_r[slice];
+ _adj = board_cnf->ch[ch].dm_adj_r[slice];
else
- _adj = Boardcnf->ch[ch].dq_adj_r[dq];
+ _adj = board_cnf->ch[ch].dq_adj_r[dq];
adj = _f_scale_adj(_adj);
- dataL =
+ data_l =
ddr_getval_s(ch, slice,
_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) +
adj;
ddr_setval_s(ch, slice,
_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i],
- dataL);
- rdqdm_dly[ch][cs][slice][i] = dataL;
+ data_l);
+ rdqdm_dly[ch][cs][slice][i] = data_l;
- dataL =
+ data_l =
ddr_getval_s(ch, slice,
_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) +
adj;
ddr_setval_s(ch, slice,
_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i],
- dataL);
- rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = dataL;
+ data_l);
+ rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l;
}
min_win = INT_LEAST32_MAX;
for (i = 0; i <= 8; i++) {
- dataL =
+ data_l =
ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS);
- rdqdm_st[ch][cs][slice] = dataL;
- rdqdm_st[ch][cs][slice + SLICE_CNT] = dataL;
+ rdqdm_st[ch][cs][slice] = data_l;
+ rdqdm_st[ch][cs][slice + SLICE_CNT] = data_l;
/* k : rise/fall */
for (k = 0; k < 2; k++) {
if (i == 8) {
@@ -3806,28 +3697,28 @@
_reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT,
rdq_status_obs_select);
- dataL =
+ data_l =
ddr_getval_s(ch, slice,
_reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS);
rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] =
- dataL;
+ data_l;
- dataL =
+ data_l =
ddr_getval_s(ch, slice,
_reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS);
rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] =
- dataL;
+ data_l;
- dataL =
+ data_l =
ddr_getval_s(ch, slice,
_reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS);
rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] =
- dataL;
+ data_l;
win =
- (int32_t) rdqdm_te[ch][cs][slice +
- SLICE_CNT *
- k][i] -
+ (int32_t)rdqdm_te[ch][cs][slice +
+ SLICE_CNT *
+ k][i] -
rdqdm_le[ch][cs][slice + SLICE_CNT * k][i];
if (i != 8) {
if (min_win > win)
@@ -3840,7 +3731,7 @@
err = 2;
}
}
- return (err);
+ return err;
}
#endif/* DDR_FAST_INIT */
@@ -3850,13 +3741,11 @@
uint32_t ddr_csn;
#ifdef DDR_FAST_INIT
uint32_t slice;
- uint32_t i, adj, dataL;
+ uint32_t i, adj, data_l;
#endif/* DDR_FAST_INIT */
uint32_t err;
- /***********************************************************************
- manual execution of training
- ***********************************************************************/
+ /* manual execution of training */
err = 0;
for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
@@ -3881,7 +3770,7 @@
if (ch_have_this_cs[ddr_csn] & (1U << ch)) {
for (slice = 0; slice < SLICE_CNT; slice++) {
if (ddr_getval_s(ch, slice,
- _reg_PHY_RDLVL_STATUS_OBS) !=
+ _reg_PHY_RDLVL_STATUS_OBS) !=
0x0D00FFFF) {
err = (1U << ch) |
(0x10U << slice);
@@ -3889,26 +3778,26 @@
}
}
}
- if (((Prr_Product == PRR_PRODUCT_H3)
- && (Prr_Cut <= PRR_PRODUCT_11))
- || ((Prr_Product == PRR_PRODUCT_M3)
- && (Prr_Cut <= PRR_PRODUCT_10))) {
+ if (((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) ||
+ ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut <= PRR_PRODUCT_10))) {
for (slice = 0; slice < SLICE_CNT; slice++) {
for (i = 0; i <= 8; i++) {
if (i == 8)
- adj = _f_scale_adj(Boardcnf->ch[ch].dm_adj_r[slice]);
+ adj = _f_scale_adj(board_cnf->ch[ch].dm_adj_r[slice]);
else
- adj = _f_scale_adj(Boardcnf->ch[ch].dq_adj_r[slice * 8 + i]);
+ adj = _f_scale_adj(board_cnf->ch[ch].dq_adj_r[slice * 8 + i]);
ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn);
- dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj;
- ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], dataL);
- rdqdm_dly[ch][ddr_csn][slice][i] = dataL;
- rdqdm_dly[ch][ddr_csn | 1][slice][i] = dataL;
+ data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj;
+ ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], data_l);
+ rdqdm_dly[ch][ddr_csn][slice][i] = data_l;
+ rdqdm_dly[ch][ddr_csn | 1][slice][i] = data_l;
- dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj;
- ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], dataL);
- rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = dataL;
- rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = dataL;
+ data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj;
+ ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], data_l);
+ rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = data_l;
+ rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = data_l;
}
}
}
@@ -3919,7 +3808,7 @@
}
err_exit:
- return (err);
+ return err;
}
static uint32_t rdqdm_man(void)
@@ -3961,9 +3850,7 @@
return (retry_cnt >= retry_max);
}
-/*******************************************************************************
- * rx offset calibration
- ******************************************************************************/
+/* rx offset calibration */
static int32_t _find_change(uint64_t val, uint32_t dir)
{
int32_t i;
@@ -3976,18 +3863,18 @@
for (i = 1; i <= VAL_END; i++) {
curval = (val >> i) & 0x01;
if (curval != startval)
- return (i);
+ return i;
}
- return (VAL_END);
- } else {
- startval = (val >> dir) & 0x01;
- for (i = dir - 1; i >= 0; i--) {
- curval = (val >> i) & 0x01;
- if (curval != startval)
- return (i);
- }
- return (0);
+ return VAL_END;
}
+
+ startval = (val >> dir) & 0x01;
+ for (i = dir - 1; i >= 0; i--) {
+ curval = (val >> i) & 0x01;
+ if (curval != startval)
+ return i;
+ }
+ return 0;
}
static uint32_t _rx_offset_cal_updn(uint32_t code)
@@ -3995,7 +3882,7 @@
const uint32_t CODE_MAX = 0x40;
uint32_t tmp;
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
if (code == 0)
tmp = (1U << 6) | (CODE_MAX - 1);
else if (code <= 0x20)
@@ -4031,9 +3918,8 @@
ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01);
foreach_vch(ch) {
for (slice = 0; slice < SLICE_CNT; slice++) {
- for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) {
+ for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++)
val[ch][slice][index] = 0;
- }
}
}
@@ -4043,7 +3929,7 @@
ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp);
}
dsb_sev();
- ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *) tmp_ach_as);
+ ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *)tmp_ach_as);
foreach_vch(ch) {
for (slice = 0; slice < SLICE_CNT; slice++) {
@@ -4063,7 +3949,8 @@
}
foreach_vch(ch) {
for (slice = 0; slice < SLICE_CNT; slice++) {
- for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) {
+ for (index = 0; index < _reg_PHY_RX_CAL_X_NUM;
+ index++) {
tmpval = val[ch][slice][index];
lsb = _find_change(tmpval, 0);
msb =
@@ -4100,7 +3987,7 @@
ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01);
}
foreach_vch(ch)
- for (slice = 0; slice < SLICE_CNT; slice++)
+ for (slice = 0; slice < SLICE_CNT; slice++)
tmp_ach_as[ch][slice] =
ddr_getval_s(ch, slice, _reg_PHY_RX_CAL_X[9]);
@@ -4109,10 +3996,10 @@
for (slice = 0; slice < SLICE_CNT; slice++) {
tmp = tmp_ach_as[ch][slice];
tmp = (tmp & 0x3f) + ((tmp >> 6) & 0x3f);
- if (((Prr_Product == PRR_PRODUCT_H3)
- && (Prr_Cut > PRR_PRODUCT_11))
- || (Prr_Product == PRR_PRODUCT_M3N)
- || (Prr_Product == PRR_PRODUCT_V3H)) {
+ if (((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut > PRR_PRODUCT_11)) ||
+ (prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
if (tmp != 0x3E)
complete = 0;
} else {
@@ -4130,9 +4017,7 @@
return (complete == 0);
}
-/*******************************************************************************
- * adjust rddqs latency
- ******************************************************************************/
+/* adjust rddqs latency */
static void adjust_rddqs_latency(void)
{
uint32_t ch, slice;
@@ -4140,6 +4025,7 @@
uint32_t maxlatx2;
uint32_t tmp;
uint32_t rdlat_adjx2[SLICE_CNT];
+
foreach_vch(ch) {
maxlatx2 = 0;
for (slice = 0; slice < SLICE_CNT; slice++) {
@@ -4172,9 +4058,7 @@
}
}
-/*******************************************************************************
- * adjust wpath latency
- ******************************************************************************/
+/* adjust wpath latency */
static void adjust_wpath_latency(void)
{
uint32_t ch, cs, slice;
@@ -4207,94 +4091,90 @@
}
}
-/*******************************************************************************
- * DDR Initialize entry
- ******************************************************************************/
+/* DDR Initialize entry */
int32_t rcar_dram_init(void)
{
uint32_t ch, cs;
- uint32_t dataL;
+ uint32_t data_l;
uint32_t bus_mbps, bus_mbpsdiv;
uint32_t tmp_tccd;
uint32_t failcount;
+ uint32_t cnf_boardtype;
- /***********************************************************************
- Thermal sensor setting
- ***********************************************************************/
- dataL = mmio_read_32(CPG_MSTPSR5);
- if (dataL & BIT(22)) { /* case THS/TSC Standby */
- dataL &= ~(BIT(22));
- cpg_write_32(CPG_SMSTPCR5, dataL);
- while ((BIT(22)) & mmio_read_32(CPG_MSTPSR5)); /* wait bit=0 */
+ /* Thermal sensor setting */
+ data_l = mmio_read_32(CPG_MSTPSR5);
+ if (data_l & BIT(22)) { /* case THS/TSC Standby */
+ data_l &= ~BIT(22);
+ cpg_write_32(CPG_SMSTPCR5, data_l);
+ while (mmio_read_32(CPG_MSTPSR5) & BIT(22))
+ ; /* wait bit=0 */
}
/* THCTR Bit6: PONM=0 , Bit0: THSST=0 */
- dataL = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE;
- mmio_write_32(THS1_THCTR, dataL);
+ data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE;
+ mmio_write_32(THS1_THCTR, data_l);
- /***********************************************************************
- Judge product and cut
- ***********************************************************************/
+ /* Judge product and cut */
#ifdef RCAR_DDR_FIXED_LSI_TYPE
-#if(RCAR_LSI==RCAR_AUTO)
- Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
- Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK;
+#if (RCAR_LSI == RCAR_AUTO)
+ prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
+ prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
#else /* RCAR_LSI */
#ifndef RCAR_LSI_CUT
- Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK;
+ prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
#endif /* RCAR_LSI_CUT */
#endif /* RCAR_LSI */
#else /* RCAR_DDR_FIXED_LSI_TYPE */
- Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
- Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK;
+ prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
+ prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
#endif /* RCAR_DDR_FIXED_LSI_TYPE */
- if (Prr_Product == PRR_PRODUCT_H3) {
- if (Prr_Cut <= PRR_PRODUCT_11) {
- pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[0][0];
+ if (prr_product == PRR_PRODUCT_H3) {
+ if (prr_cut <= PRR_PRODUCT_11) {
+ p_ddr_regdef_tbl =
+ (const uint32_t *)&DDR_REGDEF_TBL[0][0];
} else {
- pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[2][0];
+ p_ddr_regdef_tbl =
+ (const uint32_t *)&DDR_REGDEF_TBL[2][0];
}
- } else if (Prr_Product == PRR_PRODUCT_M3) {
- pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[1][0];
- } else if ((Prr_Product == PRR_PRODUCT_M3N)
- || (Prr_Product == PRR_PRODUCT_V3H)) {
- pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[3][0];
+ } else if (prr_product == PRR_PRODUCT_M3) {
+ p_ddr_regdef_tbl =
+ (const uint32_t *)&DDR_REGDEF_TBL[1][0];
+ } else if ((prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
+ p_ddr_regdef_tbl =
+ (const uint32_t *)&DDR_REGDEF_TBL[3][0];
} else {
FATAL_MSG("BL2: DDR:Unknown Product\n");
return 0xff;
}
- if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
- || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) {
+ if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) ||
+ ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) {
/* non : H3 Ver.1.x/M3-W Ver.1.x not support */
} else {
mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
}
- /***********************************************************************
- Judge board type
- ***********************************************************************/
- _cnf_BOARDTYPE = boardcnf_get_brd_type();
- if (_cnf_BOARDTYPE >= BOARDNUM) {
+ /* Judge board type */
+ cnf_boardtype = boardcnf_get_brd_type();
+ if (cnf_boardtype >= BOARDNUM) {
FATAL_MSG("BL2: DDR:Unknown Board\n");
return 0xff;
}
- Boardcnf = (const struct _boardcnf *)&boardcnfs[_cnf_BOARDTYPE];
+ board_cnf = (const struct _boardcnf *)&boardcnfs[cnf_boardtype];
/* RCAR_DRAM_SPLIT_2CH (2U) */
#if RCAR_DRAM_SPLIT == 2
- /***********************************************************************
- H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split
- ***********************************************************************/
- if ((Prr_Product == PRR_PRODUCT_H3) && (Boardcnf->phyvalid == 0x05)) {
+ /* H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split */
+ if ((prr_product == PRR_PRODUCT_H3) && (board_cnf->phyvalid == 0x05)) {
mmio_write_32(DBSC_DBMEMSWAPCONF0, 0x00000006);
ddr_phyvalid = 0x03;
} else {
- ddr_phyvalid = Boardcnf->phyvalid;
+ ddr_phyvalid = board_cnf->phyvalid;
}
#else /* RCAR_DRAM_SPLIT_2CH */
- ddr_phyvalid = Boardcnf->phyvalid;
+ ddr_phyvalid = board_cnf->phyvalid;
#endif /* RCAR_DRAM_SPLIT_2CH */
max_density = 0;
@@ -4304,53 +4184,46 @@
}
foreach_ech(ch)
- for (cs = 0; cs < CS_CNT; cs++)
+ for (cs = 0; cs < CS_CNT; cs++)
ddr_density[ch][cs] = 0xff;
foreach_vch(ch) {
for (cs = 0; cs < CS_CNT; cs++) {
- dataL = Boardcnf->ch[ch].ddr_density[cs];
- ddr_density[ch][cs] = dataL;
+ data_l = board_cnf->ch[ch].ddr_density[cs];
+ ddr_density[ch][cs] = data_l;
- if (dataL == 0xff)
+ if (data_l == 0xff)
continue;
- if (dataL > max_density)
- max_density = dataL;
- if ((cs == 1) && (Prr_Product == PRR_PRODUCT_H3)
- && (Prr_Cut <= PRR_PRODUCT_11))
+ if (data_l > max_density)
+ max_density = data_l;
+ if ((cs == 1) && (prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11))
continue;
ch_have_this_cs[cs] |= (1U << ch);
}
}
- /***********************************************************************
- Judge board clock frequency (in MHz)
- ***********************************************************************/
- boardcnf_get_brd_clk(_cnf_BOARDTYPE, &brd_clk, &brd_clkdiv);
+ /* Judge board clock frequency (in MHz) */
+ boardcnf_get_brd_clk(cnf_boardtype, &brd_clk, &brd_clkdiv);
if ((brd_clk / brd_clkdiv) > 25) {
brd_clkdiva = 1;
} else {
brd_clkdiva = 0;
}
- /***********************************************************************
- Judge ddr operating frequency clock(in Mbps)
- ***********************************************************************/
- boardcnf_get_ddr_mbps(_cnf_BOARDTYPE, &ddr_mbps, &ddr_mbpsdiv);
+ /* Judge ddr operating frequency clock(in Mbps) */
+ boardcnf_get_ddr_mbps(cnf_boardtype, &ddr_mbps, &ddr_mbpsdiv);
ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1));
- ddr_mul =
- CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk,
- brd_clkdiv * (brd_clkdiva + 1));
+ ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk,
+ brd_clkdiv * (brd_clkdiva + 1));
- /***********************************************************************
- Adjust tccd
- ***********************************************************************/
- dataL = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13;
+ /* Adjust tccd */
+ data_l = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13;
bus_mbps = 0;
bus_mbpsdiv = 0;
- switch (dataL) {
+ switch (data_l) {
case 0:
bus_mbps = brd_clk * 0x60 * 2;
bus_mbpsdiv = brd_clkdiv * 1;
@@ -4385,16 +4258,12 @@
MSG_LF("Start\n");
- /***********************************************************************
- PLL Setting
- ***********************************************************************/
+ /* PLL Setting */
pll3_control(1);
- /***********************************************************************
- initialize DDR
- ***********************************************************************/
- dataL = init_ddr();
- if (dataL == ddr_phyvalid) {
+ /* initialize DDR */
+ data_l = init_ddr();
+ if (data_l == ddr_phyvalid) {
failcount = 0;
} else {
failcount = 1;
@@ -4402,8 +4271,8 @@
foreach_vch(ch)
mmio_write_32(DBSC_DBPDLK(ch), 0x00000000);
- if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
- || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) {
+ if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) ||
+ ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) {
/* non : H3 Ver.1.x/M3-W Ver.1.x not support */
} else {
mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
@@ -4419,7 +4288,7 @@
void pvtcode_update(void)
{
uint32_t ch;
- uint32_t dataL;
+ uint32_t data_l;
uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init;
int32_t pvtp_tmp, pvtn_tmp;
@@ -4445,41 +4314,42 @@
pvtn_init) / (pvtn_tmp) +
6 * pvtp_tmp + pvtp_init;
}
- if ((Prr_Product == PRR_PRODUCT_H3)
- && (Prr_Cut <= PRR_PRODUCT_11)) {
- dataL = pvtp[ch] | (pvtn[ch] << 6) | (tcal.tcomp_cal[ch] & 0xfffff000);
+ if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) {
+ data_l = pvtp[ch] | (pvtn[ch] << 6) |
+ (tcal.tcomp_cal[ch] & 0xfffff000);
reg_ddrphy_write(ch,
ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
- dataL | 0x00020000);
+ data_l | 0x00020000);
reg_ddrphy_write(ch,
ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
- dataL);
+ data_l);
reg_ddrphy_write(ch,
ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
- dataL);
+ data_l);
reg_ddrphy_write(ch,
ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
- dataL);
+ data_l);
reg_ddrphy_write(ch,
ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
- dataL);
+ data_l);
} else {
- dataL = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000;
+ data_l = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000;
reg_ddrphy_write(ch,
ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
- dataL | 0x00020000);
+ data_l | 0x00020000);
reg_ddrphy_write(ch,
ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
- dataL);
+ data_l);
reg_ddrphy_write(ch,
ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
- dataL);
+ data_l);
reg_ddrphy_write(ch,
ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
- dataL);
+ data_l);
reg_ddrphy_write(ch,
ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
- dataL);
+ data_l);
}
}
}
@@ -4487,6 +4357,7 @@
void pvtcode_update2(void)
{
uint32_t ch;
+
foreach_vch(ch) {
reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
tcal.init_cal[ch] | 0x00020000);
@@ -4504,7 +4375,7 @@
void ddr_padcal_tcompensate_getinit(uint32_t override)
{
uint32_t ch;
- uint32_t dataL;
+ uint32_t data_l;
uint32_t pvtp, pvtn;
tcal.init_temp = 0;
@@ -4519,43 +4390,43 @@
}
if (!override) {
- dataL = mmio_read_32(THS1_TEMP);
- if (dataL < 2800) {
+ data_l = mmio_read_32(THS1_TEMP);
+ if (data_l < 2800) {
tcal.init_temp =
- (143 * (int32_t) dataL - 359000) / 1000;
+ (143 * (int32_t)data_l - 359000) / 1000;
} else {
tcal.init_temp =
- (121 * (int32_t) dataL - 296300) / 1000;
+ (121 * (int32_t)data_l - 296300) / 1000;
}
foreach_vch(ch) {
pvtp = (tcal.init_cal[ch] >> 0) & 0x000003F;
pvtn = (tcal.init_cal[ch] >> 6) & 0x000003F;
- if ((int32_t) pvtp >
+ if ((int32_t)pvtp >
((tcal.init_temp * 29 - 3625) / 1000))
pvtp =
- (int32_t) pvtp +
+ (int32_t)pvtp +
((3625 - tcal.init_temp * 29) / 1000);
else
pvtp = 0;
- if ((int32_t) pvtn >
+ if ((int32_t)pvtn >
((tcal.init_temp * 54 - 6750) / 1000))
pvtn =
- (int32_t) pvtn +
+ (int32_t)pvtn +
((6750 - tcal.init_temp * 54) / 1000);
else
pvtn = 0;
- if ((Prr_Product == PRR_PRODUCT_H3)
- && (Prr_Cut <= PRR_PRODUCT_11)) {
+ if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) {
tcal.init_cal[ch] =
- (tcal.
- init_cal[ch] & 0xfffff000) | (pvtn << 6) |
- (pvtp);
+ (tcal.init_cal[ch] & 0xfffff000) |
+ (pvtn << 6) |
+ pvtp;
} else {
tcal.init_cal[ch] =
- 0x00015000 | (pvtn << 6) | (pvtp);
+ 0x00015000 | (pvtn << 6) | pvtp;
}
}
tcal.init_temp = 125;
@@ -4563,13 +4434,9 @@
}
#ifndef ddr_qos_init_setting
-/* for QoS init */
+/* For QoS init */
uint8_t get_boardcnf_phyvalid(void)
{
return ddr_phyvalid;
}
#endif /* ddr_qos_init_setting */
-
-/*******************************************************************************
- * END
- ******************************************************************************/
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
index aaa5f00..f8caade 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
@@ -1,5 +1,6 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,7 +18,7 @@
#else
static uint32_t boardcnf_get_brd_type(void)
{
- return (1);
+ return 1;
}
#endif
@@ -115,7 +116,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
- }
+ }
}
},
/* boardcnf[1] RENESAS KRIEK board with M3-W/SoC */
@@ -126,8 +127,8 @@
0,
0x300,
0x0a0,
- {
- {
+ {
+ {
{0x02, 0x02},
0x00345201,
0x3201,
@@ -147,7 +148,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0x02},
0x00302154,
0x2310,
@@ -166,8 +167,8 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
+ }
+ }
},
/* boardcnf[2] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 1rank) */
{
@@ -177,8 +178,8 @@
-320,
0x300,
0x0a0,
- {
- {
+ {
+ {
{0x02, 0xff},
0x00543210,
0x3210,
@@ -198,7 +199,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0xff},
0x00543210,
0x3102,
@@ -218,7 +219,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0xff},
0x00543210,
0x0213,
@@ -238,7 +239,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0xff},
0x00543210,
0x0213,
@@ -257,8 +258,8 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
+ }
+ }
},
/* boardcnf[3] RENESAS Starter Kit board with M3-W/SIP(8Gbit 1rank) */
{
@@ -268,8 +269,8 @@
0,
0x0300,
0x00a0,
- {
- {
+ {
+ {
{0x02, 0xFF},
0x00543210U,
0x3201,
@@ -289,7 +290,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0xFF},
0x00543210,
0x2310,
@@ -308,8 +309,8 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
+ }
+ }
},
/* boardcnf[4] RENESAS SALVATOR-M(1rank) board with H3 Ver.1.x/SoC */
{
@@ -319,8 +320,8 @@
-320,
0x300,
0x0a0,
- {
- {
+ {
+ {
{0x02, 0xff},
0x00315024,
0x3120,
@@ -340,7 +341,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0xff},
0x00025143,
0x3210,
@@ -360,7 +361,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0xff},
0x00523104,
0x2301,
@@ -380,7 +381,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0xff},
0x00153402,
0x2031,
@@ -399,8 +400,8 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
+ }
+ }
},
/* boardcnf[5] RENESAS KRIEK-1rank board with M3-W/SoC */
{
@@ -410,8 +411,8 @@
0,
0x300,
0x0a0,
- {
- {
+ {
+ {
{0x02, 0xff},
0x00345201,
0x3201,
@@ -431,7 +432,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0xff},
0x00302154,
0x2310,
@@ -450,8 +451,8 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
+ }
+ }
},
/* boardcnf[6] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 2rank) */
{
@@ -461,8 +462,8 @@
-320,
0x300,
0x0a0,
- {
- {
+ {
+ {
{0x02, 0x02},
0x00543210,
0x3210,
@@ -482,7 +483,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0x02},
0x00543210,
0x3102,
@@ -502,7 +503,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0x02},
0x00543210,
0x0213,
@@ -522,7 +523,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0x02},
0x00543210,
0x0213,
@@ -541,10 +542,13 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
+ }
+ }
},
-/* boardcnf[7] RENESAS SALVATOR-X board with H3 Ver.2.0 or later/SIP(8Gbit 1rank) */
+/*
+ * boardcnf[7] RENESAS SALVATOR-X board with
+ * H3 Ver.2.0 or later/SIP(8Gbit 1rank)
+ */
{
0x0f,
0x01,
@@ -552,8 +556,8 @@
0,
0x300,
0x0a0,
- {
- {
+ {
+ {
{0x02, 0xff},
0x00543210,
0x2310,
@@ -573,7 +577,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0xff},
0x00105432,
0x3210,
@@ -593,7 +597,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0xff},
0x00543210,
0x2301,
@@ -613,7 +617,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0xff},
0x00543210,
0x2301,
@@ -632,10 +636,13 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
+ }
+ }
},
-/* boardcnf[8] RENESAS SALVATOR-X board with H3 Ver.2.0 or later/SIP(8Gbit 2rank) */
+/*
+ * boardcnf[8] RENESAS SALVATOR-X board with
+ * H3 Ver.2.0 or later/SIP(8Gbit 2rank)
+ */
{
#if RCAR_DRAM_CHANNEL == 5
0x05,
@@ -647,8 +654,8 @@
0,
0x300,
0x0a0,
- {
- {
+ {
+ {
{0x02, 0x02},
0x00543210,
0x2310,
@@ -669,7 +676,7 @@
0, 0, 0, 0, 0, 0, 0, 0}
},
#if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2))
- {
+ {
{0x02, 0x02},
0x00543210,
0x2301,
@@ -690,7 +697,7 @@
0, 0, 0, 0, 0, 0, 0, 0}
},
#else
- {
+ {
{0x02, 0x02},
0x00105432,
0x3210,
@@ -711,7 +718,7 @@
0, 0, 0, 0, 0, 0, 0, 0}
},
#endif
- {
+ {
{0x02, 0x02},
0x00543210,
0x2301,
@@ -731,7 +738,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0x02},
0x00543210,
0x2301,
@@ -750,8 +757,8 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
+ }
+ }
},
/* boardcnf[9] RENESAS SALVATOR-MS(1rank) board with H3 Ver.2.0 or later/SoC */
{
@@ -761,8 +768,8 @@
0,
0x300,
0x0a0,
- {
- {
+ {
+ {
{0x02, 0xff},
0x00543210,
0x3210,
@@ -782,7 +789,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0xff},
0x00543210,
0x2301,
@@ -802,7 +809,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0xff},
0x00452103,
0x3210,
@@ -822,7 +829,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0xff},
0x00520413,
0x2301,
@@ -841,8 +848,8 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
+ }
+ }
},
/* boardcnf[10] RENESAS Kriek(2rank) board with M3-N/SoC */
{
@@ -852,8 +859,8 @@
0,
0x300,
0x0a0,
- {
- {
+ {
+ {
{0x02, 0x02},
0x00345201,
0x3201,
@@ -872,8 +879,8 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
+ }
+ }
},
/* boardcnf[11] RENESAS SALVATOR-X board with M3-N/SIP(8Gbit 2rank) */
{
@@ -883,8 +890,8 @@
0,
0x300,
0x0a0,
- {
- {
+ {
+ {
#if (RCAR_DRAM_LPDDR4_MEMCONF == 2)
{0x04, 0x04},
#else
@@ -907,8 +914,8 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
+ }
+ }
},
/* boardcnf[12] RENESAS CONDOR board with V3H/SoC */
{
@@ -918,8 +925,8 @@
0,
0x300,
0x0a0,
- {
- {
+ {
+ {
{0x02, 0x02},
0x00501342,
0x3201,
@@ -938,8 +945,8 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
+ }
+ }
},
/* boardcnf[13] RENESAS KRIEK board with PM3/SoC */
{
@@ -949,8 +956,8 @@
-320,
0x300,
0x0a0,
- {
- {
+ {
+ {
{0x02, 0x02},
0x00345201,
0x3201,
@@ -970,7 +977,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0x02},
0x00302154,
0x2310,
@@ -990,7 +997,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0x02},
0x00302154,
0x2310,
@@ -1010,7 +1017,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0xff, 0xff},
0,
0,
@@ -1029,8 +1036,8 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
+ }
+ }
},
/* boardcnf[14] SALVATOR-X board with H3 Ver.2.0 or later/SIP(16Gbit 1rank) */
{
@@ -1044,8 +1051,8 @@
0,
0x300,
0x0a0,
- {
- {
+ {
+ {
{0x04, 0xff},
0x00543210,
0x2310,
@@ -1066,7 +1073,7 @@
0, 0, 0, 0, 0, 0, 0, 0}
},
#if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2))
- {
+ {
{0x04, 0xff},
0x00543210,
0x2301,
@@ -1087,7 +1094,7 @@
0, 0, 0, 0, 0, 0, 0, 0}
},
#else
- {
+ {
{0x04, 0xff},
0x00105432,
0x3210,
@@ -1108,7 +1115,7 @@
0, 0, 0, 0, 0, 0, 0, 0}
},
#endif
- {
+ {
{0x04, 0xff},
0x00543210,
0x2301,
@@ -1128,7 +1135,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x04, 0xff},
0x00543210,
0x2301,
@@ -1147,8 +1154,8 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
+ }
+ }
},
/* boardcnf[15] RENESAS KRIEK board with H3N */
{
@@ -1158,8 +1165,8 @@
0,
0x300,
0x0a0,
- {
- {
+ {
+ {
{0x02, 0x02},
0x00345201,
0x3201,
@@ -1179,7 +1186,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0x02},
0x00302154,
0x2310,
@@ -1199,7 +1206,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x02, 0x02},
0x00302154,
0x2310,
@@ -1219,7 +1226,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0xff, 0xff},
0,
0,
@@ -1238,8 +1245,8 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
+ }
+ }
},
/* boardcnf[16] RENESAS KRIEK-P2P board with M3-W/SoC */
{
@@ -1249,8 +1256,8 @@
0,
0x0300,
0x00a0,
- {
- {
+ {
+ {
{0x04, 0x04},
0x520314FFFF523041,
0x3201,
@@ -1270,7 +1277,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x04, 0x04},
0x314250FFFF312405,
0x2310,
@@ -1289,8 +1296,8 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
+ }
+ }
},
/* boardcnf[17] RENESAS KRIEK-P2P board with M3-N/SoC */
{
@@ -1300,8 +1307,8 @@
0,
0x0300,
0x00a0,
- {
- {
+ {
+ {
{0x04, 0x04},
0x520314FFFF523041,
0x3201,
@@ -1320,8 +1327,8 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
+ }
+ }
},
/* boardcnf[18] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 2rank) */
{
@@ -1331,8 +1338,8 @@
0,
0x0300,
0x00a0,
- {
- {
+ {
+ {
{0x04, 0x04},
0x00543210,
0x3201,
@@ -1352,7 +1359,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x04, 0x04},
0x00543210,
0x2310,
@@ -1371,19 +1378,19 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
+ }
+ }
},
/* boardcnf[19] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 1rank) */
- {
- 0x03,
- 0x01,
- 0x02c0,
- 0,
- 0x0300,
- 0x00a0,
- {
- {
+ {
+ 0x03,
+ 0x01,
+ 0x02c0,
+ 0,
+ 0x0300,
+ 0x00a0,
+ {
+ {
{0x04, 0xff},
0x00543210,
0x3201,
@@ -1403,7 +1410,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
- {
+ {
{0x04, 0xff},
0x00543210,
0x2310,
@@ -1422,118 +1429,118 @@
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
+ }
+ }
},
/* boardcnf[20] RENESAS KRIEK 16Gbit/2rank/2ch board with M3-W/SoC */
- {
- 0x03,
- 0x01,
- 0x02c0,
- 0,
- 0x0300,
- 0x00a0,
- {
- {
- {0x04, 0x04},
- 0x00345201,
- 0x3201,
- {0x01672543, 0x45361207, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
+ {
+ 0x03,
+ 0x01,
+ 0x02c0,
+ 0,
+ 0x0300,
+ 0x00a0,
+ {
+ {
{0x04, 0x04},
- 0x00302154,
- 0x2310,
- {0x01672543, 0x45361207, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
+ 0x00345201,
+ 0x3201,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x04, 0x04},
+ 0x00302154,
+ 0x2310,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
/* boardcnf[21] RENESAS KRIEK 16Gbit/1rank/2ch board with M3-W/SoC */
- {
- 0x03,
- 0x01,
- 0x02c0,
- 0,
- 0x0300,
- 0x00a0,
- {
- {
- {0x04, 0xff},
- 0x00345201,
- 0x3201,
- {0x01672543, 0x45361207, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x04, 0xff},
- 0x00302154,
- 0x2310,
- {0x01672543, 0x45361207, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- }
+ {
+ 0x03,
+ 0x01,
+ 0x02c0,
+ 0,
+ 0x0300,
+ 0x00a0,
+ {
+ {
+ {0x04, 0xff},
+ 0x00345201,
+ 0x3201,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x04, 0xff},
+ 0x00302154,
+ 0x2310,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ }
};
-void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
+void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div)
{
uint32_t md;
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_10)) {
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_10)) {
*clk = 50;
*div = 3;
} else {
@@ -1560,7 +1567,7 @@
(void)brd;
}
-void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t * mbps, uint32_t * div)
+void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div)
{
uint32_t md;
@@ -1599,7 +1606,7 @@
#define M3_SAMPLE_SS_E28 0xB866CC10, 0x3C231421
#define M3_SAMPLE_SS_E32 0xB866CC10, 0x3C241421
-static const uint32_t TermcodeBySample[20][3] = {
+static const uint32_t termcode_by_sample[20][3] = {
{M3_SAMPLE_TT_A84, 0x000158D5},
{M3_SAMPLE_TT_A85, 0x00015955},
{M3_SAMPLE_TT_A86, 0x00015955},
@@ -1616,13 +1623,13 @@
/*
* SAMPLE board detect function
*/
-#define PFC_PMMR 0xE6060000U
+#define PFC_PMMR 0xE6060000U
#define PFC_PUEN5 0xE6060414U
#define PFC_PUEN6 0xE6060418U
#define PFC_PUD5 0xE6060454U
#define PFC_PUD6 0xE6060458U
#define GPIO_INDT5 0xE605500CU
-#define GPIO_GPSR6 0xE6060118U
+#define GPIO_GPSR6 0xE6060118U
#if (RCAR_GEN3_ULCB == 0)
static void pfc_write_and_poll(uint32_t a, uint32_t v)
@@ -1630,7 +1637,8 @@
mmio_write_32(PFC_PMMR, ~v);
v = ~mmio_read_32(PFC_PMMR);
mmio_write_32(a, v);
- while (v != mmio_read_32(a)) ;
+ while (v != mmio_read_32(a))
+ ;
dsb_sev();
}
#endif
@@ -1688,10 +1696,10 @@
if (down == up) {
/* Same = Connect */
return 0;
- } else {
- /* Diff = Open */
- return 1;
}
+
+ /* Diff = Open */
+ return 1;
}
#endif
@@ -1699,10 +1707,10 @@
static uint32_t _board_judge(void)
{
uint32_t brd;
-#if (RCAR_GEN3_ULCB==1)
+#if (RCAR_GEN3_ULCB == 1)
/* Starter Kit */
- if (Prr_Product == PRR_PRODUCT_H3) {
- if (Prr_Cut <= PRR_PRODUCT_11) {
+ if (prr_product == PRR_PRODUCT_H3) {
+ if (prr_cut <= PRR_PRODUCT_11) {
/* RENESAS Starter Kit(H3 Ver.1.x/SIP) board */
brd = 2;
} else {
@@ -1713,7 +1721,7 @@
brd = 8;
#endif
}
- } else if (Prr_Product == PRR_PRODUCT_M3) {
+ } else if (prr_product == PRR_PRODUCT_M3) {
/* RENESAS Starter Kit(M3-W/SIP 8Gbit 1rank) board */
brd = 3;
} else {
@@ -1725,33 +1733,33 @@
usb2_ovc_open = opencheck_SSI_WS6();
- /* RENESAS Eva-borad */
+ /* RENESAS Eva-board */
brd = 99;
- if (Prr_Product == PRR_PRODUCT_V3H) {
+ if (prr_product == PRR_PRODUCT_V3H) {
/* RENESAS Condor board */
brd = 12;
} else if (usb2_ovc_open) {
- if (Prr_Product == PRR_PRODUCT_M3N) {
+ if (prr_product == PRR_PRODUCT_M3N) {
/* RENESAS Kriek board with M3-N */
brd = 10;
- } else if (Prr_Product == PRR_PRODUCT_M3) {
+ } else if (prr_product == PRR_PRODUCT_M3) {
/* RENESAS Kriek board with M3-W */
brd = 1;
- } else if ((Prr_Product == PRR_PRODUCT_H3)
- && (Prr_Cut<=PRR_PRODUCT_11)) {
+ } else if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) {
/* RENESAS Kriek board with PM3 */
brd = 13;
- } else if ((Prr_Product == PRR_PRODUCT_H3)
- && (Prr_Cut > PRR_PRODUCT_20)) {
+ } else if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut > PRR_PRODUCT_20)) {
/* RENESAS Kriek board with H3N */
brd = 15;
}
} else {
- if (Prr_Product == PRR_PRODUCT_H3) {
- if (Prr_Cut <= PRR_PRODUCT_11) {
+ if (prr_product == PRR_PRODUCT_H3) {
+ if (prr_cut <= PRR_PRODUCT_11) {
/* RENESAS SALVATOR-X (H3 Ver.1.x/SIP) */
brd = 2;
- } else if (Prr_Cut < PRR_PRODUCT_30) {
+ } else if (prr_cut < PRR_PRODUCT_30) {
/* RENESAS SALVATOR-X (H3 Ver.2.0/SIP) */
brd = 7; // 8Gbit/1rank
} else {
@@ -1762,16 +1770,19 @@
brd = 8;
#endif
}
- } else if (Prr_Product == PRR_PRODUCT_M3N) {
+ } else if (prr_product == PRR_PRODUCT_M3N) {
/* RENESAS SALVATOR-X (M3-N/SIP) */
brd = 11;
- } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_20)) {
+ } else if ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut <= PRR_PRODUCT_20)) {
/* RENESAS SALVATOR-X (M3-W/SIP) */
brd = 0;
- } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) {
+ } else if ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut < PRR_PRODUCT_30)) {
/* RENESAS SALVATOR-X (M3-W Ver.1.x/SIP) */
brd = 19;
- } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut >= PRR_PRODUCT_30)) {
+ } else if ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut >= PRR_PRODUCT_30)) {
/* RENESAS SALVATOR-X (M3-W ver.3.0/SIP) */
brd = 18;
}
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
index abddf0c..5047e5c 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
@@ -1,13 +1,14 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#define RCAR_DDR_VERSION "rev.0.36"
-#define DRAM_CH_CNT (0x04)
-#define SLICE_CNT (0x04)
-#define CS_CNT (0x02)
+#define RCAR_DDR_VERSION "rev.0.37"
+#define DRAM_CH_CNT 0x04
+#define SLICE_CNT 0x04
+#define CS_CNT 0x02
/* order : CS0A, CS0B, CS1A, CS1B */
#define CSAB_CNT (CS_CNT * 2)
@@ -16,15 +17,16 @@
#define CHAB_CNT (DRAM_CH_CNT * 2)
/* pll setting */
-#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) /((b) * (diva)))
+#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
/* for ddr deisity setting */
-#define DBMEMCONF_REG(d3, row, bank, col, dw) \
+#define DBMEMCONF_REG(d3, row, bank, col, dw) \
((d3) << 30 | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
-#define DBMEMCONF_REGD(density) \
-(DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (29-3-10-2), 3, 10, 2))
+#define DBMEMCONF_REGD(density) \
+ (DBMEMCONF_REG((density) % 2, ((density) + 1) / \
+ 2 + (29 - 3 - 10 - 2), 3, 10, 2))
#define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
@@ -32,7 +34,6 @@
#define DBSC_REFINTS (0x0)
/* system registers */
-#define CPG_BASE (0xE6150000U)
#define CPG_FRQCRB (CPG_BASE + 0x0004U)
#define CPG_PLLECR (CPG_BASE + 0x00D0U)
@@ -45,10 +46,10 @@
#define CPG_CPGWPR (CPG_BASE + 0x0900U)
#define CPG_SRSTCLR4 (CPG_BASE + 0x0950U)
-#define CPG_FRQCRB_KICK_BIT (1U<<31)
-#define CPG_PLLECR_PLL3E_BIT (1U<<3)
-#define CPG_PLLECR_PLL3ST_BIT (1U<<11)
-#define CPG_ZB3CKCR_ZB3ST_BIT (1U<<11)
+#define CPG_FRQCRB_KICK_BIT BIT(31)
+#define CPG_PLLECR_PLL3E_BIT BIT(3)
+#define CPG_PLLECR_PLL3ST_BIT BIT(11)
+#define CPG_ZB3CKCR_ZB3ST_BIT BIT(11)
#define RST_BASE (0xE6160000U)
#define RST_MODEMR (RST_BASE + 0x0060U)
@@ -56,179 +57,7 @@
#define LIFEC_CHIPID(x) (0xE6110040U + 0x04U * (x))
/* DBSC registers */
-#define DBSC_DBSYSCONF1 0xE6790004U
-#define DBSC_DBPHYCONF0 0xE6790010U
-#define DBSC_DBKIND 0xE6790020U
-
-#define DBSC_DBMEMCONF(ch, cs) (0xE6790030U + 0x10U * (ch) + 0x04U * (cs))
-#define DBSC_DBMEMCONF_0_0 0xE6790030U
-#define DBSC_DBMEMCONF_0_1 0xE6790034U
-#define DBSC_DBMEMCONF_0_2 0xE6790038U
-#define DBSC_DBMEMCONF_0_3 0xE679003CU
-#define DBSC_DBMEMCONF_1_2 0xE6790048U
-#define DBSC_DBMEMCONF_1_3 0xE679004CU
-#define DBSC_DBMEMCONF_1_0 0xE6790040U
-#define DBSC_DBMEMCONF_1_1 0xE6790044U
-#define DBSC_DBMEMCONF_2_0 0xE6790050U
-#define DBSC_DBMEMCONF_2_1 0xE6790054U
-#define DBSC_DBMEMCONF_2_2 0xE6790058U
-#define DBSC_DBMEMCONF_2_3 0xE679005CU
-#define DBSC_DBMEMCONF_3_0 0xE6790060U
-#define DBSC_DBMEMCONF_3_1 0xE6790064U
-#define DBSC_DBMEMCONF_3_2 0xE6790068U
-#define DBSC_DBMEMCONF_3_3 0xE679006CU
-
-#define DBSC_DBSYSCNT0 0xE6790100U
-
-#define DBSC_DBACEN 0xE6790200U
-#define DBSC_DBRFEN 0xE6790204U
-#define DBSC_DBCMD 0xE6790208U
-#define DBSC_DBWAIT 0xE6790210U
-#define DBSC_DBSYSCTRL0 0xE6790280U
-
-#define DBSC_DBTR(x) (0xE6790300U + 0x04U * (x))
-#define DBSC_DBTR0 0xE6790300U
-#define DBSC_DBTR1 0xE6790304U
-#define DBSC_DBTR3 0xE679030CU
-#define DBSC_DBTR4 0xE6790310U
-#define DBSC_DBTR5 0xE6790314U
-#define DBSC_DBTR6 0xE6790318U
-#define DBSC_DBTR7 0xE679031CU
-#define DBSC_DBTR8 0xE6790320U
-#define DBSC_DBTR9 0xE6790324U
-#define DBSC_DBTR10 0xE6790328U
-#define DBSC_DBTR11 0xE679032CU
-#define DBSC_DBTR12 0xE6790330U
-#define DBSC_DBTR13 0xE6790334U
-#define DBSC_DBTR14 0xE6790338U
-#define DBSC_DBTR15 0xE679033CU
-#define DBSC_DBTR16 0xE6790340U
-#define DBSC_DBTR17 0xE6790344U
-#define DBSC_DBTR18 0xE6790348U
-#define DBSC_DBTR19 0xE679034CU
-#define DBSC_DBTR20 0xE6790350U
-#define DBSC_DBTR21 0xE6790354U
-#define DBSC_DBTR22 0xE6790358U
-#define DBSC_DBTR23 0xE679035CU
-#define DBSC_DBTR24 0xE6790360U
-#define DBSC_DBTR25 0xE6790364U
-#define DBSC_DBTR26 0xE6790368U
-
-#define DBSC_DBBL 0xE6790400U
-#define DBSC_DBRFCNF1 0xE6790414U
-#define DBSC_DBRFCNF2 0xE6790418U
-#define DBSC_DBTSPCNF 0xE6790420U
-#define DBSC_DBCALCNF 0xE6790424U
-#define DBSC_DBRNK(x) (0xE6790430U + 0x04U * (x))
-#define DBSC_DBRNK2 0xE6790438U
-#define DBSC_DBRNK3 0xE679043CU
-#define DBSC_DBRNK4 0xE6790440U
-#define DBSC_DBRNK5 0xE6790444U
-#define DBSC_DBODT(x) (0xE6790460U + 0x04U * (x))
-
-#define DBSC_DBADJ0 0xE6790500U
-#define DBSC_DBDBICNT 0xE6790518U
-#define DBSC_DBDFIPMSTRCNF 0xE6790520U
-#define DBSC_DBDFICUPDCNF 0xE679052CU
-
-#define DBSC_DBDFISTAT(ch) (0xE6790600U + 0x40U * (ch))
-#define DBSC_DBDFISTAT_0 0xE6790600U
-#define DBSC_DBDFISTAT_1 0xE6790640U
-#define DBSC_DBDFISTAT_2 0xE6790680U
-#define DBSC_DBDFISTAT_3 0xE67906C0U
-
-#define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch))
-#define DBSC_DBDFICNT_0 0xE6790604U
-#define DBSC_DBDFICNT_1 0xE6790644U
-#define DBSC_DBDFICNT_2 0xE6790684U
-#define DBSC_DBDFICNT_3 0xE67906C4U
-
-#define DBSC_DBPDCNT0(ch) (0xE6790610U + 0x40U * (ch))
-#define DBSC_DBPDCNT0_0 0xE6790610U
-#define DBSC_DBPDCNT0_1 0xE6790650U
-#define DBSC_DBPDCNT0_2 0xE6790690U
-#define DBSC_DBPDCNT0_3 0xE67906D0U
-
-#define DBSC_DBPDCNT1(ch) (0xE6790614U + 0x40U * (ch))
-#define DBSC_DBPDCNT1_0 0xE6790614U
-#define DBSC_DBPDCNT1_1 0xE6790654U
-#define DBSC_DBPDCNT1_2 0xE6790694U
-#define DBSC_DBPDCNT1_3 0xE67906D4U
-
-#define DBSC_DBPDCNT2(ch) (0xE6790618U + 0x40U * (ch))
-#define DBSC_DBPDCNT2_0 0xE6790618U
-#define DBSC_DBPDCNT2_1 0xE6790658U
-#define DBSC_DBPDCNT2_2 0xE6790698U
-#define DBSC_DBPDCNT2_3 0xE67906D8U
-
-#define DBSC_DBPDCNT3(ch) (0xE679061CU + 0x40U * (ch))
-#define DBSC_DBPDCNT3_0 0xE679061CU
-#define DBSC_DBPDCNT3_1 0xE679065CU
-#define DBSC_DBPDCNT3_2 0xE679069CU
-#define DBSC_DBPDCNT3_3 0xE67906DCU
-
-#define DBSC_DBPDLK(ch) (0xE6790620U + 0x40U * (ch))
-#define DBSC_DBPDLK_0 0xE6790620U
-#define DBSC_DBPDLK_1 0xE6790660U
-#define DBSC_DBPDLK_2 0xE67906a0U
-#define DBSC_DBPDLK_3 0xE67906e0U
-
-#define DBSC_DBPDRGA(ch) (0xE6790624U + 0x40U * (ch))
-#define DBSC_DBPDRGD(ch) (0xE6790628U + 0x40U * (ch))
-#define DBSC_DBPDRGA_0 0xE6790624U
-#define DBSC_DBPDRGD_0 0xE6790628U
-#define DBSC_DBPDRGA_1 0xE6790664U
-#define DBSC_DBPDRGD_1 0xE6790668U
-#define DBSC_DBPDRGA_2 0xE67906A4U
-#define DBSC_DBPDRGD_2 0xE67906A8U
-#define DBSC_DBPDRGA_3 0xE67906E4U
-#define DBSC_DBPDRGD_3 0xE67906E8U
-
-#define DBSC_DBPDSTAT(ch) (0xE6790630U + 0x40U * (ch))
-#define DBSC_DBPDSTAT_0 0xE6790630U
-#define DBSC_DBPDSTAT_1 0xE6790670U
-#define DBSC_DBPDSTAT_2 0xE67906B0U
-#define DBSC_DBPDSTAT_3 0xE67906F0U
-
-#define DBSC_DBBUS0CNF0 0xE6790800U
-#define DBSC_DBBUS0CNF1 0xE6790804U
-
-#define DBSC_DBCAM0CNF1 0xE6790904U
-#define DBSC_DBCAM0CNF2 0xE6790908U
-#define DBSC_DBCAM0CNF3 0xE679090CU
-#define DBSC_DBBSWAP 0xE67909F0U
-#define DBSC_DBBCAMDIS 0xE67909FCU
-#define DBSC_DBSCHCNT0 0xE6791000U
-#define DBSC_DBSCHCNT1 0xE6791004U
-#define DBSC_DBSCHSZ0 0xE6791010U
-#define DBSC_DBSCHRW0 0xE6791020U
-#define DBSC_DBSCHRW1 0xE6791024U
-
-#define DBSC_DBSCHQOS_0(x) (0xE6791030U +0x10U * (x))
-#define DBSC_DBSCHQOS_1(x) (0xE6791034U +0x10U * (x))
-#define DBSC_DBSCHQOS_2(x) (0xE6791038U +0x10U * (x))
-#define DBSC_DBSCHQOS_3(x) (0xE679103CU +0x10U * (x))
-
-#define DBSC_DBSCTR0 0xE6791700U
-#define DBSC_DBSCTR1 0xE6791708U
-#define DBSC_DBSCHRW2 0xE679170CU
-
-#define DBSC_SCFCTST01(x) (0xE6791700U + 0x08U * (x))
-#define DBSC_SCFCTST0 0xE6791700U
-#define DBSC_SCFCTST1 0xE6791708U
-#define DBSC_SCFCTST2 0xE679170CU
-
-#define DBSC_DBMRRDR(chab) (0xE6791800U + 0x04U * (chab))
-#define DBSC_DBMRRDR_0 0xE6791800U
-#define DBSC_DBMRRDR_1 0xE6791804U
-#define DBSC_DBMRRDR_2 0xE6791808U
-#define DBSC_DBMRRDR_3 0xE679180CU
-#define DBSC_DBMRRDR_4 0xE6791810U
-#define DBSC_DBMRRDR_5 0xE6791814U
-#define DBSC_DBMRRDR_6 0xE6791818U
-#define DBSC_DBMRRDR_7 0xE679181CU
-
-#define DBSC_DBMEMSWAPCONF0 0xE6792000U
+#include "../ddr_regs.h"
#define DBSC_DBMONCONF4 0xE6793010U
@@ -264,33 +93,3 @@
/* other module */
#define THS1_THCTR 0xE6198020U
#define THS1_TEMP 0xE6198028U
-
-#define DBSC_BASE (0xE6790000U)
-#define DBSC_DBSCHQOS00 (DBSC_BASE + 0x1030U)
-#define DBSC_DBSCHQOS01 (DBSC_BASE + 0x1034U)
-#define DBSC_DBSCHQOS02 (DBSC_BASE + 0x1038U)
-#define DBSC_DBSCHQOS03 (DBSC_BASE + 0x103CU)
-#define DBSC_DBSCHQOS40 (DBSC_BASE + 0x1070U)
-#define DBSC_DBSCHQOS41 (DBSC_BASE + 0x1074U)
-#define DBSC_DBSCHQOS42 (DBSC_BASE + 0x1078U)
-#define DBSC_DBSCHQOS43 (DBSC_BASE + 0x107CU)
-#define DBSC_DBSCHQOS90 (DBSC_BASE + 0x10C0U)
-#define DBSC_DBSCHQOS91 (DBSC_BASE + 0x10C4U)
-#define DBSC_DBSCHQOS92 (DBSC_BASE + 0x10C8U)
-#define DBSC_DBSCHQOS93 (DBSC_BASE + 0x10CCU)
-#define DBSC_DBSCHQOS120 (DBSC_BASE + 0x10F0U)
-#define DBSC_DBSCHQOS121 (DBSC_BASE + 0x10F4U)
-#define DBSC_DBSCHQOS122 (DBSC_BASE + 0x10F8U)
-#define DBSC_DBSCHQOS123 (DBSC_BASE + 0x10FCU)
-#define DBSC_DBSCHQOS130 (DBSC_BASE + 0x1100U)
-#define DBSC_DBSCHQOS131 (DBSC_BASE + 0x1104U)
-#define DBSC_DBSCHQOS132 (DBSC_BASE + 0x1108U)
-#define DBSC_DBSCHQOS133 (DBSC_BASE + 0x110CU)
-#define DBSC_DBSCHQOS140 (DBSC_BASE + 0x1110U)
-#define DBSC_DBSCHQOS141 (DBSC_BASE + 0x1114U)
-#define DBSC_DBSCHQOS142 (DBSC_BASE + 0x1118U)
-#define DBSC_DBSCHQOS143 (DBSC_BASE + 0x111CU)
-#define DBSC_DBSCHQOS150 (DBSC_BASE + 0x1120U)
-#define DBSC_DBSCHQOS151 (DBSC_BASE + 0x1124U)
-#define DBSC_DBSCHQOS152 (DBSC_BASE + 0x1128U)
-#define DBSC_DBSCHQOS153 (DBSC_BASE + 0x112CU)
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h
index bad1de9..adf8dab 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h
@@ -1,5 +1,6 @@
/*
- * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2018-2019, Renesas Electronics Corporation.
+ * All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -1178,9 +1179,9 @@
#define _reg_PI_TSDO_F1 0x00000493U
#define _reg_PI_TSDO_F2 0x00000494U
-#define DDR_REGDEF_ADR(regdef) ((regdef)&0xffff)
-#define DDR_REGDEF_LEN(regdef) (((regdef)>>16)&0xff)
-#define DDR_REGDEF_LSB(regdef) (((regdef)>>24)&0xff)
+#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xffff)
+#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xff)
+#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xff)
static const uint32_t DDR_REGDEF_TBL[4][1173] = {
{
@@ -5882,5 +5883,5 @@
/*0492*/ 0x0808031dU,
/*0493*/ 0x1008031dU,
/*0494*/ 0x1808031dU,
- }
+ }
};
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
index 6fa9ab9..357f8ba 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
@@ -1,5 +1,6 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -23,418 +24,418 @@
#define DDR_PI_REGSET_NUM_H3 181
static const uint32_t DDR_PHY_SLICE_REGSET_H3[DDR_PHY_SLICE_REGSET_NUM_H3] = {
-/*0400*/ 0x000004f0,
-/*0401*/ 0x00000000,
-/*0402*/ 0x00000000,
-/*0403*/ 0x00000100,
-/*0404*/ 0x01003c0c,
-/*0405*/ 0x02003c0c,
-/*0406*/ 0x00010300,
-/*0407*/ 0x04000100,
-/*0408*/ 0x00000300,
-/*0409*/ 0x000700c0,
-/*040a*/ 0x00b00201,
-/*040b*/ 0x00000020,
-/*040c*/ 0x00000000,
-/*040d*/ 0x00000000,
-/*040e*/ 0x00000000,
-/*040f*/ 0x00000000,
-/*0410*/ 0x00000000,
-/*0411*/ 0x00000000,
-/*0412*/ 0x00000000,
-/*0413*/ 0x09000000,
-/*0414*/ 0x04080000,
-/*0415*/ 0x04080400,
-/*0416*/ 0x00000000,
-/*0417*/ 0x32103210,
-/*0418*/ 0x00800708,
-/*0419*/ 0x000f000c,
-/*041a*/ 0x00000100,
-/*041b*/ 0x55aa55aa,
-/*041c*/ 0x33cc33cc,
-/*041d*/ 0x0ff00ff0,
-/*041e*/ 0x0f0ff0f0,
-/*041f*/ 0x00008e38,
-/*0420*/ 0x76543210,
-/*0421*/ 0x00000001,
-/*0422*/ 0x00000000,
-/*0423*/ 0x00000000,
-/*0424*/ 0x00000000,
-/*0425*/ 0x00000000,
-/*0426*/ 0x00000000,
-/*0427*/ 0x00000000,
-/*0428*/ 0x00000000,
-/*0429*/ 0x00000000,
-/*042a*/ 0x00000000,
-/*042b*/ 0x00000000,
-/*042c*/ 0x00000000,
-/*042d*/ 0x00000000,
-/*042e*/ 0x00000000,
-/*042f*/ 0x00000000,
-/*0430*/ 0x00000000,
-/*0431*/ 0x00000000,
-/*0432*/ 0x00000000,
-/*0433*/ 0x00200000,
-/*0434*/ 0x08200820,
-/*0435*/ 0x08200820,
-/*0436*/ 0x08200820,
-/*0437*/ 0x08200820,
-/*0438*/ 0x08200820,
-/*0439*/ 0x00000820,
-/*043a*/ 0x03000300,
-/*043b*/ 0x03000300,
-/*043c*/ 0x03000300,
-/*043d*/ 0x03000300,
-/*043e*/ 0x00000300,
-/*043f*/ 0x00000000,
-/*0440*/ 0x00000000,
-/*0441*/ 0x00000000,
-/*0442*/ 0x00000000,
-/*0443*/ 0x00a000a0,
-/*0444*/ 0x00a000a0,
-/*0445*/ 0x00a000a0,
-/*0446*/ 0x00a000a0,
-/*0447*/ 0x00a000a0,
-/*0448*/ 0x00a000a0,
-/*0449*/ 0x00a000a0,
-/*044a*/ 0x00a000a0,
-/*044b*/ 0x00a000a0,
-/*044c*/ 0x01040109,
-/*044d*/ 0x00000200,
-/*044e*/ 0x01000000,
-/*044f*/ 0x00000200,
-/*0450*/ 0x4041a141,
-/*0451*/ 0xc00141a0,
-/*0452*/ 0x0e0100c0,
-/*0453*/ 0x0010000c,
-/*0454*/ 0x0c064208,
-/*0455*/ 0x000f0c18,
-/*0456*/ 0x00e00140,
-/*0457*/ 0x00000c20
+ /*0400*/ 0x000004f0,
+ /*0401*/ 0x00000000,
+ /*0402*/ 0x00000000,
+ /*0403*/ 0x00000100,
+ /*0404*/ 0x01003c0c,
+ /*0405*/ 0x02003c0c,
+ /*0406*/ 0x00010300,
+ /*0407*/ 0x04000100,
+ /*0408*/ 0x00000300,
+ /*0409*/ 0x000700c0,
+ /*040a*/ 0x00b00201,
+ /*040b*/ 0x00000020,
+ /*040c*/ 0x00000000,
+ /*040d*/ 0x00000000,
+ /*040e*/ 0x00000000,
+ /*040f*/ 0x00000000,
+ /*0410*/ 0x00000000,
+ /*0411*/ 0x00000000,
+ /*0412*/ 0x00000000,
+ /*0413*/ 0x09000000,
+ /*0414*/ 0x04080000,
+ /*0415*/ 0x04080400,
+ /*0416*/ 0x00000000,
+ /*0417*/ 0x32103210,
+ /*0418*/ 0x00800708,
+ /*0419*/ 0x000f000c,
+ /*041a*/ 0x00000100,
+ /*041b*/ 0x55aa55aa,
+ /*041c*/ 0x33cc33cc,
+ /*041d*/ 0x0ff00ff0,
+ /*041e*/ 0x0f0ff0f0,
+ /*041f*/ 0x00008e38,
+ /*0420*/ 0x76543210,
+ /*0421*/ 0x00000001,
+ /*0422*/ 0x00000000,
+ /*0423*/ 0x00000000,
+ /*0424*/ 0x00000000,
+ /*0425*/ 0x00000000,
+ /*0426*/ 0x00000000,
+ /*0427*/ 0x00000000,
+ /*0428*/ 0x00000000,
+ /*0429*/ 0x00000000,
+ /*042a*/ 0x00000000,
+ /*042b*/ 0x00000000,
+ /*042c*/ 0x00000000,
+ /*042d*/ 0x00000000,
+ /*042e*/ 0x00000000,
+ /*042f*/ 0x00000000,
+ /*0430*/ 0x00000000,
+ /*0431*/ 0x00000000,
+ /*0432*/ 0x00000000,
+ /*0433*/ 0x00200000,
+ /*0434*/ 0x08200820,
+ /*0435*/ 0x08200820,
+ /*0436*/ 0x08200820,
+ /*0437*/ 0x08200820,
+ /*0438*/ 0x08200820,
+ /*0439*/ 0x00000820,
+ /*043a*/ 0x03000300,
+ /*043b*/ 0x03000300,
+ /*043c*/ 0x03000300,
+ /*043d*/ 0x03000300,
+ /*043e*/ 0x00000300,
+ /*043f*/ 0x00000000,
+ /*0440*/ 0x00000000,
+ /*0441*/ 0x00000000,
+ /*0442*/ 0x00000000,
+ /*0443*/ 0x00a000a0,
+ /*0444*/ 0x00a000a0,
+ /*0445*/ 0x00a000a0,
+ /*0446*/ 0x00a000a0,
+ /*0447*/ 0x00a000a0,
+ /*0448*/ 0x00a000a0,
+ /*0449*/ 0x00a000a0,
+ /*044a*/ 0x00a000a0,
+ /*044b*/ 0x00a000a0,
+ /*044c*/ 0x01040109,
+ /*044d*/ 0x00000200,
+ /*044e*/ 0x01000000,
+ /*044f*/ 0x00000200,
+ /*0450*/ 0x4041a151,
+ /*0451*/ 0xc00141a0,
+ /*0452*/ 0x0e0100c0,
+ /*0453*/ 0x0010000c,
+ /*0454*/ 0x0c064208,
+ /*0455*/ 0x000f0c18,
+ /*0456*/ 0x00e00140,
+ /*0457*/ 0x00000c20
};
static const uint32_t DDR_PHY_ADR_V_REGSET_H3[DDR_PHY_ADR_V_REGSET_NUM_H3] = {
-/*0600*/ 0x00000000,
-/*0601*/ 0x00000000,
-/*0602*/ 0x00000000,
-/*0603*/ 0x00000000,
-/*0604*/ 0x00000000,
-/*0605*/ 0x00000000,
-/*0606*/ 0x00000002,
-/*0607*/ 0x00000000,
-/*0608*/ 0x00000000,
-/*0609*/ 0x00000000,
-/*060a*/ 0x00400320,
-/*060b*/ 0x00000040,
-/*060c*/ 0x00dcba98,
-/*060d*/ 0x00000000,
-/*060e*/ 0x00dcba98,
-/*060f*/ 0x01000000,
-/*0610*/ 0x00020003,
-/*0611*/ 0x00000000,
-/*0612*/ 0x00000000,
-/*0613*/ 0x00000000,
-/*0614*/ 0x00002a01,
-/*0615*/ 0x00000015,
-/*0616*/ 0x00000015,
-/*0617*/ 0x0000002a,
-/*0618*/ 0x00000033,
-/*0619*/ 0x0000000c,
-/*061a*/ 0x0000000c,
-/*061b*/ 0x00000033,
-/*061c*/ 0x00418820,
-/*061d*/ 0x003f0000,
-/*061e*/ 0x0000003f,
-/*061f*/ 0x0002006e,
-/*0620*/ 0x02000200,
-/*0621*/ 0x02000200,
-/*0622*/ 0x00000200,
-/*0623*/ 0x42080010,
-/*0624*/ 0x00000003
+ /*0600*/ 0x00000000,
+ /*0601*/ 0x00000000,
+ /*0602*/ 0x00000000,
+ /*0603*/ 0x00000000,
+ /*0604*/ 0x00000000,
+ /*0605*/ 0x00000000,
+ /*0606*/ 0x00000002,
+ /*0607*/ 0x00000000,
+ /*0608*/ 0x00000000,
+ /*0609*/ 0x00000000,
+ /*060a*/ 0x00400320,
+ /*060b*/ 0x00000040,
+ /*060c*/ 0x00dcba98,
+ /*060d*/ 0x00000000,
+ /*060e*/ 0x00dcba98,
+ /*060f*/ 0x01000000,
+ /*0610*/ 0x00020003,
+ /*0611*/ 0x00000000,
+ /*0612*/ 0x00000000,
+ /*0613*/ 0x00000000,
+ /*0614*/ 0x00002a01,
+ /*0615*/ 0x00000015,
+ /*0616*/ 0x00000015,
+ /*0617*/ 0x0000002a,
+ /*0618*/ 0x00000033,
+ /*0619*/ 0x0000000c,
+ /*061a*/ 0x0000000c,
+ /*061b*/ 0x00000033,
+ /*061c*/ 0x00418820,
+ /*061d*/ 0x003f0000,
+ /*061e*/ 0x0000003f,
+ /*061f*/ 0x0002006e,
+ /*0620*/ 0x02000200,
+ /*0621*/ 0x02000200,
+ /*0622*/ 0x00000200,
+ /*0623*/ 0x42080010,
+ /*0624*/ 0x00000003
};
static const uint32_t DDR_PHY_ADR_I_REGSET_H3[DDR_PHY_ADR_I_REGSET_NUM_H3] = {
-/*0680*/ 0x04040404,
-/*0681*/ 0x00000404,
-/*0682*/ 0x00000000,
-/*0683*/ 0x00000000,
-/*0684*/ 0x00000000,
-/*0685*/ 0x00000000,
-/*0686*/ 0x00000002,
-/*0687*/ 0x00000000,
-/*0688*/ 0x00000000,
-/*0689*/ 0x00000000,
-/*068a*/ 0x00400320,
-/*068b*/ 0x00000040,
-/*068c*/ 0x00000000,
-/*068d*/ 0x00000000,
-/*068e*/ 0x00000000,
-/*068f*/ 0x01000000,
-/*0690*/ 0x00020003,
-/*0691*/ 0x00000000,
-/*0692*/ 0x00000000,
-/*0693*/ 0x00000000,
-/*0694*/ 0x00002a01,
-/*0695*/ 0x00000015,
-/*0696*/ 0x00000015,
-/*0697*/ 0x0000002a,
-/*0698*/ 0x00000033,
-/*0699*/ 0x0000000c,
-/*069a*/ 0x0000000c,
-/*069b*/ 0x00000033,
-/*069c*/ 0x00000000,
-/*069d*/ 0x00000000,
-/*069e*/ 0x00000000,
-/*069f*/ 0x0002006e,
-/*06a0*/ 0x02000200,
-/*06a1*/ 0x02000200,
-/*06a2*/ 0x00000200,
-/*06a3*/ 0x42080010,
-/*06a4*/ 0x00000003
+ /*0680*/ 0x04040404,
+ /*0681*/ 0x00000404,
+ /*0682*/ 0x00000000,
+ /*0683*/ 0x00000000,
+ /*0684*/ 0x00000000,
+ /*0685*/ 0x00000000,
+ /*0686*/ 0x00000002,
+ /*0687*/ 0x00000000,
+ /*0688*/ 0x00000000,
+ /*0689*/ 0x00000000,
+ /*068a*/ 0x00400320,
+ /*068b*/ 0x00000040,
+ /*068c*/ 0x00000000,
+ /*068d*/ 0x00000000,
+ /*068e*/ 0x00000000,
+ /*068f*/ 0x01000000,
+ /*0690*/ 0x00020003,
+ /*0691*/ 0x00000000,
+ /*0692*/ 0x00000000,
+ /*0693*/ 0x00000000,
+ /*0694*/ 0x00002a01,
+ /*0695*/ 0x00000015,
+ /*0696*/ 0x00000015,
+ /*0697*/ 0x0000002a,
+ /*0698*/ 0x00000033,
+ /*0699*/ 0x0000000c,
+ /*069a*/ 0x0000000c,
+ /*069b*/ 0x00000033,
+ /*069c*/ 0x00000000,
+ /*069d*/ 0x00000000,
+ /*069e*/ 0x00000000,
+ /*069f*/ 0x0002006e,
+ /*06a0*/ 0x02000200,
+ /*06a1*/ 0x02000200,
+ /*06a2*/ 0x00000200,
+ /*06a3*/ 0x42080010,
+ /*06a4*/ 0x00000003
};
static const uint32_t DDR_PHY_ADR_G_REGSET_H3[DDR_PHY_ADR_G_REGSET_NUM_H3] = {
-/*0700*/ 0x00000001,
-/*0701*/ 0x00000000,
-/*0702*/ 0x00000005,
-/*0703*/ 0x04000f00,
-/*0704*/ 0x00020080,
-/*0705*/ 0x00020055,
-/*0706*/ 0x00000000,
-/*0707*/ 0x00000000,
-/*0708*/ 0x00000000,
-/*0709*/ 0x00000050,
-/*070a*/ 0x00000000,
-/*070b*/ 0x01010100,
-/*070c*/ 0x00000200,
-/*070d*/ 0x00001102,
-/*070e*/ 0x00000000,
-/*070f*/ 0x000f1f00,
-/*0710*/ 0x0f1f0f1f,
-/*0711*/ 0x0f1f0f1f,
-/*0712*/ 0x00020003,
-/*0713*/ 0x02000200,
-/*0714*/ 0x00000200,
-/*0715*/ 0x00001102,
-/*0716*/ 0x00000064,
-/*0717*/ 0x00000000,
-/*0718*/ 0x00000000,
-/*0719*/ 0x00000502,
-/*071a*/ 0x027f6e00,
-/*071b*/ 0x007f007f,
-/*071c*/ 0x00007f3c,
-/*071d*/ 0x00047f6e,
-/*071e*/ 0x0003154f,
-/*071f*/ 0x0001154f,
-/*0720*/ 0x0001154f,
-/*0721*/ 0x0001154f,
-/*0722*/ 0x0001154f,
-/*0723*/ 0x00003fee,
-/*0724*/ 0x0001154f,
-/*0725*/ 0x00003fee,
-/*0726*/ 0x0001154f,
-/*0727*/ 0x00007f3c,
-/*0728*/ 0x0001154f,
-/*0729*/ 0x00000000,
-/*072a*/ 0x00000000,
-/*072b*/ 0x00000000,
-/*072c*/ 0x65000000,
-/*072d*/ 0x00000000,
-/*072e*/ 0x00000000,
-/*072f*/ 0x00000201,
-/*0730*/ 0x00000000,
-/*0731*/ 0x00000000,
-/*0732*/ 0x00000000,
-/*0733*/ 0x00000000,
-/*0734*/ 0x00000000,
-/*0735*/ 0x00000000,
-/*0736*/ 0x00000000,
-/*0737*/ 0x00000000,
-/*0738*/ 0x00000000,
-/*0739*/ 0x00000000,
-/*073a*/ 0x00000000
+ /*0700*/ 0x00000001,
+ /*0701*/ 0x00000000,
+ /*0702*/ 0x00000005,
+ /*0703*/ 0x04000f00,
+ /*0704*/ 0x00020080,
+ /*0705*/ 0x00020055,
+ /*0706*/ 0x00000000,
+ /*0707*/ 0x00000000,
+ /*0708*/ 0x00000000,
+ /*0709*/ 0x00000050,
+ /*070a*/ 0x00000000,
+ /*070b*/ 0x01010100,
+ /*070c*/ 0x00000200,
+ /*070d*/ 0x00001102,
+ /*070e*/ 0x00000000,
+ /*070f*/ 0x000f1f00,
+ /*0710*/ 0x0f1f0f1f,
+ /*0711*/ 0x0f1f0f1f,
+ /*0712*/ 0x00020003,
+ /*0713*/ 0x02000200,
+ /*0714*/ 0x00000200,
+ /*0715*/ 0x00001102,
+ /*0716*/ 0x00000064,
+ /*0717*/ 0x00000000,
+ /*0718*/ 0x00000000,
+ /*0719*/ 0x00000502,
+ /*071a*/ 0x027f6e00,
+ /*071b*/ 0x007f007f,
+ /*071c*/ 0x00007f3c,
+ /*071d*/ 0x00047f6e,
+ /*071e*/ 0x0003154f,
+ /*071f*/ 0x0001154f,
+ /*0720*/ 0x0001154f,
+ /*0721*/ 0x0001154f,
+ /*0722*/ 0x0001154f,
+ /*0723*/ 0x00003fee,
+ /*0724*/ 0x0001154f,
+ /*0725*/ 0x00003fee,
+ /*0726*/ 0x0001154f,
+ /*0727*/ 0x00007f3c,
+ /*0728*/ 0x0001154f,
+ /*0729*/ 0x00000000,
+ /*072a*/ 0x00000000,
+ /*072b*/ 0x00000000,
+ /*072c*/ 0x65000000,
+ /*072d*/ 0x00000000,
+ /*072e*/ 0x00000000,
+ /*072f*/ 0x00000201,
+ /*0730*/ 0x00000000,
+ /*0731*/ 0x00000000,
+ /*0732*/ 0x00000000,
+ /*0733*/ 0x00000000,
+ /*0734*/ 0x00000000,
+ /*0735*/ 0x00000000,
+ /*0736*/ 0x00000000,
+ /*0737*/ 0x00000000,
+ /*0738*/ 0x00000000,
+ /*0739*/ 0x00000000,
+ /*073a*/ 0x00000000
};
static const uint32_t DDR_PI_REGSET_H3[DDR_PI_REGSET_NUM_H3] = {
-/*0200*/ 0x00000b00,
-/*0201*/ 0x00000100,
-/*0202*/ 0x00000000,
-/*0203*/ 0x0000ffff,
-/*0204*/ 0x00000000,
-/*0205*/ 0x0000ffff,
-/*0206*/ 0x00000000,
-/*0207*/ 0x304cffff,
-/*0208*/ 0x00000200,
-/*0209*/ 0x00000200,
-/*020a*/ 0x00000200,
-/*020b*/ 0x00000200,
-/*020c*/ 0x0000304c,
-/*020d*/ 0x00000200,
-/*020e*/ 0x00000200,
-/*020f*/ 0x00000200,
-/*0210*/ 0x00000200,
-/*0211*/ 0x0000304c,
-/*0212*/ 0x00000200,
-/*0213*/ 0x00000200,
-/*0214*/ 0x00000200,
-/*0215*/ 0x00000200,
-/*0216*/ 0x00010000,
-/*0217*/ 0x00000003,
-/*0218*/ 0x01000001,
-/*0219*/ 0x00000000,
-/*021a*/ 0x00000000,
-/*021b*/ 0x00000000,
-/*021c*/ 0x00000000,
-/*021d*/ 0x00000000,
-/*021e*/ 0x00000000,
-/*021f*/ 0x00000000,
-/*0220*/ 0x00000000,
-/*0221*/ 0x00000000,
-/*0222*/ 0x00000000,
-/*0223*/ 0x00000000,
-/*0224*/ 0x00000000,
-/*0225*/ 0x00000000,
-/*0226*/ 0x00000000,
-/*0227*/ 0x00000000,
-/*0228*/ 0x00000000,
-/*0229*/ 0x0f000101,
-/*022a*/ 0x08492d25,
-/*022b*/ 0x500e0c04,
-/*022c*/ 0x0002500e,
-/*022d*/ 0x00460003,
-/*022e*/ 0x182600cf,
-/*022f*/ 0x182600cf,
-/*0230*/ 0x00000005,
-/*0231*/ 0x00000000,
-/*0232*/ 0x00000000,
-/*0233*/ 0x00000000,
-/*0234*/ 0x00000000,
-/*0235*/ 0x00000000,
-/*0236*/ 0x00000000,
-/*0237*/ 0x00000000,
-/*0238*/ 0x01000000,
-/*0239*/ 0x00040404,
-/*023a*/ 0x01280a00,
-/*023b*/ 0x00000000,
-/*023c*/ 0x000f0000,
-/*023d*/ 0x00001803,
-/*023e*/ 0x00000000,
-/*023f*/ 0x00000000,
-/*0240*/ 0x00060002,
-/*0241*/ 0x00010001,
-/*0242*/ 0x01000101,
-/*0243*/ 0x04020201,
-/*0244*/ 0x00080804,
-/*0245*/ 0x00000000,
-/*0246*/ 0x08030000,
-/*0247*/ 0x15150408,
-/*0248*/ 0x00000000,
-/*0249*/ 0x00000000,
-/*024a*/ 0x00000000,
-/*024b*/ 0x001e0f0f,
-/*024c*/ 0x00000000,
-/*024d*/ 0x01000300,
-/*024e*/ 0x00000000,
-/*024f*/ 0x00000000,
-/*0250*/ 0x01000000,
-/*0251*/ 0x00010101,
-/*0252*/ 0x000e0e0e,
-/*0253*/ 0x000c0c0c,
-/*0254*/ 0x02060601,
-/*0255*/ 0x00000000,
-/*0256*/ 0x00000003,
-/*0257*/ 0x00181703,
-/*0258*/ 0x00280006,
-/*0259*/ 0x00280016,
-/*025a*/ 0x00000016,
-/*025b*/ 0x00000000,
-/*025c*/ 0x00000000,
-/*025d*/ 0x00000000,
-/*025e*/ 0x140a0000,
-/*025f*/ 0x0005010a,
-/*0260*/ 0x03018d03,
-/*0261*/ 0x000a018d,
-/*0262*/ 0x00060100,
-/*0263*/ 0x01000006,
-/*0264*/ 0x018e018e,
-/*0265*/ 0x018e0100,
-/*0266*/ 0x1111018e,
-/*0267*/ 0x10010204,
-/*0268*/ 0x09090650,
-/*0269*/ 0x20110202,
-/*026a*/ 0x00201000,
-/*026b*/ 0x00201000,
-/*026c*/ 0x04041000,
-/*026d*/ 0x18020100,
-/*026e*/ 0x00010118,
-/*026f*/ 0x004b004a,
-/*0270*/ 0x050f0000,
-/*0271*/ 0x0c01021e,
-/*0272*/ 0x34000000,
-/*0273*/ 0x00000000,
-/*0274*/ 0x00000000,
-/*0275*/ 0x00000000,
-/*0276*/ 0x312ed400,
-/*0277*/ 0xd4111132,
-/*0278*/ 0x1132312e,
-/*0279*/ 0x312ed411,
-/*027a*/ 0x00111132,
-/*027b*/ 0x32312ed4,
-/*027c*/ 0x2ed41111,
-/*027d*/ 0x11113231,
-/*027e*/ 0x32312ed4,
-/*027f*/ 0xd4001111,
-/*0280*/ 0x1132312e,
-/*0281*/ 0x312ed411,
-/*0282*/ 0xd4111132,
-/*0283*/ 0x1132312e,
-/*0284*/ 0x2ed40011,
-/*0285*/ 0x11113231,
-/*0286*/ 0x32312ed4,
-/*0287*/ 0x2ed41111,
-/*0288*/ 0x11113231,
-/*0289*/ 0x00020000,
-/*028a*/ 0x018d018d,
-/*028b*/ 0x0c08018d,
-/*028c*/ 0x1f121d22,
-/*028d*/ 0x4301b344,
-/*028e*/ 0x10172006,
-/*028f*/ 0x121d220c,
-/*0290*/ 0x01b3441f,
-/*0291*/ 0x17200643,
-/*0292*/ 0x1d220c10,
-/*0293*/ 0x00001f12,
-/*0294*/ 0x4301b344,
-/*0295*/ 0x10172006,
-/*0296*/ 0x00020002,
-/*0297*/ 0x00020002,
-/*0298*/ 0x00020002,
-/*0299*/ 0x00020002,
-/*029a*/ 0x00020002,
-/*029b*/ 0x00000000,
-/*029c*/ 0x00000000,
-/*029d*/ 0x00000000,
-/*029e*/ 0x00000000,
-/*029f*/ 0x00000000,
-/*02a0*/ 0x00000000,
-/*02a1*/ 0x00000000,
-/*02a2*/ 0x00000000,
-/*02a3*/ 0x00000000,
-/*02a4*/ 0x00000000,
-/*02a5*/ 0x00000000,
-/*02a6*/ 0x00000000,
-/*02a7*/ 0x01000400,
-/*02a8*/ 0x00304c00,
-/*02a9*/ 0x0001e2f8,
-/*02aa*/ 0x0000304c,
-/*02ab*/ 0x0001e2f8,
-/*02ac*/ 0x0000304c,
-/*02ad*/ 0x0001e2f8,
-/*02ae*/ 0x08000000,
-/*02af*/ 0x00000100,
-/*02b0*/ 0x00000000,
-/*02b1*/ 0x00000000,
-/*02b2*/ 0x00000000,
-/*02b3*/ 0x00000000,
-/*02b4*/ 0x00000002
+ /*0200*/ 0x00000b00,
+ /*0201*/ 0x00000100,
+ /*0202*/ 0x00000000,
+ /*0203*/ 0x0000ffff,
+ /*0204*/ 0x00000000,
+ /*0205*/ 0x0000ffff,
+ /*0206*/ 0x00000000,
+ /*0207*/ 0x304cffff,
+ /*0208*/ 0x00000200,
+ /*0209*/ 0x00000200,
+ /*020a*/ 0x00000200,
+ /*020b*/ 0x00000200,
+ /*020c*/ 0x0000304c,
+ /*020d*/ 0x00000200,
+ /*020e*/ 0x00000200,
+ /*020f*/ 0x00000200,
+ /*0210*/ 0x00000200,
+ /*0211*/ 0x0000304c,
+ /*0212*/ 0x00000200,
+ /*0213*/ 0x00000200,
+ /*0214*/ 0x00000200,
+ /*0215*/ 0x00000200,
+ /*0216*/ 0x00010000,
+ /*0217*/ 0x00000003,
+ /*0218*/ 0x01000001,
+ /*0219*/ 0x00000000,
+ /*021a*/ 0x00000000,
+ /*021b*/ 0x00000000,
+ /*021c*/ 0x00000000,
+ /*021d*/ 0x00000000,
+ /*021e*/ 0x00000000,
+ /*021f*/ 0x00000000,
+ /*0220*/ 0x00000000,
+ /*0221*/ 0x00000000,
+ /*0222*/ 0x00000000,
+ /*0223*/ 0x00000000,
+ /*0224*/ 0x00000000,
+ /*0225*/ 0x00000000,
+ /*0226*/ 0x00000000,
+ /*0227*/ 0x00000000,
+ /*0228*/ 0x00000000,
+ /*0229*/ 0x0f000101,
+ /*022a*/ 0x08492d25,
+ /*022b*/ 0x500e0c04,
+ /*022c*/ 0x0002500e,
+ /*022d*/ 0x00460003,
+ /*022e*/ 0x182600cf,
+ /*022f*/ 0x182600cf,
+ /*0230*/ 0x00000005,
+ /*0231*/ 0x00000000,
+ /*0232*/ 0x00000000,
+ /*0233*/ 0x00000000,
+ /*0234*/ 0x00000000,
+ /*0235*/ 0x00000000,
+ /*0236*/ 0x00000000,
+ /*0237*/ 0x00000000,
+ /*0238*/ 0x01000000,
+ /*0239*/ 0x00040404,
+ /*023a*/ 0x01280a00,
+ /*023b*/ 0x00000000,
+ /*023c*/ 0x000f0000,
+ /*023d*/ 0x00001803,
+ /*023e*/ 0x00000000,
+ /*023f*/ 0x00000000,
+ /*0240*/ 0x00060002,
+ /*0241*/ 0x00010001,
+ /*0242*/ 0x01000101,
+ /*0243*/ 0x04020201,
+ /*0244*/ 0x00080804,
+ /*0245*/ 0x00000000,
+ /*0246*/ 0x08030000,
+ /*0247*/ 0x15150408,
+ /*0248*/ 0x00000000,
+ /*0249*/ 0x00000000,
+ /*024a*/ 0x00000000,
+ /*024b*/ 0x001e0f0f,
+ /*024c*/ 0x00000000,
+ /*024d*/ 0x01000300,
+ /*024e*/ 0x00000000,
+ /*024f*/ 0x00000000,
+ /*0250*/ 0x01000000,
+ /*0251*/ 0x00010101,
+ /*0252*/ 0x000e0e0e,
+ /*0253*/ 0x000c0c0c,
+ /*0254*/ 0x02060601,
+ /*0255*/ 0x00000000,
+ /*0256*/ 0x00000003,
+ /*0257*/ 0x00181703,
+ /*0258*/ 0x00280006,
+ /*0259*/ 0x00280016,
+ /*025a*/ 0x00000016,
+ /*025b*/ 0x00000000,
+ /*025c*/ 0x00000000,
+ /*025d*/ 0x00000000,
+ /*025e*/ 0x140a0000,
+ /*025f*/ 0x0005010a,
+ /*0260*/ 0x03018d03,
+ /*0261*/ 0x000a018d,
+ /*0262*/ 0x00060100,
+ /*0263*/ 0x01000006,
+ /*0264*/ 0x018e018e,
+ /*0265*/ 0x018e0100,
+ /*0266*/ 0x1111018e,
+ /*0267*/ 0x10010204,
+ /*0268*/ 0x09090650,
+ /*0269*/ 0x20110202,
+ /*026a*/ 0x00201000,
+ /*026b*/ 0x00201000,
+ /*026c*/ 0x04041000,
+ /*026d*/ 0x18020100,
+ /*026e*/ 0x00010118,
+ /*026f*/ 0x004b004a,
+ /*0270*/ 0x050f0000,
+ /*0271*/ 0x0c01021e,
+ /*0272*/ 0x34000000,
+ /*0273*/ 0x00000000,
+ /*0274*/ 0x00000000,
+ /*0275*/ 0x00000000,
+ /*0276*/ 0x312ed400,
+ /*0277*/ 0xd4111132,
+ /*0278*/ 0x1132312e,
+ /*0279*/ 0x312ed411,
+ /*027a*/ 0x00111132,
+ /*027b*/ 0x32312ed4,
+ /*027c*/ 0x2ed41111,
+ /*027d*/ 0x11113231,
+ /*027e*/ 0x32312ed4,
+ /*027f*/ 0xd4001111,
+ /*0280*/ 0x1132312e,
+ /*0281*/ 0x312ed411,
+ /*0282*/ 0xd4111132,
+ /*0283*/ 0x1132312e,
+ /*0284*/ 0x2ed40011,
+ /*0285*/ 0x11113231,
+ /*0286*/ 0x32312ed4,
+ /*0287*/ 0x2ed41111,
+ /*0288*/ 0x11113231,
+ /*0289*/ 0x00020000,
+ /*028a*/ 0x018d018d,
+ /*028b*/ 0x0c08018d,
+ /*028c*/ 0x1f121d22,
+ /*028d*/ 0x4301b344,
+ /*028e*/ 0x10172006,
+ /*028f*/ 0x121d220c,
+ /*0290*/ 0x01b3441f,
+ /*0291*/ 0x17200643,
+ /*0292*/ 0x1d220c10,
+ /*0293*/ 0x00001f12,
+ /*0294*/ 0x4301b344,
+ /*0295*/ 0x10172006,
+ /*0296*/ 0x00020002,
+ /*0297*/ 0x00020002,
+ /*0298*/ 0x00020002,
+ /*0299*/ 0x00020002,
+ /*029a*/ 0x00020002,
+ /*029b*/ 0x00000000,
+ /*029c*/ 0x00000000,
+ /*029d*/ 0x00000000,
+ /*029e*/ 0x00000000,
+ /*029f*/ 0x00000000,
+ /*02a0*/ 0x00000000,
+ /*02a1*/ 0x00000000,
+ /*02a2*/ 0x00000000,
+ /*02a3*/ 0x00000000,
+ /*02a4*/ 0x00000000,
+ /*02a5*/ 0x00000000,
+ /*02a6*/ 0x00000000,
+ /*02a7*/ 0x01000400,
+ /*02a8*/ 0x00304c00,
+ /*02a9*/ 0x0001e2f8,
+ /*02aa*/ 0x0000304c,
+ /*02ab*/ 0x0001e2f8,
+ /*02ac*/ 0x0000304c,
+ /*02ad*/ 0x0001e2f8,
+ /*02ae*/ 0x08000000,
+ /*02af*/ 0x00000100,
+ /*02b0*/ 0x00000000,
+ /*02b1*/ 0x00000000,
+ /*02b2*/ 0x00000000,
+ /*02b3*/ 0x00000000,
+ /*02b4*/ 0x00000002
};
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h
index 6e4c30e..e5258af 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h
@@ -1,5 +1,6 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,516 +23,516 @@
#define DDR_PHY_ADR_G_REGSET_NUM_H3VER2 79
#define DDR_PI_REGSET_NUM_H3VER2 245
-static const uint32_t
- DDR_PHY_SLICE_REGSET_H3VER2[DDR_PHY_SLICE_REGSET_NUM_H3VER2] = {
-/*0400*/ 0x76543210,
-/*0401*/ 0x0004f008,
-/*0402*/ 0x00020133,
-/*0403*/ 0x00000000,
-/*0404*/ 0x00000000,
-/*0405*/ 0x00010000,
-/*0406*/ 0x016e6e0e,
-/*0407*/ 0x026e6e0e,
-/*0408*/ 0x00010300,
-/*0409*/ 0x04000100,
-/*040a*/ 0x01000000,
-/*040b*/ 0x00000000,
-/*040c*/ 0x00000000,
-/*040d*/ 0x00000100,
-/*040e*/ 0x001700c0,
-/*040f*/ 0x020100b0,
-/*0410*/ 0x00030020,
-/*0411*/ 0x00000000,
-/*0412*/ 0x00000000,
-/*0413*/ 0x00000000,
-/*0414*/ 0x00000000,
-/*0415*/ 0x00000000,
-/*0416*/ 0x00000000,
-/*0417*/ 0x00000000,
-/*0418*/ 0x09000000,
-/*0419*/ 0x04080000,
-/*041a*/ 0x04080400,
-/*041b*/ 0x08000000,
-/*041c*/ 0x0c008007,
-/*041d*/ 0x00000f00,
-/*041e*/ 0x00000100,
-/*041f*/ 0x55aa55aa,
-/*0420*/ 0x33cc33cc,
-/*0421*/ 0x0ff00ff0,
-/*0422*/ 0x0f0ff0f0,
-/*0423*/ 0x00018e38,
-/*0424*/ 0x00000000,
-/*0425*/ 0x00000000,
-/*0426*/ 0x00000000,
-/*0427*/ 0x00000000,
-/*0428*/ 0x00000000,
-/*0429*/ 0x00000000,
-/*042a*/ 0x00000000,
-/*042b*/ 0x00000000,
-/*042c*/ 0x00000000,
-/*042d*/ 0x00000000,
-/*042e*/ 0x00000000,
-/*042f*/ 0x00000000,
-/*0430*/ 0x00000000,
-/*0431*/ 0x00000000,
-/*0432*/ 0x00000000,
-/*0433*/ 0x00000000,
-/*0434*/ 0x00000000,
-/*0435*/ 0x00000000,
-/*0436*/ 0x00000000,
-/*0437*/ 0x00000000,
-/*0438*/ 0x00000104,
-/*0439*/ 0x00082020,
-/*043a*/ 0x08200820,
-/*043b*/ 0x08200820,
-/*043c*/ 0x08200820,
-/*043d*/ 0x08200820,
-/*043e*/ 0x08200820,
-/*043f*/ 0x00000000,
-/*0440*/ 0x00000000,
-/*0441*/ 0x03000300,
-/*0442*/ 0x03000300,
-/*0443*/ 0x03000300,
-/*0444*/ 0x03000300,
-/*0445*/ 0x00000300,
-/*0446*/ 0x00000000,
-/*0447*/ 0x00000000,
-/*0448*/ 0x00000000,
-/*0449*/ 0x00000000,
-/*044a*/ 0x00000000,
-/*044b*/ 0x00a000a0,
-/*044c*/ 0x00a000a0,
-/*044d*/ 0x00a000a0,
-/*044e*/ 0x00a000a0,
-/*044f*/ 0x00a000a0,
-/*0450*/ 0x00a000a0,
-/*0451*/ 0x00a000a0,
-/*0452*/ 0x00a000a0,
-/*0453*/ 0x00a000a0,
-/*0454*/ 0x01040109,
-/*0455*/ 0x00000200,
-/*0456*/ 0x01000000,
-/*0457*/ 0x00000200,
-/*0458*/ 0x00000004,
-/*0459*/ 0x4041a141,
-/*045a*/ 0xc00141a0,
-/*045b*/ 0x0e0000c0,
-/*045c*/ 0x0010000c,
-/*045d*/ 0x063e4208,
-/*045e*/ 0x0f0c180c,
-/*045f*/ 0x00e00140,
-/*0460*/ 0x00000c20
+static const uint32_t DDR_PHY_SLICE_REGSET_H3VER2
+ [DDR_PHY_SLICE_REGSET_NUM_H3VER2] = {
+ /*0400*/ 0x76543210,
+ /*0401*/ 0x0004f008,
+ /*0402*/ 0x00020133,
+ /*0403*/ 0x00000000,
+ /*0404*/ 0x00000000,
+ /*0405*/ 0x00010000,
+ /*0406*/ 0x016e6e0e,
+ /*0407*/ 0x026e6e0e,
+ /*0408*/ 0x00010300,
+ /*0409*/ 0x04000100,
+ /*040a*/ 0x01000000,
+ /*040b*/ 0x00000000,
+ /*040c*/ 0x00000000,
+ /*040d*/ 0x00000100,
+ /*040e*/ 0x001700c0,
+ /*040f*/ 0x020100b0,
+ /*0410*/ 0x00030020,
+ /*0411*/ 0x00000000,
+ /*0412*/ 0x00000000,
+ /*0413*/ 0x00000000,
+ /*0414*/ 0x00000000,
+ /*0415*/ 0x00000000,
+ /*0416*/ 0x00000000,
+ /*0417*/ 0x00000000,
+ /*0418*/ 0x09000000,
+ /*0419*/ 0x04080000,
+ /*041a*/ 0x04080400,
+ /*041b*/ 0x08000000,
+ /*041c*/ 0x0c008007,
+ /*041d*/ 0x00000f00,
+ /*041e*/ 0x00000100,
+ /*041f*/ 0x55aa55aa,
+ /*0420*/ 0x33cc33cc,
+ /*0421*/ 0x0ff00ff0,
+ /*0422*/ 0x0f0ff0f0,
+ /*0423*/ 0x00018e38,
+ /*0424*/ 0x00000000,
+ /*0425*/ 0x00000000,
+ /*0426*/ 0x00000000,
+ /*0427*/ 0x00000000,
+ /*0428*/ 0x00000000,
+ /*0429*/ 0x00000000,
+ /*042a*/ 0x00000000,
+ /*042b*/ 0x00000000,
+ /*042c*/ 0x00000000,
+ /*042d*/ 0x00000000,
+ /*042e*/ 0x00000000,
+ /*042f*/ 0x00000000,
+ /*0430*/ 0x00000000,
+ /*0431*/ 0x00000000,
+ /*0432*/ 0x00000000,
+ /*0433*/ 0x00000000,
+ /*0434*/ 0x00000000,
+ /*0435*/ 0x00000000,
+ /*0436*/ 0x00000000,
+ /*0437*/ 0x00000000,
+ /*0438*/ 0x00000104,
+ /*0439*/ 0x00082020,
+ /*043a*/ 0x08200820,
+ /*043b*/ 0x08200820,
+ /*043c*/ 0x08200820,
+ /*043d*/ 0x08200820,
+ /*043e*/ 0x08200820,
+ /*043f*/ 0x00000000,
+ /*0440*/ 0x00000000,
+ /*0441*/ 0x03000300,
+ /*0442*/ 0x03000300,
+ /*0443*/ 0x03000300,
+ /*0444*/ 0x03000300,
+ /*0445*/ 0x00000300,
+ /*0446*/ 0x00000000,
+ /*0447*/ 0x00000000,
+ /*0448*/ 0x00000000,
+ /*0449*/ 0x00000000,
+ /*044a*/ 0x00000000,
+ /*044b*/ 0x00a000a0,
+ /*044c*/ 0x00a000a0,
+ /*044d*/ 0x00a000a0,
+ /*044e*/ 0x00a000a0,
+ /*044f*/ 0x00a000a0,
+ /*0450*/ 0x00a000a0,
+ /*0451*/ 0x00a000a0,
+ /*0452*/ 0x00a000a0,
+ /*0453*/ 0x00a000a0,
+ /*0454*/ 0x01040109,
+ /*0455*/ 0x00000200,
+ /*0456*/ 0x01000000,
+ /*0457*/ 0x00000200,
+ /*0458*/ 0x00000004,
+ /*0459*/ 0x4041a151,
+ /*045a*/ 0xc00141a0,
+ /*045b*/ 0x0e0000c0,
+ /*045c*/ 0x0010000c,
+ /*045d*/ 0x063e4208,
+ /*045e*/ 0x0f0c180c,
+ /*045f*/ 0x00e00140,
+ /*0460*/ 0x00000c20
};
static const uint32_t
- DDR_PHY_ADR_V_REGSET_H3VER2[DDR_PHY_ADR_V_REGSET_NUM_H3VER2] = {
-/*0600*/ 0x00000000,
-/*0601*/ 0x00000000,
-/*0602*/ 0x00000000,
-/*0603*/ 0x00000000,
-/*0604*/ 0x00000000,
-/*0605*/ 0x00000000,
-/*0606*/ 0x00000000,
-/*0607*/ 0x00010000,
-/*0608*/ 0x00000200,
-/*0609*/ 0x00000000,
-/*060a*/ 0x00000000,
-/*060b*/ 0x00000000,
-/*060c*/ 0x00400320,
-/*060d*/ 0x00000040,
-/*060e*/ 0x00dcba98,
-/*060f*/ 0x03000000,
-/*0610*/ 0x00000200,
-/*0611*/ 0x00000000,
-/*0612*/ 0x00000000,
-/*0613*/ 0x00000000,
-/*0614*/ 0x0000002a,
-/*0615*/ 0x00000015,
-/*0616*/ 0x00000015,
-/*0617*/ 0x0000002a,
-/*0618*/ 0x00000033,
-/*0619*/ 0x0000000c,
-/*061a*/ 0x0000000c,
-/*061b*/ 0x00000033,
-/*061c*/ 0x00418820,
-/*061d*/ 0x003f0000,
-/*061e*/ 0x0000003f,
-/*061f*/ 0x0002c06e,
-/*0620*/ 0x02c002c0,
-/*0621*/ 0x02c002c0,
-/*0622*/ 0x000002c0,
-/*0623*/ 0x42080010,
-/*0624*/ 0x0000033e
+ DDR_PHY_ADR_V_REGSET_H3VER2[DDR_PHY_ADR_V_REGSET_NUM_H3VER2] = {
+ /*0600*/ 0x00000000,
+ /*0601*/ 0x00000000,
+ /*0602*/ 0x00000000,
+ /*0603*/ 0x00000000,
+ /*0604*/ 0x00000000,
+ /*0605*/ 0x00000000,
+ /*0606*/ 0x00000000,
+ /*0607*/ 0x00010000,
+ /*0608*/ 0x00000200,
+ /*0609*/ 0x00000000,
+ /*060a*/ 0x00000000,
+ /*060b*/ 0x00000000,
+ /*060c*/ 0x00400320,
+ /*060d*/ 0x00000040,
+ /*060e*/ 0x00dcba98,
+ /*060f*/ 0x03000000,
+ /*0610*/ 0x00000200,
+ /*0611*/ 0x00000000,
+ /*0612*/ 0x00000000,
+ /*0613*/ 0x00000000,
+ /*0614*/ 0x0000002a,
+ /*0615*/ 0x00000015,
+ /*0616*/ 0x00000015,
+ /*0617*/ 0x0000002a,
+ /*0618*/ 0x00000033,
+ /*0619*/ 0x0000000c,
+ /*061a*/ 0x0000000c,
+ /*061b*/ 0x00000033,
+ /*061c*/ 0x00418820,
+ /*061d*/ 0x003f0000,
+ /*061e*/ 0x0000003f,
+ /*061f*/ 0x0002c06e,
+ /*0620*/ 0x02c002c0,
+ /*0621*/ 0x02c002c0,
+ /*0622*/ 0x000002c0,
+ /*0623*/ 0x42080010,
+ /*0624*/ 0x0000033e
};
static const uint32_t
- DDR_PHY_ADR_I_REGSET_H3VER2[DDR_PHY_ADR_I_REGSET_NUM_H3VER2] = {
-/*0640*/ 0x00000000,
-/*0641*/ 0x00000000,
-/*0642*/ 0x00000000,
-/*0643*/ 0x00000000,
-/*0644*/ 0x00000000,
-/*0645*/ 0x00000000,
-/*0646*/ 0x00000000,
-/*0647*/ 0x00000000,
-/*0648*/ 0x00000000,
-/*0649*/ 0x00000000,
-/*064a*/ 0x00000000,
-/*064b*/ 0x00000000,
-/*064c*/ 0x00000000,
-/*064d*/ 0x00000000,
-/*064e*/ 0x00000000,
-/*064f*/ 0x00000000,
-/*0650*/ 0x00000000,
-/*0651*/ 0x00000000,
-/*0652*/ 0x00000000,
-/*0653*/ 0x00000000,
-/*0654*/ 0x00000000,
-/*0655*/ 0x00000000,
-/*0656*/ 0x00000000,
-/*0657*/ 0x00000000,
-/*0658*/ 0x00000000,
-/*0659*/ 0x00000000,
-/*065a*/ 0x00000000,
-/*065b*/ 0x00000000,
-/*065c*/ 0x00000000,
-/*065d*/ 0x00000000,
-/*065e*/ 0x00000000,
-/*065f*/ 0x00000000,
-/*0660*/ 0x00000000,
-/*0661*/ 0x00000000,
-/*0662*/ 0x00000000,
-/*0663*/ 0x00000000,
-/*0664*/ 0x00000000
+ DDR_PHY_ADR_I_REGSET_H3VER2[DDR_PHY_ADR_I_REGSET_NUM_H3VER2] = {
+ /*0640*/ 0x00000000,
+ /*0641*/ 0x00000000,
+ /*0642*/ 0x00000000,
+ /*0643*/ 0x00000000,
+ /*0644*/ 0x00000000,
+ /*0645*/ 0x00000000,
+ /*0646*/ 0x00000000,
+ /*0647*/ 0x00000000,
+ /*0648*/ 0x00000000,
+ /*0649*/ 0x00000000,
+ /*064a*/ 0x00000000,
+ /*064b*/ 0x00000000,
+ /*064c*/ 0x00000000,
+ /*064d*/ 0x00000000,
+ /*064e*/ 0x00000000,
+ /*064f*/ 0x00000000,
+ /*0650*/ 0x00000000,
+ /*0651*/ 0x00000000,
+ /*0652*/ 0x00000000,
+ /*0653*/ 0x00000000,
+ /*0654*/ 0x00000000,
+ /*0655*/ 0x00000000,
+ /*0656*/ 0x00000000,
+ /*0657*/ 0x00000000,
+ /*0658*/ 0x00000000,
+ /*0659*/ 0x00000000,
+ /*065a*/ 0x00000000,
+ /*065b*/ 0x00000000,
+ /*065c*/ 0x00000000,
+ /*065d*/ 0x00000000,
+ /*065e*/ 0x00000000,
+ /*065f*/ 0x00000000,
+ /*0660*/ 0x00000000,
+ /*0661*/ 0x00000000,
+ /*0662*/ 0x00000000,
+ /*0663*/ 0x00000000,
+ /*0664*/ 0x00000000
};
static const uint32_t
- DDR_PHY_ADR_G_REGSET_H3VER2[DDR_PHY_ADR_G_REGSET_NUM_H3VER2] = {
-/*0680*/ 0x00000000,
-/*0681*/ 0x00000100,
-/*0682*/ 0x00000000,
-/*0683*/ 0x00050000,
-/*0684*/ 0x0f000000,
-/*0685*/ 0x00800400,
-/*0686*/ 0x00020032,
-/*0687*/ 0x00020055,
-/*0688*/ 0x00000000,
-/*0689*/ 0x00000000,
-/*068a*/ 0x00000000,
-/*068b*/ 0x00000050,
-/*068c*/ 0x00000000,
-/*068d*/ 0x01010100,
-/*068e*/ 0x01000200,
-/*068f*/ 0x00000000,
-/*0690*/ 0x00010100,
-/*0691*/ 0x00000000,
-/*0692*/ 0x00000000,
-/*0693*/ 0x00000000,
-/*0694*/ 0x00000000,
-/*0695*/ 0x00005064,
-/*0696*/ 0x01421142,
-/*0697*/ 0x00000142,
-/*0698*/ 0x00000000,
-/*0699*/ 0x000f1100,
-/*069a*/ 0x0f110f11,
-/*069b*/ 0x09000f11,
-/*069c*/ 0x00000003,
-/*069d*/ 0x0002c000,
-/*069e*/ 0x02c002c0,
-/*069f*/ 0x000002c0,
-/*06a0*/ 0x03421342,
-/*06a1*/ 0x00000342,
-/*06a2*/ 0x00000000,
-/*06a3*/ 0x00000000,
-/*06a4*/ 0x05020000,
-/*06a5*/ 0x14000000,
-/*06a6*/ 0x027f6e00,
-/*06a7*/ 0x047f027f,
-/*06a8*/ 0x00027f6e,
-/*06a9*/ 0x00047f6e,
-/*06aa*/ 0x0003554f,
-/*06ab*/ 0x0001554f,
-/*06ac*/ 0x0001554f,
-/*06ad*/ 0x0001554f,
-/*06ae*/ 0x0001554f,
-/*06af*/ 0x00003fee,
-/*06b0*/ 0x0001554f,
-/*06b1*/ 0x00003fee,
-/*06b2*/ 0x0001554f,
-/*06b3*/ 0x00027f6e,
-/*06b4*/ 0x0001554f,
-/*06b5*/ 0x00004011,
-/*06b6*/ 0x00004410,
-/*06b7*/ 0x00000000,
-/*06b8*/ 0x00000000,
-/*06b9*/ 0x00000000,
-/*06ba*/ 0x00000065,
-/*06bb*/ 0x00000000,
-/*06bc*/ 0x00020201,
-/*06bd*/ 0x00000000,
-/*06be*/ 0x03000000,
-/*06bf*/ 0x00000008,
-/*06c0*/ 0x00000000,
-/*06c1*/ 0x00000000,
-/*06c2*/ 0x00000000,
-/*06c3*/ 0x00000000,
-/*06c4*/ 0x00000001,
-/*06c5*/ 0x00000000,
-/*06c6*/ 0x00000000,
-/*06c7*/ 0x00000000,
-/*06c8*/ 0x000000e4,
-/*06c9*/ 0x00010198,
-/*06ca*/ 0x00000000,
-/*06cb*/ 0x00000000,
-/*06cc*/ 0x07010000,
-/*06cd*/ 0x00000104,
-/*06ce*/ 0x00000000
+ DDR_PHY_ADR_G_REGSET_H3VER2[DDR_PHY_ADR_G_REGSET_NUM_H3VER2] = {
+ /*0680*/ 0x00000000,
+ /*0681*/ 0x00000100,
+ /*0682*/ 0x00000000,
+ /*0683*/ 0x00050000,
+ /*0684*/ 0x0f000000,
+ /*0685*/ 0x00800400,
+ /*0686*/ 0x00020032,
+ /*0687*/ 0x00020055,
+ /*0688*/ 0x00000000,
+ /*0689*/ 0x00000000,
+ /*068a*/ 0x00000000,
+ /*068b*/ 0x00000050,
+ /*068c*/ 0x00000000,
+ /*068d*/ 0x01010100,
+ /*068e*/ 0x01000200,
+ /*068f*/ 0x00000000,
+ /*0690*/ 0x00010100,
+ /*0691*/ 0x00000000,
+ /*0692*/ 0x00000000,
+ /*0693*/ 0x00000000,
+ /*0694*/ 0x00000000,
+ /*0695*/ 0x00005064,
+ /*0696*/ 0x01421142,
+ /*0697*/ 0x00000142,
+ /*0698*/ 0x00000000,
+ /*0699*/ 0x000f1100,
+ /*069a*/ 0x0f110f11,
+ /*069b*/ 0x09000f11,
+ /*069c*/ 0x00000003,
+ /*069d*/ 0x0002c000,
+ /*069e*/ 0x02c002c0,
+ /*069f*/ 0x000002c0,
+ /*06a0*/ 0x03421342,
+ /*06a1*/ 0x00000342,
+ /*06a2*/ 0x00000000,
+ /*06a3*/ 0x00000000,
+ /*06a4*/ 0x05020000,
+ /*06a5*/ 0x14000000,
+ /*06a6*/ 0x027f6e00,
+ /*06a7*/ 0x047f027f,
+ /*06a8*/ 0x00027f6e,
+ /*06a9*/ 0x00047f6e,
+ /*06aa*/ 0x0003554f,
+ /*06ab*/ 0x0001554f,
+ /*06ac*/ 0x0001554f,
+ /*06ad*/ 0x0001554f,
+ /*06ae*/ 0x0001554f,
+ /*06af*/ 0x00003fee,
+ /*06b0*/ 0x0001554f,
+ /*06b1*/ 0x00003fee,
+ /*06b2*/ 0x0001554f,
+ /*06b3*/ 0x00027f6e,
+ /*06b4*/ 0x0001554f,
+ /*06b5*/ 0x00004011,
+ /*06b6*/ 0x00004410,
+ /*06b7*/ 0x00000000,
+ /*06b8*/ 0x00000000,
+ /*06b9*/ 0x00000000,
+ /*06ba*/ 0x00000065,
+ /*06bb*/ 0x00000000,
+ /*06bc*/ 0x00020201,
+ /*06bd*/ 0x00000000,
+ /*06be*/ 0x03000000,
+ /*06bf*/ 0x00000008,
+ /*06c0*/ 0x00000000,
+ /*06c1*/ 0x00000000,
+ /*06c2*/ 0x00000000,
+ /*06c3*/ 0x00000000,
+ /*06c4*/ 0x00000001,
+ /*06c5*/ 0x00000000,
+ /*06c6*/ 0x00000000,
+ /*06c7*/ 0x00000000,
+ /*06c8*/ 0x000000e4,
+ /*06c9*/ 0x00010198,
+ /*06ca*/ 0x00000000,
+ /*06cb*/ 0x00000000,
+ /*06cc*/ 0x07010000,
+ /*06cd*/ 0x00000104,
+ /*06ce*/ 0x00000000
};
static const uint32_t DDR_PI_REGSET_H3VER2[DDR_PI_REGSET_NUM_H3VER2] = {
-/*0200*/ 0x00000b00,
-/*0201*/ 0x00000100,
-/*0202*/ 0x00640000,
-/*0203*/ 0x00000000,
-/*0204*/ 0x0000ffff,
-/*0205*/ 0x00000000,
-/*0206*/ 0x0000ffff,
-/*0207*/ 0x00000000,
-/*0208*/ 0x0000ffff,
-/*0209*/ 0x0000304c,
-/*020a*/ 0x00000200,
-/*020b*/ 0x00000200,
-/*020c*/ 0x00000200,
-/*020d*/ 0x00000200,
-/*020e*/ 0x0000304c,
-/*020f*/ 0x00000200,
-/*0210*/ 0x00000200,
-/*0211*/ 0x00000200,
-/*0212*/ 0x00000200,
-/*0213*/ 0x0000304c,
-/*0214*/ 0x00000200,
-/*0215*/ 0x00000200,
-/*0216*/ 0x00000200,
-/*0217*/ 0x00000200,
-/*0218*/ 0x00010000,
-/*0219*/ 0x00000003,
-/*021a*/ 0x01000001,
-/*021b*/ 0x00000000,
-/*021c*/ 0x00000000,
-/*021d*/ 0x00000000,
-/*021e*/ 0x00000000,
-/*021f*/ 0x00000000,
-/*0220*/ 0x00000000,
-/*0221*/ 0x00000000,
-/*0222*/ 0x00000000,
-/*0223*/ 0x00000000,
-/*0224*/ 0x00000000,
-/*0225*/ 0x00000000,
-/*0226*/ 0x00000000,
-/*0227*/ 0x00000000,
-/*0228*/ 0x00000000,
-/*0229*/ 0x00000000,
-/*022a*/ 0x00000000,
-/*022b*/ 0x0f000101,
-/*022c*/ 0x08492d25,
-/*022d*/ 0x500e0c04,
-/*022e*/ 0x0002500e,
-/*022f*/ 0x00000301,
-/*0230*/ 0x00000046,
-/*0231*/ 0x000000cf,
-/*0232*/ 0x00001826,
-/*0233*/ 0x000000cf,
-/*0234*/ 0x00001826,
-/*0235*/ 0x00000005,
-/*0236*/ 0x00000000,
-/*0237*/ 0x00000000,
-/*0238*/ 0x00000000,
-/*0239*/ 0x00000000,
-/*023a*/ 0x00000000,
-/*023b*/ 0x00000000,
-/*023c*/ 0x00000000,
-/*023d*/ 0x00000000,
-/*023e*/ 0x04010000,
-/*023f*/ 0x00000404,
-/*0240*/ 0x0101280a,
-/*0241*/ 0x00000000,
-/*0242*/ 0x00000000,
-/*0243*/ 0x0003000f,
-/*0244*/ 0x00000018,
-/*0245*/ 0x00000000,
-/*0246*/ 0x00000000,
-/*0247*/ 0x00060002,
-/*0248*/ 0x00010001,
-/*0249*/ 0x01000101,
-/*024a*/ 0x04020201,
-/*024b*/ 0x00080804,
-/*024c*/ 0x00000000,
-/*024d*/ 0x08030000,
-/*024e*/ 0x15150408,
-/*024f*/ 0x00000000,
-/*0250*/ 0x00000000,
-/*0251*/ 0x00000000,
-/*0252*/ 0x0f0f0000,
-/*0253*/ 0x0000001e,
-/*0254*/ 0x00000000,
-/*0255*/ 0x01000300,
-/*0256*/ 0x00000100,
-/*0257*/ 0x00000000,
-/*0258*/ 0x00000000,
-/*0259*/ 0x01000000,
-/*025a*/ 0x00000101,
-/*025b*/ 0x55555a5a,
-/*025c*/ 0x55555a5a,
-/*025d*/ 0x55555a5a,
-/*025e*/ 0x55555a5a,
-/*025f*/ 0x0e0e0001,
-/*0260*/ 0x0c0c000e,
-/*0261*/ 0x0601000c,
-/*0262*/ 0x17170106,
-/*0263*/ 0x00020202,
-/*0264*/ 0x03000000,
-/*0265*/ 0x00000000,
-/*0266*/ 0x00181703,
-/*0267*/ 0x00280006,
-/*0268*/ 0x00280016,
-/*0269*/ 0x00000016,
-/*026a*/ 0x00000000,
-/*026b*/ 0x00000000,
-/*026c*/ 0x00000000,
-/*026d*/ 0x0a000000,
-/*026e*/ 0x00010a14,
-/*026f*/ 0x00030005,
-/*0270*/ 0x0003018d,
-/*0271*/ 0x000a018d,
-/*0272*/ 0x00060100,
-/*0273*/ 0x01000006,
-/*0274*/ 0x018e018e,
-/*0275*/ 0x018e0100,
-/*0276*/ 0x1111018e,
-/*0277*/ 0x10010204,
-/*0278*/ 0x09090650,
-/*0279*/ 0xff110202,
-/*027a*/ 0x00ff1000,
-/*027b*/ 0x00ff1000,
-/*027c*/ 0x04041000,
-/*027d*/ 0x18020100,
-/*027e*/ 0x01010018,
-/*027f*/ 0x004a004a,
-/*0280*/ 0x004b004a,
-/*0281*/ 0x050f0000,
-/*0282*/ 0x0c01021e,
-/*0283*/ 0x34000000,
-/*0284*/ 0x00000000,
-/*0285*/ 0x00000000,
-/*0286*/ 0x00000000,
-/*0287*/ 0x00000000,
-/*0288*/ 0x36312ed4,
-/*0289*/ 0x2ed41111,
-/*028a*/ 0x11113631,
-/*028b*/ 0x36312ed4,
-/*028c*/ 0xd4001111,
-/*028d*/ 0x1136312e,
-/*028e*/ 0x312ed411,
-/*028f*/ 0xd4111136,
-/*0290*/ 0x1136312e,
-/*0291*/ 0x2ed40011,
-/*0292*/ 0x11113631,
-/*0293*/ 0x36312ed4,
-/*0294*/ 0x2ed41111,
-/*0295*/ 0x11113631,
-/*0296*/ 0x312ed400,
-/*0297*/ 0xd4111136,
-/*0298*/ 0x1136312e,
-/*0299*/ 0x312ed411,
-/*029a*/ 0x00111136,
-/*029b*/ 0x018d0200,
-/*029c*/ 0x018d018d,
-/*029d*/ 0x1d220c08,
-/*029e*/ 0x00001f12,
-/*029f*/ 0x4301b344,
-/*02a0*/ 0x10172006,
-/*02a1*/ 0x121d220c,
-/*02a2*/ 0x01b3441f,
-/*02a3*/ 0x17200643,
-/*02a4*/ 0x1d220c10,
-/*02a5*/ 0x00001f12,
-/*02a6*/ 0x4301b344,
-/*02a7*/ 0x10172006,
-/*02a8*/ 0x00020002,
-/*02a9*/ 0x00020002,
-/*02aa*/ 0x00020002,
-/*02ab*/ 0x00020002,
-/*02ac*/ 0x00020002,
-/*02ad*/ 0x00000000,
-/*02ae*/ 0x00000000,
-/*02af*/ 0x00000000,
-/*02b0*/ 0x00000000,
-/*02b1*/ 0x00000000,
-/*02b2*/ 0x00000000,
-/*02b3*/ 0x00000000,
-/*02b4*/ 0x00000000,
-/*02b5*/ 0x00000000,
-/*02b6*/ 0x00000000,
-/*02b7*/ 0x00000000,
-/*02b8*/ 0x00000000,
-/*02b9*/ 0x00000400,
-/*02ba*/ 0x05040302,
-/*02bb*/ 0x01000f0e,
-/*02bc*/ 0x07060504,
-/*02bd*/ 0x03020100,
-/*02be*/ 0x02010000,
-/*02bf*/ 0x00000103,
-/*02c0*/ 0x0000304c,
-/*02c1*/ 0x0001e2f8,
-/*02c2*/ 0x0000304c,
-/*02c3*/ 0x0001e2f8,
-/*02c4*/ 0x0000304c,
-/*02c5*/ 0x0001e2f8,
-/*02c6*/ 0x08000000,
-/*02c7*/ 0x00000100,
-/*02c8*/ 0x00000000,
-/*02c9*/ 0x00000000,
-/*02ca*/ 0x00000000,
-/*02cb*/ 0x00000000,
-/*02cc*/ 0x00010000,
-/*02cd*/ 0x00000000,
-/*02ce*/ 0x00000000,
-/*02cf*/ 0x00000000,
-/*02d0*/ 0x00000000,
-/*02d1*/ 0x00000000,
-/*02d2*/ 0x00000000,
-/*02d3*/ 0x00000000,
-/*02d4*/ 0x00000000,
-/*02d5*/ 0x00000000,
-/*02d6*/ 0x00000000,
-/*02d7*/ 0x00000000,
-/*02d8*/ 0x00000000,
-/*02d9*/ 0x00000000,
-/*02da*/ 0x00000000,
-/*02db*/ 0x00000000,
-/*02dc*/ 0x00000000,
-/*02dd*/ 0x00000000,
-/*02de*/ 0x00000000,
-/*02df*/ 0x00000000,
-/*02e0*/ 0x00000000,
-/*02e1*/ 0x00000000,
-/*02e2*/ 0x00000000,
-/*02e3*/ 0x00000000,
-/*02e4*/ 0x00000000,
-/*02e5*/ 0x00000000,
-/*02e6*/ 0x00000000,
-/*02e7*/ 0x00000000,
-/*02e8*/ 0x00000000,
-/*02e9*/ 0x00000000,
-/*02ea*/ 0x00000000,
-/*02eb*/ 0x00000000,
-/*02ec*/ 0x00000000,
-/*02ed*/ 0x00000000,
-/*02ee*/ 0x00000002,
-/*02ef*/ 0x00000000,
-/*02f0*/ 0x00000000,
-/*02f1*/ 0x00000000,
-/*02f2*/ 0x00000000,
-/*02f3*/ 0x00000000,
-/*02f4*/ 0x00000000
+ /*0200*/ 0x00000b00,
+ /*0201*/ 0x00000100,
+ /*0202*/ 0x00640000,
+ /*0203*/ 0x00000000,
+ /*0204*/ 0x0000ffff,
+ /*0205*/ 0x00000000,
+ /*0206*/ 0x0000ffff,
+ /*0207*/ 0x00000000,
+ /*0208*/ 0x0000ffff,
+ /*0209*/ 0x0000304c,
+ /*020a*/ 0x00000200,
+ /*020b*/ 0x00000200,
+ /*020c*/ 0x00000200,
+ /*020d*/ 0x00000200,
+ /*020e*/ 0x0000304c,
+ /*020f*/ 0x00000200,
+ /*0210*/ 0x00000200,
+ /*0211*/ 0x00000200,
+ /*0212*/ 0x00000200,
+ /*0213*/ 0x0000304c,
+ /*0214*/ 0x00000200,
+ /*0215*/ 0x00000200,
+ /*0216*/ 0x00000200,
+ /*0217*/ 0x00000200,
+ /*0218*/ 0x00010000,
+ /*0219*/ 0x00000003,
+ /*021a*/ 0x01000001,
+ /*021b*/ 0x00000000,
+ /*021c*/ 0x00000000,
+ /*021d*/ 0x00000000,
+ /*021e*/ 0x00000000,
+ /*021f*/ 0x00000000,
+ /*0220*/ 0x00000000,
+ /*0221*/ 0x00000000,
+ /*0222*/ 0x00000000,
+ /*0223*/ 0x00000000,
+ /*0224*/ 0x00000000,
+ /*0225*/ 0x00000000,
+ /*0226*/ 0x00000000,
+ /*0227*/ 0x00000000,
+ /*0228*/ 0x00000000,
+ /*0229*/ 0x00000000,
+ /*022a*/ 0x00000000,
+ /*022b*/ 0x0f000101,
+ /*022c*/ 0x08492d25,
+ /*022d*/ 0x500e0c04,
+ /*022e*/ 0x0002500e,
+ /*022f*/ 0x00000301,
+ /*0230*/ 0x00000046,
+ /*0231*/ 0x000000cf,
+ /*0232*/ 0x00001826,
+ /*0233*/ 0x000000cf,
+ /*0234*/ 0x00001826,
+ /*0235*/ 0x00000005,
+ /*0236*/ 0x00000000,
+ /*0237*/ 0x00000000,
+ /*0238*/ 0x00000000,
+ /*0239*/ 0x00000000,
+ /*023a*/ 0x00000000,
+ /*023b*/ 0x00000000,
+ /*023c*/ 0x00000000,
+ /*023d*/ 0x00000000,
+ /*023e*/ 0x04010000,
+ /*023f*/ 0x00000404,
+ /*0240*/ 0x0101280a,
+ /*0241*/ 0x00000000,
+ /*0242*/ 0x00000000,
+ /*0243*/ 0x0003000f,
+ /*0244*/ 0x00000018,
+ /*0245*/ 0x00000000,
+ /*0246*/ 0x00000000,
+ /*0247*/ 0x00060002,
+ /*0248*/ 0x00010001,
+ /*0249*/ 0x01000101,
+ /*024a*/ 0x04020201,
+ /*024b*/ 0x00080804,
+ /*024c*/ 0x00000000,
+ /*024d*/ 0x08030000,
+ /*024e*/ 0x15150408,
+ /*024f*/ 0x00000000,
+ /*0250*/ 0x00000000,
+ /*0251*/ 0x00000000,
+ /*0252*/ 0x0f0f0000,
+ /*0253*/ 0x0000001e,
+ /*0254*/ 0x00000000,
+ /*0255*/ 0x01000300,
+ /*0256*/ 0x00000100,
+ /*0257*/ 0x00000000,
+ /*0258*/ 0x00000000,
+ /*0259*/ 0x01000000,
+ /*025a*/ 0x00000101,
+ /*025b*/ 0x55555a5a,
+ /*025c*/ 0x55555a5a,
+ /*025d*/ 0x55555a5a,
+ /*025e*/ 0x55555a5a,
+ /*025f*/ 0x0e0e0001,
+ /*0260*/ 0x0c0c000e,
+ /*0261*/ 0x0601000c,
+ /*0262*/ 0x17170106,
+ /*0263*/ 0x00020202,
+ /*0264*/ 0x03000000,
+ /*0265*/ 0x00000000,
+ /*0266*/ 0x00181703,
+ /*0267*/ 0x00280006,
+ /*0268*/ 0x00280016,
+ /*0269*/ 0x00000016,
+ /*026a*/ 0x00000000,
+ /*026b*/ 0x00000000,
+ /*026c*/ 0x00000000,
+ /*026d*/ 0x0a000000,
+ /*026e*/ 0x00010a14,
+ /*026f*/ 0x00030005,
+ /*0270*/ 0x0003018d,
+ /*0271*/ 0x000a018d,
+ /*0272*/ 0x00060100,
+ /*0273*/ 0x01000006,
+ /*0274*/ 0x018e018e,
+ /*0275*/ 0x018e0100,
+ /*0276*/ 0x1111018e,
+ /*0277*/ 0x10010204,
+ /*0278*/ 0x09090650,
+ /*0279*/ 0xff110202,
+ /*027a*/ 0x00ff1000,
+ /*027b*/ 0x00ff1000,
+ /*027c*/ 0x04041000,
+ /*027d*/ 0x18020100,
+ /*027e*/ 0x01010018,
+ /*027f*/ 0x004a004a,
+ /*0280*/ 0x004b004a,
+ /*0281*/ 0x050f0000,
+ /*0282*/ 0x0c01021e,
+ /*0283*/ 0x34000000,
+ /*0284*/ 0x00000000,
+ /*0285*/ 0x00000000,
+ /*0286*/ 0x00000000,
+ /*0287*/ 0x00000000,
+ /*0288*/ 0x36312ed4,
+ /*0289*/ 0x2ed41111,
+ /*028a*/ 0x11113631,
+ /*028b*/ 0x36312ed4,
+ /*028c*/ 0xd4001111,
+ /*028d*/ 0x1136312e,
+ /*028e*/ 0x312ed411,
+ /*028f*/ 0xd4111136,
+ /*0290*/ 0x1136312e,
+ /*0291*/ 0x2ed40011,
+ /*0292*/ 0x11113631,
+ /*0293*/ 0x36312ed4,
+ /*0294*/ 0x2ed41111,
+ /*0295*/ 0x11113631,
+ /*0296*/ 0x312ed400,
+ /*0297*/ 0xd4111136,
+ /*0298*/ 0x1136312e,
+ /*0299*/ 0x312ed411,
+ /*029a*/ 0x00111136,
+ /*029b*/ 0x018d0200,
+ /*029c*/ 0x018d018d,
+ /*029d*/ 0x1d220c08,
+ /*029e*/ 0x00001f12,
+ /*029f*/ 0x4301b344,
+ /*02a0*/ 0x10172006,
+ /*02a1*/ 0x121d220c,
+ /*02a2*/ 0x01b3441f,
+ /*02a3*/ 0x17200643,
+ /*02a4*/ 0x1d220c10,
+ /*02a5*/ 0x00001f12,
+ /*02a6*/ 0x4301b344,
+ /*02a7*/ 0x10172006,
+ /*02a8*/ 0x00020002,
+ /*02a9*/ 0x00020002,
+ /*02aa*/ 0x00020002,
+ /*02ab*/ 0x00020002,
+ /*02ac*/ 0x00020002,
+ /*02ad*/ 0x00000000,
+ /*02ae*/ 0x00000000,
+ /*02af*/ 0x00000000,
+ /*02b0*/ 0x00000000,
+ /*02b1*/ 0x00000000,
+ /*02b2*/ 0x00000000,
+ /*02b3*/ 0x00000000,
+ /*02b4*/ 0x00000000,
+ /*02b5*/ 0x00000000,
+ /*02b6*/ 0x00000000,
+ /*02b7*/ 0x00000000,
+ /*02b8*/ 0x00000000,
+ /*02b9*/ 0x00000400,
+ /*02ba*/ 0x05040302,
+ /*02bb*/ 0x01000f0e,
+ /*02bc*/ 0x07060504,
+ /*02bd*/ 0x03020100,
+ /*02be*/ 0x02010000,
+ /*02bf*/ 0x00000103,
+ /*02c0*/ 0x0000304c,
+ /*02c1*/ 0x0001e2f8,
+ /*02c2*/ 0x0000304c,
+ /*02c3*/ 0x0001e2f8,
+ /*02c4*/ 0x0000304c,
+ /*02c5*/ 0x0001e2f8,
+ /*02c6*/ 0x08000000,
+ /*02c7*/ 0x00000100,
+ /*02c8*/ 0x00000000,
+ /*02c9*/ 0x00000000,
+ /*02ca*/ 0x00000000,
+ /*02cb*/ 0x00000000,
+ /*02cc*/ 0x00010000,
+ /*02cd*/ 0x00000000,
+ /*02ce*/ 0x00000000,
+ /*02cf*/ 0x00000000,
+ /*02d0*/ 0x00000000,
+ /*02d1*/ 0x00000000,
+ /*02d2*/ 0x00000000,
+ /*02d3*/ 0x00000000,
+ /*02d4*/ 0x00000000,
+ /*02d5*/ 0x00000000,
+ /*02d6*/ 0x00000000,
+ /*02d7*/ 0x00000000,
+ /*02d8*/ 0x00000000,
+ /*02d9*/ 0x00000000,
+ /*02da*/ 0x00000000,
+ /*02db*/ 0x00000000,
+ /*02dc*/ 0x00000000,
+ /*02dd*/ 0x00000000,
+ /*02de*/ 0x00000000,
+ /*02df*/ 0x00000000,
+ /*02e0*/ 0x00000000,
+ /*02e1*/ 0x00000000,
+ /*02e2*/ 0x00000000,
+ /*02e3*/ 0x00000000,
+ /*02e4*/ 0x00000000,
+ /*02e5*/ 0x00000000,
+ /*02e6*/ 0x00000000,
+ /*02e7*/ 0x00000000,
+ /*02e8*/ 0x00000000,
+ /*02e9*/ 0x00000000,
+ /*02ea*/ 0x00000000,
+ /*02eb*/ 0x00000000,
+ /*02ec*/ 0x00000000,
+ /*02ed*/ 0x00000000,
+ /*02ee*/ 0x00000002,
+ /*02ef*/ 0x00000000,
+ /*02f0*/ 0x00000000,
+ /*02f1*/ 0x00000000,
+ /*02f2*/ 0x00000000,
+ /*02f3*/ 0x00000000,
+ /*02f4*/ 0x00000000
};
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h
index 3c62107..b491f0e 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h
@@ -1,5 +1,6 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -23,445 +24,445 @@
#define DDR_PI_REGSET_NUM_M3 202
static const uint32_t DDR_PHY_SLICE_REGSET_M3[DDR_PHY_SLICE_REGSET_NUM_M3] = {
-/*0800*/ 0x76543210,
-/*0801*/ 0x0004f008,
-/*0802*/ 0x00000000,
-/*0803*/ 0x00000000,
-/*0804*/ 0x00010000,
-/*0805*/ 0x036e6e0e,
-/*0806*/ 0x026e6e0e,
-/*0807*/ 0x00010300,
-/*0808*/ 0x04000100,
-/*0809*/ 0x00000300,
-/*080a*/ 0x001700c0,
-/*080b*/ 0x00b00201,
-/*080c*/ 0x00030020,
-/*080d*/ 0x00000000,
-/*080e*/ 0x00000000,
-/*080f*/ 0x00000000,
-/*0810*/ 0x00000000,
-/*0811*/ 0x00000000,
-/*0812*/ 0x00000000,
-/*0813*/ 0x00000000,
-/*0814*/ 0x09000000,
-/*0815*/ 0x04080000,
-/*0816*/ 0x04080400,
-/*0817*/ 0x00000000,
-/*0818*/ 0x32103210,
-/*0819*/ 0x00800708,
-/*081a*/ 0x000f000c,
-/*081b*/ 0x00000100,
-/*081c*/ 0x55aa55aa,
-/*081d*/ 0x33cc33cc,
-/*081e*/ 0x0ff00ff0,
-/*081f*/ 0x0f0ff0f0,
-/*0820*/ 0x00018e38,
-/*0821*/ 0x00000000,
-/*0822*/ 0x00000000,
-/*0823*/ 0x00000000,
-/*0824*/ 0x00000000,
-/*0825*/ 0x00000000,
-/*0826*/ 0x00000000,
-/*0827*/ 0x00000000,
-/*0828*/ 0x00000000,
-/*0829*/ 0x00000000,
-/*082a*/ 0x00000000,
-/*082b*/ 0x00000000,
-/*082c*/ 0x00000000,
-/*082d*/ 0x00000000,
-/*082e*/ 0x00000000,
-/*082f*/ 0x00000000,
-/*0830*/ 0x00000000,
-/*0831*/ 0x00000000,
-/*0832*/ 0x00000000,
-/*0833*/ 0x00200000,
-/*0834*/ 0x08200820,
-/*0835*/ 0x08200820,
-/*0836*/ 0x08200820,
-/*0837*/ 0x08200820,
-/*0838*/ 0x08200820,
-/*0839*/ 0x00000820,
-/*083a*/ 0x03000300,
-/*083b*/ 0x03000300,
-/*083c*/ 0x03000300,
-/*083d*/ 0x03000300,
-/*083e*/ 0x00000300,
-/*083f*/ 0x00000000,
-/*0840*/ 0x00000000,
-/*0841*/ 0x00000000,
-/*0842*/ 0x00000000,
-/*0843*/ 0x00a00000,
-/*0844*/ 0x00a000a0,
-/*0845*/ 0x00a000a0,
-/*0846*/ 0x00a000a0,
-/*0847*/ 0x00a000a0,
-/*0848*/ 0x00a000a0,
-/*0849*/ 0x00a000a0,
-/*084a*/ 0x00a000a0,
-/*084b*/ 0x00a000a0,
-/*084c*/ 0x010900a0,
-/*084d*/ 0x02000104,
-/*084e*/ 0x00000000,
-/*084f*/ 0x00010000,
-/*0850*/ 0x00000200,
-/*0851*/ 0x4041a141,
-/*0852*/ 0xc00141a0,
-/*0853*/ 0x0e0100c0,
-/*0854*/ 0x0010000c,
-/*0855*/ 0x0c064208,
-/*0856*/ 0x000f0c18,
-/*0857*/ 0x00e00140,
-/*0858*/ 0x00000c20
+ /*0800*/ 0x76543210,
+ /*0801*/ 0x0004f008,
+ /*0802*/ 0x00000000,
+ /*0803*/ 0x00000000,
+ /*0804*/ 0x00010000,
+ /*0805*/ 0x036e6e0e,
+ /*0806*/ 0x026e6e0e,
+ /*0807*/ 0x00010300,
+ /*0808*/ 0x04000100,
+ /*0809*/ 0x00000300,
+ /*080a*/ 0x001700c0,
+ /*080b*/ 0x00b00201,
+ /*080c*/ 0x00030020,
+ /*080d*/ 0x00000000,
+ /*080e*/ 0x00000000,
+ /*080f*/ 0x00000000,
+ /*0810*/ 0x00000000,
+ /*0811*/ 0x00000000,
+ /*0812*/ 0x00000000,
+ /*0813*/ 0x00000000,
+ /*0814*/ 0x09000000,
+ /*0815*/ 0x04080000,
+ /*0816*/ 0x04080400,
+ /*0817*/ 0x00000000,
+ /*0818*/ 0x32103210,
+ /*0819*/ 0x00800708,
+ /*081a*/ 0x000f000c,
+ /*081b*/ 0x00000100,
+ /*081c*/ 0x55aa55aa,
+ /*081d*/ 0x33cc33cc,
+ /*081e*/ 0x0ff00ff0,
+ /*081f*/ 0x0f0ff0f0,
+ /*0820*/ 0x00018e38,
+ /*0821*/ 0x00000000,
+ /*0822*/ 0x00000000,
+ /*0823*/ 0x00000000,
+ /*0824*/ 0x00000000,
+ /*0825*/ 0x00000000,
+ /*0826*/ 0x00000000,
+ /*0827*/ 0x00000000,
+ /*0828*/ 0x00000000,
+ /*0829*/ 0x00000000,
+ /*082a*/ 0x00000000,
+ /*082b*/ 0x00000000,
+ /*082c*/ 0x00000000,
+ /*082d*/ 0x00000000,
+ /*082e*/ 0x00000000,
+ /*082f*/ 0x00000000,
+ /*0830*/ 0x00000000,
+ /*0831*/ 0x00000000,
+ /*0832*/ 0x00000000,
+ /*0833*/ 0x00200000,
+ /*0834*/ 0x08200820,
+ /*0835*/ 0x08200820,
+ /*0836*/ 0x08200820,
+ /*0837*/ 0x08200820,
+ /*0838*/ 0x08200820,
+ /*0839*/ 0x00000820,
+ /*083a*/ 0x03000300,
+ /*083b*/ 0x03000300,
+ /*083c*/ 0x03000300,
+ /*083d*/ 0x03000300,
+ /*083e*/ 0x00000300,
+ /*083f*/ 0x00000000,
+ /*0840*/ 0x00000000,
+ /*0841*/ 0x00000000,
+ /*0842*/ 0x00000000,
+ /*0843*/ 0x00a00000,
+ /*0844*/ 0x00a000a0,
+ /*0845*/ 0x00a000a0,
+ /*0846*/ 0x00a000a0,
+ /*0847*/ 0x00a000a0,
+ /*0848*/ 0x00a000a0,
+ /*0849*/ 0x00a000a0,
+ /*084a*/ 0x00a000a0,
+ /*084b*/ 0x00a000a0,
+ /*084c*/ 0x010900a0,
+ /*084d*/ 0x02000104,
+ /*084e*/ 0x00000000,
+ /*084f*/ 0x00010000,
+ /*0850*/ 0x00000200,
+ /*0851*/ 0x4041a151,
+ /*0852*/ 0xc00141a0,
+ /*0853*/ 0x0e0100c0,
+ /*0854*/ 0x0010000c,
+ /*0855*/ 0x0c064208,
+ /*0856*/ 0x000f0c18,
+ /*0857*/ 0x00e00140,
+ /*0858*/ 0x00000c20
};
static const uint32_t DDR_PHY_ADR_V_REGSET_M3[DDR_PHY_ADR_V_REGSET_NUM_M3] = {
-/*0a00*/ 0x00000000,
-/*0a01*/ 0x00000000,
-/*0a02*/ 0x00000000,
-/*0a03*/ 0x00000000,
-/*0a04*/ 0x00000000,
-/*0a05*/ 0x00000000,
-/*0a06*/ 0x00000002,
-/*0a07*/ 0x00000000,
-/*0a08*/ 0x00000000,
-/*0a09*/ 0x00000000,
-/*0a0a*/ 0x00400320,
-/*0a0b*/ 0x00000040,
-/*0a0c*/ 0x00dcba98,
-/*0a0d*/ 0x00000000,
-/*0a0e*/ 0x00dcba98,
-/*0a0f*/ 0x01000000,
-/*0a10*/ 0x00020003,
-/*0a11*/ 0x00000000,
-/*0a12*/ 0x00000000,
-/*0a13*/ 0x00000000,
-/*0a14*/ 0x0000002a,
-/*0a15*/ 0x00000015,
-/*0a16*/ 0x00000015,
-/*0a17*/ 0x0000002a,
-/*0a18*/ 0x00000033,
-/*0a19*/ 0x0000000c,
-/*0a1a*/ 0x0000000c,
-/*0a1b*/ 0x00000033,
-/*0a1c*/ 0x0a418820,
-/*0a1d*/ 0x003f0000,
-/*0a1e*/ 0x0000003f,
-/*0a1f*/ 0x0002c06e,
-/*0a20*/ 0x02c002c0,
-/*0a21*/ 0x02c002c0,
-/*0a22*/ 0x000002c0,
-/*0a23*/ 0x42080010,
-/*0a24*/ 0x00000003
+ /*0a00*/ 0x00000000,
+ /*0a01*/ 0x00000000,
+ /*0a02*/ 0x00000000,
+ /*0a03*/ 0x00000000,
+ /*0a04*/ 0x00000000,
+ /*0a05*/ 0x00000000,
+ /*0a06*/ 0x00000002,
+ /*0a07*/ 0x00000000,
+ /*0a08*/ 0x00000000,
+ /*0a09*/ 0x00000000,
+ /*0a0a*/ 0x00400320,
+ /*0a0b*/ 0x00000040,
+ /*0a0c*/ 0x00dcba98,
+ /*0a0d*/ 0x00000000,
+ /*0a0e*/ 0x00dcba98,
+ /*0a0f*/ 0x01000000,
+ /*0a10*/ 0x00020003,
+ /*0a11*/ 0x00000000,
+ /*0a12*/ 0x00000000,
+ /*0a13*/ 0x00000000,
+ /*0a14*/ 0x0000002a,
+ /*0a15*/ 0x00000015,
+ /*0a16*/ 0x00000015,
+ /*0a17*/ 0x0000002a,
+ /*0a18*/ 0x00000033,
+ /*0a19*/ 0x0000000c,
+ /*0a1a*/ 0x0000000c,
+ /*0a1b*/ 0x00000033,
+ /*0a1c*/ 0x0a418820,
+ /*0a1d*/ 0x003f0000,
+ /*0a1e*/ 0x0000003f,
+ /*0a1f*/ 0x0002c06e,
+ /*0a20*/ 0x02c002c0,
+ /*0a21*/ 0x02c002c0,
+ /*0a22*/ 0x000002c0,
+ /*0a23*/ 0x42080010,
+ /*0a24*/ 0x00000003
};
static const uint32_t DDR_PHY_ADR_I_REGSET_M3[DDR_PHY_ADR_I_REGSET_NUM_M3] = {
-/*0a80*/ 0x04040404,
-/*0a81*/ 0x00000404,
-/*0a82*/ 0x00000000,
-/*0a83*/ 0x00000000,
-/*0a84*/ 0x00000000,
-/*0a85*/ 0x00000000,
-/*0a86*/ 0x00000002,
-/*0a87*/ 0x00000000,
-/*0a88*/ 0x00000000,
-/*0a89*/ 0x00000000,
-/*0a8a*/ 0x00400320,
-/*0a8b*/ 0x00000040,
-/*0a8c*/ 0x00000000,
-/*0a8d*/ 0x00000000,
-/*0a8e*/ 0x00000000,
-/*0a8f*/ 0x01000000,
-/*0a90*/ 0x00020003,
-/*0a91*/ 0x00000000,
-/*0a92*/ 0x00000000,
-/*0a93*/ 0x00000000,
-/*0a94*/ 0x0000002a,
-/*0a95*/ 0x00000015,
-/*0a96*/ 0x00000015,
-/*0a97*/ 0x0000002a,
-/*0a98*/ 0x00000033,
-/*0a99*/ 0x0000000c,
-/*0a9a*/ 0x0000000c,
-/*0a9b*/ 0x00000033,
-/*0a9c*/ 0x00000000,
-/*0a9d*/ 0x00000000,
-/*0a9e*/ 0x00000000,
-/*0a9f*/ 0x0002c06e,
-/*0aa0*/ 0x02c002c0,
-/*0aa1*/ 0x02c002c0,
-/*0aa2*/ 0x000002c0,
-/*0aa3*/ 0x42080010,
-/*0aa4*/ 0x00000003
+ /*0a80*/ 0x04040404,
+ /*0a81*/ 0x00000404,
+ /*0a82*/ 0x00000000,
+ /*0a83*/ 0x00000000,
+ /*0a84*/ 0x00000000,
+ /*0a85*/ 0x00000000,
+ /*0a86*/ 0x00000002,
+ /*0a87*/ 0x00000000,
+ /*0a88*/ 0x00000000,
+ /*0a89*/ 0x00000000,
+ /*0a8a*/ 0x00400320,
+ /*0a8b*/ 0x00000040,
+ /*0a8c*/ 0x00000000,
+ /*0a8d*/ 0x00000000,
+ /*0a8e*/ 0x00000000,
+ /*0a8f*/ 0x01000000,
+ /*0a90*/ 0x00020003,
+ /*0a91*/ 0x00000000,
+ /*0a92*/ 0x00000000,
+ /*0a93*/ 0x00000000,
+ /*0a94*/ 0x0000002a,
+ /*0a95*/ 0x00000015,
+ /*0a96*/ 0x00000015,
+ /*0a97*/ 0x0000002a,
+ /*0a98*/ 0x00000033,
+ /*0a99*/ 0x0000000c,
+ /*0a9a*/ 0x0000000c,
+ /*0a9b*/ 0x00000033,
+ /*0a9c*/ 0x00000000,
+ /*0a9d*/ 0x00000000,
+ /*0a9e*/ 0x00000000,
+ /*0a9f*/ 0x0002c06e,
+ /*0aa0*/ 0x02c002c0,
+ /*0aa1*/ 0x02c002c0,
+ /*0aa2*/ 0x000002c0,
+ /*0aa3*/ 0x42080010,
+ /*0aa4*/ 0x00000003
};
static const uint32_t DDR_PHY_ADR_G_REGSET_M3[DDR_PHY_ADR_G_REGSET_NUM_M3] = {
-/*0b80*/ 0x00000001,
-/*0b81*/ 0x00000000,
-/*0b82*/ 0x00000005,
-/*0b83*/ 0x04000f00,
-/*0b84*/ 0x00020080,
-/*0b85*/ 0x00020055,
-/*0b86*/ 0x00000000,
-/*0b87*/ 0x00000000,
-/*0b88*/ 0x00000000,
-/*0b89*/ 0x00000050,
-/*0b8a*/ 0x00000000,
-/*0b8b*/ 0x01010100,
-/*0b8c*/ 0x00000600,
-/*0b8d*/ 0x50640000,
-/*0b8e*/ 0x01421142,
-/*0b8f*/ 0x00000142,
-/*0b90*/ 0x00000000,
-/*0b91*/ 0x000f1600,
-/*0b92*/ 0x0f160f16,
-/*0b93*/ 0x0f160f16,
-/*0b94*/ 0x00000003,
-/*0b95*/ 0x0002c000,
-/*0b96*/ 0x02c002c0,
-/*0b97*/ 0x000002c0,
-/*0b98*/ 0x03421342,
-/*0b99*/ 0x00000342,
-/*0b9a*/ 0x00000000,
-/*0b9b*/ 0x00000000,
-/*0b9c*/ 0x05020000,
-/*0b9d*/ 0x00000000,
-/*0b9e*/ 0x00027f6e,
-/*0b9f*/ 0x047f027f,
-/*0ba0*/ 0x00027f6e,
-/*0ba1*/ 0x00047f6e,
-/*0ba2*/ 0x0003554f,
-/*0ba3*/ 0x0001554f,
-/*0ba4*/ 0x0001554f,
-/*0ba5*/ 0x0001554f,
-/*0ba6*/ 0x0001554f,
-/*0ba7*/ 0x00003fee,
-/*0ba8*/ 0x0001554f,
-/*0ba9*/ 0x00003fee,
-/*0baa*/ 0x0001554f,
-/*0bab*/ 0x00027f6e,
-/*0bac*/ 0x0001554f,
-/*0bad*/ 0x00000000,
-/*0bae*/ 0x00000000,
-/*0baf*/ 0x00000000,
-/*0bb0*/ 0x65000000,
-/*0bb1*/ 0x00000000,
-/*0bb2*/ 0x00000000,
-/*0bb3*/ 0x00000201,
-/*0bb4*/ 0x00000000,
-/*0bb5*/ 0x00000000,
-/*0bb6*/ 0x00000000,
-/*0bb7*/ 0x00000000,
-/*0bb8*/ 0x00000000,
-/*0bb9*/ 0x00000000,
-/*0bba*/ 0x00000000,
-/*0bbb*/ 0x00000000,
-/*0bbc*/ 0x06e40000,
-/*0bbd*/ 0x00000000,
-/*0bbe*/ 0x00000000,
-/*0bbf*/ 0x00010000
+ /*0b80*/ 0x00000001,
+ /*0b81*/ 0x00000000,
+ /*0b82*/ 0x00000005,
+ /*0b83*/ 0x04000f00,
+ /*0b84*/ 0x00020080,
+ /*0b85*/ 0x00020055,
+ /*0b86*/ 0x00000000,
+ /*0b87*/ 0x00000000,
+ /*0b88*/ 0x00000000,
+ /*0b89*/ 0x00000050,
+ /*0b8a*/ 0x00000000,
+ /*0b8b*/ 0x01010100,
+ /*0b8c*/ 0x00000600,
+ /*0b8d*/ 0x50640000,
+ /*0b8e*/ 0x01421142,
+ /*0b8f*/ 0x00000142,
+ /*0b90*/ 0x00000000,
+ /*0b91*/ 0x000f1600,
+ /*0b92*/ 0x0f160f16,
+ /*0b93*/ 0x0f160f16,
+ /*0b94*/ 0x00000003,
+ /*0b95*/ 0x0002c000,
+ /*0b96*/ 0x02c002c0,
+ /*0b97*/ 0x000002c0,
+ /*0b98*/ 0x03421342,
+ /*0b99*/ 0x00000342,
+ /*0b9a*/ 0x00000000,
+ /*0b9b*/ 0x00000000,
+ /*0b9c*/ 0x05020000,
+ /*0b9d*/ 0x00000000,
+ /*0b9e*/ 0x00027f6e,
+ /*0b9f*/ 0x047f027f,
+ /*0ba0*/ 0x00027f6e,
+ /*0ba1*/ 0x00047f6e,
+ /*0ba2*/ 0x0003554f,
+ /*0ba3*/ 0x0001554f,
+ /*0ba4*/ 0x0001554f,
+ /*0ba5*/ 0x0001554f,
+ /*0ba6*/ 0x0001554f,
+ /*0ba7*/ 0x00003fee,
+ /*0ba8*/ 0x0001554f,
+ /*0ba9*/ 0x00003fee,
+ /*0baa*/ 0x0001554f,
+ /*0bab*/ 0x00027f6e,
+ /*0bac*/ 0x0001554f,
+ /*0bad*/ 0x00000000,
+ /*0bae*/ 0x00000000,
+ /*0baf*/ 0x00000000,
+ /*0bb0*/ 0x65000000,
+ /*0bb1*/ 0x00000000,
+ /*0bb2*/ 0x00000000,
+ /*0bb3*/ 0x00000201,
+ /*0bb4*/ 0x00000000,
+ /*0bb5*/ 0x00000000,
+ /*0bb6*/ 0x00000000,
+ /*0bb7*/ 0x00000000,
+ /*0bb8*/ 0x00000000,
+ /*0bb9*/ 0x00000000,
+ /*0bba*/ 0x00000000,
+ /*0bbb*/ 0x00000000,
+ /*0bbc*/ 0x06e40000,
+ /*0bbd*/ 0x00000000,
+ /*0bbe*/ 0x00000000,
+ /*0bbf*/ 0x00010000
};
static const uint32_t DDR_PI_REGSET_M3[DDR_PI_REGSET_NUM_M3] = {
-/*0200*/ 0x00000b00,
-/*0201*/ 0x00000100,
-/*0202*/ 0x00000000,
-/*0203*/ 0x0000ffff,
-/*0204*/ 0x00000000,
-/*0205*/ 0x0000ffff,
-/*0206*/ 0x00000000,
-/*0207*/ 0x304cffff,
-/*0208*/ 0x00000200,
-/*0209*/ 0x00000200,
-/*020a*/ 0x00000200,
-/*020b*/ 0x00000200,
-/*020c*/ 0x0000304c,
-/*020d*/ 0x00000200,
-/*020e*/ 0x00000200,
-/*020f*/ 0x00000200,
-/*0210*/ 0x00000200,
-/*0211*/ 0x0000304c,
-/*0212*/ 0x00000200,
-/*0213*/ 0x00000200,
-/*0214*/ 0x00000200,
-/*0215*/ 0x00000200,
-/*0216*/ 0x00010000,
-/*0217*/ 0x00000003,
-/*0218*/ 0x01000001,
-/*0219*/ 0x00000000,
-/*021a*/ 0x00000000,
-/*021b*/ 0x00000000,
-/*021c*/ 0x00000000,
-/*021d*/ 0x00000000,
-/*021e*/ 0x00000000,
-/*021f*/ 0x00000000,
-/*0220*/ 0x00000000,
-/*0221*/ 0x00000000,
-/*0222*/ 0x00000000,
-/*0223*/ 0x00000000,
-/*0224*/ 0x00000000,
-/*0225*/ 0x00000000,
-/*0226*/ 0x00000000,
-/*0227*/ 0x00000000,
-/*0228*/ 0x00000000,
-/*0229*/ 0x0f000101,
-/*022a*/ 0x08492d25,
-/*022b*/ 0x0e0c0004,
-/*022c*/ 0x000e5000,
-/*022d*/ 0x00000250,
-/*022e*/ 0x00460003,
-/*022f*/ 0x182600cf,
-/*0230*/ 0x182600cf,
-/*0231*/ 0x00000005,
-/*0232*/ 0x00000000,
-/*0233*/ 0x00000000,
-/*0234*/ 0x00000000,
-/*0235*/ 0x00000000,
-/*0236*/ 0x00000000,
-/*0237*/ 0x00000000,
-/*0238*/ 0x00000000,
-/*0239*/ 0x01000000,
-/*023a*/ 0x00040404,
-/*023b*/ 0x01280a00,
-/*023c*/ 0x00000000,
-/*023d*/ 0x000f0000,
-/*023e*/ 0x00001803,
-/*023f*/ 0x00000000,
-/*0240*/ 0x00000000,
-/*0241*/ 0x00060002,
-/*0242*/ 0x00010001,
-/*0243*/ 0x01000101,
-/*0244*/ 0x04020201,
-/*0245*/ 0x00080804,
-/*0246*/ 0x00000000,
-/*0247*/ 0x08030000,
-/*0248*/ 0x15150408,
-/*0249*/ 0x00000000,
-/*024a*/ 0x00000000,
-/*024b*/ 0x00000000,
-/*024c*/ 0x000f0f00,
-/*024d*/ 0x0000001e,
-/*024e*/ 0x00000000,
-/*024f*/ 0x01000300,
-/*0250*/ 0x00000000,
-/*0251*/ 0x00000000,
-/*0252*/ 0x01000000,
-/*0253*/ 0x00010101,
-/*0254*/ 0x000e0e0e,
-/*0255*/ 0x000c0c0c,
-/*0256*/ 0x02060601,
-/*0257*/ 0x00000000,
-/*0258*/ 0x00000003,
-/*0259*/ 0x00181703,
-/*025a*/ 0x00280006,
-/*025b*/ 0x00280016,
-/*025c*/ 0x00000016,
-/*025d*/ 0x00000000,
-/*025e*/ 0x00000000,
-/*025f*/ 0x00000000,
-/*0260*/ 0x140a0000,
-/*0261*/ 0x0005010a,
-/*0262*/ 0x03018d03,
-/*0263*/ 0x000a018d,
-/*0264*/ 0x00060100,
-/*0265*/ 0x01000006,
-/*0266*/ 0x018e018e,
-/*0267*/ 0x018e0100,
-/*0268*/ 0x1111018e,
-/*0269*/ 0x10010204,
-/*026a*/ 0x09090650,
-/*026b*/ 0x20110202,
-/*026c*/ 0x00201000,
-/*026d*/ 0x00201000,
-/*026e*/ 0x04041000,
-/*026f*/ 0x18020100,
-/*0270*/ 0x00010118,
-/*0271*/ 0x004b004a,
-/*0272*/ 0x050f0000,
-/*0273*/ 0x0c01021e,
-/*0274*/ 0x34000000,
-/*0275*/ 0x00000000,
-/*0276*/ 0x00000000,
-/*0277*/ 0x00000000,
-/*0278*/ 0x0000d400,
-/*0279*/ 0x0031002e,
-/*027a*/ 0x00111136,
-/*027b*/ 0x002e00d4,
-/*027c*/ 0x11360031,
-/*027d*/ 0x0000d411,
-/*027e*/ 0x0031002e,
-/*027f*/ 0x00111136,
-/*0280*/ 0x002e00d4,
-/*0281*/ 0x11360031,
-/*0282*/ 0x0000d411,
-/*0283*/ 0x0031002e,
-/*0284*/ 0x00111136,
-/*0285*/ 0x002e00d4,
-/*0286*/ 0x11360031,
-/*0287*/ 0x00d40011,
-/*0288*/ 0x0031002e,
-/*0289*/ 0x00111136,
-/*028a*/ 0x002e00d4,
-/*028b*/ 0x11360031,
-/*028c*/ 0x0000d411,
-/*028d*/ 0x0031002e,
-/*028e*/ 0x00111136,
-/*028f*/ 0x002e00d4,
-/*0290*/ 0x11360031,
-/*0291*/ 0x0000d411,
-/*0292*/ 0x0031002e,
-/*0293*/ 0x00111136,
-/*0294*/ 0x002e00d4,
-/*0295*/ 0x11360031,
-/*0296*/ 0x02000011,
-/*0297*/ 0x018d018d,
-/*0298*/ 0x0c08018d,
-/*0299*/ 0x1f121d22,
-/*029a*/ 0x4301b344,
-/*029b*/ 0x10172006,
-/*029c*/ 0x1d220c10,
-/*029d*/ 0x00001f12,
-/*029e*/ 0x4301b344,
-/*029f*/ 0x10172006,
-/*02a0*/ 0x1d220c10,
-/*02a1*/ 0x00001f12,
-/*02a2*/ 0x4301b344,
-/*02a3*/ 0x10172006,
-/*02a4*/ 0x02000210,
-/*02a5*/ 0x02000200,
-/*02a6*/ 0x02000200,
-/*02a7*/ 0x02000200,
-/*02a8*/ 0x02000200,
-/*02a9*/ 0x00000000,
-/*02aa*/ 0x00000000,
-/*02ab*/ 0x00000000,
-/*02ac*/ 0x00000000,
-/*02ad*/ 0x00000000,
-/*02ae*/ 0x00000000,
-/*02af*/ 0x00000000,
-/*02b0*/ 0x00000000,
-/*02b1*/ 0x00000000,
-/*02b2*/ 0x00000000,
-/*02b3*/ 0x00000000,
-/*02b4*/ 0x00000000,
-/*02b5*/ 0x00000400,
-/*02b6*/ 0x15141312,
-/*02b7*/ 0x11100f0e,
-/*02b8*/ 0x080b0c0d,
-/*02b9*/ 0x05040a09,
-/*02ba*/ 0x01000706,
-/*02bb*/ 0x00000302,
-/*02bc*/ 0x01030201,
-/*02bd*/ 0x00304c00,
-/*02be*/ 0x0001e2f8,
-/*02bf*/ 0x0000304c,
-/*02c0*/ 0x0001e2f8,
-/*02c1*/ 0x0000304c,
-/*02c2*/ 0x0001e2f8,
-/*02c3*/ 0x08000000,
-/*02c4*/ 0x00000100,
-/*02c5*/ 0x00000000,
-/*02c6*/ 0x00000000,
-/*02c7*/ 0x00000000,
-/*02c8*/ 0x00000000,
-/*02c9*/ 0x00000002
+ /*0200*/ 0x00000b00,
+ /*0201*/ 0x00000100,
+ /*0202*/ 0x00000000,
+ /*0203*/ 0x0000ffff,
+ /*0204*/ 0x00000000,
+ /*0205*/ 0x0000ffff,
+ /*0206*/ 0x00000000,
+ /*0207*/ 0x304cffff,
+ /*0208*/ 0x00000200,
+ /*0209*/ 0x00000200,
+ /*020a*/ 0x00000200,
+ /*020b*/ 0x00000200,
+ /*020c*/ 0x0000304c,
+ /*020d*/ 0x00000200,
+ /*020e*/ 0x00000200,
+ /*020f*/ 0x00000200,
+ /*0210*/ 0x00000200,
+ /*0211*/ 0x0000304c,
+ /*0212*/ 0x00000200,
+ /*0213*/ 0x00000200,
+ /*0214*/ 0x00000200,
+ /*0215*/ 0x00000200,
+ /*0216*/ 0x00010000,
+ /*0217*/ 0x00000003,
+ /*0218*/ 0x01000001,
+ /*0219*/ 0x00000000,
+ /*021a*/ 0x00000000,
+ /*021b*/ 0x00000000,
+ /*021c*/ 0x00000000,
+ /*021d*/ 0x00000000,
+ /*021e*/ 0x00000000,
+ /*021f*/ 0x00000000,
+ /*0220*/ 0x00000000,
+ /*0221*/ 0x00000000,
+ /*0222*/ 0x00000000,
+ /*0223*/ 0x00000000,
+ /*0224*/ 0x00000000,
+ /*0225*/ 0x00000000,
+ /*0226*/ 0x00000000,
+ /*0227*/ 0x00000000,
+ /*0228*/ 0x00000000,
+ /*0229*/ 0x0f000101,
+ /*022a*/ 0x08492d25,
+ /*022b*/ 0x0e0c0004,
+ /*022c*/ 0x000e5000,
+ /*022d*/ 0x00000250,
+ /*022e*/ 0x00460003,
+ /*022f*/ 0x182600cf,
+ /*0230*/ 0x182600cf,
+ /*0231*/ 0x00000005,
+ /*0232*/ 0x00000000,
+ /*0233*/ 0x00000000,
+ /*0234*/ 0x00000000,
+ /*0235*/ 0x00000000,
+ /*0236*/ 0x00000000,
+ /*0237*/ 0x00000000,
+ /*0238*/ 0x00000000,
+ /*0239*/ 0x01000000,
+ /*023a*/ 0x00040404,
+ /*023b*/ 0x01280a00,
+ /*023c*/ 0x00000000,
+ /*023d*/ 0x000f0000,
+ /*023e*/ 0x00001803,
+ /*023f*/ 0x00000000,
+ /*0240*/ 0x00000000,
+ /*0241*/ 0x00060002,
+ /*0242*/ 0x00010001,
+ /*0243*/ 0x01000101,
+ /*0244*/ 0x04020201,
+ /*0245*/ 0x00080804,
+ /*0246*/ 0x00000000,
+ /*0247*/ 0x08030000,
+ /*0248*/ 0x15150408,
+ /*0249*/ 0x00000000,
+ /*024a*/ 0x00000000,
+ /*024b*/ 0x00000000,
+ /*024c*/ 0x000f0f00,
+ /*024d*/ 0x0000001e,
+ /*024e*/ 0x00000000,
+ /*024f*/ 0x01000300,
+ /*0250*/ 0x00000000,
+ /*0251*/ 0x00000000,
+ /*0252*/ 0x01000000,
+ /*0253*/ 0x00010101,
+ /*0254*/ 0x000e0e0e,
+ /*0255*/ 0x000c0c0c,
+ /*0256*/ 0x02060601,
+ /*0257*/ 0x00000000,
+ /*0258*/ 0x00000003,
+ /*0259*/ 0x00181703,
+ /*025a*/ 0x00280006,
+ /*025b*/ 0x00280016,
+ /*025c*/ 0x00000016,
+ /*025d*/ 0x00000000,
+ /*025e*/ 0x00000000,
+ /*025f*/ 0x00000000,
+ /*0260*/ 0x140a0000,
+ /*0261*/ 0x0005010a,
+ /*0262*/ 0x03018d03,
+ /*0263*/ 0x000a018d,
+ /*0264*/ 0x00060100,
+ /*0265*/ 0x01000006,
+ /*0266*/ 0x018e018e,
+ /*0267*/ 0x018e0100,
+ /*0268*/ 0x1111018e,
+ /*0269*/ 0x10010204,
+ /*026a*/ 0x09090650,
+ /*026b*/ 0x20110202,
+ /*026c*/ 0x00201000,
+ /*026d*/ 0x00201000,
+ /*026e*/ 0x04041000,
+ /*026f*/ 0x18020100,
+ /*0270*/ 0x00010118,
+ /*0271*/ 0x004b004a,
+ /*0272*/ 0x050f0000,
+ /*0273*/ 0x0c01021e,
+ /*0274*/ 0x34000000,
+ /*0275*/ 0x00000000,
+ /*0276*/ 0x00000000,
+ /*0277*/ 0x00000000,
+ /*0278*/ 0x0000d400,
+ /*0279*/ 0x0031002e,
+ /*027a*/ 0x00111136,
+ /*027b*/ 0x002e00d4,
+ /*027c*/ 0x11360031,
+ /*027d*/ 0x0000d411,
+ /*027e*/ 0x0031002e,
+ /*027f*/ 0x00111136,
+ /*0280*/ 0x002e00d4,
+ /*0281*/ 0x11360031,
+ /*0282*/ 0x0000d411,
+ /*0283*/ 0x0031002e,
+ /*0284*/ 0x00111136,
+ /*0285*/ 0x002e00d4,
+ /*0286*/ 0x11360031,
+ /*0287*/ 0x00d40011,
+ /*0288*/ 0x0031002e,
+ /*0289*/ 0x00111136,
+ /*028a*/ 0x002e00d4,
+ /*028b*/ 0x11360031,
+ /*028c*/ 0x0000d411,
+ /*028d*/ 0x0031002e,
+ /*028e*/ 0x00111136,
+ /*028f*/ 0x002e00d4,
+ /*0290*/ 0x11360031,
+ /*0291*/ 0x0000d411,
+ /*0292*/ 0x0031002e,
+ /*0293*/ 0x00111136,
+ /*0294*/ 0x002e00d4,
+ /*0295*/ 0x11360031,
+ /*0296*/ 0x02000011,
+ /*0297*/ 0x018d018d,
+ /*0298*/ 0x0c08018d,
+ /*0299*/ 0x1f121d22,
+ /*029a*/ 0x4301b344,
+ /*029b*/ 0x10172006,
+ /*029c*/ 0x1d220c10,
+ /*029d*/ 0x00001f12,
+ /*029e*/ 0x4301b344,
+ /*029f*/ 0x10172006,
+ /*02a0*/ 0x1d220c10,
+ /*02a1*/ 0x00001f12,
+ /*02a2*/ 0x4301b344,
+ /*02a3*/ 0x10172006,
+ /*02a4*/ 0x02000210,
+ /*02a5*/ 0x02000200,
+ /*02a6*/ 0x02000200,
+ /*02a7*/ 0x02000200,
+ /*02a8*/ 0x02000200,
+ /*02a9*/ 0x00000000,
+ /*02aa*/ 0x00000000,
+ /*02ab*/ 0x00000000,
+ /*02ac*/ 0x00000000,
+ /*02ad*/ 0x00000000,
+ /*02ae*/ 0x00000000,
+ /*02af*/ 0x00000000,
+ /*02b0*/ 0x00000000,
+ /*02b1*/ 0x00000000,
+ /*02b2*/ 0x00000000,
+ /*02b3*/ 0x00000000,
+ /*02b4*/ 0x00000000,
+ /*02b5*/ 0x00000400,
+ /*02b6*/ 0x15141312,
+ /*02b7*/ 0x11100f0e,
+ /*02b8*/ 0x080b0c0d,
+ /*02b9*/ 0x05040a09,
+ /*02ba*/ 0x01000706,
+ /*02bb*/ 0x00000302,
+ /*02bc*/ 0x01030201,
+ /*02bd*/ 0x00304c00,
+ /*02be*/ 0x0001e2f8,
+ /*02bf*/ 0x0000304c,
+ /*02c0*/ 0x0001e2f8,
+ /*02c1*/ 0x0000304c,
+ /*02c2*/ 0x0001e2f8,
+ /*02c3*/ 0x08000000,
+ /*02c4*/ 0x00000100,
+ /*02c5*/ 0x00000000,
+ /*02c6*/ 0x00000000,
+ /*02c7*/ 0x00000000,
+ /*02c8*/ 0x00000000,
+ /*02c9*/ 0x00000002
};
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
index 42c3351..8d80842 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
@@ -1,5 +1,6 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -23,564 +24,564 @@
#define DDR_PI_REGSET_NUM_M3N 286
static const uint32_t DDR_PHY_SLICE_REGSET_M3N[DDR_PHY_SLICE_REGSET_NUM_M3N] = {
-/*0800*/ 0x76543210,
-/*0801*/ 0x0004f008,
-/*0802*/ 0x00020200,
-/*0803*/ 0x00000000,
-/*0804*/ 0x00000000,
-/*0805*/ 0x00010000,
-/*0806*/ 0x036e6e0e,
-/*0807*/ 0x026e6e0e,
-/*0808*/ 0x00000103,
-/*0809*/ 0x00040001,
-/*080a*/ 0x00000103,
-/*080b*/ 0x00000001,
-/*080c*/ 0x00000000,
-/*080d*/ 0x00000000,
-/*080e*/ 0x00000100,
-/*080f*/ 0x001800c0,
-/*0810*/ 0x020100b0,
-/*0811*/ 0x00030020,
-/*0812*/ 0x00000000,
-/*0813*/ 0x00000000,
-/*0814*/ 0x0000aaaa,
-/*0815*/ 0x00005555,
-/*0816*/ 0x0000b5b5,
-/*0817*/ 0x00004a4a,
-/*0818*/ 0x00000000,
-/*0819*/ 0x09000000,
-/*081a*/ 0x04080000,
-/*081b*/ 0x08040000,
-/*081c*/ 0x00000004,
-/*081d*/ 0x00800710,
-/*081e*/ 0x000f000c,
-/*081f*/ 0x00000100,
-/*0820*/ 0x55aa55aa,
-/*0821*/ 0x33cc33cc,
-/*0822*/ 0x0ff00ff0,
-/*0823*/ 0x0f0ff0f0,
-/*0824*/ 0x00018e38,
-/*0825*/ 0x00000000,
-/*0826*/ 0x00000000,
-/*0827*/ 0x00000000,
-/*0828*/ 0x00000000,
-/*0829*/ 0x00000000,
-/*082a*/ 0x00000000,
-/*082b*/ 0x00000000,
-/*082c*/ 0x00000000,
-/*082d*/ 0x00000000,
-/*082e*/ 0x00000000,
-/*082f*/ 0x00000000,
-/*0830*/ 0x00000000,
-/*0831*/ 0x00000000,
-/*0832*/ 0x00000000,
-/*0833*/ 0x00000000,
-/*0834*/ 0x00000000,
-/*0835*/ 0x00000000,
-/*0836*/ 0x00000000,
-/*0837*/ 0x00000000,
-/*0838*/ 0x00000000,
-/*0839*/ 0x00000000,
-/*083a*/ 0x00000104,
-/*083b*/ 0x00082020,
-/*083c*/ 0x08200820,
-/*083d*/ 0x08200820,
-/*083e*/ 0x08200820,
-/*083f*/ 0x08200820,
-/*0840*/ 0x08200820,
-/*0841*/ 0x00000000,
-/*0842*/ 0x00000000,
-/*0843*/ 0x03000300,
-/*0844*/ 0x03000300,
-/*0845*/ 0x03000300,
-/*0846*/ 0x03000300,
-/*0847*/ 0x00000300,
-/*0848*/ 0x00000000,
-/*0849*/ 0x00000000,
-/*084a*/ 0x00000000,
-/*084b*/ 0x00000000,
-/*084c*/ 0x00000000,
-/*084d*/ 0x00a000a0,
-/*084e*/ 0x00a000a0,
-/*084f*/ 0x00a000a0,
-/*0850*/ 0x00a000a0,
-/*0851*/ 0x00a000a0,
-/*0852*/ 0x00a000a0,
-/*0853*/ 0x00a000a0,
-/*0854*/ 0x00a000a0,
-/*0855*/ 0x00a000a0,
-/*0856*/ 0x01040119,
-/*0857*/ 0x00000200,
-/*0858*/ 0x01000000,
-/*0859*/ 0x00000200,
-/*085a*/ 0x00000004,
-/*085b*/ 0x4041a141,
-/*085c*/ 0x0141c0a0,
-/*085d*/ 0x0000c0c0,
-/*085e*/ 0x0e0c000e,
-/*085f*/ 0x10001000,
-/*0860*/ 0x0c073e42,
-/*0861*/ 0x000f0c28,
-/*0862*/ 0x00e00140,
-/*0863*/ 0x000c0020,
-/*0864*/ 0x00000203
+ /*0800*/ 0x76543210,
+ /*0801*/ 0x0004f008,
+ /*0802*/ 0x00020200,
+ /*0803*/ 0x00000000,
+ /*0804*/ 0x00000000,
+ /*0805*/ 0x00010000,
+ /*0806*/ 0x036e6e0e,
+ /*0807*/ 0x026e6e0e,
+ /*0808*/ 0x00000103,
+ /*0809*/ 0x00040001,
+ /*080a*/ 0x00000103,
+ /*080b*/ 0x00000001,
+ /*080c*/ 0x00000000,
+ /*080d*/ 0x00000000,
+ /*080e*/ 0x00000100,
+ /*080f*/ 0x001800c0,
+ /*0810*/ 0x020100b0,
+ /*0811*/ 0x00030020,
+ /*0812*/ 0x00000000,
+ /*0813*/ 0x00000000,
+ /*0814*/ 0x0000aaaa,
+ /*0815*/ 0x00005555,
+ /*0816*/ 0x0000b5b5,
+ /*0817*/ 0x00004a4a,
+ /*0818*/ 0x00000000,
+ /*0819*/ 0x09000000,
+ /*081a*/ 0x04080000,
+ /*081b*/ 0x08040000,
+ /*081c*/ 0x00000004,
+ /*081d*/ 0x00800710,
+ /*081e*/ 0x000f000c,
+ /*081f*/ 0x00000100,
+ /*0820*/ 0x55aa55aa,
+ /*0821*/ 0x33cc33cc,
+ /*0822*/ 0x0ff00ff0,
+ /*0823*/ 0x0f0ff0f0,
+ /*0824*/ 0x00018e38,
+ /*0825*/ 0x00000000,
+ /*0826*/ 0x00000000,
+ /*0827*/ 0x00000000,
+ /*0828*/ 0x00000000,
+ /*0829*/ 0x00000000,
+ /*082a*/ 0x00000000,
+ /*082b*/ 0x00000000,
+ /*082c*/ 0x00000000,
+ /*082d*/ 0x00000000,
+ /*082e*/ 0x00000000,
+ /*082f*/ 0x00000000,
+ /*0830*/ 0x00000000,
+ /*0831*/ 0x00000000,
+ /*0832*/ 0x00000000,
+ /*0833*/ 0x00000000,
+ /*0834*/ 0x00000000,
+ /*0835*/ 0x00000000,
+ /*0836*/ 0x00000000,
+ /*0837*/ 0x00000000,
+ /*0838*/ 0x00000000,
+ /*0839*/ 0x00000000,
+ /*083a*/ 0x00000104,
+ /*083b*/ 0x00082020,
+ /*083c*/ 0x08200820,
+ /*083d*/ 0x08200820,
+ /*083e*/ 0x08200820,
+ /*083f*/ 0x08200820,
+ /*0840*/ 0x08200820,
+ /*0841*/ 0x00000000,
+ /*0842*/ 0x00000000,
+ /*0843*/ 0x03000300,
+ /*0844*/ 0x03000300,
+ /*0845*/ 0x03000300,
+ /*0846*/ 0x03000300,
+ /*0847*/ 0x00000300,
+ /*0848*/ 0x00000000,
+ /*0849*/ 0x00000000,
+ /*084a*/ 0x00000000,
+ /*084b*/ 0x00000000,
+ /*084c*/ 0x00000000,
+ /*084d*/ 0x00a000a0,
+ /*084e*/ 0x00a000a0,
+ /*084f*/ 0x00a000a0,
+ /*0850*/ 0x00a000a0,
+ /*0851*/ 0x00a000a0,
+ /*0852*/ 0x00a000a0,
+ /*0853*/ 0x00a000a0,
+ /*0854*/ 0x00a000a0,
+ /*0855*/ 0x00a000a0,
+ /*0856*/ 0x01040119,
+ /*0857*/ 0x00000200,
+ /*0858*/ 0x01000000,
+ /*0859*/ 0x00000200,
+ /*085a*/ 0x00000004,
+ /*085b*/ 0x4041a151,
+ /*085c*/ 0x0141c0a0,
+ /*085d*/ 0x0000c0c0,
+ /*085e*/ 0x0e0c000e,
+ /*085f*/ 0x10001000,
+ /*0860*/ 0x0c073e42,
+ /*0861*/ 0x000f0c28,
+ /*0862*/ 0x00e00140,
+ /*0863*/ 0x000c0020,
+ /*0864*/ 0x00000203
};
static const uint32_t DDR_PHY_ADR_V_REGSET_M3N[DDR_PHY_ADR_V_REGSET_NUM_M3N] = {
-/*0a00*/ 0x00000000,
-/*0a01*/ 0x00000000,
-/*0a02*/ 0x00000000,
-/*0a03*/ 0x00000000,
-/*0a04*/ 0x00000000,
-/*0a05*/ 0x00000000,
-/*0a06*/ 0x00000000,
-/*0a07*/ 0x01000000,
-/*0a08*/ 0x00020000,
-/*0a09*/ 0x00000000,
-/*0a0a*/ 0x00000000,
-/*0a0b*/ 0x00000000,
-/*0a0c*/ 0x00400000,
-/*0a0d*/ 0x00000080,
-/*0a0e*/ 0x00dcba98,
-/*0a0f*/ 0x03000000,
-/*0a10*/ 0x00000200,
-/*0a11*/ 0x00000000,
-/*0a12*/ 0x00000000,
-/*0a13*/ 0x00000000,
-/*0a14*/ 0x0000002a,
-/*0a15*/ 0x00000015,
-/*0a16*/ 0x00000015,
-/*0a17*/ 0x0000002a,
-/*0a18*/ 0x00000033,
-/*0a19*/ 0x0000000c,
-/*0a1a*/ 0x0000000c,
-/*0a1b*/ 0x00000033,
-/*0a1c*/ 0x0a418820,
-/*0a1d*/ 0x003f0000,
-/*0a1e*/ 0x0000013f,
-/*0a1f*/ 0x0002c06e,
-/*0a20*/ 0x02c002c0,
-/*0a21*/ 0x02c002c0,
-/*0a22*/ 0x000002c0,
-/*0a23*/ 0x42080010,
-/*0a24*/ 0x0000033e
+ /*0a00*/ 0x00000000,
+ /*0a01*/ 0x00000000,
+ /*0a02*/ 0x00000000,
+ /*0a03*/ 0x00000000,
+ /*0a04*/ 0x00000000,
+ /*0a05*/ 0x00000000,
+ /*0a06*/ 0x00000000,
+ /*0a07*/ 0x01000000,
+ /*0a08*/ 0x00020000,
+ /*0a09*/ 0x00000000,
+ /*0a0a*/ 0x00000000,
+ /*0a0b*/ 0x00000000,
+ /*0a0c*/ 0x00400000,
+ /*0a0d*/ 0x00000080,
+ /*0a0e*/ 0x00dcba98,
+ /*0a0f*/ 0x03000000,
+ /*0a10*/ 0x00000200,
+ /*0a11*/ 0x00000000,
+ /*0a12*/ 0x00000000,
+ /*0a13*/ 0x00000000,
+ /*0a14*/ 0x0000002a,
+ /*0a15*/ 0x00000015,
+ /*0a16*/ 0x00000015,
+ /*0a17*/ 0x0000002a,
+ /*0a18*/ 0x00000033,
+ /*0a19*/ 0x0000000c,
+ /*0a1a*/ 0x0000000c,
+ /*0a1b*/ 0x00000033,
+ /*0a1c*/ 0x0a418820,
+ /*0a1d*/ 0x003f0000,
+ /*0a1e*/ 0x0000013f,
+ /*0a1f*/ 0x0002c06e,
+ /*0a20*/ 0x02c002c0,
+ /*0a21*/ 0x02c002c0,
+ /*0a22*/ 0x000002c0,
+ /*0a23*/ 0x42080010,
+ /*0a24*/ 0x0000033e
};
static const uint32_t DDR_PHY_ADR_I_REGSET_M3N[DDR_PHY_ADR_I_REGSET_NUM_M3N] = {
-/*0a80*/ 0x00000000,
-/*0a81*/ 0x00000000,
-/*0a82*/ 0x00000000,
-/*0a83*/ 0x00000000,
-/*0a84*/ 0x00000000,
-/*0a85*/ 0x00000000,
-/*0a86*/ 0x00000000,
-/*0a87*/ 0x01000000,
-/*0a88*/ 0x00020000,
-/*0a89*/ 0x00000000,
-/*0a8a*/ 0x00000000,
-/*0a8b*/ 0x00000000,
-/*0a8c*/ 0x00400000,
-/*0a8d*/ 0x00000080,
-/*0a8e*/ 0x00000000,
-/*0a8f*/ 0x03000000,
-/*0a90*/ 0x00000200,
-/*0a91*/ 0x00000000,
-/*0a92*/ 0x00000000,
-/*0a93*/ 0x00000000,
-/*0a94*/ 0x0000002a,
-/*0a95*/ 0x00000015,
-/*0a96*/ 0x00000015,
-/*0a97*/ 0x0000002a,
-/*0a98*/ 0x00000033,
-/*0a99*/ 0x0000000c,
-/*0a9a*/ 0x0000000c,
-/*0a9b*/ 0x00000033,
-/*0a9c*/ 0x00000000,
-/*0a9d*/ 0x00000000,
-/*0a9e*/ 0x00000000,
-/*0a9f*/ 0x0002c06e,
-/*0aa0*/ 0x02c002c0,
-/*0aa1*/ 0x02c002c0,
-/*0aa2*/ 0x000002c0,
-/*0aa3*/ 0x42080010,
-/*0aa4*/ 0x0000033e
+ /*0a80*/ 0x00000000,
+ /*0a81*/ 0x00000000,
+ /*0a82*/ 0x00000000,
+ /*0a83*/ 0x00000000,
+ /*0a84*/ 0x00000000,
+ /*0a85*/ 0x00000000,
+ /*0a86*/ 0x00000000,
+ /*0a87*/ 0x01000000,
+ /*0a88*/ 0x00020000,
+ /*0a89*/ 0x00000000,
+ /*0a8a*/ 0x00000000,
+ /*0a8b*/ 0x00000000,
+ /*0a8c*/ 0x00400000,
+ /*0a8d*/ 0x00000080,
+ /*0a8e*/ 0x00000000,
+ /*0a8f*/ 0x03000000,
+ /*0a90*/ 0x00000200,
+ /*0a91*/ 0x00000000,
+ /*0a92*/ 0x00000000,
+ /*0a93*/ 0x00000000,
+ /*0a94*/ 0x0000002a,
+ /*0a95*/ 0x00000015,
+ /*0a96*/ 0x00000015,
+ /*0a97*/ 0x0000002a,
+ /*0a98*/ 0x00000033,
+ /*0a99*/ 0x0000000c,
+ /*0a9a*/ 0x0000000c,
+ /*0a9b*/ 0x00000033,
+ /*0a9c*/ 0x00000000,
+ /*0a9d*/ 0x00000000,
+ /*0a9e*/ 0x00000000,
+ /*0a9f*/ 0x0002c06e,
+ /*0aa0*/ 0x02c002c0,
+ /*0aa1*/ 0x02c002c0,
+ /*0aa2*/ 0x000002c0,
+ /*0aa3*/ 0x42080010,
+ /*0aa4*/ 0x0000033e
};
static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = {
-/*0b80*/ 0x00000000,
-/*0b81*/ 0x00000100,
-/*0b82*/ 0x00000000,
-/*0b83*/ 0x00050000,
-/*0b84*/ 0x00000000,
-/*0b85*/ 0x0004000f,
-/*0b86*/ 0x00280080,
-/*0b87*/ 0x02005502,
-/*0b88*/ 0x00000000,
-/*0b89*/ 0x00000000,
-/*0b8a*/ 0x00000000,
-/*0b8b*/ 0x00000050,
-/*0b8c*/ 0x00000000,
-/*0b8d*/ 0x01010100,
-/*0b8e*/ 0x00010000,
-/*0b8f*/ 0x00000000,
-/*0b90*/ 0x00000101,
-/*0b91*/ 0x00000000,
-/*0b92*/ 0x00000000,
-/*0b93*/ 0x00000000,
-/*0b94*/ 0x00000000,
-/*0b95*/ 0x00005064,
-/*0b96*/ 0x01421142,
-/*0b97*/ 0x00000142,
-/*0b98*/ 0x00000000,
-/*0b99*/ 0x000f1600,
-/*0b9a*/ 0x0f160f16,
-/*0b9b*/ 0x0f160f16,
-/*0b9c*/ 0x00000003,
-/*0b9d*/ 0x0002c000,
-/*0b9e*/ 0x02c002c0,
-/*0b9f*/ 0x000002c0,
-/*0ba0*/ 0x08040201,
-/*0ba1*/ 0x03421342,
-/*0ba2*/ 0x00000342,
-/*0ba3*/ 0x00000000,
-/*0ba4*/ 0x00000000,
-/*0ba5*/ 0x05030000,
-/*0ba6*/ 0x00010700,
-/*0ba7*/ 0x00000014,
-/*0ba8*/ 0x00027f6e,
-/*0ba9*/ 0x047f027f,
-/*0baa*/ 0x00027f6e,
-/*0bab*/ 0x00047f6e,
-/*0bac*/ 0x0003554f,
-/*0bad*/ 0x0001554f,
-/*0bae*/ 0x0001554f,
-/*0baf*/ 0x0001554f,
-/*0bb0*/ 0x0001554f,
-/*0bb1*/ 0x00003fee,
-/*0bb2*/ 0x0001554f,
-/*0bb3*/ 0x00003fee,
-/*0bb4*/ 0x0001554f,
-/*0bb5*/ 0x00027f6e,
-/*0bb6*/ 0x0001554f,
-/*0bb7*/ 0x00004011,
-/*0bb8*/ 0x00004410,
-/*0bb9*/ 0x00000000,
-/*0bba*/ 0x00000000,
-/*0bbb*/ 0x00000000,
-/*0bbc*/ 0x00000265,
-/*0bbd*/ 0x00000000,
-/*0bbe*/ 0x00040401,
-/*0bbf*/ 0x00000000,
-/*0bc0*/ 0x03000000,
-/*0bc1*/ 0x00000020,
-/*0bc2*/ 0x00000000,
-/*0bc3*/ 0x00000000,
-/*0bc4*/ 0x04102006,
-/*0bc5*/ 0x00041020,
-/*0bc6*/ 0x01c98c98,
-/*0bc7*/ 0x00400000,
-/*0bc8*/ 0x00000000,
-/*0bc9*/ 0x0001ffff,
-/*0bca*/ 0x00000000,
-/*0bcb*/ 0x00000000,
-/*0bcc*/ 0x00000001,
-/*0bcd*/ 0x00000000,
-/*0bce*/ 0x00000000,
-/*0bcf*/ 0x00000000,
-/*0bd0*/ 0x76543210,
-/*0bd1*/ 0x06010198,
-/*0bd2*/ 0x00000000,
-/*0bd3*/ 0x00000000,
-/*0bd4*/ 0x04070000,
-/*0bd5*/ 0x00000001,
-/*0bd6*/ 0x00000f00
+ /*0b80*/ 0x00000000,
+ /*0b81*/ 0x00000100,
+ /*0b82*/ 0x00000000,
+ /*0b83*/ 0x00050000,
+ /*0b84*/ 0x00000000,
+ /*0b85*/ 0x0004000f,
+ /*0b86*/ 0x00280080,
+ /*0b87*/ 0x02005502,
+ /*0b88*/ 0x00000000,
+ /*0b89*/ 0x00000000,
+ /*0b8a*/ 0x00000000,
+ /*0b8b*/ 0x00000050,
+ /*0b8c*/ 0x00000000,
+ /*0b8d*/ 0x01010100,
+ /*0b8e*/ 0x00010000,
+ /*0b8f*/ 0x00000000,
+ /*0b90*/ 0x00000101,
+ /*0b91*/ 0x00000000,
+ /*0b92*/ 0x00000000,
+ /*0b93*/ 0x00000000,
+ /*0b94*/ 0x00000000,
+ /*0b95*/ 0x00005064,
+ /*0b96*/ 0x01421142,
+ /*0b97*/ 0x00000142,
+ /*0b98*/ 0x00000000,
+ /*0b99*/ 0x000f1600,
+ /*0b9a*/ 0x0f160f16,
+ /*0b9b*/ 0x0f160f16,
+ /*0b9c*/ 0x00000003,
+ /*0b9d*/ 0x0002c000,
+ /*0b9e*/ 0x02c002c0,
+ /*0b9f*/ 0x000002c0,
+ /*0ba0*/ 0x08040201,
+ /*0ba1*/ 0x03421342,
+ /*0ba2*/ 0x00000342,
+ /*0ba3*/ 0x00000000,
+ /*0ba4*/ 0x00000000,
+ /*0ba5*/ 0x05030000,
+ /*0ba6*/ 0x00010700,
+ /*0ba7*/ 0x00000014,
+ /*0ba8*/ 0x00027f6e,
+ /*0ba9*/ 0x047f027f,
+ /*0baa*/ 0x00027f6e,
+ /*0bab*/ 0x00047f6e,
+ /*0bac*/ 0x0003554f,
+ /*0bad*/ 0x0001554f,
+ /*0bae*/ 0x0001554f,
+ /*0baf*/ 0x0001554f,
+ /*0bb0*/ 0x0001554f,
+ /*0bb1*/ 0x00003fee,
+ /*0bb2*/ 0x0001554f,
+ /*0bb3*/ 0x00003fee,
+ /*0bb4*/ 0x0001554f,
+ /*0bb5*/ 0x00027f6e,
+ /*0bb6*/ 0x0001554f,
+ /*0bb7*/ 0x00004011,
+ /*0bb8*/ 0x00004410,
+ /*0bb9*/ 0x00000000,
+ /*0bba*/ 0x00000000,
+ /*0bbb*/ 0x00000000,
+ /*0bbc*/ 0x00000265,
+ /*0bbd*/ 0x00000000,
+ /*0bbe*/ 0x00040401,
+ /*0bbf*/ 0x00000000,
+ /*0bc0*/ 0x03000000,
+ /*0bc1*/ 0x00000020,
+ /*0bc2*/ 0x00000000,
+ /*0bc3*/ 0x00000000,
+ /*0bc4*/ 0x04102006,
+ /*0bc5*/ 0x00041020,
+ /*0bc6*/ 0x01c98c98,
+ /*0bc7*/ 0x00400000,
+ /*0bc8*/ 0x00000000,
+ /*0bc9*/ 0x0001ffff,
+ /*0bca*/ 0x00000000,
+ /*0bcb*/ 0x00000000,
+ /*0bcc*/ 0x00000001,
+ /*0bcd*/ 0x00000000,
+ /*0bce*/ 0x00000000,
+ /*0bcf*/ 0x00000000,
+ /*0bd0*/ 0x76543210,
+ /*0bd1*/ 0x06010198,
+ /*0bd2*/ 0x00000000,
+ /*0bd3*/ 0x00000000,
+ /*0bd4*/ 0x04070000,
+ /*0bd5*/ 0x00000001,
+ /*0bd6*/ 0x00000f00
};
static const uint32_t DDR_PI_REGSET_M3N[DDR_PI_REGSET_NUM_M3N] = {
-/*0200*/ 0x00000b00,
-/*0201*/ 0x00000101,
-/*0202*/ 0x01640000,
-/*0203*/ 0x00000014,
-/*0204*/ 0x00000014,
-/*0205*/ 0x00000014,
-/*0206*/ 0x00000014,
-/*0207*/ 0x00000000,
-/*0208*/ 0x00000000,
-/*0209*/ 0x0000ffff,
-/*020a*/ 0x00000000,
-/*020b*/ 0x0000ffff,
-/*020c*/ 0x00000000,
-/*020d*/ 0x0000ffff,
-/*020e*/ 0x0000304c,
-/*020f*/ 0x00000200,
-/*0210*/ 0x00000200,
-/*0211*/ 0x00000200,
-/*0212*/ 0x00000200,
-/*0213*/ 0x0000304c,
-/*0214*/ 0x00000200,
-/*0215*/ 0x00000200,
-/*0216*/ 0x00000200,
-/*0217*/ 0x00000200,
-/*0218*/ 0x0000304c,
-/*0219*/ 0x00000200,
-/*021a*/ 0x00000200,
-/*021b*/ 0x00000200,
-/*021c*/ 0x00000200,
-/*021d*/ 0x00010000,
-/*021e*/ 0x00000003,
-/*021f*/ 0x01000001,
-/*0220*/ 0x00000000,
-/*0221*/ 0x00000000,
-/*0222*/ 0x00000000,
-/*0223*/ 0x00000000,
-/*0224*/ 0x00000000,
-/*0225*/ 0x00000000,
-/*0226*/ 0x00000000,
-/*0227*/ 0x00000000,
-/*0228*/ 0x00000000,
-/*0229*/ 0x00000000,
-/*022a*/ 0x00000000,
-/*022b*/ 0x00000000,
-/*022c*/ 0x00000000,
-/*022d*/ 0x00000000,
-/*022e*/ 0x00000000,
-/*022f*/ 0x00000000,
-/*0230*/ 0x0f000101,
-/*0231*/ 0x084d3129,
-/*0232*/ 0x0e0c0004,
-/*0233*/ 0x000e5000,
-/*0234*/ 0x01000250,
-/*0235*/ 0x00000003,
-/*0236*/ 0x00000046,
-/*0237*/ 0x000000cf,
-/*0238*/ 0x00001826,
-/*0239*/ 0x000000cf,
-/*023a*/ 0x00001826,
-/*023b*/ 0x00000000,
-/*023c*/ 0x00000000,
-/*023d*/ 0x00000000,
-/*023e*/ 0x00000000,
-/*023f*/ 0x00000000,
-/*0240*/ 0x00000000,
-/*0241*/ 0x00000000,
-/*0242*/ 0x00000000,
-/*0243*/ 0x00000000,
-/*0244*/ 0x00000000,
-/*0245*/ 0x01000000,
-/*0246*/ 0x00040404,
-/*0247*/ 0x01280a00,
-/*0248*/ 0x00000001,
-/*0249*/ 0x00000000,
-/*024a*/ 0x03000f00,
-/*024b*/ 0x00200020,
-/*024c*/ 0x00000020,
-/*024d*/ 0x00000000,
-/*024e*/ 0x00000000,
-/*024f*/ 0x00010002,
-/*0250*/ 0x01010001,
-/*0251*/ 0x02010100,
-/*0252*/ 0x08040402,
-/*0253*/ 0x00000008,
-/*0254*/ 0x00000000,
-/*0255*/ 0x04080803,
-/*0256*/ 0x00001515,
-/*0257*/ 0x00000000,
-/*0258*/ 0x000000aa,
-/*0259*/ 0x00000055,
-/*025a*/ 0x000000b5,
-/*025b*/ 0x0000004a,
-/*025c*/ 0x00000056,
-/*025d*/ 0x000000a9,
-/*025e*/ 0x000000a9,
-/*025f*/ 0x000000b5,
-/*0260*/ 0x00000000,
-/*0261*/ 0x00000000,
-/*0262*/ 0x0f000000,
-/*0263*/ 0x00001e0f,
-/*0264*/ 0x000007d0,
-/*0265*/ 0x01000300,
-/*0266*/ 0x00000100,
-/*0267*/ 0x00000000,
-/*0268*/ 0x00000000,
-/*0269*/ 0x01000000,
-/*026a*/ 0x00010101,
-/*026b*/ 0x000e0e0e,
-/*026c*/ 0x000c0c0c,
-/*026d*/ 0x01060601,
-/*026e*/ 0x04041717,
-/*026f*/ 0x00000004,
-/*0270*/ 0x00000300,
-/*0271*/ 0x17030000,
-/*0272*/ 0x00060018,
-/*0273*/ 0x00160028,
-/*0274*/ 0x00160028,
-/*0275*/ 0x00000000,
-/*0276*/ 0x00000000,
-/*0277*/ 0x00000000,
-/*0278*/ 0x0a000000,
-/*0279*/ 0x00010a14,
-/*027a*/ 0x00030005,
-/*027b*/ 0x0003018d,
-/*027c*/ 0x000a018d,
-/*027d*/ 0x00060100,
-/*027e*/ 0x01000006,
-/*027f*/ 0x018e018e,
-/*0280*/ 0x018e0100,
-/*0281*/ 0x1e1a018e,
-/*0282*/ 0x1e1a1e1a,
-/*0283*/ 0x01010204,
-/*0284*/ 0x06501001,
-/*0285*/ 0x090d0a07,
-/*0286*/ 0x090d0a07,
-/*0287*/ 0x0811180f,
-/*0288*/ 0x00ff1102,
-/*0289*/ 0x00ff1000,
-/*028a*/ 0x00ff1000,
-/*028b*/ 0x04041000,
-/*028c*/ 0x18020100,
-/*028d*/ 0x01010018,
-/*028e*/ 0x005f005f,
-/*028f*/ 0x005f005f,
-/*0290*/ 0x050f0000,
-/*0291*/ 0x051e051e,
-/*0292*/ 0x0c01021e,
-/*0293*/ 0x00000c0c,
-/*0294*/ 0x00003400,
-/*0295*/ 0x00000000,
-/*0296*/ 0x00000000,
-/*0297*/ 0x00000000,
-/*0298*/ 0x00000000,
-/*0299*/ 0x002e00d4,
-/*029a*/ 0x11360031,
-/*029b*/ 0x00d41611,
-/*029c*/ 0x0031002e,
-/*029d*/ 0x16111136,
-/*029e*/ 0x002e00d4,
-/*029f*/ 0x11360031,
-/*02a0*/ 0x00001611,
-/*02a1*/ 0x002e00d4,
-/*02a2*/ 0x11360031,
-/*02a3*/ 0x00d41611,
-/*02a4*/ 0x0031002e,
-/*02a5*/ 0x16111136,
-/*02a6*/ 0x002e00d4,
-/*02a7*/ 0x11360031,
-/*02a8*/ 0x00001611,
-/*02a9*/ 0x002e00d4,
-/*02aa*/ 0x11360031,
-/*02ab*/ 0x00d41611,
-/*02ac*/ 0x0031002e,
-/*02ad*/ 0x16111136,
-/*02ae*/ 0x002e00d4,
-/*02af*/ 0x11360031,
-/*02b0*/ 0x00001611,
-/*02b1*/ 0x002e00d4,
-/*02b2*/ 0x11360031,
-/*02b3*/ 0x00d41611,
-/*02b4*/ 0x0031002e,
-/*02b5*/ 0x16111136,
-/*02b6*/ 0x002e00d4,
-/*02b7*/ 0x11360031,
-/*02b8*/ 0x00001611,
-/*02b9*/ 0x00018d00,
-/*02ba*/ 0x018d018d,
-/*02bb*/ 0x1d220c08,
-/*02bc*/ 0x00001f12,
-/*02bd*/ 0x4301b344,
-/*02be*/ 0x17032006,
-/*02bf*/ 0x220c1010,
-/*02c0*/ 0x001f121d,
-/*02c1*/ 0x4301b344,
-/*02c2*/ 0x17062006,
-/*02c3*/ 0x220c1010,
-/*02c4*/ 0x001f121d,
-/*02c5*/ 0x4301b344,
-/*02c6*/ 0x17182006,
-/*02c7*/ 0x00021010,
-/*02c8*/ 0x00020002,
-/*02c9*/ 0x00020002,
-/*02ca*/ 0x00020002,
-/*02cb*/ 0x00020002,
-/*02cc*/ 0x00000002,
-/*02cd*/ 0x00000000,
-/*02ce*/ 0x00000000,
-/*02cf*/ 0x00000000,
-/*02d0*/ 0x00000000,
-/*02d1*/ 0x00000000,
-/*02d2*/ 0x00000000,
-/*02d3*/ 0x00000000,
-/*02d4*/ 0x00000000,
-/*02d5*/ 0x00000000,
-/*02d6*/ 0x00000000,
-/*02d7*/ 0x00000000,
-/*02d8*/ 0x00000000,
-/*02d9*/ 0x00000400,
-/*02da*/ 0x15141312,
-/*02db*/ 0x11100f0e,
-/*02dc*/ 0x080b0c0d,
-/*02dd*/ 0x05040a09,
-/*02de*/ 0x01000706,
-/*02df*/ 0x00000302,
-/*02e0*/ 0x01030201,
-/*02e1*/ 0x00304c08,
-/*02e2*/ 0x0001e2f8,
-/*02e3*/ 0x0000304c,
-/*02e4*/ 0x0001e2f8,
-/*02e5*/ 0x0000304c,
-/*02e6*/ 0x0001e2f8,
-/*02e7*/ 0x08000000,
-/*02e8*/ 0x00000100,
-/*02e9*/ 0x00000000,
-/*02ea*/ 0x00000000,
-/*02eb*/ 0x00000000,
-/*02ec*/ 0x00000000,
-/*02ed*/ 0x00010000,
-/*02ee*/ 0x00000000,
-/*02ef*/ 0x00000000,
-/*02f0*/ 0x00000000,
-/*02f1*/ 0x00000000,
-/*02f2*/ 0x00000000,
-/*02f3*/ 0x00000000,
-/*02f4*/ 0x00000000,
-/*02f5*/ 0x00000000,
-/*02f6*/ 0x00000000,
-/*02f7*/ 0x00000000,
-/*02f8*/ 0x00000000,
-/*02f9*/ 0x00000000,
-/*02fa*/ 0x00000000,
-/*02fb*/ 0x00000000,
-/*02fc*/ 0x00000000,
-/*02fd*/ 0x00000000,
-/*02fe*/ 0x00000000,
-/*02ff*/ 0x00000000,
-/*0300*/ 0x00000000,
-/*0301*/ 0x00000000,
-/*0302*/ 0x00000000,
-/*0303*/ 0x00000000,
-/*0304*/ 0x00000000,
-/*0305*/ 0x00000000,
-/*0306*/ 0x00000000,
-/*0307*/ 0x00000000,
-/*0308*/ 0x00000000,
-/*0309*/ 0x00000000,
-/*030a*/ 0x00000000,
-/*030b*/ 0x00000000,
-/*030c*/ 0x00000000,
-/*030d*/ 0x00000000,
-/*030e*/ 0x00000000,
-/*030f*/ 0x00050002,
-/*0310*/ 0x015c0057,
-/*0311*/ 0x01000100,
-/*0312*/ 0x01020001,
-/*0313*/ 0x00010300,
-/*0314*/ 0x05000104,
-/*0315*/ 0x01060001,
-/*0316*/ 0x00010700,
-/*0317*/ 0x00000000,
-/*0318*/ 0x00000000,
-/*0319*/ 0x00000001,
-/*031a*/ 0x00000000,
-/*031b*/ 0x00000000,
-/*031c*/ 0x00000000,
-/*031d*/ 0x20080101
+ /*0200*/ 0x00000b00,
+ /*0201*/ 0x00000101,
+ /*0202*/ 0x01640000,
+ /*0203*/ 0x00000014,
+ /*0204*/ 0x00000014,
+ /*0205*/ 0x00000014,
+ /*0206*/ 0x00000014,
+ /*0207*/ 0x00000000,
+ /*0208*/ 0x00000000,
+ /*0209*/ 0x0000ffff,
+ /*020a*/ 0x00000000,
+ /*020b*/ 0x0000ffff,
+ /*020c*/ 0x00000000,
+ /*020d*/ 0x0000ffff,
+ /*020e*/ 0x0000304c,
+ /*020f*/ 0x00000200,
+ /*0210*/ 0x00000200,
+ /*0211*/ 0x00000200,
+ /*0212*/ 0x00000200,
+ /*0213*/ 0x0000304c,
+ /*0214*/ 0x00000200,
+ /*0215*/ 0x00000200,
+ /*0216*/ 0x00000200,
+ /*0217*/ 0x00000200,
+ /*0218*/ 0x0000304c,
+ /*0219*/ 0x00000200,
+ /*021a*/ 0x00000200,
+ /*021b*/ 0x00000200,
+ /*021c*/ 0x00000200,
+ /*021d*/ 0x00010000,
+ /*021e*/ 0x00000003,
+ /*021f*/ 0x01000001,
+ /*0220*/ 0x00000000,
+ /*0221*/ 0x00000000,
+ /*0222*/ 0x00000000,
+ /*0223*/ 0x00000000,
+ /*0224*/ 0x00000000,
+ /*0225*/ 0x00000000,
+ /*0226*/ 0x00000000,
+ /*0227*/ 0x00000000,
+ /*0228*/ 0x00000000,
+ /*0229*/ 0x00000000,
+ /*022a*/ 0x00000000,
+ /*022b*/ 0x00000000,
+ /*022c*/ 0x00000000,
+ /*022d*/ 0x00000000,
+ /*022e*/ 0x00000000,
+ /*022f*/ 0x00000000,
+ /*0230*/ 0x0f000101,
+ /*0231*/ 0x084d3129,
+ /*0232*/ 0x0e0c0004,
+ /*0233*/ 0x000e5000,
+ /*0234*/ 0x01000250,
+ /*0235*/ 0x00000003,
+ /*0236*/ 0x00000046,
+ /*0237*/ 0x000000cf,
+ /*0238*/ 0x00001826,
+ /*0239*/ 0x000000cf,
+ /*023a*/ 0x00001826,
+ /*023b*/ 0x00000000,
+ /*023c*/ 0x00000000,
+ /*023d*/ 0x00000000,
+ /*023e*/ 0x00000000,
+ /*023f*/ 0x00000000,
+ /*0240*/ 0x00000000,
+ /*0241*/ 0x00000000,
+ /*0242*/ 0x00000000,
+ /*0243*/ 0x00000000,
+ /*0244*/ 0x00000000,
+ /*0245*/ 0x01000000,
+ /*0246*/ 0x00040404,
+ /*0247*/ 0x01280a00,
+ /*0248*/ 0x00000001,
+ /*0249*/ 0x00000000,
+ /*024a*/ 0x03000f00,
+ /*024b*/ 0x00200020,
+ /*024c*/ 0x00000020,
+ /*024d*/ 0x00000000,
+ /*024e*/ 0x00000000,
+ /*024f*/ 0x00010002,
+ /*0250*/ 0x01010001,
+ /*0251*/ 0x02010100,
+ /*0252*/ 0x08040402,
+ /*0253*/ 0x00000008,
+ /*0254*/ 0x00000000,
+ /*0255*/ 0x04080803,
+ /*0256*/ 0x00001515,
+ /*0257*/ 0x00000000,
+ /*0258*/ 0x000000aa,
+ /*0259*/ 0x00000055,
+ /*025a*/ 0x000000b5,
+ /*025b*/ 0x0000004a,
+ /*025c*/ 0x00000056,
+ /*025d*/ 0x000000a9,
+ /*025e*/ 0x000000a9,
+ /*025f*/ 0x000000b5,
+ /*0260*/ 0x00000000,
+ /*0261*/ 0x00000000,
+ /*0262*/ 0x0f000000,
+ /*0263*/ 0x00001e0f,
+ /*0264*/ 0x000007d0,
+ /*0265*/ 0x01000300,
+ /*0266*/ 0x00000100,
+ /*0267*/ 0x00000000,
+ /*0268*/ 0x00000000,
+ /*0269*/ 0x01000000,
+ /*026a*/ 0x00010101,
+ /*026b*/ 0x000e0e0e,
+ /*026c*/ 0x000c0c0c,
+ /*026d*/ 0x01060601,
+ /*026e*/ 0x04041717,
+ /*026f*/ 0x00000004,
+ /*0270*/ 0x00000300,
+ /*0271*/ 0x17030000,
+ /*0272*/ 0x00060018,
+ /*0273*/ 0x00160028,
+ /*0274*/ 0x00160028,
+ /*0275*/ 0x00000000,
+ /*0276*/ 0x00000000,
+ /*0277*/ 0x00000000,
+ /*0278*/ 0x0a000000,
+ /*0279*/ 0x00010a14,
+ /*027a*/ 0x00030005,
+ /*027b*/ 0x0003018d,
+ /*027c*/ 0x000a018d,
+ /*027d*/ 0x00060100,
+ /*027e*/ 0x01000006,
+ /*027f*/ 0x018e018e,
+ /*0280*/ 0x018e0100,
+ /*0281*/ 0x1e1a018e,
+ /*0282*/ 0x1e1a1e1a,
+ /*0283*/ 0x01010204,
+ /*0284*/ 0x06501001,
+ /*0285*/ 0x090d0a07,
+ /*0286*/ 0x090d0a07,
+ /*0287*/ 0x0811180f,
+ /*0288*/ 0x00ff1102,
+ /*0289*/ 0x00ff1000,
+ /*028a*/ 0x00ff1000,
+ /*028b*/ 0x04041000,
+ /*028c*/ 0x18020100,
+ /*028d*/ 0x01010018,
+ /*028e*/ 0x005f005f,
+ /*028f*/ 0x005f005f,
+ /*0290*/ 0x050f0000,
+ /*0291*/ 0x051e051e,
+ /*0292*/ 0x0c01021e,
+ /*0293*/ 0x00000c0c,
+ /*0294*/ 0x00003400,
+ /*0295*/ 0x00000000,
+ /*0296*/ 0x00000000,
+ /*0297*/ 0x00000000,
+ /*0298*/ 0x00000000,
+ /*0299*/ 0x002e00d4,
+ /*029a*/ 0x11360031,
+ /*029b*/ 0x00d41611,
+ /*029c*/ 0x0031002e,
+ /*029d*/ 0x16111136,
+ /*029e*/ 0x002e00d4,
+ /*029f*/ 0x11360031,
+ /*02a0*/ 0x00001611,
+ /*02a1*/ 0x002e00d4,
+ /*02a2*/ 0x11360031,
+ /*02a3*/ 0x00d41611,
+ /*02a4*/ 0x0031002e,
+ /*02a5*/ 0x16111136,
+ /*02a6*/ 0x002e00d4,
+ /*02a7*/ 0x11360031,
+ /*02a8*/ 0x00001611,
+ /*02a9*/ 0x002e00d4,
+ /*02aa*/ 0x11360031,
+ /*02ab*/ 0x00d41611,
+ /*02ac*/ 0x0031002e,
+ /*02ad*/ 0x16111136,
+ /*02ae*/ 0x002e00d4,
+ /*02af*/ 0x11360031,
+ /*02b0*/ 0x00001611,
+ /*02b1*/ 0x002e00d4,
+ /*02b2*/ 0x11360031,
+ /*02b3*/ 0x00d41611,
+ /*02b4*/ 0x0031002e,
+ /*02b5*/ 0x16111136,
+ /*02b6*/ 0x002e00d4,
+ /*02b7*/ 0x11360031,
+ /*02b8*/ 0x00001611,
+ /*02b9*/ 0x00018d00,
+ /*02ba*/ 0x018d018d,
+ /*02bb*/ 0x1d220c08,
+ /*02bc*/ 0x00001f12,
+ /*02bd*/ 0x4301b344,
+ /*02be*/ 0x17032006,
+ /*02bf*/ 0x220c1010,
+ /*02c0*/ 0x001f121d,
+ /*02c1*/ 0x4301b344,
+ /*02c2*/ 0x17062006,
+ /*02c3*/ 0x220c1010,
+ /*02c4*/ 0x001f121d,
+ /*02c5*/ 0x4301b344,
+ /*02c6*/ 0x17182006,
+ /*02c7*/ 0x00021010,
+ /*02c8*/ 0x00020002,
+ /*02c9*/ 0x00020002,
+ /*02ca*/ 0x00020002,
+ /*02cb*/ 0x00020002,
+ /*02cc*/ 0x00000002,
+ /*02cd*/ 0x00000000,
+ /*02ce*/ 0x00000000,
+ /*02cf*/ 0x00000000,
+ /*02d0*/ 0x00000000,
+ /*02d1*/ 0x00000000,
+ /*02d2*/ 0x00000000,
+ /*02d3*/ 0x00000000,
+ /*02d4*/ 0x00000000,
+ /*02d5*/ 0x00000000,
+ /*02d6*/ 0x00000000,
+ /*02d7*/ 0x00000000,
+ /*02d8*/ 0x00000000,
+ /*02d9*/ 0x00000400,
+ /*02da*/ 0x15141312,
+ /*02db*/ 0x11100f0e,
+ /*02dc*/ 0x080b0c0d,
+ /*02dd*/ 0x05040a09,
+ /*02de*/ 0x01000706,
+ /*02df*/ 0x00000302,
+ /*02e0*/ 0x01030201,
+ /*02e1*/ 0x00304c08,
+ /*02e2*/ 0x0001e2f8,
+ /*02e3*/ 0x0000304c,
+ /*02e4*/ 0x0001e2f8,
+ /*02e5*/ 0x0000304c,
+ /*02e6*/ 0x0001e2f8,
+ /*02e7*/ 0x08000000,
+ /*02e8*/ 0x00000100,
+ /*02e9*/ 0x00000000,
+ /*02ea*/ 0x00000000,
+ /*02eb*/ 0x00000000,
+ /*02ec*/ 0x00000000,
+ /*02ed*/ 0x00010000,
+ /*02ee*/ 0x00000000,
+ /*02ef*/ 0x00000000,
+ /*02f0*/ 0x00000000,
+ /*02f1*/ 0x00000000,
+ /*02f2*/ 0x00000000,
+ /*02f3*/ 0x00000000,
+ /*02f4*/ 0x00000000,
+ /*02f5*/ 0x00000000,
+ /*02f6*/ 0x00000000,
+ /*02f7*/ 0x00000000,
+ /*02f8*/ 0x00000000,
+ /*02f9*/ 0x00000000,
+ /*02fa*/ 0x00000000,
+ /*02fb*/ 0x00000000,
+ /*02fc*/ 0x00000000,
+ /*02fd*/ 0x00000000,
+ /*02fe*/ 0x00000000,
+ /*02ff*/ 0x00000000,
+ /*0300*/ 0x00000000,
+ /*0301*/ 0x00000000,
+ /*0302*/ 0x00000000,
+ /*0303*/ 0x00000000,
+ /*0304*/ 0x00000000,
+ /*0305*/ 0x00000000,
+ /*0306*/ 0x00000000,
+ /*0307*/ 0x00000000,
+ /*0308*/ 0x00000000,
+ /*0309*/ 0x00000000,
+ /*030a*/ 0x00000000,
+ /*030b*/ 0x00000000,
+ /*030c*/ 0x00000000,
+ /*030d*/ 0x00000000,
+ /*030e*/ 0x00000000,
+ /*030f*/ 0x00050002,
+ /*0310*/ 0x015c0057,
+ /*0311*/ 0x01000100,
+ /*0312*/ 0x01020001,
+ /*0313*/ 0x00010300,
+ /*0314*/ 0x05000104,
+ /*0315*/ 0x01060001,
+ /*0316*/ 0x00010700,
+ /*0317*/ 0x00000000,
+ /*0318*/ 0x00000000,
+ /*0319*/ 0x00000001,
+ /*031a*/ 0x00000000,
+ /*031b*/ 0x00000000,
+ /*031c*/ 0x00000000,
+ /*031d*/ 0x20080101
};
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_regs.h b/drivers/staging/renesas/rcar/ddr/ddr_regs.h
new file mode 100644
index 0000000..ba26c69
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/ddr_regs.h
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BOOT_INIT_DRAM_REGDEF_H_
+#define BOOT_INIT_DRAM_REGDEF_H_
+
+/* DBSC registers */
+#define DBSC_DBSYSCONF0 0xE6790000U
+#define DBSC_DBSYSCONF1 0xE6790004U
+#define DBSC_DBPHYCONF0 0xE6790010U
+#define DBSC_DBKIND 0xE6790020U
+#define DBSC_DBMEMCONF(ch, cs) (0xE6790030U + 0x10U * (ch) + 0x04U * (cs))
+#define DBSC_DBMEMCONF_0_0 0xE6790030U
+#define DBSC_DBMEMCONF_0_1 0xE6790034U
+#define DBSC_DBMEMCONF_0_2 0xE6790038U
+#define DBSC_DBMEMCONF_0_3 0xE679003CU
+#define DBSC_DBMEMCONF_1_2 0xE6790048U
+#define DBSC_DBMEMCONF_1_3 0xE679004CU
+#define DBSC_DBMEMCONF_1_0 0xE6790040U
+#define DBSC_DBMEMCONF_1_1 0xE6790044U
+#define DBSC_DBMEMCONF_2_0 0xE6790050U
+#define DBSC_DBMEMCONF_2_1 0xE6790054U
+#define DBSC_DBMEMCONF_2_2 0xE6790058U
+#define DBSC_DBMEMCONF_2_3 0xE679005CU
+#define DBSC_DBMEMCONF_3_0 0xE6790060U
+#define DBSC_DBMEMCONF_3_1 0xE6790064U
+#define DBSC_DBMEMCONF_3_2 0xE6790068U
+#define DBSC_DBMEMCONF_3_3 0xE679006CU
+#define DBSC_DBSYSCNT0 0xE6790100U
+#define DBSC_DBSVCR1 0xE6790104U
+#define DBSC_DBSTATE0 0xE6790108U
+#define DBSC_DBSTATE1 0xE679010CU
+#define DBSC_DBINTEN 0xE6790180U
+#define DBSC_DBINTSTAT0 0xE6790184U
+#define DBSC_DBACEN 0xE6790200U
+#define DBSC_DBRFEN 0xE6790204U
+#define DBSC_DBCMD 0xE6790208U
+#define DBSC_DBWAIT 0xE6790210U
+#define DBSC_DBSYSCTRL0 0xE6790280U
+#define DBSC_DBTR(x) (0xE6790300U + 0x04U * (x))
+#define DBSC_DBTR0 0xE6790300U
+#define DBSC_DBTR1 0xE6790304U
+#define DBSC_DBTR2 0xE6790308U
+#define DBSC_DBTR3 0xE679030CU
+#define DBSC_DBTR4 0xE6790310U
+#define DBSC_DBTR5 0xE6790314U
+#define DBSC_DBTR6 0xE6790318U
+#define DBSC_DBTR7 0xE679031CU
+#define DBSC_DBTR8 0xE6790320U
+#define DBSC_DBTR9 0xE6790324U
+#define DBSC_DBTR10 0xE6790328U
+#define DBSC_DBTR11 0xE679032CU
+#define DBSC_DBTR12 0xE6790330U
+#define DBSC_DBTR13 0xE6790334U
+#define DBSC_DBTR14 0xE6790338U
+#define DBSC_DBTR15 0xE679033CU
+#define DBSC_DBTR16 0xE6790340U
+#define DBSC_DBTR17 0xE6790344U
+#define DBSC_DBTR18 0xE6790348U
+#define DBSC_DBTR19 0xE679034CU
+#define DBSC_DBTR20 0xE6790350U
+#define DBSC_DBTR21 0xE6790354U
+#define DBSC_DBTR22 0xE6790358U
+#define DBSC_DBTR23 0xE679035CU
+#define DBSC_DBTR24 0xE6790360U
+#define DBSC_DBTR25 0xE6790364U
+#define DBSC_DBTR26 0xE6790368U
+#define DBSC_DBBL 0xE6790400U
+#define DBSC_DBRFCNF1 0xE6790414U
+#define DBSC_DBRFCNF2 0xE6790418U
+#define DBSC_DBTSPCNF 0xE6790420U
+#define DBSC_DBCALCNF 0xE6790424U
+#define DBSC_DBRNK(x) (0xE6790430U + 0x04U * (x))
+#define DBSC_DBRNK2 0xE6790438U
+#define DBSC_DBRNK3 0xE679043CU
+#define DBSC_DBRNK4 0xE6790440U
+#define DBSC_DBRNK5 0xE6790444U
+#define DBSC_DBPDNCNF 0xE6790450U
+#define DBSC_DBODT(x) (0xE6790460U + 0x04U * (x))
+#define DBSC_DBODT0 0xE6790460U
+#define DBSC_DBODT1 0xE6790464U
+#define DBSC_DBODT2 0xE6790468U
+#define DBSC_DBODT3 0xE679046CU
+#define DBSC_DBODT4 0xE6790470U
+#define DBSC_DBODT5 0xE6790474U
+#define DBSC_DBODT6 0xE6790478U
+#define DBSC_DBODT7 0xE679047CU
+#define DBSC_DBADJ0 0xE6790500U
+#define DBSC_DBDBICNT 0xE6790518U
+#define DBSC_DBDFIPMSTRCNF 0xE6790520U
+#define DBSC_DBDFICUPDCNF 0xE679052CU
+#define DBSC_DBDFISTAT(ch) (0xE6790600U + 0x40U * (ch))
+#define DBSC_DBDFISTAT_0 0xE6790600U
+#define DBSC_DBDFISTAT_1 0xE6790640U
+#define DBSC_DBDFISTAT_2 0xE6790680U
+#define DBSC_DBDFISTAT_3 0xE67906C0U
+#define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch))
+#define DBSC_DBDFICNT_0 0xE6790604U
+#define DBSC_DBDFICNT_1 0xE6790644U
+#define DBSC_DBDFICNT_2 0xE6790684U
+#define DBSC_DBDFICNT_3 0xE67906C4U
+#define DBSC_DBPDCNT0(ch) (0xE6790610U + 0x40U * (ch))
+#define DBSC_DBPDCNT0_0 0xE6790610U
+#define DBSC_DBPDCNT0_1 0xE6790650U
+#define DBSC_DBPDCNT0_2 0xE6790690U
+#define DBSC_DBPDCNT0_3 0xE67906D0U
+#define DBSC_DBPDCNT1(ch) (0xE6790614U + 0x40U * (ch))
+#define DBSC_DBPDCNT1_0 0xE6790614U
+#define DBSC_DBPDCNT1_1 0xE6790654U
+#define DBSC_DBPDCNT1_2 0xE6790694U
+#define DBSC_DBPDCNT1_3 0xE67906D4U
+#define DBSC_DBPDCNT2(ch) (0xE6790618U + 0x40U * (ch))
+#define DBSC_DBPDCNT2_0 0xE6790618U
+#define DBSC_DBPDCNT2_1 0xE6790658U
+#define DBSC_DBPDCNT2_2 0xE6790698U
+#define DBSC_DBPDCNT2_3 0xE67906D8U
+#define DBSC_DBPDCNT3(ch) (0xE679061CU + 0x40U * (ch))
+#define DBSC_DBPDCNT3_0 0xE679061CU
+#define DBSC_DBPDCNT3_1 0xE679065CU
+#define DBSC_DBPDCNT3_2 0xE679069CU
+#define DBSC_DBPDCNT3_3 0xE67906DCU
+#define DBSC_DBPDLK(ch) (0xE6790620U + 0x40U * (ch))
+#define DBSC_DBPDLK_0 0xE6790620U
+#define DBSC_DBPDLK_1 0xE6790660U
+#define DBSC_DBPDLK_2 0xE67906a0U
+#define DBSC_DBPDLK_3 0xE67906e0U
+#define DBSC_DBPDRGA(ch) (0xE6790624U + 0x40U * (ch))
+#define DBSC_DBPDRGD(ch) (0xE6790628U + 0x40U * (ch))
+#define DBSC_DBPDRGA_0 0xE6790624U
+#define DBSC_DBPDRGD_0 0xE6790628U
+#define DBSC_DBPDRGA_1 0xE6790664U
+#define DBSC_DBPDRGD_1 0xE6790668U
+#define DBSC_DBPDRGA_2 0xE67906A4U
+#define DBSC_DBPDRGD_2 0xE67906A8U
+#define DBSC_DBPDRGA_3 0xE67906E4U
+#define DBSC_DBPDRGD_3 0xE67906E8U
+#define DBSC_DBPDSTAT(ch) (0xE6790630U + 0x40U * (ch))
+#define DBSC_DBPDSTAT_0 0xE6790630U
+#define DBSC_DBPDSTAT_1 0xE6790670U
+#define DBSC_DBPDSTAT_2 0xE67906B0U
+#define DBSC_DBPDSTAT_3 0xE67906F0U
+#define DBSC_DBBUS0CNF0 0xE6790800U
+#define DBSC_DBBUS0CNF1 0xE6790804U
+#define DBSC_DBCAM0CNF1 0xE6790904U
+#define DBSC_DBCAM0CNF2 0xE6790908U
+#define DBSC_DBCAM0CNF3 0xE679090CU
+#define DBSC_DBBSWAP 0xE67909F0U
+#define DBSC_DBBCAMDIS 0xE67909FCU
+#define DBSC_DBSCHCNT0 0xE6791000U
+#define DBSC_DBSCHCNT1 0xE6791004U
+#define DBSC_DBSCHSZ0 0xE6791010U
+#define DBSC_DBSCHRW0 0xE6791020U
+#define DBSC_DBSCHRW1 0xE6791024U
+#define DBSC_DBSCHQOS_0(x) (0xE6791030U + 0x10U * (x))
+#define DBSC_DBSCHQOS_1(x) (0xE6791034U + 0x10U * (x))
+#define DBSC_DBSCHQOS_2(x) (0xE6791038U + 0x10U * (x))
+#define DBSC_DBSCHQOS_3(x) (0xE679103CU + 0x10U * (x))
+#define DBSC_DBSCHQOS00 0xE6791030U
+#define DBSC_DBSCHQOS01 0xE6791034U
+#define DBSC_DBSCHQOS02 0xE6791038U
+#define DBSC_DBSCHQOS03 0xE679103CU
+#define DBSC_DBSCHQOS10 0xE6791040U
+#define DBSC_DBSCHQOS11 0xE6791044U
+#define DBSC_DBSCHQOS12 0xE6791048U
+#define DBSC_DBSCHQOS13 0xE679104CU
+#define DBSC_DBSCHQOS20 0xE6791050U
+#define DBSC_DBSCHQOS21 0xE6791054U
+#define DBSC_DBSCHQOS22 0xE6791058U
+#define DBSC_DBSCHQOS23 0xE679105CU
+#define DBSC_DBSCHQOS30 0xE6791060U
+#define DBSC_DBSCHQOS31 0xE6791064U
+#define DBSC_DBSCHQOS32 0xE6791068U
+#define DBSC_DBSCHQOS33 0xE679106CU
+#define DBSC_DBSCHQOS40 0xE6791070U
+#define DBSC_DBSCHQOS41 0xE6791074U
+#define DBSC_DBSCHQOS42 0xE6791078U
+#define DBSC_DBSCHQOS43 0xE679107CU
+#define DBSC_DBSCHQOS50 0xE6791080U
+#define DBSC_DBSCHQOS51 0xE6791084U
+#define DBSC_DBSCHQOS52 0xE6791088U
+#define DBSC_DBSCHQOS53 0xE679108CU
+#define DBSC_DBSCHQOS60 0xE6791090U
+#define DBSC_DBSCHQOS61 0xE6791094U
+#define DBSC_DBSCHQOS62 0xE6791098U
+#define DBSC_DBSCHQOS63 0xE679109CU
+#define DBSC_DBSCHQOS70 0xE67910A0U
+#define DBSC_DBSCHQOS71 0xE67910A4U
+#define DBSC_DBSCHQOS72 0xE67910A8U
+#define DBSC_DBSCHQOS73 0xE67910ACU
+#define DBSC_DBSCHQOS80 0xE67910B0U
+#define DBSC_DBSCHQOS81 0xE67910B4U
+#define DBSC_DBSCHQOS82 0xE67910B8U
+#define DBSC_DBSCHQOS83 0xE67910BCU
+#define DBSC_DBSCHQOS90 0xE67910C0U
+#define DBSC_DBSCHQOS91 0xE67910C4U
+#define DBSC_DBSCHQOS92 0xE67910C8U
+#define DBSC_DBSCHQOS93 0xE67910CCU
+#define DBSC_DBSCHQOS100 0xE67910D0U
+#define DBSC_DBSCHQOS101 0xE67910D4U
+#define DBSC_DBSCHQOS102 0xE67910D8U
+#define DBSC_DBSCHQOS103 0xE67910DCU
+#define DBSC_DBSCHQOS110 0xE67910E0U
+#define DBSC_DBSCHQOS111 0xE67910E4U
+#define DBSC_DBSCHQOS112 0xE67910E8U
+#define DBSC_DBSCHQOS113 0xE67910ECU
+#define DBSC_DBSCHQOS120 0xE67910F0U
+#define DBSC_DBSCHQOS121 0xE67910F4U
+#define DBSC_DBSCHQOS122 0xE67910F8U
+#define DBSC_DBSCHQOS123 0xE67910FCU
+#define DBSC_DBSCHQOS130 0xE6791100U
+#define DBSC_DBSCHQOS131 0xE6791104U
+#define DBSC_DBSCHQOS132 0xE6791108U
+#define DBSC_DBSCHQOS133 0xE679110CU
+#define DBSC_DBSCHQOS140 0xE6791110U
+#define DBSC_DBSCHQOS141 0xE6791114U
+#define DBSC_DBSCHQOS142 0xE6791118U
+#define DBSC_DBSCHQOS143 0xE679111CU
+#define DBSC_DBSCHQOS150 0xE6791120U
+#define DBSC_DBSCHQOS151 0xE6791124U
+#define DBSC_DBSCHQOS152 0xE6791128U
+#define DBSC_DBSCHQOS153 0xE679112CU
+#define DBSC_DBSCTR0 0xE6791700U
+#define DBSC_DBSCTR1 0xE6791708U
+#define DBSC_DBSCHRW2 0xE679170CU
+#define DBSC_SCFCTST01(x) (0xE6791700U + 0x08U * (x))
+#define DBSC_SCFCTST0 0xE6791700U
+#define DBSC_SCFCTST1 0xE6791708U
+#define DBSC_SCFCTST2 0xE679170CU
+#define DBSC_DBMRRDR(chab) (0xE6791800U + 0x04U * (chab))
+#define DBSC_DBMRRDR_0 0xE6791800U
+#define DBSC_DBMRRDR_1 0xE6791804U
+#define DBSC_DBMRRDR_2 0xE6791808U
+#define DBSC_DBMRRDR_3 0xE679180CU
+#define DBSC_DBMRRDR_4 0xE6791810U
+#define DBSC_DBMRRDR_5 0xE6791814U
+#define DBSC_DBMRRDR_6 0xE6791818U
+#define DBSC_DBMRRDR_7 0xE679181CU
+#define DBSC_DBMEMSWAPCONF0 0xE6792000U
+
+/* CPG registers */
+#define CPG_BASE 0xE6150000U
+#define CPG_FRQCRB (CPG_BASE + 0x0004U)
+#define CPG_PLLECR (CPG_BASE + 0x00D0U)
+#define CPG_MSTPSR5 (CPG_BASE + 0x003CU)
+#define CPG_SRCR4 (CPG_BASE + 0x00BCU)
+#define CPG_PLL3CR (CPG_BASE + 0x00DCU)
+#define CPG_ZB3CKCR (CPG_BASE + 0x0380U)
+#define CPG_FRQCRD (CPG_BASE + 0x00E4U)
+#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U)
+#define CPG_CPGWPR (CPG_BASE + 0x0900U)
+#define CPG_SRSTCLR4 (CPG_BASE + 0x0950U)
+
+#endif /* BOOT_INIT_DRAM_REGDEF_H_*/
diff --git a/drivers/staging/renesas/rcar/ddr/dram_sub_func.c b/drivers/staging/renesas/rcar/ddr/dram_sub_func.c
index c6ab44a..ab8eabb 100644
--- a/drivers/staging/renesas/rcar/ddr/dram_sub_func.c
+++ b/drivers/staging/renesas/rcar/ddr/dram_sub_func.c
@@ -12,38 +12,30 @@
#if RCAR_SYSTEM_SUSPEND
/* Local defines */
-#define DRAM_BACKUP_GPIO_USE (0)
+#define DRAM_BACKUP_GPIO_USE 0
#include "iic_dvfs.h"
#if PMIC_ROHM_BD9571
-#define PMIC_SLAVE_ADDR (0x30U)
-#define PMIC_BKUP_MODE_CNT (0x20U)
-#define PMIC_QLLM_CNT (0x27U)
-#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4U))
-#define BIT_QLLM_DDR0_EN ((uint8_t)(1U << 0U))
-#define BIT_QLLM_DDR1_EN ((uint8_t)(1U << 1U))
+#define PMIC_SLAVE_ADDR 0x30U
+#define PMIC_BKUP_MODE_CNT 0x20U
+#define PMIC_QLLM_CNT 0x27U
+#define BIT_BKUP_CTRL_OUT BIT(4)
+#define BIT_QLLM_DDR0_EN BIT(0)
+#define BIT_QLLM_DDR1_EN BIT(1)
#endif
-#define GPIO_OUTDT1 (0xE6051008U)
-#define GPIO_OUTDT3 (0xE6053008U)
-#define GPIO_INDT3 (0xE605300CU)
-#define GPIO_OUTDT6 (0xE6055408U)
+#define GPIO_BKUP_REQB_SHIFT_SALVATOR 9U /* GP1_9 (BKUP_REQB) */
+#define GPIO_BKUP_TRG_SHIFT_SALVATOR 8U /* GP1_8 (BKUP_TRG) */
+#define GPIO_BKUP_REQB_SHIFT_EBISU 14U /* GP6_14(BKUP_REQB) */
+#define GPIO_BKUP_TRG_SHIFT_EBISU 13U /* GP6_13(BKUP_TRG) */
+#define GPIO_BKUP_REQB_SHIFT_CONDOR 1U /* GP3_1 (BKUP_REQB) */
+#define GPIO_BKUP_TRG_SHIFT_CONDOR 0U /* GP3_0 (BKUP_TRG) */
-#if DRAM_BACKUP_GPIO_USE == 1
-#define GPIO_BKUP_REQB_SHIFT_SALVATOR (9U) /* GP1_9 (BKUP_REQB) */
-#define GPIO_BKUP_REQB_SHIFT_EBISU (14U) /* GP6_14(BKUP_REQB) */
-#define GPIO_BKUP_REQB_SHIFT_CONDOR (1U) /* GP3_1 (BKUP_REQB) */
-#endif
-#define GPIO_BKUP_TRG_SHIFT_SALVATOR (8U) /* GP1_8 (BKUP_TRG) */
-#define GPIO_BKUP_TRG_SHIFT_EBISU (13U) /* GP6_13(BKUP_TRG) */
-#define GPIO_BKUP_TRG_SHIFT_CONDOR (0U) /* GP3_0 (BKUP_TRG) */
-
-#define DRAM_BKUP_TRG_LOOP_CNT (1000U)
+#define DRAM_BKUP_TRG_LOOP_CNT 1000U
#endif
-void rcar_dram_get_boot_status(uint32_t * status)
+void rcar_dram_get_boot_status(uint32_t *status)
{
#if RCAR_SYSTEM_SUSPEND
-
uint32_t reg_data;
uint32_t product;
uint32_t shift;
@@ -62,11 +54,10 @@
}
reg_data = mmio_read_32(gpio);
- if (0U != (reg_data & ((uint32_t)1U << shift))) {
+ if (reg_data & BIT(shift))
*status = DRAM_BOOT_STATUS_WARM;
- } else {
+ else
*status = DRAM_BOOT_STATUS_COLD;
- }
#else /* RCAR_SYSTEM_SUSPEND */
*status = DRAM_BOOT_STATUS_COLD;
#endif /* RCAR_SYSTEM_SUSPEND */
@@ -116,55 +107,55 @@
}
if (status == DRAM_BOOT_STATUS_WARM) {
-#if DRAM_BACKUP_GPIO_USE==1
- mmio_setbits_32(outd, 1U << reqb);
+#if DRAM_BACKUP_GPIO_USE == 1
+ mmio_setbits_32(outd, BIT(reqb));
#else
#if PMIC_ROHM_BD9571
/* Set BKUP_CRTL_OUT=High (BKUP mode cnt register) */
i2c_dvfs_ret = rcar_iic_dvfs_receive(PMIC_SLAVE_ADDR,
- PMIC_BKUP_MODE_CNT, &bkup_mode_cnt);
- if (0 != i2c_dvfs_ret) {
+ PMIC_BKUP_MODE_CNT,
+ &bkup_mode_cnt);
+ if (i2c_dvfs_ret) {
ERROR("BKUP mode cnt READ ERROR.\n");
ret = DRAM_UPDATE_STATUS_ERR;
} else {
bkup_mode_cnt &= (uint8_t)~BIT_BKUP_CTRL_OUT;
i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
- PMIC_BKUP_MODE_CNT, bkup_mode_cnt);
- if (0 != i2c_dvfs_ret) {
- ERROR("BKUP mode cnt WRITE ERROR. "
- "value = %d\n", bkup_mode_cnt);
+ PMIC_BKUP_MODE_CNT,
+ bkup_mode_cnt);
+ if (i2c_dvfs_ret) {
+ ERROR("BKUP mode cnt WRITE ERROR. value = %d\n",
+ bkup_mode_cnt);
ret = DRAM_UPDATE_STATUS_ERR;
}
}
#endif /* PMIC_ROHM_BD9571 */
-#endif /* DRAM_BACKUP_GPIO_USE==1 */
+#endif /* DRAM_BACKUP_GPIO_USE == 1 */
/* Wait BKUP_TRG=Low */
loop_count = DRAM_BKUP_TRG_LOOP_CNT;
- while (0U < loop_count) {
+ while (loop_count > 0) {
reg_data = mmio_read_32(gpio);
- if ((reg_data &
- ((uint32_t)1U << trg)) == 0U) {
+ if (!(reg_data & BIT(trg)))
break;
- }
loop_count--;
}
- if (0U == loop_count) {
- ERROR( "\nWarm booting...\n" \
- " The potential of BKUP_TRG did not switch " \
- "to Low.\n If you expect the operation of " \
- "cold boot,\n check the board configuration" \
- " (ex, Dip-SW) and/or the H/W failure.\n");
+
+ if (!loop_count) {
+ ERROR("\nWarm booting...\n"
+ " The potential of BKUP_TRG did not switch to Low.\n"
+ " If you expect the operation of cold boot,\n"
+ " check the board configuration (ex, Dip-SW) and/or the H/W failure.\n");
ret = DRAM_UPDATE_STATUS_ERR;
}
}
#if PMIC_ROHM_BD9571
- if(0 == ret) {
- qllm_cnt = (BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN);
+ if (!ret) {
+ qllm_cnt = BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN;
i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
- PMIC_QLLM_CNT, qllm_cnt);
- if (0 != i2c_dvfs_ret) {
- ERROR("QLLM cnt WRITE ERROR. "
- "value = %d\n", qllm_cnt);
+ PMIC_QLLM_CNT,
+ qllm_cnt);
+ if (i2c_dvfs_ret) {
+ ERROR("QLLM cnt WRITE ERROR. value = %d\n", qllm_cnt);
ret = DRAM_UPDATE_STATUS_ERR;
}
}
diff --git a/drivers/staging/renesas/rcar/ddr/dram_sub_func.h b/drivers/staging/renesas/rcar/ddr/dram_sub_func.h
index 7e88f42..69c4d86 100644
--- a/drivers/staging/renesas/rcar/ddr/dram_sub_func.h
+++ b/drivers/staging/renesas/rcar/ddr/dram_sub_func.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,11 +7,11 @@
#ifndef DRAM_SUB_FUNC_H
#define DRAM_SUB_FUNC_H
-#define DRAM_UPDATE_STATUS_ERR (-1)
-#define DRAM_BOOT_STATUS_COLD (0)
-#define DRAM_BOOT_STATUS_WARM (1)
+#define DRAM_UPDATE_STATUS_ERR -1
+#define DRAM_BOOT_STATUS_COLD 0
+#define DRAM_BOOT_STATUS_WARM 1
int32_t rcar_dram_update_boot_status(uint32_t status);
-void rcar_dram_get_boot_status(uint32_t * status);
+void rcar_dram_get_boot_status(uint32_t *status);
#endif /* DRAM_SUB_FUNC_H */
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 5f84ece..3ff2912 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -598,6 +598,8 @@
#define ESR_EC_SHIFT U(26)
#define ESR_EC_MASK U(0x3f)
#define ESR_EC_LENGTH U(6)
+#define ESR_ISS_SHIFT U(0)
+#define ESR_ISS_LENGTH U(25)
#define EC_UNKNOWN U(0x0)
#define EC_WFE_WFI U(0x1)
#define EC_AARCH32_CP15_MRC_MCR U(0x3)
@@ -624,6 +626,7 @@
#define EC_AARCH32_FP U(0x28)
#define EC_AARCH64_FP U(0x2c)
#define EC_SERROR U(0x2f)
+#define EC_BRK U(0x3c)
/*
* External Abort bit in Instruction and Data Aborts synchronous exception
@@ -898,4 +901,12 @@
******************************************************************************/
#define SSBS S3_3_C4_C2_6
+/*******************************************************************************
+ * Armv8.5 - Memory Tagging Extension Registers
+ ******************************************************************************/
+#define TFSRE0_EL1 S3_0_C5_C6_1
+#define TFSR_EL1 S3_0_C5_C6_0
+#define RGSR_EL1 S3_0_C1_C0_5
+#define GCR_EL1 S3_0_C1_C0_6
+
#endif /* ARCH_H */
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index c173706..c60f2e8 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -501,6 +501,12 @@
DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1)
+/* Armv8.5 MTE Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1)
+
#define IS_IN_EL(x) \
(GET_EL(read_CurrentEl()) == MODE_EL##x)
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index a36b7da..53396d4 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -333,7 +333,7 @@
* ---------------------------------------------------------------------
*/
.if \_init_c_runtime
-#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3)
+#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_INV_DCACHE)
/* -------------------------------------------------------------
* Invalidate the RW memory used by the BL31 image. This
* includes the data and NOBITS sections. This is done to
diff --git a/include/drivers/meson/gxl/crypto/sha_dma.h b/include/drivers/amlogic/crypto/sha_dma.h
similarity index 100%
rename from include/drivers/meson/gxl/crypto/sha_dma.h
rename to include/drivers/amlogic/crypto/sha_dma.h
diff --git a/include/drivers/meson/meson_console.h b/include/drivers/amlogic/meson_console.h
similarity index 100%
rename from include/drivers/meson/meson_console.h
rename to include/drivers/amlogic/meson_console.h
diff --git a/include/drivers/auth/mbedtls/mbedtls_config.h b/include/drivers/auth/mbedtls/mbedtls_config.h
index acfde26..6e179bb 100644
--- a/include/drivers/auth/mbedtls/mbedtls_config.h
+++ b/include/drivers/auth/mbedtls/mbedtls_config.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,6 +13,11 @@
#define TF_MBEDTLS_ECDSA 2
#define TF_MBEDTLS_RSA_AND_ECDSA 3
+#define TF_MBEDTLS_USE_RSA (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA \
+ || TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA)
+#define TF_MBEDTLS_USE_ECDSA (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA \
+ || TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA)
+
/*
* Hash algorithms currently supported on mbed TLS libraries
*/
@@ -54,19 +59,14 @@
#define MBEDTLS_PLATFORM_C
-#if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA)
+#if TF_MBEDTLS_USE_ECDSA
#define MBEDTLS_ECDSA_C
#define MBEDTLS_ECP_C
#define MBEDTLS_ECP_DP_SECP256R1_ENABLED
-#elif (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA)
+#endif
+#if TF_MBEDTLS_USE_RSA
#define MBEDTLS_RSA_C
#define MBEDTLS_X509_RSASSA_PSS_SUPPORT
-#elif (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA)
-#define MBEDTLS_RSA_C
-#define MBEDTLS_X509_RSASSA_PSS_SUPPORT
-#define MBEDTLS_ECDSA_C
-#define MBEDTLS_ECP_C
-#define MBEDTLS_ECP_DP_SECP256R1_ENABLED
#endif
#define MBEDTLS_SHA256_C
@@ -80,28 +80,41 @@
#define MBEDTLS_X509_CRT_PARSE_C
/* MPI / BIGNUM options */
-#define MBEDTLS_MPI_WINDOW_SIZE 2
-#define MBEDTLS_MPI_MAX_SIZE 256
+#define MBEDTLS_MPI_WINDOW_SIZE 2
+
+#if TF_MBEDTLS_USE_RSA
+#if TF_MBEDTLS_KEY_SIZE <= 2048
+#define MBEDTLS_MPI_MAX_SIZE 256
+#else
+#define MBEDTLS_MPI_MAX_SIZE 512
+#endif
+#else
+#define MBEDTLS_MPI_MAX_SIZE 256
+#endif
/* Memory buffer allocator options */
-#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 8
+#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 8
#ifndef __ASSEMBLER__
/* System headers required to build mbed TLS with the current configuration */
#include <stdlib.h>
-#include "mbedtls/check_config.h"
+#include <mbedtls/check_config.h>
#endif
/*
* Determine Mbed TLS heap size
* 13312 = 13*1024
- * 7168 = 7*1024
+ * 11264 = 11*1024
+ * 7168 = 7*1024
*/
-#if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA) \
- || (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA)
+#if TF_MBEDTLS_USE_ECDSA
#define TF_MBEDTLS_HEAP_SIZE U(13312)
-#elif (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA)
+#elif TF_MBEDTLS_USE_RSA
+#if TF_MBEDTLS_KEY_SIZE <= 2048
#define TF_MBEDTLS_HEAP_SIZE U(7168)
+#else
+#define TF_MBEDTLS_HEAP_SIZE U(11264)
+#endif
#endif
#endif /* MBEDTLS_CONFIG_H */
diff --git a/include/export/plat/mediatek/common/plat_params_exp.h b/include/export/plat/mediatek/common/plat_params_exp.h
new file mode 100644
index 0000000..d650030
--- /dev/null
+++ b/include/export/plat/mediatek/common/plat_params_exp.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_PLAT_MEDIATEK_COMMON_PLAT_PARAMS_EXP_H
+#define ARM_TRUSTED_FIRMWARE_EXPORT_PLAT_MEDIATEK_COMMON_PLAT_PARAMS_EXP_H
+
+/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
+
+#include "../../../lib/bl_aux_params/bl_aux_params_exp.h"
+
+/* param type */
+enum bl_aux_mtk_param_type {
+ BL_AUX_PARAM_MTK_RESET_GPIO = BL_AUX_PARAM_VENDOR_SPECIFIC_FIRST,
+};
+
+#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_PLAT_MEDIATEK_COMMON_PLAT_PARAMS_EXP_H */
diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h
index 09db12b..ea7181e 100644
--- a/include/lib/cpus/aarch64/cortex_a53.h
+++ b/include/lib/cpus/aarch64/cortex_a53.h
@@ -73,4 +73,11 @@
******************************************************************************/
#define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3
+/*******************************************************************************
+ * Helper function to access a53_cpuectlr_el1 register on Cortex-A53 CPUs
+ ******************************************************************************/
+#ifndef __ASSEMBLY__
+DEFINE_RENAME_SYSREG_RW_FUNCS(a53_cpuectlr_el1, CORTEX_A53_ECTLR_EL1)
+#endif
+
#endif /* CORTEX_A53_H */
diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h
index 1238c0e..fb4f1ec 100644
--- a/include/lib/cpus/aarch64/cortex_a73.h
+++ b/include/lib/cpus/aarch64/cortex_a73.h
@@ -35,4 +35,11 @@
#define CORTEX_A73_IMP_DEF_REG2 S3_0_C15_C0_2
+/*******************************************************************************
+ * Helper function to access a73_cpuectlr_el1 register on Cortex-A73 CPUs
+ ******************************************************************************/
+#ifndef __ASSEMBLY__
+DEFINE_RENAME_SYSREG_RW_FUNCS(a73_cpuectlr_el1, CORTEX_A73_CPUECTLR_EL1)
+#endif
+
#endif /* CORTEX_A73_H */
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index 64fa8a9..e90a6e7 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -123,10 +123,22 @@
#define CTX_TIMER_SYSREGS_END CTX_AARCH32_END
#endif /* NS_TIMER_SWITCH */
+#if CTX_INCLUDE_MTE_REGS
+#define CTX_TFSRE0_EL1 (CTX_TIMER_SYSREGS_END + U(0x0))
+#define CTX_TFSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x8))
+#define CTX_RGSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x10))
+#define CTX_GCR_EL1 (CTX_TIMER_SYSREGS_END + U(0x18))
+
+/* Align to the next 16 byte boundary */
+#define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20))
+#else
+#define CTX_MTE_REGS_END CTX_TIMER_SYSREGS_END
+#endif /* CTX_INCLUDE_MTE_REGS */
+
/*
* End of system registers.
*/
-#define CTX_SYSREGS_END CTX_TIMER_SYSREGS_END
+#define CTX_SYSREGS_END CTX_MTE_REGS_END
/*******************************************************************************
* Constants that allow assembler code to access members of and the 'fp_regs'
diff --git a/include/lib/libc/assert.h b/include/lib/libc/assert.h
index d04f9dc..486bbc2 100644
--- a/include/lib/libc/assert.h
+++ b/include/lib/libc/assert.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -30,12 +30,12 @@
#endif /* ENABLE_ASSERTIONS */
#if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_VERBOSE
-__dead2 void __assert(const char *file, unsigned int line,
+void __dead2 __assert(const char *file, unsigned int line,
const char *assertion);
#elif PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO
-__dead2 void __assert(const char *file, unsigned int line);
+void __dead2 __assert(const char *file, unsigned int line);
#else
-__dead2 void __assert(void);
+void __dead2 __assert(void);
#endif
#endif /* ASSERT_H */
diff --git a/lib/cpus/aarch64/neoverse_zeus.S b/lib/cpus/aarch64/neoverse_zeus.S
index 3d85013..44882b4 100644
--- a/lib/cpus/aarch64/neoverse_zeus.S
+++ b/lib/cpus/aarch64/neoverse_zeus.S
@@ -46,6 +46,16 @@
endfunc neoverse_zeus_errata_report
#endif
+func neoverse_zeus_reset_func
+ mov x19, x30
+
+ /* Disable speculative loads */
+ msr SSBS, xzr
+
+ isb
+ ret x19
+endfunc neoverse_zeus_reset_func
+
/* ---------------------------------------------
* This function provides Neoverse-Zeus specific
* register information for crash reporting.
@@ -66,5 +76,5 @@
endfunc neoverse_zeus_cpu_reg_dump
declare_cpu_ops neoverse_zeus, NEOVERSE_ZEUS_MIDR, \
- CPU_NO_RESET_FUNC, \
+ neoverse_zeus_reset_func, \
neoverse_zeus_core_pwr_dwn
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 53dc02e..37bb12c 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -145,6 +145,17 @@
str x14, [x0, #CTX_CNTKCTL_EL1]
#endif
+ /* Save MTE system registers if the build has instructed so */
+#if CTX_INCLUDE_MTE_REGS
+ mrs x15, TFSRE0_EL1
+ mrs x16, TFSR_EL1
+ stp x15, x16, [x0, #CTX_TFSRE0_EL1]
+
+ mrs x9, RGSR_EL1
+ mrs x10, GCR_EL1
+ stp x9, x10, [x0, #CTX_RGSR_EL1]
+#endif
+
ret
endfunc el1_sysregs_context_save
@@ -229,6 +240,16 @@
ldr x14, [x0, #CTX_CNTKCTL_EL1]
msr cntkctl_el1, x14
#endif
+ /* Restore MTE system registers if the build has instructed so */
+#if CTX_INCLUDE_MTE_REGS
+ ldp x11, x12, [x0, #CTX_TFSRE0_EL1]
+ msr TFSRE0_EL1, x11
+ msr TFSR_EL1, x12
+
+ ldp x13, x14, [x0, #CTX_RGSR_EL1]
+ msr RGSR_EL1, x13
+ msr GCR_EL1, x14
+#endif
/* No explict ISB required here as ERET covers it */
ret
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index bd5b3aa..446d9da 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -137,17 +137,30 @@
scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
#endif /* !CTX_INCLUDE_PAUTH_REGS */
- unsigned int mte = get_armv8_5_mte_support();
-
/*
- * Enable MTE support unilaterally for normal world if the CPU supports
- * it.
+ * Enable MTE support. Support is enabled unilaterally for the normal
+ * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is
+ * set.
*/
- if (mte != MTE_UNIMPLEMENTED) {
- if (security_state == NON_SECURE) {
- scr_el3 |= SCR_ATA_BIT;
- }
+ unsigned int mte = get_armv8_5_mte_support();
+#if CTX_INCLUDE_MTE_REGS
+ assert(mte == MTE_IMPLEMENTED_ELX);
+ scr_el3 |= SCR_ATA_BIT;
+#else
+ if (mte == MTE_IMPLEMENTED_EL0) {
+ /*
+ * Can enable MTE across both worlds as no MTE registers are
+ * used
+ */
+ scr_el3 |= SCR_ATA_BIT;
+ } else if (mte == MTE_IMPLEMENTED_ELX && security_state == NON_SECURE) {
+ /*
+ * Can only enable MTE in Non-Secure world without register
+ * saving
+ */
+ scr_el3 |= SCR_ATA_BIT;
}
+#endif
#ifdef IMAGE_BL31
/*
diff --git a/lib/libc/assert.c b/lib/libc/assert.c
index 60f1a86..49f59db 100644
--- a/lib/libc/assert.c
+++ b/lib/libc/assert.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -18,7 +18,8 @@
*/
#if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_VERBOSE
-void __assert(const char *file, unsigned int line, const char *assertion)
+void __dead2 __assert(const char *file, unsigned int line,
+ const char *assertion)
{
printf("ASSERT: %s:%d:%s\n", file, line, assertion);
backtrace("assert");
@@ -26,7 +27,7 @@
plat_panic_handler();
}
#elif PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO
-void __assert(const char *file, unsigned int line)
+void __dead2 __assert(const char *file, unsigned int line)
{
printf("ASSERT: %s:%d\n", file, line);
backtrace("assert");
@@ -34,7 +35,7 @@
plat_panic_handler();
}
#else
-void __assert(void)
+void __dead2 __assert(void)
{
backtrace("assert");
(void)console_flush();
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index 022c877..7c42be7 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -159,9 +159,10 @@
******************************************************************************/
unsigned int psci_is_last_on_cpu(void)
{
- int cpu_idx, my_idx = (int) plat_my_core_pos();
+ unsigned int cpu_idx, my_idx = plat_my_core_pos();
- for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) {
+ for (cpu_idx = 0; cpu_idx < (unsigned int)PLATFORM_CORE_COUNT;
+ cpu_idx++) {
if (cpu_idx == my_idx) {
assert(psci_get_aff_info_state() == AFF_STATE_ON);
continue;
@@ -192,6 +193,7 @@
pwrlvl = psci_get_suspend_pwrlvl();
if (pwrlvl == PSCI_INVALID_PWR_LVL)
pwrlvl = PLAT_MAX_PWR_LVL;
+ assert(pwrlvl < PSCI_INVALID_PWR_LVL);
return pwrlvl;
}
@@ -206,7 +208,7 @@
{
assert(pwrlvl > PSCI_CPU_PWR_LVL);
if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) &&
- (cpu_idx < PLATFORM_CORE_COUNT)) {
+ (cpu_idx < (unsigned int) PLATFORM_CORE_COUNT)) {
psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx] = req_pwr_state;
}
}
@@ -237,12 +239,12 @@
* assertion is added to prevent us from accessing the CPU power level.
*****************************************************************************/
static plat_local_state_t *psci_get_req_local_pwr_states(unsigned int pwrlvl,
- int cpu_idx)
+ unsigned int cpu_idx)
{
assert(pwrlvl > PSCI_CPU_PWR_LVL);
if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) &&
- (cpu_idx < PLATFORM_CORE_COUNT)) {
+ (cpu_idx < (unsigned int) PLATFORM_CORE_COUNT)) {
return &psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx];
} else
return NULL;
@@ -351,7 +353,7 @@
/*******************************************************************************
* PSCI helper function to get the parent nodes corresponding to a cpu_index.
******************************************************************************/
-void psci_get_parent_pwr_domain_nodes(int cpu_idx,
+void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx,
unsigned int end_lvl,
unsigned int *node_index)
{
@@ -417,7 +419,7 @@
psci_power_state_t *state_info)
{
unsigned int lvl, parent_idx, cpu_idx = plat_my_core_pos();
- int start_idx;
+ unsigned int start_idx;
unsigned int ncpus;
plat_local_state_t target_state, *req_states;
@@ -763,7 +765,7 @@
void psci_warmboot_entrypoint(void)
{
unsigned int end_pwrlvl;
- int cpu_idx = (int) plat_my_core_pos();
+ unsigned int cpu_idx = plat_my_core_pos();
unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h
index bbcc5cf..b49847c 100644
--- a/lib/psci/psci_private.h
+++ b/lib/psci/psci_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -55,16 +55,16 @@
return get_cpu_data(psci_svc_cpu_data.aff_info_state);
}
-static inline aff_info_state_t psci_get_aff_info_state_by_idx(int idx)
+static inline aff_info_state_t psci_get_aff_info_state_by_idx(unsigned int idx)
{
- return get_cpu_data_by_index((unsigned int)idx,
+ return get_cpu_data_by_index(idx,
psci_svc_cpu_data.aff_info_state);
}
-static inline void psci_set_aff_info_state_by_idx(int idx,
+static inline void psci_set_aff_info_state_by_idx(unsigned int idx,
aff_info_state_t aff_state)
{
- set_cpu_data_by_index((unsigned int)idx,
+ set_cpu_data_by_index(idx,
psci_svc_cpu_data.aff_info_state, aff_state);
}
@@ -88,9 +88,10 @@
return get_cpu_data(psci_svc_cpu_data.local_state);
}
-static inline plat_local_state_t psci_get_cpu_local_state_by_idx(int idx)
+static inline plat_local_state_t psci_get_cpu_local_state_by_idx(
+ unsigned int idx)
{
- return get_cpu_data_by_index((unsigned int)idx,
+ return get_cpu_data_by_index(idx,
psci_svc_cpu_data.local_state);
}
@@ -113,7 +114,7 @@
* Index of the first CPU power domain node level 0 which has this node
* as its parent.
*/
- int cpu_start_idx;
+ unsigned int cpu_start_idx;
/*
* Number of CPU power domains which are siblings of the domain indexed
@@ -269,7 +270,7 @@
psci_power_state_t *target_state);
int psci_validate_entry_point(entry_point_info_t *ep,
uintptr_t entrypoint, u_register_t context_id);
-void psci_get_parent_pwr_domain_nodes(int cpu_idx,
+void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx,
unsigned int end_lvl,
unsigned int *node_index);
void psci_do_state_coordination(unsigned int end_pwrlvl,
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index f63e46f..b6f7655 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -33,6 +33,9 @@
# when BL2_AT_EL3 is 1.
BL2_IN_XIP_MEM := 0
+# Do dcache invalidate upon BL2 entry at EL3
+BL2_INV_DCACHE := 1
+
# Select the branch protection features to use.
BRANCH_PROTECTION := 0
@@ -214,6 +217,11 @@
override ENABLE_SPE_FOR_LOWER_ELS := 0
endif
+# Include Memory Tagging Extension registers in cpu context. This must be set
+# to 1 if the platform wants to use this feature in the Secure world and MTE is
+# enabled at ELX.
+CTX_INCLUDE_MTE_REGS := 0
+
ENABLE_AMU := 0
# By default, enable Scalable Vector Extension if implemented for Non-secure
@@ -224,3 +232,5 @@
else
override ENABLE_SVE_FOR_NS := 0
endif
+
+SANITIZE_UB := off
diff --git a/make_helpers/tbbr/tbbr_tools.mk b/make_helpers/tbbr/tbbr_tools.mk
index afc007a..9c47cc7 100644
--- a/make_helpers/tbbr/tbbr_tools.mk
+++ b/make_helpers/tbbr/tbbr_tools.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -21,6 +21,7 @@
# Build options added by this file:
#
# KEY_ALG
+# KEY_SIZE
# ROT_KEY
# TRUSTED_WORLD_KEY
# NON_TRUSTED_WORLD_KEY
@@ -52,6 +53,7 @@
# packed in the FIP). Developers can use their own keys by specifying the proper
# build option in the command line when building the Trusted Firmware
$(if ${KEY_ALG},$(eval $(call CERT_ADD_CMD_OPT,${KEY_ALG},--key-alg)))
+$(if ${KEY_SIZE},$(eval $(call CERT_ADD_CMD_OPT,${KEY_SIZE},--key-size)))
$(if ${HASH_ALG},$(eval $(call CERT_ADD_CMD_OPT,${HASH_ALG},--hash-alg)))
$(if ${ROT_KEY},$(eval $(call CERT_ADD_CMD_OPT,${ROT_KEY},--rot-key)))
$(if ${ROT_KEY},$(eval $(call CERT_ADD_CMD_OPT,${ROT_KEY},--rot-key,FWU_)))
diff --git a/plat/meson/gxbb/aarch64/gxbb_helpers.S b/plat/amlogic/common/aarch64/aml_helpers.S
similarity index 82%
rename from plat/meson/gxbb/aarch64/gxbb_helpers.S
rename to plat/amlogic/common/aarch64/aml_helpers.S
index 760d6c4..39bff08 100644
--- a/plat/meson/gxbb/aarch64/gxbb_helpers.S
+++ b/plat/amlogic/common/aarch64/aml_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,7 +16,7 @@
.globl plat_is_my_cpu_primary
.globl plat_my_core_pos
.globl plat_reset_handler
- .globl plat_gxbb_calc_core_pos
+ .globl plat_calc_core_pos
/* -----------------------------------------------------
* unsigned int plat_my_core_pos(void);
@@ -24,17 +24,17 @@
*/
func plat_my_core_pos
mrs x0, mpidr_el1
- b plat_gxbb_calc_core_pos
+ b plat_calc_core_pos
endfunc plat_my_core_pos
/* -----------------------------------------------------
- * unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr);
+ * unsigned int plat_calc_core_pos(u_register_t mpidr);
* -----------------------------------------------------
*/
-func plat_gxbb_calc_core_pos
+func plat_calc_core_pos
and x0, x0, #MPIDR_CPU_MASK
ret
-endfunc plat_gxbb_calc_core_pos
+endfunc plat_calc_core_pos
/* -----------------------------------------------------
* unsigned int plat_is_my_cpu_primary(void);
@@ -43,7 +43,7 @@
func plat_is_my_cpu_primary
mrs x0, mpidr_el1
and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
- cmp x0, #GXBB_PRIMARY_CPU
+ cmp x0, #AML_PRIMARY_CPU
cset w0, eq
ret
endfunc plat_is_my_cpu_primary
@@ -61,9 +61,9 @@
* ---------------------------------------------
*/
func plat_crash_console_init
- mov_imm x0, GXBB_UART0_AO_BASE
- mov_imm x1, GXBB_UART0_AO_CLK_IN_HZ
- mov_imm x2, GXBB_UART_BAUDRATE
+ mov_imm x0, AML_UART0_AO_BASE
+ mov_imm x1, AML_UART0_AO_CLK_IN_HZ
+ mov_imm x2, AML_UART_BAUDRATE
b console_meson_init
endfunc plat_crash_console_init
@@ -73,7 +73,7 @@
* ---------------------------------------------
*/
func plat_crash_console_putc
- mov_imm x1, GXBB_UART0_AO_BASE
+ mov_imm x1, AML_UART0_AO_BASE
b console_meson_core_putc
endfunc plat_crash_console_putc
@@ -84,7 +84,7 @@
* ---------------------------------------------
*/
func plat_crash_console_flush
- mov_imm x0, GXBB_UART0_AO_BASE
+ mov_imm x0, AML_UART0_AO_BASE
b console_meson_core_flush
endfunc plat_crash_console_flush
diff --git a/plat/amlogic/common/aml_efuse.c b/plat/amlogic/common/aml_efuse.c
new file mode 100644
index 0000000..00884eb
--- /dev/null
+++ b/plat/amlogic/common/aml_efuse.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include "aml_private.h"
+
+#define EFUSE_BASE 0x140
+#define EFUSE_SIZE 0xC0
+
+uint64_t aml_efuse_read(void *dst, uint32_t offset, uint32_t size)
+{
+ if ((uint64_t)(offset + size) > (uint64_t)EFUSE_SIZE)
+ return 0;
+
+ return aml_scpi_efuse_read(dst, offset + EFUSE_BASE, size);
+}
+
+uint64_t aml_efuse_user_max(void)
+{
+ return EFUSE_SIZE;
+}
diff --git a/plat/amlogic/common/aml_mhu.c b/plat/amlogic/common/aml_mhu.c
new file mode 100644
index 0000000..001686a
--- /dev/null
+++ b/plat/amlogic/common/aml_mhu.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/bakery_lock.h>
+#include <lib/mmio.h>
+#include <platform_def.h>
+
+static DEFINE_BAKERY_LOCK(mhu_lock);
+
+void aml_mhu_secure_message_start(void)
+{
+ bakery_lock_get(&mhu_lock);
+
+ while (mmio_read_32(AML_HIU_MAILBOX_STAT_3) != 0)
+ ;
+}
+
+void aml_mhu_secure_message_send(uint32_t msg)
+{
+ mmio_write_32(AML_HIU_MAILBOX_SET_3, msg);
+
+ while (mmio_read_32(AML_HIU_MAILBOX_STAT_3) != 0)
+ ;
+}
+
+uint32_t aml_mhu_secure_message_wait(void)
+{
+ uint32_t val;
+
+ do {
+ val = mmio_read_32(AML_HIU_MAILBOX_STAT_0);
+ } while (val == 0);
+
+ return val;
+}
+
+void aml_mhu_secure_message_end(void)
+{
+ mmio_write_32(AML_HIU_MAILBOX_CLR_0, 0xFFFFFFFF);
+
+ bakery_lock_release(&mhu_lock);
+}
+
+void aml_mhu_secure_init(void)
+{
+ bakery_lock_init(&mhu_lock);
+
+ mmio_write_32(AML_HIU_MAILBOX_CLR_3, 0xFFFFFFFF);
+}
diff --git a/plat/amlogic/common/aml_scpi.c b/plat/amlogic/common/aml_scpi.c
new file mode 100644
index 0000000..728bcd0
--- /dev/null
+++ b/plat/amlogic/common/aml_scpi.c
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <crypto/sha_dma.h>
+#include <lib/mmio.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+#include <string.h>
+
+#include "aml_private.h"
+
+#define SIZE_SHIFT 20
+#define SIZE_MASK 0x1FF
+#define SIZE_FWBLK 0x200UL
+
+/*
+ * Note: The Amlogic SCP firmware uses the legacy SCPI protocol.
+ */
+#define SCPI_CMD_SET_CSS_POWER_STATE 0x04
+#define SCPI_CMD_SET_SYS_POWER_STATE 0x08
+
+#define SCPI_CMD_JTAG_SET_STATE 0xC0
+#define SCPI_CMD_EFUSE_READ 0xC2
+
+#define SCPI_CMD_COPY_FW 0xd4
+#define SCPI_CMD_SET_FW_ADDR 0xd3
+#define SCPI_CMD_FW_SIZE 0xd2
+
+static inline uint32_t aml_scpi_cmd(uint32_t command, uint32_t size)
+{
+ return command | (size << SIZE_SHIFT);
+}
+
+static void aml_scpi_secure_message_send(uint32_t command, uint32_t size)
+{
+ aml_mhu_secure_message_send(aml_scpi_cmd(command, size));
+}
+
+static uint32_t aml_scpi_secure_message_receive(void **message_out, size_t *size_out)
+{
+ uint32_t response = aml_mhu_secure_message_wait();
+
+ size_t size = (response >> SIZE_SHIFT) & SIZE_MASK;
+
+ response &= ~(SIZE_MASK << SIZE_SHIFT);
+
+ if (size_out != NULL)
+ *size_out = size;
+
+ if (message_out != NULL)
+ *message_out = (void *)AML_MHU_SECURE_SCP_TO_AP_PAYLOAD;
+
+ return response;
+}
+
+void aml_scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state,
+ uint32_t cluster_state, uint32_t css_state)
+{
+ uint32_t state = (mpidr & 0x0F) | /* CPU ID */
+ ((mpidr & 0xF00) >> 4) | /* Cluster ID */
+ (cpu_state << 8) |
+ (cluster_state << 12) |
+ (css_state << 16);
+
+ aml_mhu_secure_message_start();
+ mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, state);
+ aml_mhu_secure_message_send(aml_scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4));
+ aml_mhu_secure_message_wait();
+ aml_mhu_secure_message_end();
+}
+
+uint32_t aml_scpi_sys_power_state(uint64_t system_state)
+{
+ uint32_t *response;
+ size_t size;
+
+ aml_mhu_secure_message_start();
+ mmio_write_8(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state);
+ aml_mhu_secure_message_send(aml_scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1));
+ aml_scpi_secure_message_receive((void *)&response, &size);
+ aml_mhu_secure_message_end();
+
+ return *response;
+}
+
+void aml_scpi_jtag_set_state(uint32_t state, uint8_t select)
+{
+ assert(state <= AML_JTAG_STATE_OFF);
+
+ if (select > AML_JTAG_A53_EE) {
+ WARN("BL31: Invalid JTAG select (0x%x).\n", select);
+ return;
+ }
+
+ aml_mhu_secure_message_start();
+ mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD,
+ (state << 8) | (uint32_t)select);
+ aml_mhu_secure_message_send(aml_scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4));
+ aml_mhu_secure_message_wait();
+ aml_mhu_secure_message_end();
+}
+
+uint32_t aml_scpi_efuse_read(void *dst, uint32_t base, uint32_t size)
+{
+ uint32_t *response;
+ size_t resp_size;
+
+ if (size > 0x1FC)
+ return 0;
+
+ aml_mhu_secure_message_start();
+ mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, base);
+ mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size);
+ aml_mhu_secure_message_send(aml_scpi_cmd(SCPI_CMD_EFUSE_READ, 8));
+ aml_scpi_secure_message_receive((void *)&response, &resp_size);
+ aml_mhu_secure_message_end();
+
+ /*
+ * response[0] is the size of the response message.
+ * response[1 ... N] are the contents.
+ */
+ if (*response != 0)
+ memcpy(dst, response + 1, *response);
+
+ return *response;
+}
+
+void aml_scpi_unknown_thermal(uint32_t arg0, uint32_t arg1,
+ uint32_t arg2, uint32_t arg3)
+{
+ aml_mhu_secure_message_start();
+ mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0);
+ mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1);
+ mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2);
+ mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3);
+ aml_mhu_secure_message_send(aml_scpi_cmd(0xC3, 16));
+ aml_mhu_secure_message_wait();
+ aml_mhu_secure_message_end();
+}
+
+static inline void aml_scpi_copy_scp_data(uint8_t *data, size_t len)
+{
+ void *dst = (void *)AML_MHU_SECURE_AP_TO_SCP_PAYLOAD;
+ size_t sz;
+
+ mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, len);
+ aml_scpi_secure_message_send(SCPI_CMD_FW_SIZE, len);
+ aml_mhu_secure_message_wait();
+
+ for (sz = 0; sz < len; sz += SIZE_FWBLK) {
+ memcpy(dst, data + sz, MIN(SIZE_FWBLK, len - sz));
+ aml_mhu_secure_message_send(SCPI_CMD_COPY_FW);
+ }
+}
+
+static inline void aml_scpi_set_scp_addr(uint64_t addr, size_t len)
+{
+ volatile uint64_t *dst = (uint64_t *)AML_MHU_SECURE_AP_TO_SCP_PAYLOAD;
+
+ /*
+ * It is ok as AML_MHU_SECURE_AP_TO_SCP_PAYLOAD is mapped as
+ * non cachable
+ */
+ *dst = addr;
+ aml_scpi_secure_message_send(SCPI_CMD_SET_FW_ADDR, sizeof(addr));
+ aml_mhu_secure_message_wait();
+
+ mmio_write_32(AML_MHU_SECURE_AP_TO_SCP_PAYLOAD, len);
+ aml_scpi_secure_message_send(SCPI_CMD_FW_SIZE, len);
+ aml_mhu_secure_message_wait();
+}
+
+static inline void aml_scpi_send_fw_hash(uint8_t hash[], size_t len)
+{
+ void *dst = (void *)AML_MHU_SECURE_AP_TO_SCP_PAYLOAD;
+
+ memcpy(dst, hash, len);
+ aml_mhu_secure_message_send(0xd0);
+ aml_mhu_secure_message_send(0xd1);
+ aml_mhu_secure_message_send(0xd5);
+ aml_mhu_secure_message_end();
+}
+
+/**
+ * Upload a FW to SCP.
+ *
+ * @param addr: firmware data address
+ * @param size: size of firmware
+ * @param send: If set, actually copy the firmware in SCP memory otherwise only
+ * send the firmware address.
+ */
+void aml_scpi_upload_scp_fw(uintptr_t addr, size_t size, int send)
+{
+ struct asd_ctx ctx;
+
+ asd_sha_init(&ctx, ASM_SHA256);
+ asd_sha_update(&ctx, (void *)addr, size);
+ asd_sha_finalize(&ctx);
+
+ aml_mhu_secure_message_start();
+ if (send == 0)
+ aml_scpi_set_scp_addr(addr, size);
+ else
+ aml_scpi_copy_scp_data((void *)addr, size);
+
+ aml_scpi_send_fw_hash(ctx.digest, sizeof(ctx.digest));
+}
diff --git a/plat/amlogic/common/aml_sip_svc.c b/plat/amlogic/common/aml_sip_svc.c
new file mode 100644
index 0000000..8a9b070
--- /dev/null
+++ b/plat/amlogic/common/aml_sip_svc.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+#include <lib/mmio.h>
+#include <platform_def.h>
+#include <stdint.h>
+
+#include "aml_private.h"
+
+/*******************************************************************************
+ * This function is responsible for handling all SiP calls
+ ******************************************************************************/
+static uintptr_t aml_sip_handler(uint32_t smc_fid,
+ u_register_t x1, u_register_t x2,
+ u_register_t x3, u_register_t x4,
+ void *cookie, void *handle,
+ u_register_t flags)
+{
+ switch (smc_fid) {
+
+ case AML_SM_GET_SHARE_MEM_INPUT_BASE:
+ SMC_RET1(handle, AML_SHARE_MEM_INPUT_BASE);
+
+ case AML_SM_GET_SHARE_MEM_OUTPUT_BASE:
+ SMC_RET1(handle, AML_SHARE_MEM_OUTPUT_BASE);
+
+ case AML_SM_EFUSE_READ:
+ {
+ void *dst = (void *)AML_SHARE_MEM_OUTPUT_BASE;
+ uint64_t ret = aml_efuse_read(dst, (uint32_t)x1, x2);
+
+ SMC_RET1(handle, ret);
+ }
+ case AML_SM_EFUSE_USER_MAX:
+ SMC_RET1(handle, aml_efuse_user_max());
+
+ case AML_SM_JTAG_ON:
+ aml_scpi_jtag_set_state(AML_JTAG_STATE_ON, x1);
+ SMC_RET1(handle, 0);
+
+ case AML_SM_JTAG_OFF:
+ aml_scpi_jtag_set_state(AML_JTAG_STATE_OFF, x1);
+ SMC_RET1(handle, 0);
+
+ default:
+ ERROR("BL31: Unhandled SIP SMC: 0x%08x\n", smc_fid);
+ break;
+ }
+
+ SMC_RET1(handle, SMC_UNK);
+}
+
+DECLARE_RT_SVC(
+ aml_sip_handler,
+
+ OEN_SIP_START,
+ OEN_SIP_END,
+ SMC_TYPE_FAST,
+ NULL,
+ aml_sip_handler
+);
diff --git a/plat/meson/gxbb/gxbb_thermal.c b/plat/amlogic/common/aml_thermal.c
similarity index 62%
rename from plat/meson/gxbb/gxbb_thermal.c
rename to plat/amlogic/common/aml_thermal.c
index b6048ee..53ed103 100644
--- a/plat/meson/gxbb/gxbb_thermal.c
+++ b/plat/amlogic/common/aml_thermal.c
@@ -1,27 +1,27 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
-#include "gxbb_private.h"
+#include "aml_private.h"
static int32_t modules_initialized = -1;
/*******************************************************************************
* Unknown commands related to something thermal-related
******************************************************************************/
-void gxbb_thermal_unknown(void)
+void aml_thermal_unknown(void)
{
uint16_t ret;
if (modules_initialized == -1) {
- scpi_efuse_read(&ret, 0, 2);
+ aml_scpi_efuse_read(&ret, 0, 2);
modules_initialized = ret;
}
- scpi_unknown_thermal(10, 2, /* thermal */
- 13, 1); /* thermalver */
+ aml_scpi_unknown_thermal(10, 2, /* thermal */
+ 13, 1); /* thermalver */
}
diff --git a/plat/meson/gxbb/gxbb_topology.c b/plat/amlogic/common/aml_topology.c
similarity index 91%
rename from plat/meson/gxbb/gxbb_topology.c
rename to plat/amlogic/common/aml_topology.c
index eec2d34..0a04c11 100644
--- a/plat/meson/gxbb/gxbb_topology.c
+++ b/plat/amlogic/common/aml_topology.c
@@ -1,16 +1,14 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <arch.h>
+#include <platform_def.h>
#include <stdint.h>
-#include <platform_def.h>
-
-#include <arch.h>
-
-#include "gxbb_private.h"
+#include "aml_private.h"
/* The power domain tree descriptor */
static unsigned char power_domain_tree_desc[] = {
@@ -51,5 +49,5 @@
if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
return -1;
- return plat_gxbb_calc_core_pos(mpidr);
+ return plat_calc_core_pos(mpidr);
}
diff --git a/plat/amlogic/common/include/aml_private.h b/plat/amlogic/common/include/aml_private.h
new file mode 100644
index 0000000..4923745
--- /dev/null
+++ b/plat/amlogic/common/include/aml_private.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AML_PRIVATE_H
+#define AML_PRIVATE_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+/* Utility functions */
+unsigned int plat_calc_core_pos(u_register_t mpidr);
+void aml_console_init(void);
+void aml_setup_page_tables(void);
+
+/* MHU functions */
+void aml_mhu_secure_message_start(void);
+void aml_mhu_secure_message_send(uint32_t msg);
+uint32_t aml_mhu_secure_message_wait(void);
+void aml_mhu_secure_message_end(void);
+void aml_mhu_secure_init(void);
+
+/* SCPI functions */
+void aml_scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state,
+ uint32_t cluster_state, uint32_t css_state);
+uint32_t aml_scpi_sys_power_state(uint64_t system_state);
+void aml_scpi_jtag_set_state(uint32_t state, uint8_t select);
+uint32_t aml_scpi_efuse_read(void *dst, uint32_t base, uint32_t size);
+void aml_scpi_unknown_thermal(uint32_t arg0, uint32_t arg1,
+ uint32_t arg2, uint32_t arg3);
+void aml_scpi_upload_scp_fw(uintptr_t addr, size_t size, int send);
+
+/* Peripherals */
+void aml_thermal_unknown(void);
+uint64_t aml_efuse_read(void *dst, uint32_t offset, uint32_t size);
+uint64_t aml_efuse_user_max(void);
+
+#endif /* AML_PRIVATE_H */
diff --git a/plat/meson/gxbb/include/plat_macros.S b/plat/amlogic/common/include/plat_macros.S
similarity index 89%
rename from plat/meson/gxbb/include/plat_macros.S
rename to plat/amlogic/common/include/plat_macros.S
index c721c21..d620fcf 100644
--- a/plat/meson/gxbb/include/plat_macros.S
+++ b/plat/amlogic/common/include/plat_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -33,7 +33,7 @@
/* GICC registers */
- mov_imm x17, GXBB_GICC_BASE
+ mov_imm x17, AML_GICC_BASE
adr x6, gicc_regs
ldr w8, [x17, #GICC_HPPIR]
@@ -43,7 +43,7 @@
/* GICD registers */
- mov_imm x16, GXBB_GICD_BASE
+ mov_imm x16, AML_GICD_BASE
add x7, x16, #GICD_ISPENDR
adr x4, gicd_pend_reg
diff --git a/plat/meson/gxbb/gxbb_bl31_setup.c b/plat/amlogic/gxbb/gxbb_bl31_setup.c
similarity index 93%
rename from plat/meson/gxbb/gxbb_bl31_setup.c
rename to plat/amlogic/gxbb/gxbb_bl31_setup.c
index b867a58..cc7a1c4 100644
--- a/plat/meson/gxbb/gxbb_bl31_setup.c
+++ b/plat/amlogic/gxbb/gxbb_bl31_setup.c
@@ -1,20 +1,18 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
-
-#include <platform_def.h>
-
#include <common/bl_common.h>
#include <common/interrupt_props.h>
#include <drivers/arm/gicv2.h>
#include <lib/xlat_tables/xlat_mmu_helpers.h>
#include <plat/common/platform.h>
+#include <platform_def.h>
-#include "gxbb_private.h"
+#include "aml_private.h"
/*
* Placeholder variables for copying the arguments that have been passed to
@@ -67,13 +65,13 @@
struct gxbb_bl31_param *from_bl2;
/* Initialize the console to provide early debug support */
- gxbb_console_init();
+ aml_console_init();
/*
* In debug builds, we pass a special value in 'arg1' to verify platform
* parameters from BL2 to BL31. In release builds it's not used.
*/
- assert(arg1 == GXBB_BL31_PLAT_PARAM_VAL);
+ assert(arg1 == AML_BL31_PLAT_PARAM_VAL);
/* Check that params passed from BL2 are not NULL. */
from_bl2 = (struct gxbb_bl31_param *) arg0;
@@ -97,7 +95,7 @@
void bl31_plat_arch_setup(void)
{
- gxbb_setup_page_tables();
+ aml_setup_page_tables();
enable_mmu_el3(0);
}
@@ -127,20 +125,20 @@
};
static const gicv2_driver_data_t gxbb_gic_data = {
- .gicd_base = GXBB_GICD_BASE,
- .gicc_base = GXBB_GICC_BASE,
+ .gicd_base = AML_GICD_BASE,
+ .gicc_base = AML_GICC_BASE,
.interrupt_props = gxbb_interrupt_props,
.interrupt_props_num = ARRAY_SIZE(gxbb_interrupt_props),
};
void bl31_platform_setup(void)
{
- mhu_secure_init();
+ aml_mhu_secure_init();
gicv2_driver_init(&gxbb_gic_data);
gicv2_distif_init();
gicv2_pcpu_distif_init();
gicv2_cpuif_enable();
- gxbb_thermal_unknown();
+ aml_thermal_unknown();
}
diff --git a/plat/meson/gxbb/gxbb_common.c b/plat/amlogic/gxbb/gxbb_common.c
similarity index 72%
rename from plat/meson/gxbb/gxbb_common.c
rename to plat/amlogic/gxbb/gxbb_common.c
index 0ca15e8..e98748e 100644
--- a/plat/meson/gxbb/gxbb_common.c
+++ b/plat/amlogic/gxbb/gxbb_common.c
@@ -1,51 +1,49 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
-#include <stdint.h>
-
-#include <platform_def.h>
-
#include <bl31/interrupt_mgmt.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <common/ep_info.h>
-#include <drivers/meson/meson_console.h>
+#include <drivers/amlogic/meson_console.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <platform_def.h>
+#include <stdint.h>
/*******************************************************************************
* Platform memory map regions
******************************************************************************/
-#define MAP_NSDRAM0 MAP_REGION_FLAT(GXBB_NSDRAM0_BASE, \
- GXBB_NSDRAM0_SIZE, \
+#define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \
+ AML_NSDRAM0_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
-#define MAP_NSDRAM1 MAP_REGION_FLAT(GXBB_NSDRAM1_BASE, \
- GXBB_NSDRAM1_SIZE, \
+#define MAP_NSDRAM1 MAP_REGION_FLAT(AML_NSDRAM1_BASE, \
+ AML_NSDRAM1_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
-#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(GXBB_SEC_DEVICE0_BASE, \
- GXBB_SEC_DEVICE0_SIZE, \
+#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \
+ AML_SEC_DEVICE0_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
-#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(GXBB_SEC_DEVICE1_BASE, \
- GXBB_SEC_DEVICE1_SIZE, \
+#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \
+ AML_SEC_DEVICE1_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
-#define MAP_TZRAM MAP_REGION_FLAT(GXBB_TZRAM_BASE, \
- GXBB_TZRAM_SIZE, \
+#define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \
+ AML_TZRAM_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
-#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(GXBB_SEC_DEVICE2_BASE, \
- GXBB_SEC_DEVICE2_SIZE, \
+#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \
+ AML_SEC_DEVICE2_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
-#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(GXBB_SEC_DEVICE3_BASE, \
- GXBB_SEC_DEVICE3_SIZE, \
+#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE, \
+ AML_SEC_DEVICE3_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
static const mmap_region_t gxbb_mmap[] = {
@@ -81,7 +79,7 @@
/*******************************************************************************
* Function that sets up the translation tables.
******************************************************************************/
-void gxbb_setup_page_tables(void)
+void aml_setup_page_tables(void)
{
#if IMAGE_BL31
const mmap_region_t gxbb_bl_mmap[] = {
@@ -107,11 +105,11 @@
******************************************************************************/
static console_meson_t gxbb_console;
-void gxbb_console_init(void)
+void aml_console_init(void)
{
- int rc = console_meson_register(GXBB_UART0_AO_BASE,
- GXBB_UART0_AO_CLK_IN_HZ,
- GXBB_UART_BAUDRATE,
+ int rc = console_meson_register(AML_UART0_AO_BASE,
+ AML_UART0_AO_CLK_IN_HZ,
+ AML_UART_BAUDRATE,
&gxbb_console);
if (rc == 0) {
/*
@@ -133,13 +131,13 @@
{
uint32_t val;
- val = mmio_read_32(GXBB_SYS_CPU_CFG7);
+ val = mmio_read_32(AML_SYS_CPU_CFG7);
val &= 0xFDFFFFFF;
- mmio_write_32(GXBB_SYS_CPU_CFG7, val);
+ mmio_write_32(AML_SYS_CPU_CFG7, val);
- val = mmio_read_32(GXBB_AO_TIMESTAMP_CNTL);
+ val = mmio_read_32(AML_AO_TIMESTAMP_CNTL);
val &= 0xFFFFFE00;
- mmio_write_32(GXBB_AO_TIMESTAMP_CNTL, val);
+ mmio_write_32(AML_AO_TIMESTAMP_CNTL, val);
- return GXBB_OSC24M_CLK_IN_HZ;
+ return AML_OSC24M_CLK_IN_HZ;
}
diff --git a/plat/amlogic/gxbb/gxbb_def.h b/plat/amlogic/gxbb/gxbb_def.h
new file mode 100644
index 0000000..2f6d1d2
--- /dev/null
+++ b/plat/amlogic/gxbb/gxbb_def.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef GXBB_DEF_H
+#define GXBB_DEF_H
+
+#include <lib/utils_def.h>
+
+/*******************************************************************************
+ * System oscillator
+ ******************************************************************************/
+#define AML_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */
+
+/*******************************************************************************
+ * Memory regions
+ ******************************************************************************/
+#define AML_NSDRAM0_BASE UL(0x01000000)
+#define AML_NSDRAM0_SIZE UL(0x0F000000)
+
+#define AML_NSDRAM1_BASE UL(0x10000000)
+#define AML_NSDRAM1_SIZE UL(0x00100000)
+
+#define BL31_BASE UL(0x10100000)
+#define BL31_SIZE UL(0x000C0000)
+#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
+
+/* Shared memory used for SMC services */
+#define AML_SHARE_MEM_INPUT_BASE UL(0x100FE000)
+#define AML_SHARE_MEM_OUTPUT_BASE UL(0x100FF000)
+
+#define AML_SEC_DEVICE0_BASE UL(0xC0000000)
+#define AML_SEC_DEVICE0_SIZE UL(0x09000000)
+
+#define AML_SEC_DEVICE1_BASE UL(0xD0040000)
+#define AML_SEC_DEVICE1_SIZE UL(0x00008000)
+
+#define AML_TZRAM_BASE UL(0xD9000000)
+#define AML_TZRAM_SIZE UL(0x00014000)
+/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */
+
+/* Mailboxes */
+#define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800)
+#define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00)
+#define AML_PSCI_MAILBOX_BASE UL(0xD9013F00)
+
+#define AML_TZROM_BASE UL(0xD9040000)
+#define AML_TZROM_SIZE UL(0x00010000)
+
+#define AML_SEC_DEVICE2_BASE UL(0xDA000000)
+#define AML_SEC_DEVICE2_SIZE UL(0x00200000)
+
+#define AML_SEC_DEVICE3_BASE UL(0xDA800000)
+#define AML_SEC_DEVICE3_SIZE UL(0x00200000)
+
+/*******************************************************************************
+ * GIC-400 and interrupt handling related constants
+ ******************************************************************************/
+#define AML_GICD_BASE UL(0xC4301000)
+#define AML_GICC_BASE UL(0xC4302000)
+
+#define IRQ_SEC_PHY_TIMER 29
+
+#define IRQ_SEC_SGI_0 8
+#define IRQ_SEC_SGI_1 9
+#define IRQ_SEC_SGI_2 10
+#define IRQ_SEC_SGI_3 11
+#define IRQ_SEC_SGI_4 12
+#define IRQ_SEC_SGI_5 13
+#define IRQ_SEC_SGI_6 14
+#define IRQ_SEC_SGI_7 15
+
+/*******************************************************************************
+ * UART definitions
+ ******************************************************************************/
+#define AML_UART0_AO_BASE UL(0xC81004C0)
+#define AML_UART0_AO_CLK_IN_HZ AML_OSC24M_CLK_IN_HZ
+#define AML_UART_BAUDRATE U(115200)
+
+/*******************************************************************************
+ * Memory-mapped I/O Registers
+ ******************************************************************************/
+#define AML_AO_TIMESTAMP_CNTL UL(0xC81000B4)
+
+#define AML_SYS_CPU_CFG7 UL(0xC8834664)
+
+#define AML_AO_RTI_STATUS_REG3 UL(0xDA10001C)
+
+#define AML_HIU_MAILBOX_SET_0 UL(0xDA83C404)
+#define AML_HIU_MAILBOX_STAT_0 UL(0xDA83C408)
+#define AML_HIU_MAILBOX_CLR_0 UL(0xDA83C40C)
+#define AML_HIU_MAILBOX_SET_3 UL(0xDA83C428)
+#define AML_HIU_MAILBOX_STAT_3 UL(0xDA83C42C)
+#define AML_HIU_MAILBOX_CLR_3 UL(0xDA83C430)
+
+/*******************************************************************************
+ * System Monitor Call IDs and arguments
+ ******************************************************************************/
+#define AML_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020)
+#define AML_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021)
+
+#define AML_SM_EFUSE_READ U(0x82000030)
+#define AML_SM_EFUSE_USER_MAX U(0x82000033)
+
+#define AML_SM_JTAG_ON U(0x82000040)
+#define AML_SM_JTAG_OFF U(0x82000041)
+
+#define AML_JTAG_STATE_ON U(0)
+#define AML_JTAG_STATE_OFF U(1)
+
+#define AML_JTAG_M3_AO U(0)
+#define AML_JTAG_M3_EE U(1)
+#define AML_JTAG_A53_AO U(2)
+#define AML_JTAG_A53_EE U(3)
+
+#endif /* GXBB_DEF_H */
diff --git a/plat/meson/gxbb/gxbb_pm.c b/plat/amlogic/gxbb/gxbb_pm.c
similarity index 76%
rename from plat/meson/gxbb/gxbb_pm.c
rename to plat/amlogic/gxbb/gxbb_pm.c
index 59b9436..48bff7b 100644
--- a/plat/meson/gxbb/gxbb_pm.c
+++ b/plat/amlogic/gxbb/gxbb_pm.c
@@ -1,23 +1,21 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <assert.h>
-#include <errno.h>
-
-#include <platform_def.h>
-
#include <arch_helpers.h>
+#include <assert.h>
#include <common/debug.h>
#include <drivers/arm/gicv2.h>
#include <drivers/console.h>
+#include <errno.h>
#include <lib/mmio.h>
#include <lib/psci/psci.h>
#include <plat/common/platform.h>
+#include <platform_def.h>
-#include "gxbb_private.h"
+#include "aml_private.h"
#define SCPI_POWER_ON 0
#define SCPI_POWER_RETENTION 1
@@ -31,8 +29,8 @@
static void gxbb_program_mailbox(u_register_t mpidr, uint64_t value)
{
- unsigned int core = plat_gxbb_calc_core_pos(mpidr);
- uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4);
+ unsigned int core = plat_calc_core_pos(mpidr);
+ uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4);
mmio_write_64(cpu_mailbox_addr, value);
flush_dcache_range(cpu_mailbox_addr, sizeof(uint64_t));
@@ -42,7 +40,7 @@
{
INFO("BL31: PSCI_SYSTEM_RESET\n");
- uint32_t status = mmio_read_32(GXBB_AO_RTI_STATUS_REG3);
+ uint32_t status = mmio_read_32(AML_AO_RTI_STATUS_REG3);
NOTICE("BL31: Reboot reason: 0x%x\n", status);
@@ -50,9 +48,9 @@
console_flush();
- mmio_write_32(GXBB_AO_RTI_STATUS_REG3, status);
+ mmio_write_32(AML_AO_RTI_STATUS_REG3, status);
- int ret = scpi_sys_power_state(SCPI_SYSTEM_REBOOT);
+ int ret = aml_scpi_sys_power_state(SCPI_SYSTEM_REBOOT);
if (ret != 0) {
ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %u\n", ret);
@@ -69,7 +67,7 @@
{
INFO("BL31: PSCI_SYSTEM_OFF\n");
- unsigned int ret = scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
+ unsigned int ret = aml_scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
if (ret != 0) {
ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %u\n", ret);
@@ -86,10 +84,10 @@
static int32_t gxbb_pwr_domain_on(u_register_t mpidr)
{
- unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+ unsigned int core = plat_calc_core_pos(mpidr);
/* CPU0 can't be turned OFF, emulate it with a WFE loop */
- if (core == GXBB_PRIMARY_CPU) {
+ if (core == AML_PRIMARY_CPU) {
VERBOSE("BL31: Releasing CPU0 from wait loop...\n");
gxbb_cpu0_go = 1;
@@ -103,8 +101,8 @@
}
gxbb_program_mailbox(mpidr, gxbb_sec_entrypoint);
- scpi_set_css_power_state(mpidr,
- SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON);
+ aml_scpi_set_css_power_state(mpidr,
+ SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON);
dmbsy();
sev();
@@ -113,12 +111,12 @@
static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
- unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1());
+ unsigned int core = plat_calc_core_pos(read_mpidr_el1());
assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
PLAT_LOCAL_STATE_OFF);
- if (core == GXBB_PRIMARY_CPU) {
+ if (core == AML_PRIMARY_CPU) {
gxbb_cpu0_go = 0;
flush_dcache_range((uintptr_t)&gxbb_cpu0_go, sizeof(gxbb_cpu0_go));
dsb();
@@ -132,8 +130,8 @@
static void gxbb_pwr_domain_off(const psci_power_state_t *target_state)
{
u_register_t mpidr = read_mpidr_el1();
- unsigned int core = plat_gxbb_calc_core_pos(mpidr);
- uintptr_t addr = GXBB_PSCI_MAILBOX_BASE + 8 + (core << 4);
+ unsigned int core = plat_calc_core_pos(mpidr);
+ uintptr_t addr = AML_PSCI_MAILBOX_BASE + 8 + (core << 4);
mmio_write_32(addr, 0xFFFFFFFF);
flush_dcache_range(addr, sizeof(uint32_t));
@@ -141,20 +139,20 @@
gicv2_cpuif_disable();
/* CPU0 can't be turned OFF, emulate it with a WFE loop */
- if (core == GXBB_PRIMARY_CPU)
+ if (core == AML_PRIMARY_CPU)
return;
- scpi_set_css_power_state(mpidr,
- SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON);
+ aml_scpi_set_css_power_state(mpidr,
+ SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON);
}
static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t
*target_state)
{
- unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1());
+ unsigned int core = plat_calc_core_pos(read_mpidr_el1());
/* CPU0 can't be turned OFF, emulate it with a WFE loop */
- if (core == GXBB_PRIMARY_CPU) {
+ if (core == AML_PRIMARY_CPU) {
VERBOSE("BL31: CPU0 entering wait loop...\n");
while (gxbb_cpu0_go == 0)
diff --git a/plat/meson/gxbb/include/platform_def.h b/plat/amlogic/gxbb/include/platform_def.h
similarity index 91%
rename from plat/meson/gxbb/include/platform_def.h
rename to plat/amlogic/gxbb/include/platform_def.h
index da4aedd..a5cbe78 100644
--- a/plat/meson/gxbb/include/platform_def.h
+++ b/plat/amlogic/gxbb/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,7 +16,7 @@
#define PLATFORM_LINKER_ARCH aarch64
/* Special value used to verify platform parameters from BL2 to BL31 */
-#define GXBB_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978)
+#define AML_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978)
#define PLATFORM_STACK_SIZE UL(0x1000)
@@ -25,7 +25,7 @@
#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
-#define GXBB_PRIMARY_CPU U(0)
+#define AML_PRIMARY_CPU U(0)
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
diff --git a/plat/amlogic/gxbb/platform.mk b/plat/amlogic/gxbb/platform.mk
new file mode 100644
index 0000000..59c4f3d
--- /dev/null
+++ b/plat/amlogic/gxbb/platform.mk
@@ -0,0 +1,74 @@
+#
+# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include lib/xlat_tables_v2/xlat_tables.mk
+
+AML_PLAT := plat/amlogic
+AML_PLAT_SOC := ${AML_PLAT}/${PLAT}
+AML_PLAT_COMMON := ${AML_PLAT}/common
+
+PLAT_INCLUDES := -Iinclude/drivers/amlogic/ \
+ -I${AML_PLAT_SOC}/include \
+ -I${AML_PLAT_COMMON}/include
+
+GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
+ drivers/arm/gic/v2/gicv2_main.c \
+ drivers/arm/gic/v2/gicv2_helpers.c \
+ plat/common/plat_gicv2.c
+
+BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
+ plat/common/plat_psci_common.c \
+ drivers/amlogic/console/aarch64/meson_console.S \
+ ${AML_PLAT_SOC}/gxbb_bl31_setup.c \
+ ${AML_PLAT_SOC}/gxbb_pm.c \
+ ${AML_PLAT_SOC}/gxbb_common.c \
+ ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \
+ ${AML_PLAT_COMMON}/aml_efuse.c \
+ ${AML_PLAT_COMMON}/aml_mhu.c \
+ ${AML_PLAT_COMMON}/aml_scpi.c \
+ ${AML_PLAT_COMMON}/aml_sip_svc.c \
+ ${AML_PLAT_COMMON}/aml_thermal.c \
+ ${AML_PLAT_COMMON}/aml_topology.c \
+ ${XLAT_TABLES_LIB_SRCS} \
+ ${GIC_SOURCES}
+
+# Tune compiler for Cortex-A53
+ifeq ($(notdir $(CC)),armclang)
+ TF_CFLAGS_aarch64 += -mcpu=cortex-a53
+else ifneq ($(findstring clang,$(notdir $(CC))),)
+ TF_CFLAGS_aarch64 += -mcpu=cortex-a53
+else
+ TF_CFLAGS_aarch64 += -mtune=cortex-a53
+endif
+
+# Build config flags
+# ------------------
+
+# Enable all errata workarounds for Cortex-A53
+ERRATA_A53_826319 := 1
+ERRATA_A53_835769 := 1
+ERRATA_A53_836870 := 1
+ERRATA_A53_843419 := 1
+ERRATA_A53_855873 := 1
+
+WORKAROUND_CVE_2017_5715 := 0
+
+# Have different sections for code and rodata
+SEPARATE_CODE_AND_RODATA := 1
+
+# Use Coherent memory
+USE_COHERENT_MEM := 1
+
+# Verify build config
+# -------------------
+
+ifneq (${RESET_TO_BL31}, 0)
+ $(error Error: ${PLAT} needs RESET_TO_BL31=0)
+endif
+
+ifeq (${ARCH},aarch32)
+ $(error Error: AArch32 not supported on ${PLAT})
+endif
diff --git a/plat/meson/gxl/gxl_bl31_setup.c b/plat/amlogic/gxl/gxl_bl31_setup.c
similarity index 86%
rename from plat/meson/gxl/gxl_bl31_setup.c
rename to plat/amlogic/gxl/gxl_bl31_setup.c
index b1da794..f581dd1 100644
--- a/plat/meson/gxl/gxl_bl31_setup.c
+++ b/plat/amlogic/gxl/gxl_bl31_setup.c
@@ -6,14 +6,14 @@
#include <assert.h>
#include <common/bl_common.h>
-#include <drivers/arm/gicv2.h>
#include <common/interrupt_props.h>
-#include <plat/common/platform.h>
-#include <platform_def.h>
+#include <drivers/arm/gicv2.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_mmu_helpers.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
-#include "gxl_private.h"
+#include "aml_private.h"
/*
* Placeholder variables for copying the arguments that have been passed to
@@ -69,7 +69,7 @@
struct gxl_bl31_param *from_bl2;
/* Initialize the console to provide early debug support */
- gxbb_console_init();
+ aml_console_init();
/* Check that params passed from BL2 are not NULL. */
from_bl2 = (struct gxl_bl31_param *) arg0;
@@ -96,22 +96,22 @@
void bl31_plat_arch_setup(void)
{
- gxbb_setup_page_tables();
+ aml_setup_page_tables();
enable_mmu_el3(0);
}
static inline bool gxl_scp_ready(void)
{
- return GXBB_AO_RTI_SCP_IS_READY(mmio_read_32(GXBB_AO_RTI_SCP_STAT));
+ return AML_AO_RTI_SCP_IS_READY(mmio_read_32(AML_AO_RTI_SCP_STAT));
}
static inline void gxl_scp_boot(void)
{
- scpi_upload_scp_fw(bl30_image_info.image_base,
- bl30_image_info.image_size, 0);
- scpi_upload_scp_fw(bl301_image_info.image_base,
- bl301_image_info.image_size, 1);
+ aml_scpi_upload_scp_fw(bl30_image_info.image_base,
+ bl30_image_info.image_size, 0);
+ aml_scpi_upload_scp_fw(bl301_image_info.image_base,
+ bl301_image_info.image_size, 1);
while (!gxl_scp_ready())
;
}
@@ -119,7 +119,7 @@
/*******************************************************************************
* GICv2 driver setup information
******************************************************************************/
-static const interrupt_prop_t gxbb_interrupt_props[] = {
+static const interrupt_prop_t gxl_interrupt_props[] = {
INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
@@ -140,23 +140,23 @@
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
};
-static const gicv2_driver_data_t gxbb_gic_data = {
- .gicd_base = GXBB_GICD_BASE,
- .gicc_base = GXBB_GICC_BASE,
- .interrupt_props = gxbb_interrupt_props,
- .interrupt_props_num = ARRAY_SIZE(gxbb_interrupt_props),
+static const gicv2_driver_data_t gxl_gic_data = {
+ .gicd_base = AML_GICD_BASE,
+ .gicc_base = AML_GICC_BASE,
+ .interrupt_props = gxl_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(gxl_interrupt_props),
};
void bl31_platform_setup(void)
{
- mhu_secure_init();
+ aml_mhu_secure_init();
- gicv2_driver_init(&gxbb_gic_data);
+ gicv2_driver_init(&gxl_gic_data);
gicv2_distif_init();
gicv2_pcpu_distif_init();
gicv2_cpuif_enable();
gxl_scp_boot();
- gxbb_thermal_unknown();
+ aml_thermal_unknown();
}
diff --git a/plat/meson/gxl/gxl_common.c b/plat/amlogic/gxl/gxl_common.c
similarity index 67%
rename from plat/meson/gxl/gxl_common.c
rename to plat/amlogic/gxl/gxl_common.c
index e3bd604..4686885 100644
--- a/plat/meson/gxl/gxl_common.c
+++ b/plat/amlogic/gxl/gxl_common.c
@@ -1,52 +1,52 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
+#include <bl31/interrupt_mgmt.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <common/ep_info.h>
-#include <bl31/interrupt_mgmt.h>
-#include <meson_console.h>
#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <meson_console.h>
#include <platform_def.h>
#include <stdint.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
/*******************************************************************************
* Platform memory map regions
******************************************************************************/
-#define MAP_NSDRAM0 MAP_REGION_FLAT(GXBB_NSDRAM0_BASE, \
- GXBB_NSDRAM0_SIZE, \
+#define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \
+ AML_NSDRAM0_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
-#define MAP_NSDRAM1 MAP_REGION_FLAT(GXBB_NSDRAM1_BASE, \
- GXBB_NSDRAM1_SIZE, \
+#define MAP_NSDRAM1 MAP_REGION_FLAT(AML_NSDRAM1_BASE, \
+ AML_NSDRAM1_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
-#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(GXBB_SEC_DEVICE0_BASE, \
- GXBB_SEC_DEVICE0_SIZE, \
+#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \
+ AML_SEC_DEVICE0_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
-#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(GXBB_SEC_DEVICE1_BASE, \
- GXBB_SEC_DEVICE1_SIZE, \
+#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \
+ AML_SEC_DEVICE1_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
-#define MAP_TZRAM MAP_REGION_FLAT(GXBB_TZRAM_BASE, \
- GXBB_TZRAM_SIZE, \
+#define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \
+ AML_TZRAM_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
-#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(GXBB_SEC_DEVICE2_BASE, \
- GXBB_SEC_DEVICE2_SIZE, \
+#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \
+ AML_SEC_DEVICE2_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
-#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(GXBB_SEC_DEVICE3_BASE, \
- GXBB_SEC_DEVICE3_SIZE, \
+#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE, \
+ AML_SEC_DEVICE3_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
-static const mmap_region_t gxbb_mmap[] = {
+static const mmap_region_t gxl_mmap[] = {
MAP_NSDRAM0,
MAP_NSDRAM1,
MAP_SEC_DEVICE0,
@@ -79,10 +79,10 @@
/*******************************************************************************
* Function that sets up the translation tables.
******************************************************************************/
-void gxbb_setup_page_tables(void)
+void aml_setup_page_tables(void)
{
#if IMAGE_BL31
- const mmap_region_t gxbb_bl_mmap[] = {
+ const mmap_region_t gxl_bl_mmap[] = {
MAP_BL31,
MAP_BL_CODE,
MAP_BL_RO_DATA,
@@ -93,9 +93,9 @@
};
#endif
- mmap_add(gxbb_bl_mmap);
+ mmap_add(gxl_bl_mmap);
- mmap_add(gxbb_mmap);
+ mmap_add(gxl_mmap);
init_xlat_tables();
}
@@ -103,14 +103,14 @@
/*******************************************************************************
* Function that sets up the console
******************************************************************************/
-static console_meson_t gxbb_console;
+static console_meson_t gxl_console;
-void gxbb_console_init(void)
+void aml_console_init(void)
{
- int rc = console_meson_register(GXBB_UART0_AO_BASE,
- GXBB_UART0_AO_CLK_IN_HZ,
- GXBB_UART_BAUDRATE,
- &gxbb_console);
+ int rc = console_meson_register(AML_UART0_AO_BASE,
+ AML_UART0_AO_CLK_IN_HZ,
+ AML_UART_BAUDRATE,
+ &gxl_console);
if (rc == 0) {
/*
* The crash console doesn't use the multi console API, it uses
@@ -120,7 +120,7 @@
panic();
}
- console_set_scope(&gxbb_console.console,
+ console_set_scope(&gxl_console.console,
CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME);
}
@@ -131,13 +131,13 @@
{
uint32_t val;
- val = mmio_read_32(GXBB_SYS_CPU_CFG7);
+ val = mmio_read_32(AML_SYS_CPU_CFG7);
val &= 0xFDFFFFFF;
- mmio_write_32(GXBB_SYS_CPU_CFG7, val);
+ mmio_write_32(AML_SYS_CPU_CFG7, val);
- val = mmio_read_32(GXBB_AO_TIMESTAMP_CNTL);
+ val = mmio_read_32(AML_AO_TIMESTAMP_CNTL);
val &= 0xFFFFFE00;
- mmio_write_32(GXBB_AO_TIMESTAMP_CNTL, val);
+ mmio_write_32(AML_AO_TIMESTAMP_CNTL, val);
- return GXBB_OSC24M_CLK_IN_HZ;
+ return AML_OSC24M_CLK_IN_HZ;
}
diff --git a/plat/amlogic/gxl/gxl_def.h b/plat/amlogic/gxl/gxl_def.h
new file mode 100644
index 0000000..6f49ed2
--- /dev/null
+++ b/plat/amlogic/gxl/gxl_def.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef GXL_DEF_H
+#define GXL_DEF_H
+
+#include <lib/utils_def.h>
+
+/*******************************************************************************
+ * System oscillator
+ ******************************************************************************/
+#define AML_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */
+
+/*******************************************************************************
+ * Memory regions
+ ******************************************************************************/
+#define AML_NSDRAM0_BASE UL(0x01000000)
+#define AML_NSDRAM0_SIZE UL(0x0F000000)
+
+#define AML_NSDRAM1_BASE UL(0x10000000)
+#define AML_NSDRAM1_SIZE UL(0x00100000)
+
+#define BL31_BASE UL(0x05100000)
+#define BL31_SIZE UL(0x000C0000)
+#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
+
+/* Shared memory used for SMC services */
+#define AML_SHARE_MEM_INPUT_BASE UL(0x050FE000)
+#define AML_SHARE_MEM_OUTPUT_BASE UL(0x050FF000)
+
+#define AML_SEC_DEVICE0_BASE UL(0xC0000000)
+#define AML_SEC_DEVICE0_SIZE UL(0x09000000)
+
+#define AML_SEC_DEVICE1_BASE UL(0xD0040000)
+#define AML_SEC_DEVICE1_SIZE UL(0x00008000)
+
+#define AML_TZRAM_BASE UL(0xD9000000)
+#define AML_TZRAM_SIZE UL(0x00014000)
+/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */
+
+/* Mailboxes */
+#define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800)
+#define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00)
+#define AML_PSCI_MAILBOX_BASE UL(0xD9013F00)
+
+// * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3)
+// * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) *
+// * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) *
+
+#define AML_TZROM_BASE UL(0xD9040000)
+#define AML_TZROM_SIZE UL(0x00010000)
+
+#define AML_SEC_DEVICE2_BASE UL(0xDA000000)
+#define AML_SEC_DEVICE2_SIZE UL(0x00200000)
+
+#define AML_SEC_DEVICE3_BASE UL(0xDA800000)
+#define AML_SEC_DEVICE3_SIZE UL(0x00200000)
+
+/*******************************************************************************
+ * GIC-400 and interrupt handling related constants
+ ******************************************************************************/
+#define AML_GICD_BASE UL(0xC4301000)
+#define AML_GICC_BASE UL(0xC4302000)
+
+#define IRQ_SEC_PHY_TIMER 29
+
+#define IRQ_SEC_SGI_0 8
+#define IRQ_SEC_SGI_1 9
+#define IRQ_SEC_SGI_2 10
+#define IRQ_SEC_SGI_3 11
+#define IRQ_SEC_SGI_4 12
+#define IRQ_SEC_SGI_5 13
+#define IRQ_SEC_SGI_6 14
+#define IRQ_SEC_SGI_7 15
+
+/*******************************************************************************
+ * UART definitions
+ ******************************************************************************/
+#define AML_UART0_AO_BASE UL(0xC81004C0)
+#define AML_UART0_AO_CLK_IN_HZ AML_OSC24M_CLK_IN_HZ
+#define AML_UART_BAUDRATE U(115200)
+
+/*******************************************************************************
+ * Memory-mapped I/O Registers
+ ******************************************************************************/
+#define AML_AO_TIMESTAMP_CNTL UL(0xC81000B4)
+
+#define AML_SYS_CPU_CFG7 UL(0xC8834664)
+
+#define AML_AO_RTI_STATUS_REG3 UL(0xDA10001C)
+#define AML_AO_RTI_SCP_STAT UL(0xDA10023C)
+#define AML_AO_RTI_SCP_READY_OFF U(0x14)
+#define AML_A0_RTI_SCP_READY_MASK U(3)
+#define AML_AO_RTI_SCP_IS_READY(v) \
+ ((((v) >> AML_AO_RTI_SCP_READY_OFF) & \
+ AML_A0_RTI_SCP_READY_MASK) == AML_A0_RTI_SCP_READY_MASK)
+
+#define AML_HIU_MAILBOX_SET_0 UL(0xDA83C404)
+#define AML_HIU_MAILBOX_STAT_0 UL(0xDA83C408)
+#define AML_HIU_MAILBOX_CLR_0 UL(0xDA83C40C)
+#define AML_HIU_MAILBOX_SET_3 UL(0xDA83C428)
+#define AML_HIU_MAILBOX_STAT_3 UL(0xDA83C42C)
+#define AML_HIU_MAILBOX_CLR_3 UL(0xDA83C430)
+
+/*******************************************************************************
+ * System Monitor Call IDs and arguments
+ ******************************************************************************/
+#define AML_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020)
+#define AML_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021)
+
+#define AML_SM_EFUSE_READ U(0x82000030)
+#define AML_SM_EFUSE_USER_MAX U(0x82000033)
+
+#define AML_SM_JTAG_ON U(0x82000040)
+#define AML_SM_JTAG_OFF U(0x82000041)
+
+#define AML_JTAG_STATE_ON U(0)
+#define AML_JTAG_STATE_OFF U(1)
+
+#define AML_JTAG_M3_AO U(0)
+#define AML_JTAG_M3_EE U(1)
+#define AML_JTAG_A53_AO U(2)
+#define AML_JTAG_A53_EE U(3)
+
+#endif /* GXL_DEF_H */
diff --git a/plat/amlogic/gxl/gxl_pm.c b/plat/amlogic/gxl/gxl_pm.c
new file mode 100644
index 0000000..433140b
--- /dev/null
+++ b/plat/amlogic/gxl/gxl_pm.c
@@ -0,0 +1,214 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <assert.h>
+#include <common/debug.h>
+#include <drivers/arm/gicv2.h>
+#include <drivers/console.h>
+#include <errno.h>
+#include <lib/mmio.h>
+#include <lib/psci/psci.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+#include "aml_private.h"
+
+#define SCPI_POWER_ON 0
+#define SCPI_POWER_RETENTION 1
+#define SCPI_POWER_OFF 3
+
+#define SCPI_SYSTEM_SHUTDOWN 0
+#define SCPI_SYSTEM_REBOOT 1
+
+static uintptr_t gxl_sec_entrypoint;
+static volatile uint32_t gxl_cpu0_go;
+
+static void gxl_pm_set_reset_addr(u_register_t mpidr, uint64_t value)
+{
+ unsigned int core = plat_calc_core_pos(mpidr);
+ uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4);
+
+ mmio_write_64(cpu_mailbox_addr, value);
+}
+
+static void gxl_pm_reset(u_register_t mpidr)
+{
+ unsigned int core = plat_calc_core_pos(mpidr);
+ uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4) + 8;
+
+ mmio_write_32(cpu_mailbox_addr, 0);
+}
+
+static void __dead2 gxl_system_reset(void)
+{
+ INFO("BL31: PSCI_SYSTEM_RESET\n");
+
+ u_register_t mpidr = read_mpidr_el1();
+ uint32_t status = mmio_read_32(AML_AO_RTI_STATUS_REG3);
+ int ret;
+
+ NOTICE("BL31: Reboot reason: 0x%x\n", status);
+
+ status &= 0xFFFF0FF0;
+
+ console_flush();
+
+ mmio_write_32(AML_AO_RTI_STATUS_REG3, status);
+
+ ret = aml_scpi_sys_power_state(SCPI_SYSTEM_REBOOT);
+
+ if (ret != 0) {
+ ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %i\n", ret);
+ panic();
+ }
+
+ gxl_pm_reset(mpidr);
+
+ wfi();
+
+ ERROR("BL31: PSCI_SYSTEM_RESET: Operation not handled\n");
+ panic();
+}
+
+static void __dead2 gxl_system_off(void)
+{
+ INFO("BL31: PSCI_SYSTEM_OFF\n");
+
+ u_register_t mpidr = read_mpidr_el1();
+ int ret;
+
+ ret = aml_scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
+
+ if (ret != 0) {
+ ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %i\n", ret);
+ panic();
+ }
+
+ gxl_pm_set_reset_addr(mpidr, 0);
+ gxl_pm_reset(mpidr);
+
+ wfi();
+
+ ERROR("BL31: PSCI_SYSTEM_OFF: Operation not handled\n");
+ panic();
+}
+
+static int32_t gxl_pwr_domain_on(u_register_t mpidr)
+{
+ unsigned int core = plat_calc_core_pos(mpidr);
+
+ /* CPU0 can't be turned OFF, emulate it with a WFE loop */
+ if (core == AML_PRIMARY_CPU) {
+ VERBOSE("BL31: Releasing CPU0 from wait loop...\n");
+
+ gxl_cpu0_go = 1;
+ flush_dcache_range((uintptr_t)&gxl_cpu0_go,
+ sizeof(gxl_cpu0_go));
+ dsb();
+ isb();
+
+ sev();
+
+ return PSCI_E_SUCCESS;
+ }
+
+ gxl_pm_set_reset_addr(mpidr, gxl_sec_entrypoint);
+ aml_scpi_set_css_power_state(mpidr,
+ SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON);
+ dmbsy();
+ sev();
+
+ return PSCI_E_SUCCESS;
+}
+
+static void gxl_pwr_domain_on_finish(const psci_power_state_t *target_state)
+{
+ unsigned int core = plat_calc_core_pos(read_mpidr_el1());
+
+ assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
+ PLAT_LOCAL_STATE_OFF);
+
+ if (core == AML_PRIMARY_CPU) {
+ gxl_cpu0_go = 0;
+ flush_dcache_range((uintptr_t)&gxl_cpu0_go,
+ sizeof(gxl_cpu0_go));
+ dsb();
+ isb();
+ }
+
+ gicv2_pcpu_distif_init();
+ gicv2_cpuif_enable();
+}
+
+static void gxl_pwr_domain_off(const psci_power_state_t *target_state)
+{
+ u_register_t mpidr = read_mpidr_el1();
+ unsigned int core = plat_calc_core_pos(mpidr);
+
+ gicv2_cpuif_disable();
+
+ /* CPU0 can't be turned OFF, emulate it with a WFE loop */
+ if (core == AML_PRIMARY_CPU)
+ return;
+
+ aml_scpi_set_css_power_state(mpidr,
+ SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON);
+}
+
+static void __dead2 gxl_pwr_domain_pwr_down_wfi(const psci_power_state_t
+ *target_state)
+{
+ u_register_t mpidr = read_mpidr_el1();
+ unsigned int core = plat_calc_core_pos(mpidr);
+
+ /* CPU0 can't be turned OFF, emulate it with a WFE loop */
+ if (core == AML_PRIMARY_CPU) {
+ VERBOSE("BL31: CPU0 entering wait loop...\n");
+
+ while (gxl_cpu0_go == 0)
+ wfe();
+
+ VERBOSE("BL31: CPU0 resumed.\n");
+
+ /*
+ * Because setting CPU0's warm reset entrypoint through PSCI
+ * mailbox and/or mmio mapped RVBAR (0xda834650) does not seem
+ * to work, jump to it manually.
+ * In order to avoid an assert, mmu has to be disabled.
+ */
+ disable_mmu_el3();
+ ((void(*)(void))gxl_sec_entrypoint)();
+ }
+
+ dsbsy();
+ gxl_pm_set_reset_addr(mpidr, 0);
+ gxl_pm_reset(mpidr);
+
+ for (;;)
+ wfi();
+}
+
+/*******************************************************************************
+ * Platform handlers and setup function.
+ ******************************************************************************/
+static const plat_psci_ops_t gxl_ops = {
+ .pwr_domain_on = gxl_pwr_domain_on,
+ .pwr_domain_on_finish = gxl_pwr_domain_on_finish,
+ .pwr_domain_off = gxl_pwr_domain_off,
+ .pwr_domain_pwr_down_wfi = gxl_pwr_domain_pwr_down_wfi,
+ .system_off = gxl_system_off,
+ .system_reset = gxl_system_reset,
+};
+
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
+ const plat_psci_ops_t **psci_ops)
+{
+ gxl_sec_entrypoint = sec_entrypoint;
+ *psci_ops = &gxl_ops;
+ gxl_cpu0_go = 0;
+ return 0;
+}
diff --git a/plat/meson/gxl/include/platform_def.h b/plat/amlogic/gxl/include/platform_def.h
similarity index 87%
rename from plat/meson/gxl/include/platform_def.h
rename to plat/amlogic/gxl/include/platform_def.h
index b32ec56..ec64d68 100644
--- a/plat/meson/gxl/include/platform_def.h
+++ b/plat/amlogic/gxl/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,9 +15,6 @@
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
-/* Special value used to verify platform parameters from BL2 to BL31 */
-#define GXBB_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978)
-
#define PLATFORM_STACK_SIZE UL(0x1000)
#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
@@ -25,7 +22,7 @@
#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
-#define GXBB_PRIMARY_CPU U(0)
+#define AML_PRIMARY_CPU U(0)
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
diff --git a/plat/amlogic/gxl/platform.mk b/plat/amlogic/gxl/platform.mk
new file mode 100644
index 0000000..80c991c
--- /dev/null
+++ b/plat/amlogic/gxl/platform.mk
@@ -0,0 +1,90 @@
+#
+# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include lib/xlat_tables_v2/xlat_tables.mk
+
+AML_PLAT := plat/amlogic
+AML_PLAT_SOC := ${AML_PLAT}/${PLAT}
+AML_PLAT_COMMON := ${AML_PLAT}/common
+
+DOIMAGEPATH ?= tools/amlogic
+DOIMAGETOOL ?= ${DOIMAGEPATH}/doimage
+
+PLAT_INCLUDES := -Iinclude/drivers/amlogic/ \
+ -I${AML_PLAT_SOC}/include \
+ -I${AML_PLAT_COMMON}/include
+
+GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
+ drivers/arm/gic/v2/gicv2_main.c \
+ drivers/arm/gic/v2/gicv2_helpers.c \
+ plat/common/plat_gicv2.c
+
+BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
+ plat/common/plat_psci_common.c \
+ drivers/amlogic/console/aarch64/meson_console.S \
+ ${AML_PLAT_SOC}/gxl_bl31_setup.c \
+ ${AML_PLAT_SOC}/gxl_pm.c \
+ ${AML_PLAT_SOC}/gxl_common.c \
+ ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \
+ ${AML_PLAT_COMMON}/aml_efuse.c \
+ ${AML_PLAT_COMMON}/aml_mhu.c \
+ ${AML_PLAT_COMMON}/aml_scpi.c \
+ ${AML_PLAT_COMMON}/aml_sip_svc.c \
+ ${AML_PLAT_COMMON}/aml_thermal.c \
+ ${AML_PLAT_COMMON}/aml_topology.c \
+ drivers/amlogic/crypto/sha_dma.c \
+ ${XLAT_TABLES_LIB_SRCS} \
+ ${GIC_SOURCES}
+
+# Tune compiler for Cortex-A53
+ifeq ($(notdir $(CC)),armclang)
+ TF_CFLAGS_aarch64 += -mcpu=cortex-a53
+else ifneq ($(findstring clang,$(notdir $(CC))),)
+ TF_CFLAGS_aarch64 += -mcpu=cortex-a53
+else
+ TF_CFLAGS_aarch64 += -mtune=cortex-a53
+endif
+
+# Build config flags
+# ------------------
+
+# Enable all errata workarounds for Cortex-A53
+ERRATA_A53_855873 := 1
+ERRATA_A53_819472 := 1
+ERRATA_A53_824069 := 1
+ERRATA_A53_827319 := 1
+
+WORKAROUND_CVE_2017_5715 := 0
+
+# Have different sections for code and rodata
+SEPARATE_CODE_AND_RODATA := 1
+
+# Use Coherent memory
+USE_COHERENT_MEM := 1
+
+# Verify build config
+# -------------------
+
+ifneq (${RESET_TO_BL31}, 0)
+ $(error Error: ${PLAT} needs RESET_TO_BL31=0)
+endif
+
+ifeq (${ARCH},aarch32)
+ $(error Error: AArch32 not supported on ${PLAT})
+endif
+
+all: ${BUILD_PLAT}/bl31.img
+distclean realclean clean: cleanimage
+
+cleanimage:
+ ${Q}${MAKE} -C ${DOIMAGEPATH} clean
+
+${DOIMAGETOOL}:
+ ${Q}${MAKE} -C ${DOIMAGEPATH}
+
+${BUILD_PLAT}/bl31.img: ${BUILD_PLAT}/bl31.bin ${DOIMAGETOOL}
+ ${DOIMAGETOOL} ${BUILD_PLAT}/bl31.bin ${BUILD_PLAT}/bl31.img
+
diff --git a/plat/common/ubsan.c b/plat/common/ubsan.c
new file mode 100644
index 0000000..45b0f7c
--- /dev/null
+++ b/plat/common/ubsan.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2016, Linaro Limited
+ * Copyright (c) 2019, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#include <arch_helpers.h>
+#include <context.h>
+#include <common/debug.h>
+#include <plat/common/platform.h>
+
+struct source_location {
+ const char *file_name;
+ uint32_t line;
+ uint32_t column;
+};
+
+struct type_descriptor {
+ uint16_t type_kind;
+ uint16_t type_info;
+ char type_name[1];
+};
+
+struct type_mismatch_data {
+ struct source_location loc;
+ struct type_descriptor *type;
+ unsigned long alignment;
+ unsigned char type_check_kind;
+};
+
+struct overflow_data {
+ struct source_location loc;
+ struct type_descriptor *type;
+};
+
+struct shift_out_of_bounds_data {
+ struct source_location loc;
+ struct type_descriptor *lhs_type;
+ struct type_descriptor *rhs_type;
+};
+
+struct out_of_bounds_data {
+ struct source_location loc;
+ struct type_descriptor *array_type;
+ struct type_descriptor *index_type;
+};
+
+struct unreachable_data {
+ struct source_location loc;
+};
+
+struct vla_bound_data {
+ struct source_location loc;
+ struct type_descriptor *type;
+};
+
+struct invalid_value_data {
+ struct source_location loc;
+ struct type_descriptor *type;
+};
+
+struct nonnull_arg_data {
+ struct source_location loc;
+};
+
+/*
+ * When compiling with -fsanitize=undefined the compiler expects functions
+ * with the following signatures. The functions are never called directly,
+ * only when undefined behavior is detected in instrumented code.
+ */
+void __ubsan_handle_type_mismatch_abort(struct type_mismatch_data *data,
+ unsigned long ptr);
+void __ubsan_handle_type_mismatch_v1_abort(struct type_mismatch_data *data,
+ unsigned long ptr);
+void __ubsan_handle_add_overflow_abort(struct overflow_data *data,
+ unsigned long lhs, unsigned long rhs);
+void __ubsan_handle_sub_overflow_abort(struct overflow_data *data,
+ unsigned long lhs, unsigned long rhs);
+void __ubsan_handle_mul_overflow_abort(struct overflow_data *data,
+ unsigned long lhs, unsigned long rhs);
+void __ubsan_handle_negate_overflow_abort(struct overflow_data *data,
+ unsigned long old_val);
+void __ubsan_handle_pointer_overflow_abort(struct overflow_data *data,
+ unsigned long old_val);
+void __ubsan_handle_divrem_overflow_abort(struct overflow_data *data,
+ unsigned long lhs, unsigned long rhs);
+void __ubsan_handle_shift_out_of_bounds_abort(struct shift_out_of_bounds_data *data,
+ unsigned long lhs, unsigned long rhs);
+void __ubsan_handle_out_of_bounds_abort(struct out_of_bounds_data *data,
+ unsigned long idx);
+void __ubsan_handle_unreachable_abort(struct unreachable_data *data);
+void __ubsan_handle_missing_return_abort(struct unreachable_data *data);
+void __ubsan_handle_vla_bound_not_positive_abort(struct vla_bound_data *data,
+ unsigned long bound);
+void __ubsan_handle_load_invalid_value_abort(struct invalid_value_data *data,
+ unsigned long val);
+void __ubsan_handle_nonnull_arg_abort(struct nonnull_arg_data *data
+#if __GCC_VERSION < 60000
+ , size_t arg_no
+#endif
+ );
+
+static void print_loc(const char *func, struct source_location *loc)
+{
+ ERROR("Undefined behavior at %s:%d col %d (%s)",
+ loc->file_name, loc->line, loc->column, func);
+}
+
+
+void __ubsan_handle_type_mismatch_abort(struct type_mismatch_data *data,
+ unsigned long ptr __unused)
+{
+ print_loc(__func__, &data->loc);
+ plat_panic_handler();
+}
+
+void __ubsan_handle_type_mismatch_v1_abort(struct type_mismatch_data *data,
+ unsigned long ptr __unused)
+{
+ print_loc(__func__, &data->loc);
+ plat_panic_handler();
+}
+
+void __ubsan_handle_add_overflow_abort(struct overflow_data *data,
+ unsigned long lhs __unused,
+ unsigned long rhs __unused)
+{
+ print_loc(__func__, &data->loc);
+ plat_panic_handler();
+}
+
+void __ubsan_handle_sub_overflow_abort(struct overflow_data *data,
+ unsigned long lhs __unused,
+ unsigned long rhs __unused)
+{
+ print_loc(__func__, &data->loc);
+ plat_panic_handler();
+}
+
+void __ubsan_handle_mul_overflow_abort(struct overflow_data *data,
+ unsigned long lhs __unused,
+ unsigned long rhs __unused)
+{
+ print_loc(__func__, &data->loc);
+ plat_panic_handler();
+}
+
+void __ubsan_handle_negate_overflow_abort(struct overflow_data *data,
+ unsigned long old_val __unused)
+{
+ print_loc(__func__, &data->loc);
+ plat_panic_handler();
+}
+
+void __ubsan_handle_pointer_overflow_abort(struct overflow_data *data,
+ unsigned long old_val __unused)
+{
+ print_loc(__func__, &data->loc);
+ plat_panic_handler();
+}
+
+void __ubsan_handle_divrem_overflow_abort(struct overflow_data *data,
+ unsigned long lhs __unused,
+ unsigned long rhs __unused)
+{
+ print_loc(__func__, &data->loc);
+ plat_panic_handler();
+}
+
+void __ubsan_handle_shift_out_of_bounds_abort(struct shift_out_of_bounds_data *data,
+ unsigned long lhs __unused,
+ unsigned long rhs __unused)
+{
+ print_loc(__func__, &data->loc);
+ plat_panic_handler();
+}
+
+void __ubsan_handle_out_of_bounds_abort(struct out_of_bounds_data *data,
+ unsigned long idx __unused)
+{
+ print_loc(__func__, &data->loc);
+ plat_panic_handler();
+}
+
+void __ubsan_handle_unreachable_abort(struct unreachable_data *data)
+{
+ print_loc(__func__, &data->loc);
+ plat_panic_handler();
+}
+
+void __ubsan_handle_missing_return_abort(struct unreachable_data *data)
+{
+ print_loc(__func__, &data->loc);
+ plat_panic_handler();
+}
+
+void __ubsan_handle_vla_bound_not_positive_abort(struct vla_bound_data *data,
+ unsigned long bound __unused)
+{
+ print_loc(__func__, &data->loc);
+ plat_panic_handler();
+}
+
+void __ubsan_handle_load_invalid_value_abort(struct invalid_value_data *data,
+ unsigned long val __unused)
+{
+ print_loc(__func__, &data->loc);
+ plat_panic_handler();
+}
+
+void __ubsan_handle_nonnull_arg_abort(struct nonnull_arg_data *data
+#if __GCC_VERSION < 60000
+ , size_t arg_no __unused
+#endif
+ )
+{
+ print_loc(__func__, &data->loc);
+ plat_panic_handler();
+}
diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk
index 5d20462..d1ea629 100644
--- a/plat/intel/soc/agilex/platform.mk
+++ b/plat/intel/soc/agilex/platform.mk
@@ -70,5 +70,6 @@
PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1
+BL2_INV_DCACHE := 0
MULTI_CONSOLE_API := 1
USE_COHERENT_MEM := 1
diff --git a/plat/intel/soc/agilex/socfpga_psci.c b/plat/intel/soc/agilex/socfpga_psci.c
index 04d8a0e..12060ef 100644
--- a/plat/intel/soc/agilex/socfpga_psci.c
+++ b/plat/intel/soc/agilex/socfpga_psci.c
@@ -61,18 +61,12 @@
******************************************************************************/
void socfpga_pwr_domain_off(const psci_power_state_t *target_state)
{
- unsigned int cpu_id = plat_my_core_pos();
-
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
- /* TODO: Prevent interrupts from spuriously waking up this cpu */
- /* gicv2_cpuif_disable(); */
-
- /* assert core reset */
- mmio_setbits_32(AGX_RSTMGR_OFST + AGX_RSTMGR_MPUMODRST_OFST,
- 1 << cpu_id);
+ /* Prevent interrupts from spuriously waking up this cpu */
+ gicv2_cpuif_disable();
}
/*******************************************************************************
diff --git a/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init.c b/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init.c
new file mode 100644
index 0000000..e3cfd46
--- /dev/null
+++ b/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <platform_def.h>
+#include <pmic_wrap_init.h>
+
+/* pmic wrap module wait_idle and read polling interval (in microseconds) */
+enum {
+ WAIT_IDLE_POLLING_DELAY_US = 1,
+ READ_POLLING_DELAY_US = 2
+};
+
+static inline uint32_t wait_for_state_idle(uint32_t timeout_us,
+ void *wacs_register,
+ void *wacs_vldclr_register,
+ uint32_t *read_reg)
+{
+ uint32_t reg_rdata;
+ uint32_t retry;
+
+ retry = (timeout_us + WAIT_IDLE_POLLING_DELAY_US) /
+ WAIT_IDLE_POLLING_DELAY_US;
+
+ do {
+ udelay(WAIT_IDLE_POLLING_DELAY_US);
+ reg_rdata = mmio_read_32((uintptr_t)wacs_register);
+ /* if last read command timeout,clear vldclr bit
+ * read command state machine:FSM_REQ-->wfdle-->WFVLDCLR;
+ * write:FSM_REQ-->idle
+ */
+ switch (((reg_rdata >> RDATA_WACS_FSM_SHIFT) &
+ RDATA_WACS_FSM_MASK)) {
+ case WACS_FSM_WFVLDCLR:
+ mmio_write_32((uintptr_t)wacs_vldclr_register, 1);
+ ERROR("WACS_FSM = PMIC_WRAP_WACS_VLDCLR\n");
+ break;
+ case WACS_FSM_WFDLE:
+ ERROR("WACS_FSM = WACS_FSM_WFDLE\n");
+ break;
+ case WACS_FSM_REQ:
+ ERROR("WACS_FSM = WACS_FSM_REQ\n");
+ break;
+ case WACS_FSM_IDLE:
+ goto done;
+ default:
+ break;
+ }
+
+ retry--;
+ } while (retry);
+
+done:
+ if (!retry) /* timeout */
+ return E_PWR_WAIT_IDLE_TIMEOUT;
+
+ if (read_reg)
+ *read_reg = reg_rdata;
+ return 0;
+}
+
+static inline uint32_t wait_for_state_ready(uint32_t timeout_us,
+ void *wacs_register,
+ uint32_t *read_reg)
+{
+ uint32_t reg_rdata;
+ uint32_t retry;
+
+ retry = (timeout_us + READ_POLLING_DELAY_US) / READ_POLLING_DELAY_US;
+
+ do {
+ udelay(READ_POLLING_DELAY_US);
+ reg_rdata = mmio_read_32((uintptr_t)wacs_register);
+
+ if (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK)
+ == WACS_FSM_WFVLDCLR)
+ break;
+
+ retry--;
+ } while (retry);
+
+ if (!retry) { /* timeout */
+ ERROR("timeout when waiting for idle\n");
+ return E_PWR_WAIT_IDLE_TIMEOUT_READ;
+ }
+
+ if (read_reg)
+ *read_reg = reg_rdata;
+ return 0;
+}
+
+static int32_t pwrap_wacs2(uint32_t write,
+ uint32_t adr,
+ uint32_t wdata,
+ uint32_t *rdata,
+ uint32_t init_check)
+{
+ uint32_t reg_rdata = 0;
+ uint32_t wacs_write = 0;
+ uint32_t wacs_adr = 0;
+ uint32_t wacs_cmd = 0;
+ uint32_t return_value = 0;
+
+ if (init_check) {
+ reg_rdata = mmio_read_32((uintptr_t)&mtk_pwrap->wacs2_rdata);
+ /* Prevent someone to used pwrap before pwrap init */
+ if (((reg_rdata >> RDATA_INIT_DONE_SHIFT) &
+ RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) {
+ ERROR("initialization isn't finished\n");
+ return E_PWR_NOT_INIT_DONE;
+ }
+ }
+ reg_rdata = 0;
+ /* Check IDLE in advance */
+ return_value = wait_for_state_idle(TIMEOUT_WAIT_IDLE,
+ &mtk_pwrap->wacs2_rdata,
+ &mtk_pwrap->wacs2_vldclr,
+ 0);
+ if (return_value != 0) {
+ ERROR("wait_for_fsm_idle fail,return_value=%d\n", return_value);
+ goto FAIL;
+ }
+ wacs_write = write << 31;
+ wacs_adr = (adr >> 1) << 16;
+ wacs_cmd = wacs_write | wacs_adr | wdata;
+
+ mmio_write_32((uintptr_t)&mtk_pwrap->wacs2_cmd, wacs_cmd);
+ if (write == 0) {
+ if (rdata == NULL) {
+ ERROR("rdata is a NULL pointer\n");
+ return_value = E_PWR_INVALID_ARG;
+ goto FAIL;
+ }
+ return_value = wait_for_state_ready(TIMEOUT_READ,
+ &mtk_pwrap->wacs2_rdata,
+ ®_rdata);
+ if (return_value != 0) {
+ ERROR("wait_for_fsm_vldclr fail,return_value=%d\n",
+ return_value);
+ goto FAIL;
+ }
+ *rdata = ((reg_rdata >> RDATA_WACS_RDATA_SHIFT)
+ & RDATA_WACS_RDATA_MASK);
+ mmio_write_32((uintptr_t)&mtk_pwrap->wacs2_vldclr, 1);
+ }
+FAIL:
+ return return_value;
+}
+
+/* external API for pmic_wrap user */
+
+int32_t pwrap_read(uint32_t adr, uint32_t *rdata)
+{
+ return pwrap_wacs2(0, adr, 0, rdata, 1);
+}
+
+int32_t pwrap_write(uint32_t adr, uint32_t wdata)
+{
+ return pwrap_wacs2(1, adr, wdata, 0, 1);
+}
diff --git a/plat/mediatek/common/drivers/rtc/rtc_common.c b/plat/mediatek/common/drivers/rtc/rtc_common.c
new file mode 100644
index 0000000..cad12a0
--- /dev/null
+++ b/plat/mediatek/common/drivers/rtc/rtc_common.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+
+#include <pmic_wrap_init.h>
+#include <rtc.h>
+
+/* RTC busy status polling interval and retry count */
+enum {
+ RTC_WRTGR_POLLING_DELAY_MS = 10,
+ RTC_WRTGR_POLLING_CNT = 100
+};
+
+uint16_t RTC_Read(uint32_t addr)
+{
+ uint32_t rdata = 0;
+
+ pwrap_read((uint32_t)addr, &rdata);
+ return (uint16_t)rdata;
+}
+
+void RTC_Write(uint32_t addr, uint16_t data)
+{
+ pwrap_write((uint32_t)addr, (uint32_t)data);
+}
+
+int32_t rtc_busy_wait(void)
+{
+ uint64_t retry = RTC_WRTGR_POLLING_CNT;
+
+ do {
+ mdelay(RTC_WRTGR_POLLING_DELAY_MS);
+ if (!(RTC_Read(RTC_BBPU) & RTC_BBPU_CBUSY))
+ return 1;
+ retry--;
+ } while (retry);
+
+ ERROR("[RTC] rtc cbusy time out!\n");
+ return 0;
+}
+
+int32_t RTC_Write_Trigger(void)
+{
+ RTC_Write(RTC_WRTGR, 1);
+ return rtc_busy_wait();
+}
+
+int32_t Writeif_unlock(void)
+{
+ RTC_Write(RTC_PROT, RTC_PROT_UNLOCK1);
+ if (!RTC_Write_Trigger())
+ return 0;
+ RTC_Write(RTC_PROT, RTC_PROT_UNLOCK2);
+ if (!RTC_Write_Trigger())
+ return 0;
+
+ return 1;
+}
+
diff --git a/plat/mediatek/common/params_setup.c b/plat/mediatek/common/params_setup.c
new file mode 100644
index 0000000..a9df13e
--- /dev/null
+++ b/plat/mediatek/common/params_setup.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/bl_aux_params/bl_aux_params.h>
+#include <common/debug.h>
+#include <plat_params.h>
+#include <string.h>
+
+static struct bl_aux_gpio_info rst_gpio;
+
+struct bl_aux_gpio_info *plat_get_mtk_gpio_reset(void)
+{
+ return &rst_gpio;
+}
+
+static bool mtk_aux_param_handler(struct bl_aux_param_header *param)
+{
+ /* Store platform parameters for later processing if needed. */
+ switch (param->type) {
+ case BL_AUX_PARAM_MTK_RESET_GPIO:
+ rst_gpio = ((struct bl_aux_param_gpio *)param)->gpio;
+ return true;
+ }
+
+ return false;
+}
+
+void params_early_setup(u_register_t plat_param_from_bl2)
+{
+ bl_aux_params_parse(plat_param_from_bl2, mtk_aux_param_handler);
+}
+
diff --git a/plat/mediatek/common/plat_params.h b/plat/mediatek/common/plat_params.h
new file mode 100644
index 0000000..828c3dc
--- /dev/null
+++ b/plat/mediatek/common/plat_params.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_PARAMS_H
+#define PLAT_PARAMS_H
+
+#include <stdint.h>
+
+#include <export/plat/mediatek/common/plat_params_exp.h>
+
+struct bl_aux_gpio_info *plat_get_mtk_gpio_reset(void);
+void params_early_setup(u_register_t plat_param_from_bl2);
+
+#endif
diff --git a/plat/mediatek/mt8173/aarch64/plat_helpers.S b/plat/mediatek/mt8173/aarch64/plat_helpers.S
index 983ebe3..095dfc5 100644
--- a/plat/mediatek/mt8173/aarch64/plat_helpers.S
+++ b/plat/mediatek/mt8173/aarch64/plat_helpers.S
@@ -11,9 +11,6 @@
.globl plat_report_exception
.globl platform_is_primary_cpu
.globl plat_my_core_pos
- .globl plat_crash_console_init
- .globl plat_crash_console_putc
- .globl plat_crash_console_flush
/* -----------------------------------------------------
* void plat_secondary_cold_boot_setup (void);
@@ -50,42 +47,3 @@
add x0, x1, x0, LSR #6
ret
endfunc plat_my_core_pos
-
- /* ---------------------------------------------
- * int plat_crash_console_init(void)
- * Function to initialize the crash console
- * without a C Runtime to print crash report.
- * Clobber list : x0 - x4
- * ---------------------------------------------
- */
-func plat_crash_console_init
- mov_imm x0, MT8173_UART0_BASE
- mov_imm x1, MT8173_UART_CLOCK
- mov_imm x2, MT8173_BAUDRATE
- b console_core_init
-endfunc plat_crash_console_init
-
- /* ---------------------------------------------
- * int plat_crash_console_putc(void)
- * Function to print a character on the crash
- * console without a C Runtime.
- * Clobber list : x1, x2
- * ---------------------------------------------
- */
-func plat_crash_console_putc
- mov_imm x1, MT8173_UART0_BASE
- b console_core_putc
-endfunc plat_crash_console_putc
-
- /* ---------------------------------------------
- * int plat_crash_console_flush(int c)
- * Function to force a write of all buffered
- * data that hasn't been output.
- * Out : return -1 on error else return 0.
- * Clobber list : x0, x1
- * ---------------------------------------------
- */
-func plat_crash_console_flush
- mov_imm x0, MT8173_UART0_BASE
- b console_core_flush
-endfunc plat_crash_console_flush
diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c
index ad81b16..73a479b 100644
--- a/plat/mediatek/mt8173/bl31_plat_setup.c
+++ b/plat/mediatek/mt8173/bl31_plat_setup.c
@@ -9,8 +9,8 @@
#include <common/bl_common.h>
#include <common/debug.h>
#include <common/desc_image_load.h>
-#include <drivers/console.h>
#include <drivers/generic_delay_timer.h>
+#include <drivers/ti/uart/uart_16550.h>
#include <lib/mmio.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/common_def.h>
@@ -100,7 +100,9 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE);
+ static console_16550_t console;
+
+ console_16550_register(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE, &console);
VERBOSE("bl31_setup\n");
diff --git a/plat/mediatek/mt8173/plat_pm.c b/plat/mediatek/mt8173/plat_pm.c
index 1b52470..c8d4599 100644
--- a/plat/mediatek/mt8173/plat_pm.c
+++ b/plat/mediatek/mt8173/plat_pm.c
@@ -11,7 +11,7 @@
#include <common/debug.h>
#include <drivers/arm/cci.h>
#include <drivers/arm/gicv2.h>
-#include <drivers/console.h>
+#include <drivers/ti/uart/uart_16550.h>
#include <lib/bakery_lock.h>
#include <lib/mmio.h>
#include <lib/psci/psci.h>
@@ -543,12 +543,14 @@
void mtk_system_pwr_domain_resume(void)
{
- console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE);
+ console_switch_state(CONSOLE_FLAG_BOOT);
/* Assert system power domain is available on the platform */
assert(PLAT_MAX_PWR_LVL >= MTK_PWR_LVL2);
plat_arm_gic_init();
+
+ console_switch_state(CONSOLE_FLAG_RUNTIME);
}
static const plat_psci_ops_t plat_plat_pm_ops = {
diff --git a/plat/mediatek/mt8173/platform.mk b/plat/mediatek/mt8173/platform.mk
index 24e4ec6..e5eca9f 100644
--- a/plat/mediatek/mt8173/platform.mk
+++ b/plat/mediatek/mt8173/platform.mk
@@ -8,7 +8,6 @@
MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
- -I${MTK_PLAT}/common/drivers/uart/ \
-Iinclude/plat/arm/common/aarch64 \
-I${MTK_PLAT_SOC}/drivers/crypt/ \
-I${MTK_PLAT_SOC}/drivers/mtcmos/ \
@@ -21,21 +20,21 @@
PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
lib/xlat_tables/aarch64/xlat_tables.c \
plat/arm/common/arm_gicv2.c \
- plat/common/plat_gicv2.c
+ plat/common/plat_gicv2.c \
+ plat/common/aarch64/crash_console_helpers.S
BL31_SOURCES += common/desc_image_load.c \
drivers/arm/cci/cci.c \
drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
- drivers/console/aarch64/console.S \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
+ drivers/ti/uart/aarch64/16550_console.S \
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
lib/cpus/aarch64/cortex_a72.S \
- ${MTK_PLAT}/common/drivers/uart/8250_console.S \
${MTK_PLAT}/common/mtk_plat_common.c \
${MTK_PLAT}/common/mtk_sip_svc.c \
${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
@@ -68,3 +67,5 @@
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0
+
+MULTI_CONSOLE_API := 1
diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c
index e623e96..337470a 100644
--- a/plat/mediatek/mt8183/bl31_plat_setup.c
+++ b/plat/mediatek/mt8183/bl31_plat_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,9 +14,12 @@
#include <drivers/generic_delay_timer.h>
#include <mcucfg.h>
#include <mt_gic_v3.h>
+#include <lib/coreboot.h>
#include <lib/mmio.h>
#include <mtk_plat_common.h>
+#include <mtspmc.h>
#include <plat_debug.h>
+#include <plat_params.h>
#include <plat_private.h>
#include <platform_def.h>
#include <scu.h>
@@ -73,7 +76,17 @@
{
static console_16550_t console;
+ params_early_setup(arg1);
+
+#if COREBOOT
+ if (coreboot_serial.type)
+ console_16550_register(coreboot_serial.baseaddr,
+ coreboot_serial.input_hertz,
+ coreboot_serial.baud,
+ &console);
+#else
console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console);
+#endif
NOTICE("MT8183 bl31_setup\n");
@@ -95,6 +108,10 @@
/* Init mcsi SF */
plat_mtk_cci_init_sf();
+
+#if SPMC_MODE == 1
+ spmc_init();
+#endif
}
/*******************************************************************************
diff --git a/plat/mediatek/mt8183/drivers/gpio/mtgpio.c b/plat/mediatek/mt8183/drivers/gpio/mtgpio.c
new file mode 100644
index 0000000..61aaeef
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/gpio/mtgpio.c
@@ -0,0 +1,439 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <gpio/mtgpio.h>
+#include <gpio/mtgpio_cfg.h>
+#include <drivers/gpio.h>
+#include <mcucfg.h>
+#include <lib/mmio.h>
+#include <platform_def.h>
+#include <spm.h>
+#include <stdbool.h>
+
+/******************************************************************************
+ *Macro Definition
+ ******************************************************************************/
+#define GPIO_MODE_BITS 4
+#define MAX_GPIO_MODE_PER_REG 8
+#define MAX_GPIO_REG_BITS 32
+#define DIR_BASE (GPIO_BASE + 0x000)
+#define DOUT_BASE (GPIO_BASE + 0x100)
+#define DIN_BASE (GPIO_BASE + 0x200)
+#define MODE_BASE (GPIO_BASE + 0x300)
+#define SET 0x4
+#define CLR 0x8
+#define PULLEN_ADDR_OFFSET 0x060
+#define PULLSEL_ADDR_OFFSET 0x080
+
+void mt_set_gpio_dir_chip(uint32_t pin, int dir)
+{
+ uint32_t pos, bit;
+
+ assert(pin < MAX_GPIO_PIN);
+ assert(dir < GPIO_DIR_MAX);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ if (dir == GPIO_DIR_IN)
+ mmio_write_32(DIR_BASE + 0x10 * pos + CLR, 1U << bit);
+ else
+ mmio_write_32(DIR_BASE + 0x10 * pos + SET, 1U << bit);
+}
+
+int mt_get_gpio_dir_chip(uint32_t pin)
+{
+ uint32_t pos, bit;
+ uint32_t reg;
+
+ assert(pin < MAX_GPIO_PIN);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ reg = mmio_read_32(DIR_BASE + 0x10 * pos);
+ return (((reg & (1U << bit)) != 0) ? GPIO_DIR_OUT : GPIO_DIR_IN);
+}
+
+void mt_set_gpio_out_chip(uint32_t pin, int output)
+{
+ uint32_t pos, bit;
+
+ assert(pin < MAX_GPIO_PIN);
+ assert(output < GPIO_OUT_MAX);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ if (output == GPIO_OUT_ZERO)
+ mmio_write_32(DOUT_BASE + 0x10 * pos + CLR, 1U << bit);
+ else
+ mmio_write_32(DOUT_BASE + 0x10 * pos + SET, 1U << bit);
+}
+
+int mt_get_gpio_out_chip(uint32_t pin)
+{
+ uint32_t pos, bit;
+ uint32_t reg;
+
+ assert(pin < MAX_GPIO_PIN);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ reg = mmio_read_32(DOUT_BASE + 0x10 * pos);
+ return (((reg & (1U << bit)) != 0) ? 1 : 0);
+}
+
+int mt_get_gpio_in_chip(uint32_t pin)
+{
+ uint32_t pos, bit;
+ uint32_t reg;
+
+ assert(pin < MAX_GPIO_PIN);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ reg = mmio_read_32(DIN_BASE + 0x10 * pos);
+ return (((reg & (1U << bit)) != 0) ? 1 : 0);
+}
+
+void mt_set_gpio_mode_chip(uint32_t pin, int mode)
+{
+ uint32_t pos, bit;
+ uint32_t data;
+ uint32_t mask;
+
+ assert(pin < MAX_GPIO_PIN);
+ assert(mode < GPIO_MODE_MAX);
+
+ mask = (1U << GPIO_MODE_BITS) - 1;
+
+ mode = mode & mask;
+ pos = pin / MAX_GPIO_MODE_PER_REG;
+ bit = (pin % MAX_GPIO_MODE_PER_REG) * GPIO_MODE_BITS;
+
+ data = mmio_read_32(MODE_BASE + 0x10 * pos);
+ data &= (~(mask << bit));
+ data |= (mode << bit);
+ mmio_write_32(MODE_BASE + 0x10 * pos, data);
+}
+
+int mt_get_gpio_mode_chip(uint32_t pin)
+{
+ uint32_t pos, bit;
+ uint32_t data;
+ uint32_t mask;
+
+ assert(pin < MAX_GPIO_PIN);
+
+ mask = (1U << GPIO_MODE_BITS) - 1;
+
+ pos = pin / MAX_GPIO_MODE_PER_REG;
+ bit = (pin % MAX_GPIO_MODE_PER_REG) * GPIO_MODE_BITS;
+
+ data = mmio_read_32(MODE_BASE + 0x10 * pos);
+ return (data >> bit) & mask;
+}
+
+int32_t gpio_get_pull_iocfg(uint32_t pin)
+{
+ switch (pin) {
+ case 0 ... 10:
+ return IOCFG_5_BASE;
+ case 11 ... 12:
+ return IOCFG_0_BASE;
+ case 13 ... 28:
+ return IOCFG_1_BASE;
+ case 43 ... 49:
+ return IOCFG_2_BASE;
+ case 50 ... 60:
+ return IOCFG_3_BASE;
+ case 61 ... 88:
+ return IOCFG_4_BASE;
+ case 89 ... 90:
+ return IOCFG_5_BASE;
+ case 95 ... 106:
+ return IOCFG_5_BASE;
+ case 107 ... 121:
+ return IOCFG_6_BASE;
+ case 134 ... 160:
+ return IOCFG_0_BASE;
+ case 161 ... 166:
+ return IOCFG_1_BASE;
+ case 167 ... 176:
+ return IOCFG_3_BASE;
+ case 177 ... 179:
+ return IOCFG_5_BASE;
+ default:
+ return -1;
+ }
+}
+
+int32_t gpio_get_pupd_iocfg(uint32_t pin)
+{
+ const int32_t offset = 0x0c0;
+
+ switch (pin) {
+ case 29 ... 34:
+ return IOCFG_1_BASE + offset;
+ case 35 ... 42:
+ return IOCFG_2_BASE + offset;
+ case 91 ... 94:
+ return IOCFG_5_BASE + offset;
+ case 122 ... 133:
+ return IOCFG_7_BASE + offset;
+ default:
+ return -1;
+ }
+}
+
+int gpio_get_pupd_offset(uint32_t pin)
+{
+ switch (pin) {
+ case 29 ... 34:
+ return (pin - 29) * 4 % 32;
+ case 35 ... 42:
+ return (pin - 35) * 4 % 32;
+ case 91 ... 94:
+ return (pin - 91) * 4 % 32;
+ case 122 ... 129:
+ return (pin - 122) * 4 % 32;
+ case 130 ... 133:
+ return (pin - 130) * 4 % 32;
+ default:
+ return -1;
+ }
+}
+
+void mt_set_gpio_pull_enable_chip(uint32_t pin, int en)
+{
+ int pullen_addr = gpio_get_pull_iocfg(pin) + PULLEN_ADDR_OFFSET;
+ int pupd_addr = gpio_get_pupd_iocfg(pin);
+ int pupd_offset = gpio_get_pupd_offset(pin);
+
+ assert(pin < MAX_GPIO_PIN);
+
+ assert(!((PULL_offset[pin].offset == (int8_t)-1) &&
+ (pupd_offset == (int8_t)-1)));
+
+ if (en == GPIO_PULL_DISABLE) {
+ if (PULL_offset[pin].offset == (int8_t)-1)
+ mmio_clrbits_32(pupd_addr, 3U << pupd_offset);
+ else
+ mmio_clrbits_32(pullen_addr,
+ 1U << PULL_offset[pin].offset);
+ } else if (en == GPIO_PULL_ENABLE) {
+ if (PULL_offset[pin].offset == (int8_t)-1) {
+ /* For PUPD+R0+R1 Type, mt_set_gpio_pull_enable
+ * does not know
+ * which one between PU and PD shall be enabled.
+ * Use R0 to guarantee at one resistor is set when lk
+ * apply default setting
+ */
+ mmio_setbits_32(pupd_addr, 1U << pupd_offset);
+ mmio_clrbits_32(pupd_addr, 1U << (pupd_offset + 1));
+ } else {
+ /* For PULLEN + PULLSEL Type */
+ mmio_setbits_32(pullen_addr,
+ 1U << PULL_offset[pin].offset);
+ }
+ } else if (en == GPIO_PULL_ENABLE_R0) {
+ assert(!(pupd_offset == (int8_t)-1));
+ mmio_setbits_32(pupd_addr, 1U << pupd_offset);
+ mmio_clrbits_32(pupd_addr, 1U << (pupd_offset + 1));
+ } else if (en == GPIO_PULL_ENABLE_R1) {
+ assert(!(pupd_offset == (int8_t)-1));
+
+ mmio_clrbits_32(pupd_addr, 1U << pupd_offset);
+ mmio_setbits_32(pupd_addr, 1U << (pupd_offset + 1));
+ } else if (en == GPIO_PULL_ENABLE_R0R1) {
+ assert(!(pupd_offset == (int8_t)-1));
+ mmio_setbits_32(pupd_addr, 3U << pupd_offset);
+ }
+}
+
+int mt_get_gpio_pull_enable_chip(uint32_t pin)
+{
+ uint32_t reg;
+
+ int pullen_addr = gpio_get_pull_iocfg(pin) + PULLEN_ADDR_OFFSET;
+ int pupd_addr = gpio_get_pupd_iocfg(pin);
+ int pupd_offset = gpio_get_pupd_offset(pin);
+
+ assert(pin < MAX_GPIO_PIN);
+
+ assert(!((PULL_offset[pin].offset == (int8_t)-1) &&
+ (pupd_offset == (int8_t)-1)));
+
+ if (PULL_offset[pin].offset == (int8_t)-1) {
+ reg = mmio_read_32(pupd_addr);
+ return ((reg & (3U << pupd_offset)) ? 1 : 0);
+ } else if (pupd_offset == (int8_t)-1) {
+ reg = mmio_read_32(pullen_addr);
+ return ((reg & (1U << PULL_offset[pin].offset)) ? 1 : 0);
+ }
+
+ return -ERINVAL;
+}
+
+void mt_set_gpio_pull_select_chip(uint32_t pin, int sel)
+{
+ int pullsel_addr = gpio_get_pull_iocfg(pin) + PULLSEL_ADDR_OFFSET;
+ int pupd_addr = gpio_get_pupd_iocfg(pin);
+ int pupd_offset = gpio_get_pupd_offset(pin);
+
+ assert(pin < MAX_GPIO_PIN);
+
+ assert(!((PULL_offset[pin].offset == (int8_t) -1) &&
+ (pupd_offset == (int8_t)-1)));
+
+ if (sel == GPIO_PULL_NONE) {
+ /* Regard No PULL as PULL disable + pull down */
+ mt_set_gpio_pull_enable_chip(pin, GPIO_PULL_DISABLE);
+ if (PULL_offset[pin].offset == (int8_t)-1)
+ mmio_setbits_32(pupd_addr, 1U << (pupd_offset + 2));
+ else
+ mmio_clrbits_32(pullsel_addr,
+ 1U << PULL_offset[pin].offset);
+ } else if (sel == GPIO_PULL_UP) {
+ mt_set_gpio_pull_enable_chip(pin, GPIO_PULL_ENABLE);
+ if (PULL_offset[pin].offset == (int8_t)-1)
+ mmio_clrbits_32(pupd_addr, 1U << (pupd_offset + 2));
+ else
+ mmio_setbits_32(pullsel_addr,
+ 1U << PULL_offset[pin].offset);
+ } else if (sel == GPIO_PULL_DOWN) {
+ mt_set_gpio_pull_enable_chip(pin, GPIO_PULL_ENABLE);
+ if (PULL_offset[pin].offset == -1)
+ mmio_setbits_32(pupd_addr, 1U << (pupd_offset + 2));
+ else
+ mmio_clrbits_32(pullsel_addr,
+ 1U << PULL_offset[pin].offset);
+ }
+}
+
+/* get pull-up or pull-down, regardless of resistor value */
+int mt_get_gpio_pull_select_chip(uint32_t pin)
+{
+ uint32_t reg;
+
+ int pullen_addr = gpio_get_pull_iocfg(pin) + PULLEN_ADDR_OFFSET;
+ int pullsel_addr = gpio_get_pull_iocfg(pin) + PULLSEL_ADDR_OFFSET;
+ int pupd_addr = gpio_get_pupd_iocfg(pin);
+ int pupd_offset = gpio_get_pupd_offset(pin);
+
+ assert(pin < MAX_GPIO_PIN);
+
+ assert(!((PULL_offset[pin].offset == (int8_t)-1) &&
+ (pupd_offset == (int8_t)-1)));
+
+ if (PULL_offset[pin].offset == (int8_t)-1) {
+ reg = mmio_read_32(pupd_addr);
+ if (reg & (3U << pupd_offset)) {
+ reg = mmio_read_32(pupd_addr);
+ /* Reg value: 0 for PU, 1 for PD -->
+ * reverse return value */
+ return ((reg & (1U << (pupd_offset + 2))) ?
+ GPIO_PULL_DOWN : GPIO_PULL_UP);
+ } else {
+ return GPIO_PULL_NONE;
+ }
+ } else if (pupd_offset == (int8_t)-1) {
+ reg = mmio_read_32(pullen_addr);
+ if ((reg & (1U << PULL_offset[pin].offset))) {
+ reg = mmio_read_32(pullsel_addr);
+ return ((reg & (1U << PULL_offset[pin].offset)) ?
+ GPIO_PULL_UP : GPIO_PULL_DOWN);
+ } else {
+ return GPIO_PULL_NONE;
+ }
+ }
+
+ return -ERINVAL;
+}
+
+void mt_set_gpio_dir(int gpio, int direction)
+{
+ mt_set_gpio_dir_chip((uint32_t)gpio, direction);
+}
+
+int mt_get_gpio_dir(int gpio)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ return mt_get_gpio_dir_chip(pin);
+}
+
+void mt_set_gpio_pull(int gpio, int pull)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ mt_set_gpio_pull_select_chip(pin, pull);
+}
+
+int mt_get_gpio_pull(int gpio)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ return mt_get_gpio_pull_select_chip(pin);
+}
+
+void mt_set_gpio_out(int gpio, int value)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ mt_set_gpio_out_chip(pin, value);
+}
+
+int mt_get_gpio_out(int gpio)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ return mt_get_gpio_out_chip(pin);
+}
+
+int mt_get_gpio_in(int gpio)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ return mt_get_gpio_in_chip(pin);
+}
+
+void mt_set_gpio_mode(int gpio, int mode)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ mt_set_gpio_mode_chip(pin, mode);
+}
+
+int mt_get_gpio_mode(int gpio)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ return mt_get_gpio_mode_chip(pin);
+}
+
+const gpio_ops_t mtgpio_ops = {
+ .get_direction = mt_get_gpio_dir,
+ .set_direction = mt_set_gpio_dir,
+ .get_value = mt_get_gpio_in,
+ .set_value = mt_set_gpio_out,
+ .set_pull = mt_set_gpio_pull,
+ .get_pull = mt_get_gpio_pull,
+};
diff --git a/plat/mediatek/mt8183/drivers/gpio/mtgpio.h b/plat/mediatek/mt8183/drivers/gpio/mtgpio.h
new file mode 100644
index 0000000..9461c54
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/gpio/mtgpio.h
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_GPIO_H
+#define MT_GPIO_H
+
+#include <stdint.h>
+#include <plat/common/common_def.h>
+
+/* Error Code No. */
+#define RSUCCESS 0
+#define ERACCESS 1
+#define ERINVAL 2
+#define ERWRAPPER 3
+#define MAX_GPIO_PIN MT_GPIO_BASE_MAX
+
+/* Enumeration for GPIO pin */
+typedef enum GPIO_PIN {
+ GPIO_UNSUPPORTED = -1,
+
+ GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7,
+ GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14, GPIO15,
+ GPIO16, GPIO17, GPIO18, GPIO19, GPIO20, GPIO21, GPIO22, GPIO23,
+ GPIO24, GPIO25, GPIO26, GPIO27, GPIO28, GPIO29, GPIO30, GPIO31,
+ GPIO32, GPIO33, GPIO34, GPIO35, GPIO36, GPIO37, GPIO38, GPIO39,
+ GPIO40, GPIO41, GPIO42, GPIO43, GPIO44, GPIO45, GPIO46, GPIO47,
+ GPIO48, GPIO49, GPIO50, GPIO51, GPIO52, GPIO53, GPIO54, GPIO55,
+ GPIO56, GPIO57, GPIO58, GPIO59, GPIO60, GPIO61, GPIO62, GPIO63,
+ GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70, GPIO71,
+ GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78, GPIO79,
+ GPIO80, GPIO81, GPIO82, GPIO83, GPIO84, GPIO85, GPIO86, GPIO87,
+ GPIO88, GPIO89, GPIO90, GPIO91, GPIO92, GPIO93, GPIO94, GPIO95,
+ GPIO96, GPIO97, GPIO98, GPIO99, GPIO100, GPIO101, GPIO102, GPIO103,
+ GPIO104, GPIO105, GPIO106, GPIO107, GPIO108, GPIO109, GPIO110, GPIO111,
+ GPIO112, GPIO113, GPIO114, GPIO115, GPIO116, GPIO117, GPIO118, GPIO119,
+ GPIO120, GPIO121, GPIO122, GPIO123, GPIO124, GPIO125, GPIO126, GPIO127,
+ GPIO128, GPIO129, GPIO130, GPIO131, GPIO132, GPIO133, GPIO134, GPIO135,
+ GPIO136, GPIO137, GPIO138, GPIO139, GPIO140, GPIO141, GPIO142, GPIO143,
+ GPIO144, GPIO145, GPIO146, GPIO147, GPIO148, GPIO149, GPIO150, GPIO151,
+ GPIO152, GPIO153, GPIO154, GPIO155, GPIO156, GPIO157, GPIO158, GPIO159,
+ GPIO160, GPIO161, GPIO162, GPIO163, GPIO164, GPIO165, GPIO166, GPIO167,
+ GPIO168, GPIO169, GPIO170, GPIO171, GPIO172, GPIO173, GPIO174, GPIO175,
+ GPIO176, GPIO177, GPIO178, GPIO179,
+ MT_GPIO_BASE_MAX
+} GPIO_PIN;
+
+/* GPIO MODE CONTROL VALUE*/
+typedef enum {
+ GPIO_MODE_UNSUPPORTED = -1,
+ GPIO_MODE_GPIO = 0,
+ GPIO_MODE_00 = 0,
+ GPIO_MODE_01,
+ GPIO_MODE_02,
+ GPIO_MODE_03,
+ GPIO_MODE_04,
+ GPIO_MODE_05,
+ GPIO_MODE_06,
+ GPIO_MODE_07,
+
+ GPIO_MODE_MAX,
+ GPIO_MODE_DEFAULT = GPIO_MODE_00,
+} GPIO_MODE;
+
+/* GPIO DIRECTION */
+typedef enum {
+ GPIO_DIR_UNSUPPORTED = -1,
+ GPIO_DIR_OUT = 0,
+ GPIO_DIR_IN = 1,
+ GPIO_DIR_MAX,
+ GPIO_DIR_DEFAULT = GPIO_DIR_IN,
+} GPIO_DIR;
+
+/* GPIO PULL ENABLE*/
+typedef enum {
+ GPIO_PULL_EN_UNSUPPORTED = -1,
+ GPIO_PULL_DISABLE = 0,
+ GPIO_PULL_ENABLE = 1,
+ GPIO_PULL_ENABLE_R0 = 2,
+ GPIO_PULL_ENABLE_R1 = 3,
+ GPIO_PULL_ENABLE_R0R1 = 4,
+
+ GPIO_PULL_EN_MAX,
+ GPIO_PULL_EN_DEFAULT = GPIO_PULL_ENABLE,
+} GPIO_PULL_EN;
+
+/* GPIO PULL-UP/PULL-DOWN*/
+typedef enum {
+ GPIO_PULL_UNSUPPORTED = -1,
+ GPIO_PULL_NONE = 0,
+ GPIO_PULL_UP = 1,
+ GPIO_PULL_DOWN = 2,
+ GPIO_PULL_MAX,
+ GPIO_PULL_DEFAULT = GPIO_PULL_DOWN
+} GPIO_PULL;
+
+/* GPIO OUTPUT */
+typedef enum {
+ GPIO_OUT_UNSUPPORTED = -1,
+ GPIO_OUT_ZERO = 0,
+ GPIO_OUT_ONE = 1,
+
+ GPIO_OUT_MAX,
+ GPIO_OUT_DEFAULT = GPIO_OUT_ZERO,
+ GPIO_DATA_OUT_DEFAULT = GPIO_OUT_ZERO, /*compatible with DCT*/
+} GPIO_OUT;
+
+/* GPIO INPUT */
+typedef enum {
+ GPIO_IN_UNSUPPORTED = -1,
+ GPIO_IN_ZERO = 0,
+ GPIO_IN_ONE = 1,
+
+ GPIO_IN_MAX,
+} GPIO_IN;
+
+typedef struct {
+ uint32_t val;
+ uint32_t set;
+ uint32_t rst;
+ uint32_t _align1;
+} VAL_REGS;
+
+typedef struct {
+ VAL_REGS dir[6]; /*0x0000 ~ 0x005F: 96 bytes */
+ uint8_t rsv00[160]; /*0x0060 ~ 0x00FF: 160 bytes */
+ VAL_REGS dout[6]; /*0x0100 ~ 0x015F: 96 bytes */
+ uint8_t rsv01[160]; /*0x0160 ~ 0x01FF: 160 bytes */
+ VAL_REGS din[6]; /*0x0200 ~ 0x025F: 96 bytes */
+ uint8_t rsv02[160]; /*0x0260 ~ 0x02FF: 160 bytes */
+ VAL_REGS mode[23]; /*0x0300 ~ 0x046F: 368 bytes */
+} GPIO_REGS;
+
+/* GPIO Driver interface */
+/*direction*/
+void mt_set_gpio_dir(int gpio, int direction);
+int mt_get_gpio_dir(int gpio);
+
+/*pull select*/
+void mt_set_gpio_pull(int gpio, int pull);
+int mt_get_gpio_pull(int gpio);
+
+/*input/output*/
+void mt_set_gpio_out(int gpio, int value);
+int mt_get_gpio_out(int gpio);
+int mt_get_gpio_in(int gpio);
+
+/*mode control*/
+void mt_set_gpio_mode(int gpio, int mode);
+int mt_get_gpio_mode(int gpio);
+
+#endif /* MT_GPIO_H */
diff --git a/plat/mediatek/mt8183/drivers/gpio/mtgpio_cfg.h b/plat/mediatek/mt8183/drivers/gpio/mtgpio_cfg.h
new file mode 100644
index 0000000..4e1fd2b
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/gpio/mtgpio_cfg.h
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_GPIO_CFG_H
+#define MT_GPIO_CFG_H
+
+#include <stdint.h>
+#include <plat/common/common_def.h>
+
+#define IOCFG_0_BASE 0x11F20000
+#define IOCFG_1_BASE 0x11E80000
+#define IOCFG_2_BASE 0x11E70000
+#define IOCFG_3_BASE 0x11E90000
+#define IOCFG_4_BASE 0x11D30000
+#define IOCFG_5_BASE 0x11D20000
+#define IOCFG_6_BASE 0x11C50000
+#define IOCFG_7_BASE 0x11F30000
+
+typedef struct {
+ int8_t offset;
+} PIN_offset;
+
+PIN_offset PULL_offset[] = {
+ /* 0 */ {6},
+ /* 1 */ {7},
+ /* 2 */ {8},
+ /* 3 */ {9},
+ /* 4 */ {11},
+ /* 5 */ {12},
+ /* 6 */ {13},
+ /* 7 */ {14},
+ /* 8 */ {0},
+ /* 9 */ {26},
+ /* 10 */ {27},
+ /* 11 */ {10},
+ /* 12 */ {17},
+ /* 13 */ {6},
+ /* 14 */ {7},
+ /* 15 */ {8},
+ /* 16 */ {9},
+ /* 17 */ {10},
+ /* 18 */ {11},
+ /* 19 */ {12},
+ /* 20 */ {13},
+ /* 21 */ {14},
+ /* 22 */ {15},
+ /* 23 */ {16},
+ /* 24 */ {17},
+ /* 25 */ {18},
+ /* 26 */ {19},
+ /* 27 */ {20},
+ /* 28 */ {21},
+ /* 29 */ {-1},
+ /* 30 */ {-1},
+ /* 31 */ {-1},
+ /* 32 */ {-1},
+ /* 33 */ {-1},
+ /* 34 */ {-1},
+ /* 35 */ {-1},
+ /* 36 */ {-1},
+ /* 37 */ {-1},
+ /* 38 */ {-1},
+ /* 39 */ {-1},
+ /* 40 */ {-1},
+ /* 41 */ {-1},
+ /* 42 */ {-1},
+ /* 43 */ {8},
+ /* 44 */ {9},
+ /* 45 */ {10},
+ /* 46 */ {11},
+ /* 47 */ {12},
+ /* 48 */ {13},
+ /* 49 */ {14},
+ /* 50 */ {0},
+ /* 51 */ {1},
+ /* 52 */ {2},
+ /* 53 */ {3},
+ /* 54 */ {4},
+ /* 55 */ {5},
+ /* 56 */ {6},
+ /* 57 */ {7},
+ /* 58 */ {8},
+ /* 59 */ {9},
+ /* 60 */ {10},
+ /* 61 */ {0},
+ /* 62 */ {1},
+ /* 63 */ {2},
+ /* 64 */ {3},
+ /* 65 */ {4},
+ /* 66 */ {5},
+ /* 67 */ {6},
+ /* 68 */ {7},
+ /* 69 */ {8},
+ /* 70 */ {9},
+ /* 71 */ {10},
+ /* 72 */ {11},
+ /* 73 */ {12},
+ /* 74 */ {13},
+ /* 75 */ {14},
+ /* 76 */ {15},
+ /* 77 */ {16},
+ /* 78 */ {17},
+ /* 79 */ {18},
+ /* 80 */ {19},
+ /* 81 */ {20},
+ /* 82 */ {21},
+ /* 83 */ {22},
+ /* 84 */ {23},
+ /* 85 */ {24},
+ /* 86 */ {25},
+ /* 87 */ {26},
+ /* 88 */ {27},
+ /* 89 */ {24},
+ /* 90 */ {1},
+ /* 91 */ {-1},
+ /* 92 */ {-1},
+ /* 93 */ {-1},
+ /* 94 */ {-1},
+ /* 95 */ {15},
+ /* 96 */ {17},
+ /* 97 */ {18},
+ /* 98 */ {19},
+ /* 99 */ {20},
+ /* 100 */ {21},
+ /* 101 */ {22},
+ /* 102 */ {23},
+ /* 103 */ {28},
+ /* 104 */ {29},
+ /* 105 */ {30},
+ /* 106 */ {31},
+ /* 107 */ {0},
+ /* 108 */ {1},
+ /* 109 */ {2},
+ /* 110 */ {3},
+ /* 111 */ {4},
+ /* 112 */ {5},
+ /* 113 */ {6},
+ /* 114 */ {7},
+ /* 115 */ {8},
+ /* 116 */ {9},
+ /* 117 */ {10},
+ /* 118 */ {11},
+ /* 119 */ {12},
+ /* 120 */ {13},
+ /* 121 */ {14},
+ /* 122 */ {-1},
+ /* 123 */ {-1},
+ /* 124 */ {-1},
+ /* 125 */ {-1},
+ /* 126 */ {-1},
+ /* 127 */ {-1},
+ /* 128 */ {-1},
+ /* 129 */ {-1},
+ /* 130 */ {-1},
+ /* 131 */ {-1},
+ /* 132 */ {-1},
+ /* 133 */ {-1},
+ /* 134 */ {0},
+ /* 135 */ {1},
+ /* 136 */ {2},
+ /* 137 */ {3},
+ /* 138 */ {4},
+ /* 139 */ {5},
+ /* 140 */ {6},
+ /* 141 */ {7},
+ /* 142 */ {8},
+ /* 143 */ {9},
+ /* 144 */ {11},
+ /* 145 */ {12},
+ /* 146 */ {13},
+ /* 147 */ {14},
+ /* 148 */ {15},
+ /* 149 */ {16},
+ /* 150 */ {18},
+ /* 151 */ {19},
+ /* 152 */ {20},
+ /* 153 */ {21},
+ /* 154 */ {22},
+ /* 155 */ {23},
+ /* 156 */ {24},
+ /* 157 */ {25},
+ /* 158 */ {26},
+ /* 159 */ {27},
+ /* 160 */ {28},
+ /* 161 */ {0},
+ /* 162 */ {1},
+ /* 163 */ {2},
+ /* 164 */ {3},
+ /* 165 */ {4},
+ /* 166 */ {5},
+ /* 167 */ {11},
+ /* 168 */ {12},
+ /* 169 */ {13},
+ /* 170 */ {14},
+ /* 171 */ {15},
+ /* 172 */ {16},
+ /* 173 */ {17},
+ /* 174 */ {18},
+ /* 175 */ {19},
+ /* 176 */ {20},
+ /* 177 */ {10},
+ /* 178 */ {16},
+ /* 179 */ {25}
+};
+#endif /* MT_GPIO_CFG_H */
diff --git a/plat/mediatek/mt8183/drivers/pmic/pmic.c b/plat/mediatek/mt8183/drivers/pmic/pmic.c
new file mode 100644
index 0000000..818c149
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/pmic/pmic.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <pmic_wrap_init.h>
+#include <pmic.h>
+
+void wk_pmic_enable_sdn_delay(void)
+{
+ uint32_t con;
+
+ pwrap_write(PMIC_TMA_KEY, 0x9CA7);
+ pwrap_read(PMIC_PSEQ_ELR11, &con);
+ con &= ~PMIC_RG_SDN_DLY_ENB;
+ pwrap_write(PMIC_PSEQ_ELR11, con);
+ pwrap_write(PMIC_TMA_KEY, 0);
+}
+
+void pmic_power_off(void)
+{
+ pwrap_write(PMIC_PWRHOLD, 0x0);
+}
diff --git a/plat/mediatek/mt8183/drivers/pmic/pmic.h b/plat/mediatek/mt8183/drivers/pmic/pmic.h
new file mode 100644
index 0000000..d62c6da
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/pmic/pmic.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_H
+#define PMIC_H
+
+enum {
+ PMIC_TMA_KEY = 0x03a8,
+ PMIC_PWRHOLD = 0x0a08,
+ PMIC_PSEQ_ELR11 = 0x0a62
+};
+
+enum {
+ PMIC_RG_SDN_DLY_ENB = 1U << 10
+};
+
+/* external API */
+void wk_pmic_enable_sdn_delay(void);
+void pmic_power_off(void);
+
+#endif /* PMIC_H */
diff --git a/plat/mediatek/mt8183/drivers/pmic/pmic_wrap_init.h b/plat/mediatek/mt8183/drivers/pmic/pmic_wrap_init.h
new file mode 100644
index 0000000..679c5e4
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/pmic/pmic_wrap_init.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_WRAP_INIT_H
+#define PMIC_WRAP_INIT_H
+
+#include <platform_def.h>
+#include <stdint.h>
+
+/* external API */
+int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
+int32_t pwrap_write(uint32_t adr, uint32_t wdata);
+
+static struct mt8183_pmic_wrap_regs *const mtk_pwrap =
+ (void *)PMIC_WRAP_BASE;
+
+/* timeout setting */
+enum {
+ TIMEOUT_READ = 255, /* us */
+ TIMEOUT_WAIT_IDLE = 255 /* us */
+};
+
+/* PMIC_WRAP registers */
+struct mt8183_pmic_wrap_regs {
+ uint32_t reserved[776];
+ uint32_t wacs2_cmd;
+ uint32_t wacs2_rdata;
+ uint32_t wacs2_vldclr;
+ uint32_t reserved1[4];
+};
+
+enum {
+ RDATA_WACS_RDATA_SHIFT = 0,
+ RDATA_WACS_FSM_SHIFT = 16,
+ RDATA_WACS_REQ_SHIFT = 19,
+ RDATA_SYNC_IDLE_SHIFT,
+ RDATA_INIT_DONE_SHIFT,
+ RDATA_SYS_IDLE_SHIFT,
+};
+
+enum {
+ RDATA_WACS_RDATA_MASK = 0xffff,
+ RDATA_WACS_FSM_MASK = 0x7,
+ RDATA_WACS_REQ_MASK = 0x1,
+ RDATA_SYNC_IDLE_MASK = 0x1,
+ RDATA_INIT_DONE_MASK = 0x1,
+ RDATA_SYS_IDLE_MASK = 0x1,
+};
+
+/* WACS_FSM */
+enum {
+ WACS_FSM_IDLE = 0x00,
+ WACS_FSM_REQ = 0x02,
+ WACS_FSM_WFDLE = 0x04,
+ WACS_FSM_WFVLDCLR = 0x06,
+ WACS_INIT_DONE = 0x01,
+ WACS_SYNC_IDLE = 0x01,
+ WACS_SYNC_BUSY = 0x00
+};
+
+/* error information flag */
+enum {
+ E_PWR_INVALID_ARG = 1,
+ E_PWR_INVALID_RW = 2,
+ E_PWR_INVALID_ADDR = 3,
+ E_PWR_INVALID_WDAT = 4,
+ E_PWR_INVALID_OP_MANUAL = 5,
+ E_PWR_NOT_IDLE_STATE = 6,
+ E_PWR_NOT_INIT_DONE = 7,
+ E_PWR_NOT_INIT_DONE_READ = 8,
+ E_PWR_WAIT_IDLE_TIMEOUT = 9,
+ E_PWR_WAIT_IDLE_TIMEOUT_READ = 10,
+ E_PWR_INIT_SIDLY_FAIL = 11,
+ E_PWR_RESET_TIMEOUT = 12,
+ E_PWR_TIMEOUT = 13,
+ E_PWR_INIT_RESET_SPI = 20,
+ E_PWR_INIT_SIDLY = 21,
+ E_PWR_INIT_REG_CLOCK = 22,
+ E_PWR_INIT_ENABLE_PMIC = 23,
+ E_PWR_INIT_DIO = 24,
+ E_PWR_INIT_CIPHER = 25,
+ E_PWR_INIT_WRITE_TEST = 26,
+ E_PWR_INIT_ENABLE_CRC = 27,
+ E_PWR_INIT_ENABLE_DEWRAP = 28,
+ E_PWR_INIT_ENABLE_EVENT = 29,
+ E_PWR_READ_TEST_FAIL = 30,
+ E_PWR_WRITE_TEST_FAIL = 31,
+ E_PWR_SWITCH_DIO = 32
+};
+
+#endif /* PMIC_WRAP_INIT_H */
diff --git a/plat/mediatek/mt8183/drivers/rtc/rtc.c b/plat/mediatek/mt8183/drivers/rtc/rtc.c
new file mode 100644
index 0000000..a821c1b
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/rtc/rtc.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <rtc.h>
+
+static void RTC_Config_Interface(uint32_t addr, uint16_t data,
+ uint16_t MASK, uint16_t SHIFT)
+{
+ uint16_t pmic_reg = 0;
+
+ pmic_reg = RTC_Read(addr);
+
+ pmic_reg &= ~(MASK << SHIFT);
+ pmic_reg |= (data << SHIFT);
+
+ RTC_Write(addr, pmic_reg);
+}
+
+static void rtc_disable_2sec_reboot(void)
+{
+ uint16_t reboot;
+
+ reboot = (RTC_Read(RTC_AL_SEC) & ~RTC_BBPU_2SEC_EN) &
+ ~RTC_BBPU_AUTO_PDN_SEL;
+ RTC_Write(RTC_AL_SEC, reboot);
+ RTC_Write_Trigger();
+}
+
+static void rtc_xosc_write(uint16_t val, bool reload)
+{
+ uint16_t bbpu;
+
+ RTC_Write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1);
+ rtc_busy_wait();
+ RTC_Write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2);
+ rtc_busy_wait();
+
+ RTC_Write(RTC_OSC32CON, val);
+ rtc_busy_wait();
+
+ if (reload) {
+ bbpu = RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD;
+ RTC_Write(RTC_BBPU, bbpu);
+ RTC_Write_Trigger();
+ }
+}
+
+static void rtc_enable_k_eosc(void)
+{
+ uint16_t osc32;
+ uint16_t rtc_eosc_cali_td = 8; /* eosc cali period time */
+
+ /* Truning on eosc cali mode clock */
+ RTC_Config_Interface(PMIC_RG_TOP_CON, 1,
+ PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK,
+ PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT);
+ RTC_Config_Interface(PMIC_RG_TOP_CON, 1,
+ PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK,
+ PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT);
+ RTC_Config_Interface(PMIC_RG_SCK_TOP_CKPDN_CON0, 0,
+ PMIC_RG_RTC_EOSC32_CK_PDN_MASK,
+ PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT);
+
+ switch (rtc_eosc_cali_td) {
+ case 1:
+ RTC_Config_Interface(PMIC_RG_EOSC_CALI_CON0, 0x3,
+ PMIC_RG_EOSC_CALI_TD_MASK, PMIC_RG_EOSC_CALI_TD_SHIFT);
+ break;
+ case 2:
+ RTC_Config_Interface(PMIC_RG_EOSC_CALI_CON0, 0x4,
+ PMIC_RG_EOSC_CALI_TD_MASK, PMIC_RG_EOSC_CALI_TD_SHIFT);
+ break;
+ case 4:
+ RTC_Config_Interface(PMIC_RG_EOSC_CALI_CON0, 0x5,
+ PMIC_RG_EOSC_CALI_TD_MASK, PMIC_RG_EOSC_CALI_TD_SHIFT);
+ break;
+ case 16:
+ RTC_Config_Interface(PMIC_RG_EOSC_CALI_CON0, 0x7,
+ PMIC_RG_EOSC_CALI_TD_MASK, PMIC_RG_EOSC_CALI_TD_SHIFT);
+ break;
+ default:
+ RTC_Config_Interface(PMIC_RG_EOSC_CALI_CON0, 0x6,
+ PMIC_RG_EOSC_CALI_TD_MASK, PMIC_RG_EOSC_CALI_TD_SHIFT);
+ break;
+ }
+ /* Switch the DCXO from 32k-less mode to RTC mode,
+ * otherwise, EOSC cali will fail
+ */
+ /* RTC mode will have only OFF mode and FPM */
+ RTC_Config_Interface(PMIC_RG_DCXO_CW02, 0, PMIC_RG_XO_EN32K_MAN_MASK,
+ PMIC_RG_XO_EN32K_MAN_SHIFT);
+ RTC_Write(RTC_BBPU,
+ RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
+ RTC_Write_Trigger();
+ /* Enable K EOSC mode for normal power off and then plug out battery */
+ RTC_Write(RTC_AL_YEA, ((RTC_Read(RTC_AL_YEA) | RTC_K_EOSC_RSV_0)
+ & (~RTC_K_EOSC_RSV_1)) | RTC_K_EOSC_RSV_2);
+ RTC_Write_Trigger();
+
+ osc32 = RTC_Read(RTC_OSC32CON);
+ rtc_xosc_write(osc32 | RTC_EMBCK_SRC_SEL, true);
+ INFO("[RTC] RTC_enable_k_eosc\n");
+}
+
+void rtc_power_off_sequence(void)
+{
+ uint16_t bbpu;
+
+ rtc_disable_2sec_reboot();
+ rtc_enable_k_eosc();
+
+ /* clear alarm */
+ bbpu = RTC_BBPU_KEY | RTC_BBPU_CLR | RTC_BBPU_PWREN;
+ if (Writeif_unlock()) {
+ RTC_Write(RTC_BBPU, bbpu);
+
+ RTC_Write(RTC_AL_MASK, RTC_AL_MASK_DOW);
+ RTC_Write_Trigger();
+ mdelay(1);
+
+ bbpu = RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD;
+ RTC_Write(RTC_BBPU, bbpu);
+ RTC_Write_Trigger();
+ INFO("[RTC] BBPU=0x%x, IRQ_EN=0x%x, AL_MSK=0x%x, AL_SEC=0x%x\n",
+ RTC_Read(RTC_BBPU), RTC_Read(RTC_IRQ_EN),
+ RTC_Read(RTC_AL_MASK), RTC_Read(RTC_AL_SEC));
+ }
+}
diff --git a/plat/mediatek/mt8183/drivers/rtc/rtc.h b/plat/mediatek/mt8183/drivers/rtc/rtc.h
new file mode 100644
index 0000000..66686b4
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/rtc/rtc.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RTC_H
+#define RTC_H
+
+/* RTC registers */
+enum {
+ RTC_BBPU = 0x0588,
+ RTC_IRQ_STA = 0x058A,
+ RTC_IRQ_EN = 0x058C,
+ RTC_CII_EN = 0x058E
+};
+
+enum {
+ RTC_AL_SEC = 0x05A0,
+ RTC_AL_MIN = 0x05A2,
+ RTC_AL_HOU = 0x05A4,
+ RTC_AL_DOM = 0x05A6,
+ RTC_AL_DOW = 0x05A8,
+ RTC_AL_MTH = 0x05AA,
+ RTC_AL_YEA = 0x05AC,
+ RTC_AL_MASK = 0x0590
+};
+
+enum {
+ RTC_OSC32CON = 0x05AE,
+ RTC_CON = 0x05C4,
+ RTC_WRTGR = 0x05C2
+};
+
+enum {
+ RTC_PDN1 = 0x05B4,
+ RTC_PDN2 = 0x05B6,
+ RTC_SPAR0 = 0x05B8,
+ RTC_SPAR1 = 0x05BA,
+ RTC_PROT = 0x05BC,
+ RTC_DIFF = 0x05BE,
+ RTC_CALI = 0x05C0
+};
+
+enum {
+ RTC_OSC32CON_UNLOCK1 = 0x1A57,
+ RTC_OSC32CON_UNLOCK2 = 0x2B68
+};
+
+enum {
+ RTC_PROT_UNLOCK1 = 0x586A,
+ RTC_PROT_UNLOCK2 = 0x9136
+};
+
+enum {
+ RTC_BBPU_PWREN = 1U << 0,
+ RTC_BBPU_CLR = 1U << 1,
+ RTC_BBPU_INIT = 1U << 2,
+ RTC_BBPU_AUTO = 1U << 3,
+ RTC_BBPU_CLRPKY = 1U << 4,
+ RTC_BBPU_RELOAD = 1U << 5,
+ RTC_BBPU_CBUSY = 1U << 6
+};
+
+enum {
+ RTC_AL_MASK_SEC = 1U << 0,
+ RTC_AL_MASK_MIN = 1U << 1,
+ RTC_AL_MASK_HOU = 1U << 2,
+ RTC_AL_MASK_DOM = 1U << 3,
+ RTC_AL_MASK_DOW = 1U << 4,
+ RTC_AL_MASK_MTH = 1U << 5,
+ RTC_AL_MASK_YEA = 1U << 6
+};
+
+enum {
+ RTC_BBPU_AUTO_PDN_SEL = 1U << 6,
+ RTC_BBPU_2SEC_CK_SEL = 1U << 7,
+ RTC_BBPU_2SEC_EN = 1U << 8,
+ RTC_BBPU_2SEC_MODE = 0x3 << 9,
+ RTC_BBPU_2SEC_STAT_CLEAR = 1U << 11,
+ RTC_BBPU_2SEC_STAT_STA = 1U << 12
+};
+
+enum {
+ RTC_BBPU_KEY = 0x43 << 8
+};
+
+enum {
+ RTC_EMBCK_SRC_SEL = 1 << 8,
+ RTC_EMBCK_SEL_MODE = 3 << 6,
+ RTC_XOSC32_ENB = 1 << 5,
+ RTC_REG_XOSC32_ENB = 1 << 15
+};
+
+enum {
+ RTC_K_EOSC_RSV_0 = 1 << 8,
+ RTC_K_EOSC_RSV_1 = 1 << 9,
+ RTC_K_EOSC_RSV_2 = 1 << 10
+};
+
+/* PMIC TOP Register Definition */
+enum {
+ PMIC_RG_TOP_CON = 0x001E,
+ PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
+ PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
+ PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
+ PMIC_RG_TOP_CKSEL_CON0 = 0x0118,
+ PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A,
+ PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C
+};
+
+/* PMIC SCK Register Definition */
+enum {
+ PMIC_RG_SCK_TOP_CKPDN_CON0 = 0x051A,
+ PMIC_RG_SCK_TOP_CKPDN_CON0_SET = 0x051C,
+ PMIC_RG_SCK_TOP_CKPDN_CON0_CLR = 0x051E,
+ PMIC_RG_EOSC_CALI_CON0 = 0x540
+};
+
+/* PMIC DCXO Register Definition */
+enum {
+ PMIC_RG_DCXO_CW00 = 0x0788,
+ PMIC_RG_DCXO_CW02 = 0x0790
+};
+
+enum {
+ PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK = 0x1,
+ PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT = 1,
+ PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK = 0x1,
+ PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT = 3,
+ PMIC_RG_RTC_EOSC32_CK_PDN_MASK = 0x1,
+ PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT = 2,
+ PMIC_RG_EOSC_CALI_TD_MASK = 0x7,
+ PMIC_RG_EOSC_CALI_TD_SHIFT = 5,
+ PMIC_RG_XO_EN32K_MAN_MASK = 0x1,
+ PMIC_RG_XO_EN32K_MAN_SHIFT = 0
+};
+
+/* external API */
+uint16_t RTC_Read(uint32_t addr);
+void RTC_Write(uint32_t addr, uint16_t data);
+int32_t rtc_busy_wait(void);
+int32_t RTC_Write_Trigger(void);
+int32_t Writeif_unlock(void);
+void rtc_power_off_sequence(void);
+
+#endif /* RTC_H */
diff --git a/plat/mediatek/mt8183/drivers/spmc/mtspmc.c b/plat/mediatek/mt8183/drivers/spmc/mtspmc.c
new file mode 100644
index 0000000..ac8e1b4
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/spmc/mtspmc.c
@@ -0,0 +1,366 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <arch_helpers.h>
+#include <cortex_a53.h>
+#include <cortex_a73.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <platform_def.h>
+#include <mcucfg.h>
+#include <spm.h>
+#include <drivers/delay_timer.h>
+#include <mtspmc.h>
+
+#include "mtspmc_private.h"
+
+
+static void set_retention(int cluster, int tick)
+{
+ uint64_t cpuectlr;
+
+ if (cluster)
+ cpuectlr = read_a73_cpuectlr_el1();
+ else
+ cpuectlr = read_a53_cpuectlr_el1();
+
+ cpuectlr &= ~0x7ULL;
+ cpuectlr |= tick & 0x7;
+
+ if (cluster)
+ write_a73_cpuectlr_el1(cpuectlr);
+ else
+ write_a53_cpuectlr_el1(cpuectlr);
+}
+
+void spm_enable_cpu_auto_off(int cluster, int cpu)
+{
+ uintptr_t reg = per_cpu(cluster, cpu, MCUCFG_SPARK);
+
+ set_retention(cluster, 1);
+ mmio_clrbits_32(reg, SW_NO_WAIT_Q);
+}
+
+void spm_disable_cpu_auto_off(int cluster, int cpu)
+{
+ uintptr_t reg = per_cpu(cluster, cpu, MCUCFG_SPARK);
+
+ mmio_setbits_32(reg, SW_NO_WAIT_Q);
+ set_retention(cluster, 0);
+}
+
+void spm_set_cpu_power_off(int cluster, int cpu)
+{
+ mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON);
+}
+
+void spm_enable_cluster_auto_off(int cluster)
+{
+ assert(cluster);
+
+ mmio_clrbits_32(MCUCFG_MP2_SPMC, SW_NO_WAIT_Q);
+ mmio_clrbits_32(MCUCFG_MP2_COQ, BIT(0));
+
+ mmio_clrbits_32(SPM_SPMC_DORMANT_ENABLE, MP1_SPMC_SRAM_DORMANT_EN);
+
+ mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON);
+}
+
+void mcucfg_set_bootaddr(int cluster, int cpu, uintptr_t bootaddr)
+{
+ uintptr_t reg;
+ const uintptr_t mp2_bootreg[] = {
+ MCUCFG_MP2_RVADDR0, MCUCFG_MP2_RVADDR1,
+ MCUCFG_MP2_RVADDR2, MCUCFG_MP2_RVADDR3 };
+
+ if (cluster) {
+ assert(cpu >= 0 && cpu < 4);
+ reg = mp2_bootreg[cpu];
+ } else {
+ reg = per_cpu(cluster, cpu, MCUCFG_BOOTADDR);
+ }
+
+ mmio_write_32(reg, bootaddr);
+}
+
+uintptr_t mcucfg_get_bootaddr(int cluster, int cpu)
+{
+ uintptr_t reg;
+ const uintptr_t mp2_bootreg[] = {
+ MCUCFG_MP2_RVADDR0, MCUCFG_MP2_RVADDR1,
+ MCUCFG_MP2_RVADDR2, MCUCFG_MP2_RVADDR3 };
+
+ if (cluster) {
+ assert(cpu >= 0 && cpu < 4);
+ reg = mp2_bootreg[cpu];
+ } else {
+ reg = per_cpu(cluster, cpu, MCUCFG_BOOTADDR);
+ }
+
+ return mmio_read_32(reg);
+}
+
+void mcucfg_init_archstate(int cluster, int cpu, int arm64)
+{
+ uintptr_t reg;
+ int i;
+
+ reg = per_cluster(cluster, MCUCFG_INITARCH);
+ i = cluster ? 16 : 12;
+
+ mmio_setbits_32(reg, (arm64 & 1) << (i + cpu));
+}
+
+/**
+ * Return power state of specified subsystem
+ *
+ * @mask: mask to SPM_PWR_STATUS to query the power state
+ * of one subsystem.
+ * RETURNS:
+ * 0 (the subsys was powered off)
+ * 1 (the subsys was powered on)
+ */
+int spm_get_powerstate(uint32_t mask)
+{
+ return mmio_read_32(SPM_PWR_STATUS) & mask;
+}
+
+int spm_get_cluster_powerstate(int cluster)
+{
+ uint32_t mask;
+
+ mask = cluster ? PWR_STATUS_MP1_CPUTOP : PWR_STATUS_MP0_CPUTOP;
+
+ return spm_get_powerstate(mask);
+}
+
+int spm_get_cpu_powerstate(int cluster, int cpu)
+{
+ uint32_t i;
+
+ /*
+ * a quick way to specify the mask of cpu[0-3]/cpu[4-7] in PWR_STATUS
+ * register which are the BITS[9:12](MP0_CPU0~3) and
+ * BITS[16:19](MP1_CPU0~3)
+ */
+ i = (cluster) ? 16 : 9;
+ i = 1 << (i + cpu);
+
+ return spm_get_powerstate(i);
+}
+
+int spmc_init(void)
+{
+ /* enable SPM register control */
+ mmio_write_32(SPM_POWERON_CONFIG_EN,
+ PROJECT_CODE | MD_BCLK_CG_EN | BCLK_CG_EN);
+
+#if SPMC_MODE == 1
+ INFO("SPM: enable SPMC mode\n");
+
+ /* 0: SPMC mode 1: Legacy mode */
+ mmio_write_32(SPM_BYPASS_SPMC, 0);
+
+ mmio_clrbits_32(per_cluster(0, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON_2ND);
+
+ mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
+ mmio_clrbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
+ mmio_clrbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
+ mmio_clrbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
+
+ mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
+ mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
+ mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
+#endif
+
+ mmio_clrbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON_2ND);
+ mmio_setbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_RST_B);
+ mmio_clrbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_CLK_DIS);
+
+ mmio_clrbits_32(per_cpu(1, 0, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
+ mmio_clrbits_32(per_cpu(1, 1, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
+ mmio_clrbits_32(per_cpu(1, 2, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
+ mmio_clrbits_32(per_cpu(1, 3, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
+
+ mmio_setbits_32(per_cpu(1, 0, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
+ mmio_setbits_32(per_cpu(1, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
+ mmio_setbits_32(per_cpu(1, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
+ mmio_setbits_32(per_cpu(1, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
+
+ return 0;
+}
+
+/**
+ * Power on a core with specified cluster and core index
+ *
+ * @cluster: the cluster ID of the CPU which to be powered on
+ * @cpu: the CPU ID of the CPU which to be powered on
+ */
+void spm_poweron_cpu(int cluster, int cpu)
+{
+ INFO("spmc: power on core %d.%d\n", cluster, cpu);
+
+ /* STA_POWER_ON */
+ /* Start to turn on MP0_CPU0 */
+
+ /* Set PWR_RST_B = 1 */
+ mmio_setbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
+
+ /* Set PWR_ON = 1 */
+ mmio_setbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON);
+
+ /* Wait until MP0_CPU0_PWR_STA_MASK = 1 */
+ while (!spm_get_cpu_powerstate(cluster, cpu))
+ ;
+
+ /* Finish to turn on MP0_CPU0 */
+ INFO("spmc: power on core %d.%d successfully\n", cluster, cpu);
+}
+
+/**
+ * Power off a core with specified cluster and core index
+ *
+ * @cluster: the cluster ID of the CPU which to be powered off
+ * @cpu: the CPU ID of the CPU which to be powered off
+ */
+void spm_poweroff_cpu(int cluster, int cpu)
+{
+ INFO("spmc: power off core %d.%d\n", cluster, cpu);
+
+ /* Start to turn off MP0_CPU0 */
+ /* Set PWR_ON_2ND = 0 */
+ mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
+
+ /* Set PWR_ON = 0 */
+ mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON);
+
+ /* Wait until MP0_CPU0_PWR_STA_MASK = 0 */
+ while (spm_get_cpu_powerstate(cluster, cpu))
+ ;
+
+ /* Set PWR_RST_B = 0 */
+ mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
+
+ /* Finish to turn off MP0_CPU0 */
+ INFO("spmc: power off core %d.%d successfully\n", cluster, cpu);
+}
+
+/**
+ * Power off a cluster with specified index
+ *
+ * @cluster: the cluster index which to be powered off
+ */
+void spm_poweroff_cluster(int cluster)
+{
+ uint32_t mask;
+ uint32_t pwr_rst_ctl;
+
+ INFO("spmc: power off cluster %d\n", cluster);
+
+ /* Start to turn off MP0_CPUTOP */
+ /* Set bus protect - step1 : 0 */
+ mask = (cluster) ? MP1_CPUTOP_PROT_STEP1_0_MASK :
+ MP0_CPUTOP_PROT_STEP1_0_MASK;
+ mmio_write_32(INFRA_TOPAXI_PROTECTEN_1_SET, mask);
+
+ while ((mmio_read_32(INFRA_TOPAXI_PROTECTEN_STA1_1) & mask) != mask)
+ ;
+
+ /* Set PWR_ON_2ND = 0 */
+ mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR),
+ PWRCTRL_PWR_ON_2ND);
+
+ /* SPMC_DORMANT_ENABLE[0]=0 */
+ mask = (cluster) ? MP1_SPMC_SRAM_DORMANT_EN : MP0_SPMC_SRAM_DORMANT_EN;
+ mmio_clrbits_32(SPM_SPMC_DORMANT_ENABLE, mask);
+
+ /* Set PWR_ON = 0" */
+ mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON);
+
+ /* Wait until MP0_CPUTOP_PWR_STA_MASK = 0 */
+ while (spm_get_cluster_powerstate(cluster))
+ ;
+
+ /* NOTE
+ * Following flow only for BIG core cluster. It was from
+ * application note but not covered in mtcmos_ctrl.c
+ */
+ if (cluster) {
+ pwr_rst_ctl = mmio_read_32(MCUCFG_MP2_PWR_RST_CTL);
+ mmio_write_32(MCUCFG_MP2_PWR_RST_CTL,
+ (pwr_rst_ctl & ~SW_RST_B) | TOPAON_APB_MASK);
+ }
+
+ /* CPU_EXT_BUCK_ISO[0]=1 */
+ if (cluster)
+ mmio_setbits_32(SPM_CPU_EXT_BUCK_ISO, MP1_EXT_BUCK_ISO);
+
+ /* Finish to turn off MP0_CPUTOP */
+ INFO("spmc: power off cluster %d successfully\n", cluster);
+}
+
+/**
+ * Power on a cluster with specified index
+ *
+ * @cluster: the cluster index which to be powered on
+ */
+void spm_poweron_cluster(int cluster)
+{
+ uint32_t mask;
+ uint32_t pwr_rst_ctl;
+
+ INFO("spmc: power on cluster %d\n", cluster);
+
+ /* Start to turn on MP1_CPUTOP */
+
+ /* NOTE
+ * Following flow only for BIG core cluster. It was from
+ * application note but not covered in mtcmos_ctrl.c
+ */
+ if (cluster) {
+ mmio_clrbits_32(MCUCFG_MP2_PWR_RST_CTL, SW_RST_B);
+
+ /* CPU_EXT_BUCK_ISO[1]=0 */
+ /* Set mp<n>_vproc_ext_off to 0 to release vproc isolation control */
+ mmio_clrbits_32(SPM_CPU_EXT_BUCK_ISO, MP1_EXT_BUCK_ISO);
+
+ /* NOTE
+ * Following flow only for BIG core cluster. It was from
+ * application note but not covered in mtcmos_ctrl.c
+ */
+ pwr_rst_ctl = mmio_read_32(MCUCFG_MP2_PWR_RST_CTL);
+ mmio_write_32(MCUCFG_MP2_PWR_RST_CTL,
+ (pwr_rst_ctl | SW_RST_B) & ~TOPAON_APB_MASK);
+ }
+
+ /* Set PWR_ON_2ND = 0 */
+ mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR),
+ PWRCTRL_PWR_ON_2ND);
+
+ /* Set PWR_RST_B = 1 */
+ mmio_setbits_32(per_cluster(cluster, SPM_CLUSTER_PWR),
+ PWRCTRL_PWR_RST_B);
+
+ /* Set PWR_CLK_DIS = 0 */
+ mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR),
+ PWRCTRL_PWR_CLK_DIS);
+
+ /* Set PWR_ON = 1 */
+ mmio_setbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON);
+
+ /* Wait until MP1_CPUTOP_PWR_STA_MASK = 1 */
+ while (!spm_get_cluster_powerstate(cluster))
+ ;
+
+ /* Release bus protect - step1 : 0 */
+ mask = (cluster) ? MP1_CPUTOP_PROT_STEP1_0_MASK :
+ MP0_CPUTOP_PROT_STEP1_0_MASK;
+ mmio_write_32(INFRA_TOPAXI_PROTECTEN_1_CLR, mask);
+
+ /* Finish to turn on MP1_CPUTOP */
+ INFO("spmc: power on cluster %d successfully\n", cluster);
+}
diff --git a/plat/mediatek/mt8183/drivers/spmc/mtspmc.h b/plat/mediatek/mt8183/drivers/spmc/mtspmc.h
new file mode 100644
index 0000000..4cf3bcf
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/spmc/mtspmc.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTSPMC_H
+#define MTSPMC_H
+
+/*
+ * CONFIG_SPMC_MODE: Select CPU power control mode.
+ *
+ * 0: Legacy
+ * Control power flow from SW through SPM register (MP*_PWR_CON).
+ * 1: HW
+ * Control power flow from SPMC. Most control flow and timing are handled
+ * by SPMC.
+ */
+#define SPMC_MODE 1
+
+int spmc_init(void);
+
+void spm_poweron_cpu(int cluster, int cpu);
+void spm_poweroff_cpu(int cluster, int cpu);
+
+void spm_poweroff_cluster(int cluster);
+void spm_poweron_cluster(int cluster);
+
+int spm_get_cpu_powerstate(int cluster, int cpu);
+int spm_get_cluster_powerstate(int cluster);
+int spm_get_powerstate(uint32_t mask);
+
+void spm_enable_cpu_auto_off(int cluster, int cpu);
+void spm_disable_cpu_auto_off(int cluster, int cpu);
+void spm_set_cpu_power_off(int cluster, int cpu);
+void spm_enable_cluster_auto_off(int cluster);
+
+void mcucfg_init_archstate(int cluster, int cpu, int arm64);
+void mcucfg_set_bootaddr(int cluster, int cpu, uintptr_t bootaddr);
+uintptr_t mcucfg_get_bootaddr(int cluster, int cpu);
+
+#endif /* MTSPMC_H */
diff --git a/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h b/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h
new file mode 100644
index 0000000..613d471
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTSPMC_PRIVATE_H
+#define MTSPMC_PRIVATE_H
+
+/*
+ * per_cpu/cluster helper
+ */
+struct per_cpu_reg {
+ int cluster_addr;
+ int cpu_stride;
+};
+
+#define per_cpu(cluster, cpu, reg) (reg[cluster].cluster_addr + \
+ (cpu << reg[cluster].cpu_stride))
+#define per_cluster(cluster, reg) (reg[cluster].cluster_addr)
+
+/* SPMC related registers */
+#define SPM_POWERON_CONFIG_EN (SPM_BASE + 0x000)
+/* bit-fields of SPM_POWERON_CONFIG_EN */
+#define BCLK_CG_EN (1 << 0)
+#define MD_BCLK_CG_EN (1 << 1)
+#define PROJECT_CODE (0xb16 << 16)
+
+#define SPM_PWR_STATUS (SPM_BASE + 0x180)
+#define SPM_PWR_STATUS_2ND (SPM_BASE + 0x184)
+
+#define SPM_BYPASS_SPMC (SPM_BASE + 0x2b4)
+#define SPM_SPMC_DORMANT_ENABLE (SPM_BASE + 0x2b8)
+
+#define SPM_MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204)
+#define SPM_MP0_CPU0_PWR_CON (SPM_BASE + 0x208)
+#define SPM_MP0_CPU1_PWR_CON (SPM_BASE + 0x20C)
+#define SPM_MP0_CPU2_PWR_CON (SPM_BASE + 0x210)
+#define SPM_MP0_CPU3_PWR_CON (SPM_BASE + 0x214)
+#define SPM_MP1_CPUTOP_PWR_CON (SPM_BASE + 0x218)
+#define SPM_MP1_CPU0_PWR_CON (SPM_BASE + 0x21C)
+#define SPM_MP1_CPU1_PWR_CON (SPM_BASE + 0x220)
+#define SPM_MP1_CPU2_PWR_CON (SPM_BASE + 0x224)
+#define SPM_MP1_CPU3_PWR_CON (SPM_BASE + 0x228)
+#define SPM_MP0_CPUTOP_L2_PDN (SPM_BASE + 0x240)
+#define SPM_MP0_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x244)
+#define SPM_MP0_CPU0_L1_PDN (SPM_BASE + 0x248)
+#define SPM_MP0_CPU1_L1_PDN (SPM_BASE + 0x24C)
+#define SPM_MP0_CPU2_L1_PDN (SPM_BASE + 0x250)
+#define SPM_MP0_CPU3_L1_PDN (SPM_BASE + 0x254)
+#define SPM_MP1_CPUTOP_L2_PDN (SPM_BASE + 0x258)
+#define SPM_MP1_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x25C)
+#define SPM_MP1_CPU0_L1_PDN (SPM_BASE + 0x260)
+#define SPM_MP1_CPU1_L1_PDN (SPM_BASE + 0x264)
+#define SPM_MP1_CPU2_L1_PDN (SPM_BASE + 0x268)
+#define SPM_MP1_CPU3_L1_PDN (SPM_BASE + 0x26C)
+
+#define SPM_CPU_EXT_BUCK_ISO (SPM_BASE + 0x290)
+/* bit-fields of SPM_CPU_EXT_BUCK_ISO */
+#define MP0_EXT_BUCK_ISO (1 << 0)
+#define MP1_EXT_BUCK_ISO (1 << 1)
+#define MP_EXT_BUCK_ISO (1 << 2)
+
+/* bit-fields of SPM_PWR_STATUS */
+#define PWR_STATUS_MD (1 << 0)
+#define PWR_STATUS_CONN (1 << 1)
+#define PWR_STATUS_DDRPHY (1 << 2)
+#define PWR_STATUS_DISP (1 << 3)
+#define PWR_STATUS_MFG (1 << 4)
+#define PWR_STATUS_ISP (1 << 5)
+#define PWR_STATUS_INFRA (1 << 6)
+#define PWR_STATUS_VDEC (1 << 7)
+#define PWR_STATUS_MP0_CPUTOP (1 << 8)
+#define PWR_STATUS_MP0_CPU0 (1 << 9)
+#define PWR_STATUS_MP0_CPU1 (1 << 10)
+#define PWR_STATUS_MP0_CPU2 (1 << 11)
+#define PWR_STATUS_MP0_CPU3 (1 << 12)
+#define PWR_STATUS_MCUSYS (1 << 14)
+#define PWR_STATUS_MP1_CPUTOP (1 << 15)
+#define PWR_STATUS_MP1_CPU0 (1 << 16)
+#define PWR_STATUS_MP1_CPU1 (1 << 17)
+#define PWR_STATUS_MP1_CPU2 (1 << 18)
+#define PWR_STATUS_MP1_CPU3 (1 << 19)
+#define PWR_STATUS_VEN (1 << 21)
+#define PWR_STATUS_MFG_ASYNC (1 << 23)
+#define PWR_STATUS_AUDIO (1 << 24)
+#define PWR_STATUS_C2K (1 << 28)
+#define PWR_STATUS_MD_INFRA (1 << 29)
+
+
+/* bit-fields of SPM_*_PWR_CON */
+#define PWRCTRL_PWR_RST_B (1 << 0)
+#define PWRCTRL_PWR_ISO (1 << 1)
+#define PWRCTRL_PWR_ON (1 << 2)
+#define PWRCTRL_PWR_ON_2ND (1 << 3)
+#define PWRCTRL_PWR_CLK_DIS (1 << 4)
+#define PWRCTRL_PWR_SRAM_CKISO (1 << 5)
+#define PWRCTRL_PWR_SRAM_ISOINT_B (1 << 6)
+#define PWRCTRL_PWR_SRAM_PD_SLPB_CLAMP (1 << 7)
+#define PWRCTRL_PWR_SRAM_PDN (1 << 8)
+#define PWRCTRL_PWR_SRAM_SLEEP_B (1 << 12)
+#define PWRCTRL_PWR_SRAM_PDN_ACK (1 << 24)
+#define PWRCTRL_PWR_SRAM_SLEEP_B_ACK (1 << 28)
+
+/* per_cpu registers for SPM_MP?_CPU?_PWR_CON */
+static const struct per_cpu_reg SPM_CPU_PWR[] = {
+ [0] = { .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2 },
+ [1] = { .cluster_addr = SPM_MP1_CPU0_PWR_CON, .cpu_stride = 2 },
+};
+
+/* per_cluster registers for SPM_MP?_CPUTOP_PWR_CON */
+static const struct per_cpu_reg SPM_CLUSTER_PWR[] = {
+ [0] = { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON },
+ [1] = { .cluster_addr = SPM_MP1_CPUTOP_PWR_CON },
+};
+
+/* APB Module infracfg_ao */
+#define INFRA_TOPAXI_PROTECTEN_1 (INFRACFG_AO_BASE + 0x250)
+#define INFRA_TOPAXI_PROTECTEN_STA1_1 (INFRACFG_AO_BASE + 0x258)
+#define INFRA_TOPAXI_PROTECTEN_1_SET (INFRACFG_AO_BASE + 0x2A8)
+#define INFRA_TOPAXI_PROTECTEN_1_CLR (INFRACFG_AO_BASE + 0x2AC)
+
+/* bit-fields of INFRA_TOPAXI_PROTECTEN_1_SET */
+#define MP0_CPUTOP_PROT_STEP1_0_MASK ((1 << 10)|(1 << 12)| \
+ (1 << 13)|(1 << 26))
+#define MP1_CPUTOP_PROT_STEP1_0_MASK ((1 << 11)|(1 << 14)| \
+ (1 << 15)|(1 << 27))
+
+/* bit-fields of INFRA_TOPAXI_PROTECTEN_STA1_1 */
+#define MP0_CPUTOP_PROT_STEP1_0_ACK_MASK ((1 << 10)|(1 << 12)| \
+ (1 << 13)|(1 << 26))
+#define MP1_CPUTOP_PROT_STEP1_0_ACK_MASK ((1 << 11)|(1 << 14)| \
+ (1 << 15)|(1 << 27))
+
+
+/*
+ * MCU configuration registers
+ */
+#define MCUCFG_MP0_AXI_CONFIG ((uintptr_t)&mt8183_mcucfg->mp0_axi_config)
+#define MCUCFG_MP1_AXI_CONFIG ((uintptr_t)&mt8183_mcucfg->mp1_axi_config)
+/* bit-fields of MCUCFG_MP?_AXI_CONFIG */
+#define MCUCFG_AXI_CONFIG_BROADCASTINNER (1 << 0)
+#define MCUCFG_AXI_CONFIG_BROADCASTOUTER (1 << 1)
+#define MCUCFG_AXI_CONFIG_BROADCASTCACHEMAINT (1 << 2)
+#define MCUCFG_AXI_CONFIG_SYSBARDISABLE (1 << 3)
+#define MCUCFG_AXI_CONFIG_ACINACTM (1 << 4)
+#define MCUCFG_AXI_CONFIG_AINACTS (1 << 5)
+
+/* per_cpu registers for MCUCFG_MP?_AXI_CONFIG */
+static const struct per_cpu_reg MCUCFG_SCUCTRL[] = {
+ [0] = { .cluster_addr = MCUCFG_MP0_AXI_CONFIG },
+ [1] = { .cluster_addr = MCUCFG_MP1_AXI_CONFIG },
+};
+
+#define MCUCFG_MP0_MISC_CONFIG2 ((uintptr_t)&mt8183_mcucfg->mp0_misc_config[2])
+#define MCUCFG_MP0_MISC_CONFIG3 ((uintptr_t)&mt8183_mcucfg->mp0_misc_config[3])
+#define MCUCFG_MP1_MISC_CONFIG2 ((uintptr_t)&mt8183_mcucfg->mp1_misc_config[2])
+#define MCUCFG_MP1_MISC_CONFIG3 ((uintptr_t)&mt8183_mcucfg->mp1_misc_config[3])
+
+#define MCUCFG_CPUSYS0_SPARKVRETCNTRL (MCUCFG_BASE + 0x1c00)
+/* bit-fields of MCUCFG_CPUSYS0_SPARKVRETCNTRL */
+#define CPU0_SPARK_VRET_CTRL (0x3f << 0)
+#define CPU1_SPARK_VRET_CTRL (0x3f << 8)
+#define CPU2_SPARK_VRET_CTRL (0x3f << 16)
+#define CPU3_SPARK_VRET_CTRL (0x3f << 24)
+
+/* SPARK control in little cores */
+#define MCUCFG_CPUSYS0_CPU0_SPMC_CTL (MCUCFG_BASE + 0x1c30)
+#define MCUCFG_CPUSYS0_CPU1_SPMC_CTL (MCUCFG_BASE + 0x1c34)
+#define MCUCFG_CPUSYS0_CPU2_SPMC_CTL (MCUCFG_BASE + 0x1c38)
+#define MCUCFG_CPUSYS0_CPU3_SPMC_CTL (MCUCFG_BASE + 0x1c3c)
+/* bit-fields of MCUCFG_CPUSYS0_CPU?_SPMC_CTL */
+#define SW_SPARK_EN (1 << 0)
+#define SW_NO_WAIT_Q (1 << 1)
+
+/* the MCUCFG which BIG cores used is at (MCUCFG_BASE + 0x2000) */
+#define MCUCFG_MP2_BASE (MCUCFG_BASE + 0x2000)
+#define MCUCFG_MP2_PWR_RST_CTL (MCUCFG_MP2_BASE + 0x8)
+/* bit-fields of MCUCFG_MP2_PWR_RST_CTL */
+#define SW_RST_B (1 << 0)
+#define TOPAON_APB_MASK (1 << 1)
+
+#define MCUCFG_MP2_CPUCFG (MCUCFG_MP2_BASE + 0x208)
+
+#define MCUCFG_MP2_RVADDR0 (MCUCFG_MP2_BASE + 0x290)
+#define MCUCFG_MP2_RVADDR1 (MCUCFG_MP2_BASE + 0x298)
+#define MCUCFG_MP2_RVADDR2 (MCUCFG_MP2_BASE + 0x2c0)
+#define MCUCFG_MP2_RVADDR3 (MCUCFG_MP2_BASE + 0x2c8)
+
+/* SPMC control */
+#define MCUCFG_MP0_SPMC (MCUCFG_BASE + 0x788)
+#define MCUCFG_MP2_SPMC (MCUCFG_MP2_BASE + 0x2a0)
+#define MCUCFG_MP2_COQ (MCUCFG_MP2_BASE + 0x2bC)
+
+/* per_cpu registers for MCUCFG_MP?_MISC_CONFIG2 */
+static const struct per_cpu_reg MCUCFG_BOOTADDR[] = {
+ [0] = { .cluster_addr = MCUCFG_MP0_MISC_CONFIG2, .cpu_stride = 3 },
+};
+
+/* per_cpu registers for MCUCFG_MP?_MISC_CONFIG3 */
+static const struct per_cpu_reg MCUCFG_INITARCH[] = {
+ [0] = { .cluster_addr = MCUCFG_MP0_MISC_CONFIG3 },
+ [1] = { .cluster_addr = MCUCFG_MP2_CPUCFG },
+};
+
+/* SPARK control in BIG cores */
+#define MCUCFG_MP2_PTP3_CPU0_SPMC0 (MCUCFG_MP2_BASE + 0x430)
+#define MCUCFG_MP2_PTP3_CPU0_SPMC1 (MCUCFG_MP2_BASE + 0x434)
+#define MCUCFG_MP2_PTP3_CPU1_SPMC0 (MCUCFG_MP2_BASE + 0x438)
+#define MCUCFG_MP2_PTP3_CPU1_SPMC1 (MCUCFG_MP2_BASE + 0x43c)
+#define MCUCFG_MP2_PTP3_CPU2_SPMC0 (MCUCFG_MP2_BASE + 0x440)
+#define MCUCFG_MP2_PTP3_CPU2_SPMC1 (MCUCFG_MP2_BASE + 0x444)
+#define MCUCFG_MP2_PTP3_CPU3_SPMC0 (MCUCFG_MP2_BASE + 0x448)
+#define MCUCFG_MP2_PTP3_CPU3_SPMC1 (MCUCFG_MP2_BASE + 0x44c)
+/* bit-fields of MCUCFG_MP2_PTP3_CPU?_SPMC? */
+#define SW_SPARK_EN (1 << 0)
+#define SW_NO_WAIT_Q (1 << 1)
+
+#define MCUCFG_MP2_SPARK2LDO (MCUCFG_MP2_BASE + 0x700)
+/* bit-fields of MCUCFG_MP2_SPARK2LDO */
+#define SPARK_VRET_CTRL (0x3f << 0)
+#define CPU0_SPARK_LDO_AMUXSEL (0xf << 6)
+#define CPU1_SPARK_LDO_AMUXSEL (0xf << 10)
+#define CPU2_SPARK_LDO_AMUXSEL (0xf << 14)
+#define CPU3_SPARK_LDO_AMUXSEL (0xf << 18)
+
+/* per_cpu registers for SPARK */
+static const struct per_cpu_reg MCUCFG_SPARK[] = {
+ [0] = { .cluster_addr = MCUCFG_CPUSYS0_CPU0_SPMC_CTL, .cpu_stride = 2 },
+ [1] = { .cluster_addr = MCUCFG_MP2_PTP3_CPU0_SPMC0, .cpu_stride = 3 },
+};
+
+/* per_cpu registers for SPARK2LDO */
+static const struct per_cpu_reg MCUCFG_SPARK2LDO[] = {
+ [0] = { .cluster_addr = MCUCFG_CPUSYS0_SPARKVRETCNTRL },
+ [1] = { .cluster_addr = MCUCFG_MP2_SPARK2LDO },
+};
+
+#endif /* MTSPMC_PRIVATE_H */
diff --git a/plat/mediatek/mt8183/include/mt_gic_v3.h b/plat/mediatek/mt8183/include/mt_gic_v3.h
index e2706f4..9d78ddb 100644
--- a/plat/mediatek/mt8183/include/mt_gic_v3.h
+++ b/plat/mediatek/mt8183/include/mt_gic_v3.h
@@ -9,11 +9,6 @@
#include <lib/mmio.h>
-enum irq_schedule_mode {
- SW_MODE,
- HW_MODE
-};
-
#define GIC_INT_MASK (MCUCFG_BASE + 0x5e8)
#define GIC500_ACTIVE_SEL_SHIFT 3
#define GIC500_ACTIVE_SEL_MASK (0x7 << GIC500_ACTIVE_SEL_SHIFT)
diff --git a/plat/mediatek/mt8183/include/plat_dcm.h b/plat/mediatek/mt8183/include/plat_dcm.h
new file mode 100644
index 0000000..afa9b63
--- /dev/null
+++ b/plat/mediatek/mt8183/include/plat_dcm.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_DCM_H
+#define PLAT_DCM_H
+
+#define MP2_SYNC_DCM (MCUCFG_BASE + 0x2274)
+#define MP2_SYNC_DCM_MASK (0x1 << 0)
+#define MP2_SYNC_DCM_ON (0x1 << 0)
+#define MP2_SYNC_DCM_OFF (0x0 << 0)
+
+extern uint64_t plat_dcm_mcsi_a_addr;
+extern uint32_t plat_dcm_mcsi_a_val;
+extern int plat_dcm_initiated;
+
+extern void plat_dcm_mcsi_a_backup(void);
+extern void plat_dcm_mcsi_a_restore(void);
+extern void plat_dcm_rgu_enable(void);
+extern void plat_dcm_restore_cluster_on(unsigned long mpidr);
+extern void plat_dcm_msg_handler(uint64_t x1);
+extern unsigned long plat_dcm_get_enabled_cnt(uint64_t type);
+extern void plat_dcm_init(void);
+
+#define ALL_DCM_TYPE (ARMCORE_DCM_TYPE | MCUSYS_DCM_TYPE \
+ | STALL_DCM_TYPE | BIG_CORE_DCM_TYPE \
+ | GIC_SYNC_DCM_TYPE | RGU_DCM_TYPE \
+ | INFRA_DCM_TYPE \
+ | DDRPHY_DCM_TYPE | EMI_DCM_TYPE | DRAMC_DCM_TYPE \
+ | MCSI_DCM_TYPE)
+
+enum {
+ ARMCORE_DCM_TYPE = (1U << 0),
+ MCUSYS_DCM_TYPE = (1U << 1),
+ INFRA_DCM_TYPE = (1U << 2),
+ PERI_DCM_TYPE = (1U << 3),
+ EMI_DCM_TYPE = (1U << 4),
+ DRAMC_DCM_TYPE = (1U << 5),
+ DDRPHY_DCM_TYPE = (1U << 6),
+ STALL_DCM_TYPE = (1U << 7),
+ BIG_CORE_DCM_TYPE = (1U << 8),
+ GIC_SYNC_DCM_TYPE = (1U << 9),
+ LAST_CORE_DCM_TYPE = (1U << 10),
+ RGU_DCM_TYPE = (1U << 11),
+ TOPCKG_DCM_TYPE = (1U << 12),
+ LPDMA_DCM_TYPE = (1U << 13),
+ MCSI_DCM_TYPE = (1U << 14),
+ NR_DCM_TYPE = 15,
+};
+
+#endif /* PLAT_DCM_H */
\ No newline at end of file
diff --git a/plat/mediatek/mt8183/include/platform_def.h b/plat/mediatek/mt8183/include/platform_def.h
index bc9022b..f802ac2 100644
--- a/plat/mediatek/mt8183/include/platform_def.h
+++ b/plat/mediatek/mt8183/include/platform_def.h
@@ -273,7 +273,7 @@
******************************************************************************/
#define TZRAM_BASE 0x54600000
-#define TZRAM_SIZE 0x00020000
+#define TZRAM_SIZE 0x00030000
/*******************************************************************************
* BL31 specific defines.
@@ -291,7 +291,7 @@
******************************************************************************/
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
-#define MAX_XLAT_TABLES 4
+#define MAX_XLAT_TABLES 16
#define MAX_MMAP_REGIONS 16
/*******************************************************************************
diff --git a/plat/mediatek/mt8183/include/spm.h b/plat/mediatek/mt8183/include/spm.h
new file mode 100644
index 0000000..208d760
--- /dev/null
+++ b/plat/mediatek/mt8183/include/spm.h
@@ -0,0 +1,1715 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SPM_H
+#define SPM_H
+
+#define POWERON_CONFIG_EN (SPM_BASE + 0x000)
+#define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
+#define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
+#define SPM_CLK_CON (SPM_BASE + 0x00C)
+#define SPM_CLK_SETTLE (SPM_BASE + 0x010)
+#define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)
+#define PCM_CON0 (SPM_BASE + 0x018)
+#define PCM_CON1 (SPM_BASE + 0x01C)
+#define PCM_IM_PTR (SPM_BASE + 0x020)
+#define PCM_IM_LEN (SPM_BASE + 0x024)
+#define PCM_REG_DATA_INI (SPM_BASE + 0x028)
+#define PCM_PWR_IO_EN (SPM_BASE + 0x02C)
+#define PCM_TIMER_VAL (SPM_BASE + 0x030)
+#define PCM_WDT_VAL (SPM_BASE + 0x034)
+#define PCM_IM_HOST_RW_PTR (SPM_BASE + 0x038)
+#define PCM_IM_HOST_RW_DAT (SPM_BASE + 0x03C)
+#define PCM_EVENT_VECTOR0 (SPM_BASE + 0x040)
+#define PCM_EVENT_VECTOR1 (SPM_BASE + 0x044)
+#define PCM_EVENT_VECTOR2 (SPM_BASE + 0x048)
+#define PCM_EVENT_VECTOR3 (SPM_BASE + 0x04C)
+#define PCM_EVENT_VECTOR4 (SPM_BASE + 0x050)
+#define PCM_EVENT_VECTOR5 (SPM_BASE + 0x054)
+#define PCM_EVENT_VECTOR6 (SPM_BASE + 0x058)
+#define PCM_EVENT_VECTOR7 (SPM_BASE + 0x05C)
+#define PCM_EVENT_VECTOR8 (SPM_BASE + 0x060)
+#define PCM_EVENT_VECTOR9 (SPM_BASE + 0x064)
+#define PCM_EVENT_VECTOR10 (SPM_BASE + 0x068)
+#define PCM_EVENT_VECTOR11 (SPM_BASE + 0x06C)
+#define PCM_EVENT_VECTOR12 (SPM_BASE + 0x070)
+#define PCM_EVENT_VECTOR13 (SPM_BASE + 0x074)
+#define PCM_EVENT_VECTOR14 (SPM_BASE + 0x078)
+#define PCM_EVENT_VECTOR15 (SPM_BASE + 0x07C)
+#define PCM_EVENT_VECTOR_EN (SPM_BASE + 0x080)
+#define SPM_SWINT (SPM_BASE + 0x08C)
+#define SPM_SWINT_SET (SPM_BASE + 0x090)
+#define SPM_SWINT_CLR (SPM_BASE + 0x094)
+#define SPM_SCP_MAILBOX (SPM_BASE + 0x098)
+#define SPM_SCP_IRQ (SPM_BASE + 0x09C)
+#define SPM_TWAM_CON (SPM_BASE + 0x0A0)
+#define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x0A4)
+#define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x0A8)
+#define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x0B0)
+#define SPM_IRQ_MASK (SPM_BASE + 0x0B4)
+#define SPM_SRC_REQ (SPM_BASE + 0x0B8)
+#define SPM_SRC_MASK (SPM_BASE + 0x0BC)
+#define SPM_SRC2_MASK (SPM_BASE + 0x0C0)
+#define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x0C4)
+#define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0C8)
+#define SCP_CLK_CON (SPM_BASE + 0x0D0)
+#define PCM_DEBUG_CON (SPM_BASE + 0x0D4)
+#define PCM_REG0_DATA (SPM_BASE + 0x100)
+#define PCM_REG1_DATA (SPM_BASE + 0x104)
+#define PCM_REG2_DATA (SPM_BASE + 0x108)
+#define PCM_REG3_DATA (SPM_BASE + 0x10C)
+#define PCM_REG4_DATA (SPM_BASE + 0x110)
+#define PCM_REG5_DATA (SPM_BASE + 0x114)
+#define PCM_REG6_DATA (SPM_BASE + 0x118)
+#define PCM_REG7_DATA (SPM_BASE + 0x11C)
+#define PCM_REG8_DATA (SPM_BASE + 0x120)
+#define PCM_REG9_DATA (SPM_BASE + 0x124)
+#define PCM_REG10_DATA (SPM_BASE + 0x128)
+#define PCM_REG11_DATA (SPM_BASE + 0x12C)
+#define PCM_REG12_DATA (SPM_BASE + 0x130)
+#define PCM_REG13_DATA (SPM_BASE + 0x134)
+#define PCM_REG14_DATA (SPM_BASE + 0x138)
+#define PCM_REG15_DATA (SPM_BASE + 0x13C)
+#define PCM_REG12_MASK_B_STA (SPM_BASE + 0x140)
+#define PCM_REG12_EXT_DATA (SPM_BASE + 0x144)
+#define PCM_REG12_EXT_MASK_B_STA (SPM_BASE + 0x148)
+#define PCM_EVENT_REG_STA (SPM_BASE + 0x14C)
+#define PCM_TIMER_OUT (SPM_BASE + 0x150)
+#define PCM_WDT_OUT (SPM_BASE + 0x154)
+#define SPM_IRQ_STA (SPM_BASE + 0x158)
+#define SPM_WAKEUP_STA (SPM_BASE + 0x15C)
+#define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x160)
+#define SPM_WAKEUP_MISC (SPM_BASE + 0x164)
+#define BUS_PROTECT_RDY (SPM_BASE + 0x168)
+#define BUS_PROTECT2_RDY (SPM_BASE + 0x16C)
+#define SUBSYS_IDLE_STA (SPM_BASE + 0x170)
+#define CPU_IDLE_STA (SPM_BASE + 0x174)
+#define PCM_FSM_STA (SPM_BASE + 0x178)
+#define PWR_STATUS (SPM_BASE + 0x180)
+#define PWR_STATUS_2ND (SPM_BASE + 0x184)
+#define CPU_PWR_STATUS (SPM_BASE + 0x188)
+#define CPU_PWR_STATUS_2ND (SPM_BASE + 0x18C)
+#define PCM_WDT_LATCH_0 (SPM_BASE + 0x190)
+#define PCM_WDT_LATCH_1 (SPM_BASE + 0x194)
+#define PCM_WDT_LATCH_2 (SPM_BASE + 0x198)
+#define DRAMC_DBG_LATCH (SPM_BASE + 0x19C)
+#define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1A0)
+#define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1A4)
+#define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1A8)
+#define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1AC)
+#define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1B0)
+#define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1B4)
+#define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1B8)
+#define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1BC)
+#define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1C0)
+#define PCM_WDT_LATCH_3 (SPM_BASE + 0x1C4)
+#define SPM_SRC_RDY_STA (SPM_BASE + 0x1D0)
+#define MISC_STA (SPM_BASE + 0x1D4)
+#define MCU_PWR_CON (SPM_BASE + 0x200)
+#define MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204)
+#define MP0_CPU0_PWR_CON (SPM_BASE + 0x208)
+#define MP0_CPU1_PWR_CON (SPM_BASE + 0x20C)
+#define MP0_CPU2_PWR_CON (SPM_BASE + 0x210)
+#define MP0_CPU3_PWR_CON (SPM_BASE + 0x214)
+#define MP1_CPUTOP_PWR_CON (SPM_BASE + 0x218)
+#define MP1_CPU0_PWR_CON (SPM_BASE + 0x21C)
+#define MP1_CPU1_PWR_CON (SPM_BASE + 0x220)
+#define MP1_CPU2_PWR_CON (SPM_BASE + 0x224)
+#define MP1_CPU3_PWR_CON (SPM_BASE + 0x228)
+#define MP0_CPUTOP_L2_PDN (SPM_BASE + 0x240)
+#define MP0_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x244)
+#define MP0_CPU0_L1_PDN (SPM_BASE + 0x248)
+#define MP0_CPU1_L1_PDN (SPM_BASE + 0x24C)
+#define MP0_CPU2_L1_PDN (SPM_BASE + 0x250)
+#define MP0_CPU3_L1_PDN (SPM_BASE + 0x254)
+#define MP1_CPUTOP_L2_PDN (SPM_BASE + 0x258)
+#define MP1_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x25C)
+#define MP1_CPU0_L1_PDN (SPM_BASE + 0x260)
+#define MP1_CPU1_L1_PDN (SPM_BASE + 0x264)
+#define MP1_CPU2_L1_PDN (SPM_BASE + 0x268)
+#define MP1_CPU3_L1_PDN (SPM_BASE + 0x26C)
+#define CPU_EXT_BUCK_ISO (SPM_BASE + 0x290)
+#define DUMMY1_PWR_CON (SPM_BASE + 0x2B0)
+#define BYPASS_SPMC (SPM_BASE + 0x2B4)
+#define SPMC_DORMANT_ENABLE (SPM_BASE + 0x2B8)
+#define ARMPLL_CLK_CON (SPM_BASE + 0x2BC)
+#define SPMC_IN_RET (SPM_BASE + 0x2C0)
+#define VDE_PWR_CON (SPM_BASE + 0x300)
+#define VEN_PWR_CON (SPM_BASE + 0x304)
+#define ISP_PWR_CON (SPM_BASE + 0x308)
+#define DIS_PWR_CON (SPM_BASE + 0x30C)
+#define MJC_PWR_CON (SPM_BASE + 0x310)
+#define AUDIO_PWR_CON (SPM_BASE + 0x314)
+#define IFR_PWR_CON (SPM_BASE + 0x318)
+#define DPY_PWR_CON (SPM_BASE + 0x31C)
+#define MD1_PWR_CON (SPM_BASE + 0x320)
+#define MD2_PWR_CON (SPM_BASE + 0x324)
+#define C2K_PWR_CON (SPM_BASE + 0x328)
+#define CONN_PWR_CON (SPM_BASE + 0x32C)
+#define VCOREPDN_PWR_CON (SPM_BASE + 0x330)
+#define MFG_ASYNC_PWR_CON (SPM_BASE + 0x334)
+#define MFG_PWR_CON (SPM_BASE + 0x338)
+#define MFG_CORE0_PWR_CON (SPM_BASE + 0x33C)
+#define MFG_CORE1_PWR_CON (SPM_BASE + 0x340)
+#define CAM_PWR_CON (SPM_BASE + 0x344)
+#define SYSRAM_CON (SPM_BASE + 0x350)
+#define SYSROM_CON (SPM_BASE + 0x354)
+#define SCP_SRAM_CON (SPM_BASE + 0x358)
+#define GCPU_SRAM_CON (SPM_BASE + 0x35C)
+#define MDSYS_INTF_INFRA_PWR_CON (SPM_BASE + 0x360)
+#define MDSYS_INTF_MD1_PWR_CON (SPM_BASE + 0x364)
+#define MDSYS_INTF_C2K_PWR_CON (SPM_BASE + 0x368)
+#define BSI_TOP_SRAM_CON (SPM_BASE + 0x370)
+#define DVFSP_SRAM_CON (SPM_BASE + 0x374)
+#define MD_EXT_BUCK_ISO (SPM_BASE + 0x390)
+#define DUMMY2_PWR_CON (SPM_BASE + 0x3B0)
+#define MD1_OUTPUT_PISO_S_EN_IZ (SPM_BASE + 0x3B4)
+#define SPM_DVFS_CON (SPM_BASE + 0x400)
+#define SPM_MDBSI_CON (SPM_BASE + 0x404)
+#define SPM_MAS_PAUSE_MASK_B (SPM_BASE + 0x408)
+#define SPM_MAS_PAUSE2_MASK_B (SPM_BASE + 0x40C)
+#define SPM_BSI_GEN (SPM_BASE + 0x410)
+#define SPM_BSI_EN_SR (SPM_BASE + 0x414)
+#define SPM_BSI_CLK_SR (SPM_BASE + 0x418)
+#define SPM_BSI_D0_SR (SPM_BASE + 0x41C)
+#define SPM_BSI_D1_SR (SPM_BASE + 0x420)
+#define SPM_BSI_D2_SR (SPM_BASE + 0x424)
+#define SPM_AP_SEMA (SPM_BASE + 0x428)
+#define SPM_SPM_SEMA (SPM_BASE + 0x42C)
+#define AP2MD_CROSS_TRIGGER (SPM_BASE + 0x430)
+#define AP_MDSRC_REQ (SPM_BASE + 0x434)
+#define SPM2MD_DVFS_CON (SPM_BASE + 0x438)
+#define MD2SPM_DVFS_CON (SPM_BASE + 0x43C)
+#define DRAMC_DPY_CLK_SW_CON_RSV (SPM_BASE + 0x440)
+#define DPY_LP_CON (SPM_BASE + 0x444)
+#define CPU_DVFS_REQ (SPM_BASE + 0x448)
+#define SPM_PLL_CON (SPM_BASE + 0x44C)
+#define SPM_EMI_BW_MODE (SPM_BASE + 0x450)
+#define AP2MD_PEER_WAKEUP (SPM_BASE + 0x454)
+#define ULPOSC_CON (SPM_BASE + 0x458)
+#define DRAMC_DPY_CLK_SW_CON_SEL (SPM_BASE + 0x460)
+#define DRAMC_DPY_CLK_SW_CON (SPM_BASE + 0x464)
+#define DRAMC_DPY_CLK_SW_CON_SEL2 (SPM_BASE + 0x470)
+#define DRAMC_DPY_CLK_SW_CON2 (SPM_BASE + 0x474)
+#define SPM_SEMA_M0 (SPM_BASE + 0x480)
+#define SPM_SEMA_M1 (SPM_BASE + 0x484)
+#define SPM_SEMA_M2 (SPM_BASE + 0x488)
+#define SPM_SEMA_M3 (SPM_BASE + 0x48C)
+#define SPM_SEMA_M4 (SPM_BASE + 0x490)
+#define SPM_SEMA_M5 (SPM_BASE + 0x494)
+#define SPM_SEMA_M6 (SPM_BASE + 0x498)
+#define SPM_SEMA_M7 (SPM_BASE + 0x49C)
+#define SPM_SEMA_M8 (SPM_BASE + 0x4A0)
+#define SPM_SEMA_M9 (SPM_BASE + 0x4A4)
+#define SRAM_DREQ_ACK (SPM_BASE + 0x4AC)
+#define SRAM_DREQ_CON (SPM_BASE + 0x4B0)
+#define SRAM_DREQ_CON_SET (SPM_BASE + 0x4B4)
+#define SRAM_DREQ_CON_CLR (SPM_BASE + 0x4B8)
+#define MP0_CPU0_IRQ_MASK (SPM_BASE + 0x500)
+#define MP0_CPU1_IRQ_MASK (SPM_BASE + 0x504)
+#define MP0_CPU2_IRQ_MASK (SPM_BASE + 0x508)
+#define MP0_CPU3_IRQ_MASK (SPM_BASE + 0x50C)
+#define MP1_CPU0_IRQ_MASK (SPM_BASE + 0x510)
+#define MP1_CPU1_IRQ_MASK (SPM_BASE + 0x514)
+#define MP1_CPU2_IRQ_MASK (SPM_BASE + 0x518)
+#define MP1_CPU3_IRQ_MASK (SPM_BASE + 0x51C)
+#define MP0_CPU0_WFI_EN (SPM_BASE + 0x530)
+#define MP0_CPU1_WFI_EN (SPM_BASE + 0x534)
+#define MP0_CPU2_WFI_EN (SPM_BASE + 0x538)
+#define MP0_CPU3_WFI_EN (SPM_BASE + 0x53C)
+#define MP1_CPU0_WFI_EN (SPM_BASE + 0x540)
+#define MP1_CPU1_WFI_EN (SPM_BASE + 0x544)
+#define MP1_CPU2_WFI_EN (SPM_BASE + 0x548)
+#define MP1_CPU3_WFI_EN (SPM_BASE + 0x54C)
+#define CPU_PTPOD2_CON (SPM_BASE + 0x560)
+#define ROOT_CPUTOP_ADDR (SPM_BASE + 0x570)
+#define ROOT_CORE_ADDR (SPM_BASE + 0x574)
+#define CPU_SPARE_CON (SPM_BASE + 0x580)
+#define CPU_SPARE_CON_SET (SPM_BASE + 0x584)
+#define CPU_SPARE_CON_CLR (SPM_BASE + 0x588)
+#define SPM_SW_FLAG (SPM_BASE + 0x600)
+#define SPM_SW_DEBUG (SPM_BASE + 0x604)
+#define SPM_SW_RSV_0 (SPM_BASE + 0x608)
+#define SPM_SW_RSV_1 (SPM_BASE + 0x60C)
+#define SPM_SW_RSV_2 (SPM_BASE + 0x610)
+#define SPM_SW_RSV_3 (SPM_BASE + 0x614)
+#define SPM_SW_RSV_4 (SPM_BASE + 0x618)
+#define SPM_SW_RSV_5 (SPM_BASE + 0x61C)
+#define SPM_RSV_CON (SPM_BASE + 0x620)
+#define SPM_RSV_STA (SPM_BASE + 0x624)
+#define SPM_PASR_DPD_0 (SPM_BASE + 0x630)
+#define SPM_PASR_DPD_1 (SPM_BASE + 0x634)
+#define SPM_PASR_DPD_2 (SPM_BASE + 0x638)
+#define SPM_PASR_DPD_3 (SPM_BASE + 0x63C)
+#define SPM_SPARE_CON (SPM_BASE + 0x640)
+#define SPM_SPARE_CON_SET (SPM_BASE + 0x644)
+#define SPM_SPARE_CON_CLR (SPM_BASE + 0x648)
+#define SPM_SW_RSV_6 (SPM_BASE + 0x64C)
+#define SPM_SW_RSV_7 (SPM_BASE + 0x650)
+#define SPM_SW_RSV_8 (SPM_BASE + 0x654)
+#define SPM_SW_RSV_9 (SPM_BASE + 0x658)
+#define SPM_SW_RSV_10 (SPM_BASE + 0x65C)
+#define SPM_SW_RSV_11 (SPM_BASE + 0x660)
+#define SPM_SW_RSV_12 (SPM_BASE + 0x664)
+#define SPM_SW_RSV_13 (SPM_BASE + 0x668)
+#define SPM_SW_RSV_14 (SPM_BASE + 0x66C)
+#define SPM_SW_RSV_15 (SPM_BASE + 0x670)
+#define SPM_SW_RSV_16 (SPM_BASE + 0x674)
+#define SPM_SW_RSV_17 (SPM_BASE + 0x678)
+#define SPM_SW_RSV_18 (SPM_BASE + 0x67C)
+#define SPM_SW_RSV_19 (SPM_BASE + 0x680)
+#define SW_CRTL_EVENT (SPM_BASE + 0x690)
+
+
+#define MP1_CPU3_PWR_STA_MASK (1U << 19)
+#define MP1_CPU2_PWR_STA_MASK (1U << 18)
+#define MP1_CPU1_PWR_STA_MASK (1U << 17)
+#define MP1_CPU0_PWR_STA_MASK (1U << 16)
+#define MP1_CPUTOP_PWR_STA_MASK (1U << 15)
+#define MCU_PWR_STA_MASK (1U << 14)
+#define MP0_CPU3_PWR_STA_MASK (1U << 12)
+#define MP0_CPU2_PWR_STA_MASK (1U << 11)
+#define MP0_CPU1_PWR_STA_MASK (1U << 10)
+#define MP0_CPU0_PWR_STA_MASK (1U << 9)
+#define MP0_CPUTOP_PWR_STA_MASK (1U << 8)
+
+
+#define MP1_CPU3_STANDBYWFI (1U << 17)
+#define MP1_CPU2_STANDBYWFI (1U << 16)
+#define MP1_CPU1_STANDBYWFI (1U << 15)
+#define MP1_CPU0_STANDBYWFI (1U << 14)
+#define MP0_CPU3_STANDBYWFI (1U << 13)
+#define MP0_CPU2_STANDBYWFI (1U << 12)
+#define MP0_CPU1_STANDBYWFI (1U << 11)
+#define MP0_CPU0_STANDBYWFI (1U << 10)
+
+#define MP0_SPMC_SRAM_DORMANT_EN (1<<0)
+#define MP1_SPMC_SRAM_DORMANT_EN (1<<1)
+#define MP2_SPMC_SRAM_DORMANT_EN (1<<2)
+
+/* POWERON_CONFIG_EN (0x10006000+0x000) */
+#define BCLK_CG_EN_LSB (1U << 0) /* 1b */
+#define PROJECT_CODE_LSB (1U << 16) /* 16b */
+
+/* SPM_POWER_ON_VAL0 (0x10006000+0x004) */
+#define POWER_ON_VAL0_LSB (1U << 0) /* 32b */
+
+/* SPM_POWER_ON_VAL1 (0x10006000+0x008) */
+#define POWER_ON_VAL1_LSB (1U << 0) /* 32b */
+
+/* SPM_CLK_CON (0x10006000+0x00C) */
+#define SYSCLK0_EN_CTRL_LSB (1U << 0) /* 2b */
+#define SYSCLK1_EN_CTRL_LSB (1U << 2) /* 2b */
+#define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */
+#define SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */
+#define EXT_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */
+#define CXO32K_REMOVE_EN_MD1_LSB (1U << 9) /* 1b */
+#define CXO32K_REMOVE_EN_MD2_LSB (1U << 10) /* 1b */
+#define CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */
+#define CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */
+#define SRCLKEN0_EN_LSB (1U << 13) /* 1b */
+#define SRCLKEN1_EN_LSB (1U << 14) /* 1b */
+#define SCP_DCM_EN_LSB (1U << 15) /* 1b */
+#define SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 7b */
+#define SYSCLK1_SRC_MASK_B_LSB (1U << 23) /* 7b */
+
+/* SPM_CLK_SETTLE (0x10006000+0x010) */
+#define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */
+
+/* SPM_AP_STANDBY_CON (0x10006000+0x014) */
+#define WFI_OP_LSB (1U << 0) /* 1b */
+#define MP0_CPUTOP_IDLE_MASK_LSB (1U << 1) /* 1b */
+#define MP1_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */
+#define MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */
+#define MM_MASK_B_LSB (1U << 16) /* 2b */
+#define MD_DDR_EN_DBC_EN_LSB (1U << 18) /* 1b */
+#define MD_MASK_B_LSB (1U << 19) /* 2b */
+#define SCP_MASK_B_LSB (1U << 21) /* 1b */
+#define LTE_MASK_B_LSB (1U << 22) /* 1b */
+#define SRCCLKENI_MASK_B_LSB (1U << 23) /* 1b */
+#define MD_APSRC_1_SEL_LSB (1U << 24) /* 1b */
+#define MD_APSRC_0_SEL_LSB (1U << 25) /* 1b */
+#define CONN_MASK_B_LSB (1U << 26) /* 1b */
+#define CONN_APSRC_SEL_LSB (1U << 27) /* 1b */
+
+/* PCM_CON0 (0x10006000+0x018) */
+#define PCM_KICK_L_LSB (1U << 0) /* 1b */
+#define IM_KICK_L_LSB (1U << 1) /* 1b */
+#define PCM_CK_EN_LSB (1U << 2) /* 1b */
+#define EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */
+#define IM_AUTO_PDN_EN_LSB (1U << 4) /* 1b */
+#define PCM_SW_RESET_LSB (1U << 15) /* 1b */
+#define PROJECT_CODE_LSB (1U << 16) /* 16b */
+
+/* PCM_CON1 (0x10006000+0x01C) */
+#define IM_SLAVE_LSB (1U << 0) /* 1b */
+#define IM_SLEEP_LSB (1U << 1) /* 1b */
+#define MIF_APBEN_LSB (1U << 3) /* 1b */
+#define IM_PDN_LSB (1U << 4) /* 1b */
+#define PCM_TIMER_EN_LSB (1U << 5) /* 1b */
+#define IM_NONRP_EN_LSB (1U << 6) /* 1b */
+#define DIS_MIF_PROT_LSB (1U << 7) /* 1b */
+#define PCM_WDT_EN_LSB (1U << 8) /* 1b */
+#define PCM_WDT_WAKE_MODE_LSB (1U << 9) /* 1b */
+#define SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */
+#define SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */
+#define EVENT_LOCK_EN_LSB (1U << 12) /* 1b */
+#define SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */
+#define SCP_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */
+#define PROJECT_CODE_LSB (1U << 16) /* 16b */
+
+/* PCM_IM_PTR (0x10006000+0x020) */
+#define PCM_IM_PTR_LSB (1U << 0) /* 32b */
+
+/* PCM_IM_LEN (0x10006000+0x024) */
+#define PCM_IM_LEN_LSB (1U << 0) /* 13b */
+
+/* PCM_REG_DATA_INI (0x10006000+0x028) */
+#define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */
+
+/* PCM_PWR_IO_EN (0x10006000+0x02C) */
+#define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */
+#define PCM_RF_SYNC_EN_LSB (1U << 16) /* 8b */
+
+/* PCM_TIMER_VAL (0x10006000+0x030) */
+#define PCM_TIMER_VAL_LSB (1U << 0) /* 32b */
+
+/* PCM_WDT_VAL (0x10006000+0x034) */
+#define PCM_WDT_VAL_LSB (1U << 0) /* 32b */
+
+/* PCM_IM_HOST_RW_PTR (0x10006000+0x038) */
+#define PCM_IM_HOST_RW_PTR_LSB (1U << 0) /* 12b */
+#define PCM_IM_HOST_W_EN_LSB (1U << 30) /* 1b */
+#define PCM_IM_HOST_EN_LSB (1U << 31) /* 1b */
+
+/* PCM_IM_HOST_RW_DAT (0x10006000+0x03C) */
+#define PCM_IM_HOST_RW_DAT_LSB (1U << 0) /* 32b */
+
+/* PCM_EVENT_VECTOR0 (0x10006000+0x040) */
+#define PCM_EVENT_VECTOR_0_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_0_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_0_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_0_LSB (1U << 16) /* 11b */
+
+/* PCM_EVENT_VECTOR1 (0x10006000+0x044) */
+#define PCM_EVENT_VECTOR_1_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_1_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_1_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_1_LSB (1U << 16) /* 11b */
+
+/* PCM_EVENT_VECTOR2 (0x10006000+0x048) */
+#define PCM_EVENT_VECTOR_2_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_2_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_2_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_2_LSB (1U << 16) /* 11b */
+
+/* PCM_EVENT_VECTOR3 (0x10006000+0x04C) */
+#define PCM_EVENT_VECTOR_3_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_3_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_3_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_3_LSB (1U << 16) /* 11b */
+
+/* PCM_EVENT_VECTOR4 (0x10006000+0x050) */
+#define PCM_EVENT_VECTOR_4_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_4_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_4_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_4_LSB (1U << 16) /* 11b */
+
+/* PCM_EVENT_VECTOR5 (0x10006000+0x054) */
+#define PCM_EVENT_VECTOR_5_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_5_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_5_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_5_LSB (1U << 16) /* 11b */
+
+/* PCM_EVENT_VECTOR6 (0x10006000+0x058) */
+#define PCM_EVENT_VECTOR_6_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_6_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_6_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_6_LSB (1U << 16) /* 11b */
+
+/* PCM_EVENT_VECTOR7 (0x10006000+0x05C) */
+#define PCM_EVENT_VECTOR_7_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_7_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_7_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_7_LSB (1U << 16) /* 11b */
+
+/* PCM_EVENT_VECTOR8 (0x10006000+0x060) */
+#define PCM_EVENT_VECTOR_8_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_8_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_8_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_8_LSB (1U << 16) /* 11b */
+
+/* PCM_EVENT_VECTOR9 (0x10006000+0x064) */
+#define PCM_EVENT_VECTOR_9_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_9_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_9_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_9_LSB (1U << 16) /* 11b */
+
+/* PCM_EVENT_VECTOR10 (0x10006000+0x068) */
+#define PCM_EVENT_VECTOR_10_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_10_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_10_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_10_LSB (1U << 16) /* 11b */
+
+/* PCM_EVENT_VECTOR11 (0x10006000+0x06C) */
+#define PCM_EVENT_VECTOR_11_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_11_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_11_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_11_LSB (1U << 16) /* 11b */
+
+/* PCM_EVENT_VECTOR12 (0x10006000+0x070) */
+#define PCM_EVENT_VECTOR_12_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_12_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_12_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_12_LSB (1U << 16) /* 11b */
+
+/* PCM_EVENT_VECTOR13 (0x10006000+0x074) */
+#define PCM_EVENT_VECTOR_13_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_13_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_13_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_13_LSB (1U << 16) /* 11b */
+
+/* PCM_EVENT_VECTOR14 (0x10006000+0x078) */
+#define PCM_EVENT_VECTOR_14_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_14_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_14_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_14_LSB (1U << 16) /* 11b */
+
+/* PCM_EVENT_VECTOR15 (0x10006000+0x07C) */
+#define PCM_EVENT_VECTOR_15_LSB (1U << 0) /* 6b */
+#define PCM_EVENT_RESUME_15_LSB (1U << 6) /* 1b */
+#define PCM_EVENT_IMMEDIA_15_LSB (1U << 7) /* 1b */
+#define PCM_EVENT_VECTPC_15_LSB (1U << 16) /* 11b */
+
+/* PCM_EVENT_VECTOR_EN (0x10006000+0x080) */
+#define PCM_EVENT_VECTOR_EN_LSB (1U << 0) /* 16b */
+
+/* SPM_SWINT (0x10006000+0x08C) */
+#define SPM_SWINT_LSB (1U << 0) /* 10b */
+
+/* SPM_SWINT_SET (0x10006000+0x090) */
+#define SPM_SWINT_SET_LSB (1U << 0) /* 10b */
+
+/* SPM_SWINT_CLR (0x10006000+0x094) */
+#define SPM_SWINT_CLR_LSB (1U << 0) /* 10b */
+
+/* SPM_SCP_MAILBOX (0x10006000+0x098) */
+#define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */
+
+/* SPM_SCP_IRQ (0x10006000+0x09C) */
+#define SPM_SCP_IRQ_LSB (1U << 0) /* 1b */
+#define SPM_SCP_IRQ_SEL_LSB (1U << 4) /* 1b */
+
+/* SPM_TWAM_CON (0x10006000+0x0A0) */
+#define TWAM_ENABLE_LSB (1U << 0) /* 1b */
+#define TWAM_SPEED_MODE_ENABLE_LSB (1U << 1) /* 1b */
+#define TWAM_SW_RST_LSB (1U << 2) /* 1b */
+#define TWAM_MON_TYPE0_LSB (1U << 4) /* 2b */
+#define TWAM_MON_TYPE1_LSB (1U << 6) /* 2b */
+#define TWAM_MON_TYPE2_LSB (1U << 8) /* 2b */
+#define TWAM_MON_TYPE3_LSB (1U << 10) /* 2b */
+#define TWAM_SIGNAL_SEL0_LSB (1U << 12) /* 5b */
+#define TWAM_SIGNAL_SEL1_LSB (1U << 17) /* 5b */
+#define TWAM_SIGNAL_SEL2_LSB (1U << 22) /* 5b */
+#define TWAM_SIGNAL_SEL3_LSB (1U << 27) /* 5b */
+
+/* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */
+#define TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */
+
+/* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */
+#define TWAM_IDLE_SEL_LSB (1U << 0) /* 5b */
+
+/* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */
+#define SPM_CPU_WAKEUP_EVENT_LSB (1U << 0) /* 1b */
+
+/* SPM_IRQ_MASK (0x10006000+0x0B4) */
+#define SPM_TWAM_IRQ_MASK_LSB (1U << 2) /* 1b */
+#define PCM_IRQ_ROOT_MASK_LSB (1U << 3) /* 1b */
+#define SPM_IRQ_MASK_LSB (1U << 8) /* 10b */
+
+/* SPM_SRC_REQ (0x10006000+0x0B8) */
+#define SPM_APSRC_REQ_LSB (1U << 0) /* 1b */
+#define SPM_F26M_REQ_LSB (1U << 1) /* 1b */
+#define SPM_LTE_REQ_LSB (1U << 2) /* 1b */
+#define SPM_INFRA_REQ_LSB (1U << 3) /* 1b */
+#define SPM_VRF18_REQ_LSB (1U << 4) /* 1b */
+#define SPM_DVFS_REQ_LSB (1U << 5) /* 1b */
+#define SPM_DVFS_FORCE_DOWN_LSB (1U << 6) /* 1b */
+#define SPM_DDREN_REQ_LSB (1U << 7) /* 1b */
+#define SPM_RSV_SRC_REQ_LSB (1U << 8) /* 3b */
+#define CPU_MD_DVFS_SOP_FORCE_ON_LSB (1U << 16) /* 1b */
+
+/* SPM_SRC_MASK (0x10006000+0x0BC) */
+#define CSYSPWREQ_MASK_LSB (1U << 0) /* 1b */
+#define CCIF0_MD_EVENT_MASK_B_LSB (1U << 1) /* 1b */
+#define CCIF0_AP_EVENT_MASK_B_LSB (1U << 2) /* 1b */
+#define CCIF1_MD_EVENT_MASK_B_LSB (1U << 3) /* 1b */
+#define CCIF1_AP_EVENT_MASK_B_LSB (1U << 4) /* 1b */
+#define CCIFMD_MD1_EVENT_MASK_B_LSB (1U << 5) /* 1b */
+#define CCIFMD_MD2_EVENT_MASK_B_LSB (1U << 6) /* 1b */
+#define DSI0_VSYNC_MASK_B_LSB (1U << 7) /* 1b */
+#define DSI1_VSYNC_MASK_B_LSB (1U << 8) /* 1b */
+#define DPI_VSYNC_MASK_B_LSB (1U << 9) /* 1b */
+#define ISP0_VSYNC_MASK_B_LSB (1U << 10) /* 1b */
+#define ISP1_VSYNC_MASK_B_LSB (1U << 11) /* 1b */
+#define MD_SRCCLKENA_0_INFRA_MASK_B_LSB (1U << 12) /* 1b */
+#define MD_SRCCLKENA_1_INFRA_MASK_B_LSB (1U << 13) /* 1b */
+#define CONN_SRCCLKENA_INFRA_MASK_B_LSB (1U << 14) /* 1b */
+#define MD32_SRCCLKENA_INFRA_MASK_B_LSB (1U << 15) /* 1b */
+#define SRCCLKENI_INFRA_MASK_B_LSB (1U << 16) /* 1b */
+#define MD_APSRC_REQ_0_INFRA_MASK_B_LSB (1U << 17) /* 1b */
+#define MD_APSRC_REQ_1_INFRA_MASK_B_LSB (1U << 18) /* 1b */
+#define CONN_APSRCREQ_INFRA_MASK_B_LSB (1U << 19) /* 1b */
+#define MD32_APSRCREQ_INFRA_MASK_B_LSB (1U << 20) /* 1b */
+#define MD_DDR_EN_0_MASK_B_LSB (1U << 21) /* 1b */
+#define MD_DDR_EN_1_MASK_B_LSB (1U << 22) /* 1b */
+#define MD_VRF18_REQ_0_MASK_B_LSB (1U << 23) /* 1b */
+#define MD_VRF18_REQ_1_MASK_B_LSB (1U << 24) /* 1b */
+#define MD1_DVFS_REQ_MASK_LSB (1U << 25) /* 2b */
+#define CPU_DVFS_REQ_MASK_LSB (1U << 27) /* 1b */
+#define EMI_BW_DVFS_REQ_MASK_LSB (1U << 28) /* 1b */
+#define MD_SRCCLKENA_0_DVFS_REQ_MASK_B_LSB (1U << 29) /* 1b */
+#define MD_SRCCLKENA_1_DVFS_REQ_MASK_B_LSB (1U << 30) /* 1b */
+#define CONN_SRCCLKENA_DVFS_REQ_MASK_B_LSB (1U << 31) /* 1b */
+
+/* SPM_SRC2_MASK (0x10006000+0x0C0) */
+#define DVFS_HALT_MASK_B_LSB (1U << 0) /* 5b */
+#define VDEC_REQ_MASK_B_LSB (1U << 6) /* 1b */
+#define GCE_REQ_MASK_B_LSB (1U << 7) /* 1b */
+#define CPU_MD_DVFS_REQ_MERGE_MASK_B_LSB (1U << 8) /* 1b */
+#define MD_DDR_EN_DVFS_HALT_MASK_B_LSB (1U << 9) /* 2b */
+#define DSI0_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 11) /* 1b */
+#define DSI1_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 12) /* 1b */
+#define DPI_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 13) /* 1b */
+#define ISP0_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 14) /* 1b */
+#define ISP1_VSYNC_DVFS_HALT_MASK_B_LSB (1U << 15) /* 1b */
+#define CONN_DDR_EN_MASK_B_LSB (1U << 16) /* 1b */
+#define DISP_REQ_MASK_B_LSB (1U << 17) /* 1b */
+#define DISP1_REQ_MASK_B_LSB (1U << 18) /* 1b */
+#define MFG_REQ_MASK_B_LSB (1U << 19) /* 1b */
+#define C2K_PS_RCCIF_WAKE_MASK_B_LSB (1U << 20) /* 1b */
+#define C2K_L1_RCCIF_WAKE_MASK_B_LSB (1U << 21) /* 1b */
+#define PS_C2K_RCCIF_WAKE_MASK_B_LSB (1U << 22) /* 1b */
+#define L1_C2K_RCCIF_WAKE_MASK_B_LSB (1U << 23) /* 1b */
+#define SDIO_ON_DVFS_REQ_MASK_B_LSB (1U << 24) /* 1b */
+#define EMI_BOOST_DVFS_REQ_MASK_B_LSB (1U << 25) /* 1b */
+#define CPU_MD_EMI_DVFS_REQ_PROT_DIS_LSB (1U << 26) /* 1b */
+#define DRAMC_SPCMD_APSRC_REQ_MASK_B_LSB (1U << 27) /* 1b */
+
+/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0C4) */
+#define SPM_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */
+
+/* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0C8) */
+#define SPM_WAKEUP_EVENT_EXT_MASK_LSB (1U << 0) /* 32b */
+
+/* SCP_CLK_CON (0x10006000+0x0D0) */
+#define SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */
+
+/* PCM_DEBUG_CON (0x10006000+0x0D4) */
+#define PCM_DEBUG_OUT_ENABLE_LSB (1U << 0) /* 1b */
+
+/* PCM_REG0_DATA (0x10006000+0x100) */
+#define PCM_REG0_DATA_LSB (1U << 0) /* 32b */
+
+/* PCM_REG1_DATA (0x10006000+0x104) */
+#define PCM_REG1_DATA_LSB (1U << 0) /* 32b */
+
+/* PCM_REG2_DATA (0x10006000+0x108) */
+#define PCM_REG2_DATA_LSB (1U << 0) /* 32b */
+
+/* PCM_REG3_DATA (0x10006000+0x10C) */
+#define PCM_REG3_DATA_LSB (1U << 0) /* 32b */
+
+/* PCM_REG4_DATA (0x10006000+0x110) */
+#define PCM_REG4_DATA_LSB (1U << 0) /* 32b */
+
+/* PCM_REG5_DATA (0x10006000+0x114) */
+#define PCM_REG5_DATA_LSB (1U << 0) /* 32b */
+
+/* PCM_REG6_DATA (0x10006000+0x118) */
+#define PCM_REG6_DATA_LSB (1U << 0) /* 32b */
+
+/* PCM_REG7_DATA (0x10006000+0x11C) */
+#define PCM_REG7_DATA_LSB (1U << 0) /* 32b */
+
+/* PCM_REG8_DATA (0x10006000+0x120) */
+#define PCM_REG8_DATA_LSB (1U << 0) /* 32b */
+
+/* PCM_REG9_DATA (0x10006000+0x124) */
+#define PCM_REG9_DATA_LSB (1U << 0) /* 32b */
+
+/* PCM_REG10_DATA (0x10006000+0x128) */
+#define PCM_REG10_DATA_LSB (1U << 0) /* 32b */
+
+/* PCM_REG11_DATA (0x10006000+0x12C) */
+#define PCM_REG11_DATA_LSB (1U << 0) /* 32b */
+
+/* PCM_REG12_DATA (0x10006000+0x130) */
+#define PCM_REG12_DATA_LSB (1U << 0) /* 32b */
+
+/* PCM_REG13_DATA (0x10006000+0x134) */
+#define PCM_REG13_DATA_LSB (1U << 0) /* 32b */
+
+/* PCM_REG14_DATA (0x10006000+0x138) */
+#define PCM_REG14_DATA_LSB (1U << 0) /* 32b */
+
+/* PCM_REG15_DATA (0x10006000+0x13C) */
+#define PCM_REG15_DATA_LSB (1U << 0) /* 32b */
+
+/* PCM_REG12_MASK_B_STA (0x10006000+0x140) */
+#define PCM_REG12_MASK_B_STA_LSB (1U << 0) /* 32b */
+
+/* PCM_REG12_EXT_DATA (0x10006000+0x144) */
+#define PCM_REG12_EXT_DATA_LSB (1U << 0) /* 32b */
+
+/* PCM_REG12_EXT_MASK_B_STA (0x10006000+0x148) */
+#define PCM_REG12_EXT_MASK_B_STA_LSB (1U << 0) /* 32b */
+
+/* PCM_EVENT_REG_STA (0x10006000+0x14C) */
+#define PCM_EVENT_REG_STA_LSB (1U << 0) /* 32b */
+
+/* PCM_TIMER_OUT (0x10006000+0x150) */
+#define PCM_TIMER_OUT_LSB (1U << 0) /* 32b */
+
+/* PCM_WDT_OUT (0x10006000+0x154) */
+#define PCM_WDT_OUT_LSB (1U << 0) /* 32b */
+
+/* SPM_IRQ_STA (0x10006000+0x158) */
+#define TWAM_IRQ_LSB (1U << 2) /* 1b */
+#define PCM_IRQ_LSB (1U << 3) /* 1b */
+#define SPM_IRQ_SWINT_LSB (1U << 4) /* 10b */
+
+/* SPM_WAKEUP_STA (0x10006000+0x15C) */
+#define SPM_WAKEUP_EVENT_STA_LSB (1U << 0) /* 32b */
+
+/* SPM_WAKEUP_EXT_STA (0x10006000+0x160) */
+#define SPM_WAKEUP_EVENT_EXT_STA_LSB (1U << 0) /* 32b */
+
+/* SPM_WAKEUP_MISC (0x10006000+0x164) */
+#define SPM_WAKEUP_EVENT_MISC_LSB (1U << 0) /* 30b */
+#define SPM_PWRAP_IRQ_ACK_LSB (1U << 30) /* 1b */
+#define SPM_PWRAP_IRQ_LSB (1U << 31) /* 1b */
+
+/* BUS_PROTECT_RDY (0x10006000+0x168) */
+#define BUS_PROTECT_RDY_LSB (1U << 0) /* 32b */
+
+/* BUS_PROTECT2_RDY (0x10006000+0x16C) */
+#define BUS_PROTECT2_RDY_LSB (1U << 0) /* 32b */
+
+/* SUBSYS_IDLE_STA (0x10006000+0x170) */
+#define SUBSYS_IDLE_STA_LSB (1U << 0) /* 32b */
+
+/* CPU_IDLE_STA (0x10006000+0x174) */
+#define MP0_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 0) /* 1b */
+#define MP0_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 1) /* 1b */
+#define MP0_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 2) /* 1b */
+#define MP0_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 3) /* 1b */
+#define MP1_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 4) /* 1b */
+#define MP1_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 5) /* 1b */
+#define MP1_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 6) /* 1b */
+#define MP1_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 7) /* 1b */
+#define MP0_CPU0_STANDBYWFI_LSB (1U << 10) /* 1b */
+#define MP0_CPU1_STANDBYWFI_LSB (1U << 11) /* 1b */
+#define MP0_CPU2_STANDBYWFI_LSB (1U << 12) /* 1b */
+#define MP0_CPU3_STANDBYWFI_LSB (1U << 13) /* 1b */
+#define MP1_CPU0_STANDBYWFI_LSB (1U << 14) /* 1b */
+#define MP1_CPU1_STANDBYWFI_LSB (1U << 15) /* 1b */
+#define MP1_CPU2_STANDBYWFI_LSB (1U << 16) /* 1b */
+#define MP1_CPU3_STANDBYWFI_LSB (1U << 17) /* 1b */
+#define MP0_CPUTOP_IDLE_LSB (1U << 20) /* 1b */
+#define MP1_CPUTOP_IDLE_LSB (1U << 21) /* 1b */
+#define MCU_BIU_IDLE_LSB (1U << 22) /* 1b */
+#define MCUSYS_IDLE_LSB (1U << 23) /* 1b */
+
+/* PCM_FSM_STA (0x10006000+0x178) */
+#define EXEC_INST_OP_LSB (1U << 0) /* 4b */
+#define PC_STATE_LSB (1U << 4) /* 3b */
+#define IM_STATE_LSB (1U << 7) /* 3b */
+#define MASTER_STATE_LSB (1U << 10) /* 5b */
+#define EVENT_FSM_LSB (1U << 15) /* 3b */
+#define PCM_CLK_SEL_STA_LSB (1U << 18) /* 3b */
+#define PCM_KICK_LSB (1U << 21) /* 1b */
+#define IM_KICK_LSB (1U << 22) /* 1b */
+#define EXT_SRCCLKEN_STA_LSB (1U << 23) /* 2b */
+#define EXT_SRCVOLTEN_STA_LSB (1U << 25) /* 1b */
+
+/* PWR_STATUS (0x10006000+0x180) */
+#define PWR_STATUS_LSB (1U << 0) /* 32b */
+
+/* PWR_STATUS_2ND (0x10006000+0x184) */
+#define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */
+
+/* CPU_PWR_STATUS (0x10006000+0x188) */
+#define CPU_PWR_STATUS_LSB (1U << 0) /* 32b */
+
+/* CPU_PWR_STATUS_2ND (0x10006000+0x18C) */
+#define CPU_PWR_STATUS_2ND_LSB (1U << 0) /* 32b */
+
+/* PCM_WDT_LATCH_0 (0x10006000+0x190) */
+#define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */
+
+/* PCM_WDT_LATCH_1 (0x10006000+0x194) */
+#define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */
+
+/* PCM_WDT_LATCH_2 (0x10006000+0x198) */
+#define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */
+
+/* DRAMC_DBG_LATCH (0x10006000+0x19C) */
+#define DRAMC_DEBUG_LATCH_STATUS_LSB (1U << 0) /* 32b */
+
+/* SPM_TWAM_LAST_STA0 (0x10006000+0x1A0) */
+#define SPM_TWAM_LAST_STA0_LSB (1U << 0) /* 32b */
+
+/* SPM_TWAM_LAST_STA1 (0x10006000+0x1A4) */
+#define SPM_TWAM_LAST_STA1_LSB (1U << 0) /* 32b */
+
+/* SPM_TWAM_LAST_STA2 (0x10006000+0x1A8) */
+#define SPM_TWAM_LAST_STA2_LSB (1U << 0) /* 32b */
+
+/* SPM_TWAM_LAST_STA3 (0x10006000+0x1AC) */
+#define SPM_TWAM_LAST_STA3_LSB (1U << 0) /* 32b */
+
+/* SPM_TWAM_CURR_STA0 (0x10006000+0x1B0) */
+#define SPM_TWAM_CURR_STA0_LSB (1U << 0) /* 32b */
+
+/* SPM_TWAM_CURR_STA1 (0x10006000+0x1B4) */
+#define SPM_TWAM_CURR_STA1_LSB (1U << 0) /* 32b */
+
+/* SPM_TWAM_CURR_STA2 (0x10006000+0x1B8) */
+#define SPM_TWAM_CURR_STA2_LSB (1U << 0) /* 32b */
+
+/* SPM_TWAM_CURR_STA3 (0x10006000+0x1BC) */
+#define SPM_TWAM_CURR_STA3_LSB (1U << 0) /* 32b */
+
+/* SPM_TWAM_TIMER_OUT (0x10006000+0x1C0) */
+#define SPM_TWAM_TIMER_OUT_LSB (1U << 0) /* 32b */
+
+/* PCM_WDT_LATCH_3 (0x10006000+0x1C4) */
+#define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */
+
+/* SPM_SRC_RDY_STA (0x10006000+0x1D0) */
+#define SPM_INFRA_SRC_ACK_LSB (1U << 0) /* 1b */
+#define SPM_VRF18_SRC_ACK_LSB (1U << 1) /* 1b */
+
+/* MISC_STA (0x10006000+0x1D4) */
+#define MM_DVFS_HALT_AF_MASK_LSB (1U << 0) /* 5b */
+
+/* MCU_PWR_CON (0x10006000+0x200) */
+#define MCU_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MCU_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MCU_PWR_ON_LSB (1U << 2) /* 1b */
+#define MCU_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MCU_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MCU_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MCU_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MCU_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MCU_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MCU_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MCU_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MCU_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+
+/* MP0_CPUTOP_PWR_CON (0x10006000+0x204) */
+#define MP0_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP0_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP0_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP0_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP0_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP0_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP0_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP0_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP0_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP0_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MP0_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MP0_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+
+/* MP0_CPU0_PWR_CON (0x10006000+0x208) */
+#define MP0_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP0_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP0_CPU0_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP0_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP0_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP0_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP0_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP0_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP0_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP0_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MP0_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MP0_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+
+/* MP0_CPU1_PWR_CON (0x10006000+0x20C) */
+#define MP0_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP0_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP0_CPU1_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP0_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP0_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP0_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP0_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP0_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP0_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP0_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MP0_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MP0_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+
+/* MP0_CPU2_PWR_CON (0x10006000+0x210) */
+#define MP0_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP0_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP0_CPU2_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP0_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP0_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP0_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP0_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP0_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP0_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP0_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MP0_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MP0_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+
+/* MP0_CPU3_PWR_CON (0x10006000+0x214) */
+#define MP0_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP0_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP0_CPU3_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP0_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP0_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP0_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP0_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP0_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP0_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP0_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MP0_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MP0_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+
+/* MP1_CPUTOP_PWR_CON (0x10006000+0x218) */
+#define MP1_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP1_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP1_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP1_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP1_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP1_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP1_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP1_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP1_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP1_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MP1_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MP1_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+
+/* MP1_CPU0_PWR_CON (0x10006000+0x21C) */
+#define MP1_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP1_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP1_CPU0_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP1_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP1_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP1_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP1_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP1_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP1_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP1_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MP1_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MP1_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+
+/* MP1_CPU1_PWR_CON (0x10006000+0x220) */
+#define MP1_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP1_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP1_CPU1_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP1_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP1_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP1_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP1_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP1_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP1_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP1_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MP1_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MP1_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+
+/* MP1_CPU2_PWR_CON (0x10006000+0x224) */
+#define MP1_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP1_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP1_CPU2_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP1_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP1_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP1_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP1_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP1_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP1_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP1_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MP1_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MP1_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+
+/* MP1_CPU3_PWR_CON (0x10006000+0x228) */
+#define MP1_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MP1_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MP1_CPU3_PWR_ON_LSB (1U << 2) /* 1b */
+#define MP1_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MP1_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MP1_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MP1_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MP1_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */
+#define MP1_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MP1_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */
+#define SC_MP1_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */
+#define SC_MP1_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */
+
+/* MP0_CPUTOP_L2_PDN (0x10006000+0x240) */
+#define MP0_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */
+#define MP0_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */
+
+/* MP0_CPUTOP_L2_SLEEP_B (0x10006000+0x244) */
+#define MP0_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */
+#define MP0_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */
+
+/* MP0_CPU0_L1_PDN (0x10006000+0x248) */
+#define MP0_CPU0_L1_PDN_LSB (1U << 0) /* 1b */
+#define MP0_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */
+
+/* MP0_CPU1_L1_PDN (0x10006000+0x24C) */
+#define MP0_CPU1_L1_PDN_LSB (1U << 0) /* 1b */
+#define MP0_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */
+
+/* MP0_CPU2_L1_PDN (0x10006000+0x250) */
+#define MP0_CPU2_L1_PDN_LSB (1U << 0) /* 1b */
+#define MP0_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */
+
+/* MP0_CPU3_L1_PDN (0x10006000+0x254) */
+#define MP0_CPU3_L1_PDN_LSB (1U << 0) /* 1b */
+#define MP0_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */
+
+/* MP1_CPUTOP_L2_PDN (0x10006000+0x258) */
+#define MP1_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */
+#define MP1_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */
+
+/* MP1_CPUTOP_L2_SLEEP_B (0x10006000+0x25C) */
+#define MP1_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */
+#define MP1_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */
+
+/* MP1_CPU0_L1_PDN (0x10006000+0x260) */
+#define MP1_CPU0_L1_PDN_LSB (1U << 0) /* 1b */
+#define MP1_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */
+
+/* MP1_CPU1_L1_PDN (0x10006000+0x264) */
+#define MP1_CPU1_L1_PDN_LSB (1U << 0) /* 1b */
+#define MP1_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */
+
+/* MP1_CPU2_L1_PDN (0x10006000+0x268) */
+#define MP1_CPU2_L1_PDN_LSB (1U << 0) /* 1b */
+#define MP1_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */
+
+/* MP1_CPU3_L1_PDN (0x10006000+0x26C) */
+#define MP1_CPU3_L1_PDN_LSB (1U << 0) /* 1b */
+#define MP1_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */
+
+/* CPU_EXT_BUCK_ISO (0x10006000+0x290) */
+#define MP0_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */
+#define MP1_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */
+
+/* DUMMY1_PWR_CON (0x10006000+0x2B0) */
+#define DUMMY1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DUMMY1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DUMMY1_PWR_ON_LSB (1U << 2) /* 1b */
+#define DUMMY1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DUMMY1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+
+/* BYPASS_SPMC (0x10006000+0x2B4) */
+#define BYPASS_CPU_SPMC_MODE_LSB (1U << 0) /* 1b */
+
+/* SPMC_DORMANT_ENABLE (0x10006000+0x2B8) */
+#define MP0_SPMC_SRAM_DORMANT_EN_LSB (1U << 0) /* 1b */
+#define MP1_SPMC_SRAM_DORMANT_EN_LSB (1U << 1) /* 1b */
+
+/* ARMPLL_CLK_CON (0x10006000+0x2BC) */
+#define MUXSEL_SC_CCIPLL_LSB (1U << 0) /* 1b */
+#define MUXSEL_SC_ARMPLL1_LSB (1U << 1) /* 1b */
+#define MUXSEL_SC_ARMPLL2_LSB (1U << 2) /* 1b */
+#define REG_SC_ARM_CLK_OFF_LSB (1U << 8) /* 4b */
+#define REG_SC_ARMPLL_OFF_LSB (1U << 12) /* 4b */
+#define REG_SC_ARMPLLOUT_OFF_LSB (1U << 16) /* 4b */
+#define REG_SC_FHC_PAUSE_LSB (1U << 20) /* 4b */
+#define REG_SC_ARMPLL_S_OFF_LSB (1U << 24) /* 4b */
+
+/* SPMC_IN_RET (0x10006000+0x2C0) */
+#define SPMC_STATUS_LSB (1U << 0) /* 8b */
+
+/* VDE_PWR_CON (0x10006000+0x300) */
+#define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VDE_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VDE_PWR_ON_LSB (1U << 2) /* 1b */
+#define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VDE_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+
+/* VEN_PWR_CON (0x10006000+0x304) */
+#define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VEN_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VEN_PWR_ON_LSB (1U << 2) /* 1b */
+#define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VEN_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+
+/* ISP_PWR_CON (0x10006000+0x308) */
+#define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define ISP_PWR_ISO_LSB (1U << 1) /* 1b */
+#define ISP_PWR_ON_LSB (1U << 2) /* 1b */
+#define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define ISP_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+
+/* DIS_PWR_CON (0x10006000+0x30C) */
+#define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DIS_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DIS_PWR_ON_LSB (1U << 2) /* 1b */
+#define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DIS_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+
+/* MJC_PWR_CON (0x10006000+0x310) */
+#define MJC_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MJC_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MJC_PWR_ON_LSB (1U << 2) /* 1b */
+#define MJC_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MJC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MJC_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define MJC_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+
+/* AUDIO_PWR_CON (0x10006000+0x314) */
+#define AUD_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define AUD_PWR_ISO_LSB (1U << 1) /* 1b */
+#define AUD_PWR_ON_LSB (1U << 2) /* 1b */
+#define AUD_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define AUD_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define AUD_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define AUD_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+
+/* IFR_PWR_CON (0x10006000+0x318) */
+#define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define IFR_PWR_ISO_LSB (1U << 1) /* 1b */
+#define IFR_PWR_ON_LSB (1U << 2) /* 1b */
+#define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define IFR_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+
+/* DPY_PWR_CON (0x10006000+0x31C) */
+#define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DPY_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DPY_PWR_ON_LSB (1U << 2) /* 1b */
+#define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DPY_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+
+/* MD1_PWR_CON (0x10006000+0x320) */
+#define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MD1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MD1_PWR_ON_LSB (1U << 2) /* 1b */
+#define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */
+
+/* MD2_PWR_CON (0x10006000+0x324) */
+#define MD2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MD2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MD2_PWR_ON_LSB (1U << 2) /* 1b */
+#define MD2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MD2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MD2_SRAM_PDN_LSB (1U << 8) /* 1b */
+
+/* C2K_PWR_CON (0x10006000+0x328) */
+#define C2K_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define C2K_PWR_ISO_LSB (1U << 1) /* 1b */
+#define C2K_PWR_ON_LSB (1U << 2) /* 1b */
+#define C2K_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define C2K_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+
+/* CONN_PWR_CON (0x10006000+0x32C) */
+#define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CONN_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CONN_PWR_ON_LSB (1U << 2) /* 1b */
+#define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define CONN_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define CONN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+
+/* VCOREPDN_PWR_CON (0x10006000+0x330) */
+#define VCOREPDN_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VCOREPDN_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VCOREPDN_PWR_ON_LSB (1U << 2) /* 1b */
+#define VCOREPDN_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VCOREPDN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+
+/* MFG_ASYNC_PWR_CON (0x10006000+0x334) */
+#define MFG_ASYNC_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG_ASYNC_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG_ASYNC_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG_ASYNC_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG_ASYNC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG_ASYNC_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define MFG_ASYNC_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+
+/* MFG_PWR_CON (0x10006000+0x338) */
+#define MFG_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG_SRAM_PDN_LSB (1U << 8) /* 6b */
+#define MFG_SRAM_PDN_ACK_LSB (1U << 16) /* 6b */
+
+/* MFG_CORE0_PWR_CON (0x10006000+0x33C) */
+#define MFG_CORE0_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG_CORE0_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG_CORE0_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG_CORE0_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG_CORE0_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG_CORE0_SRAM_PDN_LSB (1U << 5) /* 1b */
+#define MFG_CORE0_SRAM_PDN_ACK_LSB (1U << 6) /* 1b */
+
+/* MFG_CORE1_PWR_CON (0x10006000+0x340) */
+#define MFG_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG_CORE1_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG_CORE1_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG_CORE1_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG_CORE1_SRAM_PDN_LSB (1U << 5) /* 1b */
+#define MFG_CORE1_SRAM_PDN_ACK_LSB (1U << 6) /* 1b */
+
+/* CAM_PWR_CON (0x10006000+0x344) */
+#define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CAM_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CAM_PWR_ON_LSB (1U << 2) /* 1b */
+#define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define CAM_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+
+/* SYSRAM_CON (0x10006000+0x350) */
+#define IFR_SRAMROM_SRAM_PDN_LSB (1U << 0) /* 8b */
+#define IFR_SRAMROM_SRAM_CKISO_LSB (1U << 8) /* 8b */
+#define IFR_SRAMROM_SRAM_SLEEP_B_LSB (1U << 16) /* 8b */
+#define IFR_SRAMROM_SRAM_ISOINT_B_LSB (1U << 24) /* 8b */
+
+/* SYSROM_CON (0x10006000+0x354) */
+#define IFR_SRAMROM_ROM_PDN_LSB (1U << 0) /* 6b */
+
+/* SCP_SRAM_CON (0x10006000+0x358) */
+#define SCP_SRAM_PDN_LSB (1U << 0) /* 1b */
+#define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define SCP_SRAM_ISOINT_B_LSB (1U << 8) /* 1b */
+
+/* GCPU_SRAM_CON (0x10006000+0x35C) */
+#define GCPU_SRAM_PDN_LSB (1U << 0) /* 4b */
+#define GCPU_SRAM_CKISO_LSB (1U << 4) /* 4b */
+#define GCPU_SRAM_SLEEP_B_LSB (1U << 8) /* 4b */
+#define GCPU_SRAM_ISOINT_B_LSB (1U << 12) /* 4b */
+
+/* MDSYS_INTF_INFRA_PWR_CON (0x10006000+0x360) */
+#define MDSYS_INTF_INFRA_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MDSYS_INTF_INFRA_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MDSYS_INTF_INFRA_PWR_ON_LSB (1U << 2) /* 1b */
+#define MDSYS_INTF_INFRA_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MDSYS_INTF_INFRA_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+
+/* MDSYS_INTF_MD1_PWR_CON (0x10006000+0x364) */
+#define MDSYS_INTF_MD1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MDSYS_INTF_MD1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MDSYS_INTF_MD1_PWR_ON_LSB (1U << 2) /* 1b */
+#define MDSYS_INTF_MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MDSYS_INTF_MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+
+/* MDSYS_INTF_C2K_PWR_CON (0x10006000+0x368) */
+#define MDSYS_INTF_C2K_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MDSYS_INTF_C2K_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MDSYS_INTF_C2K_PWR_ON_LSB (1U << 2) /* 1b */
+#define MDSYS_INTF_C2K_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MDSYS_INTF_C2K_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+
+/* BSI_TOP_SRAM_CON (0x10006000+0x370) */
+#define BSI_TOP_SRAM_PDN_LSB (1U << 0) /* 7b */
+#define BSI_TOP_SRAM_DSLP_LSB (1U << 7) /* 7b */
+#define BSI_TOP_SRAM_SLEEP_B_LSB (1U << 14) /* 7b */
+#define BSI_TOP_SRAM_ISOINT_B_LSB (1U << 21) /* 7b */
+#define BSI_TOP_SRAM_ISO_EN_LSB (1U << 28) /* 2b */
+
+/* DVFSP_SRAM_CON (0x10006000+0x374) */
+#define DVFSP_SRAM_PDN_LSB (1U << 0) /* 2b */
+#define DVFSP_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */
+#define DVFSP_SRAM_ISOINT_B_LSB (1U << 8) /* 2b */
+
+/* MD_EXT_BUCK_ISO (0x10006000+0x390) */
+#define MD_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */
+
+/* DUMMY2_PWR_CON (0x10006000+0x3B0) */
+#define DUMMY2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DUMMY2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DUMMY2_PWR_ON_LSB (1U << 2) /* 1b */
+#define DUMMY2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DUMMY2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DUMMY2_SRAM_PDN_LSB (1U << 8) /* 4b */
+#define DUMMY2_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */
+
+/* MD1_OUTPUT_PISO_S_EN_IZ (0x10006000+0x3B4) */
+#define MD1_OUTPUT_PISO_S_EN_IZ_LSB (1U << 0) /* 1b */
+
+/* SPM_DVFS_CON (0x10006000+0x400) */
+#define SPM_DVFS_CON_LSB (1U << 0) /* 4b */
+#define SPM_DVFS_ACK_LSB (1U << 30) /* 2b */
+
+/* SPM_MDBSI_CON (0x10006000+0x404) */
+#define SPM_MDBSI_CON_LSB (1U << 0) /* 3b */
+
+/* SPM_MAS_PAUSE_MASK_B (0x10006000+0x408) */
+#define SPM_MAS_PAUSE_MASK_B_LSB (1U << 0) /* 32b */
+
+/* SPM_MAS_PAUSE2_MASK_B (0x10006000+0x40C) */
+#define SPM_MAS_PAUSE2_MASK_B_LSB (1U << 0) /* 32b */
+
+/* SPM_BSI_GEN (0x10006000+0x410) */
+#define SPM_BSI_START_LSB (1U << 0) /* 1b */
+
+/* SPM_BSI_EN_SR (0x10006000+0x414) */
+#define SPM_BSI_EN_SR_LSB (1U << 0) /* 32b */
+
+/* SPM_BSI_CLK_SR (0x10006000+0x418) */
+#define SPM_BSI_CLK_SR_LSB (1U << 0) /* 32b */
+
+/* SPM_BSI_D0_SR (0x10006000+0x41C) */
+#define SPM_BSI_D0_SR_LSB (1U << 0) /* 32b */
+
+/* SPM_BSI_D1_SR (0x10006000+0x420) */
+#define SPM_BSI_D1_SR_LSB (1U << 0) /* 32b */
+
+/* SPM_BSI_D2_SR (0x10006000+0x424) */
+#define SPM_BSI_D2_SR_LSB (1U << 0) /* 32b */
+
+/* SPM_AP_SEMA (0x10006000+0x428) */
+#define SPM_AP_SEMA_LSB (1U << 0) /* 1b */
+
+/* SPM_SPM_SEMA (0x10006000+0x42C) */
+#define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */
+
+/* AP2MD_CROSS_TRIGGER (0x10006000+0x430) */
+#define AP2MD_CROSS_TRIGGER_REQ_LSB (1U << 0) /* 1b */
+#define AP2MD_CROSS_TRIGGER_ACK_LSB (1U << 1) /* 1b */
+
+/* AP_MDSRC_REQ (0x10006000+0x434) */
+#define AP_MD1SRC_REQ_LSB (1U << 0) /* 1b */
+#define AP_MD2SRC_REQ_LSB (1U << 1) /* 1b */
+#define AP_MD1SRC_ACK_LSB (1U << 4) /* 1b */
+#define AP_MD2SRC_ACK_LSB (1U << 5) /* 1b */
+
+/* SPM2MD_DVFS_CON (0x10006000+0x438) */
+#define SPM2MD_DVFS_CON_LSB (1U << 0) /* 16b */
+
+/* MD2SPM_DVFS_CON (0x10006000+0x43C) */
+#define MD2SPM_DVFS_CON_LSB (1U << 0) /* 16b */
+
+/* DRAMC_DPY_CLK_SW_CON_RSV (0x10006000+0x440) */
+#define SPM2DRAMC_SHUFFLE_START_LSB (1U << 0) /* 1b */
+#define SPM2DRAMC_SHUFFLE_SWITCH_LSB (1U << 1) /* 1b */
+#define SPM2DPY_DIV2_SYNC_LSB (1U << 2) /* 1b */
+#define SPM2DPY_1PLL_SWITCH_LSB (1U << 3) /* 1b */
+#define SPM2DPY_TEST_CK_MUX_LSB (1U << 4) /* 1b */
+#define SPM2DPY_ASYNC_MODE_LSB (1U << 5) /* 1b */
+#define SPM2TOP_ASYNC_MODE_LSB (1U << 6) /* 1b */
+
+/* DPY_LP_CON (0x10006000+0x444) */
+#define SC_DDRPHY_LP_SIGNALS_LSB (1U << 0) /* 3b */
+
+/* CPU_DVFS_REQ (0x10006000+0x448) */
+#define CPU_DVFS_REQ_LSB (1U << 0) /* 16b */
+#define DVFS_HALT_LSB (1U << 16) /* 1b */
+#define MD_DVFS_ERROR_STATUS_LSB (1U << 17) /* 1b */
+
+/* SPM_PLL_CON (0x10006000+0x44C) */
+#define SC_MPLLOUT_OFF_LSB (1U << 0) /* 1b */
+#define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */
+#define SC_MPLL_OFF_LSB (1U << 4) /* 1b */
+#define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */
+#define SC_MPLL_S_OFF_LSB (1U << 8) /* 1b */
+#define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */
+#define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */
+#define SC_MD32K_CK_OFF_LSB (1U << 17) /* 1b */
+
+/* SPM_EMI_BW_MODE (0x10006000+0x450) */
+#define EMI_BW_MODE_LSB (1U << 0) /* 1b */
+#define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */
+
+/* AP2MD_PEER_WAKEUP (0x10006000+0x454) */
+#define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */
+
+/* ULPOSC_CON (0x10006000+0x458) */
+#define ULPOSC_EN_LSB (1U << 0) /* 1b */
+#define ULPOSC_RST_LSB (1U << 1) /* 1b */
+#define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */
+
+/* DRAMC_DPY_CLK_SW_CON_SEL (0x10006000+0x460) */
+#define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 0) /* 2b */
+#define SW_EMI_CLK_OFF_SEL_LSB (1U << 2) /* 2b */
+#define SW_DPY_MODE_SW_SEL_LSB (1U << 4) /* 2b */
+#define SW_DMSUS_OFF_SEL_LSB (1U << 6) /* 2b */
+#define SW_MEM_CK_OFF_SEL_LSB (1U << 8) /* 2b */
+#define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 10) /* 2b */
+#define SW_DPY_DLL_EN_SEL_LSB (1U << 12) /* 2b */
+#define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 14) /* 2b */
+#define SW_DPY_VREF_EN_SEL_LSB (1U << 16) /* 2b */
+#define SW_PHYPLL_EN_SEL_LSB (1U << 18) /* 2b */
+#define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 20) /* 2b */
+#define SEPERATE_PHY_PWR_SEL_LSB (1U << 23) /* 1b */
+#define SW_DMDRAMCSHU_ACK_SEL_LSB (1U << 24) /* 2b */
+#define SW_EMI_CLK_OFF_ACK_SEL_LSB (1U << 26) /* 2b */
+#define SW_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 28) /* 2b */
+#define SW_DRAMC_DFS_STA_SEL_LSB (1U << 30) /* 2b */
+
+/* DRAMC_DPY_CLK_SW_CON (0x10006000+0x464) */
+#define SW_DR_GATE_RETRY_EN_LSB (1U << 0) /* 2b */
+#define SW_EMI_CLK_OFF_LSB (1U << 2) /* 2b */
+#define SW_DPY_MODE_SW_LSB (1U << 4) /* 2b */
+#define SW_DMSUS_OFF_LSB (1U << 6) /* 2b */
+#define SW_MEM_CK_OFF_LSB (1U << 8) /* 2b */
+#define SW_DPY_2ND_DLL_EN_LSB (1U << 10) /* 2b */
+#define SW_DPY_DLL_EN_LSB (1U << 12) /* 2b */
+#define SW_DPY_DLL_CK_EN_LSB (1U << 14) /* 2b */
+#define SW_DPY_VREF_EN_LSB (1U << 16) /* 2b */
+#define SW_PHYPLL_EN_LSB (1U << 18) /* 2b */
+#define SW_DDRPHY_FB_CK_EN_LSB (1U << 20) /* 2b */
+#define SC_DR_SHU_EN_ACK_LSB (1U << 24) /* 2b */
+#define EMI_CLK_OFF_ACK_LSB (1U << 26) /* 2b */
+#define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 28) /* 2b */
+#define SC_DRAMC_DFS_STA_LSB (1U << 30) /* 2b */
+
+/* DRAMC_DPY_CLK_SW_CON_SEL2 (0x10006000+0x470) */
+#define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 0) /* 1b */
+#define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 1) /* 1b */
+#define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 2) /* 1b */
+#define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 3) /* 1b */
+#define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 4) /* 1b */
+#define SW_DR_SHU_EN_SEL_LSB (1U << 5) /* 1b */
+#define SW_DR_SHU_LEVEL_SEL_LSB (1U << 6) /* 1b */
+
+/* DRAMC_DPY_CLK_SW_CON2 (0x10006000+0x474) */
+#define SW_PHYPLL_SHU_EN_LSB (1U << 0) /* 1b */
+#define SW_PHYPLL2_SHU_EN_LSB (1U << 1) /* 1b */
+#define SW_PHYPLL_MODE_SW_LSB (1U << 2) /* 1b */
+#define SW_PHYPLL2_MODE_SW_LSB (1U << 3) /* 1b */
+#define SW_DR_SHORT_QUEUE_LSB (1U << 4) /* 1b */
+#define SW_DR_SHU_EN_LSB (1U << 5) /* 1b */
+#define SW_DR_SHU_LEVEL_LSB (1U << 6) /* 2b */
+#define SPM2MM_ULTRAREQ_LSB (1U << 8) /* 1b */
+#define SPM2MD_ULTRAREQ_LSB (1U << 9) /* 1b */
+#define SPM2MM_ULTRAACK_D2T_LSB (1U << 30) /* 1b */
+#define SPM2MD_ULTRAACK_D2T_LSB (1U << 31) /* 1b */
+
+/* SPM_SEMA_M0 (0x10006000+0x480) */
+#define SPM_SEMA_M0_LSB (1U << 0) /* 8b */
+
+/* SPM_SEMA_M1 (0x10006000+0x484) */
+#define SPM_SEMA_M1_LSB (1U << 0) /* 8b */
+
+/* SPM_SEMA_M2 (0x10006000+0x488) */
+#define SPM_SEMA_M2_LSB (1U << 0) /* 8b */
+
+/* SPM_SEMA_M3 (0x10006000+0x48C) */
+#define SPM_SEMA_M3_LSB (1U << 0) /* 8b */
+
+/* SPM_SEMA_M4 (0x10006000+0x490) */
+#define SPM_SEMA_M4_LSB (1U << 0) /* 8b */
+
+/* SPM_SEMA_M5 (0x10006000+0x494) */
+#define SPM_SEMA_M5_LSB (1U << 0) /* 8b */
+
+/* SPM_SEMA_M6 (0x10006000+0x498) */
+#define SPM_SEMA_M6_LSB (1U << 0) /* 8b */
+
+/* SPM_SEMA_M7 (0x10006000+0x49C) */
+#define SPM_SEMA_M7_LSB (1U << 0) /* 8b */
+
+/* SPM_SEMA_M8 (0x10006000+0x4A0) */
+#define SPM_SEMA_M8_LSB (1U << 0) /* 8b */
+
+/* SPM_SEMA_M9 (0x10006000+0x4A4) */
+#define SPM_SEMA_M9_LSB (1U << 0) /* 8b */
+
+/* SRAM_DREQ_ACK (0x10006000+0x4AC) */
+#define SRAM_DREQ_ACK_LSB (1U << 0) /* 16b */
+
+/* SRAM_DREQ_CON (0x10006000+0x4B0) */
+#define SRAM_DREQ_CON_LSB (1U << 0) /* 16b */
+
+/* SRAM_DREQ_CON_SET (0x10006000+0x4B4) */
+#define SRAM_DREQ_CON_SET_LSB (1U << 0) /* 16b */
+
+/* SRAM_DREQ_CON_CLR (0x10006000+0x4B8) */
+#define SRAM_DREQ_CON_CLR_LSB (1U << 0) /* 16b */
+
+/* MP0_CPU0_IRQ_MASK (0x10006000+0x500) */
+#define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */
+
+/* MP0_CPU1_IRQ_MASK (0x10006000+0x504) */
+#define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */
+
+/* MP0_CPU2_IRQ_MASK (0x10006000+0x508) */
+#define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */
+
+/* MP0_CPU3_IRQ_MASK (0x10006000+0x50C) */
+#define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */
+
+/* MP1_CPU0_IRQ_MASK (0x10006000+0x510) */
+#define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */
+
+/* MP1_CPU1_IRQ_MASK (0x10006000+0x514) */
+#define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */
+
+/* MP1_CPU2_IRQ_MASK (0x10006000+0x518) */
+#define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */
+
+/* MP1_CPU3_IRQ_MASK (0x10006000+0x51C) */
+#define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */
+
+/* MP0_CPU0_WFI_EN (0x10006000+0x530) */
+#define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */
+
+/* MP0_CPU1_WFI_EN (0x10006000+0x534) */
+#define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */
+
+/* MP0_CPU2_WFI_EN (0x10006000+0x538) */
+#define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */
+
+/* MP0_CPU3_WFI_EN (0x10006000+0x53C) */
+#define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */
+
+/* MP1_CPU0_WFI_EN (0x10006000+0x540) */
+#define MP1_CPU0_WFI_EN_LSB (1U << 0) /* 1b */
+
+/* MP1_CPU1_WFI_EN (0x10006000+0x544) */
+#define MP1_CPU1_WFI_EN_LSB (1U << 0) /* 1b */
+
+/* MP1_CPU2_WFI_EN (0x10006000+0x548) */
+#define MP1_CPU2_WFI_EN_LSB (1U << 0) /* 1b */
+
+/* MP1_CPU3_WFI_EN (0x10006000+0x54C) */
+#define MP1_CPU3_WFI_EN_LSB (1U << 0) /* 1b */
+
+/* CPU_PTPOD2_CON (0x10006000+0x560) */
+#define MP0_PTPOD2_FBB_EN_LSB (1U << 0) /* 1b */
+#define MP1_PTPOD2_FBB_EN_LSB (1U << 1) /* 1b */
+#define MP0_PTPOD2_SPARK_EN_LSB (1U << 2) /* 1b */
+#define MP1_PTPOD2_SPARK_EN_LSB (1U << 3) /* 1b */
+#define MP0_PTPOD2_FBB_ACK_LSB (1U << 4) /* 1b */
+#define MP1_PTPOD2_FBB_ACK_LSB (1U << 5) /* 1b */
+
+/* ROOT_CPUTOP_ADDR (0x10006000+0x570) */
+#define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */
+
+/* ROOT_CORE_ADDR (0x10006000+0x574) */
+#define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */
+
+/* CPU_SPARE_CON (0x10006000+0x580) */
+#define CPU_SPARE_CON_LSB (1U << 0) /* 32b */
+
+/* CPU_SPARE_CON_SET (0x10006000+0x584) */
+#define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */
+
+/* CPU_SPARE_CON_CLR (0x10006000+0x588) */
+#define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_FLAG (0x10006000+0x600) */
+#define SPM_SW_FLAG_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_DEBUG (0x10006000+0x604) */
+#define SPM_SW_DEBUG_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_RSV_0 (0x10006000+0x608) */
+#define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_RSV_1 (0x10006000+0x60C) */
+#define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_RSV_2 (0x10006000+0x610) */
+#define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_RSV_3 (0x10006000+0x614) */
+#define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_RSV_4 (0x10006000+0x618) */
+#define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_RSV_5 (0x10006000+0x61C) */
+#define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */
+
+/* SPM_RSV_CON (0x10006000+0x620) */
+#define SPM_RSV_CON_LSB (1U << 0) /* 16b */
+
+/* SPM_RSV_STA (0x10006000+0x624) */
+#define SPM_RSV_STA_LSB (1U << 0) /* 16b */
+
+/* SPM_PASR_DPD_0 (0x10006000+0x630) */
+#define SPM_PASR_DPD_0_LSB (1U << 0) /* 32b */
+
+/* SPM_PASR_DPD_1 (0x10006000+0x634) */
+#define SPM_PASR_DPD_1_LSB (1U << 0) /* 32b */
+
+/* SPM_PASR_DPD_2 (0x10006000+0x638) */
+#define SPM_PASR_DPD_2_LSB (1U << 0) /* 32b */
+
+/* SPM_PASR_DPD_3 (0x10006000+0x63C) */
+#define SPM_PASR_DPD_3_LSB (1U << 0) /* 32b */
+
+/* SPM_SPARE_CON (0x10006000+0x640) */
+#define SPM_SPARE_CON_LSB (1U << 0) /* 32b */
+
+/* SPM_SPARE_CON_SET (0x10006000+0x644) */
+#define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */
+
+/* SPM_SPARE_CON_CLR (0x10006000+0x648) */
+#define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_RSV_6 (0x10006000+0x64C) */
+#define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_RSV_7 (0x10006000+0x650) */
+#define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_RSV_8 (0x10006000+0x654) */
+#define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_RSV_9 (0x10006000+0x658) */
+#define SPM_SW_RSV_9_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_RSV_10 (0x10006000+0x65C) */
+#define SPM_SW_RSV_10_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_RSV_11 (0x10006000+0x660) */
+#define SPM_SW_RSV_11_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_RSV_12 (0x10006000+0x664) */
+#define SPM_SW_RSV_12_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_RSV_13 (0x10006000+0x668) */
+#define SPM_SW_RSV_13_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_RSV_14 (0x10006000+0x66C) */
+#define SPM_SW_RSV_14_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_RSV_15 (0x10006000+0x670) */
+#define SPM_SW_RSV_15_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_RSV_16 (0x10006000+0x674) */
+#define SPM_SW_RSV_16_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_RSV_17 (0x10006000+0x678) */
+#define SPM_SW_RSV_17_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_RSV_18 (0x10006000+0x67C) */
+#define SPM_SW_RSV_18_LSB (1U << 0) /* 32b */
+
+/* SPM_SW_RSV_19 (0x10006000+0x680) */
+#define SPM_SW_RSV_19_LSB (1U << 0) /* 32b */
+
+/* SW_CRTL_EVENT (0x10006000+0x690) */
+#define SW_CRTL_EVENT_ON_LSB (1U << 0) /* 1b */
+
+#define SPM_PROJECT_CODE 0xb16
+
+#define SPM_REGWR_EN (1U << 0)
+#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16)
+
+#define SPM_CPU_PDN_DIS (1U << 0)
+#define SPM_INFRA_PDN_DIS (1U << 1)
+#define SPM_DDRPHY_PDN_DIS (1U << 2)
+#define SPM_DUALVCORE_PDN_DIS (1U << 3)
+#define SPM_PASR_DIS (1U << 4)
+#define SPM_DPD_DIS (1U << 5)
+#define SPM_SODI_DIS (1U << 6)
+#define SPM_MEMPLL_RESET (1U << 7)
+#define SPM_MAINPLL_PDN_DIS (1U << 8)
+#define SPM_CPU_DVS_DIS (1U << 9)
+#define SPM_CPU_DORMANT (1U << 10)
+#define SPM_EXT_VSEL_GPIO103 (1U << 11)
+#define SPM_DDR_HIGH_SPEED (1U << 12)
+#define SPM_OPT (1U << 13)
+
+#define POWER_ON_VAL1_DEF 0x15820
+#define PCM_FSM_STA_DEF 0x48490
+#define PCM_END_FSM_STA_DEF 0x08490
+#define PCM_END_FSM_STA_MASK 0x3fff0
+#define PCM_HANDSHAKE_SEND1 0xbeefbeef
+
+#define PCM_WDT_TIMEOUT (30 * 32768)
+#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT)
+
+#define CON0_PCM_KICK (1U << 0)
+#define CON0_IM_KICK (1U << 1)
+#define CON0_IM_SLEEP_DVS (1U << 3)
+#define CON0_PCM_SW_RESET (1U << 15)
+#define CON0_CFG_KEY (SPM_PROJECT_CODE << 16)
+
+#define CON1_IM_SLAVE (1U << 0)
+#define CON1_MIF_APBEN (1U << 3)
+#define CON1_PCM_TIMER_EN (1U << 5)
+#define CON1_IM_NONRP_EN (1U << 6)
+#define CON1_PCM_WDT_EN (1U << 8)
+#define CON1_PCM_WDT_WAKE_MODE (1U << 9)
+#define CON1_SPM_SRAM_SLP_B (1U << 10)
+#define CON1_SPM_SRAM_ISO_B (1U << 11)
+#define CON1_EVENT_LOCK_EN (1U << 12)
+#define CON1_CFG_KEY (SPM_PROJECT_CODE << 16)
+
+#define PCM_PWRIO_EN_R0 (1U << 0)
+#define PCM_PWRIO_EN_R7 (1U << 7)
+#define PCM_RF_SYNC_R0 (1U << 16)
+#define PCM_RF_SYNC_R2 (1U << 18)
+#define PCM_RF_SYNC_R6 (1U << 22)
+#define PCM_RF_SYNC_R7 (1U << 23)
+
+#define CC_SYSCLK0_EN_0 (1U << 0)
+#define CC_SYSCLK0_EN_1 (1U << 1)
+#define CC_SYSCLK1_EN_0 (1U << 2)
+#define CC_SYSCLK1_EN_1 (1U << 3)
+#define CC_SYSSETTLE_SEL (1U << 4)
+#define CC_LOCK_INFRA_DCM (1U << 5)
+#define CC_SRCLKENA_MASK_0 (1U << 6)
+#define CC_CXO32K_RM_EN_MD1 (1U << 9)
+#define CC_CXO32K_RM_EN_MD2 (1U << 10)
+#define CC_CLKSQ1_SEL (1U << 12)
+#define CC_DISABLE_DORM_PWR (1U << 14)
+#define CC_MD32_DCM_EN (1U << 18)
+
+#define WFI_OP_AND 1
+#define WFI_OP_OR 0
+
+#define WAKE_MISC_PCM_TIMER (1U << 19)
+#define WAKE_MISC_CPU_WAKE (1U << 20)
+
+/* define WAKE_SRC_XXX */
+#define WAKE_SRC_SPM_MERGE (1 << 0)
+#define WAKE_SRC_KP (1 << 2)
+#define WAKE_SRC_WDT (1 << 3)
+#define WAKE_SRC_GPT (1 << 4)
+#define WAKE_SRC_EINT (1 << 6)
+#define WAKE_SRC_LOW_BAT (1 << 9)
+#define WAKE_SRC_MD32 (1 << 10)
+#define WAKE_SRC_USB_CD (1 << 14)
+#define WAKE_SRC_USB_PDN (1 << 15)
+#define WAKE_SRC_AFE (1 << 20)
+#define WAKE_SRC_THERM (1 << 21)
+#define WAKE_SRC_SYSPWREQ (1 << 24)
+#define WAKE_SRC_SEJ (1 << 27)
+#define WAKE_SRC_ALL_MD32 (1 << 28)
+#define WAKE_SRC_CPU_IRQ (1 << 29)
+
+#define spm_read(addr) mmio_read_32(addr)
+#define spm_write(addr, val) mmio_write_32(addr, val)
+
+#endif /* SPM_H */
diff --git a/plat/mediatek/mt8183/plat_dcm.c b/plat/mediatek/mt8183/plat_dcm.c
new file mode 100644
index 0000000..8ee77f1
--- /dev/null
+++ b/plat/mediatek/mt8183/plat_dcm.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <lib/bakery_lock.h>
+#include <drivers/console.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <plat_dcm.h>
+#include <plat_private.h>
+#include <plat_dcm.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+#include <mtk_plat_common.h>
+
+#define PWR_STATUS (SPM_BASE + 0x180)
+
+uint64_t plat_dcm_mcsi_a_addr;
+uint32_t plat_dcm_mcsi_a_val;
+static int plat_dcm_init_type;
+static unsigned int dcm_big_core_cnt;
+int plat_dcm_initiated;
+
+#define PWR_STA_BIG_MP_MASK (0x1 << 15)
+
+DEFINE_BAKERY_LOCK(dcm_lock);
+
+void dcm_lock_init(void)
+{
+ bakery_lock_init(&dcm_lock);
+}
+
+void dcm_lock_get(void)
+{
+ bakery_lock_get(&dcm_lock);
+}
+
+void dcm_lock_release(void)
+{
+ bakery_lock_release(&dcm_lock);
+}
+
+void plat_dcm_mcsi_a_backup(void)
+{
+}
+
+void plat_dcm_mcsi_a_restore(void)
+{
+}
+
+void plat_dcm_rgu_enable(void)
+{
+}
+
+void plat_dcm_big_core_sync(short on)
+{
+ /* Check if Big cluster power is existed */
+ if (!(mmio_read_32(PWR_STATUS) & PWR_STA_BIG_MP_MASK))
+ return;
+
+ if (on) {
+ mmio_write_32(MP2_SYNC_DCM,
+ (mmio_read_32(MP2_SYNC_DCM) & ~MP2_SYNC_DCM_MASK)
+ | MP2_SYNC_DCM_ON);
+ dcm_big_core_cnt++;
+ } else
+ mmio_write_32(MP2_SYNC_DCM,
+ (mmio_read_32(MP2_SYNC_DCM) & ~MP2_SYNC_DCM_MASK)
+ | MP2_SYNC_DCM_OFF);
+}
+
+void plat_dcm_restore_cluster_on(unsigned long mpidr)
+{
+ unsigned long cluster_id =
+ (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS;
+
+ switch (cluster_id) {
+ case 0x1:
+ dcm_lock_get();
+ if (plat_dcm_init_type & BIG_CORE_DCM_TYPE)
+ plat_dcm_big_core_sync(1);
+ else
+ plat_dcm_big_core_sync(0);
+ dcm_lock_release();
+ break;
+ default:
+ break;
+ }
+}
+
+void plat_dcm_msg_handler(uint64_t x1)
+{
+ plat_dcm_init_type = x1 & ALL_DCM_TYPE;
+}
+
+unsigned long plat_dcm_get_enabled_cnt(uint64_t type)
+{
+ switch (type) {
+ case BIG_CORE_DCM_TYPE:
+ return dcm_big_core_cnt;
+ default:
+ return 0;
+ }
+}
+
+void plat_dcm_init(void)
+{
+ dcm_lock_init();
+}
diff --git a/plat/mediatek/mt8183/plat_mt_gic.c b/plat/mediatek/mt8183/plat_mt_gic.c
index 2144379..ccb72be 100644
--- a/plat/mediatek/mt8183/plat_mt_gic.c
+++ b/plat/mediatek/mt8183/plat_mt_gic.c
@@ -1,14 +1,14 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <assert.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/arm/gicv3.h>
#include <bl31/interrupt_mgmt.h>
-#include <../drivers/arm/gic/v3/gicv3_private.h>
#include <mt_gic_v3.h>
#include <mtk_plat_common.h>
#include "plat_private.h"
@@ -21,13 +21,9 @@
uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
-/*
- * We save and restore the GICv3 context on system suspend. Allocate the
- * data in the designated EL3 Secure carve-out memory
- */
-gicv3_redist_ctx_t rdist_ctx __section("arm_el3_tzc_dram");
-gicv3_dist_ctx_t dist_ctx __section("arm_el3_tzc_dram");
-
+/* we save and restore the GICv3 context on system suspend */
+gicv3_redist_ctx_t rdist_ctx;
+gicv3_dist_ctx_t dist_ctx;
static unsigned int mt_mpidr_to_core_pos(u_register_t mpidr)
{
@@ -42,27 +38,6 @@
.mpidr_to_core_pos = mt_mpidr_to_core_pos,
};
-void setup_int_schedule_mode(enum irq_schedule_mode mode,
- unsigned int active_cpu)
-{
- assert(mode <= HW_MODE);
- assert(active_cpu <= 0xFF);
-
- if (mode == HW_MODE) {
- mmio_write_32(GIC_INT_MASK,
- (mmio_read_32(GIC_INT_MASK) & ~(GIC500_ACTIVE_SEL_MASK))
- | (0x1 << GIC500_ACTIVE_SEL_SHIFT));
- } else if (mode == SW_MODE) {
- mmio_write_32(GIC_INT_MASK,
- (mmio_read_32(GIC_INT_MASK) & ~(GIC500_ACTIVE_SEL_MASK)));
- }
-
- mmio_write_32(GIC_INT_MASK,
- (mmio_read_32(GIC_INT_MASK) & ~(GIC500_ACTIVE_CPU_MASK))
- | (active_cpu << GIC500_ACTIVE_CPU_SHIFT));
- return;
-}
-
void clear_sec_pol_ctl_en(void)
{
unsigned int i;
@@ -85,7 +60,6 @@
gicv3_rdistif_init(plat_my_core_pos());
gicv3_cpuif_enable(plat_my_core_pos());
- setup_int_schedule_mode(SW_MODE, 0xf);
clear_sec_pol_ctl_en();
}
@@ -94,14 +68,6 @@
gicv3_set_interrupt_pending(irq, plat_my_core_pos());
}
-uint32_t mt_gic_get_pending(uint32_t irq)
-{
- uint32_t bit = 1 << (irq % 32);
-
- return (mmio_read_32(gicv3_driver_data->gicd_base +
- GICD_ISPENDR + irq / 32 * 4) & bit) ? 1 : 0;
-}
-
void mt_gic_cpuif_enable(void)
{
gicv3_cpuif_enable(plat_my_core_pos());
diff --git a/plat/mediatek/mt8183/plat_pm.c b/plat/mediatek/mt8183/plat_pm.c
index dd54d70..83c8d4c 100644
--- a/plat/mediatek/mt8183/plat_pm.c
+++ b/plat/mediatek/mt8183/plat_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,25 +15,151 @@
/* mediatek platform specific headers */
#include <platform_def.h>
#include <scu.h>
+#include <mt_gic_v3.h>
#include <mtk_plat_common.h>
-#include <power_tracer.h>
+#include <mtgpio.h>
+#include <mtspmc.h>
+#include <plat_dcm.h>
+#include <plat_debug.h>
+#include <plat_params.h>
#include <plat_private.h>
+#include <power_tracer.h>
+#include <pmic.h>
+#include <rtc.h>
+
+#define MTK_LOCAL_STATE_OFF 2
+
+static uintptr_t secure_entrypoint;
+
+static void mp1_L2_desel_config(void)
+{
+ mmio_write_64(MCUCFG_BASE + 0x2200, 0x2092c820);
+
+ dsb();
+}
+
+static int plat_mtk_power_domain_on(unsigned long mpidr)
+{
+ int cpu = MPIDR_AFFLVL0_VAL(mpidr);
+ int cluster = MPIDR_AFFLVL1_VAL(mpidr);
+
+ INFO("%s():%d: mpidr: %lx, c.c: %d.%d\n",
+ __func__, __LINE__, mpidr, cluster, cpu);
+
+ /* power on cluster */
+ if (!spm_get_cluster_powerstate(cluster)) {
+ spm_poweron_cluster(cluster);
+ if (cluster == 1) {
+ l2c_parity_check_setup();
+ circular_buffer_setup();
+ mp1_L2_desel_config();
+ mt_gic_sync_dcm_disable();
+ }
+ }
+
+ /* init cpu reset arch as AARCH64 */
+ mcucfg_init_archstate(cluster, cpu, 1);
+ mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint);
+
+ spm_poweron_cpu(cluster, cpu);
+
+ return PSCI_E_SUCCESS;
+}
+
+static void plat_mtk_power_domain_off(const psci_power_state_t *state)
+{
+ uint64_t mpidr = read_mpidr();
+ int cpu = MPIDR_AFFLVL0_VAL(mpidr);
+ int cluster = MPIDR_AFFLVL1_VAL(mpidr);
+
+ INFO("%s():%d: c.c: %d.%d\n", __func__, __LINE__, cluster, cpu);
+
+ /* Prevent interrupts from spuriously waking up this cpu */
+ mt_gic_cpuif_disable();
+
+ spm_enable_cpu_auto_off(cluster, cpu);
+
+ if (state->pwr_domain_state[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF) {
+ if (cluster == 1)
+ mt_gic_sync_dcm_enable();
+
+ plat_mtk_cci_disable();
+ spm_enable_cluster_auto_off(cluster);
+ }
+
+ spm_set_cpu_power_off(cluster, cpu);
+}
+
+static void plat_mtk_power_domain_on_finish(const psci_power_state_t *state)
+{
+ uint64_t mpidr = read_mpidr();
+ int cpu = MPIDR_AFFLVL0_VAL(mpidr);
+ int cluster = MPIDR_AFFLVL1_VAL(mpidr);
+
+ INFO("%s():%d: c.c: %d.%d\n", __func__, __LINE__, cluster, cpu);
+
+ assert(state->pwr_domain_state[MPIDR_AFFLVL0] == MTK_LOCAL_STATE_OFF);
+
+ if (state->pwr_domain_state[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF) {
+ enable_scu(mpidr);
+
+ /* Enable coherency if this cluster was off */
+ plat_mtk_cci_enable();
+ /* Enable big core dcm if this cluster was on */
+ plat_dcm_restore_cluster_on(mpidr);
+ /* Enable rgu dcm if this cluster was off */
+ plat_dcm_rgu_enable();
+ }
+
+ spm_disable_cpu_auto_off(cluster, cpu);
+
+ /* Enable the gic cpu interface */
+ mt_gic_pcpu_init();
+ mt_gic_cpuif_enable();
+}
+
+/*******************************************************************************
+ * MTK handlers to shutdown/reboot the system
+ ******************************************************************************/
+static void __dead2 plat_mtk_system_off(void)
+{
+ INFO("MTK System Off\n");
+
+ rtc_power_off_sequence();
+ wk_pmic_enable_sdn_delay();
+ pmic_power_off();
+
+ wfi();
+ ERROR("MTK System Off: operation not handled.\n");
+ panic();
+}
+
+static void __dead2 plat_mtk_system_reset(void)
+{
+ struct bl_aux_gpio_info *gpio_reset = plat_get_mtk_gpio_reset();
+
+ INFO("MTK System Reset\n");
+
+ mt_set_gpio_out(gpio_reset->index, gpio_reset->polarity);
+
+ wfi();
+ ERROR("MTK System Reset: operation not handled.\n");
+ panic();
+}
/*******************************************************************************
* MTK_platform handler called when an affinity instance is about to be turned
* on. The level and mpidr determine the affinity instance.
******************************************************************************/
-static uintptr_t secure_entrypoint;
-
static const plat_psci_ops_t plat_plat_pm_ops = {
.cpu_standby = NULL,
- .pwr_domain_on = NULL,
- .pwr_domain_on_finish = NULL,
- .pwr_domain_off = NULL,
+ .pwr_domain_on = plat_mtk_power_domain_on,
+ .pwr_domain_on_finish = plat_mtk_power_domain_on_finish,
+ .pwr_domain_off = plat_mtk_power_domain_off,
.pwr_domain_suspend = NULL,
.pwr_domain_suspend_finish = NULL,
- .system_off = NULL,
- .system_reset = NULL,
+ .system_off = plat_mtk_system_off,
+ .system_reset = plat_mtk_system_reset,
.validate_power_state = NULL,
.get_sys_suspend_power_state = NULL,
};
diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk
index f0a598a..09fd133 100644
--- a/plat/mediatek/mt8183/platform.mk
+++ b/plat/mediatek/mt8183/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2019, MediaTek Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -9,6 +9,10 @@
PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
-I${MTK_PLAT_SOC}/drivers/ \
+ -I${MTK_PLAT_SOC}/drivers/spmc/ \
+ -I${MTK_PLAT_SOC}/drivers/gpio/ \
+ -I${MTK_PLAT_SOC}/drivers/pmic/ \
+ -I${MTK_PLAT_SOC}/drivers/rtc/ \
-I${MTK_PLAT_SOC}/include/
PLAT_BL_COMMON_SOURCES := lib/xlat_tables/aarch64/xlat_tables.c \
@@ -27,17 +31,26 @@
drivers/delay_timer/generic_delay_timer.c \
drivers/gpio/gpio.c \
drivers/ti/uart/aarch64/16550_console.S \
+ lib/bl_aux_params/bl_aux_params.c \
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a73.S \
plat/common/plat_gicv3.c \
${MTK_PLAT}/common/mtk_plat_common.c \
+ ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init.c \
+ ${MTK_PLAT}/common/drivers/rtc/rtc_common.c \
+ ${MTK_PLAT}/common/params_setup.c \
${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
${MTK_PLAT_SOC}/aarch64/platform_common.c \
${MTK_PLAT_SOC}/drivers/mcsi/mcsi.c \
+ ${MTK_PLAT_SOC}/drivers/pmic/pmic.c \
+ ${MTK_PLAT_SOC}/drivers/rtc/rtc.c \
+ ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \
+ ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
${MTK_PLAT_SOC}/plat_pm.c \
${MTK_PLAT_SOC}/plat_topology.c \
${MTK_PLAT_SOC}/plat_mt_gic.c \
+ ${MTK_PLAT_SOC}/plat_dcm.c \
${MTK_PLAT_SOC}/bl31_plat_setup.c \
${MTK_PLAT_SOC}/plat_debug.c \
${MTK_PLAT_SOC}/scu.c
@@ -57,3 +70,5 @@
MACH_MT8183 := 1
$(eval $(call add_define,MACH_MT8183))
+include lib/coreboot/coreboot.mk
+
diff --git a/plat/meson/gxbb/gxbb_def.h b/plat/meson/gxbb/gxbb_def.h
deleted file mode 100644
index 3e27097..0000000
--- a/plat/meson/gxbb/gxbb_def.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef GXBB_DEF_H
-#define GXBB_DEF_H
-
-#include <lib/utils_def.h>
-
-/*******************************************************************************
- * System oscillator
- ******************************************************************************/
-#define GXBB_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */
-
-/*******************************************************************************
- * Memory regions
- ******************************************************************************/
-#define GXBB_NSDRAM0_BASE UL(0x01000000)
-#define GXBB_NSDRAM0_SIZE UL(0x0F000000)
-
-#define GXBB_NSDRAM1_BASE UL(0x10000000)
-#define GXBB_NSDRAM1_SIZE UL(0x00100000)
-
-#define BL31_BASE UL(0x10100000)
-#define BL31_SIZE UL(0x000C0000)
-#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
-
-/* Shared memory used for SMC services */
-#define GXBB_SHARE_MEM_INPUT_BASE UL(0x100FE000)
-#define GXBB_SHARE_MEM_OUTPUT_BASE UL(0x100FF000)
-
-#define GXBB_SEC_DEVICE0_BASE UL(0xC0000000)
-#define GXBB_SEC_DEVICE0_SIZE UL(0x09000000)
-
-#define GXBB_SEC_DEVICE1_BASE UL(0xD0040000)
-#define GXBB_SEC_DEVICE1_SIZE UL(0x00008000)
-
-#define GXBB_TZRAM_BASE UL(0xD9000000)
-#define GXBB_TZRAM_SIZE UL(0x00014000)
-/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */
-
-/* Mailboxes */
-#define GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800)
-#define GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00)
-#define GXBB_PSCI_MAILBOX_BASE UL(0xD9013F00)
-
-#define GXBB_TZROM_BASE UL(0xD9040000)
-#define GXBB_TZROM_SIZE UL(0x00010000)
-
-#define GXBB_SEC_DEVICE2_BASE UL(0xDA000000)
-#define GXBB_SEC_DEVICE2_SIZE UL(0x00200000)
-
-#define GXBB_SEC_DEVICE3_BASE UL(0xDA800000)
-#define GXBB_SEC_DEVICE3_SIZE UL(0x00200000)
-
-/*******************************************************************************
- * GIC-400 and interrupt handling related constants
- ******************************************************************************/
-#define GXBB_GICD_BASE UL(0xC4301000)
-#define GXBB_GICC_BASE UL(0xC4302000)
-
-#define IRQ_SEC_PHY_TIMER 29
-
-#define IRQ_SEC_SGI_0 8
-#define IRQ_SEC_SGI_1 9
-#define IRQ_SEC_SGI_2 10
-#define IRQ_SEC_SGI_3 11
-#define IRQ_SEC_SGI_4 12
-#define IRQ_SEC_SGI_5 13
-#define IRQ_SEC_SGI_6 14
-#define IRQ_SEC_SGI_7 15
-
-/*******************************************************************************
- * UART definitions
- ******************************************************************************/
-#define GXBB_UART0_AO_BASE UL(0xC81004C0)
-#define GXBB_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ
-#define GXBB_UART_BAUDRATE U(115200)
-
-/*******************************************************************************
- * Memory-mapped I/O Registers
- ******************************************************************************/
-#define GXBB_AO_TIMESTAMP_CNTL UL(0xC81000B4)
-
-#define GXBB_SYS_CPU_CFG7 UL(0xC8834664)
-
-#define GXBB_AO_RTI_STATUS_REG3 UL(0xDA10001C)
-
-#define GXBB_HIU_MAILBOX_SET_0 UL(0xDA83C404)
-#define GXBB_HIU_MAILBOX_STAT_0 UL(0xDA83C408)
-#define GXBB_HIU_MAILBOX_CLR_0 UL(0xDA83C40C)
-#define GXBB_HIU_MAILBOX_SET_3 UL(0xDA83C428)
-#define GXBB_HIU_MAILBOX_STAT_3 UL(0xDA83C42C)
-#define GXBB_HIU_MAILBOX_CLR_3 UL(0xDA83C430)
-
-/*******************************************************************************
- * System Monitor Call IDs and arguments
- ******************************************************************************/
-#define GXBB_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020)
-#define GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021)
-
-#define GXBB_SM_EFUSE_READ U(0x82000030)
-#define GXBB_SM_EFUSE_USER_MAX U(0x82000033)
-
-#define GXBB_SM_JTAG_ON U(0x82000040)
-#define GXBB_SM_JTAG_OFF U(0x82000041)
-
-#define GXBB_JTAG_STATE_ON U(0)
-#define GXBB_JTAG_STATE_OFF U(1)
-
-#define GXBB_JTAG_M3_AO U(0)
-#define GXBB_JTAG_M3_EE U(1)
-#define GXBB_JTAG_A53_AO U(2)
-#define GXBB_JTAG_A53_EE U(3)
-
-#endif /* GXBB_DEF_H */
diff --git a/plat/meson/gxbb/gxbb_efuse.c b/plat/meson/gxbb/gxbb_efuse.c
deleted file mode 100644
index edea542..0000000
--- a/plat/meson/gxbb/gxbb_efuse.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include "gxbb_private.h"
-
-#define EFUSE_BASE 0x140
-#define EFUSE_SIZE 0xC0
-
-uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size)
-{
- if ((uint64_t)(offset + size) > (uint64_t)EFUSE_SIZE)
- return 0;
-
- return scpi_efuse_read(dst, offset + EFUSE_BASE, size);
-}
-
-uint64_t gxbb_efuse_user_max(void)
-{
- return EFUSE_SIZE;
-}
diff --git a/plat/meson/gxbb/gxbb_mhu.c b/plat/meson/gxbb/gxbb_mhu.c
deleted file mode 100644
index 903ef41..0000000
--- a/plat/meson/gxbb/gxbb_mhu.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <platform_def.h>
-
-#include <lib/bakery_lock.h>
-#include <lib/mmio.h>
-
-static DEFINE_BAKERY_LOCK(mhu_lock);
-
-void mhu_secure_message_start(void)
-{
- bakery_lock_get(&mhu_lock);
-
- while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0)
- ;
-}
-
-void mhu_secure_message_send(uint32_t msg)
-{
- mmio_write_32(GXBB_HIU_MAILBOX_SET_3, msg);
-
- while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0)
- ;
-}
-
-uint32_t mhu_secure_message_wait(void)
-{
- uint32_t val;
-
- do {
- val = mmio_read_32(GXBB_HIU_MAILBOX_STAT_0);
- } while (val == 0);
-
- return val;
-}
-
-void mhu_secure_message_end(void)
-{
- mmio_write_32(GXBB_HIU_MAILBOX_CLR_0, 0xFFFFFFFF);
-
- bakery_lock_release(&mhu_lock);
-}
-
-void mhu_secure_init(void)
-{
- bakery_lock_init(&mhu_lock);
-
- mmio_write_32(GXBB_HIU_MAILBOX_CLR_3, 0xFFFFFFFF);
-}
diff --git a/plat/meson/gxbb/gxbb_private.h b/plat/meson/gxbb/gxbb_private.h
deleted file mode 100644
index 910a42c..0000000
--- a/plat/meson/gxbb/gxbb_private.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef GXBB_PRIVATE_H
-#define GXBB_PRIVATE_H
-
-#include <stdint.h>
-
-/* Utility functions */
-unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr);
-void gxbb_console_init(void);
-void gxbb_setup_page_tables(void);
-
-/* MHU functions */
-void mhu_secure_message_start(void);
-void mhu_secure_message_send(uint32_t msg);
-uint32_t mhu_secure_message_wait(void);
-void mhu_secure_message_end(void);
-void mhu_secure_init(void);
-
-/* SCPI functions */
-void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state,
- uint32_t cluster_state, uint32_t css_state);
-uint32_t scpi_sys_power_state(uint64_t system_state);
-void scpi_jtag_set_state(uint32_t state, uint8_t select);
-uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size);
-void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1,
- uint32_t arg2, uint32_t arg3);
-
-/* Peripherals */
-void gxbb_thermal_unknown(void);
-uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size);
-uint64_t gxbb_efuse_user_max(void);
-
-#endif /* GXBB_PRIVATE_H */
diff --git a/plat/meson/gxbb/gxbb_scpi.c b/plat/meson/gxbb/gxbb_scpi.c
deleted file mode 100644
index 83eeda2..0000000
--- a/plat/meson/gxbb/gxbb_scpi.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <string.h>
-
-#include <platform_def.h>
-
-#include <lib/mmio.h>
-#include <plat/common/platform.h>
-
-#include "gxbb_private.h"
-
-#define SIZE_SHIFT 20
-#define SIZE_MASK 0x1FF
-
-/*
- * Note: The Amlogic SCP firmware uses the legacy SCPI protocol.
- */
-#define SCPI_CMD_SET_CSS_POWER_STATE 0x04
-#define SCPI_CMD_SET_SYS_POWER_STATE 0x08
-
-#define SCPI_CMD_JTAG_SET_STATE 0xC0
-#define SCPI_CMD_EFUSE_READ 0xC2
-
-static inline uint32_t scpi_cmd(uint32_t command, uint32_t size)
-{
- return command | (size << SIZE_SHIFT);
-}
-
-void scpi_secure_message_send(uint32_t command, uint32_t size)
-{
- mhu_secure_message_send(scpi_cmd(command, size));
-}
-
-uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out)
-{
- uint32_t response = mhu_secure_message_wait();
-
- size_t size = (response >> SIZE_SHIFT) & SIZE_MASK;
-
- response &= ~(SIZE_MASK << SIZE_SHIFT);
-
- if (size_out != NULL)
- *size_out = size;
-
- if (message_out != NULL)
- *message_out = (void *)GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD;
-
- return response;
-}
-
-void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state,
- uint32_t cluster_state, uint32_t css_state)
-{
- uint32_t state = (mpidr & 0x0F) | /* CPU ID */
- ((mpidr & 0xF00) >> 4) | /* Cluster ID */
- (cpu_state << 8) |
- (cluster_state << 12) |
- (css_state << 16);
-
- mhu_secure_message_start();
- mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, state);
- mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4));
- mhu_secure_message_wait();
- mhu_secure_message_end();
-}
-
-uint32_t scpi_sys_power_state(uint64_t system_state)
-{
- uint32_t *response;
- size_t size;
-
- mhu_secure_message_start();
- mmio_write_8(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state);
- mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1));
- scpi_secure_message_receive((void *)&response, &size);
- mhu_secure_message_end();
-
- return *response;
-}
-
-void scpi_jtag_set_state(uint32_t state, uint8_t select)
-{
- assert(state <= GXBB_JTAG_STATE_OFF);
-
- if (select > GXBB_JTAG_A53_EE) {
- WARN("BL31: Invalid JTAG select (0x%x).\n", select);
- return;
- }
-
- mhu_secure_message_start();
- mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD,
- (state << 8) | (uint32_t)select);
- mhu_secure_message_send(scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4));
- mhu_secure_message_wait();
- mhu_secure_message_end();
-}
-
-uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size)
-{
- uint32_t *response;
- size_t resp_size;
-
- if (size > 0x1FC)
- return 0;
-
- mhu_secure_message_start();
- mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, base);
- mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size);
- mhu_secure_message_send(scpi_cmd(SCPI_CMD_EFUSE_READ, 8));
- scpi_secure_message_receive((void *)&response, &resp_size);
- mhu_secure_message_end();
-
- /*
- * response[0] is the size of the response message.
- * response[1 ... N] are the contents.
- */
- if (*response != 0)
- memcpy(dst, response + 1, *response);
-
- return *response;
-}
-
-void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1,
- uint32_t arg2, uint32_t arg3)
-{
- mhu_secure_message_start();
- mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0);
- mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1);
- mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2);
- mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3);
- mhu_secure_message_send(scpi_cmd(0xC3, 16));
- mhu_secure_message_wait();
- mhu_secure_message_end();
-}
diff --git a/plat/meson/gxbb/gxbb_sip_svc.c b/plat/meson/gxbb/gxbb_sip_svc.c
deleted file mode 100644
index 63c7dba..0000000
--- a/plat/meson/gxbb/gxbb_sip_svc.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <common/runtime_svc.h>
-#include <lib/mmio.h>
-
-#include "gxbb_private.h"
-
-/*******************************************************************************
- * This function is responsible for handling all SiP calls
- ******************************************************************************/
-static uintptr_t gxbb_sip_handler(uint32_t smc_fid,
- u_register_t x1, u_register_t x2,
- u_register_t x3, u_register_t x4,
- void *cookie, void *handle,
- u_register_t flags)
-{
- switch (smc_fid) {
-
- case GXBB_SM_GET_SHARE_MEM_INPUT_BASE:
- SMC_RET1(handle, GXBB_SHARE_MEM_INPUT_BASE);
-
- case GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE:
- SMC_RET1(handle, GXBB_SHARE_MEM_OUTPUT_BASE);
-
- case GXBB_SM_EFUSE_READ:
- {
- void *dst = (void *)GXBB_SHARE_MEM_OUTPUT_BASE;
- uint64_t ret = gxbb_efuse_read(dst, (uint32_t)x1, x2);
-
- SMC_RET1(handle, ret);
- }
- case GXBB_SM_EFUSE_USER_MAX:
- SMC_RET1(handle, gxbb_efuse_user_max());
-
- case GXBB_SM_JTAG_ON:
- scpi_jtag_set_state(GXBB_JTAG_STATE_ON, x1);
- SMC_RET1(handle, 0);
-
- case GXBB_SM_JTAG_OFF:
- scpi_jtag_set_state(GXBB_JTAG_STATE_OFF, x1);
- SMC_RET1(handle, 0);
-
- default:
- ERROR("BL31: Unhandled SIP SMC: 0x%08x\n", smc_fid);
- break;
- }
-
- SMC_RET1(handle, SMC_UNK);
-}
-
-DECLARE_RT_SVC(
- gxbb_sip_handler,
-
- OEN_SIP_START,
- OEN_SIP_END,
- SMC_TYPE_FAST,
- NULL,
- gxbb_sip_handler
-);
diff --git a/plat/meson/gxbb/platform.mk b/plat/meson/gxbb/platform.mk
deleted file mode 100644
index 9e65040..0000000
--- a/plat/meson/gxbb/platform.mk
+++ /dev/null
@@ -1,69 +0,0 @@
-#
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-include lib/xlat_tables_v2/xlat_tables.mk
-
-PLAT_INCLUDES := -Iplat/meson/gxbb/include
-
-GXBB_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v2/gicv2_main.c \
- drivers/arm/gic/v2/gicv2_helpers.c \
- plat/common/plat_gicv2.c
-
-PLAT_BL_COMMON_SOURCES := drivers/meson/console/aarch64/meson_console.S \
- plat/meson/gxbb/gxbb_common.c \
- plat/meson/gxbb/gxbb_topology.c \
- ${XLAT_TABLES_LIB_SRCS}
-
-BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
- plat/common/plat_psci_common.c \
- plat/meson/gxbb/aarch64/gxbb_helpers.S \
- plat/meson/gxbb/gxbb_bl31_setup.c \
- plat/meson/gxbb/gxbb_efuse.c \
- plat/meson/gxbb/gxbb_mhu.c \
- plat/meson/gxbb/gxbb_pm.c \
- plat/meson/gxbb/gxbb_scpi.c \
- plat/meson/gxbb/gxbb_sip_svc.c \
- plat/meson/gxbb/gxbb_thermal.c \
- ${GXBB_GIC_SOURCES}
-
-# Tune compiler for Cortex-A53
-ifeq ($(notdir $(CC)),armclang)
- TF_CFLAGS_aarch64 += -mcpu=cortex-a53
-else ifneq ($(findstring clang,$(notdir $(CC))),)
- TF_CFLAGS_aarch64 += -mcpu=cortex-a53
-else
- TF_CFLAGS_aarch64 += -mtune=cortex-a53
-endif
-
-# Build config flags
-# ------------------
-
-# Enable all errata workarounds for Cortex-A53
-ERRATA_A53_826319 := 1
-ERRATA_A53_835769 := 1
-ERRATA_A53_836870 := 1
-ERRATA_A53_843419 := 1
-ERRATA_A53_855873 := 1
-
-WORKAROUND_CVE_2017_5715 := 0
-
-# Have different sections for code and rodata
-SEPARATE_CODE_AND_RODATA := 1
-
-# Use Coherent memory
-USE_COHERENT_MEM := 1
-
-# Verify build config
-# -------------------
-
-ifneq (${RESET_TO_BL31}, 0)
- $(error Error: gxbb needs RESET_TO_BL31=0)
-endif
-
-ifeq (${ARCH},aarch32)
- $(error Error: AArch32 not supported on gxbb)
-endif
diff --git a/plat/meson/gxl/aarch64/gxl_helpers.S b/plat/meson/gxl/aarch64/gxl_helpers.S
deleted file mode 100644
index 760d6c4..0000000
--- a/plat/meson/gxl/aarch64/gxl_helpers.S
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <assert_macros.S>
-#include <platform_def.h>
-
- .globl plat_crash_console_flush
- .globl plat_crash_console_init
- .globl plat_crash_console_putc
- .globl platform_mem_init
- .globl plat_is_my_cpu_primary
- .globl plat_my_core_pos
- .globl plat_reset_handler
- .globl plat_gxbb_calc_core_pos
-
- /* -----------------------------------------------------
- * unsigned int plat_my_core_pos(void);
- * -----------------------------------------------------
- */
-func plat_my_core_pos
- mrs x0, mpidr_el1
- b plat_gxbb_calc_core_pos
-endfunc plat_my_core_pos
-
- /* -----------------------------------------------------
- * unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr);
- * -----------------------------------------------------
- */
-func plat_gxbb_calc_core_pos
- and x0, x0, #MPIDR_CPU_MASK
- ret
-endfunc plat_gxbb_calc_core_pos
-
- /* -----------------------------------------------------
- * unsigned int plat_is_my_cpu_primary(void);
- * -----------------------------------------------------
- */
-func plat_is_my_cpu_primary
- mrs x0, mpidr_el1
- and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
- cmp x0, #GXBB_PRIMARY_CPU
- cset w0, eq
- ret
-endfunc plat_is_my_cpu_primary
-
- /* ---------------------------------------------
- * void platform_mem_init(void);
- * ---------------------------------------------
- */
-func platform_mem_init
- ret
-endfunc platform_mem_init
-
- /* ---------------------------------------------
- * int plat_crash_console_init(void)
- * ---------------------------------------------
- */
-func plat_crash_console_init
- mov_imm x0, GXBB_UART0_AO_BASE
- mov_imm x1, GXBB_UART0_AO_CLK_IN_HZ
- mov_imm x2, GXBB_UART_BAUDRATE
- b console_meson_init
-endfunc plat_crash_console_init
-
- /* ---------------------------------------------
- * int plat_crash_console_putc(int c)
- * Clobber list : x1, x2
- * ---------------------------------------------
- */
-func plat_crash_console_putc
- mov_imm x1, GXBB_UART0_AO_BASE
- b console_meson_core_putc
-endfunc plat_crash_console_putc
-
- /* ---------------------------------------------
- * int plat_crash_console_flush()
- * Out : return -1 on error else return 0.
- * Clobber list : x0, x1
- * ---------------------------------------------
- */
-func plat_crash_console_flush
- mov_imm x0, GXBB_UART0_AO_BASE
- b console_meson_core_flush
-endfunc plat_crash_console_flush
-
- /* ---------------------------------------------
- * void plat_reset_handler(void);
- * ---------------------------------------------
- */
-func plat_reset_handler
- ret
-endfunc plat_reset_handler
diff --git a/plat/meson/gxl/gxl_def.h b/plat/meson/gxl/gxl_def.h
deleted file mode 100644
index 089fa8d..0000000
--- a/plat/meson/gxl/gxl_def.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef GXBB_DEF_H
-#define GXBB_DEF_H
-
-#include <lib/utils_def.h>
-
-/*******************************************************************************
- * System oscillator
- ******************************************************************************/
-#define GXBB_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */
-
-/*******************************************************************************
- * Memory regions
- ******************************************************************************/
-#define GXBB_NSDRAM0_BASE UL(0x01000000)
-#define GXBB_NSDRAM0_SIZE UL(0x0F000000)
-
-#define GXBB_NSDRAM1_BASE UL(0x10000000)
-#define GXBB_NSDRAM1_SIZE UL(0x00100000)
-
-#define BL31_BASE UL(0x05100000)
-#define BL31_SIZE UL(0x000C0000)
-#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
-
-/* Shared memory used for SMC services */
-#define GXBB_SHARE_MEM_INPUT_BASE UL(0x050FE000)
-#define GXBB_SHARE_MEM_OUTPUT_BASE UL(0x050FF000)
-
-#define GXBB_SEC_DEVICE0_BASE UL(0xC0000000)
-#define GXBB_SEC_DEVICE0_SIZE UL(0x09000000)
-
-#define GXBB_SEC_DEVICE1_BASE UL(0xD0040000)
-#define GXBB_SEC_DEVICE1_SIZE UL(0x00008000)
-
-#define GXBB_TZRAM_BASE UL(0xD9000000)
-#define GXBB_TZRAM_SIZE UL(0x00014000)
-/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */
-
-/* Mailboxes */
-#define GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800)
-#define GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00)
-#define GXBB_PSCI_MAILBOX_BASE UL(0xD9013F00)
-
-// * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3)
-// * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) *
-// * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) *
-
-#define GXBB_TZROM_BASE UL(0xD9040000)
-#define GXBB_TZROM_SIZE UL(0x00010000)
-
-#define GXBB_SEC_DEVICE2_BASE UL(0xDA000000)
-#define GXBB_SEC_DEVICE2_SIZE UL(0x00200000)
-
-#define GXBB_SEC_DEVICE3_BASE UL(0xDA800000)
-#define GXBB_SEC_DEVICE3_SIZE UL(0x00200000)
-
-/*******************************************************************************
- * GIC-400 and interrupt handling related constants
- ******************************************************************************/
-#define GXBB_GICD_BASE UL(0xC4301000)
-#define GXBB_GICC_BASE UL(0xC4302000)
-
-#define IRQ_SEC_PHY_TIMER 29
-
-#define IRQ_SEC_SGI_0 8
-#define IRQ_SEC_SGI_1 9
-#define IRQ_SEC_SGI_2 10
-#define IRQ_SEC_SGI_3 11
-#define IRQ_SEC_SGI_4 12
-#define IRQ_SEC_SGI_5 13
-#define IRQ_SEC_SGI_6 14
-#define IRQ_SEC_SGI_7 15
-
-/*******************************************************************************
- * UART definitions
- ******************************************************************************/
-#define GXBB_UART0_AO_BASE UL(0xC81004C0)
-#define GXBB_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ
-#define GXBB_UART_BAUDRATE U(115200)
-
-/*******************************************************************************
- * Memory-mapped I/O Registers
- ******************************************************************************/
-#define GXBB_AO_TIMESTAMP_CNTL UL(0xC81000B4)
-
-#define GXBB_SYS_CPU_CFG7 UL(0xC8834664)
-
-#define GXBB_AO_RTI_STATUS_REG3 UL(0xDA10001C)
-#define GXBB_AO_RTI_SCP_STAT UL(0xDA10023C)
-#define GXBB_AO_RTI_SCP_READY_OFF U(0x14)
-#define GXBB_A0_RTI_SCP_READY_MASK U(3)
-#define GXBB_AO_RTI_SCP_IS_READY(v) \
- ((((v) >> GXBB_AO_RTI_SCP_READY_OFF) & \
- GXBB_A0_RTI_SCP_READY_MASK) == GXBB_A0_RTI_SCP_READY_MASK)
-
-#define GXBB_HIU_MAILBOX_SET_0 UL(0xDA83C404)
-#define GXBB_HIU_MAILBOX_STAT_0 UL(0xDA83C408)
-#define GXBB_HIU_MAILBOX_CLR_0 UL(0xDA83C40C)
-#define GXBB_HIU_MAILBOX_SET_3 UL(0xDA83C428)
-#define GXBB_HIU_MAILBOX_STAT_3 UL(0xDA83C42C)
-#define GXBB_HIU_MAILBOX_CLR_3 UL(0xDA83C430)
-
-/*******************************************************************************
- * System Monitor Call IDs and arguments
- ******************************************************************************/
-#define GXBB_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020)
-#define GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021)
-
-#define GXBB_SM_EFUSE_READ U(0x82000030)
-#define GXBB_SM_EFUSE_USER_MAX U(0x82000033)
-
-#define GXBB_SM_JTAG_ON U(0x82000040)
-#define GXBB_SM_JTAG_OFF U(0x82000041)
-
-#define GXBB_JTAG_STATE_ON U(0)
-#define GXBB_JTAG_STATE_OFF U(1)
-
-#define GXBB_JTAG_M3_AO U(0)
-#define GXBB_JTAG_M3_EE U(1)
-#define GXBB_JTAG_A53_AO U(2)
-#define GXBB_JTAG_A53_EE U(3)
-
-#endif /* GXBB_DEF_H */
diff --git a/plat/meson/gxl/gxl_efuse.c b/plat/meson/gxl/gxl_efuse.c
deleted file mode 100644
index b17d1b8..0000000
--- a/plat/meson/gxl/gxl_efuse.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include "gxl_private.h"
-
-#define EFUSE_BASE 0x140
-#define EFUSE_SIZE 0xC0
-
-uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size)
-{
- if ((uint64_t)(offset + size) > (uint64_t)EFUSE_SIZE)
- return 0;
-
- return scpi_efuse_read(dst, offset + EFUSE_BASE, size);
-}
-
-uint64_t gxbb_efuse_user_max(void)
-{
- return EFUSE_SIZE;
-}
diff --git a/plat/meson/gxl/gxl_mhu.c b/plat/meson/gxl/gxl_mhu.c
deleted file mode 100644
index 4c1d5b6..0000000
--- a/plat/meson/gxl/gxl_mhu.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <lib/bakery_lock.h>
-#include <lib/mmio.h>
-#include <platform_def.h>
-
-static DEFINE_BAKERY_LOCK(mhu_lock);
-
-void mhu_secure_message_start(void)
-{
- bakery_lock_get(&mhu_lock);
-
- while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0)
- ;
-}
-
-void mhu_secure_message_send(uint32_t msg)
-{
- mmio_write_32(GXBB_HIU_MAILBOX_SET_3, msg);
-
- while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0)
- ;
-}
-
-uint32_t mhu_secure_message_wait(void)
-{
- uint32_t val;
-
- do {
- val = mmio_read_32(GXBB_HIU_MAILBOX_STAT_0);
- } while (val == 0);
-
- return val;
-}
-
-void mhu_secure_message_end(void)
-{
- mmio_write_32(GXBB_HIU_MAILBOX_CLR_0, 0xFFFFFFFF);
-
- bakery_lock_release(&mhu_lock);
-}
-
-void mhu_secure_init(void)
-{
- bakery_lock_init(&mhu_lock);
-
- mmio_write_32(GXBB_HIU_MAILBOX_CLR_3, 0xFFFFFFFF);
-}
diff --git a/plat/meson/gxl/gxl_pm.c b/plat/meson/gxl/gxl_pm.c
deleted file mode 100644
index 4a5d26e..0000000
--- a/plat/meson/gxl/gxl_pm.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch_helpers.h>
-#include <assert.h>
-#include <drivers/console.h>
-#include <common/debug.h>
-#include <errno.h>
-#include <drivers/arm/gicv2.h>
-#include <lib/mmio.h>
-#include <plat/common/platform.h>
-#include <platform_def.h>
-#include <lib/psci/psci.h>
-
-#include "gxl_private.h"
-
-#define SCPI_POWER_ON 0
-#define SCPI_POWER_RETENTION 1
-#define SCPI_POWER_OFF 3
-
-#define SCPI_SYSTEM_SHUTDOWN 0
-#define SCPI_SYSTEM_REBOOT 1
-
-static uintptr_t gxbb_sec_entrypoint;
-static volatile uint32_t gxbb_cpu0_go;
-
-static void gxl_pm_set_reset_addr(u_register_t mpidr, uint64_t value)
-{
- unsigned int core = plat_gxbb_calc_core_pos(mpidr);
- uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4);
-
- mmio_write_64(cpu_mailbox_addr, value);
-}
-
-static void gxl_pm_reset(u_register_t mpidr)
-{
- unsigned int core = plat_gxbb_calc_core_pos(mpidr);
- uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4) + 8;
-
- mmio_write_32(cpu_mailbox_addr, 0);
-}
-
-static void __dead2 gxbb_system_reset(void)
-{
- INFO("BL31: PSCI_SYSTEM_RESET\n");
-
- u_register_t mpidr = read_mpidr_el1();
- uint32_t status = mmio_read_32(GXBB_AO_RTI_STATUS_REG3);
- int ret;
-
- NOTICE("BL31: Reboot reason: 0x%x\n", status);
-
- status &= 0xFFFF0FF0;
-
- console_flush();
-
- mmio_write_32(GXBB_AO_RTI_STATUS_REG3, status);
-
- ret = scpi_sys_power_state(SCPI_SYSTEM_REBOOT);
-
- if (ret != 0) {
- ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %i\n", ret);
- panic();
- }
-
- gxl_pm_reset(mpidr);
-
- wfi();
-
- ERROR("BL31: PSCI_SYSTEM_RESET: Operation not handled\n");
- panic();
-}
-
-static void __dead2 gxbb_system_off(void)
-{
- INFO("BL31: PSCI_SYSTEM_OFF\n");
-
- u_register_t mpidr = read_mpidr_el1();
- int ret;
-
- ret = scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
-
- if (ret != 0) {
- ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %i\n", ret);
- panic();
- }
-
- gxl_pm_set_reset_addr(mpidr, 0);
- gxl_pm_reset(mpidr);
-
- wfi();
-
- ERROR("BL31: PSCI_SYSTEM_OFF: Operation not handled\n");
- panic();
-}
-
-static int32_t gxbb_pwr_domain_on(u_register_t mpidr)
-{
- unsigned int core = plat_gxbb_calc_core_pos(mpidr);
-
- /* CPU0 can't be turned OFF, emulate it with a WFE loop */
- if (core == GXBB_PRIMARY_CPU) {
- VERBOSE("BL31: Releasing CPU0 from wait loop...\n");
-
- gxbb_cpu0_go = 1;
- flush_dcache_range((uintptr_t)&gxbb_cpu0_go,
- sizeof(gxbb_cpu0_go));
- dsb();
- isb();
-
- sev();
-
- return PSCI_E_SUCCESS;
- }
-
- gxl_pm_set_reset_addr(mpidr, gxbb_sec_entrypoint);
- scpi_set_css_power_state(mpidr,
- SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON);
- dmbsy();
- sev();
-
- return PSCI_E_SUCCESS;
-}
-
-static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state)
-{
- unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1());
-
- assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
- PLAT_LOCAL_STATE_OFF);
-
- if (core == GXBB_PRIMARY_CPU) {
- gxbb_cpu0_go = 0;
- flush_dcache_range((uintptr_t)&gxbb_cpu0_go,
- sizeof(gxbb_cpu0_go));
- dsb();
- isb();
- }
-
- gicv2_pcpu_distif_init();
- gicv2_cpuif_enable();
-}
-
-static void gxbb_pwr_domain_off(const psci_power_state_t *target_state)
-{
- u_register_t mpidr = read_mpidr_el1();
- unsigned int core = plat_gxbb_calc_core_pos(mpidr);
-
- gicv2_cpuif_disable();
-
- /* CPU0 can't be turned OFF, emulate it with a WFE loop */
- if (core == GXBB_PRIMARY_CPU)
- return;
-
- scpi_set_css_power_state(mpidr,
- SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON);
-}
-
-static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t
- *target_state)
-{
- u_register_t mpidr = read_mpidr_el1();
- unsigned int core = plat_gxbb_calc_core_pos(mpidr);
-
- /* CPU0 can't be turned OFF, emulate it with a WFE loop */
- if (core == GXBB_PRIMARY_CPU) {
- VERBOSE("BL31: CPU0 entering wait loop...\n");
-
- while (gxbb_cpu0_go == 0)
- wfe();
-
- VERBOSE("BL31: CPU0 resumed.\n");
-
- /*
- * Because setting CPU0's warm reset entrypoint through PSCI
- * mailbox and/or mmio mapped RVBAR (0xda834650) does not seem
- * to work, jump to it manually.
- * In order to avoid an assert, mmu has to be disabled.
- */
- disable_mmu_el3();
- ((void(*)(void))gxbb_sec_entrypoint)();
- }
-
- dsbsy();
- gxl_pm_set_reset_addr(mpidr, 0);
- gxl_pm_reset(mpidr);
-
- for (;;)
- wfi();
-}
-
-/*******************************************************************************
- * Platform handlers and setup function.
- ******************************************************************************/
-static const plat_psci_ops_t gxbb_ops = {
- .pwr_domain_on = gxbb_pwr_domain_on,
- .pwr_domain_on_finish = gxbb_pwr_domain_on_finish,
- .pwr_domain_off = gxbb_pwr_domain_off,
- .pwr_domain_pwr_down_wfi = gxbb_pwr_domain_pwr_down_wfi,
- .system_off = gxbb_system_off,
- .system_reset = gxbb_system_reset,
-};
-
-int plat_setup_psci_ops(uintptr_t sec_entrypoint,
- const plat_psci_ops_t **psci_ops)
-{
- gxbb_sec_entrypoint = sec_entrypoint;
- *psci_ops = &gxbb_ops;
- gxbb_cpu0_go = 0;
- return 0;
-}
diff --git a/plat/meson/gxl/gxl_private.h b/plat/meson/gxl/gxl_private.h
deleted file mode 100644
index 913cbf6..0000000
--- a/plat/meson/gxl/gxl_private.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef GXBB_PRIVATE_H
-#define GXBB_PRIVATE_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-/* Utility functions */
-unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr);
-void gxbb_console_init(void);
-void gxbb_setup_page_tables(void);
-
-/* MHU functions */
-void mhu_secure_message_start(void);
-void mhu_secure_message_send(uint32_t msg);
-uint32_t mhu_secure_message_wait(void);
-void mhu_secure_message_end(void);
-void mhu_secure_init(void);
-
-/* SCPI functions */
-void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state,
- uint32_t cluster_state, uint32_t css_state);
-uint32_t scpi_sys_power_state(uint64_t system_state);
-void scpi_jtag_set_state(uint32_t state, uint8_t select);
-uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size);
-void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1,
- uint32_t arg2, uint32_t arg3);
-void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send);
-
-/* Peripherals */
-void gxbb_thermal_unknown(void);
-uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size);
-uint64_t gxbb_efuse_user_max(void);
-
-#endif /* GXBB_PRIVATE_H */
diff --git a/plat/meson/gxl/gxl_scpi.c b/plat/meson/gxl/gxl_scpi.c
deleted file mode 100644
index 13d6524..0000000
--- a/plat/meson/gxl/gxl_scpi.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <lib/mmio.h>
-#include <plat/common/platform.h>
-#include <platform_def.h>
-#include <string.h>
-#include <crypto/sha_dma.h>
-
-#include "gxl_private.h"
-
-#define SIZE_SHIFT 20
-#define SIZE_MASK 0x1FF
-#define SIZE_FWBLK 0x200UL
-
-/*
- * Note: The Amlogic SCP firmware uses the legacy SCPI protocol.
- */
-#define SCPI_CMD_SET_CSS_POWER_STATE 0x04
-#define SCPI_CMD_SET_SYS_POWER_STATE 0x08
-
-#define SCPI_CMD_JTAG_SET_STATE 0xC0
-#define SCPI_CMD_EFUSE_READ 0xC2
-
-#define SCPI_CMD_COPY_FW 0xd4
-#define SCPI_CMD_SET_FW_ADDR 0xd3
-#define SCPI_CMD_FW_SIZE 0xd2
-
-static inline uint32_t scpi_cmd(uint32_t command, uint32_t size)
-{
- return command | (size << SIZE_SHIFT);
-}
-
-static void scpi_secure_message_send(uint32_t command, uint32_t size)
-{
- mhu_secure_message_send(scpi_cmd(command, size));
-}
-
-uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out)
-{
- uint32_t response = mhu_secure_message_wait();
-
- size_t size = (response >> SIZE_SHIFT) & SIZE_MASK;
-
- response &= ~(SIZE_MASK << SIZE_SHIFT);
-
- if (size_out != NULL)
- *size_out = size;
-
- if (message_out != NULL)
- *message_out = (void *)GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD;
-
- return response;
-}
-
-void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state,
- uint32_t cluster_state, uint32_t css_state)
-{
- uint32_t state = (mpidr & 0x0F) | /* CPU ID */
- ((mpidr & 0xF00) >> 4) | /* Cluster ID */
- (cpu_state << 8) |
- (cluster_state << 12) |
- (css_state << 16);
-
- mhu_secure_message_start();
- mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, state);
- mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4));
- mhu_secure_message_wait();
- mhu_secure_message_end();
-}
-
-uint32_t scpi_sys_power_state(uint64_t system_state)
-{
- uint32_t *response;
- size_t size;
-
- mhu_secure_message_start();
- mmio_write_8(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state);
- mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1));
- scpi_secure_message_receive((void *)&response, &size);
- mhu_secure_message_end();
-
- return *response;
-}
-
-void scpi_jtag_set_state(uint32_t state, uint8_t select)
-{
- assert(state <= GXBB_JTAG_STATE_OFF);
-
- if (select > GXBB_JTAG_A53_EE) {
- WARN("BL31: Invalid JTAG select (0x%x).\n", select);
- return;
- }
-
- mhu_secure_message_start();
- mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD,
- (state << 8) | (uint32_t)select);
- mhu_secure_message_send(scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4));
- mhu_secure_message_wait();
- mhu_secure_message_end();
-}
-
-uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size)
-{
- uint32_t *response;
- size_t resp_size;
-
- if (size > 0x1FC)
- return 0;
-
- mhu_secure_message_start();
- mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, base);
- mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size);
- mhu_secure_message_send(scpi_cmd(SCPI_CMD_EFUSE_READ, 8));
- scpi_secure_message_receive((void *)&response, &resp_size);
- mhu_secure_message_end();
-
- /*
- * response[0] is the size of the response message.
- * response[1 ... N] are the contents.
- */
- if (*response != 0)
- memcpy(dst, response + 1, *response);
-
- return *response;
-}
-
-void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1,
- uint32_t arg2, uint32_t arg3)
-{
- mhu_secure_message_start();
- mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0);
- mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1);
- mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2);
- mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3);
- mhu_secure_message_send(scpi_cmd(0xC3, 16));
- mhu_secure_message_wait();
- mhu_secure_message_end();
-}
-
-static inline void scpi_copy_scp_data(uint8_t *data, size_t len)
-{
- void *dst = (void *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD;
- size_t sz;
-
- mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, len);
- scpi_secure_message_send(SCPI_CMD_FW_SIZE, len);
- mhu_secure_message_wait();
-
- for (sz = 0; sz < len; sz += SIZE_FWBLK) {
- memcpy(dst, data + sz, MIN(SIZE_FWBLK, len - sz));
- mhu_secure_message_send(SCPI_CMD_COPY_FW);
- }
-}
-
-static inline void scpi_set_scp_addr(uint64_t addr, size_t len)
-{
- volatile uint64_t *dst = (uint64_t *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD;
-
- /*
- * It is ok as GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD is mapped as
- * non cachable
- */
- *dst = addr;
- scpi_secure_message_send(SCPI_CMD_SET_FW_ADDR, sizeof(addr));
- mhu_secure_message_wait();
-
- mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, len);
- scpi_secure_message_send(SCPI_CMD_FW_SIZE, len);
- mhu_secure_message_wait();
-}
-
-static inline void scpi_send_fw_hash(uint8_t hash[], size_t len)
-{
- void *dst = (void *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD;
-
- memcpy(dst, hash, len);
- mhu_secure_message_send(0xd0);
- mhu_secure_message_send(0xd1);
- mhu_secure_message_send(0xd5);
- mhu_secure_message_end();
-}
-
-/**
- * Upload a FW to SCP.
- *
- * @param addr: firmware data address
- * @param size: size of firmware
- * @param send: If set, actually copy the firmware in SCP memory otherwise only
- * send the firmware address.
- */
-void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send)
-{
- struct asd_ctx ctx;
-
- asd_sha_init(&ctx, ASM_SHA256);
- asd_sha_update(&ctx, (void *)addr, size);
- asd_sha_finalize(&ctx);
-
- mhu_secure_message_start();
- if (send == 0)
- scpi_set_scp_addr(addr, size);
- else
- scpi_copy_scp_data((void *)addr, size);
-
- scpi_send_fw_hash(ctx.digest, sizeof(ctx.digest));
-}
diff --git a/plat/meson/gxl/gxl_sip_svc.c b/plat/meson/gxl/gxl_sip_svc.c
deleted file mode 100644
index 74fbc80..0000000
--- a/plat/meson/gxl/gxl_sip_svc.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <lib/mmio.h>
-#include <platform_def.h>
-#include <common/runtime_svc.h>
-#include <stdint.h>
-
-#include "gxl_private.h"
-
-/*******************************************************************************
- * This function is responsible for handling all SiP calls
- ******************************************************************************/
-static uintptr_t gxbb_sip_handler(uint32_t smc_fid,
- u_register_t x1, u_register_t x2,
- u_register_t x3, u_register_t x4,
- void *cookie, void *handle,
- u_register_t flags)
-{
- switch (smc_fid) {
-
- case GXBB_SM_GET_SHARE_MEM_INPUT_BASE:
- SMC_RET1(handle, GXBB_SHARE_MEM_INPUT_BASE);
-
- case GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE:
- SMC_RET1(handle, GXBB_SHARE_MEM_OUTPUT_BASE);
-
- case GXBB_SM_EFUSE_READ:
- {
- void *dst = (void *)GXBB_SHARE_MEM_OUTPUT_BASE;
- uint64_t ret = gxbb_efuse_read(dst, (uint32_t)x1, x2);
-
- SMC_RET1(handle, ret);
- }
- case GXBB_SM_EFUSE_USER_MAX:
- SMC_RET1(handle, gxbb_efuse_user_max());
-
- case GXBB_SM_JTAG_ON:
- scpi_jtag_set_state(GXBB_JTAG_STATE_ON, x1);
- SMC_RET1(handle, 0);
-
- case GXBB_SM_JTAG_OFF:
- scpi_jtag_set_state(GXBB_JTAG_STATE_OFF, x1);
- SMC_RET1(handle, 0);
-
- default:
- ERROR("BL31: Unhandled SIP SMC: 0x%08x\n", smc_fid);
- break;
- }
-
- SMC_RET1(handle, SMC_UNK);
-}
-
-DECLARE_RT_SVC(
- gxbb_sip_handler,
-
- OEN_SIP_START,
- OEN_SIP_END,
- SMC_TYPE_FAST,
- NULL,
- gxbb_sip_handler
-);
diff --git a/plat/meson/gxl/gxl_thermal.c b/plat/meson/gxl/gxl_thermal.c
deleted file mode 100644
index 3af1c6d..0000000
--- a/plat/meson/gxl/gxl_thermal.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include "gxl_private.h"
-
-static int32_t modules_initialized = -1;
-
-/*******************************************************************************
- * Unknown commands related to something thermal-related
- ******************************************************************************/
-void gxbb_thermal_unknown(void)
-{
- uint16_t ret;
-
- if (modules_initialized == -1) {
- scpi_efuse_read(&ret, 0, 2);
- modules_initialized = ret;
- }
-
- scpi_unknown_thermal(10, 2, /* thermal */
- 13, 1); /* thermalver */
-}
diff --git a/plat/meson/gxl/gxl_topology.c b/plat/meson/gxl/gxl_topology.c
deleted file mode 100644
index cca3ead..0000000
--- a/plat/meson/gxl/gxl_topology.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <platform_def.h>
-#include <stdint.h>
-
-#include "gxl_private.h"
-
-/* The power domain tree descriptor */
-static unsigned char power_domain_tree_desc[] = {
- /* Number of root nodes */
- PLATFORM_CLUSTER_COUNT,
- /* Number of children for the first node */
- PLATFORM_CLUSTER0_CORE_COUNT
-};
-
-/*******************************************************************************
- * This function returns the ARM default topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
- return power_domain_tree_desc;
-}
-
-/*******************************************************************************
- * This function implements a part of the critical interface between the psci
- * generic layer and the platform that allows the former to query the platform
- * to convert an MPIDR to a unique linear index. An error code (-1) is returned
- * in case the MPIDR is invalid.
- ******************************************************************************/
-int plat_core_pos_by_mpidr(u_register_t mpidr)
-{
- unsigned int cluster_id, cpu_id;
-
- mpidr &= MPIDR_AFFINITY_MASK;
- if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
- return -1;
-
- cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
- cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
-
- if (cluster_id >= PLATFORM_CLUSTER_COUNT)
- return -1;
-
- if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
- return -1;
-
- return plat_gxbb_calc_core_pos(mpidr);
-}
diff --git a/plat/meson/gxl/include/plat_macros.S b/plat/meson/gxl/include/plat_macros.S
deleted file mode 100644
index c721c21..0000000
--- a/plat/meson/gxl/include/plat_macros.S
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLAT_MACROS_S
-#define PLAT_MACROS_S
-
-#include <drivers/arm/gicv2.h>
-#include <platform_def.h>
-
-.section .rodata.gic_reg_name, "aS"
-
-gicc_regs:
- .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
-gicd_pend_reg:
- .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
-newline:
- .asciz "\n"
-spacer:
- .asciz ":\t\t0x"
-
- /* ---------------------------------------------
- * The below required platform porting macro
- * prints out relevant GIC and CCI registers
- * whenever an unhandled exception is taken in
- * BL31.
- * Clobbers: x0 - x10, x16, x17, sp
- * ---------------------------------------------
- */
- .macro plat_crash_print_regs
-
- /* GICC registers */
-
- mov_imm x17, GXBB_GICC_BASE
-
- adr x6, gicc_regs
- ldr w8, [x17, #GICC_HPPIR]
- ldr w9, [x17, #GICC_AHPPIR]
- ldr w10, [x17, #GICC_CTLR]
- bl str_in_crash_buf_print
-
- /* GICD registers */
-
- mov_imm x16, GXBB_GICD_BASE
-
- add x7, x16, #GICD_ISPENDR
- adr x4, gicd_pend_reg
- bl asm_print_str
-
-gicd_ispendr_loop:
- sub x4, x7, x16
- cmp x4, #0x280
- b.eq exit_print_gic_regs
- bl asm_print_hex
-
- adr x4, spacer
- bl asm_print_str
-
- ldr x4, [x7], #8
- bl asm_print_hex
-
- adr x4, newline
- bl asm_print_str
- b gicd_ispendr_loop
-exit_print_gic_regs:
-
- .endm
-
-#endif /* PLAT_MACROS_S */
diff --git a/plat/meson/gxl/platform.mk b/plat/meson/gxl/platform.mk
deleted file mode 100644
index a788e96..0000000
--- a/plat/meson/gxl/platform.mk
+++ /dev/null
@@ -1,87 +0,0 @@
-#
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-include lib/xlat_tables_v2/xlat_tables.mk
-
-DOIMAGEPATH ?= tools/meson
-DOIMAGETOOL ?= ${DOIMAGEPATH}/doimage
-
-PLAT_INCLUDES := -Iinclude/drivers/meson/ \
- -Iinclude/drivers/meson/gxl \
- -Iplat/meson/gxl/include
-
-GXBB_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v2/gicv2_main.c \
- drivers/arm/gic/v2/gicv2_helpers.c \
- plat/common/plat_gicv2.c
-
-PLAT_BL_COMMON_SOURCES := drivers/meson/console/aarch64/meson_console.S \
- plat/meson/gxl/gxl_common.c \
- plat/meson/gxl/gxl_topology.c \
- ${XLAT_TABLES_LIB_SRCS}
-
-BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
- plat/common/plat_psci_common.c \
- plat/meson/gxl/aarch64/gxl_helpers.S \
- plat/meson/gxl/gxl_bl31_setup.c \
- plat/meson/gxl/gxl_efuse.c \
- plat/meson/gxl/gxl_mhu.c \
- plat/meson/gxl/gxl_pm.c \
- plat/meson/gxl/gxl_scpi.c \
- plat/meson/gxl/gxl_sip_svc.c \
- plat/meson/gxl/gxl_thermal.c \
- drivers/meson/gxl/crypto/sha_dma.c \
- ${GXBB_GIC_SOURCES}
-
-# Tune compiler for Cortex-A53
-ifeq ($(notdir $(CC)),armclang)
- TF_CFLAGS_aarch64 += -mcpu=cortex-a53
-else ifneq ($(findstring clang,$(notdir $(CC))),)
- TF_CFLAGS_aarch64 += -mcpu=cortex-a53
-else
- TF_CFLAGS_aarch64 += -mtune=cortex-a53
-endif
-
-# Build config flags
-# ------------------
-
-# Enable all errata workarounds for Cortex-A53
-ERRATA_A53_855873 := 1
-ERRATA_A53_819472 := 1
-ERRATA_A53_824069 := 1
-ERRATA_A53_827319 := 1
-
-WORKAROUND_CVE_2017_5715 := 0
-
-# Have different sections for code and rodata
-SEPARATE_CODE_AND_RODATA := 1
-
-# Use Coherent memory
-USE_COHERENT_MEM := 1
-
-# Verify build config
-# -------------------
-
-ifneq (${RESET_TO_BL31}, 0)
- $(error Error: gxl needs RESET_TO_BL31=0)
-endif
-
-ifeq (${ARCH},aarch32)
- $(error Error: AArch32 not supported on gxl)
-endif
-
-all: ${BUILD_PLAT}/bl31.img
-distclean realclean clean: cleanimage
-
-cleanimage:
- ${Q}${MAKE} -C ${DOIMAGEPATH} clean
-
-${DOIMAGETOOL}:
- ${Q}${MAKE} -C ${DOIMAGEPATH}
-
-${BUILD_PLAT}/bl31.img: ${BUILD_PLAT}/bl31.bin ${DOIMAGETOOL}
- ${DOIMAGETOOL} ${BUILD_PLAT}/bl31.bin ${BUILD_PLAT}/bl31.img
-
diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index a3ef5e1..2f31906 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -360,17 +361,15 @@
if ((phys_base > vmem_end_old) || (video_mem_base > vmem_end_new)) {
tegra_clear_videomem(video_mem_base,
- (uint32_t)video_mem_size_mb << 20U);
+ video_mem_size_mb << 20U);
} else {
if (video_mem_base < phys_base) {
non_overlap_area_size = phys_base - video_mem_base;
- tegra_clear_videomem(video_mem_base,
- (uint32_t)non_overlap_area_size);
+ tegra_clear_videomem(video_mem_base, non_overlap_area_size);
}
if (vmem_end_old > vmem_end_new) {
non_overlap_area_size = vmem_end_old - vmem_end_new;
- tegra_clear_videomem(vmem_end_new,
- (uint32_t)non_overlap_area_size);
+ tegra_clear_videomem(vmem_end_new, non_overlap_area_size);
}
}
diff --git a/plat/renesas/rcar/include/rcar_def.h b/plat/renesas/rcar/include/rcar_def.h
index a60f9b6..0ffbfe9 100644
--- a/plat/renesas/rcar/include/rcar_def.h
+++ b/plat/renesas/rcar/include/rcar_def.h
@@ -221,9 +221,11 @@
#define CPG_PLL0CR (CPG_BASE + 0x00D8U)
#define CPG_PLL2CR (CPG_BASE + 0x002CU)
#define CPG_PLL4CR (CPG_BASE + 0x01F4U)
+#define CPG_CPGWPCR (CPG_BASE + 0x0904U)
/* RST Registers */
#define RST_BASE (0xE6160000U)
#define RST_WDTRSTCR (RST_BASE + 0x0054U)
+#define RST_MODEMR (RST_BASE + 0x0060U)
#define WDTRSTCR_PASSWORD (0xA55A0000U)
#define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U)
/* MFIS Registers */
@@ -267,11 +269,15 @@
#define MIDR_CA57 (0x0D07U << MIDR_PN_SHIFT)
#define MIDR_CA53 (0x0D03U << MIDR_PN_SHIFT)
/* for SuspendToRAM */
-#define GPIO_BASE (0xE6050000U)
-#define GPIO_INDT1 (GPIO_BASE + 0x100CU)
+#define GPIO_BASE (0xE6050000U)
+#define GPIO_INDT1 (GPIO_BASE + 0x100CU)
+#define GPIO_INDT3 (GPIO_BASE + 0x300CU)
#define GPIO_INDT6 (GPIO_BASE + 0x540CU)
-#define RCAR_COLD_BOOT (0x00U)
-#define RCAR_WARM_BOOT (0x01U)
+#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U)
+#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U)
+#define GPIO_OUTDT6 (GPIO_BASE + 0x5408U)
+#define RCAR_COLD_BOOT (0x00U)
+#define RCAR_WARM_BOOT (0x01U)
#if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
#define KEEP10_MAGIC (0x55U)
#endif
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index 8ff6c43..ab5d95d 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,6 +11,7 @@
#include <drivers/generic_delay_timer.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables.h>
+#include <plat_ipi.h>
#include <plat_private.h>
#include <plat/common/platform.h>
@@ -325,6 +326,9 @@
void zynqmp_config_setup(void)
{
+ /* Configure IPI data for ZynqMP */
+ zynqmp_ipi_config_table_init();
+
zynqmp_print_platform_name();
generic_delay_timer_init();
}
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index bd7bc08..c34a516 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -64,6 +64,7 @@
plat/arm/common/arm_gicv2.c \
plat/common/plat_gicv2.c \
plat/xilinx/common/ipi.c \
+ plat/xilinx/zynqmp/zynqmp_ipi.c \
plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S \
plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -78,7 +79,6 @@
plat/xilinx/zynqmp/plat_startup.c \
plat/xilinx/zynqmp/plat_topology.c \
plat/xilinx/zynqmp/sip_svc_setup.c \
- plat/xilinx/zynqmp/zynqmp_ipi.c \
plat/xilinx/zynqmp/pm_service/pm_svc_main.c \
plat/xilinx/zynqmp/pm_service/pm_api_sys.c \
plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c \
diff --git a/plat/xilinx/zynqmp/sip_svc_setup.c b/plat/xilinx/zynqmp/sip_svc_setup.c
index edb81f5..9b18274 100644
--- a/plat/xilinx/zynqmp/sip_svc_setup.c
+++ b/plat/xilinx/zynqmp/sip_svc_setup.c
@@ -9,7 +9,6 @@
#include <common/runtime_svc.h>
#include <tools_share/uuid.h>
-#include <plat_ipi.h>
#include "ipi_mailbox_svc.h"
#include "pm_svc_main.h"
@@ -41,9 +40,6 @@
*/
static int32_t sip_svc_setup(void)
{
- /* Configure IPI data for ZynqMP */
- zynqmp_ipi_config_table_init();
-
/* PM implementation as SiP Service */
pm_setup();
diff --git a/tools/meson/Makefile b/tools/amlogic/Makefile
similarity index 100%
rename from tools/meson/Makefile
rename to tools/amlogic/Makefile
diff --git a/tools/meson/doimage.c b/tools/amlogic/doimage.c
similarity index 100%
rename from tools/meson/doimage.c
rename to tools/amlogic/doimage.c
diff --git a/tools/cert_create/include/cert.h b/tools/cert_create/include/cert.h
index 39b45b5..6db9b57 100644
--- a/tools/cert_create/include/cert.h
+++ b/tools/cert_create/include/cert.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -49,7 +49,6 @@
cert_t *cert_get_by_opt(const char *opt);
int cert_add_ext(X509 *issuer, X509 *subject, int nid, char *value);
int cert_new(
- int key_alg,
int md_alg,
cert_t *cert,
int days,
diff --git a/tools/cert_create/include/key.h b/tools/cert_create/include/key.h
index 310a77f..d96d983 100644
--- a/tools/cert_create/include/key.h
+++ b/tools/cert_create/include/key.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,8 +9,6 @@
#include <openssl/ossl_typ.h>
-#define RSA_KEY_BITS 2048
-
/* Error codes */
enum {
KEY_ERR_NONE,
@@ -23,13 +21,15 @@
/* Supported key algorithms */
enum {
KEY_ALG_RSA, /* RSA PSS as defined by PKCS#1 v2.1 (default) */
- KEY_ALG_RSA_1_5, /* RSA as defined by PKCS#1 v1.5 */
#ifndef OPENSSL_NO_EC
KEY_ALG_ECDSA,
#endif /* OPENSSL_NO_EC */
KEY_ALG_MAX_NUM
};
+/* Maximum number of valid key sizes per algorithm */
+#define KEY_SIZE_MAX_NUM 4
+
/* Supported hash algorithms */
enum{
HASH_ALG_SHA256,
@@ -37,6 +37,15 @@
HASH_ALG_SHA512,
};
+/* Supported key sizes */
+/* NOTE: the first item in each array is the default key size */
+static const unsigned int KEY_SIZES[KEY_ALG_MAX_NUM][KEY_SIZE_MAX_NUM] = {
+ { 2048, 1024, 3072, 4096 }, /* KEY_ALG_RSA */
+#ifndef OPENSSL_NO_EC
+ {} /* KEY_ALG_ECDSA */
+#endif /* OPENSSL_NO_EC */
+};
+
/*
* This structure contains the relevant information to create the keys
* required to sign the certificates.
@@ -58,7 +67,7 @@
int key_init(void);
key_t *key_get_by_opt(const char *opt);
int key_new(key_t *key);
-int key_create(key_t *key, int type);
+int key_create(key_t *key, int type, int key_bits);
int key_load(key_t *key, unsigned int *err_code);
int key_store(key_t *key);
diff --git a/tools/cert_create/src/cert.c b/tools/cert_create/src/cert.c
index 8e8aee6..c68a265 100644
--- a/tools/cert_create/src/cert.c
+++ b/tools/cert_create/src/cert.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -93,7 +93,6 @@
}
int cert_new(
- int key_alg,
int md_alg,
cert_t *cert,
int days,
@@ -143,10 +142,10 @@
}
/*
- * Set additional parameters if algorithm is RSA PSS. This is not
- * required for RSA 1.5 or ECDSA.
+ * Set additional parameters if issuing public key algorithm is RSA.
+ * This is not required for ECDSA.
*/
- if (key_alg == KEY_ALG_RSA) {
+ if (EVP_PKEY_base_id(ikey) == EVP_PKEY_RSA) {
if (!EVP_PKEY_CTX_set_rsa_padding(pKeyCtx, RSA_PKCS1_PSS_PADDING)) {
ERR_print_errors_fp(stdout);
goto END;
diff --git a/tools/cert_create/src/key.c b/tools/cert_create/src/key.c
index fece770..0f80cce 100644
--- a/tools/cert_create/src/key.c
+++ b/tools/cert_create/src/key.c
@@ -41,7 +41,7 @@
return 1;
}
-static int key_create_rsa(key_t *key)
+static int key_create_rsa(key_t *key, int key_bits)
{
BIGNUM *e;
RSA *rsa = NULL;
@@ -63,7 +63,7 @@
goto err;
}
- if (!RSA_generate_key_ex(rsa, RSA_KEY_BITS, e, NULL)) {
+ if (!RSA_generate_key_ex(rsa, key_bits, e, NULL)) {
printf("Cannot generate RSA key\n");
goto err;
}
@@ -82,7 +82,7 @@
}
#ifndef OPENSSL_NO_EC
-static int key_create_ecdsa(key_t *key)
+static int key_create_ecdsa(key_t *key, int key_bits)
{
EC_KEY *ec;
@@ -109,16 +109,15 @@
}
#endif /* OPENSSL_NO_EC */
-typedef int (*key_create_fn_t)(key_t *key);
+typedef int (*key_create_fn_t)(key_t *key, int key_bits);
static const key_create_fn_t key_create_fn[KEY_ALG_MAX_NUM] = {
key_create_rsa, /* KEY_ALG_RSA */
- key_create_rsa, /* KEY_ALG_RSA_1_5 */
#ifndef OPENSSL_NO_EC
key_create_ecdsa, /* KEY_ALG_ECDSA */
#endif /* OPENSSL_NO_EC */
};
-int key_create(key_t *key, int type)
+int key_create(key_t *key, int type, int key_bits)
{
if (type >= KEY_ALG_MAX_NUM) {
printf("Invalid key type\n");
@@ -126,7 +125,7 @@
}
if (key_create_fn[type]) {
- return key_create_fn[type](key);
+ return key_create_fn[type](key, key_bits);
}
return 0;
diff --git a/tools/cert_create/src/main.c b/tools/cert_create/src/main.c
index 0f588cc..0cbd219 100644
--- a/tools/cert_create/src/main.c
+++ b/tools/cert_create/src/main.c
@@ -10,6 +10,7 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
+#include <stdbool.h>
#include <openssl/conf.h>
#include <openssl/engine.h>
@@ -69,6 +70,7 @@
/* Global options */
static int key_alg;
static int hash_alg;
+static int key_size;
static int new_keys;
static int save_keys;
static int print_cert;
@@ -90,7 +92,6 @@
static const char *key_algs_str[] = {
[KEY_ALG_RSA] = "rsa",
- [KEY_ALG_RSA_1_5] = "rsa_1_5",
#ifndef OPENSSL_NO_EC
[KEY_ALG_ECDSA] = "ecdsa"
#endif /* OPENSSL_NO_EC */
@@ -155,6 +156,18 @@
return -1;
}
+static int get_key_size(const char *key_size_str)
+{
+ char *end;
+ long key_size;
+
+ key_size = strtol(key_size_str, &end, 10);
+ if (*end != '\0')
+ return -1;
+
+ return key_size;
+}
+
static int get_hash_alg(const char *hash_alg_str)
{
int i;
@@ -174,6 +187,7 @@
ext_t *ext;
key_t *key;
int i, j;
+ bool valid_size;
/* Only save new keys */
if (save_keys && !new_keys) {
@@ -181,6 +195,26 @@
exit(1);
}
+ /* Validate key-size */
+ valid_size = false;
+ for (i = 0; i < KEY_SIZE_MAX_NUM; i++) {
+ if (key_size == KEY_SIZES[key_alg][i]) {
+ valid_size = true;
+ break;
+ }
+ }
+ if (!valid_size) {
+ ERROR("'%d' is not a valid key size for '%s'\n",
+ key_size, key_algs_str[key_alg]);
+ NOTICE("Valid sizes are: ");
+ for (i = 0; i < KEY_SIZE_MAX_NUM &&
+ KEY_SIZES[key_alg][i] != 0; i++) {
+ printf("%d ", KEY_SIZES[key_alg][i]);
+ }
+ printf("\n");
+ exit(1);
+ }
+
/* Check that all required options have been specified in the
* command line */
for (i = 0; i < num_certs; i++) {
@@ -242,8 +276,11 @@
},
{
{ "key-alg", required_argument, NULL, 'a' },
- "Key algorithm: 'rsa' (default) - RSAPSS scheme as per \
-PKCS#1 v2.1, 'rsa_1_5' - RSA PKCS#1 v1.5, 'ecdsa'"
+ "Key algorithm: 'rsa' (default)- RSAPSS scheme as per PKCS#1 v2.1, 'ecdsa'"
+ },
+ {
+ { "key-size", required_argument, NULL, 'b' },
+ "Key size (for supported algorithms)."
},
{
{ "hash-alg", required_argument, NULL, 's' },
@@ -286,6 +323,7 @@
/* Set default options */
key_alg = KEY_ALG_RSA;
hash_alg = HASH_ALG_SHA256;
+ key_size = -1;
/* Add common command line options */
for (i = 0; i < NUM_ELEM(common_cmd_opt); i++) {
@@ -315,7 +353,7 @@
while (1) {
/* getopt_long stores the option index here. */
- c = getopt_long(argc, argv, "a:hknps:", cmd_opt, &opt_idx);
+ c = getopt_long(argc, argv, "a:b:hknps:", cmd_opt, &opt_idx);
/* Detect the end of the options. */
if (c == -1) {
@@ -330,6 +368,13 @@
exit(1);
}
break;
+ case 'b':
+ key_size = get_key_size(optarg);
+ if (key_size <= 0) {
+ ERROR("Invalid key size '%s'\n", optarg);
+ exit(1);
+ }
+ break;
case 'h':
print_help(argv[0], cmd_opt);
exit(0);
@@ -371,6 +416,11 @@
}
}
+ /* Select a reasonable default key-size */
+ if (key_size == -1) {
+ key_size = KEY_SIZES[key_alg][0];
+ }
+
/* Check command line arguments */
check_cmd_params();
@@ -413,7 +463,7 @@
if (new_keys) {
/* Try to create a new key */
NOTICE("Creating new key for '%s'\n", keys[i].desc);
- if (!key_create(&keys[i], key_alg)) {
+ if (!key_create(&keys[i], key_alg, key_size)) {
ERROR("Error creating key '%s'\n", keys[i].desc);
exit(1);
}
@@ -493,7 +543,7 @@
}
/* Create certificate. Signed with corresponding key */
- if (cert->fn && !cert_new(key_alg, hash_alg, cert, VAL_DAYS, 0, sk)) {
+ if (cert->fn && !cert_new(hash_alg, cert, VAL_DAYS, 0, sk)) {
ERROR("Cannot create %s\n", cert->cn);
exit(1);
}
