| /* |
| * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| * |
| * SPDX-License-Identifier: BSD-3-Clause |
| */ |
| |
| #ifndef RTC_H |
| #define RTC_H |
| |
| #define RTC_BASE_MT6392 0x8000 |
| #define RTC_BASE_MT6397 0xE000 |
| |
| #if defined(RTC_MT6392) && defined(RTC_MT6397) |
| #error "Only define one of RTC_MT6392 or RTC_MT6397!" |
| #endif |
| |
| #if defined(RTC_MT6392) |
| #define RTC_BASE RTC_BASE_MT6392 |
| #elif defined(RTC_MT6397) |
| #define RTC_BASE RTC_BASE_MT6397 |
| #else |
| #error "Please select an RTC!" |
| #endif |
| |
| /* RTC registers */ |
| enum { |
| RTC_BBPU = RTC_BASE + 0x00, |
| RTC_IRQ_STA = RTC_BASE + 0x02, |
| RTC_IRQ_EN = RTC_BASE + 0x04, |
| RTC_CII_EN = RTC_BASE + 0x06 |
| }; |
| |
| enum { |
| RTC_OSC32CON = RTC_BASE + 0x26, |
| RTC_CON = RTC_BASE + 0x3E, |
| RTC_WRTGR = RTC_BASE + 0x3C |
| }; |
| |
| enum { |
| RTC_PDN1 = RTC_BASE + 0x2C, |
| RTC_PDN2 = RTC_BASE + 0x2E, |
| RTC_SPAR0 = RTC_BASE + 0x30, |
| RTC_SPAR1 = RTC_BASE + 0x32, |
| RTC_PROT = RTC_BASE + 0x36, |
| RTC_DIFF = RTC_BASE + 0x38, |
| RTC_CALI = RTC_BASE + 0x3A |
| }; |
| |
| enum { |
| RTC_PROT_UNLOCK1 = 0x586A, |
| RTC_PROT_UNLOCK2 = 0x9136 |
| }; |
| |
| enum { |
| RTC_BBPU_PWREN = 1U << 0, |
| RTC_BBPU_BBPU = 1U << 2, |
| RTC_BBPU_AUTO = 1U << 3, |
| RTC_BBPU_CLRPKY = 1U << 4, |
| RTC_BBPU_RELOAD = 1U << 5, |
| RTC_BBPU_CBUSY = 1U << 6 |
| }; |
| |
| enum { |
| RTC_BBPU_KEY = 0x43 << 8 |
| }; |
| |
| void rtc_bbpu_power_down(void); |
| |
| #endif /* RTC_H */ |