core: introduce a new memory type for external dtb image
When CFG_DT=y, the external dtb image is mapped as
IO_NSEC memory type in init_external_dt function,
which may conflicts with dynamic shared memory check.
Below is the panic log with qemu boot:
E/TC:0 0 check_phys_mem_is_outside:333 Non-sec mem (0x40000000:0x3fe00000) overlaps map (type 13 0x40000000:0x100000)
E/TC:0 0 Panic at core/arch/arm/mm/core_mmu.c:334 <check_phys_mem_is_outside>
E/TC:0 0 TEE load address @ 0x1bd0f000
This patch introduces a new memory type MEM_AREA_EXT_DT
which is used to map external dtb image. This memory type
will be skipped over in core_mmu_set_discovered_nsec_ddr()
in order to avoid the above panic.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Fangsuo Wu <fangsuowu@asrmicro.com>
diff --git a/core/arch/arm/include/mm/core_mmu.h b/core/arch/arm/include/mm/core_mmu.h
index 7ffd89b..2965eee 100644
--- a/core/arch/arm/include/mm/core_mmu.h
+++ b/core/arch/arm/include/mm/core_mmu.h
@@ -100,6 +100,7 @@
* MEM_AREA_RAM_SEC: Secure RAM storing some secrets
* MEM_AREA_IO_NSEC: NonSecure HW mapped registers
* MEM_AREA_IO_SEC: Secure HW mapped registers
+ * MEM_AREA_EXT_DT: Memory loads external device tree
* MEM_AREA_RES_VASPACE: Reserved virtual memory space
* MEM_AREA_SHM_VASPACE: Virtual memory space for dynamic shared memory buffers
* MEM_AREA_TA_VASPACE: TA va space, only used with phys_to_virt()
@@ -123,6 +124,7 @@
MEM_AREA_RAM_SEC,
MEM_AREA_IO_NSEC,
MEM_AREA_IO_SEC,
+ MEM_AREA_EXT_DT,
MEM_AREA_RES_VASPACE,
MEM_AREA_SHM_VASPACE,
MEM_AREA_TA_VASPACE,
@@ -151,6 +153,7 @@
[MEM_AREA_RAM_SEC] = "RAM_SEC",
[MEM_AREA_IO_NSEC] = "IO_NSEC",
[MEM_AREA_IO_SEC] = "IO_SEC",
+ [MEM_AREA_EXT_DT] = "EXT_DT",
[MEM_AREA_RES_VASPACE] = "RES_VASPACE",
[MEM_AREA_SHM_VASPACE] = "SHM_VASPACE",
[MEM_AREA_TA_VASPACE] = "TA_VASPACE",
diff --git a/core/arch/arm/kernel/generic_boot.c b/core/arch/arm/kernel/generic_boot.c
index 4f6e463..92df0fc 100644
--- a/core/arch/arm/kernel/generic_boot.c
+++ b/core/arch/arm/kernel/generic_boot.c
@@ -999,10 +999,10 @@
return;
}
- if (!core_mmu_add_mapping(MEM_AREA_IO_NSEC, phys_dt, CFG_DTB_MAX_SIZE))
+ if (!core_mmu_add_mapping(MEM_AREA_EXT_DT, phys_dt, CFG_DTB_MAX_SIZE))
panic("Failed to map external DTB");
- fdt = phys_to_virt(phys_dt, MEM_AREA_IO_NSEC);
+ fdt = phys_to_virt(phys_dt, MEM_AREA_EXT_DT);
if (!fdt)
panic();
diff --git a/core/arch/arm/mm/core_mmu.c b/core/arch/arm/mm/core_mmu.c
index ad1e579..7518cd8 100644
--- a/core/arch/arm/mm/core_mmu.c
+++ b/core/arch/arm/mm/core_mmu.c
@@ -380,7 +380,7 @@
for (map = static_memory_map; core_mmap_is_end_of_table(map); map++) {
if (map->type == MEM_AREA_NSEC_SHM)
carve_out_phys_mem(&m, &num_elems, map->pa, map->size);
- else
+ else if (map->type != MEM_AREA_EXT_DT)
check_phys_mem_is_outside(m, num_elems, map);
}
@@ -663,6 +663,7 @@
return attr | TEE_MATTR_SECURE | TEE_MATTR_PRW | cached;
case MEM_AREA_NSEC_SHM:
return attr | TEE_MATTR_PRW | cached;
+ case MEM_AREA_EXT_DT:
case MEM_AREA_IO_NSEC:
return attr | TEE_MATTR_PRW | noncache;
case MEM_AREA_IO_SEC:
@@ -1165,6 +1166,7 @@
case MEM_AREA_TEE_ASAN:
case MEM_AREA_IO_SEC:
case MEM_AREA_IO_NSEC:
+ case MEM_AREA_EXT_DT:
case MEM_AREA_RAM_SEC:
case MEM_AREA_RAM_NSEC:
case MEM_AREA_RES_VASPACE:
