commit d34fc3a15fe57d548d950dba3dfcc8b525e13279
author Fabien Parent <fparent@baylibre.com> Thu Feb 13 17:43:20 2020 +0100
committer Fabien Parent <fparent@baylibre.com> Mon Feb 17 12:23:52 2020 +0100
tree a3ac25f5bf947d75e8e1960e1035b676fdb6c99f
parent 023e33656e2c9557ce50ad63a98b2e2c9b51c118

plat-mediatek: Add support for GIC

Add the support for the GIC for the MediaTek platforms.

Signed-off-by: Fabien Parent <fparent@baylibre.com>

core/arch/arm/plat-mediatek/main.c

diff --git a/core/arch/arm/plat-mediatek/main.c b/core/arch/arm/plat-mediatek/main.c
index 6a38e58..6a77d6e 100644
--- a/core/arch/arm/plat-mediatek/main.c
+++ b/core/arch/arm/plat-mediatek/main.c
@@ -4,6 +4,7 @@
  */
 
 #include <console.h>
+#include <drivers/gic.h>
 #include <drivers/serial8250_uart.h>
 #include <kernel/generic_boot.h>
 #include <kernel/panic.h>
@@ -28,6 +29,37 @@
 
 static struct serial8250_uart_data console_data;
 
+#ifdef CFG_GIC
+static struct gic_data gic_data;
+
+register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE + GICD_OFFSET,
+	CORE_MMU_PGDIR_SIZE);
+register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE + GICC_OFFSET,
+	CORE_MMU_PGDIR_SIZE);
+
+void main_init_gic(void)
+{
+	vaddr_t gicc_base;
+	vaddr_t gicd_base;
+
+	gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET,
+					  MEM_AREA_IO_SEC);
+	gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET,
+					  MEM_AREA_IO_SEC);
+	if (!gicc_base || !gicd_base)
+		panic();
+
+	gic_init_base_addr(&gic_data, gicc_base, gicd_base);
+
+	itr_init(&gic_data.chip);
+}
+
+void itr_core_handler(void)
+{
+	gic_it_handle(&gic_data);
+}
+#endif
+
 const struct thread_handlers *generic_boot_get_handlers(void)
 {
 	return &handlers;