core: generic_entry_a64.S: use CIVAC over IVAC to clean cache data
After moving some initial sections around in memory we clean out the new
data and invalidate the cache so it can be seen by other cores when they
enable caches. The instruction used was invalidate; on most systems this
will behave the same as clean/invalidate, but on some with L3 caches this
can cause the just written data to be invalidated. Use the
clean+invalidate to prevent this on such systems.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
diff --git a/core/arch/arm/kernel/generic_entry_a64.S b/core/arch/arm/kernel/generic_entry_a64.S
index 93e4e2a..b3cbb8f 100644
--- a/core/arch/arm/kernel/generic_entry_a64.S
+++ b/core/arch/arm/kernel/generic_entry_a64.S
@@ -154,7 +154,7 @@
adr_l x0, __text_start
ldr x1, cached_mem_end
sub x1, x1, x0
- bl dcache_inv_range
+ bl dcache_cleaninv_range
/* Enable Console */
bl console_init
