| /* |
| ** ################################################################### |
| ** Version: rev. 4.0, 2018-01-26 |
| ** Build: b191210 |
| ** |
| ** Abstract: |
| ** Chip specific module features. |
| ** |
| ** Copyright 2016 Freescale Semiconductor, Inc. |
| ** Copyright 2016-2019 NXP |
| ** All rights reserved. |
| ** |
| ** SPDX-License-Identifier: BSD-3-Clause |
| ** |
| ** http: www.nxp.com |
| ** mail: support@nxp.com |
| ** |
| ** Revisions: |
| ** - rev. 1.0 (2016-06-02) |
| ** Initial version. |
| ** - rev. 2.0 (2017-04-27) |
| ** Rev.B Header EAR1 |
| ** - rev. 3.0 (2017-07-19) |
| ** Rev.C Header EAR2 |
| ** - rev. 4.0 (2018-01-26) |
| ** Rev.D Header RFP |
| ** |
| ** ################################################################### |
| */ |
| |
| #ifndef _MIMX8MQ6_cm4_FEATURES_H_ |
| #define _MIMX8MQ6_cm4_FEATURES_H_ |
| |
| /* SOC module features */ |
| |
| /* @brief AIPSTZ availability on the SoC. */ |
| #define FSL_FEATURE_SOC_AIPSTZ_COUNT (4) |
| /* @brief APBH availability on the SoC. */ |
| #define FSL_FEATURE_SOC_APBH_COUNT (1) |
| /* @brief BCH availability on the SoC. */ |
| #define FSL_FEATURE_SOC_BCH_COUNT (1) |
| /* @brief CCM availability on the SoC. */ |
| #define FSL_FEATURE_SOC_CCM_COUNT (1) |
| /* @brief CCM_ANALOG availability on the SoC. */ |
| #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) |
| /* @brief ECSPI availability on the SoC. */ |
| #define FSL_FEATURE_SOC_ECSPI_COUNT (3) |
| /* @brief ENET availability on the SoC. */ |
| #define FSL_FEATURE_SOC_ENET_COUNT (1) |
| /* @brief GPC availability on the SoC. */ |
| #define FSL_FEATURE_SOC_GPC_COUNT (1) |
| /* @brief GPC_PGC availability on the SoC. */ |
| #define FSL_FEATURE_SOC_GPC_PGC_COUNT (1) |
| /* @brief GPMI availability on the SoC. */ |
| #define FSL_FEATURE_SOC_GPMI_COUNT (1) |
| /* @brief GPT availability on the SoC. */ |
| #define FSL_FEATURE_SOC_GPT_COUNT (6) |
| /* @brief I2S availability on the SoC. */ |
| #define FSL_FEATURE_SOC_I2S_COUNT (6) |
| /* @brief IGPIO availability on the SoC. */ |
| #define FSL_FEATURE_SOC_IGPIO_COUNT (5) |
| /* @brief II2C availability on the SoC. */ |
| #define FSL_FEATURE_SOC_II2C_COUNT (4) |
| /* @brief IOMUXC availability on the SoC. */ |
| #define FSL_FEATURE_SOC_IOMUXC_COUNT (1) |
| /* @brief IOMUXC_GPR availability on the SoC. */ |
| #define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1) |
| /* @brief IPWM availability on the SoC. */ |
| #define FSL_FEATURE_SOC_IPWM_COUNT (4) |
| /* @brief IUART availability on the SoC. */ |
| #define FSL_FEATURE_SOC_IUART_COUNT (4) |
| /* @brief LCDIF availability on the SoC. */ |
| #define FSL_FEATURE_SOC_LCDIF_COUNT (1) |
| /* @brief LMEM availability on the SoC. */ |
| #define FSL_FEATURE_SOC_LMEM_COUNT (1) |
| /* @brief MCM availability on the SoC. */ |
| #define FSL_FEATURE_SOC_MCM_COUNT (1) |
| /* @brief MIPI_CSI2RX availability on the SoC. */ |
| #define FSL_FEATURE_SOC_MIPI_CSI2RX_COUNT (2) |
| /* @brief MIPI_DSI_HOST availability on the SoC. */ |
| #define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (1) |
| /* @brief MU availability on the SoC. */ |
| #define FSL_FEATURE_SOC_MU_COUNT (1) |
| /* @brief OCOTP availability on the SoC. */ |
| #define FSL_FEATURE_SOC_OCOTP_COUNT (1) |
| /* @brief QuadSPI availability on the SoC. */ |
| #define FSL_FEATURE_SOC_QuadSPI_COUNT (1) |
| /* @brief RDC availability on the SoC. */ |
| #define FSL_FEATURE_SOC_RDC_COUNT (1) |
| /* @brief RDC_SEMAPHORE availability on the SoC. */ |
| #define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (2) |
| /* @brief ROMC availability on the SoC. */ |
| #define FSL_FEATURE_SOC_ROMC_COUNT (1) |
| /* @brief SEMA4 availability on the SoC. */ |
| #define FSL_FEATURE_SOC_SEMA4_COUNT (1) |
| /* @brief SNVS availability on the SoC. */ |
| #define FSL_FEATURE_SOC_SNVS_COUNT (1) |
| /* @brief SPBA availability on the SoC. */ |
| #define FSL_FEATURE_SOC_SPBA_COUNT (2) |
| /* @brief SPDIF availability on the SoC. */ |
| #define FSL_FEATURE_SOC_SPDIF_COUNT (2) |
| /* @brief SRC availability on the SoC. */ |
| #define FSL_FEATURE_SOC_SRC_COUNT (1) |
| /* @brief USDHC availability on the SoC. */ |
| #define FSL_FEATURE_SOC_USDHC_COUNT (2) |
| /* @brief WDOG availability on the SoC. */ |
| #define FSL_FEATURE_SOC_WDOG_COUNT (3) |
| /* @brief XTALOSC availability on the SoC. */ |
| #define FSL_FEATURE_SOC_XTALOSC_COUNT (1) |
| |
| /* CCM module features */ |
| |
| /* @brief Is affected by errata with ID 50235 (Incorrect clock setting for CAN affects by LPUART clock gate). */ |
| #define FSL_FEATURE_CCM_HAS_ERRATA_50235 (0) |
| |
| /* ECSPI module features */ |
| |
| /* @brief ECSPI Tx FIFO Size. */ |
| #define FSL_FEATURE_ECSPI_TX_FIFO_SIZEn(x) (64) |
| |
| /* ENET module features */ |
| |
| /* @brief Support Interrupt Coalesce */ |
| #define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (0) |
| /* @brief Queue Size. */ |
| #define FSL_FEATURE_ENET_QUEUE (3) |
| /* @brief Has AVB Support. */ |
| #define FSL_FEATURE_ENET_HAS_AVB (1) |
| /* @brief Has Timer Pulse Width control. */ |
| #define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (0) |
| /* @brief Has Extend MDIO Support. */ |
| #define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1) |
| /* @brief Has Additional 1588 Timer Channel Interrupt. */ |
| #define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (1) |
| /* @brief Support Interrupt Coalesce for each instance */ |
| #define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (0) |
| /* @brief Queue Size for each instance. */ |
| #define FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) (3) |
| /* @brief Has AVB Support for each instance. */ |
| #define FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(x) (1) |
| /* @brief Has Timer Pulse Width control for each instance. */ |
| #define FSL_FEATURE_ENET_INSTANCE_HAS_TIMER_PWCONTROLn(x) (0) |
| /* @brief Has Extend MDIO Support for each instance. */ |
| #define FSL_FEATURE_ENET_INSTANCE_HAS_EXTEND_MDIOn(x) (1) |
| /* @brief Has Additional 1588 Timer Channel Interrupt for each instance. */ |
| #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) |
| |
| /* GPC module features */ |
| |
| /* @brief Has PGC MF. */ |
| #define FSL_FEATURE_GPC_HAS_PGC_MF (1) |
| |
| /* IGPIO module features */ |
| |
| /* @brief Has data register set DR_SET. */ |
| #define FSL_FEATURE_IGPIO_HAS_DR_SET (0) |
| /* @brief Has data register clear DR_CLEAR. */ |
| #define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (0) |
| /* @brief Has data register toggle DR_TOGGLE. */ |
| #define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (0) |
| |
| /* SAI module features */ |
| |
| /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ |
| #define FSL_FEATURE_SAI_FIFO_COUNT (128) |
| /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ |
| #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \ |
| (((x) == I2S1) ? (8) : \ |
| (((x) == I2S2) ? (1) : \ |
| (((x) == I2S3) ? (1) : \ |
| (((x) == I2S4) ? (1) : \ |
| (((x) == I2S5) ? (1) : \ |
| (((x) == I2S6) ? (1) : (-1))))))) |
| /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ |
| #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) |
| /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ |
| #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) |
| /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ |
| #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) |
| /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ |
| #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) |
| /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ |
| #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) |
| /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ |
| #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) |
| /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ |
| #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) |
| /* @brief Interrupt source number */ |
| #define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) |
| /* @brief Has register of MCR. */ |
| #define FSL_FEATURE_SAI_HAS_MCR (0) |
| /* @brief Has bit field MICS of the MCR register. */ |
| #define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) |
| /* @brief Has register of MDR */ |
| #define FSL_FEATURE_SAI_HAS_MDR (0) |
| /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ |
| #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) |
| /* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ |
| #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) |
| /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ |
| #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) |
| /* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ |
| #define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) |
| |
| /* LMEM module features */ |
| |
| /* @brief Has process identifier support. */ |
| #define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (1) |
| /* @brief Support instruction cache demote. */ |
| #define FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE (1) |
| /* @brief Has no NONCACHEABLE section. */ |
| #define FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION (0) |
| /* @brief L1 ICACHE line size in byte. */ |
| #define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32) |
| /* @brief L1 DCACHE line size in byte. */ |
| #define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32) |
| |
| /* MEMORY module features */ |
| |
| /* @brief Memory map has offset between subsystems. */ |
| #define FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET (1) |
| |
| /* MU module features */ |
| |
| /* @brief MU side for current core */ |
| #define FSL_FEATURE_MU_SIDE_B (1) |
| /* @brief MU Has register CCR */ |
| #define FSL_FEATURE_MU_HAS_CCR (0) |
| /* @brief MU Has register SR[RS], BSR[ARS] */ |
| #define FSL_FEATURE_MU_HAS_SR_RS (1) |
| /* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */ |
| #define FSL_FEATURE_MU_HAS_RESET_INT (0) |
| /* @brief MU Has register SR[MURIP] */ |
| #define FSL_FEATURE_MU_HAS_SR_MURIP (0) |
| /* @brief MU Has register SR[HRIP] */ |
| #define FSL_FEATURE_MU_HAS_SR_HRIP (0) |
| /* @brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */ |
| #define FSL_FEATURE_MU_NO_CLKE (1) |
| /* @brief MU does not support NMI, CR[NMI]. */ |
| #define FSL_FEATURE_MU_NO_NMI (1) |
| /* @brief MU does not support hold the other core reset. CR[RSTH] or CCR[RSTH]. */ |
| #define FSL_FEATURE_MU_NO_RSTH (1) |
| /* @brief MU does not supports MU reset, CR[MUR]. */ |
| #define FSL_FEATURE_MU_NO_MUR (1) |
| /* @brief MU does not supports hardware reset, CR[HR] or CCR[HR]. */ |
| #define FSL_FEATURE_MU_NO_HR (1) |
| /* @brief MU supports mask the hardware reset. CR[HRM] or CCR[HRM]. */ |
| #define FSL_FEATURE_MU_HAS_HRM (1) |
| /* @brief MU does not support check the other core power mode. SR[PM]. */ |
| #define FSL_FEATURE_MU_NO_PM (1) |
| /* @brief MU supports reset assert interrupt. CR[RAIE] or BCR[RAIE]. */ |
| #define FSL_FEATURE_MU_HAS_RESET_ASSERT_INT (0) |
| /* @brief MU supports reset de-assert interrupt. CR[RDIE] or BCR[RDIE]. */ |
| #define FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT (0) |
| |
| /* interrupt module features */ |
| |
| /* @brief Lowest interrupt request number. */ |
| #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) |
| /* @brief Highest interrupt request number. */ |
| #define FSL_FEATURE_INTERRUPT_IRQ_MAX (105) |
| |
| /* QSPI module features */ |
| |
| /* @brief QSPI lookup table depth. */ |
| #define FSL_FEATURE_QSPI_LUT_DEPTH (64) |
| /* @brief QSPI Tx FIFO depth. */ |
| #define FSL_FEATURE_QSPI_TXFIFO_DEPTH (16) |
| /* @brief QSPI Rx FIFO depth. */ |
| #define FSL_FEATURE_QSPI_RXFIFO_DEPTH (16) |
| /* @brief QSPI AHB buffer count. */ |
| #define FSL_FEATURE_QSPI_AHB_BUFFER_COUNT (4) |
| /* @brief QSPI has command usage error flag. */ |
| #define FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR (1) |
| /* @brief QSPI support parallel mode. */ |
| #define FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE (1) |
| /* @brief QSPI support dual die. */ |
| #define FSL_FEATURE_QSPI_SUPPORT_DUAL_DIE (1) |
| /* @brief there is no SCLKCFG bit in MCR register. */ |
| #define FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL (1) |
| /* @brief there is no AITEF bit in FR register. */ |
| #define FSL_FEATURE_QSPI_HAS_NO_AITEF (1) |
| /* @brief there is no AIBSEF bit in FR register. */ |
| #define FSL_FEATURE_QSPI_HAS_NO_AIBSEF (1) |
| /* @brief there is no TXDMA and TXWA bit in SR register. */ |
| #define FSL_FEATURE_QSPI_HAS_NO_TXDMA (1) |
| /* @brief there is no SFACR register. */ |
| #define FSL_FEATURE_QSPI_HAS_NO_SFACR (1) |
| /* @brief there is no TDH bit in FLSHCR register. */ |
| #define FSL_FEATURE_QSPI_HAS_NO_TDH (0) |
| /* @brief QSPI AHB buffer size in byte. */ |
| #define FSL_FEATURE_QSPI_AHB_BUFFER_SIZE (1024U) |
| /* @brief QSPI AMBA base address. */ |
| #define FSL_FEATURE_QSPI_AMBA_BASE (0xC0000000U) |
| /* @brief QSPI AHB buffer ARDB base address. */ |
| #define FSL_FEATURE_QSPI_ARDB_BASE (0x34000000U) |
| /* @brief QSPI has no SOCCR register. */ |
| #define FSL_FEATURE_QSPI_HAS_NO_SOCCR_REG (1) |
| |
| /* SDMA module features */ |
| |
| /* @brief SDMA module channel number. */ |
| #define FSL_FEATURE_SDMA_MODULE_CHANNEL (32) |
| /* @brief SDMA module event number. */ |
| #define FSL_FEATURE_SDMA_EVENT_NUM (48) |
| /* @brief SDMA ROM memory to memory script start address. */ |
| #define FSL_FEATURE_SDMA_M2M_ADDR (644) |
| /* @brief SDMA ROM peripheral to memory script start address. */ |
| #define FSL_FEATURE_SDMA_P2M_ADDR (685) |
| /* @brief SDMA ROM memory to peripheral script start address. */ |
| #define FSL_FEATURE_SDMA_M2P_ADDR (749) |
| /* @brief SDMA ROM uart to memory script start address. */ |
| #define FSL_FEATURE_SDMA_UART2M_ADDR (819) |
| /* @brief SDMA ROM peripheral on SPBA to memory script start address. */ |
| #define FSL_FEATURE_SDMA_SHP2M_ADDR (893) |
| /* @brief SDMA ROM memory to peripheral on SPBA script start address. */ |
| #define FSL_FEATURE_SDMA_M2SHP_ADDR (962) |
| /* @brief SDMA ROM UART on SPBA to memory script start address. */ |
| #define FSL_FEATURE_SDMA_UARTSH2M_ADDR (1034) |
| /* @brief SDMA ROM SPDIF to memory script start address. */ |
| #define FSL_FEATURE_SDMA_SPDIF2M_ADDR (1102) |
| /* @brief SDMA ROM memory to SPDIF script start address. */ |
| #define FSL_FEATURE_SDMA_M2SPDIF_ADDR (1136) |
| |
| /* SEMA4 module features */ |
| |
| /* @brief Gate counts */ |
| #define FSL_FEATURE_SEMA4_GATE_COUNT (16) |
| |
| /* SNVS module features */ |
| |
| /* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */ |
| #define FSL_FEATURE_SNVS_HAS_SRTC (1) |
| |
| /* SPBA module features */ |
| |
| /* @brief SPBA module start address. */ |
| #define FSL_FEATURE_SPBA_STARTn(x) \ |
| (((x) == SPBA1) ? (0x30800000) : \ |
| (((x) == SPBA2) ? (0x30000000) : (-1))) |
| /* @brief SPBA module end address. */ |
| #define FSL_FEATURE_SPBA_ENDn(x) \ |
| (((x) == SPBA1) ? (0x308FFFFF) : \ |
| (((x) == SPBA2) ? (0x300FFFFF) : (-1))) |
| |
| /* SysTick module features */ |
| |
| /* @brief Systick has external reference clock. */ |
| #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) |
| /* @brief Systick external reference clock is core clock divided by this value. */ |
| #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) |
| |
| /* IUART module features */ |
| |
| /* @brief UART Transmit/Receive FIFO Size */ |
| #define FSL_FEATURE_IUART_FIFO_SIZEn(x) (32) |
| /* @brief UART RX MUXed input selected option */ |
| #define FSL_FEATURE_IUART_RXDMUXSEL (1) |
| |
| /* USDHC module features */ |
| |
| /* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ |
| #define FSL_FEATURE_USDHC_HAS_EXT_DMA (1) |
| /* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ |
| #define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) |
| /* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ |
| #define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) |
| /* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ |
| #define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) |
| /* @brief USDHC has reset control */ |
| #define FSL_FEATURE_USDHC_HAS_RESET (0) |
| /* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ |
| #define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) |
| |
| #endif /* _MIMX8MQ6_cm4_FEATURES_H_ */ |
| |
