| /* |
| ** ################################################################### |
| ** Processors: MIMX8MQ6CVAHZ |
| ** MIMX8MQ6DVAJZ |
| ** |
| ** Compilers: Keil ARM C/C++ Compiler |
| ** GNU C Compiler |
| ** IAR ANSI C/C++ Compiler for ARM |
| ** |
| ** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018 |
| ** Version: rev. 4.0, 2018-01-26 |
| ** Build: b180903 |
| ** |
| ** Abstract: |
| ** CMSIS Peripheral Access Layer for MIMX8MQ6_cm4 |
| ** |
| ** Copyright 1997-2016 Freescale Semiconductor, Inc. |
| ** Copyright 2016-2018 NXP |
| ** All rights reserved. |
| ** |
| ** SPDX-License-Identifier: BSD-3-Clause |
| ** |
| ** http: www.nxp.com |
| ** mail: support@nxp.com |
| ** |
| ** Revisions: |
| ** - rev. 1.0 (2017-01-10) |
| ** Initial version. |
| ** - rev. 2.0 (2017-04-27) |
| ** Rev.B Header EAR1 |
| ** - rev. 3.0 (2017-07-19) |
| ** Rev.C Header EAR2 |
| ** - rev. 4.0 (2018-01-26) |
| ** Rev.D Header RFP |
| ** |
| ** ################################################################### |
| */ |
| |
| /*! |
| * @file MIMX8MQ6_cm4.h |
| * @version 4.0 |
| * @date 2018-01-26 |
| * @brief CMSIS Peripheral Access Layer for MIMX8MQ6_cm4 |
| * |
| * CMSIS Peripheral Access Layer for MIMX8MQ6_cm4 |
| */ |
| |
| #ifndef _MIMX8MQ6_CM4_H_ |
| #define _MIMX8MQ6_CM4_H_ /**< Symbol preventing repeated inclusion */ |
| |
| /** Memory map major version (memory maps with equal major version number are |
| * compatible) */ |
| #define MCU_MEM_MAP_VERSION 0x0400U |
| /** Memory map minor version */ |
| #define MCU_MEM_MAP_VERSION_MINOR 0x0000U |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- Interrupt vector numbers |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup Interrupt_vector_numbers Interrupt vector numbers |
| * @{ |
| */ |
| |
| /** Interrupt Number Definitions */ |
| #define NUMBER_OF_INT_VECTORS 144 /**< Number of interrupts in the Vector table */ |
| |
| typedef enum IRQn { |
| /* Auxiliary constants */ |
| NotAvail_IRQn = -128, /**< Not available device specific interrupt */ |
| |
| /* Core interrupts */ |
| NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ |
| HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ |
| MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ |
| BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ |
| UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ |
| SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ |
| DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ |
| PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ |
| SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ |
| |
| /* Device specific interrupts */ |
| GPR_IRQ_IRQn = 0, /**< GPR Interrupt. Used to notify cores on exception condition while boot. */ |
| DAP_IRQn = 1, /**< DAP Interrupt */ |
| SDMA1_IRQn = 2, /**< AND of all 48 SDMA interrupts (events) from all the channels */ |
| GPU_IRQn = 3, /**< GPU Interrupt */ |
| SNVS_IRQn = 4, /**< ON-OFF button press shorter than 5 seconds (pulse event) */ |
| LCDIF_IRQn = 5, /**< LCDIF Sync Interrupt */ |
| SPDIF1_IRQn = 6, /**< SPDIF1 Interrupt */ |
| H264_IRQn = 7, /**< h264 Decoder Interrupt */ |
| VPUDMA_IRQn = 8, /**< VPU DMA Interrupt */ |
| QOS_IRQn = 9, /**< QOS interrupt */ |
| WDOG3_IRQn = 10, /**< Watchdog Timer reset */ |
| HS_CP1_IRQn = 11, /**< HS Interrupt Request */ |
| APBHDMA_IRQn = 12, /**< GPMI operation channel 0-3 description complete interrupt */ |
| SPDIF2_IRQn = 13, /**< SPDIF2 Interrupt */ |
| BCH_IRQn = 14, /**< BCH operation complete interrupt */ |
| GPMI_IRQn = 15, /**< GPMI operation TIMEOUT ERROR interrupt */ |
| HDMI_IRQ0_IRQn = 16, /**< HDMI Interrupt 0 */ |
| HDMI_IRQ1_IRQn = 17, /**< HDMI Interrupt 1 */ |
| HDMI_IRQ2_IRQn = 18, /**< HDMI Interrupt 2 */ |
| SNVS_Consolidated_IRQn = 19, /**< SRTC Consolidated Interrupt. Non TZ. */ |
| SNVS_Security_IRQn = 20, /**< SRTC Security Interrupt. TZ. */ |
| CSU_IRQn = 21, /**< CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted. */ |
| USDHC1_IRQn = 22, /**< uSDHC1 Enhanced SDHC Interrupt Request */ |
| USDHC2_IRQn = 23, /**< uSDHC2 Enhanced SDHC Interrupt Request */ |
| DDC_IRQn = 24, /**< DC8000 Display Controller IRQ */ |
| DTRC_IRQn = 25, /**< DTRC interrupt */ |
| UART1_IRQn = 26, /**< UART-1 ORed interrupt */ |
| UART2_IRQn = 27, /**< UART-2 ORed interrupt */ |
| UART3_IRQn = 28, /**< UART-3 ORed interrupt */ |
| UART4_IRQn = 29, /**< UART-4 ORed interrupt */ |
| VP9_IRQn = 30, /**< VP9 Decoder interrupt */ |
| ECSPI1_IRQn = 31, /**< ECSPI1 interrupt request line to the core. */ |
| ECSPI2_IRQn = 32, /**< ECSPI2 interrupt request line to the core. */ |
| ECSPI3_IRQn = 33, /**< ECSPI3 interrupt request line to the core. */ |
| MIPI_DSI_IRQn = 34, /**< DSI Interrupt */ |
| I2C1_IRQn = 35, /**< I2C-1 Interrupt */ |
| I2C2_IRQn = 36, /**< I2C-2 Interrupt */ |
| I2C3_IRQn = 37, /**< I2C-3 Interrupt */ |
| I2C4_IRQn = 38, /**< I2C-4 Interrupt */ |
| RDC_IRQn = 39, /**< RDC interrupt */ |
| USB1_IRQn = 40, /**< USB1 Interrupt */ |
| USB2_IRQn = 41, /**< USB1 Interrupt */ |
| CSI1_IRQn = 42, /**< CSI1 interrupt */ |
| CSI2_IRQn = 43, /**< CSI2 interrupt */ |
| MIPI_CSI1_IRQn = 44, /**< MIPI-CSI-1 Interrupt */ |
| MIPI_CSI2_IRQn = 45, /**< MIPI-CSI-2 Interrupt */ |
| GPT6_IRQn = 46, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */ |
| SCTR_IRQ0_IRQn = 47, /**< ISO7816IP Interrupt 0 */ |
| SCTR_IRQ1_IRQn = 48, /**< ISO7816IP Interrupt 1 */ |
| TEMPMON_IRQn = 49, /**< TempSensor (Temperature alarm). */ |
| I2S3_IRQn = 50, /**< SAI3 Receive / Transmit Interrupt */ |
| GPT5_IRQn = 51, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */ |
| GPT4_IRQn = 52, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */ |
| GPT3_IRQn = 53, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */ |
| GPT2_IRQn = 54, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */ |
| GPT1_IRQn = 55, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */ |
| GPIO1_INT7_IRQn = 56, /**< Active HIGH Interrupt from INT7 from GPIO */ |
| GPIO1_INT6_IRQn = 57, /**< Active HIGH Interrupt from INT6 from GPIO */ |
| GPIO1_INT5_IRQn = 58, /**< Active HIGH Interrupt from INT5 from GPIO */ |
| GPIO1_INT4_IRQn = 59, /**< Active HIGH Interrupt from INT4 from GPIO */ |
| GPIO1_INT3_IRQn = 60, /**< Active HIGH Interrupt from INT3 from GPIO */ |
| GPIO1_INT2_IRQn = 61, /**< Active HIGH Interrupt from INT2 from GPIO */ |
| GPIO1_INT1_IRQn = 62, /**< Active HIGH Interrupt from INT1 from GPIO */ |
| GPIO1_INT0_IRQn = 63, /**< Active HIGH Interrupt from INT0 from GPIO */ |
| GPIO1_Combined_0_15_IRQn = 64, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */ |
| GPIO1_Combined_16_31_IRQn = 65, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */ |
| GPIO2_Combined_0_15_IRQn = 66, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */ |
| GPIO2_Combined_16_31_IRQn = 67, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */ |
| GPIO3_Combined_0_15_IRQn = 68, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */ |
| GPIO3_Combined_16_31_IRQn = 69, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */ |
| GPIO4_Combined_0_15_IRQn = 70, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */ |
| GPIO4_Combined_16_31_IRQn = 71, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */ |
| GPIO5_Combined_0_15_IRQn = 72, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */ |
| GPIO5_Combined_16_31_IRQn = 73, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */ |
| PCIE_CTRL2_IRQ0_IRQn = 74, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ |
| PCIE_CTRL2_IRQ1_IRQn = 75, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ |
| PCIE_CTRL2_IRQ2_IRQn = 76, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ |
| PCIE_CTRL2_IRQ3_IRQn = 77, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ |
| WDOG1_IRQn = 78, /**< Watchdog Timer reset */ |
| WDOG2_IRQn = 79, /**< Watchdog Timer reset */ |
| PCIE_CTRL2_IRQn = 80, /**< Channels [63:32] interrupts requests */ |
| PWM1_IRQn = 81, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */ |
| PWM2_IRQn = 82, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */ |
| PWM3_IRQn = 83, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */ |
| PWM4_IRQn = 84, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */ |
| CCM_IRQ1_IRQn = 85, /**< CCM, Interrupt Request 1 */ |
| CCM_IRQ2_IRQn = 86, /**< CCM, Interrupt Request 2 */ |
| GPC_IRQn = 87, /**< GPC Interrupt Request 1 */ |
| MU_A53_IRQn = 88, /**< Interrupt to A53 */ |
| SRC_IRQn = 89, /**< SRC interrupt request */ |
| I2S56_IRQn = 90, /**< SAI5/6 Receive / Transmit Interrupt */ |
| RTIC_IRQn = 91, /**< RTIC Interrupt */ |
| CPU_PerformanceUnit_IRQn = 92, /**< Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[n] */ |
| CPU_CTI_Trigger_IRQn = 93, /**< CTI trigger outputs (internal: nCTIIRQ[n] */ |
| SRC_Combined_IRQn = 94, /**< Combined CPU wdog interrupts (4x) out of SRC. */ |
| I2S1_IRQn = 95, /**< SAI1 Receive / Transmit Interrupt */ |
| I2S2_IRQn = 96, /**< SAI2 Receive / Transmit Interrupt */ |
| MU_M4_IRQn = 97, /**< Interrupt to M4 */ |
| DDR_PerformanceMonitor_IRQn = 98, /**< ddr Interrupt for performance monitor */ |
| DDR_IRQn = 99, /**< ddr Interrupt */ |
| I2S4_IRQn = 100, /**< SAI4 Receive / Transmit Interrupt */ |
| CPU_Error_AXI_IRQn = 101, /**< CPU Error indicator for AXI transaction with a write response error condition */ |
| CPU_Error_L2RAM_IRQn = 102, /**< CPU Error indicator for L2 RAM double-bit ECC error */ |
| SDMA2_IRQn = 103, /**< AND of all 48 SDMA interrupts (events) from all the channels */ |
| Reserved120_IRQn = 104, /**< Reserved */ |
| CAAM_IRQ0_IRQn = 105, /**< CAAM interrupt queue for JQ */ |
| CAAM_IRQ1_IRQn = 106, /**< CAAM interrupt queue for JQ */ |
| QSPI_IRQn = 107, /**< QSPI Interrupt */ |
| TZASC_IRQn = 108, /**< TZASC (PL380) interrupt */ |
| Reserved125_IRQn = 109, /**< Reserved */ |
| Reserved126_IRQn = 110, /**< Reserved */ |
| Reserved127_IRQn = 111, /**< Reserved */ |
| PERFMON1_IRQn = 112, /**< General Interrupt */ |
| PERFMON2_IRQn = 113, /**< General Interrupt */ |
| CAAM_IRQ2_IRQn = 114, /**< CAAM interrupt queue for JQ */ |
| CAAM_ERROR_IRQn = 115, /**< Recoverable error interrupt */ |
| HS_CP0_IRQn = 116, /**< HS Interrupt Request */ |
| HEVC_IRQn = 117, /**< HEVC interrupt */ |
| ENET_MAC0_Rx_Tx_Done1_IRQn = 118, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */ |
| ENET_MAC0_Rx_Tx_Done2_IRQn = 119, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */ |
| ENET_IRQn = 120, /**< MAC 0 IRQ */ |
| ENET_1588_IRQn = 121, /**< MAC 0 1588 Timer Interrupt - synchronous */ |
| PCIE_CTRL1_IRQ0_IRQn = 122, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ |
| PCIE_CTRL1_IRQ1_IRQn = 123, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ |
| PCIE_CTRL1_IRQ2_IRQn = 124, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ |
| PCIE_CTRL1_IRQ3_IRQn = 125, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ |
| Reserved142_IRQn = 126, /**< Reserved */ |
| PCIE_CTRL1_IRQn = 127 /**< Channels [63:32] interrupts requests */ |
| } IRQn_Type; |
| |
| /*! |
| * @} |
| */ /* end of group Interrupt_vector_numbers */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- Cortex M4 Core Configuration |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration |
| * @{ |
| */ |
| |
| #define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ |
| #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ |
| #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ |
| #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ |
| |
| #include "core_cm4.h" /* Core Peripheral Access Layer */ |
| #include "system_MIMX8MQ6_cm4.h" /* Device specific configuration file */ |
| |
| /*! |
| * @} |
| */ /* end of group Cortex_Core_Configuration */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- Mapping Information |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup Mapping_Information Mapping Information |
| * @{ |
| */ |
| |
| /** Mapping Information */ |
| /*! |
| * @addtogroup iomuxc_pads |
| * @{ */ |
| |
| /******************************************************************************* |
| * Definitions |
| *******************************************************************************/ |
| |
| /*! |
| * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD |
| * |
| * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections. |
| */ |
| typedef enum _iomuxc_sw_mux_ctl_pad |
| { |
| kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ENET_MDC = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ENET_MDIO = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ENET_TD3 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ENET_TD2 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ENET_TD1 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ENET_TD0 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ENET_TX_CTL = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ENET_TXC = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ENET_RX_CTL = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ENET_RXC = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ENET_RD0 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ENET_RD1 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ENET_RD2 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ENET_RD3 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SD1_CLK = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SD1_CMD = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA4 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA5 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA6 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA7 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SD1_STROBE = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SD2_CD_B = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SD2_CLK = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SD2_CMD = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SD2_WP = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_NAND_ALE = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_NAND_CE2_B = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_NAND_CE3_B = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_NAND_CLE = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_NAND_DQS = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_NAND_RE_B = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_NAND_READY_B = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_NAND_WE_B = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_NAND_WP_B = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXC = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD0 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD1 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD2 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD3 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI5_MCLK = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXFS = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXC = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD0 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD1 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD2 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD3 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD4 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD5 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD6 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD7 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXFS = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXC = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD0 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD1 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD2 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD3 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD4 = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD5 = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD6 = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD7 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXFS = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXC = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXD0 = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXFS = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXC = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXD0 = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI2_MCLK = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXFS = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXC = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXD = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXC = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXD = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SAI3_MCLK = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SPDIF_TX = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SPDIF_RX = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_SPDIF_EXT_CLK = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0 = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_I2C1_SCL = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_I2C1_SDA = 124U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_I2C2_SCL = 125U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_I2C2_SDA = 126U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_I2C3_SCL = 127U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_I2C3_SDA = 128U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_I2C4_SCL = 129U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_I2C4_SDA = 130U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_UART1_RXD = 131U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_UART1_TXD = 132U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_UART2_RXD = 133U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_UART2_TXD = 134U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_UART3_RXD = 135U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_UART3_TXD = 136U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_UART4_RXD = 137U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| kIOMUXC_SW_MUX_CTL_PAD_UART4_TXD = 138U, /**< IOMUXC SW_MUX_CTL_PAD index */ |
| } iomuxc_sw_mux_ctl_pad_t; |
| |
| /*! |
| * @addtogroup iomuxc_pads |
| * @{ */ |
| |
| /******************************************************************************* |
| * Definitions |
| *******************************************************************************/ |
| |
| /*! |
| * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD |
| * |
| * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections. |
| */ |
| typedef enum _iomuxc_sw_pad_ctl_pad |
| { |
| kIOMUXC_SW_PAD_CTL_PAD_TEST_MODE = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_JTAG_MOD = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDI = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_JTAG_TMS = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_JTAG_TCK = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDO = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_RTC = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ONOFF = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_POR_B = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_RTC_RESET_B = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ENET_MDC = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ENET_MDIO = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ENET_TD3 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ENET_TD2 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ENET_TD1 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ENET_TD0 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ENET_TX_CTL = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ENET_TXC = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ENET_RX_CTL = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ENET_RXC = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ENET_RD0 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ENET_RD1 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ENET_RD2 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ENET_RD3 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SD1_CLK = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SD1_CMD = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA4 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA5 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA6 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA7 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SD1_STROBE = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SD2_CD_B = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SD2_CLK = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SD2_CMD = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SD2_WP = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_NAND_ALE = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_NAND_CE2_B = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_NAND_CE3_B = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_NAND_CLE = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_NAND_DQS = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_NAND_RE_B = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_NAND_READY_B = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_NAND_WE_B = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_NAND_WP_B = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXFS = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXC = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD0 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD1 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD2 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD3 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI5_MCLK = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXFS = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXC = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD0 = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD1 = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD2 = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD3 = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD4 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD5 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD6 = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD7 = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXFS = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXC = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD0 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD1 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD2 = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD3 = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD4 = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD5 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD6 = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD7 = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK = 112U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXFS = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXC = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXD0 = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXFS = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXC = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXD0 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI2_MCLK = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXFS = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXC = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXD = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXFS = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXC = 124U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXD = 125U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SAI3_MCLK = 126U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SPDIF_TX = 127U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SPDIF_RX = 128U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_SPDIF_EXT_CLK = 129U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK = 130U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI = 131U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO = 132U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0 = 133U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK = 134U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI = 135U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO = 136U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0 = 137U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_I2C1_SCL = 138U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_I2C1_SDA = 139U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_I2C2_SCL = 140U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_I2C2_SDA = 141U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_I2C3_SCL = 142U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_I2C3_SDA = 143U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_I2C4_SCL = 144U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_I2C4_SDA = 145U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_UART1_RXD = 146U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_UART1_TXD = 147U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_UART2_RXD = 148U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_UART2_TXD = 149U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_UART3_RXD = 150U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_UART3_TXD = 151U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_UART4_RXD = 152U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| kIOMUXC_SW_PAD_CTL_PAD_UART4_TXD = 153U, /**< IOMUXC SW_PAD_CTL_PAD index */ |
| } iomuxc_sw_pad_ctl_pad_t; |
| |
| /* @} */ |
| |
| /*! |
| * @brief Enumeration for the IOMUXC select input |
| * |
| * Defines the enumeration for the IOMUXC select input collections. |
| */ |
| typedef enum _iomuxc_select_input |
| { |
| kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 0U, /**< IOMUXC select input index */ |
| kIOMUXC_ENET1_MDIO_SELECT_INPUT = 1U, /**< IOMUXC select input index */ |
| kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 2U, /**< IOMUXC select input index */ |
| kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 3U, /**< IOMUXC select input index */ |
| kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 4U, /**< IOMUXC select input index */ |
| kIOMUXC_SAI5_RX_BCLK_SELECT_INPUT = 5U, /**< IOMUXC select input index */ |
| kIOMUXC_SAI5_RXD0_SELECT_INPUT = 6U, /**< IOMUXC select input index */ |
| kIOMUXC_SAI5_RXD1_SELECT_INPUT = 7U, /**< IOMUXC select input index */ |
| kIOMUXC_SAI5_RXD2_SELECT_INPUT = 8U, /**< IOMUXC select input index */ |
| kIOMUXC_SAI5_RXD3_SELECT_INPUT = 9U, /**< IOMUXC select input index */ |
| kIOMUXC_SAI5_RX_SYNC_SELECT_INPUT = 10U, /**< IOMUXC select input index */ |
| kIOMUXC_SAI5_TX_BCLK_SELECT_INPUT = 11U, /**< IOMUXC select input index */ |
| kIOMUXC_SAI5_TX_SYNC_SELECT_INPUT = 12U, /**< IOMUXC select input index */ |
| kIOMUXC_UART1_RTS_B_SELECT_INPUT = 13U, /**< IOMUXC select input index */ |
| kIOMUXC_UART1_RXD_SELECT_INPUT = 14U, /**< IOMUXC select input index */ |
| kIOMUXC_UART2_RTS_B_SELECT_INPUT = 15U, /**< IOMUXC select input index */ |
| kIOMUXC_UART2_RXD_SELECT_INPUT = 16U, /**< IOMUXC select input index */ |
| kIOMUXC_UART3_RTS_B_SELECT_INPUT = 17U, /**< IOMUXC select input index */ |
| kIOMUXC_UART3_RXD_SELECT_INPUT = 18U, /**< IOMUXC select input index */ |
| kIOMUXC_UART4_RTS_B_SELECT_INPUT = 19U, /**< IOMUXC select input index */ |
| kIOMUXC_UART4_RXD_SELECT_INPUT = 20U, /**< IOMUXC select input index */ |
| kIOMUXC_SAI6_RX_BCLK_SELECT_INPUT = 21U, /**< IOMUXC select input index */ |
| kIOMUXC_SAI6_RXD0_SELECT_INPUT = 22U, /**< IOMUXC select input index */ |
| kIOMUXC_SAI6_RX_SYNC_SELECT_INPUT = 23U, /**< IOMUXC select input index */ |
| kIOMUXC_SAI6_TX_BCLK_SELECT_INPUT = 24U, /**< IOMUXC select input index */ |
| kIOMUXC_SAI6_TX_SYNC_SELECT_INPUT = 25U, /**< IOMUXC select input index */ |
| kIOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT = 26U, /**< IOMUXC select input index */ |
| kIOMUXC_PCIE2_CLKREQ_B_SELECT_INPUT = 27U, /**< IOMUXC select input index */ |
| kIOMUXC_SAI5_MCLK_SELECT_INPUT = 28U, /**< IOMUXC select input index */ |
| kIOMUXC_SAI6_MCLK_SELECT_INPUT = 29U, /**< IOMUXC select input index */ |
| } iomuxc_select_input_t; |
| |
| /*! |
| * @addtogroup rdc_mapping |
| * @{ |
| */ |
| |
| /******************************************************************************* |
| * Definitions |
| ******************************************************************************/ |
| |
| /*! |
| * @brief Structure for the RDC mapping |
| * |
| * Defines the structure for the RDC resource collections. |
| */ |
| |
| typedef enum _rdc_master |
| { |
| kRDC_Master_A53 = 0U, /**< ARM Cortex-A53 RDC Master */ |
| kRDC_Master_M4 = 1U, /**< ARM Cortex-M4 RDC Master */ |
| kRDC_Master_PCIE1 = 2U, /**< PCIE1 RDC Master */ |
| kRDC_Master_PCIE2 = 3U, /**< PCIE2 RDC Master */ |
| kRDC_Master_VPU = 4U, /**< VPU RDC Master */ |
| kRDC_Master_LCDIF = 5U, /**< LCDIF RDC Master */ |
| kRDC_Master_CSI1 = 6U, /**< CSI1 PORT RDC Master */ |
| kRDC_Master_CSI2 = 7U, /**< CSI2 RDC Master */ |
| kRDC_Master_Coresight = 8U, /**< CORESIGHT RDC Master */ |
| kRDC_Master_DAP = 9U, /**< DAP RDC Master */ |
| kRDC_Master_CAAM = 10U, /**< CAAM RDC Master */ |
| kRDC_Master_SDMA1_PERIPH = 11U, /**< SDMA1 PERIPHERAL RDC Master */ |
| kRDC_Master_SDMA1_BURST = 12U, /**< SDMA1 BURST RDC Master */ |
| kRDC_Master_APBHDMA = 13U, /**< APBH DMA RDC Master */ |
| kRDC_Master_RAWNAND = 14U, /**< RAW NAND RDC Master */ |
| kRDC_Master_USDHC1 = 15U, /**< USDHC1 RDC Master */ |
| kRDC_Master_USDHC2 = 16U, /**< USDHC2 RDC Master */ |
| kRDC_Master_DP = 17U, /**< DP RDC Master */ |
| kRDC_Master_GPU = 18U, /**< GPU RDC Master */ |
| kRDC_Master_USB1 = 19U, /**< USB1 RDC Master */ |
| kRDC_Master_USB2 = 20U, /**< USB2 RDC Master */ |
| kRDC_Master_TESTPORT = 21U, /**< TESTPORT RDC Master */ |
| kRDC_Master_ENET1TX = 22U, /**< ENET1 TX RDC Master */ |
| kRDC_Master_ENET1RX = 23U, /**< ENET1 RX RDC Master */ |
| kRDC_Master_SDMA2_PERIPH = 24U, /**< SDMA2 PERIPH RDC Master */ |
| kRDC_Master_SDMA2_BURST = 24U, /**< SDMA2 BURST RDC Master */ |
| kRDC_Master_SDMA2_SPDA2 = 24U, /**< SDMA2 to SPDA2 RDC Master */ |
| kRDC_Master_SDMA1_SPBA1 = 26U, /**< SDMA1 to SPBA1 RDC Master */ |
| } rdc_master_t; |
| |
| typedef enum _rdc_mem |
| { |
| kRDC_Mem_MRC0_0 = 0U, /**< MMDC/DRAM. Region resolution 4KB. */ |
| kRDC_Mem_MRC0_1 = 1U, |
| kRDC_Mem_MRC0_2 = 2U, |
| kRDC_Mem_MRC0_3 = 3U, |
| kRDC_Mem_MRC0_4 = 4U, |
| kRDC_Mem_MRC0_5 = 5U, |
| kRDC_Mem_MRC0_6 = 6U, |
| kRDC_Mem_MRC0_7 = 7U, |
| kRDC_Mem_MRC1_0 = 8U, /**< PCIE2. Region resolution 4KB. */ |
| kRDC_Mem_MRC1_1 = 9U, |
| kRDC_Mem_MRC1_2 = 10U, |
| kRDC_Mem_MRC1_3 = 11U, |
| kRDC_Mem_MRC2_0 = 12U, /**< QSPI. Region resolution 4KB. */ |
| kRDC_Mem_MRC2_1 = 13U, |
| kRDC_Mem_MRC2_2 = 14U, |
| kRDC_Mem_MRC2_3 = 15U, |
| kRDC_Mem_MRC2_4 = 16U, |
| kRDC_Mem_MRC2_5 = 17U, |
| kRDC_Mem_MRC2_6 = 18U, |
| kRDC_Mem_MRC2_7 = 19U, |
| kRDC_Mem_MRC3_0 = 20U, /**< PCIE1. Region resolution 4KB. */ |
| kRDC_Mem_MRC3_1 = 21U, |
| kRDC_Mem_MRC3_2 = 22U, |
| kRDC_Mem_MRC3_3 = 23U, |
| kRDC_Mem_MRC4_0 = 24U, /**< OCRAM. Region resolution 128B. */ |
| kRDC_Mem_MRC4_1 = 25U, |
| kRDC_Mem_MRC4_2 = 26U, |
| kRDC_Mem_MRC4_3 = 27U, |
| kRDC_Mem_MRC4_4 = 28U, |
| kRDC_Mem_MRC5_0 = 29U, /**< OCRAM_S. Region resolution 128B. */ |
| kRDC_Mem_MRC5_1 = 30U, |
| kRDC_Mem_MRC5_2 = 31U, |
| kRDC_Mem_MRC5_3 = 32U, |
| kRDC_Mem_MRC5_4 = 33U, |
| kRDC_Mem_MRC6_0 = 34U, /**< TCM. Region resolution 128B. */ |
| kRDC_Mem_MRC6_1 = 35U, |
| kRDC_Mem_MRC6_2 = 36U, |
| kRDC_Mem_MRC6_3 = 37U, |
| kRDC_Mem_MRC6_4 = 38U, |
| kRDC_Mem_MRC7_0 = 39U, /**< GIC. Region resolution 4KB. */ |
| kRDC_Mem_MRC7_1 = 40U, |
| kRDC_Mem_MRC7_2 = 41U, |
| kRDC_Mem_MRC7_3 = 42U, |
| kRDC_Mem_MRC8_0 = 43U, /**< USBMIX. Region resolution 4KB. */ |
| kRDC_Mem_MRC8_1 = 44U, |
| kRDC_Mem_MRC8_2 = 45U, |
| kRDC_Mem_MRC8_3 = 46U, |
| kRDC_Mem_MRC9_0 = 47U, /**< GPU. Region resolution 4KB. */ |
| kRDC_Mem_MRC9_1 = 48U, |
| kRDC_Mem_MRC9_2 = 49U, |
| kRDC_Mem_MRC9_3 = 50U, |
| kRDC_Mem_MRC10_0 = 51U, /**< VPU(Decoder). Region resolution 4KB. */ |
| kRDC_Mem_MRC10_1 = 52U, |
| kRDC_Mem_MRC10_2 = 53U, |
| kRDC_Mem_MRC10_3 = 54U, |
| kRDC_Mem_MRC11_0 = 55U, /**< DEBUG(DAP). Region resolution 4KB. */ |
| kRDC_Mem_MRC11_1 = 56U, |
| kRDC_Mem_MRC11_2 = 57U, |
| kRDC_Mem_MRC11_3 = 58U, |
| kRDC_Mem_MRC12_0 = 59U, /**< DDRC(REG). Region resolution 4KB. */ |
| kRDC_Mem_MRC12_1 = 60U, |
| kRDC_Mem_MRC12_2 = 61U, |
| kRDC_Mem_MRC12_3 = 62U, |
| kRDC_Mem_MRC12_4 = 63U, |
| } rdc_mem_t; |
| |
| typedef enum _rdc_periph |
| { |
| kRDC_Periph_GPIO1 = 0U, /**< GPIO1 RDC Peripheral */ |
| kRDC_Periph_GPIO2 = 1U, /**< GPIO2 RDC Peripheral */ |
| kRDC_Periph_GPIO3 = 2U, /**< GPIO3 RDC Peripheral */ |
| kRDC_Periph_GPIO4 = 3U, /**< GPIO4 RDC Peripheral */ |
| kRDC_Periph_GPIO5 = 4U, /**< GPIO5 RDC Peripheral */ |
| kRDC_Periph_ANA_TSENSOR = 6U, /**< ANA_TSENSOR RDC Peripheral */ |
| kRDC_Periph_ANA_OSC = 7U, /**< ANA_OSC RDC Peripheral */ |
| kRDC_Periph_WDOG1 = 8U, /**< WDOG1 RDC Peripheral */ |
| kRDC_Periph_WDOG2 = 9U, /**< WDOG2 RDC Peripheral */ |
| kRDC_Periph_WDOG3 = 10U, /**< WDOG3 RDC Peripheral */ |
| kRDC_Periph_SDMA2 = 12U, /**< SDMA2 RDC Peripheral */ |
| kRDC_Periph_GPT1 = 13U, /**< GPT1 RDC Peripheral */ |
| kRDC_Periph_GPT2 = 14U, /**< GPT2 RDC Peripheral */ |
| kRDC_Periph_GPT3 = 15U, /**< GPT3 RDC Peripheral */ |
| kRDC_Periph_ROMCP = 17U, /**< ROMCP RDC Peripheral */ |
| kRDC_Periph_LCDIF = 18U, /**< LCDIF RDC Peripheral */ |
| kRDC_Periph_IOMUXC = 19U, /**< IOMUXC RDC Peripheral */ |
| kRDC_Periph_IOMUXC_GPR = 20U, /**< IOMUXC_GPR RDC Peripheral */ |
| kRDC_Periph_OCOTP_CTRL = 21U, /**< OCOTP_CTRL RDC Peripheral */ |
| kRDC_Periph_ANA_PLL = 22U, /**< ANA_PLL RDC Peripheral */ |
| kRDC_Periph_SNVS_HP = 23U, /**< SNVS_HP GPR RDC Peripheral */ |
| kRDC_Periph_CCM = 24U, /**< CCM RDC Peripheral */ |
| kRDC_Periph_SRC = 25U, /**< SRC RDC Peripheral */ |
| kRDC_Periph_GPC = 26U, /**< GPC RDC Peripheral */ |
| kRDC_Periph_SEMAPHORE1 = 27U, /**< SEMAPHORE1 RDC Peripheral */ |
| kRDC_Periph_SEMAPHORE2 = 28U, /**< SEMAPHORE2 RDC Peripheral */ |
| kRDC_Periph_RDC = 29U, /**< RDC RDC Peripheral */ |
| kRDC_Periph_CSU = 30U, /**< CSU RDC Peripheral */ |
| kRDC_Periph_DC_MST0 = 32U, /**< DC_MST0 RDC Peripheral */ |
| kRDC_Periph_DC_MST1 = 33U, /**< DC_MST1 RDC Peripheral */ |
| kRDC_Periph_DC_MST2 = 34U, /**< DC_MST2 RDC Peripheral */ |
| kRDC_Periph_DC_MST3 = 35U, /**< DC_MST3 RDC Peripheral */ |
| kRDC_Periph_HDMI_SEC = 36U, /**< HDMI_SEC RDC Peripheral */ |
| kRDC_Periph_PWM1 = 38U, /**< PWM1 RDC Peripheral */ |
| kRDC_Periph_PWM2 = 39U, /**< PWM2 RDC Peripheral */ |
| kRDC_Periph_PWM3 = 40U, /**< PWM3 RDC Peripheral */ |
| kRDC_Periph_PWM4 = 41U, /**< PWM4 RDC Peripheral */ |
| kRDC_Periph_SYS_COUNTER_RD = 42U, /**< System counter read RDC Peripheral */ |
| kRDC_Periph_SYS_COUNTER_CMP = 43U, /**< System counter compare RDC Peripheral */ |
| kRDC_Periph_SYS_COUNTER_CTRL = 44U, /**< System counter control RDC Peripheral */ |
| kRDC_Periph_HDMI_CTRL = 45U, /**< HDMI_CTRL RDC Peripheral */ |
| kRDC_Periph_GPT6 = 46U, /**< GPT6 RDC Peripheral */ |
| kRDC_Periph_GPT5 = 47U, /**< GPT5 RDC Peripheral */ |
| kRDC_Periph_GPT4 = 48U, /**< GPT4 RDC Peripheral */ |
| kRDC_Periph_TZASC = 56U, /**< TZASC RDC Peripheral */ |
| kRDC_Periph_MTR = 59U, /**< MTR RDC Peripheral */ |
| kRDC_Periph_PERFMON1 = 60U, /**< PERFMON1 RDC Peripheral */ |
| kRDC_Periph_PERFMON2 = 61U, /**< PERFMON2 RDC Peripheral */ |
| kRDC_Periph_PLATFORM_CTRL = 62U, /**< PLATFORM_CTRL RDC Peripheral */ |
| kRDC_Periph_QOSC = 63U, /**< QOSC RDC Peripheral */ |
| kRDC_Periph_MIPI_PHY = 64U, /**< MIPI_PHY RDC Peripheral */ |
| kRDC_Periph_MIPI_DSI = 65U, /**< MIPI_DSI RDC Peripheral */ |
| kRDC_Periph_I2C1 = 66U, /**< I2C1 RDC Peripheral */ |
| kRDC_Periph_I2C2 = 67U, /**< I2C2 RDC Peripheral */ |
| kRDC_Periph_I2C3 = 68U, /**< I2C3 RDC Peripheral */ |
| kRDC_Periph_I2C4 = 69U, /**< I2C4 RDC Peripheral */ |
| kRDC_Periph_UART4 = 70U, /**< UART4 RDC Peripheral */ |
| kRDC_Periph_MIPI_CSI1 = 71U, /**< MIPI_CSI1 RDC Peripheral */ |
| kRDC_Periph_MIPI_CSI_PHY1 = 72U, /**< MIPI_CSI_PHY1 RDC Peripheral */ |
| kRDC_Periph_CSI1 = 73U, /**< CSI1 RDC Peripheral */ |
| kRDC_Periph_MU_A = 74U, /**< MU_A RDC Peripheral */ |
| kRDC_Periph_MU_B = 75U, /**< MU_B RDC Peripheral */ |
| kRDC_Periph_SEMAPHORE_HS = 76U, /**< SEMAPHORE_HS RDC Peripheral */ |
| kRDC_Periph_SAI1 = 78U, /**< SAI1 RDC Peripheral */ |
| kRDC_Periph_SAI6 = 80U, /**< SAI6 RDC Peripheral */ |
| kRDC_Periph_SAI5 = 81U, /**< SAI5 RDC Peripheral */ |
| kRDC_Periph_SAI4 = 82U, /**< SAI4 RDC Peripheral */ |
| kRDC_Periph_USDHC1 = 84U, /**< USDHC1 RDC Peripheral */ |
| kRDC_Periph_USDHC2 = 85U, /**< USDHC2 RDC Peripheral */ |
| kRDC_Periph_MIPI_CSI2 = 86U, /**< MIPI_CSI2 RDC Peripheral */ |
| kRDC_Periph_MIPI_CSI_PHY2 = 87U, /**< MIPI_CSI_PHY2 RDC Peripheral */ |
| kRDC_Periph_CSI2 = 88U, /**< CSI2 RDC Peripheral */ |
| kRDC_Periph_SPBA2 = 90U, /**< SPBA2 RDC Peripheral */ |
| kRDC_Periph_QSPI = 91U, /**< QSPI RDC Peripheral */ |
| kRDC_Periph_SDMA1 = 93U, /**< SDMA1 RDC Peripheral */ |
| kRDC_Periph_ENET1 = 94U, /**< ENET1 RDC Peripheral */ |
| kRDC_Periph_SPDIF1 = 97U, /**< SPDIF1 RDC Peripheral */ |
| kRDC_Periph_ECSPI1 = 98U, /**< ECSPI1 RDC Peripheral */ |
| kRDC_Periph_ECSPI2 = 99U, /**< ECSPI2 RDC Peripheral */ |
| kRDC_Periph_ECSPI3 = 100U, /**< ECSPI3 RDC Peripheral */ |
| kRDC_Periph_UART1 = 102U, /**< UART1 RDC Peripheral */ |
| kRDC_Periph_UART3 = 104U, /**< UART3 RDC Peripheral */ |
| kRDC_Periph_UART2 = 105U, /**< UART2 RDC Peripheral */ |
| kRDC_Periph_SPDIF2 = 106U, /**< SPDIF2 RDC Peripheral */ |
| kRDC_Periph_SAI2 = 107U, /**< SAI2 RDC Peripheral */ |
| kRDC_Periph_SAI3 = 108U, /**< SAI3 RDC Peripheral */ |
| kRDC_Periph_SPBA1 = 111U, /**< SPBA1 RDC Peripheral */ |
| kRDC_Periph_CAAM = 114U, /**< CAAM RDC Peripheral */ |
| } rdc_periph_t; |
| |
| /* @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group Mapping_Information */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- Device Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup Peripheral_access_layer Device Peripheral Access Layer |
| * @{ |
| */ |
| |
| |
| /* |
| ** Start of section using anonymous unions |
| */ |
| |
| #if defined(__ARMCC_VERSION) |
| #if (__ARMCC_VERSION >= 6010050) |
| #pragma clang diagnostic push |
| #else |
| #pragma push |
| #pragma anon_unions |
| #endif |
| #elif defined(__GNUC__) |
| /* anonymous unions are enabled by default */ |
| #elif defined(__IAR_SYSTEMS_ICC__) |
| #pragma language=extended |
| #else |
| #error Not supported compiler type |
| #endif |
| |
| /* ---------------------------------------------------------------------------- |
| -- AIPSTZ Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** AIPSTZ - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t MPR; /**< MPR, offset: 0x0 */ |
| uint8_t RESERVED_0[60]; |
| __IO uint32_t OPACR; /**< OPACR, offset: 0x40 */ |
| __IO uint32_t OPACR1; /**< OPACR1, offset: 0x44 */ |
| __IO uint32_t OPACR2; /**< OPACR2, offset: 0x48 */ |
| __IO uint32_t OPACR3; /**< OPACR3, offset: 0x4C */ |
| __IO uint32_t OPACR4; /**< OPACR4, offset: 0x50 */ |
| } AIPSTZ_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- AIPSTZ Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks |
| * @{ |
| */ |
| |
| /*! @name MPR - MPR */ |
| /*! @{ */ |
| #define AIPSTZ_MPR_MPROT5_MASK (0xF00U) |
| #define AIPSTZ_MPR_MPROT5_SHIFT (8U) |
| #define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK) |
| #define AIPSTZ_MPR_MPROT3_MASK (0xF0000U) |
| #define AIPSTZ_MPR_MPROT3_SHIFT (16U) |
| #define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK) |
| #define AIPSTZ_MPR_MPROT2_MASK (0xF00000U) |
| #define AIPSTZ_MPR_MPROT2_SHIFT (20U) |
| #define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK) |
| #define AIPSTZ_MPR_MPROT1_MASK (0xF000000U) |
| #define AIPSTZ_MPR_MPROT1_SHIFT (24U) |
| #define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK) |
| #define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) |
| #define AIPSTZ_MPR_MPROT0_SHIFT (28U) |
| #define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) |
| /*! @} */ |
| |
| /*! @name OPACR - OPACR */ |
| /*! @{ */ |
| #define AIPSTZ_OPACR_OPAC7_MASK (0xFU) |
| #define AIPSTZ_OPACR_OPAC7_SHIFT (0U) |
| #define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK) |
| #define AIPSTZ_OPACR_OPAC6_MASK (0xF0U) |
| #define AIPSTZ_OPACR_OPAC6_SHIFT (4U) |
| #define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK) |
| #define AIPSTZ_OPACR_OPAC5_MASK (0xF00U) |
| #define AIPSTZ_OPACR_OPAC5_SHIFT (8U) |
| #define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK) |
| #define AIPSTZ_OPACR_OPAC4_MASK (0xF000U) |
| #define AIPSTZ_OPACR_OPAC4_SHIFT (12U) |
| #define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK) |
| #define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U) |
| #define AIPSTZ_OPACR_OPAC3_SHIFT (16U) |
| #define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK) |
| #define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U) |
| #define AIPSTZ_OPACR_OPAC2_SHIFT (20U) |
| #define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK) |
| #define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U) |
| #define AIPSTZ_OPACR_OPAC1_SHIFT (24U) |
| #define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK) |
| #define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U) |
| #define AIPSTZ_OPACR_OPAC0_SHIFT (28U) |
| #define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK) |
| /*! @} */ |
| |
| /*! @name OPACR1 - OPACR1 */ |
| /*! @{ */ |
| #define AIPSTZ_OPACR1_OPAC15_MASK (0xFU) |
| #define AIPSTZ_OPACR1_OPAC15_SHIFT (0U) |
| #define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK) |
| #define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U) |
| #define AIPSTZ_OPACR1_OPAC14_SHIFT (4U) |
| #define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK) |
| #define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U) |
| #define AIPSTZ_OPACR1_OPAC13_SHIFT (8U) |
| #define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK) |
| #define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U) |
| #define AIPSTZ_OPACR1_OPAC12_SHIFT (12U) |
| #define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK) |
| #define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U) |
| #define AIPSTZ_OPACR1_OPAC11_SHIFT (16U) |
| #define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK) |
| #define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U) |
| #define AIPSTZ_OPACR1_OPAC10_SHIFT (20U) |
| #define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK) |
| #define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U) |
| #define AIPSTZ_OPACR1_OPAC9_SHIFT (24U) |
| #define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK) |
| #define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U) |
| #define AIPSTZ_OPACR1_OPAC8_SHIFT (28U) |
| #define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK) |
| /*! @} */ |
| |
| /*! @name OPACR2 - OPACR2 */ |
| /*! @{ */ |
| #define AIPSTZ_OPACR2_OPAC23_MASK (0xFU) |
| #define AIPSTZ_OPACR2_OPAC23_SHIFT (0U) |
| #define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK) |
| #define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U) |
| #define AIPSTZ_OPACR2_OPAC22_SHIFT (4U) |
| #define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK) |
| #define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U) |
| #define AIPSTZ_OPACR2_OPAC21_SHIFT (8U) |
| #define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK) |
| #define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U) |
| #define AIPSTZ_OPACR2_OPAC20_SHIFT (12U) |
| #define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK) |
| #define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U) |
| #define AIPSTZ_OPACR2_OPAC19_SHIFT (16U) |
| #define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK) |
| #define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U) |
| #define AIPSTZ_OPACR2_OPAC18_SHIFT (20U) |
| #define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK) |
| #define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U) |
| #define AIPSTZ_OPACR2_OPAC17_SHIFT (24U) |
| #define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK) |
| #define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U) |
| #define AIPSTZ_OPACR2_OPAC16_SHIFT (28U) |
| #define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK) |
| /*! @} */ |
| |
| /*! @name OPACR3 - OPACR3 */ |
| /*! @{ */ |
| #define AIPSTZ_OPACR3_OPAC31_MASK (0xFU) |
| #define AIPSTZ_OPACR3_OPAC31_SHIFT (0U) |
| #define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK) |
| #define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U) |
| #define AIPSTZ_OPACR3_OPAC30_SHIFT (4U) |
| #define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK) |
| #define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U) |
| #define AIPSTZ_OPACR3_OPAC29_SHIFT (8U) |
| #define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK) |
| #define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U) |
| #define AIPSTZ_OPACR3_OPAC28_SHIFT (12U) |
| #define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK) |
| #define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U) |
| #define AIPSTZ_OPACR3_OPAC27_SHIFT (16U) |
| #define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK) |
| #define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U) |
| #define AIPSTZ_OPACR3_OPAC26_SHIFT (20U) |
| #define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK) |
| #define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U) |
| #define AIPSTZ_OPACR3_OPAC25_SHIFT (24U) |
| #define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK) |
| #define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U) |
| #define AIPSTZ_OPACR3_OPAC24_SHIFT (28U) |
| #define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK) |
| /*! @} */ |
| |
| /*! @name OPACR4 - OPACR4 */ |
| /*! @{ */ |
| #define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U) |
| #define AIPSTZ_OPACR4_OPAC33_SHIFT (24U) |
| #define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK) |
| #define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U) |
| #define AIPSTZ_OPACR4_OPAC32_SHIFT (28U) |
| #define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group AIPSTZ_Register_Masks */ |
| |
| |
| /* AIPSTZ - Peripheral instance base addresses */ |
| /** Peripheral AIPSTZ1 base address */ |
| #define AIPSTZ1_BASE (0x301F0000u) |
| /** Peripheral AIPSTZ1 base pointer */ |
| #define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE) |
| /** Peripheral AIPSTZ2 base address */ |
| #define AIPSTZ2_BASE (0x305F0000u) |
| /** Peripheral AIPSTZ2 base pointer */ |
| #define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE) |
| /** Peripheral AIPSTZ3 base address */ |
| #define AIPSTZ3_BASE (0x309F0000u) |
| /** Peripheral AIPSTZ3 base pointer */ |
| #define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE) |
| /** Peripheral AIPSTZ4 base address */ |
| #define AIPSTZ4_BASE (0x32DF0000u) |
| /** Peripheral AIPSTZ4 base pointer */ |
| #define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE) |
| /** Array initializer of AIPSTZ peripheral base addresses */ |
| #define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE } |
| /** Array initializer of AIPSTZ peripheral base pointers */ |
| #define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 } |
| |
| /*! |
| * @} |
| */ /* end of group AIPSTZ_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- APBH Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** APBH - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t CTRL0; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */ |
| __IO uint32_t CTRL0_SET; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */ |
| __IO uint32_t CTRL0_CLR; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */ |
| __IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */ |
| __IO uint32_t CTRL1; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */ |
| __IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */ |
| __IO uint32_t CTRL1_CLR; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */ |
| __IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */ |
| __IO uint32_t CTRL2; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */ |
| __IO uint32_t CTRL2_SET; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */ |
| __IO uint32_t CTRL2_CLR; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */ |
| __IO uint32_t CTRL2_TOG; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */ |
| __IO uint32_t CHANNEL_CTRL; /**< AHB to APBH Bridge Channel Register, offset: 0x30 */ |
| __IO uint32_t CHANNEL_CTRL_SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */ |
| __IO uint32_t CHANNEL_CTRL_CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */ |
| __IO uint32_t CHANNEL_CTRL_TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */ |
| __I uint32_t DEVSEL; /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */ |
| uint8_t RESERVED_0[12]; |
| __IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */ |
| uint8_t RESERVED_1[12]; |
| __IO uint32_t DEBUGr; /**< AHB to APBH DMA Debug Register, offset: 0x60 */ |
| uint8_t RESERVED_2[156]; |
| __I uint32_t CH0_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x100 */ |
| uint8_t RESERVED_3[12]; |
| __IO uint32_t CH0_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x110 */ |
| uint8_t RESERVED_4[12]; |
| __I uint32_t CH0_CMD; /**< APBH DMA Channel n Command Register, offset: 0x120 */ |
| uint8_t RESERVED_5[12]; |
| __I uint32_t CH0_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x130 */ |
| uint8_t RESERVED_6[12]; |
| __IO uint32_t CH0_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x140 */ |
| uint8_t RESERVED_7[12]; |
| __I uint32_t CH0_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x150 */ |
| uint8_t RESERVED_8[12]; |
| __I uint32_t CH0_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x160 */ |
| uint8_t RESERVED_9[12]; |
| __I uint32_t CH1_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x170 */ |
| uint8_t RESERVED_10[12]; |
| __IO uint32_t CH1_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x180 */ |
| uint8_t RESERVED_11[12]; |
| __I uint32_t CH1_CMD; /**< APBH DMA Channel n Command Register, offset: 0x190 */ |
| uint8_t RESERVED_12[12]; |
| __I uint32_t CH1_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x1A0 */ |
| uint8_t RESERVED_13[12]; |
| __IO uint32_t CH1_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x1B0 */ |
| uint8_t RESERVED_14[12]; |
| __I uint32_t CH1_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x1C0 */ |
| uint8_t RESERVED_15[12]; |
| __I uint32_t CH1_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x1D0 */ |
| uint8_t RESERVED_16[12]; |
| __I uint32_t CH2_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x1E0 */ |
| uint8_t RESERVED_17[12]; |
| __IO uint32_t CH2_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x1F0 */ |
| uint8_t RESERVED_18[12]; |
| __I uint32_t CH2_CMD; /**< APBH DMA Channel n Command Register, offset: 0x200 */ |
| uint8_t RESERVED_19[12]; |
| __I uint32_t CH2_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x210 */ |
| uint8_t RESERVED_20[12]; |
| __IO uint32_t CH2_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x220 */ |
| uint8_t RESERVED_21[12]; |
| __I uint32_t CH2_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x230 */ |
| uint8_t RESERVED_22[12]; |
| __I uint32_t CH2_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x240 */ |
| uint8_t RESERVED_23[12]; |
| __I uint32_t CH3_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x250 */ |
| uint8_t RESERVED_24[12]; |
| __IO uint32_t CH3_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x260 */ |
| uint8_t RESERVED_25[12]; |
| __I uint32_t CH3_CMD; /**< APBH DMA Channel n Command Register, offset: 0x270 */ |
| uint8_t RESERVED_26[12]; |
| __I uint32_t CH3_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x280 */ |
| uint8_t RESERVED_27[12]; |
| __IO uint32_t CH3_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x290 */ |
| uint8_t RESERVED_28[12]; |
| __I uint32_t CH3_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x2A0 */ |
| uint8_t RESERVED_29[12]; |
| __I uint32_t CH3_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x2B0 */ |
| uint8_t RESERVED_30[12]; |
| __I uint32_t CH4_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x2C0 */ |
| uint8_t RESERVED_31[12]; |
| __IO uint32_t CH4_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x2D0 */ |
| uint8_t RESERVED_32[12]; |
| __I uint32_t CH4_CMD; /**< APBH DMA Channel n Command Register, offset: 0x2E0 */ |
| uint8_t RESERVED_33[12]; |
| __I uint32_t CH4_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x2F0 */ |
| uint8_t RESERVED_34[12]; |
| __IO uint32_t CH4_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x300 */ |
| uint8_t RESERVED_35[12]; |
| __I uint32_t CH4_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x310 */ |
| uint8_t RESERVED_36[12]; |
| __I uint32_t CH4_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x320 */ |
| uint8_t RESERVED_37[12]; |
| __I uint32_t CH5_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x330 */ |
| uint8_t RESERVED_38[12]; |
| __IO uint32_t CH5_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x340 */ |
| uint8_t RESERVED_39[12]; |
| __I uint32_t CH5_CMD; /**< APBH DMA Channel n Command Register, offset: 0x350 */ |
| uint8_t RESERVED_40[12]; |
| __I uint32_t CH5_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x360 */ |
| uint8_t RESERVED_41[12]; |
| __IO uint32_t CH5_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x370 */ |
| uint8_t RESERVED_42[12]; |
| __I uint32_t CH5_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x380 */ |
| uint8_t RESERVED_43[12]; |
| __I uint32_t CH5_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x390 */ |
| uint8_t RESERVED_44[12]; |
| __I uint32_t CH6_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x3A0 */ |
| uint8_t RESERVED_45[12]; |
| __IO uint32_t CH6_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x3B0 */ |
| uint8_t RESERVED_46[12]; |
| __I uint32_t CH6_CMD; /**< APBH DMA Channel n Command Register, offset: 0x3C0 */ |
| uint8_t RESERVED_47[12]; |
| __I uint32_t CH6_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x3D0 */ |
| uint8_t RESERVED_48[12]; |
| __IO uint32_t CH6_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x3E0 */ |
| uint8_t RESERVED_49[12]; |
| __I uint32_t CH6_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x3F0 */ |
| uint8_t RESERVED_50[12]; |
| __I uint32_t CH6_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x400 */ |
| uint8_t RESERVED_51[12]; |
| __I uint32_t CH7_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x410 */ |
| uint8_t RESERVED_52[12]; |
| __IO uint32_t CH7_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x420 */ |
| uint8_t RESERVED_53[12]; |
| __I uint32_t CH7_CMD; /**< APBH DMA Channel n Command Register, offset: 0x430 */ |
| uint8_t RESERVED_54[12]; |
| __I uint32_t CH7_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x440 */ |
| uint8_t RESERVED_55[12]; |
| __IO uint32_t CH7_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x450 */ |
| uint8_t RESERVED_56[12]; |
| __I uint32_t CH7_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x460 */ |
| uint8_t RESERVED_57[12]; |
| __I uint32_t CH7_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x470 */ |
| uint8_t RESERVED_58[12]; |
| __I uint32_t CH8_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x480 */ |
| uint8_t RESERVED_59[12]; |
| __IO uint32_t CH8_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x490 */ |
| uint8_t RESERVED_60[12]; |
| __I uint32_t CH8_CMD; /**< APBH DMA Channel n Command Register, offset: 0x4A0 */ |
| uint8_t RESERVED_61[12]; |
| __I uint32_t CH8_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x4B0 */ |
| uint8_t RESERVED_62[12]; |
| __IO uint32_t CH8_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x4C0 */ |
| uint8_t RESERVED_63[12]; |
| __I uint32_t CH8_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x4D0 */ |
| uint8_t RESERVED_64[12]; |
| __I uint32_t CH8_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x4E0 */ |
| uint8_t RESERVED_65[12]; |
| __I uint32_t CH9_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x4F0 */ |
| uint8_t RESERVED_66[12]; |
| __IO uint32_t CH9_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x500 */ |
| uint8_t RESERVED_67[12]; |
| __I uint32_t CH9_CMD; /**< APBH DMA Channel n Command Register, offset: 0x510 */ |
| uint8_t RESERVED_68[12]; |
| __I uint32_t CH9_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x520 */ |
| uint8_t RESERVED_69[12]; |
| __IO uint32_t CH9_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x530 */ |
| uint8_t RESERVED_70[12]; |
| __I uint32_t CH9_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x540 */ |
| uint8_t RESERVED_71[12]; |
| __I uint32_t CH9_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x550 */ |
| uint8_t RESERVED_72[12]; |
| __I uint32_t CH10_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x560 */ |
| uint8_t RESERVED_73[12]; |
| __IO uint32_t CH10_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x570 */ |
| uint8_t RESERVED_74[12]; |
| __I uint32_t CH10_CMD; /**< APBH DMA Channel n Command Register, offset: 0x580 */ |
| uint8_t RESERVED_75[12]; |
| __I uint32_t CH10_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x590 */ |
| uint8_t RESERVED_76[12]; |
| __IO uint32_t CH10_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x5A0 */ |
| uint8_t RESERVED_77[12]; |
| __I uint32_t CH10_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x5B0 */ |
| uint8_t RESERVED_78[12]; |
| __I uint32_t CH10_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x5C0 */ |
| uint8_t RESERVED_79[12]; |
| __I uint32_t CH11_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x5D0 */ |
| uint8_t RESERVED_80[12]; |
| __IO uint32_t CH11_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x5E0 */ |
| uint8_t RESERVED_81[12]; |
| __I uint32_t CH11_CMD; /**< APBH DMA Channel n Command Register, offset: 0x5F0 */ |
| uint8_t RESERVED_82[12]; |
| __I uint32_t CH11_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x600 */ |
| uint8_t RESERVED_83[12]; |
| __IO uint32_t CH11_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x610 */ |
| uint8_t RESERVED_84[12]; |
| __I uint32_t CH11_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x620 */ |
| uint8_t RESERVED_85[12]; |
| __I uint32_t CH11_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x630 */ |
| uint8_t RESERVED_86[12]; |
| __I uint32_t CH12_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x640 */ |
| uint8_t RESERVED_87[12]; |
| __IO uint32_t CH12_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x650 */ |
| uint8_t RESERVED_88[12]; |
| __I uint32_t CH12_CMD; /**< APBH DMA Channel n Command Register, offset: 0x660 */ |
| uint8_t RESERVED_89[12]; |
| __I uint32_t CH12_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x670 */ |
| uint8_t RESERVED_90[12]; |
| __IO uint32_t CH12_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x680 */ |
| uint8_t RESERVED_91[12]; |
| __I uint32_t CH12_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x690 */ |
| uint8_t RESERVED_92[12]; |
| __I uint32_t CH12_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x6A0 */ |
| uint8_t RESERVED_93[12]; |
| __I uint32_t CH13_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x6B0 */ |
| uint8_t RESERVED_94[12]; |
| __IO uint32_t CH13_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x6C0 */ |
| uint8_t RESERVED_95[12]; |
| __I uint32_t CH13_CMD; /**< APBH DMA Channel n Command Register, offset: 0x6D0 */ |
| uint8_t RESERVED_96[12]; |
| __I uint32_t CH13_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x6E0 */ |
| uint8_t RESERVED_97[12]; |
| __IO uint32_t CH13_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x6F0 */ |
| uint8_t RESERVED_98[12]; |
| __I uint32_t CH13_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x700 */ |
| uint8_t RESERVED_99[12]; |
| __I uint32_t CH13_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x710 */ |
| uint8_t RESERVED_100[12]; |
| __I uint32_t CH14_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x720 */ |
| uint8_t RESERVED_101[12]; |
| __IO uint32_t CH14_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x730 */ |
| uint8_t RESERVED_102[12]; |
| __I uint32_t CH14_CMD; /**< APBH DMA Channel n Command Register, offset: 0x740 */ |
| uint8_t RESERVED_103[12]; |
| __I uint32_t CH14_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x750 */ |
| uint8_t RESERVED_104[12]; |
| __IO uint32_t CH14_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x760 */ |
| uint8_t RESERVED_105[12]; |
| __I uint32_t CH14_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x770 */ |
| uint8_t RESERVED_106[12]; |
| __I uint32_t CH14_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x780 */ |
| uint8_t RESERVED_107[12]; |
| __I uint32_t CH15_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x790 */ |
| uint8_t RESERVED_108[12]; |
| __IO uint32_t CH15_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x7A0 */ |
| uint8_t RESERVED_109[12]; |
| __I uint32_t CH15_CMD; /**< APBH DMA Channel n Command Register, offset: 0x7B0 */ |
| uint8_t RESERVED_110[12]; |
| __I uint32_t CH15_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x7C0 */ |
| uint8_t RESERVED_111[12]; |
| __IO uint32_t CH15_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x7D0 */ |
| uint8_t RESERVED_112[12]; |
| __I uint32_t CH15_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x7E0 */ |
| uint8_t RESERVED_113[12]; |
| __I uint32_t CH15_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x7F0 */ |
| uint8_t RESERVED_114[12]; |
| __I uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */ |
| } APBH_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- APBH Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup APBH_Register_Masks APBH Register Masks |
| * @{ |
| */ |
| |
| /*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */ |
| /*! @{ */ |
| #define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xFFFFU) |
| #define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT (0U) |
| /*! CLKGATE_CHANNEL |
| * 0b0000000000000001..NAND0 |
| * 0b0000000000000010..NAND1 |
| * 0b0000000000000100..NAND2 |
| * 0b0000000000001000..NAND3 |
| * 0b0000000000010000..NAND4 |
| * 0b0000000000100000..NAND5 |
| * 0b0000000001000000..NAND6 |
| * 0b0000000010000000..NAND7 |
| * 0b0000000100000000..SSP |
| */ |
| #define APBH_CTRL0_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK) |
| #define APBH_CTRL0_RSVD0_MASK (0xFFF0000U) |
| #define APBH_CTRL0_RSVD0_SHIFT (16U) |
| #define APBH_CTRL0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_RSVD0_SHIFT)) & APBH_CTRL0_RSVD0_MASK) |
| #define APBH_CTRL0_APB_BURST_EN_MASK (0x10000000U) |
| #define APBH_CTRL0_APB_BURST_EN_SHIFT (28U) |
| #define APBH_CTRL0_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK) |
| #define APBH_CTRL0_AHB_BURST8_EN_MASK (0x20000000U) |
| #define APBH_CTRL0_AHB_BURST8_EN_SHIFT (29U) |
| #define APBH_CTRL0_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK) |
| #define APBH_CTRL0_CLKGATE_MASK (0x40000000U) |
| #define APBH_CTRL0_CLKGATE_SHIFT (30U) |
| #define APBH_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK) |
| #define APBH_CTRL0_SFTRST_MASK (0x80000000U) |
| #define APBH_CTRL0_SFTRST_SHIFT (31U) |
| #define APBH_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL0_SET - AHB to APBH Bridge Control and Status Register 0 */ |
| /*! @{ */ |
| #define APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK (0xFFFFU) |
| #define APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT (0U) |
| /*! CLKGATE_CHANNEL |
| * 0b0000000000000001..NAND0 |
| * 0b0000000000000010..NAND1 |
| * 0b0000000000000100..NAND2 |
| * 0b0000000000001000..NAND3 |
| * 0b0000000000010000..NAND4 |
| * 0b0000000000100000..NAND5 |
| * 0b0000000001000000..NAND6 |
| * 0b0000000010000000..NAND7 |
| * 0b0000000100000000..SSP |
| */ |
| #define APBH_CTRL0_SET_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK) |
| #define APBH_CTRL0_SET_RSVD0_MASK (0xFFF0000U) |
| #define APBH_CTRL0_SET_RSVD0_SHIFT (16U) |
| #define APBH_CTRL0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_RSVD0_SHIFT)) & APBH_CTRL0_SET_RSVD0_MASK) |
| #define APBH_CTRL0_SET_APB_BURST_EN_MASK (0x10000000U) |
| #define APBH_CTRL0_SET_APB_BURST_EN_SHIFT (28U) |
| #define APBH_CTRL0_SET_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_APB_BURST_EN_SHIFT)) & APBH_CTRL0_SET_APB_BURST_EN_MASK) |
| #define APBH_CTRL0_SET_AHB_BURST8_EN_MASK (0x20000000U) |
| #define APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT (29U) |
| #define APBH_CTRL0_SET_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_SET_AHB_BURST8_EN_MASK) |
| #define APBH_CTRL0_SET_CLKGATE_MASK (0x40000000U) |
| #define APBH_CTRL0_SET_CLKGATE_SHIFT (30U) |
| #define APBH_CTRL0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_SHIFT)) & APBH_CTRL0_SET_CLKGATE_MASK) |
| #define APBH_CTRL0_SET_SFTRST_MASK (0x80000000U) |
| #define APBH_CTRL0_SET_SFTRST_SHIFT (31U) |
| #define APBH_CTRL0_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_SFTRST_SHIFT)) & APBH_CTRL0_SET_SFTRST_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL0_CLR - AHB to APBH Bridge Control and Status Register 0 */ |
| /*! @{ */ |
| #define APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK (0xFFFFU) |
| #define APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT (0U) |
| /*! CLKGATE_CHANNEL |
| * 0b0000000000000001..NAND0 |
| * 0b0000000000000010..NAND1 |
| * 0b0000000000000100..NAND2 |
| * 0b0000000000001000..NAND3 |
| * 0b0000000000010000..NAND4 |
| * 0b0000000000100000..NAND5 |
| * 0b0000000001000000..NAND6 |
| * 0b0000000010000000..NAND7 |
| * 0b0000000100000000..SSP |
| */ |
| #define APBH_CTRL0_CLR_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK) |
| #define APBH_CTRL0_CLR_RSVD0_MASK (0xFFF0000U) |
| #define APBH_CTRL0_CLR_RSVD0_SHIFT (16U) |
| #define APBH_CTRL0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_RSVD0_SHIFT)) & APBH_CTRL0_CLR_RSVD0_MASK) |
| #define APBH_CTRL0_CLR_APB_BURST_EN_MASK (0x10000000U) |
| #define APBH_CTRL0_CLR_APB_BURST_EN_SHIFT (28U) |
| #define APBH_CTRL0_CLR_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_APB_BURST_EN_SHIFT)) & APBH_CTRL0_CLR_APB_BURST_EN_MASK) |
| #define APBH_CTRL0_CLR_AHB_BURST8_EN_MASK (0x20000000U) |
| #define APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT (29U) |
| #define APBH_CTRL0_CLR_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_CLR_AHB_BURST8_EN_MASK) |
| #define APBH_CTRL0_CLR_CLKGATE_MASK (0x40000000U) |
| #define APBH_CTRL0_CLR_CLKGATE_SHIFT (30U) |
| #define APBH_CTRL0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_MASK) |
| #define APBH_CTRL0_CLR_SFTRST_MASK (0x80000000U) |
| #define APBH_CTRL0_CLR_SFTRST_SHIFT (31U) |
| #define APBH_CTRL0_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_SFTRST_SHIFT)) & APBH_CTRL0_CLR_SFTRST_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL0_TOG - AHB to APBH Bridge Control and Status Register 0 */ |
| /*! @{ */ |
| #define APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK (0xFFFFU) |
| #define APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT (0U) |
| /*! CLKGATE_CHANNEL |
| * 0b0000000000000001..NAND0 |
| * 0b0000000000000010..NAND1 |
| * 0b0000000000000100..NAND2 |
| * 0b0000000000001000..NAND3 |
| * 0b0000000000010000..NAND4 |
| * 0b0000000000100000..NAND5 |
| * 0b0000000001000000..NAND6 |
| * 0b0000000010000000..NAND7 |
| * 0b0000000100000000..SSP |
| */ |
| #define APBH_CTRL0_TOG_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK) |
| #define APBH_CTRL0_TOG_RSVD0_MASK (0xFFF0000U) |
| #define APBH_CTRL0_TOG_RSVD0_SHIFT (16U) |
| #define APBH_CTRL0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_RSVD0_SHIFT)) & APBH_CTRL0_TOG_RSVD0_MASK) |
| #define APBH_CTRL0_TOG_APB_BURST_EN_MASK (0x10000000U) |
| #define APBH_CTRL0_TOG_APB_BURST_EN_SHIFT (28U) |
| #define APBH_CTRL0_TOG_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_APB_BURST_EN_SHIFT)) & APBH_CTRL0_TOG_APB_BURST_EN_MASK) |
| #define APBH_CTRL0_TOG_AHB_BURST8_EN_MASK (0x20000000U) |
| #define APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT (29U) |
| #define APBH_CTRL0_TOG_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_TOG_AHB_BURST8_EN_MASK) |
| #define APBH_CTRL0_TOG_CLKGATE_MASK (0x40000000U) |
| #define APBH_CTRL0_TOG_CLKGATE_SHIFT (30U) |
| #define APBH_CTRL0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_MASK) |
| #define APBH_CTRL0_TOG_SFTRST_MASK (0x80000000U) |
| #define APBH_CTRL0_TOG_SFTRST_SHIFT (31U) |
| #define APBH_CTRL0_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_SFTRST_SHIFT)) & APBH_CTRL0_TOG_SFTRST_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */ |
| /*! @{ */ |
| #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK (0x1U) |
| #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT (0U) |
| #define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK (0x2U) |
| #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT (1U) |
| #define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK (0x4U) |
| #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT (2U) |
| #define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK (0x8U) |
| #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT (3U) |
| #define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK (0x10U) |
| #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT (4U) |
| #define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK (0x20U) |
| #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT (5U) |
| #define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK (0x40U) |
| #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT (6U) |
| #define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK (0x80U) |
| #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT (7U) |
| #define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK (0x100U) |
| #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT (8U) |
| #define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK (0x200U) |
| #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT (9U) |
| #define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK (0x400U) |
| #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT (10U) |
| #define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK (0x800U) |
| #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT (11U) |
| #define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK (0x1000U) |
| #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT (12U) |
| #define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK (0x2000U) |
| #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT (13U) |
| #define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK (0x4000U) |
| #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT (14U) |
| #define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK (0x8000U) |
| #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT (15U) |
| #define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) |
| #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) |
| #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) |
| #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) |
| #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) |
| #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) |
| #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) |
| #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) |
| #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) |
| #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) |
| #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) |
| #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) |
| #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) |
| #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) |
| #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) |
| #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) |
| #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) |
| #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) |
| #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) |
| #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) |
| #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) |
| #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) |
| #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) |
| #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) |
| #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) |
| #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) |
| #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) |
| #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) |
| #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) |
| #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) |
| #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) |
| #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) |
| #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL1_SET - AHB to APBH Bridge Control and Status Register 1 */ |
| /*! @{ */ |
| #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK (0x1U) |
| #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT (0U) |
| #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK (0x2U) |
| #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT (1U) |
| #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK (0x4U) |
| #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT (2U) |
| #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK (0x8U) |
| #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT (3U) |
| #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK (0x10U) |
| #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT (4U) |
| #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK (0x20U) |
| #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT (5U) |
| #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK (0x40U) |
| #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT (6U) |
| #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK (0x80U) |
| #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT (7U) |
| #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK (0x100U) |
| #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT (8U) |
| #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK (0x200U) |
| #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT (9U) |
| #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK (0x400U) |
| #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT (10U) |
| #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK (0x800U) |
| #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT (11U) |
| #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK (0x1000U) |
| #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT (12U) |
| #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK (0x2000U) |
| #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT (13U) |
| #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK (0x4000U) |
| #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT (14U) |
| #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK (0x8000U) |
| #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT (15U) |
| #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) |
| #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) |
| #define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) |
| #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) |
| #define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) |
| #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) |
| #define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) |
| #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) |
| #define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) |
| #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) |
| #define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) |
| #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) |
| #define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) |
| #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) |
| #define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) |
| #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) |
| #define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) |
| #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) |
| #define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) |
| #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) |
| #define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) |
| #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) |
| #define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) |
| #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) |
| #define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) |
| #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) |
| #define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) |
| #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) |
| #define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) |
| #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) |
| #define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) |
| #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) |
| #define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL1_CLR - AHB to APBH Bridge Control and Status Register 1 */ |
| /*! @{ */ |
| #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK (0x1U) |
| #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT (0U) |
| #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK (0x2U) |
| #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT (1U) |
| #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK (0x4U) |
| #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT (2U) |
| #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK (0x8U) |
| #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT (3U) |
| #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK (0x10U) |
| #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT (4U) |
| #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK (0x20U) |
| #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT (5U) |
| #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK (0x40U) |
| #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT (6U) |
| #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK (0x80U) |
| #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT (7U) |
| #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK (0x100U) |
| #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT (8U) |
| #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK (0x200U) |
| #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT (9U) |
| #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK (0x400U) |
| #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT (10U) |
| #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK (0x800U) |
| #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT (11U) |
| #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK (0x1000U) |
| #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT (12U) |
| #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK (0x2000U) |
| #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT (13U) |
| #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK (0x4000U) |
| #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT (14U) |
| #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK (0x8000U) |
| #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT (15U) |
| #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) |
| #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) |
| #define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) |
| #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) |
| #define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) |
| #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) |
| #define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) |
| #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) |
| #define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) |
| #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) |
| #define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) |
| #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) |
| #define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) |
| #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) |
| #define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) |
| #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) |
| #define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) |
| #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) |
| #define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) |
| #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) |
| #define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) |
| #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) |
| #define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) |
| #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) |
| #define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) |
| #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) |
| #define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) |
| #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) |
| #define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) |
| #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) |
| #define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) |
| #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) |
| #define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL1_TOG - AHB to APBH Bridge Control and Status Register 1 */ |
| /*! @{ */ |
| #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK (0x1U) |
| #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT (0U) |
| #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK (0x2U) |
| #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT (1U) |
| #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK (0x4U) |
| #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT (2U) |
| #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK (0x8U) |
| #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT (3U) |
| #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK (0x10U) |
| #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT (4U) |
| #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK (0x20U) |
| #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT (5U) |
| #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK (0x40U) |
| #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT (6U) |
| #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK (0x80U) |
| #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT (7U) |
| #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK (0x100U) |
| #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT (8U) |
| #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK (0x200U) |
| #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT (9U) |
| #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK (0x400U) |
| #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT (10U) |
| #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK (0x800U) |
| #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT (11U) |
| #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK (0x1000U) |
| #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT (12U) |
| #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK (0x2000U) |
| #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT (13U) |
| #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK (0x4000U) |
| #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT (14U) |
| #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK (0x8000U) |
| #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT (15U) |
| #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK) |
| #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) |
| #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) |
| #define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) |
| #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) |
| #define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) |
| #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) |
| #define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) |
| #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) |
| #define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) |
| #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) |
| #define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) |
| #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) |
| #define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) |
| #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) |
| #define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) |
| #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) |
| #define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) |
| #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) |
| #define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) |
| #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) |
| #define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) |
| #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) |
| #define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) |
| #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) |
| #define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) |
| #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) |
| #define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) |
| #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) |
| #define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) |
| #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) |
| #define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK) |
| #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) |
| #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) |
| #define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */ |
| /*! @{ */ |
| #define APBH_CTRL2_CH0_ERROR_IRQ_MASK (0x1U) |
| #define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT (0U) |
| #define APBH_CTRL2_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CH1_ERROR_IRQ_MASK (0x2U) |
| #define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT (1U) |
| #define APBH_CTRL2_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CH2_ERROR_IRQ_MASK (0x4U) |
| #define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT (2U) |
| #define APBH_CTRL2_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CH3_ERROR_IRQ_MASK (0x8U) |
| #define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT (3U) |
| #define APBH_CTRL2_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CH4_ERROR_IRQ_MASK (0x10U) |
| #define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT (4U) |
| #define APBH_CTRL2_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CH5_ERROR_IRQ_MASK (0x20U) |
| #define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT (5U) |
| #define APBH_CTRL2_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CH6_ERROR_IRQ_MASK (0x40U) |
| #define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT (6U) |
| #define APBH_CTRL2_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CH7_ERROR_IRQ_MASK (0x80U) |
| #define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT (7U) |
| #define APBH_CTRL2_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CH8_ERROR_IRQ_MASK (0x100U) |
| #define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT (8U) |
| #define APBH_CTRL2_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CH9_ERROR_IRQ_MASK (0x200U) |
| #define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT (9U) |
| #define APBH_CTRL2_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CH10_ERROR_IRQ_MASK (0x400U) |
| #define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT (10U) |
| #define APBH_CTRL2_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CH11_ERROR_IRQ_MASK (0x800U) |
| #define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT (11U) |
| #define APBH_CTRL2_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CH12_ERROR_IRQ_MASK (0x1000U) |
| #define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT (12U) |
| #define APBH_CTRL2_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CH13_ERROR_IRQ_MASK (0x2000U) |
| #define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT (13U) |
| #define APBH_CTRL2_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CH14_ERROR_IRQ_MASK (0x4000U) |
| #define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT (14U) |
| #define APBH_CTRL2_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CH15_ERROR_IRQ_MASK (0x8000U) |
| #define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT (15U) |
| #define APBH_CTRL2_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CH0_ERROR_STATUS_MASK (0x10000U) |
| #define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT (16U) |
| /*! CH0_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CH1_ERROR_STATUS_MASK (0x20000U) |
| #define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT (17U) |
| /*! CH1_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CH2_ERROR_STATUS_MASK (0x40000U) |
| #define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT (18U) |
| /*! CH2_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CH3_ERROR_STATUS_MASK (0x80000U) |
| #define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT (19U) |
| /*! CH3_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CH4_ERROR_STATUS_MASK (0x100000U) |
| #define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT (20U) |
| /*! CH4_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CH5_ERROR_STATUS_MASK (0x200000U) |
| #define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT (21U) |
| /*! CH5_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CH6_ERROR_STATUS_MASK (0x400000U) |
| #define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT (22U) |
| /*! CH6_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CH7_ERROR_STATUS_MASK (0x800000U) |
| #define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT (23U) |
| /*! CH7_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CH8_ERROR_STATUS_MASK (0x1000000U) |
| #define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT (24U) |
| /*! CH8_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CH9_ERROR_STATUS_MASK (0x2000000U) |
| #define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT (25U) |
| /*! CH9_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CH10_ERROR_STATUS_MASK (0x4000000U) |
| #define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT (26U) |
| /*! CH10_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CH11_ERROR_STATUS_MASK (0x8000000U) |
| #define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT (27U) |
| /*! CH11_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CH12_ERROR_STATUS_MASK (0x10000000U) |
| #define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT (28U) |
| /*! CH12_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CH13_ERROR_STATUS_MASK (0x20000000U) |
| #define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT (29U) |
| /*! CH13_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CH14_ERROR_STATUS_MASK (0x40000000U) |
| #define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT (30U) |
| /*! CH14_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CH15_ERROR_STATUS_MASK (0x80000000U) |
| #define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT (31U) |
| /*! CH15_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL2_SET - AHB to APBH Bridge Control and Status Register 2 */ |
| /*! @{ */ |
| #define APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK (0x1U) |
| #define APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT (0U) |
| #define APBH_CTRL2_SET_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK (0x2U) |
| #define APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT (1U) |
| #define APBH_CTRL2_SET_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK (0x4U) |
| #define APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT (2U) |
| #define APBH_CTRL2_SET_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK (0x8U) |
| #define APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT (3U) |
| #define APBH_CTRL2_SET_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK (0x10U) |
| #define APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT (4U) |
| #define APBH_CTRL2_SET_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK (0x20U) |
| #define APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT (5U) |
| #define APBH_CTRL2_SET_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK (0x40U) |
| #define APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT (6U) |
| #define APBH_CTRL2_SET_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK (0x80U) |
| #define APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT (7U) |
| #define APBH_CTRL2_SET_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK (0x100U) |
| #define APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT (8U) |
| #define APBH_CTRL2_SET_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK (0x200U) |
| #define APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT (9U) |
| #define APBH_CTRL2_SET_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK (0x400U) |
| #define APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT (10U) |
| #define APBH_CTRL2_SET_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK (0x800U) |
| #define APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT (11U) |
| #define APBH_CTRL2_SET_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK (0x1000U) |
| #define APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT (12U) |
| #define APBH_CTRL2_SET_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK (0x2000U) |
| #define APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT (13U) |
| #define APBH_CTRL2_SET_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK (0x4000U) |
| #define APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT (14U) |
| #define APBH_CTRL2_SET_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK (0x8000U) |
| #define APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT (15U) |
| #define APBH_CTRL2_SET_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK (0x10000U) |
| #define APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT (16U) |
| /*! CH0_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_SET_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK (0x20000U) |
| #define APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT (17U) |
| /*! CH1_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_SET_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK (0x40000U) |
| #define APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT (18U) |
| /*! CH2_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_SET_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK (0x80000U) |
| #define APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT (19U) |
| /*! CH3_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_SET_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK (0x100000U) |
| #define APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT (20U) |
| /*! CH4_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_SET_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK (0x200000U) |
| #define APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT (21U) |
| /*! CH5_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_SET_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK (0x400000U) |
| #define APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT (22U) |
| /*! CH6_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_SET_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK (0x800000U) |
| #define APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT (23U) |
| /*! CH7_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_SET_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK (0x1000000U) |
| #define APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT (24U) |
| /*! CH8_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_SET_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK (0x2000000U) |
| #define APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT (25U) |
| /*! CH9_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_SET_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK (0x4000000U) |
| #define APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT (26U) |
| /*! CH10_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_SET_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK (0x8000000U) |
| #define APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT (27U) |
| /*! CH11_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_SET_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK (0x10000000U) |
| #define APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT (28U) |
| /*! CH12_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_SET_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK (0x20000000U) |
| #define APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT (29U) |
| /*! CH13_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_SET_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK (0x40000000U) |
| #define APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT (30U) |
| /*! CH14_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_SET_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK (0x80000000U) |
| #define APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT (31U) |
| /*! CH15_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_SET_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL2_CLR - AHB to APBH Bridge Control and Status Register 2 */ |
| /*! @{ */ |
| #define APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK (0x1U) |
| #define APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT (0U) |
| #define APBH_CTRL2_CLR_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK (0x2U) |
| #define APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT (1U) |
| #define APBH_CTRL2_CLR_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK (0x4U) |
| #define APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT (2U) |
| #define APBH_CTRL2_CLR_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK (0x8U) |
| #define APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT (3U) |
| #define APBH_CTRL2_CLR_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK (0x10U) |
| #define APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT (4U) |
| #define APBH_CTRL2_CLR_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK (0x20U) |
| #define APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT (5U) |
| #define APBH_CTRL2_CLR_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK (0x40U) |
| #define APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT (6U) |
| #define APBH_CTRL2_CLR_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK (0x80U) |
| #define APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT (7U) |
| #define APBH_CTRL2_CLR_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK (0x100U) |
| #define APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT (8U) |
| #define APBH_CTRL2_CLR_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK (0x200U) |
| #define APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT (9U) |
| #define APBH_CTRL2_CLR_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK (0x400U) |
| #define APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT (10U) |
| #define APBH_CTRL2_CLR_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK (0x800U) |
| #define APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT (11U) |
| #define APBH_CTRL2_CLR_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK (0x1000U) |
| #define APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT (12U) |
| #define APBH_CTRL2_CLR_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK (0x2000U) |
| #define APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT (13U) |
| #define APBH_CTRL2_CLR_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK (0x4000U) |
| #define APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT (14U) |
| #define APBH_CTRL2_CLR_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK (0x8000U) |
| #define APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT (15U) |
| #define APBH_CTRL2_CLR_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK (0x10000U) |
| #define APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT (16U) |
| /*! CH0_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CLR_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK (0x20000U) |
| #define APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT (17U) |
| /*! CH1_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CLR_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK (0x40000U) |
| #define APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT (18U) |
| /*! CH2_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CLR_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK (0x80000U) |
| #define APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT (19U) |
| /*! CH3_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CLR_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK (0x100000U) |
| #define APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT (20U) |
| /*! CH4_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CLR_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK (0x200000U) |
| #define APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT (21U) |
| /*! CH5_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CLR_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK (0x400000U) |
| #define APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT (22U) |
| /*! CH6_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CLR_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK (0x800000U) |
| #define APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT (23U) |
| /*! CH7_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CLR_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK (0x1000000U) |
| #define APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT (24U) |
| /*! CH8_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CLR_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK (0x2000000U) |
| #define APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT (25U) |
| /*! CH9_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CLR_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK (0x4000000U) |
| #define APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT (26U) |
| /*! CH10_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CLR_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK (0x8000000U) |
| #define APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT (27U) |
| /*! CH11_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CLR_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK (0x10000000U) |
| #define APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT (28U) |
| /*! CH12_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CLR_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK (0x20000000U) |
| #define APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT (29U) |
| /*! CH13_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CLR_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK (0x40000000U) |
| #define APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT (30U) |
| /*! CH14_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CLR_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK (0x80000000U) |
| #define APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT (31U) |
| /*! CH15_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_CLR_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL2_TOG - AHB to APBH Bridge Control and Status Register 2 */ |
| /*! @{ */ |
| #define APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK (0x1U) |
| #define APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT (0U) |
| #define APBH_CTRL2_TOG_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK (0x2U) |
| #define APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT (1U) |
| #define APBH_CTRL2_TOG_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK (0x4U) |
| #define APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT (2U) |
| #define APBH_CTRL2_TOG_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK (0x8U) |
| #define APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT (3U) |
| #define APBH_CTRL2_TOG_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK (0x10U) |
| #define APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT (4U) |
| #define APBH_CTRL2_TOG_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK (0x20U) |
| #define APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT (5U) |
| #define APBH_CTRL2_TOG_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK (0x40U) |
| #define APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT (6U) |
| #define APBH_CTRL2_TOG_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK (0x80U) |
| #define APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT (7U) |
| #define APBH_CTRL2_TOG_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK (0x100U) |
| #define APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT (8U) |
| #define APBH_CTRL2_TOG_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK (0x200U) |
| #define APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT (9U) |
| #define APBH_CTRL2_TOG_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK (0x400U) |
| #define APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT (10U) |
| #define APBH_CTRL2_TOG_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK (0x800U) |
| #define APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT (11U) |
| #define APBH_CTRL2_TOG_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK (0x1000U) |
| #define APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT (12U) |
| #define APBH_CTRL2_TOG_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK (0x2000U) |
| #define APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT (13U) |
| #define APBH_CTRL2_TOG_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK (0x4000U) |
| #define APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT (14U) |
| #define APBH_CTRL2_TOG_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK (0x8000U) |
| #define APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT (15U) |
| #define APBH_CTRL2_TOG_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK) |
| #define APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK (0x10000U) |
| #define APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT (16U) |
| /*! CH0_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_TOG_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK (0x20000U) |
| #define APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT (17U) |
| /*! CH1_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_TOG_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK (0x40000U) |
| #define APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT (18U) |
| /*! CH2_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_TOG_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK (0x80000U) |
| #define APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT (19U) |
| /*! CH3_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_TOG_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK (0x100000U) |
| #define APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT (20U) |
| /*! CH4_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_TOG_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK (0x200000U) |
| #define APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT (21U) |
| /*! CH5_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_TOG_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK (0x400000U) |
| #define APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT (22U) |
| /*! CH6_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_TOG_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK (0x800000U) |
| #define APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT (23U) |
| /*! CH7_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_TOG_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK (0x1000000U) |
| #define APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT (24U) |
| /*! CH8_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_TOG_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK (0x2000000U) |
| #define APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT (25U) |
| /*! CH9_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_TOG_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK (0x4000000U) |
| #define APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT (26U) |
| /*! CH10_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_TOG_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK (0x8000000U) |
| #define APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT (27U) |
| /*! CH11_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_TOG_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK (0x10000000U) |
| #define APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT (28U) |
| /*! CH12_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_TOG_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK (0x20000000U) |
| #define APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT (29U) |
| /*! CH13_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_TOG_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK (0x40000000U) |
| #define APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT (30U) |
| /*! CH14_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_TOG_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK) |
| #define APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK (0x80000000U) |
| #define APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT (31U) |
| /*! CH15_ERROR_STATUS |
| * 0b0..An early termination from the device causes error IRQ. |
| * 0b1..An AHB bus error causes error IRQ. |
| */ |
| #define APBH_CTRL2_TOG_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK) |
| /*! @} */ |
| |
| /*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */ |
| /*! @{ */ |
| #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK (0xFFFFU) |
| #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT (0U) |
| /*! FREEZE_CHANNEL |
| * 0b0000000000000001..NAND0 |
| * 0b0000000000000010..NAND1 |
| * 0b0000000000000100..NAND2 |
| * 0b0000000000001000..NAND3 |
| * 0b0000000000010000..NAND4 |
| * 0b0000000000100000..NAND5 |
| * 0b0000000001000000..NAND6 |
| * 0b0000000010000000..NAND7 |
| * 0b0000000100000000..SSP |
| */ |
| #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK) |
| #define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xFFFF0000U) |
| #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT (16U) |
| /*! RESET_CHANNEL |
| * 0b0000000000000001..NAND0 |
| * 0b0000000000000010..NAND1 |
| * 0b0000000000000100..NAND2 |
| * 0b0000000000001000..NAND3 |
| * 0b0000000000010000..NAND4 |
| * 0b0000000000100000..NAND5 |
| * 0b0000000001000000..NAND6 |
| * 0b0000000010000000..NAND7 |
| * 0b0000000100000000..SSP |
| */ |
| #define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK) |
| /*! @} */ |
| |
| /*! @name CHANNEL_CTRL_SET - AHB to APBH Bridge Channel Register */ |
| /*! @{ */ |
| #define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK (0xFFFFU) |
| #define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT (0U) |
| /*! FREEZE_CHANNEL |
| * 0b0000000000000001..NAND0 |
| * 0b0000000000000010..NAND1 |
| * 0b0000000000000100..NAND2 |
| * 0b0000000000001000..NAND3 |
| * 0b0000000000010000..NAND4 |
| * 0b0000000000100000..NAND5 |
| * 0b0000000001000000..NAND6 |
| * 0b0000000010000000..NAND7 |
| * 0b0000000100000000..SSP |
| */ |
| #define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK) |
| #define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK (0xFFFF0000U) |
| #define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT (16U) |
| /*! RESET_CHANNEL |
| * 0b0000000000000001..NAND0 |
| * 0b0000000000000010..NAND1 |
| * 0b0000000000000100..NAND2 |
| * 0b0000000000001000..NAND3 |
| * 0b0000000000010000..NAND4 |
| * 0b0000000000100000..NAND5 |
| * 0b0000000001000000..NAND6 |
| * 0b0000000010000000..NAND7 |
| * 0b0000000100000000..SSP |
| */ |
| #define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK) |
| /*! @} */ |
| |
| /*! @name CHANNEL_CTRL_CLR - AHB to APBH Bridge Channel Register */ |
| /*! @{ */ |
| #define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK (0xFFFFU) |
| #define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT (0U) |
| /*! FREEZE_CHANNEL |
| * 0b0000000000000001..NAND0 |
| * 0b0000000000000010..NAND1 |
| * 0b0000000000000100..NAND2 |
| * 0b0000000000001000..NAND3 |
| * 0b0000000000010000..NAND4 |
| * 0b0000000000100000..NAND5 |
| * 0b0000000001000000..NAND6 |
| * 0b0000000010000000..NAND7 |
| * 0b0000000100000000..SSP |
| */ |
| #define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK) |
| #define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK (0xFFFF0000U) |
| #define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT (16U) |
| /*! RESET_CHANNEL |
| * 0b0000000000000001..NAND0 |
| * 0b0000000000000010..NAND1 |
| * 0b0000000000000100..NAND2 |
| * 0b0000000000001000..NAND3 |
| * 0b0000000000010000..NAND4 |
| * 0b0000000000100000..NAND5 |
| * 0b0000000001000000..NAND6 |
| * 0b0000000010000000..NAND7 |
| * 0b0000000100000000..SSP |
| */ |
| #define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK) |
| /*! @} */ |
| |
| /*! @name CHANNEL_CTRL_TOG - AHB to APBH Bridge Channel Register */ |
| /*! @{ */ |
| #define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK (0xFFFFU) |
| #define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT (0U) |
| /*! FREEZE_CHANNEL |
| * 0b0000000000000001..NAND0 |
| * 0b0000000000000010..NAND1 |
| * 0b0000000000000100..NAND2 |
| * 0b0000000000001000..NAND3 |
| * 0b0000000000010000..NAND4 |
| * 0b0000000000100000..NAND5 |
| * 0b0000000001000000..NAND6 |
| * 0b0000000010000000..NAND7 |
| * 0b0000000100000000..SSP |
| */ |
| #define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK) |
| #define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK (0xFFFF0000U) |
| #define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT (16U) |
| /*! RESET_CHANNEL |
| * 0b0000000000000001..NAND0 |
| * 0b0000000000000010..NAND1 |
| * 0b0000000000000100..NAND2 |
| * 0b0000000000001000..NAND3 |
| * 0b0000000000010000..NAND4 |
| * 0b0000000000100000..NAND5 |
| * 0b0000000001000000..NAND6 |
| * 0b0000000010000000..NAND7 |
| * 0b0000000100000000..SSP |
| */ |
| #define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK) |
| /*! @} */ |
| |
| /*! @name DEVSEL - AHB to APBH DMA Device Assignment Register */ |
| /*! @{ */ |
| #define APBH_DEVSEL_CH0_MASK (0x3U) |
| #define APBH_DEVSEL_CH0_SHIFT (0U) |
| #define APBH_DEVSEL_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH0_SHIFT)) & APBH_DEVSEL_CH0_MASK) |
| #define APBH_DEVSEL_CH1_MASK (0xCU) |
| #define APBH_DEVSEL_CH1_SHIFT (2U) |
| #define APBH_DEVSEL_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH1_SHIFT)) & APBH_DEVSEL_CH1_MASK) |
| #define APBH_DEVSEL_CH2_MASK (0x30U) |
| #define APBH_DEVSEL_CH2_SHIFT (4U) |
| #define APBH_DEVSEL_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH2_SHIFT)) & APBH_DEVSEL_CH2_MASK) |
| #define APBH_DEVSEL_CH3_MASK (0xC0U) |
| #define APBH_DEVSEL_CH3_SHIFT (6U) |
| #define APBH_DEVSEL_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH3_SHIFT)) & APBH_DEVSEL_CH3_MASK) |
| #define APBH_DEVSEL_CH4_MASK (0x300U) |
| #define APBH_DEVSEL_CH4_SHIFT (8U) |
| #define APBH_DEVSEL_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH4_SHIFT)) & APBH_DEVSEL_CH4_MASK) |
| #define APBH_DEVSEL_CH5_MASK (0xC00U) |
| #define APBH_DEVSEL_CH5_SHIFT (10U) |
| #define APBH_DEVSEL_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH5_SHIFT)) & APBH_DEVSEL_CH5_MASK) |
| #define APBH_DEVSEL_CH6_MASK (0x3000U) |
| #define APBH_DEVSEL_CH6_SHIFT (12U) |
| #define APBH_DEVSEL_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH6_SHIFT)) & APBH_DEVSEL_CH6_MASK) |
| #define APBH_DEVSEL_CH7_MASK (0xC000U) |
| #define APBH_DEVSEL_CH7_SHIFT (14U) |
| #define APBH_DEVSEL_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH7_SHIFT)) & APBH_DEVSEL_CH7_MASK) |
| #define APBH_DEVSEL_CH8_MASK (0x30000U) |
| #define APBH_DEVSEL_CH8_SHIFT (16U) |
| #define APBH_DEVSEL_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH8_SHIFT)) & APBH_DEVSEL_CH8_MASK) |
| #define APBH_DEVSEL_CH9_MASK (0xC0000U) |
| #define APBH_DEVSEL_CH9_SHIFT (18U) |
| #define APBH_DEVSEL_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH9_SHIFT)) & APBH_DEVSEL_CH9_MASK) |
| #define APBH_DEVSEL_CH10_MASK (0x300000U) |
| #define APBH_DEVSEL_CH10_SHIFT (20U) |
| #define APBH_DEVSEL_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH10_SHIFT)) & APBH_DEVSEL_CH10_MASK) |
| #define APBH_DEVSEL_CH11_MASK (0xC00000U) |
| #define APBH_DEVSEL_CH11_SHIFT (22U) |
| #define APBH_DEVSEL_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH11_SHIFT)) & APBH_DEVSEL_CH11_MASK) |
| #define APBH_DEVSEL_CH12_MASK (0x3000000U) |
| #define APBH_DEVSEL_CH12_SHIFT (24U) |
| #define APBH_DEVSEL_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH12_SHIFT)) & APBH_DEVSEL_CH12_MASK) |
| #define APBH_DEVSEL_CH13_MASK (0xC000000U) |
| #define APBH_DEVSEL_CH13_SHIFT (26U) |
| #define APBH_DEVSEL_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH13_SHIFT)) & APBH_DEVSEL_CH13_MASK) |
| #define APBH_DEVSEL_CH14_MASK (0x30000000U) |
| #define APBH_DEVSEL_CH14_SHIFT (28U) |
| #define APBH_DEVSEL_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH14_SHIFT)) & APBH_DEVSEL_CH14_MASK) |
| #define APBH_DEVSEL_CH15_MASK (0xC0000000U) |
| #define APBH_DEVSEL_CH15_SHIFT (30U) |
| #define APBH_DEVSEL_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH15_SHIFT)) & APBH_DEVSEL_CH15_MASK) |
| /*! @} */ |
| |
| /*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */ |
| /*! @{ */ |
| #define APBH_DMA_BURST_SIZE_CH0_MASK (0x3U) |
| #define APBH_DMA_BURST_SIZE_CH0_SHIFT (0U) |
| #define APBH_DMA_BURST_SIZE_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK) |
| #define APBH_DMA_BURST_SIZE_CH1_MASK (0xCU) |
| #define APBH_DMA_BURST_SIZE_CH1_SHIFT (2U) |
| #define APBH_DMA_BURST_SIZE_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK) |
| #define APBH_DMA_BURST_SIZE_CH2_MASK (0x30U) |
| #define APBH_DMA_BURST_SIZE_CH2_SHIFT (4U) |
| #define APBH_DMA_BURST_SIZE_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK) |
| #define APBH_DMA_BURST_SIZE_CH3_MASK (0xC0U) |
| #define APBH_DMA_BURST_SIZE_CH3_SHIFT (6U) |
| #define APBH_DMA_BURST_SIZE_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK) |
| #define APBH_DMA_BURST_SIZE_CH4_MASK (0x300U) |
| #define APBH_DMA_BURST_SIZE_CH4_SHIFT (8U) |
| #define APBH_DMA_BURST_SIZE_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK) |
| #define APBH_DMA_BURST_SIZE_CH5_MASK (0xC00U) |
| #define APBH_DMA_BURST_SIZE_CH5_SHIFT (10U) |
| #define APBH_DMA_BURST_SIZE_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK) |
| #define APBH_DMA_BURST_SIZE_CH6_MASK (0x3000U) |
| #define APBH_DMA_BURST_SIZE_CH6_SHIFT (12U) |
| #define APBH_DMA_BURST_SIZE_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK) |
| #define APBH_DMA_BURST_SIZE_CH7_MASK (0xC000U) |
| #define APBH_DMA_BURST_SIZE_CH7_SHIFT (14U) |
| #define APBH_DMA_BURST_SIZE_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK) |
| #define APBH_DMA_BURST_SIZE_CH8_MASK (0x30000U) |
| #define APBH_DMA_BURST_SIZE_CH8_SHIFT (16U) |
| /*! CH8 |
| * 0b00..BURST0 |
| * 0b01..BURST4 |
| * 0b10..BURST8 |
| */ |
| #define APBH_DMA_BURST_SIZE_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK) |
| #define APBH_DMA_BURST_SIZE_CH9_MASK (0xC0000U) |
| #define APBH_DMA_BURST_SIZE_CH9_SHIFT (18U) |
| #define APBH_DMA_BURST_SIZE_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH9_SHIFT)) & APBH_DMA_BURST_SIZE_CH9_MASK) |
| #define APBH_DMA_BURST_SIZE_CH10_MASK (0x300000U) |
| #define APBH_DMA_BURST_SIZE_CH10_SHIFT (20U) |
| #define APBH_DMA_BURST_SIZE_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH10_SHIFT)) & APBH_DMA_BURST_SIZE_CH10_MASK) |
| #define APBH_DMA_BURST_SIZE_CH11_MASK (0xC00000U) |
| #define APBH_DMA_BURST_SIZE_CH11_SHIFT (22U) |
| #define APBH_DMA_BURST_SIZE_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH11_SHIFT)) & APBH_DMA_BURST_SIZE_CH11_MASK) |
| #define APBH_DMA_BURST_SIZE_CH12_MASK (0x3000000U) |
| #define APBH_DMA_BURST_SIZE_CH12_SHIFT (24U) |
| #define APBH_DMA_BURST_SIZE_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH12_SHIFT)) & APBH_DMA_BURST_SIZE_CH12_MASK) |
| #define APBH_DMA_BURST_SIZE_CH13_MASK (0xC000000U) |
| #define APBH_DMA_BURST_SIZE_CH13_SHIFT (26U) |
| #define APBH_DMA_BURST_SIZE_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH13_SHIFT)) & APBH_DMA_BURST_SIZE_CH13_MASK) |
| #define APBH_DMA_BURST_SIZE_CH14_MASK (0x30000000U) |
| #define APBH_DMA_BURST_SIZE_CH14_SHIFT (28U) |
| #define APBH_DMA_BURST_SIZE_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH14_SHIFT)) & APBH_DMA_BURST_SIZE_CH14_MASK) |
| #define APBH_DMA_BURST_SIZE_CH15_MASK (0xC0000000U) |
| #define APBH_DMA_BURST_SIZE_CH15_SHIFT (30U) |
| #define APBH_DMA_BURST_SIZE_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH15_SHIFT)) & APBH_DMA_BURST_SIZE_CH15_MASK) |
| /*! @} */ |
| |
| /*! @name DEBUG - AHB to APBH DMA Debug Register */ |
| /*! @{ */ |
| #define APBH_DEBUG_GPMI_ONE_FIFO_MASK (0x1U) |
| #define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT (0U) |
| #define APBH_DEBUG_GPMI_ONE_FIFO(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK) |
| /*! @} */ |
| |
| /*! @name CH0_CURCMDAR - APBH DMA Channel n Current Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH0_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH0_CURCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH0_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH0_CURCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH0_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH0_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH0_NXTCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH0_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH0_NXTCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH0_CMD - APBH DMA Channel n Command Register */ |
| /*! @{ */ |
| #define APBH_CH0_CMD_COMMAND_MASK (0x3U) |
| #define APBH_CH0_CMD_COMMAND_SHIFT (0U) |
| /*! COMMAND |
| * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. |
| * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. |
| * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. |
| * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. |
| */ |
| #define APBH_CH0_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_COMMAND_SHIFT)) & APBH_CH0_CMD_COMMAND_MASK) |
| #define APBH_CH0_CMD_CHAIN_MASK (0x4U) |
| #define APBH_CH0_CMD_CHAIN_SHIFT (2U) |
| #define APBH_CH0_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_CHAIN_SHIFT)) & APBH_CH0_CMD_CHAIN_MASK) |
| #define APBH_CH0_CMD_IRQONCMPLT_MASK (0x8U) |
| #define APBH_CH0_CMD_IRQONCMPLT_SHIFT (3U) |
| #define APBH_CH0_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_IRQONCMPLT_SHIFT)) & APBH_CH0_CMD_IRQONCMPLT_MASK) |
| #define APBH_CH0_CMD_NANDLOCK_MASK (0x10U) |
| #define APBH_CH0_CMD_NANDLOCK_SHIFT (4U) |
| #define APBH_CH0_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_NANDLOCK_SHIFT)) & APBH_CH0_CMD_NANDLOCK_MASK) |
| #define APBH_CH0_CMD_NANDWAIT4READY_MASK (0x20U) |
| #define APBH_CH0_CMD_NANDWAIT4READY_SHIFT (5U) |
| #define APBH_CH0_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH0_CMD_NANDWAIT4READY_MASK) |
| #define APBH_CH0_CMD_SEMAPHORE_MASK (0x40U) |
| #define APBH_CH0_CMD_SEMAPHORE_SHIFT (6U) |
| #define APBH_CH0_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_SEMAPHORE_SHIFT)) & APBH_CH0_CMD_SEMAPHORE_MASK) |
| #define APBH_CH0_CMD_WAIT4ENDCMD_MASK (0x80U) |
| #define APBH_CH0_CMD_WAIT4ENDCMD_SHIFT (7U) |
| #define APBH_CH0_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH0_CMD_WAIT4ENDCMD_MASK) |
| #define APBH_CH0_CMD_HALTONTERMINATE_MASK (0x100U) |
| #define APBH_CH0_CMD_HALTONTERMINATE_SHIFT (8U) |
| #define APBH_CH0_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH0_CMD_HALTONTERMINATE_MASK) |
| #define APBH_CH0_CMD_CMDWORDS_MASK (0xF000U) |
| #define APBH_CH0_CMD_CMDWORDS_SHIFT (12U) |
| #define APBH_CH0_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_CMDWORDS_SHIFT)) & APBH_CH0_CMD_CMDWORDS_MASK) |
| #define APBH_CH0_CMD_XFER_COUNT_MASK (0xFFFF0000U) |
| #define APBH_CH0_CMD_XFER_COUNT_SHIFT (16U) |
| #define APBH_CH0_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_XFER_COUNT_SHIFT)) & APBH_CH0_CMD_XFER_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name CH0_BAR - APBH DMA Channel n Buffer Address Register */ |
| /*! @{ */ |
| #define APBH_CH0_BAR_ADDRESS_MASK (0xFFFFFFFFU) |
| #define APBH_CH0_BAR_ADDRESS_SHIFT (0U) |
| #define APBH_CH0_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_BAR_ADDRESS_SHIFT)) & APBH_CH0_BAR_ADDRESS_MASK) |
| /*! @} */ |
| |
| /*! @name CH0_SEMA - APBH DMA Channel n Semaphore Register */ |
| /*! @{ */ |
| #define APBH_CH0_SEMA_INCREMENT_SEMA_MASK (0xFFU) |
| #define APBH_CH0_SEMA_INCREMENT_SEMA_SHIFT (0U) |
| #define APBH_CH0_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH0_SEMA_INCREMENT_SEMA_MASK) |
| #define APBH_CH0_SEMA_PHORE_MASK (0xFF0000U) |
| #define APBH_CH0_SEMA_PHORE_SHIFT (16U) |
| #define APBH_CH0_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_SEMA_PHORE_SHIFT)) & APBH_CH0_SEMA_PHORE_MASK) |
| /*! @} */ |
| |
| /*! @name CH0_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH0_DEBUG1_STATEMACHINE_MASK (0x1FU) |
| #define APBH_CH0_DEBUG1_STATEMACHINE_SHIFT (0U) |
| /*! STATEMACHINE |
| * 0b00000..This is the idle state of the DMA state machine. |
| * 0b00001..State in which the DMA is waiting to receive the first word of a command. |
| * 0b00010..State in which the DMA is waiting to receive the third word of a command. |
| * 0b00011..State in which the DMA is waiting to receive the second word of a command. |
| * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. |
| * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. |
| * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. |
| * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. |
| * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. |
| * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. |
| * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. |
| * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. |
| * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. |
| * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. |
| * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. |
| * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state |
| * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. |
| * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. |
| */ |
| #define APBH_CH0_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH0_DEBUG1_STATEMACHINE_MASK) |
| #define APBH_CH0_DEBUG1_RSVD1_MASK (0xFFFE0U) |
| #define APBH_CH0_DEBUG1_RSVD1_SHIFT (5U) |
| #define APBH_CH0_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RSVD1_SHIFT)) & APBH_CH0_DEBUG1_RSVD1_MASK) |
| #define APBH_CH0_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) |
| #define APBH_CH0_DEBUG1_WR_FIFO_FULL_SHIFT (20U) |
| #define APBH_CH0_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH0_DEBUG1_WR_FIFO_FULL_MASK) |
| #define APBH_CH0_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) |
| #define APBH_CH0_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) |
| #define APBH_CH0_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH0_DEBUG1_WR_FIFO_EMPTY_MASK) |
| #define APBH_CH0_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) |
| #define APBH_CH0_DEBUG1_RD_FIFO_FULL_SHIFT (22U) |
| #define APBH_CH0_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH0_DEBUG1_RD_FIFO_FULL_MASK) |
| #define APBH_CH0_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) |
| #define APBH_CH0_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) |
| #define APBH_CH0_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH0_DEBUG1_RD_FIFO_EMPTY_MASK) |
| #define APBH_CH0_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) |
| #define APBH_CH0_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) |
| #define APBH_CH0_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH0_DEBUG1_NEXTCMDADDRVALID_MASK) |
| #define APBH_CH0_DEBUG1_LOCK_MASK (0x2000000U) |
| #define APBH_CH0_DEBUG1_LOCK_SHIFT (25U) |
| #define APBH_CH0_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_LOCK_SHIFT)) & APBH_CH0_DEBUG1_LOCK_MASK) |
| #define APBH_CH0_DEBUG1_READY_MASK (0x4000000U) |
| #define APBH_CH0_DEBUG1_READY_SHIFT (26U) |
| #define APBH_CH0_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_READY_SHIFT)) & APBH_CH0_DEBUG1_READY_MASK) |
| #define APBH_CH0_DEBUG1_SENSE_MASK (0x8000000U) |
| #define APBH_CH0_DEBUG1_SENSE_SHIFT (27U) |
| #define APBH_CH0_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_SENSE_SHIFT)) & APBH_CH0_DEBUG1_SENSE_MASK) |
| #define APBH_CH0_DEBUG1_END_MASK (0x10000000U) |
| #define APBH_CH0_DEBUG1_END_SHIFT (28U) |
| #define APBH_CH0_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_END_SHIFT)) & APBH_CH0_DEBUG1_END_MASK) |
| #define APBH_CH0_DEBUG1_KICK_MASK (0x20000000U) |
| #define APBH_CH0_DEBUG1_KICK_SHIFT (29U) |
| #define APBH_CH0_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_KICK_SHIFT)) & APBH_CH0_DEBUG1_KICK_MASK) |
| #define APBH_CH0_DEBUG1_BURST_MASK (0x40000000U) |
| #define APBH_CH0_DEBUG1_BURST_SHIFT (30U) |
| #define APBH_CH0_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_BURST_SHIFT)) & APBH_CH0_DEBUG1_BURST_MASK) |
| #define APBH_CH0_DEBUG1_REQ_MASK (0x80000000U) |
| #define APBH_CH0_DEBUG1_REQ_SHIFT (31U) |
| #define APBH_CH0_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_REQ_SHIFT)) & APBH_CH0_DEBUG1_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name CH0_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH0_DEBUG2_AHB_BYTES_MASK (0xFFFFU) |
| #define APBH_CH0_DEBUG2_AHB_BYTES_SHIFT (0U) |
| #define APBH_CH0_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH0_DEBUG2_AHB_BYTES_MASK) |
| #define APBH_CH0_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) |
| #define APBH_CH0_DEBUG2_APB_BYTES_SHIFT (16U) |
| #define APBH_CH0_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH0_DEBUG2_APB_BYTES_MASK) |
| /*! @} */ |
| |
| /*! @name CH1_CURCMDAR - APBH DMA Channel n Current Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH1_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH1_CURCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH1_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH1_CURCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH1_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH1_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH1_NXTCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH1_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH1_NXTCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH1_CMD - APBH DMA Channel n Command Register */ |
| /*! @{ */ |
| #define APBH_CH1_CMD_COMMAND_MASK (0x3U) |
| #define APBH_CH1_CMD_COMMAND_SHIFT (0U) |
| /*! COMMAND |
| * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. |
| * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. |
| * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. |
| * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. |
| */ |
| #define APBH_CH1_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_COMMAND_SHIFT)) & APBH_CH1_CMD_COMMAND_MASK) |
| #define APBH_CH1_CMD_CHAIN_MASK (0x4U) |
| #define APBH_CH1_CMD_CHAIN_SHIFT (2U) |
| #define APBH_CH1_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_CHAIN_SHIFT)) & APBH_CH1_CMD_CHAIN_MASK) |
| #define APBH_CH1_CMD_IRQONCMPLT_MASK (0x8U) |
| #define APBH_CH1_CMD_IRQONCMPLT_SHIFT (3U) |
| #define APBH_CH1_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_IRQONCMPLT_SHIFT)) & APBH_CH1_CMD_IRQONCMPLT_MASK) |
| #define APBH_CH1_CMD_NANDLOCK_MASK (0x10U) |
| #define APBH_CH1_CMD_NANDLOCK_SHIFT (4U) |
| #define APBH_CH1_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_NANDLOCK_SHIFT)) & APBH_CH1_CMD_NANDLOCK_MASK) |
| #define APBH_CH1_CMD_NANDWAIT4READY_MASK (0x20U) |
| #define APBH_CH1_CMD_NANDWAIT4READY_SHIFT (5U) |
| #define APBH_CH1_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH1_CMD_NANDWAIT4READY_MASK) |
| #define APBH_CH1_CMD_SEMAPHORE_MASK (0x40U) |
| #define APBH_CH1_CMD_SEMAPHORE_SHIFT (6U) |
| #define APBH_CH1_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_SEMAPHORE_SHIFT)) & APBH_CH1_CMD_SEMAPHORE_MASK) |
| #define APBH_CH1_CMD_WAIT4ENDCMD_MASK (0x80U) |
| #define APBH_CH1_CMD_WAIT4ENDCMD_SHIFT (7U) |
| #define APBH_CH1_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH1_CMD_WAIT4ENDCMD_MASK) |
| #define APBH_CH1_CMD_HALTONTERMINATE_MASK (0x100U) |
| #define APBH_CH1_CMD_HALTONTERMINATE_SHIFT (8U) |
| #define APBH_CH1_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH1_CMD_HALTONTERMINATE_MASK) |
| #define APBH_CH1_CMD_CMDWORDS_MASK (0xF000U) |
| #define APBH_CH1_CMD_CMDWORDS_SHIFT (12U) |
| #define APBH_CH1_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_CMDWORDS_SHIFT)) & APBH_CH1_CMD_CMDWORDS_MASK) |
| #define APBH_CH1_CMD_XFER_COUNT_MASK (0xFFFF0000U) |
| #define APBH_CH1_CMD_XFER_COUNT_SHIFT (16U) |
| #define APBH_CH1_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_XFER_COUNT_SHIFT)) & APBH_CH1_CMD_XFER_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name CH1_BAR - APBH DMA Channel n Buffer Address Register */ |
| /*! @{ */ |
| #define APBH_CH1_BAR_ADDRESS_MASK (0xFFFFFFFFU) |
| #define APBH_CH1_BAR_ADDRESS_SHIFT (0U) |
| #define APBH_CH1_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_BAR_ADDRESS_SHIFT)) & APBH_CH1_BAR_ADDRESS_MASK) |
| /*! @} */ |
| |
| /*! @name CH1_SEMA - APBH DMA Channel n Semaphore Register */ |
| /*! @{ */ |
| #define APBH_CH1_SEMA_INCREMENT_SEMA_MASK (0xFFU) |
| #define APBH_CH1_SEMA_INCREMENT_SEMA_SHIFT (0U) |
| #define APBH_CH1_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH1_SEMA_INCREMENT_SEMA_MASK) |
| #define APBH_CH1_SEMA_PHORE_MASK (0xFF0000U) |
| #define APBH_CH1_SEMA_PHORE_SHIFT (16U) |
| #define APBH_CH1_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_SEMA_PHORE_SHIFT)) & APBH_CH1_SEMA_PHORE_MASK) |
| /*! @} */ |
| |
| /*! @name CH1_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH1_DEBUG1_STATEMACHINE_MASK (0x1FU) |
| #define APBH_CH1_DEBUG1_STATEMACHINE_SHIFT (0U) |
| /*! STATEMACHINE |
| * 0b00000..This is the idle state of the DMA state machine. |
| * 0b00001..State in which the DMA is waiting to receive the first word of a command. |
| * 0b00010..State in which the DMA is waiting to receive the third word of a command. |
| * 0b00011..State in which the DMA is waiting to receive the second word of a command. |
| * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. |
| * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. |
| * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. |
| * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. |
| * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. |
| * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. |
| * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. |
| * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. |
| * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. |
| * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. |
| * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. |
| * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state |
| * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. |
| * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. |
| */ |
| #define APBH_CH1_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH1_DEBUG1_STATEMACHINE_MASK) |
| #define APBH_CH1_DEBUG1_RSVD1_MASK (0xFFFE0U) |
| #define APBH_CH1_DEBUG1_RSVD1_SHIFT (5U) |
| #define APBH_CH1_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RSVD1_SHIFT)) & APBH_CH1_DEBUG1_RSVD1_MASK) |
| #define APBH_CH1_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) |
| #define APBH_CH1_DEBUG1_WR_FIFO_FULL_SHIFT (20U) |
| #define APBH_CH1_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH1_DEBUG1_WR_FIFO_FULL_MASK) |
| #define APBH_CH1_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) |
| #define APBH_CH1_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) |
| #define APBH_CH1_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH1_DEBUG1_WR_FIFO_EMPTY_MASK) |
| #define APBH_CH1_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) |
| #define APBH_CH1_DEBUG1_RD_FIFO_FULL_SHIFT (22U) |
| #define APBH_CH1_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH1_DEBUG1_RD_FIFO_FULL_MASK) |
| #define APBH_CH1_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) |
| #define APBH_CH1_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) |
| #define APBH_CH1_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH1_DEBUG1_RD_FIFO_EMPTY_MASK) |
| #define APBH_CH1_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) |
| #define APBH_CH1_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) |
| #define APBH_CH1_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH1_DEBUG1_NEXTCMDADDRVALID_MASK) |
| #define APBH_CH1_DEBUG1_LOCK_MASK (0x2000000U) |
| #define APBH_CH1_DEBUG1_LOCK_SHIFT (25U) |
| #define APBH_CH1_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_LOCK_SHIFT)) & APBH_CH1_DEBUG1_LOCK_MASK) |
| #define APBH_CH1_DEBUG1_READY_MASK (0x4000000U) |
| #define APBH_CH1_DEBUG1_READY_SHIFT (26U) |
| #define APBH_CH1_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_READY_SHIFT)) & APBH_CH1_DEBUG1_READY_MASK) |
| #define APBH_CH1_DEBUG1_SENSE_MASK (0x8000000U) |
| #define APBH_CH1_DEBUG1_SENSE_SHIFT (27U) |
| #define APBH_CH1_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_SENSE_SHIFT)) & APBH_CH1_DEBUG1_SENSE_MASK) |
| #define APBH_CH1_DEBUG1_END_MASK (0x10000000U) |
| #define APBH_CH1_DEBUG1_END_SHIFT (28U) |
| #define APBH_CH1_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_END_SHIFT)) & APBH_CH1_DEBUG1_END_MASK) |
| #define APBH_CH1_DEBUG1_KICK_MASK (0x20000000U) |
| #define APBH_CH1_DEBUG1_KICK_SHIFT (29U) |
| #define APBH_CH1_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_KICK_SHIFT)) & APBH_CH1_DEBUG1_KICK_MASK) |
| #define APBH_CH1_DEBUG1_BURST_MASK (0x40000000U) |
| #define APBH_CH1_DEBUG1_BURST_SHIFT (30U) |
| #define APBH_CH1_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_BURST_SHIFT)) & APBH_CH1_DEBUG1_BURST_MASK) |
| #define APBH_CH1_DEBUG1_REQ_MASK (0x80000000U) |
| #define APBH_CH1_DEBUG1_REQ_SHIFT (31U) |
| #define APBH_CH1_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_REQ_SHIFT)) & APBH_CH1_DEBUG1_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name CH1_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH1_DEBUG2_AHB_BYTES_MASK (0xFFFFU) |
| #define APBH_CH1_DEBUG2_AHB_BYTES_SHIFT (0U) |
| #define APBH_CH1_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH1_DEBUG2_AHB_BYTES_MASK) |
| #define APBH_CH1_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) |
| #define APBH_CH1_DEBUG2_APB_BYTES_SHIFT (16U) |
| #define APBH_CH1_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH1_DEBUG2_APB_BYTES_MASK) |
| /*! @} */ |
| |
| /*! @name CH2_CURCMDAR - APBH DMA Channel n Current Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH2_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH2_CURCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH2_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH2_CURCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH2_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH2_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH2_NXTCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH2_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH2_NXTCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH2_CMD - APBH DMA Channel n Command Register */ |
| /*! @{ */ |
| #define APBH_CH2_CMD_COMMAND_MASK (0x3U) |
| #define APBH_CH2_CMD_COMMAND_SHIFT (0U) |
| /*! COMMAND |
| * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. |
| * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. |
| * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. |
| * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. |
| */ |
| #define APBH_CH2_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_COMMAND_SHIFT)) & APBH_CH2_CMD_COMMAND_MASK) |
| #define APBH_CH2_CMD_CHAIN_MASK (0x4U) |
| #define APBH_CH2_CMD_CHAIN_SHIFT (2U) |
| #define APBH_CH2_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_CHAIN_SHIFT)) & APBH_CH2_CMD_CHAIN_MASK) |
| #define APBH_CH2_CMD_IRQONCMPLT_MASK (0x8U) |
| #define APBH_CH2_CMD_IRQONCMPLT_SHIFT (3U) |
| #define APBH_CH2_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_IRQONCMPLT_SHIFT)) & APBH_CH2_CMD_IRQONCMPLT_MASK) |
| #define APBH_CH2_CMD_NANDLOCK_MASK (0x10U) |
| #define APBH_CH2_CMD_NANDLOCK_SHIFT (4U) |
| #define APBH_CH2_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_NANDLOCK_SHIFT)) & APBH_CH2_CMD_NANDLOCK_MASK) |
| #define APBH_CH2_CMD_NANDWAIT4READY_MASK (0x20U) |
| #define APBH_CH2_CMD_NANDWAIT4READY_SHIFT (5U) |
| #define APBH_CH2_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH2_CMD_NANDWAIT4READY_MASK) |
| #define APBH_CH2_CMD_SEMAPHORE_MASK (0x40U) |
| #define APBH_CH2_CMD_SEMAPHORE_SHIFT (6U) |
| #define APBH_CH2_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_SEMAPHORE_SHIFT)) & APBH_CH2_CMD_SEMAPHORE_MASK) |
| #define APBH_CH2_CMD_WAIT4ENDCMD_MASK (0x80U) |
| #define APBH_CH2_CMD_WAIT4ENDCMD_SHIFT (7U) |
| #define APBH_CH2_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH2_CMD_WAIT4ENDCMD_MASK) |
| #define APBH_CH2_CMD_HALTONTERMINATE_MASK (0x100U) |
| #define APBH_CH2_CMD_HALTONTERMINATE_SHIFT (8U) |
| #define APBH_CH2_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH2_CMD_HALTONTERMINATE_MASK) |
| #define APBH_CH2_CMD_CMDWORDS_MASK (0xF000U) |
| #define APBH_CH2_CMD_CMDWORDS_SHIFT (12U) |
| #define APBH_CH2_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_CMDWORDS_SHIFT)) & APBH_CH2_CMD_CMDWORDS_MASK) |
| #define APBH_CH2_CMD_XFER_COUNT_MASK (0xFFFF0000U) |
| #define APBH_CH2_CMD_XFER_COUNT_SHIFT (16U) |
| #define APBH_CH2_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_XFER_COUNT_SHIFT)) & APBH_CH2_CMD_XFER_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name CH2_BAR - APBH DMA Channel n Buffer Address Register */ |
| /*! @{ */ |
| #define APBH_CH2_BAR_ADDRESS_MASK (0xFFFFFFFFU) |
| #define APBH_CH2_BAR_ADDRESS_SHIFT (0U) |
| #define APBH_CH2_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_BAR_ADDRESS_SHIFT)) & APBH_CH2_BAR_ADDRESS_MASK) |
| /*! @} */ |
| |
| /*! @name CH2_SEMA - APBH DMA Channel n Semaphore Register */ |
| /*! @{ */ |
| #define APBH_CH2_SEMA_INCREMENT_SEMA_MASK (0xFFU) |
| #define APBH_CH2_SEMA_INCREMENT_SEMA_SHIFT (0U) |
| #define APBH_CH2_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH2_SEMA_INCREMENT_SEMA_MASK) |
| #define APBH_CH2_SEMA_PHORE_MASK (0xFF0000U) |
| #define APBH_CH2_SEMA_PHORE_SHIFT (16U) |
| #define APBH_CH2_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_SEMA_PHORE_SHIFT)) & APBH_CH2_SEMA_PHORE_MASK) |
| /*! @} */ |
| |
| /*! @name CH2_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH2_DEBUG1_STATEMACHINE_MASK (0x1FU) |
| #define APBH_CH2_DEBUG1_STATEMACHINE_SHIFT (0U) |
| /*! STATEMACHINE |
| * 0b00000..This is the idle state of the DMA state machine. |
| * 0b00001..State in which the DMA is waiting to receive the first word of a command. |
| * 0b00010..State in which the DMA is waiting to receive the third word of a command. |
| * 0b00011..State in which the DMA is waiting to receive the second word of a command. |
| * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. |
| * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. |
| * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. |
| * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. |
| * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. |
| * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. |
| * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. |
| * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. |
| * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. |
| * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. |
| * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. |
| * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state |
| * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. |
| * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. |
| */ |
| #define APBH_CH2_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH2_DEBUG1_STATEMACHINE_MASK) |
| #define APBH_CH2_DEBUG1_RSVD1_MASK (0xFFFE0U) |
| #define APBH_CH2_DEBUG1_RSVD1_SHIFT (5U) |
| #define APBH_CH2_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RSVD1_SHIFT)) & APBH_CH2_DEBUG1_RSVD1_MASK) |
| #define APBH_CH2_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) |
| #define APBH_CH2_DEBUG1_WR_FIFO_FULL_SHIFT (20U) |
| #define APBH_CH2_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH2_DEBUG1_WR_FIFO_FULL_MASK) |
| #define APBH_CH2_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) |
| #define APBH_CH2_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) |
| #define APBH_CH2_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH2_DEBUG1_WR_FIFO_EMPTY_MASK) |
| #define APBH_CH2_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) |
| #define APBH_CH2_DEBUG1_RD_FIFO_FULL_SHIFT (22U) |
| #define APBH_CH2_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH2_DEBUG1_RD_FIFO_FULL_MASK) |
| #define APBH_CH2_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) |
| #define APBH_CH2_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) |
| #define APBH_CH2_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH2_DEBUG1_RD_FIFO_EMPTY_MASK) |
| #define APBH_CH2_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) |
| #define APBH_CH2_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) |
| #define APBH_CH2_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH2_DEBUG1_NEXTCMDADDRVALID_MASK) |
| #define APBH_CH2_DEBUG1_LOCK_MASK (0x2000000U) |
| #define APBH_CH2_DEBUG1_LOCK_SHIFT (25U) |
| #define APBH_CH2_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_LOCK_SHIFT)) & APBH_CH2_DEBUG1_LOCK_MASK) |
| #define APBH_CH2_DEBUG1_READY_MASK (0x4000000U) |
| #define APBH_CH2_DEBUG1_READY_SHIFT (26U) |
| #define APBH_CH2_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_READY_SHIFT)) & APBH_CH2_DEBUG1_READY_MASK) |
| #define APBH_CH2_DEBUG1_SENSE_MASK (0x8000000U) |
| #define APBH_CH2_DEBUG1_SENSE_SHIFT (27U) |
| #define APBH_CH2_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_SENSE_SHIFT)) & APBH_CH2_DEBUG1_SENSE_MASK) |
| #define APBH_CH2_DEBUG1_END_MASK (0x10000000U) |
| #define APBH_CH2_DEBUG1_END_SHIFT (28U) |
| #define APBH_CH2_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_END_SHIFT)) & APBH_CH2_DEBUG1_END_MASK) |
| #define APBH_CH2_DEBUG1_KICK_MASK (0x20000000U) |
| #define APBH_CH2_DEBUG1_KICK_SHIFT (29U) |
| #define APBH_CH2_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_KICK_SHIFT)) & APBH_CH2_DEBUG1_KICK_MASK) |
| #define APBH_CH2_DEBUG1_BURST_MASK (0x40000000U) |
| #define APBH_CH2_DEBUG1_BURST_SHIFT (30U) |
| #define APBH_CH2_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_BURST_SHIFT)) & APBH_CH2_DEBUG1_BURST_MASK) |
| #define APBH_CH2_DEBUG1_REQ_MASK (0x80000000U) |
| #define APBH_CH2_DEBUG1_REQ_SHIFT (31U) |
| #define APBH_CH2_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_REQ_SHIFT)) & APBH_CH2_DEBUG1_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name CH2_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH2_DEBUG2_AHB_BYTES_MASK (0xFFFFU) |
| #define APBH_CH2_DEBUG2_AHB_BYTES_SHIFT (0U) |
| #define APBH_CH2_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH2_DEBUG2_AHB_BYTES_MASK) |
| #define APBH_CH2_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) |
| #define APBH_CH2_DEBUG2_APB_BYTES_SHIFT (16U) |
| #define APBH_CH2_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH2_DEBUG2_APB_BYTES_MASK) |
| /*! @} */ |
| |
| /*! @name CH3_CURCMDAR - APBH DMA Channel n Current Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH3_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH3_CURCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH3_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH3_CURCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH3_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH3_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH3_NXTCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH3_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH3_NXTCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH3_CMD - APBH DMA Channel n Command Register */ |
| /*! @{ */ |
| #define APBH_CH3_CMD_COMMAND_MASK (0x3U) |
| #define APBH_CH3_CMD_COMMAND_SHIFT (0U) |
| /*! COMMAND |
| * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. |
| * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. |
| * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. |
| * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. |
| */ |
| #define APBH_CH3_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_COMMAND_SHIFT)) & APBH_CH3_CMD_COMMAND_MASK) |
| #define APBH_CH3_CMD_CHAIN_MASK (0x4U) |
| #define APBH_CH3_CMD_CHAIN_SHIFT (2U) |
| #define APBH_CH3_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_CHAIN_SHIFT)) & APBH_CH3_CMD_CHAIN_MASK) |
| #define APBH_CH3_CMD_IRQONCMPLT_MASK (0x8U) |
| #define APBH_CH3_CMD_IRQONCMPLT_SHIFT (3U) |
| #define APBH_CH3_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_IRQONCMPLT_SHIFT)) & APBH_CH3_CMD_IRQONCMPLT_MASK) |
| #define APBH_CH3_CMD_NANDLOCK_MASK (0x10U) |
| #define APBH_CH3_CMD_NANDLOCK_SHIFT (4U) |
| #define APBH_CH3_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_NANDLOCK_SHIFT)) & APBH_CH3_CMD_NANDLOCK_MASK) |
| #define APBH_CH3_CMD_NANDWAIT4READY_MASK (0x20U) |
| #define APBH_CH3_CMD_NANDWAIT4READY_SHIFT (5U) |
| #define APBH_CH3_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH3_CMD_NANDWAIT4READY_MASK) |
| #define APBH_CH3_CMD_SEMAPHORE_MASK (0x40U) |
| #define APBH_CH3_CMD_SEMAPHORE_SHIFT (6U) |
| #define APBH_CH3_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_SEMAPHORE_SHIFT)) & APBH_CH3_CMD_SEMAPHORE_MASK) |
| #define APBH_CH3_CMD_WAIT4ENDCMD_MASK (0x80U) |
| #define APBH_CH3_CMD_WAIT4ENDCMD_SHIFT (7U) |
| #define APBH_CH3_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH3_CMD_WAIT4ENDCMD_MASK) |
| #define APBH_CH3_CMD_HALTONTERMINATE_MASK (0x100U) |
| #define APBH_CH3_CMD_HALTONTERMINATE_SHIFT (8U) |
| #define APBH_CH3_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH3_CMD_HALTONTERMINATE_MASK) |
| #define APBH_CH3_CMD_CMDWORDS_MASK (0xF000U) |
| #define APBH_CH3_CMD_CMDWORDS_SHIFT (12U) |
| #define APBH_CH3_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_CMDWORDS_SHIFT)) & APBH_CH3_CMD_CMDWORDS_MASK) |
| #define APBH_CH3_CMD_XFER_COUNT_MASK (0xFFFF0000U) |
| #define APBH_CH3_CMD_XFER_COUNT_SHIFT (16U) |
| #define APBH_CH3_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_XFER_COUNT_SHIFT)) & APBH_CH3_CMD_XFER_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name CH3_BAR - APBH DMA Channel n Buffer Address Register */ |
| /*! @{ */ |
| #define APBH_CH3_BAR_ADDRESS_MASK (0xFFFFFFFFU) |
| #define APBH_CH3_BAR_ADDRESS_SHIFT (0U) |
| #define APBH_CH3_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_BAR_ADDRESS_SHIFT)) & APBH_CH3_BAR_ADDRESS_MASK) |
| /*! @} */ |
| |
| /*! @name CH3_SEMA - APBH DMA Channel n Semaphore Register */ |
| /*! @{ */ |
| #define APBH_CH3_SEMA_INCREMENT_SEMA_MASK (0xFFU) |
| #define APBH_CH3_SEMA_INCREMENT_SEMA_SHIFT (0U) |
| #define APBH_CH3_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH3_SEMA_INCREMENT_SEMA_MASK) |
| #define APBH_CH3_SEMA_PHORE_MASK (0xFF0000U) |
| #define APBH_CH3_SEMA_PHORE_SHIFT (16U) |
| #define APBH_CH3_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_SEMA_PHORE_SHIFT)) & APBH_CH3_SEMA_PHORE_MASK) |
| /*! @} */ |
| |
| /*! @name CH3_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH3_DEBUG1_STATEMACHINE_MASK (0x1FU) |
| #define APBH_CH3_DEBUG1_STATEMACHINE_SHIFT (0U) |
| /*! STATEMACHINE |
| * 0b00000..This is the idle state of the DMA state machine. |
| * 0b00001..State in which the DMA is waiting to receive the first word of a command. |
| * 0b00010..State in which the DMA is waiting to receive the third word of a command. |
| * 0b00011..State in which the DMA is waiting to receive the second word of a command. |
| * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. |
| * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. |
| * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. |
| * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. |
| * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. |
| * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. |
| * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. |
| * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. |
| * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. |
| * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. |
| * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. |
| * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state |
| * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. |
| * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. |
| */ |
| #define APBH_CH3_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH3_DEBUG1_STATEMACHINE_MASK) |
| #define APBH_CH3_DEBUG1_RSVD1_MASK (0xFFFE0U) |
| #define APBH_CH3_DEBUG1_RSVD1_SHIFT (5U) |
| #define APBH_CH3_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RSVD1_SHIFT)) & APBH_CH3_DEBUG1_RSVD1_MASK) |
| #define APBH_CH3_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) |
| #define APBH_CH3_DEBUG1_WR_FIFO_FULL_SHIFT (20U) |
| #define APBH_CH3_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH3_DEBUG1_WR_FIFO_FULL_MASK) |
| #define APBH_CH3_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) |
| #define APBH_CH3_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) |
| #define APBH_CH3_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH3_DEBUG1_WR_FIFO_EMPTY_MASK) |
| #define APBH_CH3_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) |
| #define APBH_CH3_DEBUG1_RD_FIFO_FULL_SHIFT (22U) |
| #define APBH_CH3_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH3_DEBUG1_RD_FIFO_FULL_MASK) |
| #define APBH_CH3_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) |
| #define APBH_CH3_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) |
| #define APBH_CH3_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH3_DEBUG1_RD_FIFO_EMPTY_MASK) |
| #define APBH_CH3_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) |
| #define APBH_CH3_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) |
| #define APBH_CH3_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH3_DEBUG1_NEXTCMDADDRVALID_MASK) |
| #define APBH_CH3_DEBUG1_LOCK_MASK (0x2000000U) |
| #define APBH_CH3_DEBUG1_LOCK_SHIFT (25U) |
| #define APBH_CH3_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_LOCK_SHIFT)) & APBH_CH3_DEBUG1_LOCK_MASK) |
| #define APBH_CH3_DEBUG1_READY_MASK (0x4000000U) |
| #define APBH_CH3_DEBUG1_READY_SHIFT (26U) |
| #define APBH_CH3_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_READY_SHIFT)) & APBH_CH3_DEBUG1_READY_MASK) |
| #define APBH_CH3_DEBUG1_SENSE_MASK (0x8000000U) |
| #define APBH_CH3_DEBUG1_SENSE_SHIFT (27U) |
| #define APBH_CH3_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_SENSE_SHIFT)) & APBH_CH3_DEBUG1_SENSE_MASK) |
| #define APBH_CH3_DEBUG1_END_MASK (0x10000000U) |
| #define APBH_CH3_DEBUG1_END_SHIFT (28U) |
| #define APBH_CH3_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_END_SHIFT)) & APBH_CH3_DEBUG1_END_MASK) |
| #define APBH_CH3_DEBUG1_KICK_MASK (0x20000000U) |
| #define APBH_CH3_DEBUG1_KICK_SHIFT (29U) |
| #define APBH_CH3_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_KICK_SHIFT)) & APBH_CH3_DEBUG1_KICK_MASK) |
| #define APBH_CH3_DEBUG1_BURST_MASK (0x40000000U) |
| #define APBH_CH3_DEBUG1_BURST_SHIFT (30U) |
| #define APBH_CH3_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_BURST_SHIFT)) & APBH_CH3_DEBUG1_BURST_MASK) |
| #define APBH_CH3_DEBUG1_REQ_MASK (0x80000000U) |
| #define APBH_CH3_DEBUG1_REQ_SHIFT (31U) |
| #define APBH_CH3_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_REQ_SHIFT)) & APBH_CH3_DEBUG1_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name CH3_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH3_DEBUG2_AHB_BYTES_MASK (0xFFFFU) |
| #define APBH_CH3_DEBUG2_AHB_BYTES_SHIFT (0U) |
| #define APBH_CH3_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH3_DEBUG2_AHB_BYTES_MASK) |
| #define APBH_CH3_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) |
| #define APBH_CH3_DEBUG2_APB_BYTES_SHIFT (16U) |
| #define APBH_CH3_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH3_DEBUG2_APB_BYTES_MASK) |
| /*! @} */ |
| |
| /*! @name CH4_CURCMDAR - APBH DMA Channel n Current Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH4_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH4_CURCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH4_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH4_CURCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH4_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH4_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH4_NXTCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH4_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH4_NXTCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH4_CMD - APBH DMA Channel n Command Register */ |
| /*! @{ */ |
| #define APBH_CH4_CMD_COMMAND_MASK (0x3U) |
| #define APBH_CH4_CMD_COMMAND_SHIFT (0U) |
| /*! COMMAND |
| * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. |
| * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. |
| * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. |
| * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. |
| */ |
| #define APBH_CH4_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_COMMAND_SHIFT)) & APBH_CH4_CMD_COMMAND_MASK) |
| #define APBH_CH4_CMD_CHAIN_MASK (0x4U) |
| #define APBH_CH4_CMD_CHAIN_SHIFT (2U) |
| #define APBH_CH4_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_CHAIN_SHIFT)) & APBH_CH4_CMD_CHAIN_MASK) |
| #define APBH_CH4_CMD_IRQONCMPLT_MASK (0x8U) |
| #define APBH_CH4_CMD_IRQONCMPLT_SHIFT (3U) |
| #define APBH_CH4_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_IRQONCMPLT_SHIFT)) & APBH_CH4_CMD_IRQONCMPLT_MASK) |
| #define APBH_CH4_CMD_NANDLOCK_MASK (0x10U) |
| #define APBH_CH4_CMD_NANDLOCK_SHIFT (4U) |
| #define APBH_CH4_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_NANDLOCK_SHIFT)) & APBH_CH4_CMD_NANDLOCK_MASK) |
| #define APBH_CH4_CMD_NANDWAIT4READY_MASK (0x20U) |
| #define APBH_CH4_CMD_NANDWAIT4READY_SHIFT (5U) |
| #define APBH_CH4_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH4_CMD_NANDWAIT4READY_MASK) |
| #define APBH_CH4_CMD_SEMAPHORE_MASK (0x40U) |
| #define APBH_CH4_CMD_SEMAPHORE_SHIFT (6U) |
| #define APBH_CH4_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_SEMAPHORE_SHIFT)) & APBH_CH4_CMD_SEMAPHORE_MASK) |
| #define APBH_CH4_CMD_WAIT4ENDCMD_MASK (0x80U) |
| #define APBH_CH4_CMD_WAIT4ENDCMD_SHIFT (7U) |
| #define APBH_CH4_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH4_CMD_WAIT4ENDCMD_MASK) |
| #define APBH_CH4_CMD_HALTONTERMINATE_MASK (0x100U) |
| #define APBH_CH4_CMD_HALTONTERMINATE_SHIFT (8U) |
| #define APBH_CH4_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH4_CMD_HALTONTERMINATE_MASK) |
| #define APBH_CH4_CMD_CMDWORDS_MASK (0xF000U) |
| #define APBH_CH4_CMD_CMDWORDS_SHIFT (12U) |
| #define APBH_CH4_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_CMDWORDS_SHIFT)) & APBH_CH4_CMD_CMDWORDS_MASK) |
| #define APBH_CH4_CMD_XFER_COUNT_MASK (0xFFFF0000U) |
| #define APBH_CH4_CMD_XFER_COUNT_SHIFT (16U) |
| #define APBH_CH4_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_XFER_COUNT_SHIFT)) & APBH_CH4_CMD_XFER_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name CH4_BAR - APBH DMA Channel n Buffer Address Register */ |
| /*! @{ */ |
| #define APBH_CH4_BAR_ADDRESS_MASK (0xFFFFFFFFU) |
| #define APBH_CH4_BAR_ADDRESS_SHIFT (0U) |
| #define APBH_CH4_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_BAR_ADDRESS_SHIFT)) & APBH_CH4_BAR_ADDRESS_MASK) |
| /*! @} */ |
| |
| /*! @name CH4_SEMA - APBH DMA Channel n Semaphore Register */ |
| /*! @{ */ |
| #define APBH_CH4_SEMA_INCREMENT_SEMA_MASK (0xFFU) |
| #define APBH_CH4_SEMA_INCREMENT_SEMA_SHIFT (0U) |
| #define APBH_CH4_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH4_SEMA_INCREMENT_SEMA_MASK) |
| #define APBH_CH4_SEMA_PHORE_MASK (0xFF0000U) |
| #define APBH_CH4_SEMA_PHORE_SHIFT (16U) |
| #define APBH_CH4_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_SEMA_PHORE_SHIFT)) & APBH_CH4_SEMA_PHORE_MASK) |
| /*! @} */ |
| |
| /*! @name CH4_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH4_DEBUG1_STATEMACHINE_MASK (0x1FU) |
| #define APBH_CH4_DEBUG1_STATEMACHINE_SHIFT (0U) |
| /*! STATEMACHINE |
| * 0b00000..This is the idle state of the DMA state machine. |
| * 0b00001..State in which the DMA is waiting to receive the first word of a command. |
| * 0b00010..State in which the DMA is waiting to receive the third word of a command. |
| * 0b00011..State in which the DMA is waiting to receive the second word of a command. |
| * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. |
| * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. |
| * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. |
| * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. |
| * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. |
| * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. |
| * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. |
| * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. |
| * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. |
| * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. |
| * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. |
| * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state |
| * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. |
| * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. |
| */ |
| #define APBH_CH4_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH4_DEBUG1_STATEMACHINE_MASK) |
| #define APBH_CH4_DEBUG1_RSVD1_MASK (0xFFFE0U) |
| #define APBH_CH4_DEBUG1_RSVD1_SHIFT (5U) |
| #define APBH_CH4_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RSVD1_SHIFT)) & APBH_CH4_DEBUG1_RSVD1_MASK) |
| #define APBH_CH4_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) |
| #define APBH_CH4_DEBUG1_WR_FIFO_FULL_SHIFT (20U) |
| #define APBH_CH4_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH4_DEBUG1_WR_FIFO_FULL_MASK) |
| #define APBH_CH4_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) |
| #define APBH_CH4_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) |
| #define APBH_CH4_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH4_DEBUG1_WR_FIFO_EMPTY_MASK) |
| #define APBH_CH4_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) |
| #define APBH_CH4_DEBUG1_RD_FIFO_FULL_SHIFT (22U) |
| #define APBH_CH4_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH4_DEBUG1_RD_FIFO_FULL_MASK) |
| #define APBH_CH4_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) |
| #define APBH_CH4_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) |
| #define APBH_CH4_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH4_DEBUG1_RD_FIFO_EMPTY_MASK) |
| #define APBH_CH4_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) |
| #define APBH_CH4_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) |
| #define APBH_CH4_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH4_DEBUG1_NEXTCMDADDRVALID_MASK) |
| #define APBH_CH4_DEBUG1_LOCK_MASK (0x2000000U) |
| #define APBH_CH4_DEBUG1_LOCK_SHIFT (25U) |
| #define APBH_CH4_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_LOCK_SHIFT)) & APBH_CH4_DEBUG1_LOCK_MASK) |
| #define APBH_CH4_DEBUG1_READY_MASK (0x4000000U) |
| #define APBH_CH4_DEBUG1_READY_SHIFT (26U) |
| #define APBH_CH4_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_READY_SHIFT)) & APBH_CH4_DEBUG1_READY_MASK) |
| #define APBH_CH4_DEBUG1_SENSE_MASK (0x8000000U) |
| #define APBH_CH4_DEBUG1_SENSE_SHIFT (27U) |
| #define APBH_CH4_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_SENSE_SHIFT)) & APBH_CH4_DEBUG1_SENSE_MASK) |
| #define APBH_CH4_DEBUG1_END_MASK (0x10000000U) |
| #define APBH_CH4_DEBUG1_END_SHIFT (28U) |
| #define APBH_CH4_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_END_SHIFT)) & APBH_CH4_DEBUG1_END_MASK) |
| #define APBH_CH4_DEBUG1_KICK_MASK (0x20000000U) |
| #define APBH_CH4_DEBUG1_KICK_SHIFT (29U) |
| #define APBH_CH4_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_KICK_SHIFT)) & APBH_CH4_DEBUG1_KICK_MASK) |
| #define APBH_CH4_DEBUG1_BURST_MASK (0x40000000U) |
| #define APBH_CH4_DEBUG1_BURST_SHIFT (30U) |
| #define APBH_CH4_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_BURST_SHIFT)) & APBH_CH4_DEBUG1_BURST_MASK) |
| #define APBH_CH4_DEBUG1_REQ_MASK (0x80000000U) |
| #define APBH_CH4_DEBUG1_REQ_SHIFT (31U) |
| #define APBH_CH4_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_REQ_SHIFT)) & APBH_CH4_DEBUG1_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name CH4_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH4_DEBUG2_AHB_BYTES_MASK (0xFFFFU) |
| #define APBH_CH4_DEBUG2_AHB_BYTES_SHIFT (0U) |
| #define APBH_CH4_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH4_DEBUG2_AHB_BYTES_MASK) |
| #define APBH_CH4_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) |
| #define APBH_CH4_DEBUG2_APB_BYTES_SHIFT (16U) |
| #define APBH_CH4_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH4_DEBUG2_APB_BYTES_MASK) |
| /*! @} */ |
| |
| /*! @name CH5_CURCMDAR - APBH DMA Channel n Current Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH5_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH5_CURCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH5_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH5_CURCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH5_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH5_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH5_NXTCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH5_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH5_NXTCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH5_CMD - APBH DMA Channel n Command Register */ |
| /*! @{ */ |
| #define APBH_CH5_CMD_COMMAND_MASK (0x3U) |
| #define APBH_CH5_CMD_COMMAND_SHIFT (0U) |
| /*! COMMAND |
| * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. |
| * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. |
| * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. |
| * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. |
| */ |
| #define APBH_CH5_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_COMMAND_SHIFT)) & APBH_CH5_CMD_COMMAND_MASK) |
| #define APBH_CH5_CMD_CHAIN_MASK (0x4U) |
| #define APBH_CH5_CMD_CHAIN_SHIFT (2U) |
| #define APBH_CH5_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_CHAIN_SHIFT)) & APBH_CH5_CMD_CHAIN_MASK) |
| #define APBH_CH5_CMD_IRQONCMPLT_MASK (0x8U) |
| #define APBH_CH5_CMD_IRQONCMPLT_SHIFT (3U) |
| #define APBH_CH5_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_IRQONCMPLT_SHIFT)) & APBH_CH5_CMD_IRQONCMPLT_MASK) |
| #define APBH_CH5_CMD_NANDLOCK_MASK (0x10U) |
| #define APBH_CH5_CMD_NANDLOCK_SHIFT (4U) |
| #define APBH_CH5_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDLOCK_SHIFT)) & APBH_CH5_CMD_NANDLOCK_MASK) |
| #define APBH_CH5_CMD_NANDWAIT4READY_MASK (0x20U) |
| #define APBH_CH5_CMD_NANDWAIT4READY_SHIFT (5U) |
| #define APBH_CH5_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH5_CMD_NANDWAIT4READY_MASK) |
| #define APBH_CH5_CMD_SEMAPHORE_MASK (0x40U) |
| #define APBH_CH5_CMD_SEMAPHORE_SHIFT (6U) |
| #define APBH_CH5_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_SEMAPHORE_SHIFT)) & APBH_CH5_CMD_SEMAPHORE_MASK) |
| #define APBH_CH5_CMD_WAIT4ENDCMD_MASK (0x80U) |
| #define APBH_CH5_CMD_WAIT4ENDCMD_SHIFT (7U) |
| #define APBH_CH5_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH5_CMD_WAIT4ENDCMD_MASK) |
| #define APBH_CH5_CMD_HALTONTERMINATE_MASK (0x100U) |
| #define APBH_CH5_CMD_HALTONTERMINATE_SHIFT (8U) |
| #define APBH_CH5_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH5_CMD_HALTONTERMINATE_MASK) |
| #define APBH_CH5_CMD_CMDWORDS_MASK (0xF000U) |
| #define APBH_CH5_CMD_CMDWORDS_SHIFT (12U) |
| #define APBH_CH5_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_CMDWORDS_SHIFT)) & APBH_CH5_CMD_CMDWORDS_MASK) |
| #define APBH_CH5_CMD_XFER_COUNT_MASK (0xFFFF0000U) |
| #define APBH_CH5_CMD_XFER_COUNT_SHIFT (16U) |
| #define APBH_CH5_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_XFER_COUNT_SHIFT)) & APBH_CH5_CMD_XFER_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name CH5_BAR - APBH DMA Channel n Buffer Address Register */ |
| /*! @{ */ |
| #define APBH_CH5_BAR_ADDRESS_MASK (0xFFFFFFFFU) |
| #define APBH_CH5_BAR_ADDRESS_SHIFT (0U) |
| #define APBH_CH5_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_BAR_ADDRESS_SHIFT)) & APBH_CH5_BAR_ADDRESS_MASK) |
| /*! @} */ |
| |
| /*! @name CH5_SEMA - APBH DMA Channel n Semaphore Register */ |
| /*! @{ */ |
| #define APBH_CH5_SEMA_INCREMENT_SEMA_MASK (0xFFU) |
| #define APBH_CH5_SEMA_INCREMENT_SEMA_SHIFT (0U) |
| #define APBH_CH5_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH5_SEMA_INCREMENT_SEMA_MASK) |
| #define APBH_CH5_SEMA_PHORE_MASK (0xFF0000U) |
| #define APBH_CH5_SEMA_PHORE_SHIFT (16U) |
| #define APBH_CH5_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_SEMA_PHORE_SHIFT)) & APBH_CH5_SEMA_PHORE_MASK) |
| /*! @} */ |
| |
| /*! @name CH5_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH5_DEBUG1_STATEMACHINE_MASK (0x1FU) |
| #define APBH_CH5_DEBUG1_STATEMACHINE_SHIFT (0U) |
| /*! STATEMACHINE |
| * 0b00000..This is the idle state of the DMA state machine. |
| * 0b00001..State in which the DMA is waiting to receive the first word of a command. |
| * 0b00010..State in which the DMA is waiting to receive the third word of a command. |
| * 0b00011..State in which the DMA is waiting to receive the second word of a command. |
| * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. |
| * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. |
| * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. |
| * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. |
| * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. |
| * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. |
| * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. |
| * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. |
| * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. |
| * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. |
| * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. |
| * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state |
| * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. |
| * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. |
| */ |
| #define APBH_CH5_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH5_DEBUG1_STATEMACHINE_MASK) |
| #define APBH_CH5_DEBUG1_RSVD1_MASK (0xFFFE0U) |
| #define APBH_CH5_DEBUG1_RSVD1_SHIFT (5U) |
| #define APBH_CH5_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RSVD1_SHIFT)) & APBH_CH5_DEBUG1_RSVD1_MASK) |
| #define APBH_CH5_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) |
| #define APBH_CH5_DEBUG1_WR_FIFO_FULL_SHIFT (20U) |
| #define APBH_CH5_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH5_DEBUG1_WR_FIFO_FULL_MASK) |
| #define APBH_CH5_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) |
| #define APBH_CH5_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) |
| #define APBH_CH5_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH5_DEBUG1_WR_FIFO_EMPTY_MASK) |
| #define APBH_CH5_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) |
| #define APBH_CH5_DEBUG1_RD_FIFO_FULL_SHIFT (22U) |
| #define APBH_CH5_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH5_DEBUG1_RD_FIFO_FULL_MASK) |
| #define APBH_CH5_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) |
| #define APBH_CH5_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) |
| #define APBH_CH5_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH5_DEBUG1_RD_FIFO_EMPTY_MASK) |
| #define APBH_CH5_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) |
| #define APBH_CH5_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) |
| #define APBH_CH5_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH5_DEBUG1_NEXTCMDADDRVALID_MASK) |
| #define APBH_CH5_DEBUG1_LOCK_MASK (0x2000000U) |
| #define APBH_CH5_DEBUG1_LOCK_SHIFT (25U) |
| #define APBH_CH5_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_LOCK_SHIFT)) & APBH_CH5_DEBUG1_LOCK_MASK) |
| #define APBH_CH5_DEBUG1_READY_MASK (0x4000000U) |
| #define APBH_CH5_DEBUG1_READY_SHIFT (26U) |
| #define APBH_CH5_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_READY_SHIFT)) & APBH_CH5_DEBUG1_READY_MASK) |
| #define APBH_CH5_DEBUG1_SENSE_MASK (0x8000000U) |
| #define APBH_CH5_DEBUG1_SENSE_SHIFT (27U) |
| #define APBH_CH5_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_SENSE_SHIFT)) & APBH_CH5_DEBUG1_SENSE_MASK) |
| #define APBH_CH5_DEBUG1_END_MASK (0x10000000U) |
| #define APBH_CH5_DEBUG1_END_SHIFT (28U) |
| #define APBH_CH5_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_END_SHIFT)) & APBH_CH5_DEBUG1_END_MASK) |
| #define APBH_CH5_DEBUG1_KICK_MASK (0x20000000U) |
| #define APBH_CH5_DEBUG1_KICK_SHIFT (29U) |
| #define APBH_CH5_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_KICK_SHIFT)) & APBH_CH5_DEBUG1_KICK_MASK) |
| #define APBH_CH5_DEBUG1_BURST_MASK (0x40000000U) |
| #define APBH_CH5_DEBUG1_BURST_SHIFT (30U) |
| #define APBH_CH5_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_BURST_SHIFT)) & APBH_CH5_DEBUG1_BURST_MASK) |
| #define APBH_CH5_DEBUG1_REQ_MASK (0x80000000U) |
| #define APBH_CH5_DEBUG1_REQ_SHIFT (31U) |
| #define APBH_CH5_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_REQ_SHIFT)) & APBH_CH5_DEBUG1_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name CH5_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH5_DEBUG2_AHB_BYTES_MASK (0xFFFFU) |
| #define APBH_CH5_DEBUG2_AHB_BYTES_SHIFT (0U) |
| #define APBH_CH5_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH5_DEBUG2_AHB_BYTES_MASK) |
| #define APBH_CH5_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) |
| #define APBH_CH5_DEBUG2_APB_BYTES_SHIFT (16U) |
| #define APBH_CH5_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH5_DEBUG2_APB_BYTES_MASK) |
| /*! @} */ |
| |
| /*! @name CH6_CURCMDAR - APBH DMA Channel n Current Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH6_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH6_CURCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH6_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH6_CURCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH6_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH6_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH6_NXTCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH6_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH6_NXTCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH6_CMD - APBH DMA Channel n Command Register */ |
| /*! @{ */ |
| #define APBH_CH6_CMD_COMMAND_MASK (0x3U) |
| #define APBH_CH6_CMD_COMMAND_SHIFT (0U) |
| /*! COMMAND |
| * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. |
| * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. |
| * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. |
| * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. |
| */ |
| #define APBH_CH6_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_COMMAND_SHIFT)) & APBH_CH6_CMD_COMMAND_MASK) |
| #define APBH_CH6_CMD_CHAIN_MASK (0x4U) |
| #define APBH_CH6_CMD_CHAIN_SHIFT (2U) |
| #define APBH_CH6_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_CHAIN_SHIFT)) & APBH_CH6_CMD_CHAIN_MASK) |
| #define APBH_CH6_CMD_IRQONCMPLT_MASK (0x8U) |
| #define APBH_CH6_CMD_IRQONCMPLT_SHIFT (3U) |
| #define APBH_CH6_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_IRQONCMPLT_SHIFT)) & APBH_CH6_CMD_IRQONCMPLT_MASK) |
| #define APBH_CH6_CMD_NANDLOCK_MASK (0x10U) |
| #define APBH_CH6_CMD_NANDLOCK_SHIFT (4U) |
| #define APBH_CH6_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_NANDLOCK_SHIFT)) & APBH_CH6_CMD_NANDLOCK_MASK) |
| #define APBH_CH6_CMD_NANDWAIT4READY_MASK (0x20U) |
| #define APBH_CH6_CMD_NANDWAIT4READY_SHIFT (5U) |
| #define APBH_CH6_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH6_CMD_NANDWAIT4READY_MASK) |
| #define APBH_CH6_CMD_SEMAPHORE_MASK (0x40U) |
| #define APBH_CH6_CMD_SEMAPHORE_SHIFT (6U) |
| #define APBH_CH6_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_SEMAPHORE_SHIFT)) & APBH_CH6_CMD_SEMAPHORE_MASK) |
| #define APBH_CH6_CMD_WAIT4ENDCMD_MASK (0x80U) |
| #define APBH_CH6_CMD_WAIT4ENDCMD_SHIFT (7U) |
| #define APBH_CH6_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH6_CMD_WAIT4ENDCMD_MASK) |
| #define APBH_CH6_CMD_HALTONTERMINATE_MASK (0x100U) |
| #define APBH_CH6_CMD_HALTONTERMINATE_SHIFT (8U) |
| #define APBH_CH6_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH6_CMD_HALTONTERMINATE_MASK) |
| #define APBH_CH6_CMD_CMDWORDS_MASK (0xF000U) |
| #define APBH_CH6_CMD_CMDWORDS_SHIFT (12U) |
| #define APBH_CH6_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_CMDWORDS_SHIFT)) & APBH_CH6_CMD_CMDWORDS_MASK) |
| #define APBH_CH6_CMD_XFER_COUNT_MASK (0xFFFF0000U) |
| #define APBH_CH6_CMD_XFER_COUNT_SHIFT (16U) |
| #define APBH_CH6_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_XFER_COUNT_SHIFT)) & APBH_CH6_CMD_XFER_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name CH6_BAR - APBH DMA Channel n Buffer Address Register */ |
| /*! @{ */ |
| #define APBH_CH6_BAR_ADDRESS_MASK (0xFFFFFFFFU) |
| #define APBH_CH6_BAR_ADDRESS_SHIFT (0U) |
| #define APBH_CH6_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_BAR_ADDRESS_SHIFT)) & APBH_CH6_BAR_ADDRESS_MASK) |
| /*! @} */ |
| |
| /*! @name CH6_SEMA - APBH DMA Channel n Semaphore Register */ |
| /*! @{ */ |
| #define APBH_CH6_SEMA_INCREMENT_SEMA_MASK (0xFFU) |
| #define APBH_CH6_SEMA_INCREMENT_SEMA_SHIFT (0U) |
| #define APBH_CH6_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH6_SEMA_INCREMENT_SEMA_MASK) |
| #define APBH_CH6_SEMA_PHORE_MASK (0xFF0000U) |
| #define APBH_CH6_SEMA_PHORE_SHIFT (16U) |
| #define APBH_CH6_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_SEMA_PHORE_SHIFT)) & APBH_CH6_SEMA_PHORE_MASK) |
| /*! @} */ |
| |
| /*! @name CH6_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH6_DEBUG1_STATEMACHINE_MASK (0x1FU) |
| #define APBH_CH6_DEBUG1_STATEMACHINE_SHIFT (0U) |
| /*! STATEMACHINE |
| * 0b00000..This is the idle state of the DMA state machine. |
| * 0b00001..State in which the DMA is waiting to receive the first word of a command. |
| * 0b00010..State in which the DMA is waiting to receive the third word of a command. |
| * 0b00011..State in which the DMA is waiting to receive the second word of a command. |
| * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. |
| * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. |
| * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. |
| * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. |
| * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. |
| * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. |
| * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. |
| * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. |
| * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. |
| * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. |
| * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. |
| * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state |
| * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. |
| * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. |
| */ |
| #define APBH_CH6_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH6_DEBUG1_STATEMACHINE_MASK) |
| #define APBH_CH6_DEBUG1_RSVD1_MASK (0xFFFE0U) |
| #define APBH_CH6_DEBUG1_RSVD1_SHIFT (5U) |
| #define APBH_CH6_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RSVD1_SHIFT)) & APBH_CH6_DEBUG1_RSVD1_MASK) |
| #define APBH_CH6_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) |
| #define APBH_CH6_DEBUG1_WR_FIFO_FULL_SHIFT (20U) |
| #define APBH_CH6_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH6_DEBUG1_WR_FIFO_FULL_MASK) |
| #define APBH_CH6_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) |
| #define APBH_CH6_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) |
| #define APBH_CH6_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH6_DEBUG1_WR_FIFO_EMPTY_MASK) |
| #define APBH_CH6_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) |
| #define APBH_CH6_DEBUG1_RD_FIFO_FULL_SHIFT (22U) |
| #define APBH_CH6_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH6_DEBUG1_RD_FIFO_FULL_MASK) |
| #define APBH_CH6_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) |
| #define APBH_CH6_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) |
| #define APBH_CH6_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH6_DEBUG1_RD_FIFO_EMPTY_MASK) |
| #define APBH_CH6_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) |
| #define APBH_CH6_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) |
| #define APBH_CH6_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH6_DEBUG1_NEXTCMDADDRVALID_MASK) |
| #define APBH_CH6_DEBUG1_LOCK_MASK (0x2000000U) |
| #define APBH_CH6_DEBUG1_LOCK_SHIFT (25U) |
| #define APBH_CH6_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_LOCK_SHIFT)) & APBH_CH6_DEBUG1_LOCK_MASK) |
| #define APBH_CH6_DEBUG1_READY_MASK (0x4000000U) |
| #define APBH_CH6_DEBUG1_READY_SHIFT (26U) |
| #define APBH_CH6_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_READY_SHIFT)) & APBH_CH6_DEBUG1_READY_MASK) |
| #define APBH_CH6_DEBUG1_SENSE_MASK (0x8000000U) |
| #define APBH_CH6_DEBUG1_SENSE_SHIFT (27U) |
| #define APBH_CH6_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_SENSE_SHIFT)) & APBH_CH6_DEBUG1_SENSE_MASK) |
| #define APBH_CH6_DEBUG1_END_MASK (0x10000000U) |
| #define APBH_CH6_DEBUG1_END_SHIFT (28U) |
| #define APBH_CH6_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_END_SHIFT)) & APBH_CH6_DEBUG1_END_MASK) |
| #define APBH_CH6_DEBUG1_KICK_MASK (0x20000000U) |
| #define APBH_CH6_DEBUG1_KICK_SHIFT (29U) |
| #define APBH_CH6_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_KICK_SHIFT)) & APBH_CH6_DEBUG1_KICK_MASK) |
| #define APBH_CH6_DEBUG1_BURST_MASK (0x40000000U) |
| #define APBH_CH6_DEBUG1_BURST_SHIFT (30U) |
| #define APBH_CH6_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_BURST_SHIFT)) & APBH_CH6_DEBUG1_BURST_MASK) |
| #define APBH_CH6_DEBUG1_REQ_MASK (0x80000000U) |
| #define APBH_CH6_DEBUG1_REQ_SHIFT (31U) |
| #define APBH_CH6_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_REQ_SHIFT)) & APBH_CH6_DEBUG1_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name CH6_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH6_DEBUG2_AHB_BYTES_MASK (0xFFFFU) |
| #define APBH_CH6_DEBUG2_AHB_BYTES_SHIFT (0U) |
| #define APBH_CH6_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH6_DEBUG2_AHB_BYTES_MASK) |
| #define APBH_CH6_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) |
| #define APBH_CH6_DEBUG2_APB_BYTES_SHIFT (16U) |
| #define APBH_CH6_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH6_DEBUG2_APB_BYTES_MASK) |
| /*! @} */ |
| |
| /*! @name CH7_CURCMDAR - APBH DMA Channel n Current Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH7_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH7_CURCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH7_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH7_CURCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH7_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH7_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH7_NXTCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH7_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH7_NXTCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH7_CMD - APBH DMA Channel n Command Register */ |
| /*! @{ */ |
| #define APBH_CH7_CMD_COMMAND_MASK (0x3U) |
| #define APBH_CH7_CMD_COMMAND_SHIFT (0U) |
| /*! COMMAND |
| * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. |
| * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. |
| * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. |
| * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. |
| */ |
| #define APBH_CH7_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_COMMAND_SHIFT)) & APBH_CH7_CMD_COMMAND_MASK) |
| #define APBH_CH7_CMD_CHAIN_MASK (0x4U) |
| #define APBH_CH7_CMD_CHAIN_SHIFT (2U) |
| #define APBH_CH7_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_CHAIN_SHIFT)) & APBH_CH7_CMD_CHAIN_MASK) |
| #define APBH_CH7_CMD_IRQONCMPLT_MASK (0x8U) |
| #define APBH_CH7_CMD_IRQONCMPLT_SHIFT (3U) |
| #define APBH_CH7_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_IRQONCMPLT_SHIFT)) & APBH_CH7_CMD_IRQONCMPLT_MASK) |
| #define APBH_CH7_CMD_NANDLOCK_MASK (0x10U) |
| #define APBH_CH7_CMD_NANDLOCK_SHIFT (4U) |
| #define APBH_CH7_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_NANDLOCK_SHIFT)) & APBH_CH7_CMD_NANDLOCK_MASK) |
| #define APBH_CH7_CMD_NANDWAIT4READY_MASK (0x20U) |
| #define APBH_CH7_CMD_NANDWAIT4READY_SHIFT (5U) |
| #define APBH_CH7_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH7_CMD_NANDWAIT4READY_MASK) |
| #define APBH_CH7_CMD_SEMAPHORE_MASK (0x40U) |
| #define APBH_CH7_CMD_SEMAPHORE_SHIFT (6U) |
| #define APBH_CH7_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_SEMAPHORE_SHIFT)) & APBH_CH7_CMD_SEMAPHORE_MASK) |
| #define APBH_CH7_CMD_WAIT4ENDCMD_MASK (0x80U) |
| #define APBH_CH7_CMD_WAIT4ENDCMD_SHIFT (7U) |
| #define APBH_CH7_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH7_CMD_WAIT4ENDCMD_MASK) |
| #define APBH_CH7_CMD_HALTONTERMINATE_MASK (0x100U) |
| #define APBH_CH7_CMD_HALTONTERMINATE_SHIFT (8U) |
| #define APBH_CH7_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH7_CMD_HALTONTERMINATE_MASK) |
| #define APBH_CH7_CMD_CMDWORDS_MASK (0xF000U) |
| #define APBH_CH7_CMD_CMDWORDS_SHIFT (12U) |
| #define APBH_CH7_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_CMDWORDS_SHIFT)) & APBH_CH7_CMD_CMDWORDS_MASK) |
| #define APBH_CH7_CMD_XFER_COUNT_MASK (0xFFFF0000U) |
| #define APBH_CH7_CMD_XFER_COUNT_SHIFT (16U) |
| #define APBH_CH7_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_XFER_COUNT_SHIFT)) & APBH_CH7_CMD_XFER_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name CH7_BAR - APBH DMA Channel n Buffer Address Register */ |
| /*! @{ */ |
| #define APBH_CH7_BAR_ADDRESS_MASK (0xFFFFFFFFU) |
| #define APBH_CH7_BAR_ADDRESS_SHIFT (0U) |
| #define APBH_CH7_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_BAR_ADDRESS_SHIFT)) & APBH_CH7_BAR_ADDRESS_MASK) |
| /*! @} */ |
| |
| /*! @name CH7_SEMA - APBH DMA Channel n Semaphore Register */ |
| /*! @{ */ |
| #define APBH_CH7_SEMA_INCREMENT_SEMA_MASK (0xFFU) |
| #define APBH_CH7_SEMA_INCREMENT_SEMA_SHIFT (0U) |
| #define APBH_CH7_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH7_SEMA_INCREMENT_SEMA_MASK) |
| #define APBH_CH7_SEMA_PHORE_MASK (0xFF0000U) |
| #define APBH_CH7_SEMA_PHORE_SHIFT (16U) |
| #define APBH_CH7_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_SEMA_PHORE_SHIFT)) & APBH_CH7_SEMA_PHORE_MASK) |
| /*! @} */ |
| |
| /*! @name CH7_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH7_DEBUG1_STATEMACHINE_MASK (0x1FU) |
| #define APBH_CH7_DEBUG1_STATEMACHINE_SHIFT (0U) |
| /*! STATEMACHINE |
| * 0b00000..This is the idle state of the DMA state machine. |
| * 0b00001..State in which the DMA is waiting to receive the first word of a command. |
| * 0b00010..State in which the DMA is waiting to receive the third word of a command. |
| * 0b00011..State in which the DMA is waiting to receive the second word of a command. |
| * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. |
| * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. |
| * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. |
| * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. |
| * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. |
| * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. |
| * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. |
| * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. |
| * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. |
| * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. |
| * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. |
| * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state |
| * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. |
| * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. |
| */ |
| #define APBH_CH7_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH7_DEBUG1_STATEMACHINE_MASK) |
| #define APBH_CH7_DEBUG1_RSVD1_MASK (0xFFFE0U) |
| #define APBH_CH7_DEBUG1_RSVD1_SHIFT (5U) |
| #define APBH_CH7_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RSVD1_SHIFT)) & APBH_CH7_DEBUG1_RSVD1_MASK) |
| #define APBH_CH7_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) |
| #define APBH_CH7_DEBUG1_WR_FIFO_FULL_SHIFT (20U) |
| #define APBH_CH7_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH7_DEBUG1_WR_FIFO_FULL_MASK) |
| #define APBH_CH7_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) |
| #define APBH_CH7_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) |
| #define APBH_CH7_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH7_DEBUG1_WR_FIFO_EMPTY_MASK) |
| #define APBH_CH7_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) |
| #define APBH_CH7_DEBUG1_RD_FIFO_FULL_SHIFT (22U) |
| #define APBH_CH7_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH7_DEBUG1_RD_FIFO_FULL_MASK) |
| #define APBH_CH7_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) |
| #define APBH_CH7_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) |
| #define APBH_CH7_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH7_DEBUG1_RD_FIFO_EMPTY_MASK) |
| #define APBH_CH7_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) |
| #define APBH_CH7_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) |
| #define APBH_CH7_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH7_DEBUG1_NEXTCMDADDRVALID_MASK) |
| #define APBH_CH7_DEBUG1_LOCK_MASK (0x2000000U) |
| #define APBH_CH7_DEBUG1_LOCK_SHIFT (25U) |
| #define APBH_CH7_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_LOCK_SHIFT)) & APBH_CH7_DEBUG1_LOCK_MASK) |
| #define APBH_CH7_DEBUG1_READY_MASK (0x4000000U) |
| #define APBH_CH7_DEBUG1_READY_SHIFT (26U) |
| #define APBH_CH7_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_READY_SHIFT)) & APBH_CH7_DEBUG1_READY_MASK) |
| #define APBH_CH7_DEBUG1_SENSE_MASK (0x8000000U) |
| #define APBH_CH7_DEBUG1_SENSE_SHIFT (27U) |
| #define APBH_CH7_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_SENSE_SHIFT)) & APBH_CH7_DEBUG1_SENSE_MASK) |
| #define APBH_CH7_DEBUG1_END_MASK (0x10000000U) |
| #define APBH_CH7_DEBUG1_END_SHIFT (28U) |
| #define APBH_CH7_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_END_SHIFT)) & APBH_CH7_DEBUG1_END_MASK) |
| #define APBH_CH7_DEBUG1_KICK_MASK (0x20000000U) |
| #define APBH_CH7_DEBUG1_KICK_SHIFT (29U) |
| #define APBH_CH7_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_KICK_SHIFT)) & APBH_CH7_DEBUG1_KICK_MASK) |
| #define APBH_CH7_DEBUG1_BURST_MASK (0x40000000U) |
| #define APBH_CH7_DEBUG1_BURST_SHIFT (30U) |
| #define APBH_CH7_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_BURST_SHIFT)) & APBH_CH7_DEBUG1_BURST_MASK) |
| #define APBH_CH7_DEBUG1_REQ_MASK (0x80000000U) |
| #define APBH_CH7_DEBUG1_REQ_SHIFT (31U) |
| #define APBH_CH7_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_REQ_SHIFT)) & APBH_CH7_DEBUG1_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name CH7_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH7_DEBUG2_AHB_BYTES_MASK (0xFFFFU) |
| #define APBH_CH7_DEBUG2_AHB_BYTES_SHIFT (0U) |
| #define APBH_CH7_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH7_DEBUG2_AHB_BYTES_MASK) |
| #define APBH_CH7_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) |
| #define APBH_CH7_DEBUG2_APB_BYTES_SHIFT (16U) |
| #define APBH_CH7_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH7_DEBUG2_APB_BYTES_MASK) |
| /*! @} */ |
| |
| /*! @name CH8_CURCMDAR - APBH DMA Channel n Current Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH8_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH8_CURCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH8_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH8_CURCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH8_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH8_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH8_NXTCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH8_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH8_NXTCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH8_CMD - APBH DMA Channel n Command Register */ |
| /*! @{ */ |
| #define APBH_CH8_CMD_COMMAND_MASK (0x3U) |
| #define APBH_CH8_CMD_COMMAND_SHIFT (0U) |
| /*! COMMAND |
| * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. |
| * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. |
| * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. |
| * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. |
| */ |
| #define APBH_CH8_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_COMMAND_SHIFT)) & APBH_CH8_CMD_COMMAND_MASK) |
| #define APBH_CH8_CMD_CHAIN_MASK (0x4U) |
| #define APBH_CH8_CMD_CHAIN_SHIFT (2U) |
| #define APBH_CH8_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_CHAIN_SHIFT)) & APBH_CH8_CMD_CHAIN_MASK) |
| #define APBH_CH8_CMD_IRQONCMPLT_MASK (0x8U) |
| #define APBH_CH8_CMD_IRQONCMPLT_SHIFT (3U) |
| #define APBH_CH8_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_IRQONCMPLT_SHIFT)) & APBH_CH8_CMD_IRQONCMPLT_MASK) |
| #define APBH_CH8_CMD_NANDLOCK_MASK (0x10U) |
| #define APBH_CH8_CMD_NANDLOCK_SHIFT (4U) |
| #define APBH_CH8_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_NANDLOCK_SHIFT)) & APBH_CH8_CMD_NANDLOCK_MASK) |
| #define APBH_CH8_CMD_NANDWAIT4READY_MASK (0x20U) |
| #define APBH_CH8_CMD_NANDWAIT4READY_SHIFT (5U) |
| #define APBH_CH8_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH8_CMD_NANDWAIT4READY_MASK) |
| #define APBH_CH8_CMD_SEMAPHORE_MASK (0x40U) |
| #define APBH_CH8_CMD_SEMAPHORE_SHIFT (6U) |
| #define APBH_CH8_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_SEMAPHORE_SHIFT)) & APBH_CH8_CMD_SEMAPHORE_MASK) |
| #define APBH_CH8_CMD_WAIT4ENDCMD_MASK (0x80U) |
| #define APBH_CH8_CMD_WAIT4ENDCMD_SHIFT (7U) |
| #define APBH_CH8_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH8_CMD_WAIT4ENDCMD_MASK) |
| #define APBH_CH8_CMD_HALTONTERMINATE_MASK (0x100U) |
| #define APBH_CH8_CMD_HALTONTERMINATE_SHIFT (8U) |
| #define APBH_CH8_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH8_CMD_HALTONTERMINATE_MASK) |
| #define APBH_CH8_CMD_CMDWORDS_MASK (0xF000U) |
| #define APBH_CH8_CMD_CMDWORDS_SHIFT (12U) |
| #define APBH_CH8_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_CMDWORDS_SHIFT)) & APBH_CH8_CMD_CMDWORDS_MASK) |
| #define APBH_CH8_CMD_XFER_COUNT_MASK (0xFFFF0000U) |
| #define APBH_CH8_CMD_XFER_COUNT_SHIFT (16U) |
| #define APBH_CH8_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_XFER_COUNT_SHIFT)) & APBH_CH8_CMD_XFER_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name CH8_BAR - APBH DMA Channel n Buffer Address Register */ |
| /*! @{ */ |
| #define APBH_CH8_BAR_ADDRESS_MASK (0xFFFFFFFFU) |
| #define APBH_CH8_BAR_ADDRESS_SHIFT (0U) |
| #define APBH_CH8_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_BAR_ADDRESS_SHIFT)) & APBH_CH8_BAR_ADDRESS_MASK) |
| /*! @} */ |
| |
| /*! @name CH8_SEMA - APBH DMA Channel n Semaphore Register */ |
| /*! @{ */ |
| #define APBH_CH8_SEMA_INCREMENT_SEMA_MASK (0xFFU) |
| #define APBH_CH8_SEMA_INCREMENT_SEMA_SHIFT (0U) |
| #define APBH_CH8_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH8_SEMA_INCREMENT_SEMA_MASK) |
| #define APBH_CH8_SEMA_PHORE_MASK (0xFF0000U) |
| #define APBH_CH8_SEMA_PHORE_SHIFT (16U) |
| #define APBH_CH8_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_SEMA_PHORE_SHIFT)) & APBH_CH8_SEMA_PHORE_MASK) |
| /*! @} */ |
| |
| /*! @name CH8_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH8_DEBUG1_STATEMACHINE_MASK (0x1FU) |
| #define APBH_CH8_DEBUG1_STATEMACHINE_SHIFT (0U) |
| /*! STATEMACHINE |
| * 0b00000..This is the idle state of the DMA state machine. |
| * 0b00001..State in which the DMA is waiting to receive the first word of a command. |
| * 0b00010..State in which the DMA is waiting to receive the third word of a command. |
| * 0b00011..State in which the DMA is waiting to receive the second word of a command. |
| * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. |
| * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. |
| * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. |
| * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. |
| * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. |
| * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. |
| * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. |
| * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. |
| * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. |
| * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. |
| * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. |
| * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state |
| * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. |
| * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. |
| */ |
| #define APBH_CH8_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH8_DEBUG1_STATEMACHINE_MASK) |
| #define APBH_CH8_DEBUG1_RSVD1_MASK (0xFFFE0U) |
| #define APBH_CH8_DEBUG1_RSVD1_SHIFT (5U) |
| #define APBH_CH8_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RSVD1_SHIFT)) & APBH_CH8_DEBUG1_RSVD1_MASK) |
| #define APBH_CH8_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) |
| #define APBH_CH8_DEBUG1_WR_FIFO_FULL_SHIFT (20U) |
| #define APBH_CH8_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH8_DEBUG1_WR_FIFO_FULL_MASK) |
| #define APBH_CH8_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) |
| #define APBH_CH8_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) |
| #define APBH_CH8_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH8_DEBUG1_WR_FIFO_EMPTY_MASK) |
| #define APBH_CH8_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) |
| #define APBH_CH8_DEBUG1_RD_FIFO_FULL_SHIFT (22U) |
| #define APBH_CH8_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH8_DEBUG1_RD_FIFO_FULL_MASK) |
| #define APBH_CH8_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) |
| #define APBH_CH8_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) |
| #define APBH_CH8_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH8_DEBUG1_RD_FIFO_EMPTY_MASK) |
| #define APBH_CH8_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) |
| #define APBH_CH8_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) |
| #define APBH_CH8_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH8_DEBUG1_NEXTCMDADDRVALID_MASK) |
| #define APBH_CH8_DEBUG1_LOCK_MASK (0x2000000U) |
| #define APBH_CH8_DEBUG1_LOCK_SHIFT (25U) |
| #define APBH_CH8_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_LOCK_SHIFT)) & APBH_CH8_DEBUG1_LOCK_MASK) |
| #define APBH_CH8_DEBUG1_READY_MASK (0x4000000U) |
| #define APBH_CH8_DEBUG1_READY_SHIFT (26U) |
| #define APBH_CH8_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_READY_SHIFT)) & APBH_CH8_DEBUG1_READY_MASK) |
| #define APBH_CH8_DEBUG1_SENSE_MASK (0x8000000U) |
| #define APBH_CH8_DEBUG1_SENSE_SHIFT (27U) |
| #define APBH_CH8_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_SENSE_SHIFT)) & APBH_CH8_DEBUG1_SENSE_MASK) |
| #define APBH_CH8_DEBUG1_END_MASK (0x10000000U) |
| #define APBH_CH8_DEBUG1_END_SHIFT (28U) |
| #define APBH_CH8_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_END_SHIFT)) & APBH_CH8_DEBUG1_END_MASK) |
| #define APBH_CH8_DEBUG1_KICK_MASK (0x20000000U) |
| #define APBH_CH8_DEBUG1_KICK_SHIFT (29U) |
| #define APBH_CH8_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_KICK_SHIFT)) & APBH_CH8_DEBUG1_KICK_MASK) |
| #define APBH_CH8_DEBUG1_BURST_MASK (0x40000000U) |
| #define APBH_CH8_DEBUG1_BURST_SHIFT (30U) |
| #define APBH_CH8_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_BURST_SHIFT)) & APBH_CH8_DEBUG1_BURST_MASK) |
| #define APBH_CH8_DEBUG1_REQ_MASK (0x80000000U) |
| #define APBH_CH8_DEBUG1_REQ_SHIFT (31U) |
| #define APBH_CH8_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_REQ_SHIFT)) & APBH_CH8_DEBUG1_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name CH8_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH8_DEBUG2_AHB_BYTES_MASK (0xFFFFU) |
| #define APBH_CH8_DEBUG2_AHB_BYTES_SHIFT (0U) |
| #define APBH_CH8_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH8_DEBUG2_AHB_BYTES_MASK) |
| #define APBH_CH8_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) |
| #define APBH_CH8_DEBUG2_APB_BYTES_SHIFT (16U) |
| #define APBH_CH8_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH8_DEBUG2_APB_BYTES_MASK) |
| /*! @} */ |
| |
| /*! @name CH9_CURCMDAR - APBH DMA Channel n Current Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH9_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH9_CURCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH9_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH9_CURCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH9_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH9_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH9_NXTCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH9_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH9_NXTCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH9_CMD - APBH DMA Channel n Command Register */ |
| /*! @{ */ |
| #define APBH_CH9_CMD_COMMAND_MASK (0x3U) |
| #define APBH_CH9_CMD_COMMAND_SHIFT (0U) |
| /*! COMMAND |
| * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. |
| * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. |
| * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. |
| * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. |
| */ |
| #define APBH_CH9_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_COMMAND_SHIFT)) & APBH_CH9_CMD_COMMAND_MASK) |
| #define APBH_CH9_CMD_CHAIN_MASK (0x4U) |
| #define APBH_CH9_CMD_CHAIN_SHIFT (2U) |
| #define APBH_CH9_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_CHAIN_SHIFT)) & APBH_CH9_CMD_CHAIN_MASK) |
| #define APBH_CH9_CMD_IRQONCMPLT_MASK (0x8U) |
| #define APBH_CH9_CMD_IRQONCMPLT_SHIFT (3U) |
| #define APBH_CH9_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_IRQONCMPLT_SHIFT)) & APBH_CH9_CMD_IRQONCMPLT_MASK) |
| #define APBH_CH9_CMD_NANDLOCK_MASK (0x10U) |
| #define APBH_CH9_CMD_NANDLOCK_SHIFT (4U) |
| #define APBH_CH9_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_NANDLOCK_SHIFT)) & APBH_CH9_CMD_NANDLOCK_MASK) |
| #define APBH_CH9_CMD_NANDWAIT4READY_MASK (0x20U) |
| #define APBH_CH9_CMD_NANDWAIT4READY_SHIFT (5U) |
| #define APBH_CH9_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH9_CMD_NANDWAIT4READY_MASK) |
| #define APBH_CH9_CMD_SEMAPHORE_MASK (0x40U) |
| #define APBH_CH9_CMD_SEMAPHORE_SHIFT (6U) |
| #define APBH_CH9_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_SEMAPHORE_SHIFT)) & APBH_CH9_CMD_SEMAPHORE_MASK) |
| #define APBH_CH9_CMD_WAIT4ENDCMD_MASK (0x80U) |
| #define APBH_CH9_CMD_WAIT4ENDCMD_SHIFT (7U) |
| #define APBH_CH9_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH9_CMD_WAIT4ENDCMD_MASK) |
| #define APBH_CH9_CMD_HALTONTERMINATE_MASK (0x100U) |
| #define APBH_CH9_CMD_HALTONTERMINATE_SHIFT (8U) |
| #define APBH_CH9_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH9_CMD_HALTONTERMINATE_MASK) |
| #define APBH_CH9_CMD_CMDWORDS_MASK (0xF000U) |
| #define APBH_CH9_CMD_CMDWORDS_SHIFT (12U) |
| #define APBH_CH9_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_CMDWORDS_SHIFT)) & APBH_CH9_CMD_CMDWORDS_MASK) |
| #define APBH_CH9_CMD_XFER_COUNT_MASK (0xFFFF0000U) |
| #define APBH_CH9_CMD_XFER_COUNT_SHIFT (16U) |
| #define APBH_CH9_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_XFER_COUNT_SHIFT)) & APBH_CH9_CMD_XFER_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name CH9_BAR - APBH DMA Channel n Buffer Address Register */ |
| /*! @{ */ |
| #define APBH_CH9_BAR_ADDRESS_MASK (0xFFFFFFFFU) |
| #define APBH_CH9_BAR_ADDRESS_SHIFT (0U) |
| #define APBH_CH9_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_BAR_ADDRESS_SHIFT)) & APBH_CH9_BAR_ADDRESS_MASK) |
| /*! @} */ |
| |
| /*! @name CH9_SEMA - APBH DMA Channel n Semaphore Register */ |
| /*! @{ */ |
| #define APBH_CH9_SEMA_INCREMENT_SEMA_MASK (0xFFU) |
| #define APBH_CH9_SEMA_INCREMENT_SEMA_SHIFT (0U) |
| #define APBH_CH9_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH9_SEMA_INCREMENT_SEMA_MASK) |
| #define APBH_CH9_SEMA_PHORE_MASK (0xFF0000U) |
| #define APBH_CH9_SEMA_PHORE_SHIFT (16U) |
| #define APBH_CH9_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_SEMA_PHORE_SHIFT)) & APBH_CH9_SEMA_PHORE_MASK) |
| /*! @} */ |
| |
| /*! @name CH9_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH9_DEBUG1_STATEMACHINE_MASK (0x1FU) |
| #define APBH_CH9_DEBUG1_STATEMACHINE_SHIFT (0U) |
| /*! STATEMACHINE |
| * 0b00000..This is the idle state of the DMA state machine. |
| * 0b00001..State in which the DMA is waiting to receive the first word of a command. |
| * 0b00010..State in which the DMA is waiting to receive the third word of a command. |
| * 0b00011..State in which the DMA is waiting to receive the second word of a command. |
| * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. |
| * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. |
| * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. |
| * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. |
| * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. |
| * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. |
| * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. |
| * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. |
| * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. |
| * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. |
| * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. |
| * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state |
| * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. |
| * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. |
| */ |
| #define APBH_CH9_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH9_DEBUG1_STATEMACHINE_MASK) |
| #define APBH_CH9_DEBUG1_RSVD1_MASK (0xFFFE0U) |
| #define APBH_CH9_DEBUG1_RSVD1_SHIFT (5U) |
| #define APBH_CH9_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RSVD1_SHIFT)) & APBH_CH9_DEBUG1_RSVD1_MASK) |
| #define APBH_CH9_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) |
| #define APBH_CH9_DEBUG1_WR_FIFO_FULL_SHIFT (20U) |
| #define APBH_CH9_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH9_DEBUG1_WR_FIFO_FULL_MASK) |
| #define APBH_CH9_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) |
| #define APBH_CH9_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) |
| #define APBH_CH9_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH9_DEBUG1_WR_FIFO_EMPTY_MASK) |
| #define APBH_CH9_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) |
| #define APBH_CH9_DEBUG1_RD_FIFO_FULL_SHIFT (22U) |
| #define APBH_CH9_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH9_DEBUG1_RD_FIFO_FULL_MASK) |
| #define APBH_CH9_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) |
| #define APBH_CH9_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) |
| #define APBH_CH9_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH9_DEBUG1_RD_FIFO_EMPTY_MASK) |
| #define APBH_CH9_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) |
| #define APBH_CH9_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) |
| #define APBH_CH9_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH9_DEBUG1_NEXTCMDADDRVALID_MASK) |
| #define APBH_CH9_DEBUG1_LOCK_MASK (0x2000000U) |
| #define APBH_CH9_DEBUG1_LOCK_SHIFT (25U) |
| #define APBH_CH9_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_LOCK_SHIFT)) & APBH_CH9_DEBUG1_LOCK_MASK) |
| #define APBH_CH9_DEBUG1_READY_MASK (0x4000000U) |
| #define APBH_CH9_DEBUG1_READY_SHIFT (26U) |
| #define APBH_CH9_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_READY_SHIFT)) & APBH_CH9_DEBUG1_READY_MASK) |
| #define APBH_CH9_DEBUG1_SENSE_MASK (0x8000000U) |
| #define APBH_CH9_DEBUG1_SENSE_SHIFT (27U) |
| #define APBH_CH9_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_SENSE_SHIFT)) & APBH_CH9_DEBUG1_SENSE_MASK) |
| #define APBH_CH9_DEBUG1_END_MASK (0x10000000U) |
| #define APBH_CH9_DEBUG1_END_SHIFT (28U) |
| #define APBH_CH9_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_END_SHIFT)) & APBH_CH9_DEBUG1_END_MASK) |
| #define APBH_CH9_DEBUG1_KICK_MASK (0x20000000U) |
| #define APBH_CH9_DEBUG1_KICK_SHIFT (29U) |
| #define APBH_CH9_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_KICK_SHIFT)) & APBH_CH9_DEBUG1_KICK_MASK) |
| #define APBH_CH9_DEBUG1_BURST_MASK (0x40000000U) |
| #define APBH_CH9_DEBUG1_BURST_SHIFT (30U) |
| #define APBH_CH9_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_BURST_SHIFT)) & APBH_CH9_DEBUG1_BURST_MASK) |
| #define APBH_CH9_DEBUG1_REQ_MASK (0x80000000U) |
| #define APBH_CH9_DEBUG1_REQ_SHIFT (31U) |
| #define APBH_CH9_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_REQ_SHIFT)) & APBH_CH9_DEBUG1_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name CH9_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH9_DEBUG2_AHB_BYTES_MASK (0xFFFFU) |
| #define APBH_CH9_DEBUG2_AHB_BYTES_SHIFT (0U) |
| #define APBH_CH9_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH9_DEBUG2_AHB_BYTES_MASK) |
| #define APBH_CH9_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) |
| #define APBH_CH9_DEBUG2_APB_BYTES_SHIFT (16U) |
| #define APBH_CH9_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH9_DEBUG2_APB_BYTES_MASK) |
| /*! @} */ |
| |
| /*! @name CH10_CURCMDAR - APBH DMA Channel n Current Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH10_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH10_CURCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH10_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH10_CURCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH10_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH10_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH10_NXTCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH10_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH10_NXTCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH10_CMD - APBH DMA Channel n Command Register */ |
| /*! @{ */ |
| #define APBH_CH10_CMD_COMMAND_MASK (0x3U) |
| #define APBH_CH10_CMD_COMMAND_SHIFT (0U) |
| /*! COMMAND |
| * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. |
| * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. |
| * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. |
| * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. |
| */ |
| #define APBH_CH10_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_COMMAND_SHIFT)) & APBH_CH10_CMD_COMMAND_MASK) |
| #define APBH_CH10_CMD_CHAIN_MASK (0x4U) |
| #define APBH_CH10_CMD_CHAIN_SHIFT (2U) |
| #define APBH_CH10_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_CHAIN_SHIFT)) & APBH_CH10_CMD_CHAIN_MASK) |
| #define APBH_CH10_CMD_IRQONCMPLT_MASK (0x8U) |
| #define APBH_CH10_CMD_IRQONCMPLT_SHIFT (3U) |
| #define APBH_CH10_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_IRQONCMPLT_SHIFT)) & APBH_CH10_CMD_IRQONCMPLT_MASK) |
| #define APBH_CH10_CMD_NANDLOCK_MASK (0x10U) |
| #define APBH_CH10_CMD_NANDLOCK_SHIFT (4U) |
| #define APBH_CH10_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_NANDLOCK_SHIFT)) & APBH_CH10_CMD_NANDLOCK_MASK) |
| #define APBH_CH10_CMD_NANDWAIT4READY_MASK (0x20U) |
| #define APBH_CH10_CMD_NANDWAIT4READY_SHIFT (5U) |
| #define APBH_CH10_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH10_CMD_NANDWAIT4READY_MASK) |
| #define APBH_CH10_CMD_SEMAPHORE_MASK (0x40U) |
| #define APBH_CH10_CMD_SEMAPHORE_SHIFT (6U) |
| #define APBH_CH10_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_SEMAPHORE_SHIFT)) & APBH_CH10_CMD_SEMAPHORE_MASK) |
| #define APBH_CH10_CMD_WAIT4ENDCMD_MASK (0x80U) |
| #define APBH_CH10_CMD_WAIT4ENDCMD_SHIFT (7U) |
| #define APBH_CH10_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH10_CMD_WAIT4ENDCMD_MASK) |
| #define APBH_CH10_CMD_HALTONTERMINATE_MASK (0x100U) |
| #define APBH_CH10_CMD_HALTONTERMINATE_SHIFT (8U) |
| #define APBH_CH10_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH10_CMD_HALTONTERMINATE_MASK) |
| #define APBH_CH10_CMD_CMDWORDS_MASK (0xF000U) |
| #define APBH_CH10_CMD_CMDWORDS_SHIFT (12U) |
| #define APBH_CH10_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_CMDWORDS_SHIFT)) & APBH_CH10_CMD_CMDWORDS_MASK) |
| #define APBH_CH10_CMD_XFER_COUNT_MASK (0xFFFF0000U) |
| #define APBH_CH10_CMD_XFER_COUNT_SHIFT (16U) |
| #define APBH_CH10_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_XFER_COUNT_SHIFT)) & APBH_CH10_CMD_XFER_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name CH10_BAR - APBH DMA Channel n Buffer Address Register */ |
| /*! @{ */ |
| #define APBH_CH10_BAR_ADDRESS_MASK (0xFFFFFFFFU) |
| #define APBH_CH10_BAR_ADDRESS_SHIFT (0U) |
| #define APBH_CH10_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_BAR_ADDRESS_SHIFT)) & APBH_CH10_BAR_ADDRESS_MASK) |
| /*! @} */ |
| |
| /*! @name CH10_SEMA - APBH DMA Channel n Semaphore Register */ |
| /*! @{ */ |
| #define APBH_CH10_SEMA_INCREMENT_SEMA_MASK (0xFFU) |
| #define APBH_CH10_SEMA_INCREMENT_SEMA_SHIFT (0U) |
| #define APBH_CH10_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH10_SEMA_INCREMENT_SEMA_MASK) |
| #define APBH_CH10_SEMA_PHORE_MASK (0xFF0000U) |
| #define APBH_CH10_SEMA_PHORE_SHIFT (16U) |
| #define APBH_CH10_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_SEMA_PHORE_SHIFT)) & APBH_CH10_SEMA_PHORE_MASK) |
| /*! @} */ |
| |
| /*! @name CH10_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH10_DEBUG1_STATEMACHINE_MASK (0x1FU) |
| #define APBH_CH10_DEBUG1_STATEMACHINE_SHIFT (0U) |
| /*! STATEMACHINE |
| * 0b00000..This is the idle state of the DMA state machine. |
| * 0b00001..State in which the DMA is waiting to receive the first word of a command. |
| * 0b00010..State in which the DMA is waiting to receive the third word of a command. |
| * 0b00011..State in which the DMA is waiting to receive the second word of a command. |
| * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. |
| * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. |
| * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. |
| * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. |
| * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. |
| * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. |
| * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. |
| * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. |
| * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. |
| * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. |
| * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. |
| * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state |
| * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. |
| * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. |
| */ |
| #define APBH_CH10_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH10_DEBUG1_STATEMACHINE_MASK) |
| #define APBH_CH10_DEBUG1_RSVD1_MASK (0xFFFE0U) |
| #define APBH_CH10_DEBUG1_RSVD1_SHIFT (5U) |
| #define APBH_CH10_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RSVD1_SHIFT)) & APBH_CH10_DEBUG1_RSVD1_MASK) |
| #define APBH_CH10_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) |
| #define APBH_CH10_DEBUG1_WR_FIFO_FULL_SHIFT (20U) |
| #define APBH_CH10_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH10_DEBUG1_WR_FIFO_FULL_MASK) |
| #define APBH_CH10_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) |
| #define APBH_CH10_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) |
| #define APBH_CH10_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH10_DEBUG1_WR_FIFO_EMPTY_MASK) |
| #define APBH_CH10_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) |
| #define APBH_CH10_DEBUG1_RD_FIFO_FULL_SHIFT (22U) |
| #define APBH_CH10_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH10_DEBUG1_RD_FIFO_FULL_MASK) |
| #define APBH_CH10_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) |
| #define APBH_CH10_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) |
| #define APBH_CH10_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH10_DEBUG1_RD_FIFO_EMPTY_MASK) |
| #define APBH_CH10_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) |
| #define APBH_CH10_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) |
| #define APBH_CH10_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH10_DEBUG1_NEXTCMDADDRVALID_MASK) |
| #define APBH_CH10_DEBUG1_LOCK_MASK (0x2000000U) |
| #define APBH_CH10_DEBUG1_LOCK_SHIFT (25U) |
| #define APBH_CH10_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_LOCK_SHIFT)) & APBH_CH10_DEBUG1_LOCK_MASK) |
| #define APBH_CH10_DEBUG1_READY_MASK (0x4000000U) |
| #define APBH_CH10_DEBUG1_READY_SHIFT (26U) |
| #define APBH_CH10_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_READY_SHIFT)) & APBH_CH10_DEBUG1_READY_MASK) |
| #define APBH_CH10_DEBUG1_SENSE_MASK (0x8000000U) |
| #define APBH_CH10_DEBUG1_SENSE_SHIFT (27U) |
| #define APBH_CH10_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_SENSE_SHIFT)) & APBH_CH10_DEBUG1_SENSE_MASK) |
| #define APBH_CH10_DEBUG1_END_MASK (0x10000000U) |
| #define APBH_CH10_DEBUG1_END_SHIFT (28U) |
| #define APBH_CH10_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_END_SHIFT)) & APBH_CH10_DEBUG1_END_MASK) |
| #define APBH_CH10_DEBUG1_KICK_MASK (0x20000000U) |
| #define APBH_CH10_DEBUG1_KICK_SHIFT (29U) |
| #define APBH_CH10_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_KICK_SHIFT)) & APBH_CH10_DEBUG1_KICK_MASK) |
| #define APBH_CH10_DEBUG1_BURST_MASK (0x40000000U) |
| #define APBH_CH10_DEBUG1_BURST_SHIFT (30U) |
| #define APBH_CH10_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_BURST_SHIFT)) & APBH_CH10_DEBUG1_BURST_MASK) |
| #define APBH_CH10_DEBUG1_REQ_MASK (0x80000000U) |
| #define APBH_CH10_DEBUG1_REQ_SHIFT (31U) |
| #define APBH_CH10_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_REQ_SHIFT)) & APBH_CH10_DEBUG1_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name CH10_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH10_DEBUG2_AHB_BYTES_MASK (0xFFFFU) |
| #define APBH_CH10_DEBUG2_AHB_BYTES_SHIFT (0U) |
| #define APBH_CH10_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH10_DEBUG2_AHB_BYTES_MASK) |
| #define APBH_CH10_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) |
| #define APBH_CH10_DEBUG2_APB_BYTES_SHIFT (16U) |
| #define APBH_CH10_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH10_DEBUG2_APB_BYTES_MASK) |
| /*! @} */ |
| |
| /*! @name CH11_CURCMDAR - APBH DMA Channel n Current Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH11_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH11_CURCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH11_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH11_CURCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH11_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH11_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH11_NXTCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH11_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH11_NXTCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH11_CMD - APBH DMA Channel n Command Register */ |
| /*! @{ */ |
| #define APBH_CH11_CMD_COMMAND_MASK (0x3U) |
| #define APBH_CH11_CMD_COMMAND_SHIFT (0U) |
| /*! COMMAND |
| * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. |
| * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. |
| * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. |
| * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. |
| */ |
| #define APBH_CH11_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_COMMAND_SHIFT)) & APBH_CH11_CMD_COMMAND_MASK) |
| #define APBH_CH11_CMD_CHAIN_MASK (0x4U) |
| #define APBH_CH11_CMD_CHAIN_SHIFT (2U) |
| #define APBH_CH11_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_CHAIN_SHIFT)) & APBH_CH11_CMD_CHAIN_MASK) |
| #define APBH_CH11_CMD_IRQONCMPLT_MASK (0x8U) |
| #define APBH_CH11_CMD_IRQONCMPLT_SHIFT (3U) |
| #define APBH_CH11_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_IRQONCMPLT_SHIFT)) & APBH_CH11_CMD_IRQONCMPLT_MASK) |
| #define APBH_CH11_CMD_NANDLOCK_MASK (0x10U) |
| #define APBH_CH11_CMD_NANDLOCK_SHIFT (4U) |
| #define APBH_CH11_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_NANDLOCK_SHIFT)) & APBH_CH11_CMD_NANDLOCK_MASK) |
| #define APBH_CH11_CMD_NANDWAIT4READY_MASK (0x20U) |
| #define APBH_CH11_CMD_NANDWAIT4READY_SHIFT (5U) |
| #define APBH_CH11_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH11_CMD_NANDWAIT4READY_MASK) |
| #define APBH_CH11_CMD_SEMAPHORE_MASK (0x40U) |
| #define APBH_CH11_CMD_SEMAPHORE_SHIFT (6U) |
| #define APBH_CH11_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_SEMAPHORE_SHIFT)) & APBH_CH11_CMD_SEMAPHORE_MASK) |
| #define APBH_CH11_CMD_WAIT4ENDCMD_MASK (0x80U) |
| #define APBH_CH11_CMD_WAIT4ENDCMD_SHIFT (7U) |
| #define APBH_CH11_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH11_CMD_WAIT4ENDCMD_MASK) |
| #define APBH_CH11_CMD_HALTONTERMINATE_MASK (0x100U) |
| #define APBH_CH11_CMD_HALTONTERMINATE_SHIFT (8U) |
| #define APBH_CH11_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH11_CMD_HALTONTERMINATE_MASK) |
| #define APBH_CH11_CMD_CMDWORDS_MASK (0xF000U) |
| #define APBH_CH11_CMD_CMDWORDS_SHIFT (12U) |
| #define APBH_CH11_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_CMDWORDS_SHIFT)) & APBH_CH11_CMD_CMDWORDS_MASK) |
| #define APBH_CH11_CMD_XFER_COUNT_MASK (0xFFFF0000U) |
| #define APBH_CH11_CMD_XFER_COUNT_SHIFT (16U) |
| #define APBH_CH11_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_XFER_COUNT_SHIFT)) & APBH_CH11_CMD_XFER_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name CH11_BAR - APBH DMA Channel n Buffer Address Register */ |
| /*! @{ */ |
| #define APBH_CH11_BAR_ADDRESS_MASK (0xFFFFFFFFU) |
| #define APBH_CH11_BAR_ADDRESS_SHIFT (0U) |
| #define APBH_CH11_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_BAR_ADDRESS_SHIFT)) & APBH_CH11_BAR_ADDRESS_MASK) |
| /*! @} */ |
| |
| /*! @name CH11_SEMA - APBH DMA Channel n Semaphore Register */ |
| /*! @{ */ |
| #define APBH_CH11_SEMA_INCREMENT_SEMA_MASK (0xFFU) |
| #define APBH_CH11_SEMA_INCREMENT_SEMA_SHIFT (0U) |
| #define APBH_CH11_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH11_SEMA_INCREMENT_SEMA_MASK) |
| #define APBH_CH11_SEMA_PHORE_MASK (0xFF0000U) |
| #define APBH_CH11_SEMA_PHORE_SHIFT (16U) |
| #define APBH_CH11_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_SEMA_PHORE_SHIFT)) & APBH_CH11_SEMA_PHORE_MASK) |
| /*! @} */ |
| |
| /*! @name CH11_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH11_DEBUG1_STATEMACHINE_MASK (0x1FU) |
| #define APBH_CH11_DEBUG1_STATEMACHINE_SHIFT (0U) |
| /*! STATEMACHINE |
| * 0b00000..This is the idle state of the DMA state machine. |
| * 0b00001..State in which the DMA is waiting to receive the first word of a command. |
| * 0b00010..State in which the DMA is waiting to receive the third word of a command. |
| * 0b00011..State in which the DMA is waiting to receive the second word of a command. |
| * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. |
| * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. |
| * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. |
| * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. |
| * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. |
| * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. |
| * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. |
| * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. |
| * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. |
| * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. |
| * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. |
| * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state |
| * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. |
| * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. |
| */ |
| #define APBH_CH11_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH11_DEBUG1_STATEMACHINE_MASK) |
| #define APBH_CH11_DEBUG1_RSVD1_MASK (0xFFFE0U) |
| #define APBH_CH11_DEBUG1_RSVD1_SHIFT (5U) |
| #define APBH_CH11_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RSVD1_SHIFT)) & APBH_CH11_DEBUG1_RSVD1_MASK) |
| #define APBH_CH11_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) |
| #define APBH_CH11_DEBUG1_WR_FIFO_FULL_SHIFT (20U) |
| #define APBH_CH11_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH11_DEBUG1_WR_FIFO_FULL_MASK) |
| #define APBH_CH11_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) |
| #define APBH_CH11_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) |
| #define APBH_CH11_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH11_DEBUG1_WR_FIFO_EMPTY_MASK) |
| #define APBH_CH11_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) |
| #define APBH_CH11_DEBUG1_RD_FIFO_FULL_SHIFT (22U) |
| #define APBH_CH11_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH11_DEBUG1_RD_FIFO_FULL_MASK) |
| #define APBH_CH11_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) |
| #define APBH_CH11_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) |
| #define APBH_CH11_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH11_DEBUG1_RD_FIFO_EMPTY_MASK) |
| #define APBH_CH11_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) |
| #define APBH_CH11_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) |
| #define APBH_CH11_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH11_DEBUG1_NEXTCMDADDRVALID_MASK) |
| #define APBH_CH11_DEBUG1_LOCK_MASK (0x2000000U) |
| #define APBH_CH11_DEBUG1_LOCK_SHIFT (25U) |
| #define APBH_CH11_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_LOCK_SHIFT)) & APBH_CH11_DEBUG1_LOCK_MASK) |
| #define APBH_CH11_DEBUG1_READY_MASK (0x4000000U) |
| #define APBH_CH11_DEBUG1_READY_SHIFT (26U) |
| #define APBH_CH11_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_READY_SHIFT)) & APBH_CH11_DEBUG1_READY_MASK) |
| #define APBH_CH11_DEBUG1_SENSE_MASK (0x8000000U) |
| #define APBH_CH11_DEBUG1_SENSE_SHIFT (27U) |
| #define APBH_CH11_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_SENSE_SHIFT)) & APBH_CH11_DEBUG1_SENSE_MASK) |
| #define APBH_CH11_DEBUG1_END_MASK (0x10000000U) |
| #define APBH_CH11_DEBUG1_END_SHIFT (28U) |
| #define APBH_CH11_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_END_SHIFT)) & APBH_CH11_DEBUG1_END_MASK) |
| #define APBH_CH11_DEBUG1_KICK_MASK (0x20000000U) |
| #define APBH_CH11_DEBUG1_KICK_SHIFT (29U) |
| #define APBH_CH11_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_KICK_SHIFT)) & APBH_CH11_DEBUG1_KICK_MASK) |
| #define APBH_CH11_DEBUG1_BURST_MASK (0x40000000U) |
| #define APBH_CH11_DEBUG1_BURST_SHIFT (30U) |
| #define APBH_CH11_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_BURST_SHIFT)) & APBH_CH11_DEBUG1_BURST_MASK) |
| #define APBH_CH11_DEBUG1_REQ_MASK (0x80000000U) |
| #define APBH_CH11_DEBUG1_REQ_SHIFT (31U) |
| #define APBH_CH11_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_REQ_SHIFT)) & APBH_CH11_DEBUG1_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name CH11_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH11_DEBUG2_AHB_BYTES_MASK (0xFFFFU) |
| #define APBH_CH11_DEBUG2_AHB_BYTES_SHIFT (0U) |
| #define APBH_CH11_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH11_DEBUG2_AHB_BYTES_MASK) |
| #define APBH_CH11_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) |
| #define APBH_CH11_DEBUG2_APB_BYTES_SHIFT (16U) |
| #define APBH_CH11_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH11_DEBUG2_APB_BYTES_MASK) |
| /*! @} */ |
| |
| /*! @name CH12_CURCMDAR - APBH DMA Channel n Current Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH12_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH12_CURCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH12_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH12_CURCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH12_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH12_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH12_NXTCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH12_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH12_NXTCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH12_CMD - APBH DMA Channel n Command Register */ |
| /*! @{ */ |
| #define APBH_CH12_CMD_COMMAND_MASK (0x3U) |
| #define APBH_CH12_CMD_COMMAND_SHIFT (0U) |
| /*! COMMAND |
| * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. |
| * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. |
| * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. |
| * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. |
| */ |
| #define APBH_CH12_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_COMMAND_SHIFT)) & APBH_CH12_CMD_COMMAND_MASK) |
| #define APBH_CH12_CMD_CHAIN_MASK (0x4U) |
| #define APBH_CH12_CMD_CHAIN_SHIFT (2U) |
| #define APBH_CH12_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_CHAIN_SHIFT)) & APBH_CH12_CMD_CHAIN_MASK) |
| #define APBH_CH12_CMD_IRQONCMPLT_MASK (0x8U) |
| #define APBH_CH12_CMD_IRQONCMPLT_SHIFT (3U) |
| #define APBH_CH12_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_IRQONCMPLT_SHIFT)) & APBH_CH12_CMD_IRQONCMPLT_MASK) |
| #define APBH_CH12_CMD_NANDLOCK_MASK (0x10U) |
| #define APBH_CH12_CMD_NANDLOCK_SHIFT (4U) |
| #define APBH_CH12_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_NANDLOCK_SHIFT)) & APBH_CH12_CMD_NANDLOCK_MASK) |
| #define APBH_CH12_CMD_NANDWAIT4READY_MASK (0x20U) |
| #define APBH_CH12_CMD_NANDWAIT4READY_SHIFT (5U) |
| #define APBH_CH12_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH12_CMD_NANDWAIT4READY_MASK) |
| #define APBH_CH12_CMD_SEMAPHORE_MASK (0x40U) |
| #define APBH_CH12_CMD_SEMAPHORE_SHIFT (6U) |
| #define APBH_CH12_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_SEMAPHORE_SHIFT)) & APBH_CH12_CMD_SEMAPHORE_MASK) |
| #define APBH_CH12_CMD_WAIT4ENDCMD_MASK (0x80U) |
| #define APBH_CH12_CMD_WAIT4ENDCMD_SHIFT (7U) |
| #define APBH_CH12_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH12_CMD_WAIT4ENDCMD_MASK) |
| #define APBH_CH12_CMD_HALTONTERMINATE_MASK (0x100U) |
| #define APBH_CH12_CMD_HALTONTERMINATE_SHIFT (8U) |
| #define APBH_CH12_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH12_CMD_HALTONTERMINATE_MASK) |
| #define APBH_CH12_CMD_CMDWORDS_MASK (0xF000U) |
| #define APBH_CH12_CMD_CMDWORDS_SHIFT (12U) |
| #define APBH_CH12_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_CMDWORDS_SHIFT)) & APBH_CH12_CMD_CMDWORDS_MASK) |
| #define APBH_CH12_CMD_XFER_COUNT_MASK (0xFFFF0000U) |
| #define APBH_CH12_CMD_XFER_COUNT_SHIFT (16U) |
| #define APBH_CH12_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_XFER_COUNT_SHIFT)) & APBH_CH12_CMD_XFER_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name CH12_BAR - APBH DMA Channel n Buffer Address Register */ |
| /*! @{ */ |
| #define APBH_CH12_BAR_ADDRESS_MASK (0xFFFFFFFFU) |
| #define APBH_CH12_BAR_ADDRESS_SHIFT (0U) |
| #define APBH_CH12_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_BAR_ADDRESS_SHIFT)) & APBH_CH12_BAR_ADDRESS_MASK) |
| /*! @} */ |
| |
| /*! @name CH12_SEMA - APBH DMA Channel n Semaphore Register */ |
| /*! @{ */ |
| #define APBH_CH12_SEMA_INCREMENT_SEMA_MASK (0xFFU) |
| #define APBH_CH12_SEMA_INCREMENT_SEMA_SHIFT (0U) |
| #define APBH_CH12_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH12_SEMA_INCREMENT_SEMA_MASK) |
| #define APBH_CH12_SEMA_PHORE_MASK (0xFF0000U) |
| #define APBH_CH12_SEMA_PHORE_SHIFT (16U) |
| #define APBH_CH12_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_SEMA_PHORE_SHIFT)) & APBH_CH12_SEMA_PHORE_MASK) |
| /*! @} */ |
| |
| /*! @name CH12_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH12_DEBUG1_STATEMACHINE_MASK (0x1FU) |
| #define APBH_CH12_DEBUG1_STATEMACHINE_SHIFT (0U) |
| /*! STATEMACHINE |
| * 0b00000..This is the idle state of the DMA state machine. |
| * 0b00001..State in which the DMA is waiting to receive the first word of a command. |
| * 0b00010..State in which the DMA is waiting to receive the third word of a command. |
| * 0b00011..State in which the DMA is waiting to receive the second word of a command. |
| * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. |
| * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. |
| * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. |
| * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. |
| * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. |
| * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. |
| * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. |
| * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. |
| * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. |
| * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. |
| * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. |
| * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state |
| * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. |
| * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. |
| */ |
| #define APBH_CH12_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH12_DEBUG1_STATEMACHINE_MASK) |
| #define APBH_CH12_DEBUG1_RSVD1_MASK (0xFFFE0U) |
| #define APBH_CH12_DEBUG1_RSVD1_SHIFT (5U) |
| #define APBH_CH12_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RSVD1_SHIFT)) & APBH_CH12_DEBUG1_RSVD1_MASK) |
| #define APBH_CH12_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) |
| #define APBH_CH12_DEBUG1_WR_FIFO_FULL_SHIFT (20U) |
| #define APBH_CH12_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH12_DEBUG1_WR_FIFO_FULL_MASK) |
| #define APBH_CH12_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) |
| #define APBH_CH12_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) |
| #define APBH_CH12_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH12_DEBUG1_WR_FIFO_EMPTY_MASK) |
| #define APBH_CH12_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) |
| #define APBH_CH12_DEBUG1_RD_FIFO_FULL_SHIFT (22U) |
| #define APBH_CH12_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH12_DEBUG1_RD_FIFO_FULL_MASK) |
| #define APBH_CH12_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) |
| #define APBH_CH12_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) |
| #define APBH_CH12_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH12_DEBUG1_RD_FIFO_EMPTY_MASK) |
| #define APBH_CH12_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) |
| #define APBH_CH12_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) |
| #define APBH_CH12_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH12_DEBUG1_NEXTCMDADDRVALID_MASK) |
| #define APBH_CH12_DEBUG1_LOCK_MASK (0x2000000U) |
| #define APBH_CH12_DEBUG1_LOCK_SHIFT (25U) |
| #define APBH_CH12_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_LOCK_SHIFT)) & APBH_CH12_DEBUG1_LOCK_MASK) |
| #define APBH_CH12_DEBUG1_READY_MASK (0x4000000U) |
| #define APBH_CH12_DEBUG1_READY_SHIFT (26U) |
| #define APBH_CH12_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_READY_SHIFT)) & APBH_CH12_DEBUG1_READY_MASK) |
| #define APBH_CH12_DEBUG1_SENSE_MASK (0x8000000U) |
| #define APBH_CH12_DEBUG1_SENSE_SHIFT (27U) |
| #define APBH_CH12_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_SENSE_SHIFT)) & APBH_CH12_DEBUG1_SENSE_MASK) |
| #define APBH_CH12_DEBUG1_END_MASK (0x10000000U) |
| #define APBH_CH12_DEBUG1_END_SHIFT (28U) |
| #define APBH_CH12_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_END_SHIFT)) & APBH_CH12_DEBUG1_END_MASK) |
| #define APBH_CH12_DEBUG1_KICK_MASK (0x20000000U) |
| #define APBH_CH12_DEBUG1_KICK_SHIFT (29U) |
| #define APBH_CH12_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_KICK_SHIFT)) & APBH_CH12_DEBUG1_KICK_MASK) |
| #define APBH_CH12_DEBUG1_BURST_MASK (0x40000000U) |
| #define APBH_CH12_DEBUG1_BURST_SHIFT (30U) |
| #define APBH_CH12_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_BURST_SHIFT)) & APBH_CH12_DEBUG1_BURST_MASK) |
| #define APBH_CH12_DEBUG1_REQ_MASK (0x80000000U) |
| #define APBH_CH12_DEBUG1_REQ_SHIFT (31U) |
| #define APBH_CH12_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_REQ_SHIFT)) & APBH_CH12_DEBUG1_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name CH12_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH12_DEBUG2_AHB_BYTES_MASK (0xFFFFU) |
| #define APBH_CH12_DEBUG2_AHB_BYTES_SHIFT (0U) |
| #define APBH_CH12_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH12_DEBUG2_AHB_BYTES_MASK) |
| #define APBH_CH12_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) |
| #define APBH_CH12_DEBUG2_APB_BYTES_SHIFT (16U) |
| #define APBH_CH12_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH12_DEBUG2_APB_BYTES_MASK) |
| /*! @} */ |
| |
| /*! @name CH13_CURCMDAR - APBH DMA Channel n Current Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH13_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH13_CURCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH13_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH13_CURCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH13_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH13_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH13_NXTCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH13_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH13_NXTCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH13_CMD - APBH DMA Channel n Command Register */ |
| /*! @{ */ |
| #define APBH_CH13_CMD_COMMAND_MASK (0x3U) |
| #define APBH_CH13_CMD_COMMAND_SHIFT (0U) |
| /*! COMMAND |
| * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. |
| * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. |
| * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. |
| * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. |
| */ |
| #define APBH_CH13_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_COMMAND_SHIFT)) & APBH_CH13_CMD_COMMAND_MASK) |
| #define APBH_CH13_CMD_CHAIN_MASK (0x4U) |
| #define APBH_CH13_CMD_CHAIN_SHIFT (2U) |
| #define APBH_CH13_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_CHAIN_SHIFT)) & APBH_CH13_CMD_CHAIN_MASK) |
| #define APBH_CH13_CMD_IRQONCMPLT_MASK (0x8U) |
| #define APBH_CH13_CMD_IRQONCMPLT_SHIFT (3U) |
| #define APBH_CH13_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_IRQONCMPLT_SHIFT)) & APBH_CH13_CMD_IRQONCMPLT_MASK) |
| #define APBH_CH13_CMD_NANDLOCK_MASK (0x10U) |
| #define APBH_CH13_CMD_NANDLOCK_SHIFT (4U) |
| #define APBH_CH13_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_NANDLOCK_SHIFT)) & APBH_CH13_CMD_NANDLOCK_MASK) |
| #define APBH_CH13_CMD_NANDWAIT4READY_MASK (0x20U) |
| #define APBH_CH13_CMD_NANDWAIT4READY_SHIFT (5U) |
| #define APBH_CH13_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH13_CMD_NANDWAIT4READY_MASK) |
| #define APBH_CH13_CMD_SEMAPHORE_MASK (0x40U) |
| #define APBH_CH13_CMD_SEMAPHORE_SHIFT (6U) |
| #define APBH_CH13_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_SEMAPHORE_SHIFT)) & APBH_CH13_CMD_SEMAPHORE_MASK) |
| #define APBH_CH13_CMD_WAIT4ENDCMD_MASK (0x80U) |
| #define APBH_CH13_CMD_WAIT4ENDCMD_SHIFT (7U) |
| #define APBH_CH13_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH13_CMD_WAIT4ENDCMD_MASK) |
| #define APBH_CH13_CMD_HALTONTERMINATE_MASK (0x100U) |
| #define APBH_CH13_CMD_HALTONTERMINATE_SHIFT (8U) |
| #define APBH_CH13_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH13_CMD_HALTONTERMINATE_MASK) |
| #define APBH_CH13_CMD_CMDWORDS_MASK (0xF000U) |
| #define APBH_CH13_CMD_CMDWORDS_SHIFT (12U) |
| #define APBH_CH13_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_CMDWORDS_SHIFT)) & APBH_CH13_CMD_CMDWORDS_MASK) |
| #define APBH_CH13_CMD_XFER_COUNT_MASK (0xFFFF0000U) |
| #define APBH_CH13_CMD_XFER_COUNT_SHIFT (16U) |
| #define APBH_CH13_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_XFER_COUNT_SHIFT)) & APBH_CH13_CMD_XFER_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name CH13_BAR - APBH DMA Channel n Buffer Address Register */ |
| /*! @{ */ |
| #define APBH_CH13_BAR_ADDRESS_MASK (0xFFFFFFFFU) |
| #define APBH_CH13_BAR_ADDRESS_SHIFT (0U) |
| #define APBH_CH13_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_BAR_ADDRESS_SHIFT)) & APBH_CH13_BAR_ADDRESS_MASK) |
| /*! @} */ |
| |
| /*! @name CH13_SEMA - APBH DMA Channel n Semaphore Register */ |
| /*! @{ */ |
| #define APBH_CH13_SEMA_INCREMENT_SEMA_MASK (0xFFU) |
| #define APBH_CH13_SEMA_INCREMENT_SEMA_SHIFT (0U) |
| #define APBH_CH13_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH13_SEMA_INCREMENT_SEMA_MASK) |
| #define APBH_CH13_SEMA_PHORE_MASK (0xFF0000U) |
| #define APBH_CH13_SEMA_PHORE_SHIFT (16U) |
| #define APBH_CH13_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_SEMA_PHORE_SHIFT)) & APBH_CH13_SEMA_PHORE_MASK) |
| /*! @} */ |
| |
| /*! @name CH13_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH13_DEBUG1_STATEMACHINE_MASK (0x1FU) |
| #define APBH_CH13_DEBUG1_STATEMACHINE_SHIFT (0U) |
| /*! STATEMACHINE |
| * 0b00000..This is the idle state of the DMA state machine. |
| * 0b00001..State in which the DMA is waiting to receive the first word of a command. |
| * 0b00010..State in which the DMA is waiting to receive the third word of a command. |
| * 0b00011..State in which the DMA is waiting to receive the second word of a command. |
| * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. |
| * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. |
| * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. |
| * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. |
| * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. |
| * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. |
| * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. |
| * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. |
| * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. |
| * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. |
| * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. |
| * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state |
| * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. |
| * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. |
| */ |
| #define APBH_CH13_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH13_DEBUG1_STATEMACHINE_MASK) |
| #define APBH_CH13_DEBUG1_RSVD1_MASK (0xFFFE0U) |
| #define APBH_CH13_DEBUG1_RSVD1_SHIFT (5U) |
| #define APBH_CH13_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RSVD1_SHIFT)) & APBH_CH13_DEBUG1_RSVD1_MASK) |
| #define APBH_CH13_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) |
| #define APBH_CH13_DEBUG1_WR_FIFO_FULL_SHIFT (20U) |
| #define APBH_CH13_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH13_DEBUG1_WR_FIFO_FULL_MASK) |
| #define APBH_CH13_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) |
| #define APBH_CH13_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) |
| #define APBH_CH13_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH13_DEBUG1_WR_FIFO_EMPTY_MASK) |
| #define APBH_CH13_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) |
| #define APBH_CH13_DEBUG1_RD_FIFO_FULL_SHIFT (22U) |
| #define APBH_CH13_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH13_DEBUG1_RD_FIFO_FULL_MASK) |
| #define APBH_CH13_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) |
| #define APBH_CH13_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) |
| #define APBH_CH13_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH13_DEBUG1_RD_FIFO_EMPTY_MASK) |
| #define APBH_CH13_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) |
| #define APBH_CH13_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) |
| #define APBH_CH13_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH13_DEBUG1_NEXTCMDADDRVALID_MASK) |
| #define APBH_CH13_DEBUG1_LOCK_MASK (0x2000000U) |
| #define APBH_CH13_DEBUG1_LOCK_SHIFT (25U) |
| #define APBH_CH13_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_LOCK_SHIFT)) & APBH_CH13_DEBUG1_LOCK_MASK) |
| #define APBH_CH13_DEBUG1_READY_MASK (0x4000000U) |
| #define APBH_CH13_DEBUG1_READY_SHIFT (26U) |
| #define APBH_CH13_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_READY_SHIFT)) & APBH_CH13_DEBUG1_READY_MASK) |
| #define APBH_CH13_DEBUG1_SENSE_MASK (0x8000000U) |
| #define APBH_CH13_DEBUG1_SENSE_SHIFT (27U) |
| #define APBH_CH13_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_SENSE_SHIFT)) & APBH_CH13_DEBUG1_SENSE_MASK) |
| #define APBH_CH13_DEBUG1_END_MASK (0x10000000U) |
| #define APBH_CH13_DEBUG1_END_SHIFT (28U) |
| #define APBH_CH13_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_END_SHIFT)) & APBH_CH13_DEBUG1_END_MASK) |
| #define APBH_CH13_DEBUG1_KICK_MASK (0x20000000U) |
| #define APBH_CH13_DEBUG1_KICK_SHIFT (29U) |
| #define APBH_CH13_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_KICK_SHIFT)) & APBH_CH13_DEBUG1_KICK_MASK) |
| #define APBH_CH13_DEBUG1_BURST_MASK (0x40000000U) |
| #define APBH_CH13_DEBUG1_BURST_SHIFT (30U) |
| #define APBH_CH13_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_BURST_SHIFT)) & APBH_CH13_DEBUG1_BURST_MASK) |
| #define APBH_CH13_DEBUG1_REQ_MASK (0x80000000U) |
| #define APBH_CH13_DEBUG1_REQ_SHIFT (31U) |
| #define APBH_CH13_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_REQ_SHIFT)) & APBH_CH13_DEBUG1_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name CH13_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH13_DEBUG2_AHB_BYTES_MASK (0xFFFFU) |
| #define APBH_CH13_DEBUG2_AHB_BYTES_SHIFT (0U) |
| #define APBH_CH13_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH13_DEBUG2_AHB_BYTES_MASK) |
| #define APBH_CH13_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) |
| #define APBH_CH13_DEBUG2_APB_BYTES_SHIFT (16U) |
| #define APBH_CH13_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH13_DEBUG2_APB_BYTES_MASK) |
| /*! @} */ |
| |
| /*! @name CH14_CURCMDAR - APBH DMA Channel n Current Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH14_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH14_CURCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH14_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH14_CURCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH14_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH14_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH14_NXTCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH14_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH14_NXTCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH14_CMD - APBH DMA Channel n Command Register */ |
| /*! @{ */ |
| #define APBH_CH14_CMD_COMMAND_MASK (0x3U) |
| #define APBH_CH14_CMD_COMMAND_SHIFT (0U) |
| /*! COMMAND |
| * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. |
| * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. |
| * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. |
| * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. |
| */ |
| #define APBH_CH14_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_COMMAND_SHIFT)) & APBH_CH14_CMD_COMMAND_MASK) |
| #define APBH_CH14_CMD_CHAIN_MASK (0x4U) |
| #define APBH_CH14_CMD_CHAIN_SHIFT (2U) |
| #define APBH_CH14_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_CHAIN_SHIFT)) & APBH_CH14_CMD_CHAIN_MASK) |
| #define APBH_CH14_CMD_IRQONCMPLT_MASK (0x8U) |
| #define APBH_CH14_CMD_IRQONCMPLT_SHIFT (3U) |
| #define APBH_CH14_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_IRQONCMPLT_SHIFT)) & APBH_CH14_CMD_IRQONCMPLT_MASK) |
| #define APBH_CH14_CMD_NANDLOCK_MASK (0x10U) |
| #define APBH_CH14_CMD_NANDLOCK_SHIFT (4U) |
| #define APBH_CH14_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_NANDLOCK_SHIFT)) & APBH_CH14_CMD_NANDLOCK_MASK) |
| #define APBH_CH14_CMD_NANDWAIT4READY_MASK (0x20U) |
| #define APBH_CH14_CMD_NANDWAIT4READY_SHIFT (5U) |
| #define APBH_CH14_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH14_CMD_NANDWAIT4READY_MASK) |
| #define APBH_CH14_CMD_SEMAPHORE_MASK (0x40U) |
| #define APBH_CH14_CMD_SEMAPHORE_SHIFT (6U) |
| #define APBH_CH14_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_SEMAPHORE_SHIFT)) & APBH_CH14_CMD_SEMAPHORE_MASK) |
| #define APBH_CH14_CMD_WAIT4ENDCMD_MASK (0x80U) |
| #define APBH_CH14_CMD_WAIT4ENDCMD_SHIFT (7U) |
| #define APBH_CH14_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH14_CMD_WAIT4ENDCMD_MASK) |
| #define APBH_CH14_CMD_HALTONTERMINATE_MASK (0x100U) |
| #define APBH_CH14_CMD_HALTONTERMINATE_SHIFT (8U) |
| #define APBH_CH14_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH14_CMD_HALTONTERMINATE_MASK) |
| #define APBH_CH14_CMD_CMDWORDS_MASK (0xF000U) |
| #define APBH_CH14_CMD_CMDWORDS_SHIFT (12U) |
| #define APBH_CH14_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_CMDWORDS_SHIFT)) & APBH_CH14_CMD_CMDWORDS_MASK) |
| #define APBH_CH14_CMD_XFER_COUNT_MASK (0xFFFF0000U) |
| #define APBH_CH14_CMD_XFER_COUNT_SHIFT (16U) |
| #define APBH_CH14_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_XFER_COUNT_SHIFT)) & APBH_CH14_CMD_XFER_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name CH14_BAR - APBH DMA Channel n Buffer Address Register */ |
| /*! @{ */ |
| #define APBH_CH14_BAR_ADDRESS_MASK (0xFFFFFFFFU) |
| #define APBH_CH14_BAR_ADDRESS_SHIFT (0U) |
| #define APBH_CH14_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_BAR_ADDRESS_SHIFT)) & APBH_CH14_BAR_ADDRESS_MASK) |
| /*! @} */ |
| |
| /*! @name CH14_SEMA - APBH DMA Channel n Semaphore Register */ |
| /*! @{ */ |
| #define APBH_CH14_SEMA_INCREMENT_SEMA_MASK (0xFFU) |
| #define APBH_CH14_SEMA_INCREMENT_SEMA_SHIFT (0U) |
| #define APBH_CH14_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH14_SEMA_INCREMENT_SEMA_MASK) |
| #define APBH_CH14_SEMA_PHORE_MASK (0xFF0000U) |
| #define APBH_CH14_SEMA_PHORE_SHIFT (16U) |
| #define APBH_CH14_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_SEMA_PHORE_SHIFT)) & APBH_CH14_SEMA_PHORE_MASK) |
| /*! @} */ |
| |
| /*! @name CH14_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH14_DEBUG1_STATEMACHINE_MASK (0x1FU) |
| #define APBH_CH14_DEBUG1_STATEMACHINE_SHIFT (0U) |
| /*! STATEMACHINE |
| * 0b00000..This is the idle state of the DMA state machine. |
| * 0b00001..State in which the DMA is waiting to receive the first word of a command. |
| * 0b00010..State in which the DMA is waiting to receive the third word of a command. |
| * 0b00011..State in which the DMA is waiting to receive the second word of a command. |
| * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. |
| * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. |
| * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. |
| * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. |
| * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. |
| * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. |
| * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. |
| * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. |
| * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. |
| * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. |
| * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. |
| * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state |
| * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. |
| * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. |
| */ |
| #define APBH_CH14_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH14_DEBUG1_STATEMACHINE_MASK) |
| #define APBH_CH14_DEBUG1_RSVD1_MASK (0xFFFE0U) |
| #define APBH_CH14_DEBUG1_RSVD1_SHIFT (5U) |
| #define APBH_CH14_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RSVD1_SHIFT)) & APBH_CH14_DEBUG1_RSVD1_MASK) |
| #define APBH_CH14_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) |
| #define APBH_CH14_DEBUG1_WR_FIFO_FULL_SHIFT (20U) |
| #define APBH_CH14_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH14_DEBUG1_WR_FIFO_FULL_MASK) |
| #define APBH_CH14_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) |
| #define APBH_CH14_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) |
| #define APBH_CH14_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH14_DEBUG1_WR_FIFO_EMPTY_MASK) |
| #define APBH_CH14_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) |
| #define APBH_CH14_DEBUG1_RD_FIFO_FULL_SHIFT (22U) |
| #define APBH_CH14_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH14_DEBUG1_RD_FIFO_FULL_MASK) |
| #define APBH_CH14_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) |
| #define APBH_CH14_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) |
| #define APBH_CH14_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH14_DEBUG1_RD_FIFO_EMPTY_MASK) |
| #define APBH_CH14_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) |
| #define APBH_CH14_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) |
| #define APBH_CH14_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH14_DEBUG1_NEXTCMDADDRVALID_MASK) |
| #define APBH_CH14_DEBUG1_LOCK_MASK (0x2000000U) |
| #define APBH_CH14_DEBUG1_LOCK_SHIFT (25U) |
| #define APBH_CH14_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_LOCK_SHIFT)) & APBH_CH14_DEBUG1_LOCK_MASK) |
| #define APBH_CH14_DEBUG1_READY_MASK (0x4000000U) |
| #define APBH_CH14_DEBUG1_READY_SHIFT (26U) |
| #define APBH_CH14_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_READY_SHIFT)) & APBH_CH14_DEBUG1_READY_MASK) |
| #define APBH_CH14_DEBUG1_SENSE_MASK (0x8000000U) |
| #define APBH_CH14_DEBUG1_SENSE_SHIFT (27U) |
| #define APBH_CH14_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_SENSE_SHIFT)) & APBH_CH14_DEBUG1_SENSE_MASK) |
| #define APBH_CH14_DEBUG1_END_MASK (0x10000000U) |
| #define APBH_CH14_DEBUG1_END_SHIFT (28U) |
| #define APBH_CH14_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_END_SHIFT)) & APBH_CH14_DEBUG1_END_MASK) |
| #define APBH_CH14_DEBUG1_KICK_MASK (0x20000000U) |
| #define APBH_CH14_DEBUG1_KICK_SHIFT (29U) |
| #define APBH_CH14_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_KICK_SHIFT)) & APBH_CH14_DEBUG1_KICK_MASK) |
| #define APBH_CH14_DEBUG1_BURST_MASK (0x40000000U) |
| #define APBH_CH14_DEBUG1_BURST_SHIFT (30U) |
| #define APBH_CH14_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_BURST_SHIFT)) & APBH_CH14_DEBUG1_BURST_MASK) |
| #define APBH_CH14_DEBUG1_REQ_MASK (0x80000000U) |
| #define APBH_CH14_DEBUG1_REQ_SHIFT (31U) |
| #define APBH_CH14_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_REQ_SHIFT)) & APBH_CH14_DEBUG1_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name CH14_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH14_DEBUG2_AHB_BYTES_MASK (0xFFFFU) |
| #define APBH_CH14_DEBUG2_AHB_BYTES_SHIFT (0U) |
| #define APBH_CH14_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH14_DEBUG2_AHB_BYTES_MASK) |
| #define APBH_CH14_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) |
| #define APBH_CH14_DEBUG2_APB_BYTES_SHIFT (16U) |
| #define APBH_CH14_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH14_DEBUG2_APB_BYTES_MASK) |
| /*! @} */ |
| |
| /*! @name CH15_CURCMDAR - APBH DMA Channel n Current Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH15_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH15_CURCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH15_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH15_CURCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH15_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ |
| /*! @{ */ |
| #define APBH_CH15_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) |
| #define APBH_CH15_NXTCMDAR_CMD_ADDR_SHIFT (0U) |
| #define APBH_CH15_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH15_NXTCMDAR_CMD_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CH15_CMD - APBH DMA Channel n Command Register */ |
| /*! @{ */ |
| #define APBH_CH15_CMD_COMMAND_MASK (0x3U) |
| #define APBH_CH15_CMD_COMMAND_SHIFT (0U) |
| /*! COMMAND |
| * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. |
| * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. |
| * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. |
| * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. |
| */ |
| #define APBH_CH15_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_COMMAND_SHIFT)) & APBH_CH15_CMD_COMMAND_MASK) |
| #define APBH_CH15_CMD_CHAIN_MASK (0x4U) |
| #define APBH_CH15_CMD_CHAIN_SHIFT (2U) |
| #define APBH_CH15_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_CHAIN_SHIFT)) & APBH_CH15_CMD_CHAIN_MASK) |
| #define APBH_CH15_CMD_IRQONCMPLT_MASK (0x8U) |
| #define APBH_CH15_CMD_IRQONCMPLT_SHIFT (3U) |
| #define APBH_CH15_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_IRQONCMPLT_SHIFT)) & APBH_CH15_CMD_IRQONCMPLT_MASK) |
| #define APBH_CH15_CMD_NANDLOCK_MASK (0x10U) |
| #define APBH_CH15_CMD_NANDLOCK_SHIFT (4U) |
| #define APBH_CH15_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_NANDLOCK_SHIFT)) & APBH_CH15_CMD_NANDLOCK_MASK) |
| #define APBH_CH15_CMD_NANDWAIT4READY_MASK (0x20U) |
| #define APBH_CH15_CMD_NANDWAIT4READY_SHIFT (5U) |
| #define APBH_CH15_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH15_CMD_NANDWAIT4READY_MASK) |
| #define APBH_CH15_CMD_SEMAPHORE_MASK (0x40U) |
| #define APBH_CH15_CMD_SEMAPHORE_SHIFT (6U) |
| #define APBH_CH15_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_SEMAPHORE_SHIFT)) & APBH_CH15_CMD_SEMAPHORE_MASK) |
| #define APBH_CH15_CMD_WAIT4ENDCMD_MASK (0x80U) |
| #define APBH_CH15_CMD_WAIT4ENDCMD_SHIFT (7U) |
| #define APBH_CH15_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH15_CMD_WAIT4ENDCMD_MASK) |
| #define APBH_CH15_CMD_HALTONTERMINATE_MASK (0x100U) |
| #define APBH_CH15_CMD_HALTONTERMINATE_SHIFT (8U) |
| #define APBH_CH15_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH15_CMD_HALTONTERMINATE_MASK) |
| #define APBH_CH15_CMD_CMDWORDS_MASK (0xF000U) |
| #define APBH_CH15_CMD_CMDWORDS_SHIFT (12U) |
| #define APBH_CH15_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_CMDWORDS_SHIFT)) & APBH_CH15_CMD_CMDWORDS_MASK) |
| #define APBH_CH15_CMD_XFER_COUNT_MASK (0xFFFF0000U) |
| #define APBH_CH15_CMD_XFER_COUNT_SHIFT (16U) |
| #define APBH_CH15_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_XFER_COUNT_SHIFT)) & APBH_CH15_CMD_XFER_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name CH15_BAR - APBH DMA Channel n Buffer Address Register */ |
| /*! @{ */ |
| #define APBH_CH15_BAR_ADDRESS_MASK (0xFFFFFFFFU) |
| #define APBH_CH15_BAR_ADDRESS_SHIFT (0U) |
| #define APBH_CH15_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_BAR_ADDRESS_SHIFT)) & APBH_CH15_BAR_ADDRESS_MASK) |
| /*! @} */ |
| |
| /*! @name CH15_SEMA - APBH DMA Channel n Semaphore Register */ |
| /*! @{ */ |
| #define APBH_CH15_SEMA_INCREMENT_SEMA_MASK (0xFFU) |
| #define APBH_CH15_SEMA_INCREMENT_SEMA_SHIFT (0U) |
| #define APBH_CH15_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH15_SEMA_INCREMENT_SEMA_MASK) |
| #define APBH_CH15_SEMA_PHORE_MASK (0xFF0000U) |
| #define APBH_CH15_SEMA_PHORE_SHIFT (16U) |
| #define APBH_CH15_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_SEMA_PHORE_SHIFT)) & APBH_CH15_SEMA_PHORE_MASK) |
| /*! @} */ |
| |
| /*! @name CH15_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH15_DEBUG1_STATEMACHINE_MASK (0x1FU) |
| #define APBH_CH15_DEBUG1_STATEMACHINE_SHIFT (0U) |
| /*! STATEMACHINE |
| * 0b00000..This is the idle state of the DMA state machine. |
| * 0b00001..State in which the DMA is waiting to receive the first word of a command. |
| * 0b00010..State in which the DMA is waiting to receive the third word of a command. |
| * 0b00011..State in which the DMA is waiting to receive the second word of a command. |
| * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. |
| * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. |
| * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. |
| * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. |
| * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. |
| * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. |
| * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. |
| * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. |
| * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. |
| * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. |
| * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. |
| * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. |
| * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state |
| * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. |
| * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. |
| */ |
| #define APBH_CH15_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH15_DEBUG1_STATEMACHINE_MASK) |
| #define APBH_CH15_DEBUG1_RSVD1_MASK (0xFFFE0U) |
| #define APBH_CH15_DEBUG1_RSVD1_SHIFT (5U) |
| #define APBH_CH15_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RSVD1_SHIFT)) & APBH_CH15_DEBUG1_RSVD1_MASK) |
| #define APBH_CH15_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) |
| #define APBH_CH15_DEBUG1_WR_FIFO_FULL_SHIFT (20U) |
| #define APBH_CH15_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH15_DEBUG1_WR_FIFO_FULL_MASK) |
| #define APBH_CH15_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) |
| #define APBH_CH15_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) |
| #define APBH_CH15_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH15_DEBUG1_WR_FIFO_EMPTY_MASK) |
| #define APBH_CH15_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) |
| #define APBH_CH15_DEBUG1_RD_FIFO_FULL_SHIFT (22U) |
| #define APBH_CH15_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH15_DEBUG1_RD_FIFO_FULL_MASK) |
| #define APBH_CH15_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) |
| #define APBH_CH15_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) |
| #define APBH_CH15_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH15_DEBUG1_RD_FIFO_EMPTY_MASK) |
| #define APBH_CH15_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) |
| #define APBH_CH15_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) |
| #define APBH_CH15_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH15_DEBUG1_NEXTCMDADDRVALID_MASK) |
| #define APBH_CH15_DEBUG1_LOCK_MASK (0x2000000U) |
| #define APBH_CH15_DEBUG1_LOCK_SHIFT (25U) |
| #define APBH_CH15_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_LOCK_SHIFT)) & APBH_CH15_DEBUG1_LOCK_MASK) |
| #define APBH_CH15_DEBUG1_READY_MASK (0x4000000U) |
| #define APBH_CH15_DEBUG1_READY_SHIFT (26U) |
| #define APBH_CH15_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_READY_SHIFT)) & APBH_CH15_DEBUG1_READY_MASK) |
| #define APBH_CH15_DEBUG1_SENSE_MASK (0x8000000U) |
| #define APBH_CH15_DEBUG1_SENSE_SHIFT (27U) |
| #define APBH_CH15_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_SENSE_SHIFT)) & APBH_CH15_DEBUG1_SENSE_MASK) |
| #define APBH_CH15_DEBUG1_END_MASK (0x10000000U) |
| #define APBH_CH15_DEBUG1_END_SHIFT (28U) |
| #define APBH_CH15_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_END_SHIFT)) & APBH_CH15_DEBUG1_END_MASK) |
| #define APBH_CH15_DEBUG1_KICK_MASK (0x20000000U) |
| #define APBH_CH15_DEBUG1_KICK_SHIFT (29U) |
| #define APBH_CH15_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_KICK_SHIFT)) & APBH_CH15_DEBUG1_KICK_MASK) |
| #define APBH_CH15_DEBUG1_BURST_MASK (0x40000000U) |
| #define APBH_CH15_DEBUG1_BURST_SHIFT (30U) |
| #define APBH_CH15_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_BURST_SHIFT)) & APBH_CH15_DEBUG1_BURST_MASK) |
| #define APBH_CH15_DEBUG1_REQ_MASK (0x80000000U) |
| #define APBH_CH15_DEBUG1_REQ_SHIFT (31U) |
| #define APBH_CH15_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_REQ_SHIFT)) & APBH_CH15_DEBUG1_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name CH15_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ |
| /*! @{ */ |
| #define APBH_CH15_DEBUG2_AHB_BYTES_MASK (0xFFFFU) |
| #define APBH_CH15_DEBUG2_AHB_BYTES_SHIFT (0U) |
| #define APBH_CH15_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH15_DEBUG2_AHB_BYTES_MASK) |
| #define APBH_CH15_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) |
| #define APBH_CH15_DEBUG2_APB_BYTES_SHIFT (16U) |
| #define APBH_CH15_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH15_DEBUG2_APB_BYTES_MASK) |
| /*! @} */ |
| |
| /*! @name VERSION - APBH Bridge Version Register */ |
| /*! @{ */ |
| #define APBH_VERSION_STEP_MASK (0xFFFFU) |
| #define APBH_VERSION_STEP_SHIFT (0U) |
| #define APBH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK) |
| #define APBH_VERSION_MINOR_MASK (0xFF0000U) |
| #define APBH_VERSION_MINOR_SHIFT (16U) |
| #define APBH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK) |
| #define APBH_VERSION_MAJOR_MASK (0xFF000000U) |
| #define APBH_VERSION_MAJOR_SHIFT (24U) |
| #define APBH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group APBH_Register_Masks */ |
| |
| |
| /* APBH - Peripheral instance base addresses */ |
| /** Peripheral APBH base address */ |
| #define APBH_BASE (0x33000000u) |
| /** Peripheral APBH base pointer */ |
| #define APBH ((APBH_Type *)APBH_BASE) |
| /** Array initializer of APBH peripheral base addresses */ |
| #define APBH_BASE_ADDRS { APBH_BASE } |
| /** Array initializer of APBH peripheral base pointers */ |
| #define APBH_BASE_PTRS { APBH } |
| /** Interrupt vectors for the APBH peripheral type */ |
| #define APBH_IRQS { APBHDMA_IRQn } |
| |
| /*! |
| * @} |
| */ /* end of group APBH_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- BCH Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** BCH - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t CTRL; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */ |
| __IO uint32_t CTRL_SET; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */ |
| __IO uint32_t CTRL_CLR; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */ |
| __IO uint32_t CTRL_TOG; /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */ |
| __I uint32_t STATUS0; /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */ |
| __I uint32_t STATUS0_SET; /**< Hardware ECC Accelerator Status Register 0, offset: 0x14 */ |
| __I uint32_t STATUS0_CLR; /**< Hardware ECC Accelerator Status Register 0, offset: 0x18 */ |
| __I uint32_t STATUS0_TOG; /**< Hardware ECC Accelerator Status Register 0, offset: 0x1C */ |
| __IO uint32_t MODE; /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */ |
| __IO uint32_t MODE_SET; /**< Hardware ECC Accelerator Mode Register, offset: 0x24 */ |
| __IO uint32_t MODE_CLR; /**< Hardware ECC Accelerator Mode Register, offset: 0x28 */ |
| __IO uint32_t MODE_TOG; /**< Hardware ECC Accelerator Mode Register, offset: 0x2C */ |
| __IO uint32_t ENCODEPTR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */ |
| __IO uint32_t ENCODEPTR_SET; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x34 */ |
| __IO uint32_t ENCODEPTR_CLR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x38 */ |
| __IO uint32_t ENCODEPTR_TOG; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x3C */ |
| __IO uint32_t DATAPTR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */ |
| __IO uint32_t DATAPTR_SET; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x44 */ |
| __IO uint32_t DATAPTR_CLR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x48 */ |
| __IO uint32_t DATAPTR_TOG; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x4C */ |
| __IO uint32_t METAPTR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */ |
| __IO uint32_t METAPTR_SET; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x54 */ |
| __IO uint32_t METAPTR_CLR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x58 */ |
| __IO uint32_t METAPTR_TOG; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x5C */ |
| uint8_t RESERVED_0[16]; |
| __IO uint32_t LAYOUTSELECT; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */ |
| __IO uint32_t LAYOUTSELECT_SET; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x74 */ |
| __IO uint32_t LAYOUTSELECT_CLR; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x78 */ |
| __IO uint32_t LAYOUTSELECT_TOG; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x7C */ |
| __IO uint32_t FLASH0LAYOUT0; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */ |
| __IO uint32_t FLASH0LAYOUT0_SET; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x84 */ |
| __IO uint32_t FLASH0LAYOUT0_CLR; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x88 */ |
| __IO uint32_t FLASH0LAYOUT0_TOG; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x8C */ |
| __IO uint32_t FLASH0LAYOUT1; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */ |
| __IO uint32_t FLASH0LAYOUT1_SET; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x94 */ |
| __IO uint32_t FLASH0LAYOUT1_CLR; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x98 */ |
| __IO uint32_t FLASH0LAYOUT1_TOG; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x9C */ |
| __IO uint32_t FLASH1LAYOUT0; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */ |
| __IO uint32_t FLASH1LAYOUT0_SET; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA4 */ |
| __IO uint32_t FLASH1LAYOUT0_CLR; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA8 */ |
| __IO uint32_t FLASH1LAYOUT0_TOG; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xAC */ |
| __IO uint32_t FLASH1LAYOUT1; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */ |
| __IO uint32_t FLASH1LAYOUT1_SET; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB4 */ |
| __IO uint32_t FLASH1LAYOUT1_CLR; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB8 */ |
| __IO uint32_t FLASH1LAYOUT1_TOG; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xBC */ |
| __IO uint32_t FLASH2LAYOUT0; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */ |
| __IO uint32_t FLASH2LAYOUT0_SET; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC4 */ |
| __IO uint32_t FLASH2LAYOUT0_CLR; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC8 */ |
| __IO uint32_t FLASH2LAYOUT0_TOG; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xCC */ |
| __IO uint32_t FLASH2LAYOUT1; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */ |
| __IO uint32_t FLASH2LAYOUT1_SET; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD4 */ |
| __IO uint32_t FLASH2LAYOUT1_CLR; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD8 */ |
| __IO uint32_t FLASH2LAYOUT1_TOG; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xDC */ |
| __IO uint32_t FLASH3LAYOUT0; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */ |
| __IO uint32_t FLASH3LAYOUT0_SET; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE4 */ |
| __IO uint32_t FLASH3LAYOUT0_CLR; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE8 */ |
| __IO uint32_t FLASH3LAYOUT0_TOG; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xEC */ |
| __IO uint32_t FLASH3LAYOUT1; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */ |
| __IO uint32_t FLASH3LAYOUT1_SET; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF4 */ |
| __IO uint32_t FLASH3LAYOUT1_CLR; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF8 */ |
| __IO uint32_t FLASH3LAYOUT1_TOG; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xFC */ |
| __IO uint32_t DEBUG0; /**< Hardware BCH ECC Debug Register0, offset: 0x100 */ |
| __IO uint32_t DEBUG0_SET; /**< Hardware BCH ECC Debug Register0, offset: 0x104 */ |
| __IO uint32_t DEBUG0_CLR; /**< Hardware BCH ECC Debug Register0, offset: 0x108 */ |
| __IO uint32_t DEBUG0_TOG; /**< Hardware BCH ECC Debug Register0, offset: 0x10C */ |
| __I uint32_t DBGKESREAD; /**< KES Debug Read Register, offset: 0x110 */ |
| __I uint32_t DBGKESREAD_SET; /**< KES Debug Read Register, offset: 0x114 */ |
| __I uint32_t DBGKESREAD_CLR; /**< KES Debug Read Register, offset: 0x118 */ |
| __I uint32_t DBGKESREAD_TOG; /**< KES Debug Read Register, offset: 0x11C */ |
| __I uint32_t DBGCSFEREAD; /**< Chien Search Debug Read Register, offset: 0x120 */ |
| __I uint32_t DBGCSFEREAD_SET; /**< Chien Search Debug Read Register, offset: 0x124 */ |
| __I uint32_t DBGCSFEREAD_CLR; /**< Chien Search Debug Read Register, offset: 0x128 */ |
| __I uint32_t DBGCSFEREAD_TOG; /**< Chien Search Debug Read Register, offset: 0x12C */ |
| __I uint32_t DBGSYNDGENREAD; /**< Syndrome Generator Debug Read Register, offset: 0x130 */ |
| __I uint32_t DBGSYNDGENREAD_SET; /**< Syndrome Generator Debug Read Register, offset: 0x134 */ |
| __I uint32_t DBGSYNDGENREAD_CLR; /**< Syndrome Generator Debug Read Register, offset: 0x138 */ |
| __I uint32_t DBGSYNDGENREAD_TOG; /**< Syndrome Generator Debug Read Register, offset: 0x13C */ |
| __I uint32_t DBGAHBMREAD; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */ |
| __I uint32_t DBGAHBMREAD_SET; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x144 */ |
| __I uint32_t DBGAHBMREAD_CLR; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x148 */ |
| __I uint32_t DBGAHBMREAD_TOG; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x14C */ |
| __I uint32_t BLOCKNAME; /**< Block Name Register, offset: 0x150 */ |
| __I uint32_t BLOCKNAME_SET; /**< Block Name Register, offset: 0x154 */ |
| __I uint32_t BLOCKNAME_CLR; /**< Block Name Register, offset: 0x158 */ |
| __I uint32_t BLOCKNAME_TOG; /**< Block Name Register, offset: 0x15C */ |
| __I uint32_t VERSION; /**< BCH Version Register, offset: 0x160 */ |
| __I uint32_t VERSION_SET; /**< BCH Version Register, offset: 0x164 */ |
| __I uint32_t VERSION_CLR; /**< BCH Version Register, offset: 0x168 */ |
| __I uint32_t VERSION_TOG; /**< BCH Version Register, offset: 0x16C */ |
| __IO uint32_t DEBUG1; /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */ |
| __IO uint32_t DEBUG1_SET; /**< Hardware BCH ECC Debug Register 1, offset: 0x174 */ |
| __IO uint32_t DEBUG1_CLR; /**< Hardware BCH ECC Debug Register 1, offset: 0x178 */ |
| __IO uint32_t DEBUG1_TOG; /**< Hardware BCH ECC Debug Register 1, offset: 0x17C */ |
| } BCH_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- BCH Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup BCH_Register_Masks BCH Register Masks |
| * @{ |
| */ |
| |
| /*! @name CTRL - Hardware BCH ECC Accelerator Control Register */ |
| /*! @{ */ |
| #define BCH_CTRL_COMPLETE_IRQ_MASK (0x1U) |
| #define BCH_CTRL_COMPLETE_IRQ_SHIFT (0U) |
| #define BCH_CTRL_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK) |
| #define BCH_CTRL_RSVD0_MASK (0x2U) |
| #define BCH_CTRL_RSVD0_SHIFT (1U) |
| #define BCH_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK) |
| #define BCH_CTRL_DEBUG_STALL_IRQ_MASK (0x4U) |
| #define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT (2U) |
| #define BCH_CTRL_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK) |
| #define BCH_CTRL_BM_ERROR_IRQ_MASK (0x8U) |
| #define BCH_CTRL_BM_ERROR_IRQ_SHIFT (3U) |
| #define BCH_CTRL_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK) |
| #define BCH_CTRL_RSVD1_MASK (0xF0U) |
| #define BCH_CTRL_RSVD1_SHIFT (4U) |
| #define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK) |
| #define BCH_CTRL_COMPLETE_IRQ_EN_MASK (0x100U) |
| #define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT (8U) |
| #define BCH_CTRL_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK) |
| #define BCH_CTRL_RSVD2_MASK (0x200U) |
| #define BCH_CTRL_RSVD2_SHIFT (9U) |
| #define BCH_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK) |
| #define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK (0x400U) |
| #define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT (10U) |
| #define BCH_CTRL_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK) |
| #define BCH_CTRL_RSVD3_MASK (0xF800U) |
| #define BCH_CTRL_RSVD3_SHIFT (11U) |
| #define BCH_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK) |
| #define BCH_CTRL_M2M_ENABLE_MASK (0x10000U) |
| #define BCH_CTRL_M2M_ENABLE_SHIFT (16U) |
| #define BCH_CTRL_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK) |
| #define BCH_CTRL_M2M_ENCODE_MASK (0x20000U) |
| #define BCH_CTRL_M2M_ENCODE_SHIFT (17U) |
| #define BCH_CTRL_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK) |
| #define BCH_CTRL_M2M_LAYOUT_MASK (0xC0000U) |
| #define BCH_CTRL_M2M_LAYOUT_SHIFT (18U) |
| #define BCH_CTRL_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK) |
| #define BCH_CTRL_RSVD4_MASK (0x300000U) |
| #define BCH_CTRL_RSVD4_SHIFT (20U) |
| #define BCH_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK) |
| #define BCH_CTRL_DEBUGSYNDROME_MASK (0x400000U) |
| #define BCH_CTRL_DEBUGSYNDROME_SHIFT (22U) |
| #define BCH_CTRL_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK) |
| #define BCH_CTRL_RSVD5_MASK (0x3F800000U) |
| #define BCH_CTRL_RSVD5_SHIFT (23U) |
| #define BCH_CTRL_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK) |
| #define BCH_CTRL_CLKGATE_MASK (0x40000000U) |
| #define BCH_CTRL_CLKGATE_SHIFT (30U) |
| /*! CLKGATE |
| * 0b0..Allow BCH to operate normally. |
| * 0b1..Do not clock BCH gates in order to minimize power consumption. |
| */ |
| #define BCH_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK) |
| #define BCH_CTRL_SFTRST_MASK (0x80000000U) |
| #define BCH_CTRL_SFTRST_SHIFT (31U) |
| /*! SFTRST |
| * 0b0..Allow BCH to operate normally. |
| * 0b1..Hold BCH in reset. |
| */ |
| #define BCH_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL_SET - Hardware BCH ECC Accelerator Control Register */ |
| /*! @{ */ |
| #define BCH_CTRL_SET_COMPLETE_IRQ_MASK (0x1U) |
| #define BCH_CTRL_SET_COMPLETE_IRQ_SHIFT (0U) |
| #define BCH_CTRL_SET_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_MASK) |
| #define BCH_CTRL_SET_RSVD0_MASK (0x2U) |
| #define BCH_CTRL_SET_RSVD0_SHIFT (1U) |
| #define BCH_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD0_SHIFT)) & BCH_CTRL_SET_RSVD0_MASK) |
| #define BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK (0x4U) |
| #define BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT (2U) |
| #define BCH_CTRL_SET_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK) |
| #define BCH_CTRL_SET_BM_ERROR_IRQ_MASK (0x8U) |
| #define BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT (3U) |
| #define BCH_CTRL_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_SET_BM_ERROR_IRQ_MASK) |
| #define BCH_CTRL_SET_RSVD1_MASK (0xF0U) |
| #define BCH_CTRL_SET_RSVD1_SHIFT (4U) |
| #define BCH_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD1_SHIFT)) & BCH_CTRL_SET_RSVD1_MASK) |
| #define BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK (0x100U) |
| #define BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT (8U) |
| #define BCH_CTRL_SET_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK) |
| #define BCH_CTRL_SET_RSVD2_MASK (0x200U) |
| #define BCH_CTRL_SET_RSVD2_SHIFT (9U) |
| #define BCH_CTRL_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD2_SHIFT)) & BCH_CTRL_SET_RSVD2_MASK) |
| #define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK (0x400U) |
| #define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT (10U) |
| #define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK) |
| #define BCH_CTRL_SET_RSVD3_MASK (0xF800U) |
| #define BCH_CTRL_SET_RSVD3_SHIFT (11U) |
| #define BCH_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD3_SHIFT)) & BCH_CTRL_SET_RSVD3_MASK) |
| #define BCH_CTRL_SET_M2M_ENABLE_MASK (0x10000U) |
| #define BCH_CTRL_SET_M2M_ENABLE_SHIFT (16U) |
| #define BCH_CTRL_SET_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENABLE_SHIFT)) & BCH_CTRL_SET_M2M_ENABLE_MASK) |
| #define BCH_CTRL_SET_M2M_ENCODE_MASK (0x20000U) |
| #define BCH_CTRL_SET_M2M_ENCODE_SHIFT (17U) |
| #define BCH_CTRL_SET_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENCODE_SHIFT)) & BCH_CTRL_SET_M2M_ENCODE_MASK) |
| #define BCH_CTRL_SET_M2M_LAYOUT_MASK (0xC0000U) |
| #define BCH_CTRL_SET_M2M_LAYOUT_SHIFT (18U) |
| #define BCH_CTRL_SET_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_LAYOUT_SHIFT)) & BCH_CTRL_SET_M2M_LAYOUT_MASK) |
| #define BCH_CTRL_SET_RSVD4_MASK (0x300000U) |
| #define BCH_CTRL_SET_RSVD4_SHIFT (20U) |
| #define BCH_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD4_SHIFT)) & BCH_CTRL_SET_RSVD4_MASK) |
| #define BCH_CTRL_SET_DEBUGSYNDROME_MASK (0x400000U) |
| #define BCH_CTRL_SET_DEBUGSYNDROME_SHIFT (22U) |
| #define BCH_CTRL_SET_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_SET_DEBUGSYNDROME_MASK) |
| #define BCH_CTRL_SET_RSVD5_MASK (0x3F800000U) |
| #define BCH_CTRL_SET_RSVD5_SHIFT (23U) |
| #define BCH_CTRL_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD5_SHIFT)) & BCH_CTRL_SET_RSVD5_MASK) |
| #define BCH_CTRL_SET_CLKGATE_MASK (0x40000000U) |
| #define BCH_CTRL_SET_CLKGATE_SHIFT (30U) |
| /*! CLKGATE |
| * 0b0..Allow BCH to operate normally. |
| * 0b1..Do not clock BCH gates in order to minimize power consumption. |
| */ |
| #define BCH_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_CLKGATE_SHIFT)) & BCH_CTRL_SET_CLKGATE_MASK) |
| #define BCH_CTRL_SET_SFTRST_MASK (0x80000000U) |
| #define BCH_CTRL_SET_SFTRST_SHIFT (31U) |
| /*! SFTRST |
| * 0b0..Allow BCH to operate normally. |
| * 0b1..Hold BCH in reset. |
| */ |
| #define BCH_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_SFTRST_SHIFT)) & BCH_CTRL_SET_SFTRST_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL_CLR - Hardware BCH ECC Accelerator Control Register */ |
| /*! @{ */ |
| #define BCH_CTRL_CLR_COMPLETE_IRQ_MASK (0x1U) |
| #define BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT (0U) |
| #define BCH_CTRL_CLR_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_MASK) |
| #define BCH_CTRL_CLR_RSVD0_MASK (0x2U) |
| #define BCH_CTRL_CLR_RSVD0_SHIFT (1U) |
| #define BCH_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD0_SHIFT)) & BCH_CTRL_CLR_RSVD0_MASK) |
| #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK (0x4U) |
| #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT (2U) |
| #define BCH_CTRL_CLR_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK) |
| #define BCH_CTRL_CLR_BM_ERROR_IRQ_MASK (0x8U) |
| #define BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT (3U) |
| #define BCH_CTRL_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_CLR_BM_ERROR_IRQ_MASK) |
| #define BCH_CTRL_CLR_RSVD1_MASK (0xF0U) |
| #define BCH_CTRL_CLR_RSVD1_SHIFT (4U) |
| #define BCH_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD1_SHIFT)) & BCH_CTRL_CLR_RSVD1_MASK) |
| #define BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK (0x100U) |
| #define BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT (8U) |
| #define BCH_CTRL_CLR_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK) |
| #define BCH_CTRL_CLR_RSVD2_MASK (0x200U) |
| #define BCH_CTRL_CLR_RSVD2_SHIFT (9U) |
| #define BCH_CTRL_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD2_SHIFT)) & BCH_CTRL_CLR_RSVD2_MASK) |
| #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK (0x400U) |
| #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT (10U) |
| #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK) |
| #define BCH_CTRL_CLR_RSVD3_MASK (0xF800U) |
| #define BCH_CTRL_CLR_RSVD3_SHIFT (11U) |
| #define BCH_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD3_SHIFT)) & BCH_CTRL_CLR_RSVD3_MASK) |
| #define BCH_CTRL_CLR_M2M_ENABLE_MASK (0x10000U) |
| #define BCH_CTRL_CLR_M2M_ENABLE_SHIFT (16U) |
| #define BCH_CTRL_CLR_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENABLE_SHIFT)) & BCH_CTRL_CLR_M2M_ENABLE_MASK) |
| #define BCH_CTRL_CLR_M2M_ENCODE_MASK (0x20000U) |
| #define BCH_CTRL_CLR_M2M_ENCODE_SHIFT (17U) |
| #define BCH_CTRL_CLR_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENCODE_SHIFT)) & BCH_CTRL_CLR_M2M_ENCODE_MASK) |
| #define BCH_CTRL_CLR_M2M_LAYOUT_MASK (0xC0000U) |
| #define BCH_CTRL_CLR_M2M_LAYOUT_SHIFT (18U) |
| #define BCH_CTRL_CLR_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_LAYOUT_SHIFT)) & BCH_CTRL_CLR_M2M_LAYOUT_MASK) |
| #define BCH_CTRL_CLR_RSVD4_MASK (0x300000U) |
| #define BCH_CTRL_CLR_RSVD4_SHIFT (20U) |
| #define BCH_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD4_SHIFT)) & BCH_CTRL_CLR_RSVD4_MASK) |
| #define BCH_CTRL_CLR_DEBUGSYNDROME_MASK (0x400000U) |
| #define BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT (22U) |
| #define BCH_CTRL_CLR_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_CLR_DEBUGSYNDROME_MASK) |
| #define BCH_CTRL_CLR_RSVD5_MASK (0x3F800000U) |
| #define BCH_CTRL_CLR_RSVD5_SHIFT (23U) |
| #define BCH_CTRL_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD5_SHIFT)) & BCH_CTRL_CLR_RSVD5_MASK) |
| #define BCH_CTRL_CLR_CLKGATE_MASK (0x40000000U) |
| #define BCH_CTRL_CLR_CLKGATE_SHIFT (30U) |
| /*! CLKGATE |
| * 0b0..Allow BCH to operate normally. |
| * 0b1..Do not clock BCH gates in order to minimize power consumption. |
| */ |
| #define BCH_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_CLKGATE_SHIFT)) & BCH_CTRL_CLR_CLKGATE_MASK) |
| #define BCH_CTRL_CLR_SFTRST_MASK (0x80000000U) |
| #define BCH_CTRL_CLR_SFTRST_SHIFT (31U) |
| /*! SFTRST |
| * 0b0..Allow BCH to operate normally. |
| * 0b1..Hold BCH in reset. |
| */ |
| #define BCH_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_SFTRST_SHIFT)) & BCH_CTRL_CLR_SFTRST_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL_TOG - Hardware BCH ECC Accelerator Control Register */ |
| /*! @{ */ |
| #define BCH_CTRL_TOG_COMPLETE_IRQ_MASK (0x1U) |
| #define BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT (0U) |
| #define BCH_CTRL_TOG_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_MASK) |
| #define BCH_CTRL_TOG_RSVD0_MASK (0x2U) |
| #define BCH_CTRL_TOG_RSVD0_SHIFT (1U) |
| #define BCH_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD0_SHIFT)) & BCH_CTRL_TOG_RSVD0_MASK) |
| #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK (0x4U) |
| #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT (2U) |
| #define BCH_CTRL_TOG_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK) |
| #define BCH_CTRL_TOG_BM_ERROR_IRQ_MASK (0x8U) |
| #define BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT (3U) |
| #define BCH_CTRL_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_TOG_BM_ERROR_IRQ_MASK) |
| #define BCH_CTRL_TOG_RSVD1_MASK (0xF0U) |
| #define BCH_CTRL_TOG_RSVD1_SHIFT (4U) |
| #define BCH_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD1_SHIFT)) & BCH_CTRL_TOG_RSVD1_MASK) |
| #define BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK (0x100U) |
| #define BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT (8U) |
| #define BCH_CTRL_TOG_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK) |
| #define BCH_CTRL_TOG_RSVD2_MASK (0x200U) |
| #define BCH_CTRL_TOG_RSVD2_SHIFT (9U) |
| #define BCH_CTRL_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD2_SHIFT)) & BCH_CTRL_TOG_RSVD2_MASK) |
| #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK (0x400U) |
| #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT (10U) |
| #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK) |
| #define BCH_CTRL_TOG_RSVD3_MASK (0xF800U) |
| #define BCH_CTRL_TOG_RSVD3_SHIFT (11U) |
| #define BCH_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD3_SHIFT)) & BCH_CTRL_TOG_RSVD3_MASK) |
| #define BCH_CTRL_TOG_M2M_ENABLE_MASK (0x10000U) |
| #define BCH_CTRL_TOG_M2M_ENABLE_SHIFT (16U) |
| #define BCH_CTRL_TOG_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENABLE_SHIFT)) & BCH_CTRL_TOG_M2M_ENABLE_MASK) |
| #define BCH_CTRL_TOG_M2M_ENCODE_MASK (0x20000U) |
| #define BCH_CTRL_TOG_M2M_ENCODE_SHIFT (17U) |
| #define BCH_CTRL_TOG_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENCODE_SHIFT)) & BCH_CTRL_TOG_M2M_ENCODE_MASK) |
| #define BCH_CTRL_TOG_M2M_LAYOUT_MASK (0xC0000U) |
| #define BCH_CTRL_TOG_M2M_LAYOUT_SHIFT (18U) |
| #define BCH_CTRL_TOG_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_LAYOUT_SHIFT)) & BCH_CTRL_TOG_M2M_LAYOUT_MASK) |
| #define BCH_CTRL_TOG_RSVD4_MASK (0x300000U) |
| #define BCH_CTRL_TOG_RSVD4_SHIFT (20U) |
| #define BCH_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD4_SHIFT)) & BCH_CTRL_TOG_RSVD4_MASK) |
| #define BCH_CTRL_TOG_DEBUGSYNDROME_MASK (0x400000U) |
| #define BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT (22U) |
| #define BCH_CTRL_TOG_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_TOG_DEBUGSYNDROME_MASK) |
| #define BCH_CTRL_TOG_RSVD5_MASK (0x3F800000U) |
| #define BCH_CTRL_TOG_RSVD5_SHIFT (23U) |
| #define BCH_CTRL_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD5_SHIFT)) & BCH_CTRL_TOG_RSVD5_MASK) |
| #define BCH_CTRL_TOG_CLKGATE_MASK (0x40000000U) |
| #define BCH_CTRL_TOG_CLKGATE_SHIFT (30U) |
| /*! CLKGATE |
| * 0b0..Allow BCH to operate normally. |
| * 0b1..Do not clock BCH gates in order to minimize power consumption. |
| */ |
| #define BCH_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_CLKGATE_SHIFT)) & BCH_CTRL_TOG_CLKGATE_MASK) |
| #define BCH_CTRL_TOG_SFTRST_MASK (0x80000000U) |
| #define BCH_CTRL_TOG_SFTRST_SHIFT (31U) |
| /*! SFTRST |
| * 0b0..Allow BCH to operate normally. |
| * 0b1..Hold BCH in reset. |
| */ |
| #define BCH_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_SFTRST_SHIFT)) & BCH_CTRL_TOG_SFTRST_MASK) |
| /*! @} */ |
| |
| /*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */ |
| /*! @{ */ |
| #define BCH_STATUS0_RSVD0_MASK (0x3U) |
| #define BCH_STATUS0_RSVD0_SHIFT (0U) |
| #define BCH_STATUS0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK) |
| #define BCH_STATUS0_UNCORRECTABLE_MASK (0x4U) |
| #define BCH_STATUS0_UNCORRECTABLE_SHIFT (2U) |
| #define BCH_STATUS0_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK) |
| #define BCH_STATUS0_CORRECTED_MASK (0x8U) |
| #define BCH_STATUS0_CORRECTED_SHIFT (3U) |
| #define BCH_STATUS0_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK) |
| #define BCH_STATUS0_ALLONES_MASK (0x10U) |
| #define BCH_STATUS0_ALLONES_SHIFT (4U) |
| #define BCH_STATUS0_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK) |
| #define BCH_STATUS0_RSVD1_MASK (0xE0U) |
| #define BCH_STATUS0_RSVD1_SHIFT (5U) |
| #define BCH_STATUS0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK) |
| #define BCH_STATUS0_STATUS_BLK0_MASK (0xFF00U) |
| #define BCH_STATUS0_STATUS_BLK0_SHIFT (8U) |
| /*! STATUS_BLK0 |
| * 0b00000000..No errors found on block. |
| * 0b00000001..One error found on block. |
| * 0b00000010..One errors found on block. |
| * 0b00000011..One errors found on block. |
| * 0b00000100..One errors found on block. |
| * 0b11111110..Block exhibited uncorrectable errors. |
| * 0b11111111..Page is erased. |
| */ |
| #define BCH_STATUS0_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK) |
| #define BCH_STATUS0_COMPLETED_CE_MASK (0xF0000U) |
| #define BCH_STATUS0_COMPLETED_CE_SHIFT (16U) |
| #define BCH_STATUS0_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK) |
| #define BCH_STATUS0_HANDLE_MASK (0xFFF00000U) |
| #define BCH_STATUS0_HANDLE_SHIFT (20U) |
| #define BCH_STATUS0_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK) |
| /*! @} */ |
| |
| /*! @name STATUS0_SET - Hardware ECC Accelerator Status Register 0 */ |
| /*! @{ */ |
| #define BCH_STATUS0_SET_RSVD0_MASK (0x3U) |
| #define BCH_STATUS0_SET_RSVD0_SHIFT (0U) |
| #define BCH_STATUS0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_RSVD0_SHIFT)) & BCH_STATUS0_SET_RSVD0_MASK) |
| #define BCH_STATUS0_SET_UNCORRECTABLE_MASK (0x4U) |
| #define BCH_STATUS0_SET_UNCORRECTABLE_SHIFT (2U) |
| #define BCH_STATUS0_SET_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_SET_UNCORRECTABLE_MASK) |
| #define BCH_STATUS0_SET_CORRECTED_MASK (0x8U) |
| #define BCH_STATUS0_SET_CORRECTED_SHIFT (3U) |
| #define BCH_STATUS0_SET_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_CORRECTED_SHIFT)) & BCH_STATUS0_SET_CORRECTED_MASK) |
| #define BCH_STATUS0_SET_ALLONES_MASK (0x10U) |
| #define BCH_STATUS0_SET_ALLONES_SHIFT (4U) |
| #define BCH_STATUS0_SET_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_ALLONES_SHIFT)) & BCH_STATUS0_SET_ALLONES_MASK) |
| #define BCH_STATUS0_SET_RSVD1_MASK (0xE0U) |
| #define BCH_STATUS0_SET_RSVD1_SHIFT (5U) |
| #define BCH_STATUS0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_RSVD1_SHIFT)) & BCH_STATUS0_SET_RSVD1_MASK) |
| #define BCH_STATUS0_SET_STATUS_BLK0_MASK (0xFF00U) |
| #define BCH_STATUS0_SET_STATUS_BLK0_SHIFT (8U) |
| /*! STATUS_BLK0 |
| * 0b00000000..No errors found on block. |
| * 0b00000001..One error found on block. |
| * 0b00000010..One errors found on block. |
| * 0b00000011..One errors found on block. |
| * 0b00000100..One errors found on block. |
| * 0b11111110..Block exhibited uncorrectable errors. |
| * 0b11111111..Page is erased. |
| */ |
| #define BCH_STATUS0_SET_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_STATUS_BLK0_SHIFT)) & BCH_STATUS0_SET_STATUS_BLK0_MASK) |
| #define BCH_STATUS0_SET_COMPLETED_CE_MASK (0xF0000U) |
| #define BCH_STATUS0_SET_COMPLETED_CE_SHIFT (16U) |
| #define BCH_STATUS0_SET_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_COMPLETED_CE_SHIFT)) & BCH_STATUS0_SET_COMPLETED_CE_MASK) |
| #define BCH_STATUS0_SET_HANDLE_MASK (0xFFF00000U) |
| #define BCH_STATUS0_SET_HANDLE_SHIFT (20U) |
| #define BCH_STATUS0_SET_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_HANDLE_SHIFT)) & BCH_STATUS0_SET_HANDLE_MASK) |
| /*! @} */ |
| |
| /*! @name STATUS0_CLR - Hardware ECC Accelerator Status Register 0 */ |
| /*! @{ */ |
| #define BCH_STATUS0_CLR_RSVD0_MASK (0x3U) |
| #define BCH_STATUS0_CLR_RSVD0_SHIFT (0U) |
| #define BCH_STATUS0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_RSVD0_SHIFT)) & BCH_STATUS0_CLR_RSVD0_MASK) |
| #define BCH_STATUS0_CLR_UNCORRECTABLE_MASK (0x4U) |
| #define BCH_STATUS0_CLR_UNCORRECTABLE_SHIFT (2U) |
| #define BCH_STATUS0_CLR_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_CLR_UNCORRECTABLE_MASK) |
| #define BCH_STATUS0_CLR_CORRECTED_MASK (0x8U) |
| #define BCH_STATUS0_CLR_CORRECTED_SHIFT (3U) |
| #define BCH_STATUS0_CLR_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_CORRECTED_SHIFT)) & BCH_STATUS0_CLR_CORRECTED_MASK) |
| #define BCH_STATUS0_CLR_ALLONES_MASK (0x10U) |
| #define BCH_STATUS0_CLR_ALLONES_SHIFT (4U) |
| #define BCH_STATUS0_CLR_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_ALLONES_SHIFT)) & BCH_STATUS0_CLR_ALLONES_MASK) |
| #define BCH_STATUS0_CLR_RSVD1_MASK (0xE0U) |
| #define BCH_STATUS0_CLR_RSVD1_SHIFT (5U) |
| #define BCH_STATUS0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_RSVD1_SHIFT)) & BCH_STATUS0_CLR_RSVD1_MASK) |
| #define BCH_STATUS0_CLR_STATUS_BLK0_MASK (0xFF00U) |
| #define BCH_STATUS0_CLR_STATUS_BLK0_SHIFT (8U) |
| /*! STATUS_BLK0 |
| * 0b00000000..No errors found on block. |
| * 0b00000001..One error found on block. |
| * 0b00000010..One errors found on block. |
| * 0b00000011..One errors found on block. |
| * 0b00000100..One errors found on block. |
| * 0b11111110..Block exhibited uncorrectable errors. |
| * 0b11111111..Page is erased. |
| */ |
| #define BCH_STATUS0_CLR_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_STATUS_BLK0_SHIFT)) & BCH_STATUS0_CLR_STATUS_BLK0_MASK) |
| #define BCH_STATUS0_CLR_COMPLETED_CE_MASK (0xF0000U) |
| #define BCH_STATUS0_CLR_COMPLETED_CE_SHIFT (16U) |
| #define BCH_STATUS0_CLR_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_COMPLETED_CE_SHIFT)) & BCH_STATUS0_CLR_COMPLETED_CE_MASK) |
| #define BCH_STATUS0_CLR_HANDLE_MASK (0xFFF00000U) |
| #define BCH_STATUS0_CLR_HANDLE_SHIFT (20U) |
| #define BCH_STATUS0_CLR_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_HANDLE_SHIFT)) & BCH_STATUS0_CLR_HANDLE_MASK) |
| /*! @} */ |
| |
| /*! @name STATUS0_TOG - Hardware ECC Accelerator Status Register 0 */ |
| /*! @{ */ |
| #define BCH_STATUS0_TOG_RSVD0_MASK (0x3U) |
| #define BCH_STATUS0_TOG_RSVD0_SHIFT (0U) |
| #define BCH_STATUS0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_RSVD0_SHIFT)) & BCH_STATUS0_TOG_RSVD0_MASK) |
| #define BCH_STATUS0_TOG_UNCORRECTABLE_MASK (0x4U) |
| #define BCH_STATUS0_TOG_UNCORRECTABLE_SHIFT (2U) |
| #define BCH_STATUS0_TOG_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_TOG_UNCORRECTABLE_MASK) |
| #define BCH_STATUS0_TOG_CORRECTED_MASK (0x8U) |
| #define BCH_STATUS0_TOG_CORRECTED_SHIFT (3U) |
| #define BCH_STATUS0_TOG_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_CORRECTED_SHIFT)) & BCH_STATUS0_TOG_CORRECTED_MASK) |
| #define BCH_STATUS0_TOG_ALLONES_MASK (0x10U) |
| #define BCH_STATUS0_TOG_ALLONES_SHIFT (4U) |
| #define BCH_STATUS0_TOG_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_ALLONES_SHIFT)) & BCH_STATUS0_TOG_ALLONES_MASK) |
| #define BCH_STATUS0_TOG_RSVD1_MASK (0xE0U) |
| #define BCH_STATUS0_TOG_RSVD1_SHIFT (5U) |
| #define BCH_STATUS0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_RSVD1_SHIFT)) & BCH_STATUS0_TOG_RSVD1_MASK) |
| #define BCH_STATUS0_TOG_STATUS_BLK0_MASK (0xFF00U) |
| #define BCH_STATUS0_TOG_STATUS_BLK0_SHIFT (8U) |
| /*! STATUS_BLK0 |
| * 0b00000000..No errors found on block. |
| * 0b00000001..One error found on block. |
| * 0b00000010..One errors found on block. |
| * 0b00000011..One errors found on block. |
| * 0b00000100..One errors found on block. |
| * 0b11111110..Block exhibited uncorrectable errors. |
| * 0b11111111..Page is erased. |
| */ |
| #define BCH_STATUS0_TOG_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_STATUS_BLK0_SHIFT)) & BCH_STATUS0_TOG_STATUS_BLK0_MASK) |
| #define BCH_STATUS0_TOG_COMPLETED_CE_MASK (0xF0000U) |
| #define BCH_STATUS0_TOG_COMPLETED_CE_SHIFT (16U) |
| #define BCH_STATUS0_TOG_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_COMPLETED_CE_SHIFT)) & BCH_STATUS0_TOG_COMPLETED_CE_MASK) |
| #define BCH_STATUS0_TOG_HANDLE_MASK (0xFFF00000U) |
| #define BCH_STATUS0_TOG_HANDLE_SHIFT (20U) |
| #define BCH_STATUS0_TOG_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_HANDLE_SHIFT)) & BCH_STATUS0_TOG_HANDLE_MASK) |
| /*! @} */ |
| |
| /*! @name MODE - Hardware ECC Accelerator Mode Register */ |
| /*! @{ */ |
| #define BCH_MODE_ERASE_THRESHOLD_MASK (0xFFU) |
| #define BCH_MODE_ERASE_THRESHOLD_SHIFT (0U) |
| #define BCH_MODE_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK) |
| #define BCH_MODE_RSVD_MASK (0xFFFFFF00U) |
| #define BCH_MODE_RSVD_SHIFT (8U) |
| #define BCH_MODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK) |
| /*! @} */ |
| |
| /*! @name MODE_SET - Hardware ECC Accelerator Mode Register */ |
| /*! @{ */ |
| #define BCH_MODE_SET_ERASE_THRESHOLD_MASK (0xFFU) |
| #define BCH_MODE_SET_ERASE_THRESHOLD_SHIFT (0U) |
| #define BCH_MODE_SET_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_SET_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_SET_ERASE_THRESHOLD_MASK) |
| #define BCH_MODE_SET_RSVD_MASK (0xFFFFFF00U) |
| #define BCH_MODE_SET_RSVD_SHIFT (8U) |
| #define BCH_MODE_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_SET_RSVD_SHIFT)) & BCH_MODE_SET_RSVD_MASK) |
| /*! @} */ |
| |
| /*! @name MODE_CLR - Hardware ECC Accelerator Mode Register */ |
| /*! @{ */ |
| #define BCH_MODE_CLR_ERASE_THRESHOLD_MASK (0xFFU) |
| #define BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT (0U) |
| #define BCH_MODE_CLR_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_CLR_ERASE_THRESHOLD_MASK) |
| #define BCH_MODE_CLR_RSVD_MASK (0xFFFFFF00U) |
| #define BCH_MODE_CLR_RSVD_SHIFT (8U) |
| #define BCH_MODE_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_CLR_RSVD_SHIFT)) & BCH_MODE_CLR_RSVD_MASK) |
| /*! @} */ |
| |
| /*! @name MODE_TOG - Hardware ECC Accelerator Mode Register */ |
| /*! @{ */ |
| #define BCH_MODE_TOG_ERASE_THRESHOLD_MASK (0xFFU) |
| #define BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT (0U) |
| #define BCH_MODE_TOG_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_TOG_ERASE_THRESHOLD_MASK) |
| #define BCH_MODE_TOG_RSVD_MASK (0xFFFFFF00U) |
| #define BCH_MODE_TOG_RSVD_SHIFT (8U) |
| #define BCH_MODE_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_TOG_RSVD_SHIFT)) & BCH_MODE_TOG_RSVD_MASK) |
| /*! @} */ |
| |
| /*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */ |
| /*! @{ */ |
| #define BCH_ENCODEPTR_ADDR_MASK (0xFFFFFFFFU) |
| #define BCH_ENCODEPTR_ADDR_SHIFT (0U) |
| #define BCH_ENCODEPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name ENCODEPTR_SET - Hardware BCH ECC Loopback Encode Buffer Register */ |
| /*! @{ */ |
| #define BCH_ENCODEPTR_SET_ADDR_MASK (0xFFFFFFFFU) |
| #define BCH_ENCODEPTR_SET_ADDR_SHIFT (0U) |
| #define BCH_ENCODEPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_SET_ADDR_SHIFT)) & BCH_ENCODEPTR_SET_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name ENCODEPTR_CLR - Hardware BCH ECC Loopback Encode Buffer Register */ |
| /*! @{ */ |
| #define BCH_ENCODEPTR_CLR_ADDR_MASK (0xFFFFFFFFU) |
| #define BCH_ENCODEPTR_CLR_ADDR_SHIFT (0U) |
| #define BCH_ENCODEPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_CLR_ADDR_SHIFT)) & BCH_ENCODEPTR_CLR_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name ENCODEPTR_TOG - Hardware BCH ECC Loopback Encode Buffer Register */ |
| /*! @{ */ |
| #define BCH_ENCODEPTR_TOG_ADDR_MASK (0xFFFFFFFFU) |
| #define BCH_ENCODEPTR_TOG_ADDR_SHIFT (0U) |
| #define BCH_ENCODEPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_TOG_ADDR_SHIFT)) & BCH_ENCODEPTR_TOG_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */ |
| /*! @{ */ |
| #define BCH_DATAPTR_ADDR_MASK (0xFFFFFFFFU) |
| #define BCH_DATAPTR_ADDR_SHIFT (0U) |
| #define BCH_DATAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name DATAPTR_SET - Hardware BCH ECC Loopback Data Buffer Register */ |
| /*! @{ */ |
| #define BCH_DATAPTR_SET_ADDR_MASK (0xFFFFFFFFU) |
| #define BCH_DATAPTR_SET_ADDR_SHIFT (0U) |
| #define BCH_DATAPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_SET_ADDR_SHIFT)) & BCH_DATAPTR_SET_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name DATAPTR_CLR - Hardware BCH ECC Loopback Data Buffer Register */ |
| /*! @{ */ |
| #define BCH_DATAPTR_CLR_ADDR_MASK (0xFFFFFFFFU) |
| #define BCH_DATAPTR_CLR_ADDR_SHIFT (0U) |
| #define BCH_DATAPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_CLR_ADDR_SHIFT)) & BCH_DATAPTR_CLR_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name DATAPTR_TOG - Hardware BCH ECC Loopback Data Buffer Register */ |
| /*! @{ */ |
| #define BCH_DATAPTR_TOG_ADDR_MASK (0xFFFFFFFFU) |
| #define BCH_DATAPTR_TOG_ADDR_SHIFT (0U) |
| #define BCH_DATAPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_TOG_ADDR_SHIFT)) & BCH_DATAPTR_TOG_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */ |
| /*! @{ */ |
| #define BCH_METAPTR_ADDR_MASK (0xFFFFFFFFU) |
| #define BCH_METAPTR_ADDR_SHIFT (0U) |
| #define BCH_METAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name METAPTR_SET - Hardware BCH ECC Loopback Metadata Buffer Register */ |
| /*! @{ */ |
| #define BCH_METAPTR_SET_ADDR_MASK (0xFFFFFFFFU) |
| #define BCH_METAPTR_SET_ADDR_SHIFT (0U) |
| #define BCH_METAPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_SET_ADDR_SHIFT)) & BCH_METAPTR_SET_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name METAPTR_CLR - Hardware BCH ECC Loopback Metadata Buffer Register */ |
| /*! @{ */ |
| #define BCH_METAPTR_CLR_ADDR_MASK (0xFFFFFFFFU) |
| #define BCH_METAPTR_CLR_ADDR_SHIFT (0U) |
| #define BCH_METAPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_CLR_ADDR_SHIFT)) & BCH_METAPTR_CLR_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name METAPTR_TOG - Hardware BCH ECC Loopback Metadata Buffer Register */ |
| /*! @{ */ |
| #define BCH_METAPTR_TOG_ADDR_MASK (0xFFFFFFFFU) |
| #define BCH_METAPTR_TOG_ADDR_SHIFT (0U) |
| #define BCH_METAPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_TOG_ADDR_SHIFT)) & BCH_METAPTR_TOG_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */ |
| /*! @{ */ |
| #define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3U) |
| #define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT (0U) |
| #define BCH_LAYOUTSELECT_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0xCU) |
| #define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT (2U) |
| #define BCH_LAYOUTSELECT_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x30U) |
| #define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT (4U) |
| #define BCH_LAYOUTSELECT_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0xC0U) |
| #define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT (6U) |
| #define BCH_LAYOUTSELECT_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x300U) |
| #define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT (8U) |
| #define BCH_LAYOUTSELECT_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0xC00U) |
| #define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT (10U) |
| #define BCH_LAYOUTSELECT_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3000U) |
| #define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT (12U) |
| #define BCH_LAYOUTSELECT_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0xC000U) |
| #define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT (14U) |
| #define BCH_LAYOUTSELECT_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x30000U) |
| #define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT (16U) |
| #define BCH_LAYOUTSELECT_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0xC0000U) |
| #define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT (18U) |
| #define BCH_LAYOUTSELECT_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x300000U) |
| #define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT (20U) |
| #define BCH_LAYOUTSELECT_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0xC00000U) |
| #define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT (22U) |
| #define BCH_LAYOUTSELECT_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3000000U) |
| #define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT (24U) |
| #define BCH_LAYOUTSELECT_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0xC000000U) |
| #define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT (26U) |
| #define BCH_LAYOUTSELECT_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x30000000U) |
| #define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT (28U) |
| #define BCH_LAYOUTSELECT_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0xC0000000U) |
| #define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT (30U) |
| #define BCH_LAYOUTSELECT_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK) |
| /*! @} */ |
| |
| /*! @name LAYOUTSELECT_SET - Hardware ECC Accelerator Layout Select Register */ |
| /*! @{ */ |
| #define BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK (0x3U) |
| #define BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT (0U) |
| #define BCH_LAYOUTSELECT_SET_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK (0xCU) |
| #define BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT (2U) |
| #define BCH_LAYOUTSELECT_SET_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK (0x30U) |
| #define BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT (4U) |
| #define BCH_LAYOUTSELECT_SET_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK (0xC0U) |
| #define BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT (6U) |
| #define BCH_LAYOUTSELECT_SET_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK (0x300U) |
| #define BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT (8U) |
| #define BCH_LAYOUTSELECT_SET_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK (0xC00U) |
| #define BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT (10U) |
| #define BCH_LAYOUTSELECT_SET_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK (0x3000U) |
| #define BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT (12U) |
| #define BCH_LAYOUTSELECT_SET_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK (0xC000U) |
| #define BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT (14U) |
| #define BCH_LAYOUTSELECT_SET_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK (0x30000U) |
| #define BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT (16U) |
| #define BCH_LAYOUTSELECT_SET_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK (0xC0000U) |
| #define BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT (18U) |
| #define BCH_LAYOUTSELECT_SET_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK (0x300000U) |
| #define BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT (20U) |
| #define BCH_LAYOUTSELECT_SET_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK (0xC00000U) |
| #define BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT (22U) |
| #define BCH_LAYOUTSELECT_SET_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK (0x3000000U) |
| #define BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT (24U) |
| #define BCH_LAYOUTSELECT_SET_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK (0xC000000U) |
| #define BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT (26U) |
| #define BCH_LAYOUTSELECT_SET_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK (0x30000000U) |
| #define BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT (28U) |
| #define BCH_LAYOUTSELECT_SET_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK (0xC0000000U) |
| #define BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT (30U) |
| #define BCH_LAYOUTSELECT_SET_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK) |
| /*! @} */ |
| |
| /*! @name LAYOUTSELECT_CLR - Hardware ECC Accelerator Layout Select Register */ |
| /*! @{ */ |
| #define BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK (0x3U) |
| #define BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT (0U) |
| #define BCH_LAYOUTSELECT_CLR_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK (0xCU) |
| #define BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT (2U) |
| #define BCH_LAYOUTSELECT_CLR_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK (0x30U) |
| #define BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT (4U) |
| #define BCH_LAYOUTSELECT_CLR_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK (0xC0U) |
| #define BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT (6U) |
| #define BCH_LAYOUTSELECT_CLR_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK (0x300U) |
| #define BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT (8U) |
| #define BCH_LAYOUTSELECT_CLR_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK (0xC00U) |
| #define BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT (10U) |
| #define BCH_LAYOUTSELECT_CLR_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK (0x3000U) |
| #define BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT (12U) |
| #define BCH_LAYOUTSELECT_CLR_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK (0xC000U) |
| #define BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT (14U) |
| #define BCH_LAYOUTSELECT_CLR_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK (0x30000U) |
| #define BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT (16U) |
| #define BCH_LAYOUTSELECT_CLR_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK (0xC0000U) |
| #define BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT (18U) |
| #define BCH_LAYOUTSELECT_CLR_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK (0x300000U) |
| #define BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT (20U) |
| #define BCH_LAYOUTSELECT_CLR_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK (0xC00000U) |
| #define BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT (22U) |
| #define BCH_LAYOUTSELECT_CLR_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK (0x3000000U) |
| #define BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT (24U) |
| #define BCH_LAYOUTSELECT_CLR_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK (0xC000000U) |
| #define BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT (26U) |
| #define BCH_LAYOUTSELECT_CLR_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK (0x30000000U) |
| #define BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT (28U) |
| #define BCH_LAYOUTSELECT_CLR_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK (0xC0000000U) |
| #define BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT (30U) |
| #define BCH_LAYOUTSELECT_CLR_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK) |
| /*! @} */ |
| |
| /*! @name LAYOUTSELECT_TOG - Hardware ECC Accelerator Layout Select Register */ |
| /*! @{ */ |
| #define BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK (0x3U) |
| #define BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT (0U) |
| #define BCH_LAYOUTSELECT_TOG_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK (0xCU) |
| #define BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT (2U) |
| #define BCH_LAYOUTSELECT_TOG_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK (0x30U) |
| #define BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT (4U) |
| #define BCH_LAYOUTSELECT_TOG_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK (0xC0U) |
| #define BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT (6U) |
| #define BCH_LAYOUTSELECT_TOG_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK (0x300U) |
| #define BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT (8U) |
| #define BCH_LAYOUTSELECT_TOG_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK (0xC00U) |
| #define BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT (10U) |
| #define BCH_LAYOUTSELECT_TOG_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK (0x3000U) |
| #define BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT (12U) |
| #define BCH_LAYOUTSELECT_TOG_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK (0xC000U) |
| #define BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT (14U) |
| #define BCH_LAYOUTSELECT_TOG_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK (0x30000U) |
| #define BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT (16U) |
| #define BCH_LAYOUTSELECT_TOG_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK (0xC0000U) |
| #define BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT (18U) |
| #define BCH_LAYOUTSELECT_TOG_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK (0x300000U) |
| #define BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT (20U) |
| #define BCH_LAYOUTSELECT_TOG_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK (0xC00000U) |
| #define BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT (22U) |
| #define BCH_LAYOUTSELECT_TOG_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK (0x3000000U) |
| #define BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT (24U) |
| #define BCH_LAYOUTSELECT_TOG_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK (0xC000000U) |
| #define BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT (26U) |
| #define BCH_LAYOUTSELECT_TOG_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK (0x30000000U) |
| #define BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT (28U) |
| #define BCH_LAYOUTSELECT_TOG_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK (0xC0000000U) |
| #define BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT (30U) |
| #define BCH_LAYOUTSELECT_TOG_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */ |
| /*! @{ */ |
| #define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT (0U) |
| #define BCH_FLASH0LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH0LAYOUT0_ECC0_MASK (0xF800U) |
| #define BCH_FLASH0LAYOUT0_ECC0_SHIFT (11U) |
| /*! ECC0 |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH0LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK) |
| #define BCH_FLASH0LAYOUT0_META_SIZE_MASK (0xFF0000U) |
| #define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT (16U) |
| #define BCH_FLASH0LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT0_NBLOCKS_MASK (0xFF000000U) |
| #define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT (24U) |
| #define BCH_FLASH0LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH0LAYOUT0_SET - Hardware BCH ECC Flash 0 Layout 0 Register */ |
| /*! @{ */ |
| #define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) |
| #define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH0LAYOUT0_SET_ECC0_MASK (0xF800U) |
| #define BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT (11U) |
| /*! ECC0 |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH0LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_SET_ECC0_MASK) |
| #define BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) |
| #define BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT (16U) |
| #define BCH_FLASH0LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) |
| #define BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT (24U) |
| #define BCH_FLASH0LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH0LAYOUT0_CLR - Hardware BCH ECC Flash 0 Layout 0 Register */ |
| /*! @{ */ |
| #define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) |
| #define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH0LAYOUT0_CLR_ECC0_MASK (0xF800U) |
| #define BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT (11U) |
| /*! ECC0 |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH0LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_ECC0_MASK) |
| #define BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) |
| #define BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT (16U) |
| #define BCH_FLASH0LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) |
| #define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT (24U) |
| #define BCH_FLASH0LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH0LAYOUT0_TOG - Hardware BCH ECC Flash 0 Layout 0 Register */ |
| /*! @{ */ |
| #define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) |
| #define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH0LAYOUT0_TOG_ECC0_MASK (0xF800U) |
| #define BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT (11U) |
| /*! ECC0 |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH0LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_ECC0_MASK) |
| #define BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) |
| #define BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT (16U) |
| #define BCH_FLASH0LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) |
| #define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT (24U) |
| #define BCH_FLASH0LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */ |
| /*! @{ */ |
| #define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT (0U) |
| #define BCH_FLASH0LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH0LAYOUT1_ECCN_MASK (0xF800U) |
| #define BCH_FLASH0LAYOUT1_ECCN_SHIFT (11U) |
| /*! ECCN |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH0LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK) |
| #define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) |
| #define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT (16U) |
| #define BCH_FLASH0LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH0LAYOUT1_SET - Hardware BCH ECC Flash 0 Layout 1 Register */ |
| /*! @{ */ |
| #define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) |
| #define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH0LAYOUT1_SET_ECCN_MASK (0xF800U) |
| #define BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT (11U) |
| /*! ECCN |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH0LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_SET_ECCN_MASK) |
| #define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) |
| #define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) |
| #define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH0LAYOUT1_CLR - Hardware BCH ECC Flash 0 Layout 1 Register */ |
| /*! @{ */ |
| #define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) |
| #define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH0LAYOUT1_CLR_ECCN_MASK (0xF800U) |
| #define BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT (11U) |
| /*! ECCN |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH0LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_ECCN_MASK) |
| #define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) |
| #define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) |
| #define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH0LAYOUT1_TOG - Hardware BCH ECC Flash 0 Layout 1 Register */ |
| /*! @{ */ |
| #define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) |
| #define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH0LAYOUT1_TOG_ECCN_MASK (0xF800U) |
| #define BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT (11U) |
| /*! ECCN |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH0LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_ECCN_MASK) |
| #define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) |
| #define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) |
| #define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */ |
| /*! @{ */ |
| #define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT (0U) |
| #define BCH_FLASH1LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH1LAYOUT0_ECC0_MASK (0xF800U) |
| #define BCH_FLASH1LAYOUT0_ECC0_SHIFT (11U) |
| /*! ECC0 |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH1LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK) |
| #define BCH_FLASH1LAYOUT0_META_SIZE_MASK (0xFF0000U) |
| #define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT (16U) |
| #define BCH_FLASH1LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT0_NBLOCKS_MASK (0xFF000000U) |
| #define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT (24U) |
| #define BCH_FLASH1LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH1LAYOUT0_SET - Hardware BCH ECC Flash 1 Layout 0 Register */ |
| /*! @{ */ |
| #define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) |
| #define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH1LAYOUT0_SET_ECC0_MASK (0xF800U) |
| #define BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT (11U) |
| /*! ECC0 |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH1LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_SET_ECC0_MASK) |
| #define BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) |
| #define BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT (16U) |
| #define BCH_FLASH1LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) |
| #define BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT (24U) |
| #define BCH_FLASH1LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH1LAYOUT0_CLR - Hardware BCH ECC Flash 1 Layout 0 Register */ |
| /*! @{ */ |
| #define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) |
| #define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH1LAYOUT0_CLR_ECC0_MASK (0xF800U) |
| #define BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT (11U) |
| /*! ECC0 |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH1LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_ECC0_MASK) |
| #define BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) |
| #define BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT (16U) |
| #define BCH_FLASH1LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) |
| #define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT (24U) |
| #define BCH_FLASH1LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH1LAYOUT0_TOG - Hardware BCH ECC Flash 1 Layout 0 Register */ |
| /*! @{ */ |
| #define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) |
| #define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH1LAYOUT0_TOG_ECC0_MASK (0xF800U) |
| #define BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT (11U) |
| /*! ECC0 |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH1LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_ECC0_MASK) |
| #define BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) |
| #define BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT (16U) |
| #define BCH_FLASH1LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) |
| #define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT (24U) |
| #define BCH_FLASH1LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */ |
| /*! @{ */ |
| #define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT (0U) |
| #define BCH_FLASH1LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH1LAYOUT1_ECCN_MASK (0xF800U) |
| #define BCH_FLASH1LAYOUT1_ECCN_SHIFT (11U) |
| /*! ECCN |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH1LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK) |
| #define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) |
| #define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT (16U) |
| #define BCH_FLASH1LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH1LAYOUT1_SET - Hardware BCH ECC Flash 1 Layout 1 Register */ |
| /*! @{ */ |
| #define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) |
| #define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH1LAYOUT1_SET_ECCN_MASK (0xF800U) |
| #define BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT (11U) |
| /*! ECCN |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH1LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_SET_ECCN_MASK) |
| #define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) |
| #define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) |
| #define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH1LAYOUT1_CLR - Hardware BCH ECC Flash 1 Layout 1 Register */ |
| /*! @{ */ |
| #define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) |
| #define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH1LAYOUT1_CLR_ECCN_MASK (0xF800U) |
| #define BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT (11U) |
| /*! ECCN |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH1LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_ECCN_MASK) |
| #define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) |
| #define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) |
| #define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH1LAYOUT1_TOG - Hardware BCH ECC Flash 1 Layout 1 Register */ |
| /*! @{ */ |
| #define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) |
| #define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH1LAYOUT1_TOG_ECCN_MASK (0xF800U) |
| #define BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT (11U) |
| /*! ECCN |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH1LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_ECCN_MASK) |
| #define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) |
| #define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) |
| #define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */ |
| /*! @{ */ |
| #define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT (0U) |
| #define BCH_FLASH2LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH2LAYOUT0_ECC0_MASK (0xF800U) |
| #define BCH_FLASH2LAYOUT0_ECC0_SHIFT (11U) |
| /*! ECC0 |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH2LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK) |
| #define BCH_FLASH2LAYOUT0_META_SIZE_MASK (0xFF0000U) |
| #define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT (16U) |
| #define BCH_FLASH2LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT0_NBLOCKS_MASK (0xFF000000U) |
| #define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT (24U) |
| #define BCH_FLASH2LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH2LAYOUT0_SET - Hardware BCH ECC Flash 2 Layout 0 Register */ |
| /*! @{ */ |
| #define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) |
| #define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH2LAYOUT0_SET_ECC0_MASK (0xF800U) |
| #define BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT (11U) |
| /*! ECC0 |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH2LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_SET_ECC0_MASK) |
| #define BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) |
| #define BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT (16U) |
| #define BCH_FLASH2LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) |
| #define BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT (24U) |
| #define BCH_FLASH2LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH2LAYOUT0_CLR - Hardware BCH ECC Flash 2 Layout 0 Register */ |
| /*! @{ */ |
| #define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) |
| #define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH2LAYOUT0_CLR_ECC0_MASK (0xF800U) |
| #define BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT (11U) |
| /*! ECC0 |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH2LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_ECC0_MASK) |
| #define BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) |
| #define BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT (16U) |
| #define BCH_FLASH2LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) |
| #define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT (24U) |
| #define BCH_FLASH2LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH2LAYOUT0_TOG - Hardware BCH ECC Flash 2 Layout 0 Register */ |
| /*! @{ */ |
| #define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) |
| #define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH2LAYOUT0_TOG_ECC0_MASK (0xF800U) |
| #define BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT (11U) |
| /*! ECC0 |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH2LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_ECC0_MASK) |
| #define BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) |
| #define BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT (16U) |
| #define BCH_FLASH2LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) |
| #define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT (24U) |
| #define BCH_FLASH2LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */ |
| /*! @{ */ |
| #define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT (0U) |
| #define BCH_FLASH2LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH2LAYOUT1_ECCN_MASK (0xF800U) |
| #define BCH_FLASH2LAYOUT1_ECCN_SHIFT (11U) |
| /*! ECCN |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH2LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK) |
| #define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) |
| #define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT (16U) |
| #define BCH_FLASH2LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH2LAYOUT1_SET - Hardware BCH ECC Flash 2 Layout 1 Register */ |
| /*! @{ */ |
| #define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) |
| #define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH2LAYOUT1_SET_ECCN_MASK (0xF800U) |
| #define BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT (11U) |
| /*! ECCN |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH2LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_SET_ECCN_MASK) |
| #define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) |
| #define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) |
| #define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH2LAYOUT1_CLR - Hardware BCH ECC Flash 2 Layout 1 Register */ |
| /*! @{ */ |
| #define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) |
| #define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH2LAYOUT1_CLR_ECCN_MASK (0xF800U) |
| #define BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT (11U) |
| /*! ECCN |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH2LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_ECCN_MASK) |
| #define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) |
| #define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) |
| #define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH2LAYOUT1_TOG - Hardware BCH ECC Flash 2 Layout 1 Register */ |
| /*! @{ */ |
| #define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) |
| #define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH2LAYOUT1_TOG_ECCN_MASK (0xF800U) |
| #define BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT (11U) |
| /*! ECCN |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH2LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_ECCN_MASK) |
| #define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) |
| #define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) |
| #define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */ |
| /*! @{ */ |
| #define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT (0U) |
| #define BCH_FLASH3LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH3LAYOUT0_ECC0_MASK (0xF800U) |
| #define BCH_FLASH3LAYOUT0_ECC0_SHIFT (11U) |
| /*! ECC0 |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH3LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK) |
| #define BCH_FLASH3LAYOUT0_META_SIZE_MASK (0xFF0000U) |
| #define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT (16U) |
| #define BCH_FLASH3LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT0_NBLOCKS_MASK (0xFF000000U) |
| #define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT (24U) |
| #define BCH_FLASH3LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH3LAYOUT0_SET - Hardware BCH ECC Flash 3 Layout 0 Register */ |
| /*! @{ */ |
| #define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) |
| #define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH3LAYOUT0_SET_ECC0_MASK (0xF800U) |
| #define BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT (11U) |
| /*! ECC0 |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH3LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_SET_ECC0_MASK) |
| #define BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) |
| #define BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT (16U) |
| #define BCH_FLASH3LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) |
| #define BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT (24U) |
| #define BCH_FLASH3LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH3LAYOUT0_CLR - Hardware BCH ECC Flash 3 Layout 0 Register */ |
| /*! @{ */ |
| #define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) |
| #define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH3LAYOUT0_CLR_ECC0_MASK (0xF800U) |
| #define BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT (11U) |
| /*! ECC0 |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH3LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_ECC0_MASK) |
| #define BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) |
| #define BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT (16U) |
| #define BCH_FLASH3LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) |
| #define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT (24U) |
| #define BCH_FLASH3LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH3LAYOUT0_TOG - Hardware BCH ECC Flash 3 Layout 0 Register */ |
| /*! @{ */ |
| #define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) |
| #define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH3LAYOUT0_TOG_ECC0_MASK (0xF800U) |
| #define BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT (11U) |
| /*! ECC0 |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH3LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_ECC0_MASK) |
| #define BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) |
| #define BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT (16U) |
| #define BCH_FLASH3LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) |
| #define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT (24U) |
| #define BCH_FLASH3LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */ |
| /*! @{ */ |
| #define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT (0U) |
| #define BCH_FLASH3LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH3LAYOUT1_ECCN_MASK (0xF800U) |
| #define BCH_FLASH3LAYOUT1_ECCN_SHIFT (11U) |
| /*! ECCN |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH3LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK) |
| #define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) |
| #define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT (16U) |
| #define BCH_FLASH3LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH3LAYOUT1_SET - Hardware BCH ECC Flash 3 Layout 1 Register */ |
| /*! @{ */ |
| #define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) |
| #define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH3LAYOUT1_SET_ECCN_MASK (0xF800U) |
| #define BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT (11U) |
| /*! ECCN |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH3LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_SET_ECCN_MASK) |
| #define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) |
| #define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) |
| #define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH3LAYOUT1_CLR - Hardware BCH ECC Flash 3 Layout 1 Register */ |
| /*! @{ */ |
| #define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) |
| #define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH3LAYOUT1_CLR_ECCN_MASK (0xF800U) |
| #define BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT (11U) |
| /*! ECCN |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH3LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_ECCN_MASK) |
| #define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) |
| #define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) |
| #define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK) |
| /*! @} */ |
| |
| /*! @name FLASH3LAYOUT1_TOG - Hardware BCH ECC Flash 3 Layout 1 Register */ |
| /*! @{ */ |
| #define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) |
| #define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) |
| #define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) |
| #define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) |
| #define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_MASK) |
| #define BCH_FLASH3LAYOUT1_TOG_ECCN_MASK (0xF800U) |
| #define BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT (11U) |
| /*! ECCN |
| * 0b00000..No ECC to be performed |
| * 0b00001..ECC 2 to be performed |
| * 0b00010..ECC 4 to be performed |
| * 0b11110..ECC 60 to be performed |
| * 0b11111..ECC 62 to be performed |
| */ |
| #define BCH_FLASH3LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_ECCN_MASK) |
| #define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) |
| #define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) |
| #define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK) |
| /*! @} */ |
| |
| /*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */ |
| /*! @{ */ |
| #define BCH_DEBUG0_DEBUG_REG_SELECT_MASK (0x3FU) |
| #define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT (0U) |
| #define BCH_DEBUG0_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK) |
| #define BCH_DEBUG0_RSVD0_MASK (0xC0U) |
| #define BCH_DEBUG0_RSVD0_SHIFT (6U) |
| #define BCH_DEBUG0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK) |
| #define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK (0x100U) |
| #define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT (8U) |
| /*! BM_KES_TEST_BYPASS |
| * 0b0..Bus master address generator for SYND_GEN writes operates normally. |
| * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. |
| */ |
| #define BCH_DEBUG0_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK) |
| #define BCH_DEBUG0_KES_DEBUG_STALL_MASK (0x200U) |
| #define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT (9U) |
| /*! KES_DEBUG_STALL |
| * 0b0..KES FSM proceeds to next block supplied by bus master. |
| * 0b1..KES FSM waits after current equations are solved and the search engine is started. |
| */ |
| #define BCH_DEBUG0_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK) |
| #define BCH_DEBUG0_KES_DEBUG_STEP_MASK (0x400U) |
| #define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT (10U) |
| #define BCH_DEBUG0_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK) |
| #define BCH_DEBUG0_KES_STANDALONE_MASK (0x800U) |
| #define BCH_DEBUG0_KES_STANDALONE_SHIFT (11U) |
| /*! KES_STANDALONE |
| * 0b0..Bus master address generator for SYND_GEN writes operates normally. |
| * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. |
| */ |
| #define BCH_DEBUG0_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK) |
| #define BCH_DEBUG0_KES_DEBUG_KICK_MASK (0x1000U) |
| #define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT (12U) |
| #define BCH_DEBUG0_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK) |
| #define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK (0x2000U) |
| #define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT (13U) |
| /*! KES_DEBUG_MODE4K |
| * 0b1..Mode is set for 4K NAND pages. |
| * 0b1..Mode is set for 2K NAND pages. |
| */ |
| #define BCH_DEBUG0_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK) |
| #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) |
| #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) |
| /*! KES_DEBUG_PAYLOAD_FLAG |
| * 0b1..Payload is set for 512 bytes data block. |
| * 0b1..Payload is set for 65 or 19 bytes auxiliary block. |
| */ |
| #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK) |
| #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) |
| #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT (15U) |
| #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK) |
| #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) |
| #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) |
| /*! KES_DEBUG_SYNDROME_SYMBOL |
| * 0b000000000..Bus master address generator for SYND_GEN writes operates normally. |
| * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block. |
| */ |
| #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK) |
| #define BCH_DEBUG0_RSVD1_MASK (0xFE000000U) |
| #define BCH_DEBUG0_RSVD1_SHIFT (25U) |
| #define BCH_DEBUG0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK) |
| /*! @} */ |
| |
| /*! @name DEBUG0_SET - Hardware BCH ECC Debug Register0 */ |
| /*! @{ */ |
| #define BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK (0x3FU) |
| #define BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT (0U) |
| #define BCH_DEBUG0_SET_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK) |
| #define BCH_DEBUG0_SET_RSVD0_MASK (0xC0U) |
| #define BCH_DEBUG0_SET_RSVD0_SHIFT (6U) |
| #define BCH_DEBUG0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD0_SHIFT)) & BCH_DEBUG0_SET_RSVD0_MASK) |
| #define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK (0x100U) |
| #define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT (8U) |
| /*! BM_KES_TEST_BYPASS |
| * 0b0..Bus master address generator for SYND_GEN writes operates normally. |
| * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. |
| */ |
| #define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK) |
| #define BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK (0x200U) |
| #define BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT (9U) |
| /*! KES_DEBUG_STALL |
| * 0b0..KES FSM proceeds to next block supplied by bus master. |
| * 0b1..KES FSM waits after current equations are solved and the search engine is started. |
| */ |
| #define BCH_DEBUG0_SET_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK) |
| #define BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK (0x400U) |
| #define BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT (10U) |
| #define BCH_DEBUG0_SET_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK) |
| #define BCH_DEBUG0_SET_KES_STANDALONE_MASK (0x800U) |
| #define BCH_DEBUG0_SET_KES_STANDALONE_SHIFT (11U) |
| /*! KES_STANDALONE |
| * 0b0..Bus master address generator for SYND_GEN writes operates normally. |
| * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. |
| */ |
| #define BCH_DEBUG0_SET_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_SET_KES_STANDALONE_MASK) |
| #define BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK (0x1000U) |
| #define BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT (12U) |
| #define BCH_DEBUG0_SET_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK) |
| #define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK (0x2000U) |
| #define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT (13U) |
| /*! KES_DEBUG_MODE4K |
| * 0b1..Mode is set for 4K NAND pages. |
| * 0b1..Mode is set for 2K NAND pages. |
| */ |
| #define BCH_DEBUG0_SET_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK) |
| #define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) |
| #define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) |
| /*! KES_DEBUG_PAYLOAD_FLAG |
| * 0b1..Payload is set for 512 bytes data block. |
| * 0b1..Payload is set for 65 or 19 bytes auxiliary block. |
| */ |
| #define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK) |
| #define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) |
| #define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT (15U) |
| #define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK) |
| #define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) |
| #define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) |
| /*! KES_DEBUG_SYNDROME_SYMBOL |
| * 0b000000000..Bus master address generator for SYND_GEN writes operates normally. |
| * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block. |
| */ |
| #define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK) |
| #define BCH_DEBUG0_SET_RSVD1_MASK (0xFE000000U) |
| #define BCH_DEBUG0_SET_RSVD1_SHIFT (25U) |
| #define BCH_DEBUG0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD1_SHIFT)) & BCH_DEBUG0_SET_RSVD1_MASK) |
| /*! @} */ |
| |
| /*! @name DEBUG0_CLR - Hardware BCH ECC Debug Register0 */ |
| /*! @{ */ |
| #define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK (0x3FU) |
| #define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT (0U) |
| #define BCH_DEBUG0_CLR_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK) |
| #define BCH_DEBUG0_CLR_RSVD0_MASK (0xC0U) |
| #define BCH_DEBUG0_CLR_RSVD0_SHIFT (6U) |
| #define BCH_DEBUG0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD0_SHIFT)) & BCH_DEBUG0_CLR_RSVD0_MASK) |
| #define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK (0x100U) |
| #define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT (8U) |
| /*! BM_KES_TEST_BYPASS |
| * 0b0..Bus master address generator for SYND_GEN writes operates normally. |
| * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. |
| */ |
| #define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK) |
| #define BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK (0x200U) |
| #define BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT (9U) |
| /*! KES_DEBUG_STALL |
| * 0b0..KES FSM proceeds to next block supplied by bus master. |
| * 0b1..KES FSM waits after current equations are solved and the search engine is started. |
| */ |
| #define BCH_DEBUG0_CLR_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK) |
| #define BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK (0x400U) |
| #define BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT (10U) |
| #define BCH_DEBUG0_CLR_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK) |
| #define BCH_DEBUG0_CLR_KES_STANDALONE_MASK (0x800U) |
| #define BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT (11U) |
| /*! KES_STANDALONE |
| * 0b0..Bus master address generator for SYND_GEN writes operates normally. |
| * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. |
| */ |
| #define BCH_DEBUG0_CLR_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_CLR_KES_STANDALONE_MASK) |
| #define BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK (0x1000U) |
| #define BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT (12U) |
| #define BCH_DEBUG0_CLR_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK) |
| #define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK (0x2000U) |
| #define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT (13U) |
| /*! KES_DEBUG_MODE4K |
| * 0b1..Mode is set for 4K NAND pages. |
| * 0b1..Mode is set for 2K NAND pages. |
| */ |
| #define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK) |
| #define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) |
| #define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) |
| /*! KES_DEBUG_PAYLOAD_FLAG |
| * 0b1..Payload is set for 512 bytes data block. |
| * 0b1..Payload is set for 65 or 19 bytes auxiliary block. |
| */ |
| #define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK) |
| #define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) |
| #define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT (15U) |
| #define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK) |
| #define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) |
| #define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) |
| /*! KES_DEBUG_SYNDROME_SYMBOL |
| * 0b000000000..Bus master address generator for SYND_GEN writes operates normally. |
| * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block. |
| */ |
| #define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK) |
| #define BCH_DEBUG0_CLR_RSVD1_MASK (0xFE000000U) |
| #define BCH_DEBUG0_CLR_RSVD1_SHIFT (25U) |
| #define BCH_DEBUG0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD1_SHIFT)) & BCH_DEBUG0_CLR_RSVD1_MASK) |
| /*! @} */ |
| |
| /*! @name DEBUG0_TOG - Hardware BCH ECC Debug Register0 */ |
| /*! @{ */ |
| #define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK (0x3FU) |
| #define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT (0U) |
| #define BCH_DEBUG0_TOG_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK) |
| #define BCH_DEBUG0_TOG_RSVD0_MASK (0xC0U) |
| #define BCH_DEBUG0_TOG_RSVD0_SHIFT (6U) |
| #define BCH_DEBUG0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD0_SHIFT)) & BCH_DEBUG0_TOG_RSVD0_MASK) |
| #define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK (0x100U) |
| #define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT (8U) |
| /*! BM_KES_TEST_BYPASS |
| * 0b0..Bus master address generator for SYND_GEN writes operates normally. |
| * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. |
| */ |
| #define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK) |
| #define BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK (0x200U) |
| #define BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT (9U) |
| /*! KES_DEBUG_STALL |
| * 0b0..KES FSM proceeds to next block supplied by bus master. |
| * 0b1..KES FSM waits after current equations are solved and the search engine is started. |
| */ |
| #define BCH_DEBUG0_TOG_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK) |
| #define BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK (0x400U) |
| #define BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT (10U) |
| #define BCH_DEBUG0_TOG_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK) |
| #define BCH_DEBUG0_TOG_KES_STANDALONE_MASK (0x800U) |
| #define BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT (11U) |
| /*! KES_STANDALONE |
| * 0b0..Bus master address generator for SYND_GEN writes operates normally. |
| * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. |
| */ |
| #define BCH_DEBUG0_TOG_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_TOG_KES_STANDALONE_MASK) |
| #define BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK (0x1000U) |
| #define BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT (12U) |
| #define BCH_DEBUG0_TOG_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK) |
| #define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK (0x2000U) |
| #define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT (13U) |
| /*! KES_DEBUG_MODE4K |
| * 0b1..Mode is set for 4K NAND pages. |
| * 0b1..Mode is set for 2K NAND pages. |
| */ |
| #define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK) |
| #define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) |
| #define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) |
| /*! KES_DEBUG_PAYLOAD_FLAG |
| * 0b1..Payload is set for 512 bytes data block. |
| * 0b1..Payload is set for 65 or 19 bytes auxiliary block. |
| */ |
| #define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK) |
| #define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) |
| #define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT (15U) |
| #define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK) |
| #define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) |
| #define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) |
| /*! KES_DEBUG_SYNDROME_SYMBOL |
| * 0b000000000..Bus master address generator for SYND_GEN writes operates normally. |
| * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block. |
| */ |
| #define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK) |
| #define BCH_DEBUG0_TOG_RSVD1_MASK (0xFE000000U) |
| #define BCH_DEBUG0_TOG_RSVD1_SHIFT (25U) |
| #define BCH_DEBUG0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD1_SHIFT)) & BCH_DEBUG0_TOG_RSVD1_MASK) |
| /*! @} */ |
| |
| /*! @name DBGKESREAD - KES Debug Read Register */ |
| /*! @{ */ |
| #define BCH_DBGKESREAD_VALUES_MASK (0xFFFFFFFFU) |
| #define BCH_DBGKESREAD_VALUES_SHIFT (0U) |
| #define BCH_DBGKESREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK) |
| /*! @} */ |
| |
| /*! @name DBGKESREAD_SET - KES Debug Read Register */ |
| /*! @{ */ |
| #define BCH_DBGKESREAD_SET_VALUES_MASK (0xFFFFFFFFU) |
| #define BCH_DBGKESREAD_SET_VALUES_SHIFT (0U) |
| #define BCH_DBGKESREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_SET_VALUES_SHIFT)) & BCH_DBGKESREAD_SET_VALUES_MASK) |
| /*! @} */ |
| |
| /*! @name DBGKESREAD_CLR - KES Debug Read Register */ |
| /*! @{ */ |
| #define BCH_DBGKESREAD_CLR_VALUES_MASK (0xFFFFFFFFU) |
| #define BCH_DBGKESREAD_CLR_VALUES_SHIFT (0U) |
| #define BCH_DBGKESREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_CLR_VALUES_SHIFT)) & BCH_DBGKESREAD_CLR_VALUES_MASK) |
| /*! @} */ |
| |
| /*! @name DBGKESREAD_TOG - KES Debug Read Register */ |
| /*! @{ */ |
| #define BCH_DBGKESREAD_TOG_VALUES_MASK (0xFFFFFFFFU) |
| #define BCH_DBGKESREAD_TOG_VALUES_SHIFT (0U) |
| #define BCH_DBGKESREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_TOG_VALUES_SHIFT)) & BCH_DBGKESREAD_TOG_VALUES_MASK) |
| /*! @} */ |
| |
| /*! @name DBGCSFEREAD - Chien Search Debug Read Register */ |
| /*! @{ */ |
| #define BCH_DBGCSFEREAD_VALUES_MASK (0xFFFFFFFFU) |
| #define BCH_DBGCSFEREAD_VALUES_SHIFT (0U) |
| #define BCH_DBGCSFEREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK) |
| /*! @} */ |
| |
| /*! @name DBGCSFEREAD_SET - Chien Search Debug Read Register */ |
| /*! @{ */ |
| #define BCH_DBGCSFEREAD_SET_VALUES_MASK (0xFFFFFFFFU) |
| #define BCH_DBGCSFEREAD_SET_VALUES_SHIFT (0U) |
| #define BCH_DBGCSFEREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_SET_VALUES_SHIFT)) & BCH_DBGCSFEREAD_SET_VALUES_MASK) |
| /*! @} */ |
| |
| /*! @name DBGCSFEREAD_CLR - Chien Search Debug Read Register */ |
| /*! @{ */ |
| #define BCH_DBGCSFEREAD_CLR_VALUES_MASK (0xFFFFFFFFU) |
| #define BCH_DBGCSFEREAD_CLR_VALUES_SHIFT (0U) |
| #define BCH_DBGCSFEREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_CLR_VALUES_SHIFT)) & BCH_DBGCSFEREAD_CLR_VALUES_MASK) |
| /*! @} */ |
| |
| /*! @name DBGCSFEREAD_TOG - Chien Search Debug Read Register */ |
| /*! @{ */ |
| #define BCH_DBGCSFEREAD_TOG_VALUES_MASK (0xFFFFFFFFU) |
| #define BCH_DBGCSFEREAD_TOG_VALUES_SHIFT (0U) |
| #define BCH_DBGCSFEREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_TOG_VALUES_SHIFT)) & BCH_DBGCSFEREAD_TOG_VALUES_MASK) |
| /*! @} */ |
| |
| /*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */ |
| /*! @{ */ |
| #define BCH_DBGSYNDGENREAD_VALUES_MASK (0xFFFFFFFFU) |
| #define BCH_DBGSYNDGENREAD_VALUES_SHIFT (0U) |
| #define BCH_DBGSYNDGENREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK) |
| /*! @} */ |
| |
| /*! @name DBGSYNDGENREAD_SET - Syndrome Generator Debug Read Register */ |
| /*! @{ */ |
| #define BCH_DBGSYNDGENREAD_SET_VALUES_MASK (0xFFFFFFFFU) |
| #define BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT (0U) |
| #define BCH_DBGSYNDGENREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_SET_VALUES_MASK) |
| /*! @} */ |
| |
| /*! @name DBGSYNDGENREAD_CLR - Syndrome Generator Debug Read Register */ |
| /*! @{ */ |
| #define BCH_DBGSYNDGENREAD_CLR_VALUES_MASK (0xFFFFFFFFU) |
| #define BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT (0U) |
| #define BCH_DBGSYNDGENREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_CLR_VALUES_MASK) |
| /*! @} */ |
| |
| /*! @name DBGSYNDGENREAD_TOG - Syndrome Generator Debug Read Register */ |
| /*! @{ */ |
| #define BCH_DBGSYNDGENREAD_TOG_VALUES_MASK (0xFFFFFFFFU) |
| #define BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT (0U) |
| #define BCH_DBGSYNDGENREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_TOG_VALUES_MASK) |
| /*! @} */ |
| |
| /*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */ |
| /*! @{ */ |
| #define BCH_DBGAHBMREAD_VALUES_MASK (0xFFFFFFFFU) |
| #define BCH_DBGAHBMREAD_VALUES_SHIFT (0U) |
| #define BCH_DBGAHBMREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK) |
| /*! @} */ |
| |
| /*! @name DBGAHBMREAD_SET - Bus Master and ECC Controller Debug Read Register */ |
| /*! @{ */ |
| #define BCH_DBGAHBMREAD_SET_VALUES_MASK (0xFFFFFFFFU) |
| #define BCH_DBGAHBMREAD_SET_VALUES_SHIFT (0U) |
| #define BCH_DBGAHBMREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_SET_VALUES_SHIFT)) & BCH_DBGAHBMREAD_SET_VALUES_MASK) |
| /*! @} */ |
| |
| /*! @name DBGAHBMREAD_CLR - Bus Master and ECC Controller Debug Read Register */ |
| /*! @{ */ |
| #define BCH_DBGAHBMREAD_CLR_VALUES_MASK (0xFFFFFFFFU) |
| #define BCH_DBGAHBMREAD_CLR_VALUES_SHIFT (0U) |
| #define BCH_DBGAHBMREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_CLR_VALUES_SHIFT)) & BCH_DBGAHBMREAD_CLR_VALUES_MASK) |
| /*! @} */ |
| |
| /*! @name DBGAHBMREAD_TOG - Bus Master and ECC Controller Debug Read Register */ |
| /*! @{ */ |
| #define BCH_DBGAHBMREAD_TOG_VALUES_MASK (0xFFFFFFFFU) |
| #define BCH_DBGAHBMREAD_TOG_VALUES_SHIFT (0U) |
| #define BCH_DBGAHBMREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_TOG_VALUES_SHIFT)) & BCH_DBGAHBMREAD_TOG_VALUES_MASK) |
| /*! @} */ |
| |
| /*! @name BLOCKNAME - Block Name Register */ |
| /*! @{ */ |
| #define BCH_BLOCKNAME_NAME_MASK (0xFFFFFFFFU) |
| #define BCH_BLOCKNAME_NAME_SHIFT (0U) |
| #define BCH_BLOCKNAME_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK) |
| /*! @} */ |
| |
| /*! @name BLOCKNAME_SET - Block Name Register */ |
| /*! @{ */ |
| #define BCH_BLOCKNAME_SET_NAME_MASK (0xFFFFFFFFU) |
| #define BCH_BLOCKNAME_SET_NAME_SHIFT (0U) |
| #define BCH_BLOCKNAME_SET_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_SET_NAME_SHIFT)) & BCH_BLOCKNAME_SET_NAME_MASK) |
| /*! @} */ |
| |
| /*! @name BLOCKNAME_CLR - Block Name Register */ |
| /*! @{ */ |
| #define BCH_BLOCKNAME_CLR_NAME_MASK (0xFFFFFFFFU) |
| #define BCH_BLOCKNAME_CLR_NAME_SHIFT (0U) |
| #define BCH_BLOCKNAME_CLR_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_CLR_NAME_SHIFT)) & BCH_BLOCKNAME_CLR_NAME_MASK) |
| /*! @} */ |
| |
| /*! @name BLOCKNAME_TOG - Block Name Register */ |
| /*! @{ */ |
| #define BCH_BLOCKNAME_TOG_NAME_MASK (0xFFFFFFFFU) |
| #define BCH_BLOCKNAME_TOG_NAME_SHIFT (0U) |
| #define BCH_BLOCKNAME_TOG_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_TOG_NAME_SHIFT)) & BCH_BLOCKNAME_TOG_NAME_MASK) |
| /*! @} */ |
| |
| /*! @name VERSION - BCH Version Register */ |
| /*! @{ */ |
| #define BCH_VERSION_STEP_MASK (0xFFFFU) |
| #define BCH_VERSION_STEP_SHIFT (0U) |
| #define BCH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK) |
| #define BCH_VERSION_MINOR_MASK (0xFF0000U) |
| #define BCH_VERSION_MINOR_SHIFT (16U) |
| #define BCH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK) |
| #define BCH_VERSION_MAJOR_MASK (0xFF000000U) |
| #define BCH_VERSION_MAJOR_SHIFT (24U) |
| #define BCH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK) |
| /*! @} */ |
| |
| /*! @name VERSION_SET - BCH Version Register */ |
| /*! @{ */ |
| #define BCH_VERSION_SET_STEP_MASK (0xFFFFU) |
| #define BCH_VERSION_SET_STEP_SHIFT (0U) |
| #define BCH_VERSION_SET_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_SET_STEP_SHIFT)) & BCH_VERSION_SET_STEP_MASK) |
| #define BCH_VERSION_SET_MINOR_MASK (0xFF0000U) |
| #define BCH_VERSION_SET_MINOR_SHIFT (16U) |
| #define BCH_VERSION_SET_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_SET_MINOR_SHIFT)) & BCH_VERSION_SET_MINOR_MASK) |
| #define BCH_VERSION_SET_MAJOR_MASK (0xFF000000U) |
| #define BCH_VERSION_SET_MAJOR_SHIFT (24U) |
| #define BCH_VERSION_SET_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_SET_MAJOR_SHIFT)) & BCH_VERSION_SET_MAJOR_MASK) |
| /*! @} */ |
| |
| /*! @name VERSION_CLR - BCH Version Register */ |
| /*! @{ */ |
| #define BCH_VERSION_CLR_STEP_MASK (0xFFFFU) |
| #define BCH_VERSION_CLR_STEP_SHIFT (0U) |
| #define BCH_VERSION_CLR_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_CLR_STEP_SHIFT)) & BCH_VERSION_CLR_STEP_MASK) |
| #define BCH_VERSION_CLR_MINOR_MASK (0xFF0000U) |
| #define BCH_VERSION_CLR_MINOR_SHIFT (16U) |
| #define BCH_VERSION_CLR_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_CLR_MINOR_SHIFT)) & BCH_VERSION_CLR_MINOR_MASK) |
| #define BCH_VERSION_CLR_MAJOR_MASK (0xFF000000U) |
| #define BCH_VERSION_CLR_MAJOR_SHIFT (24U) |
| #define BCH_VERSION_CLR_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_CLR_MAJOR_SHIFT)) & BCH_VERSION_CLR_MAJOR_MASK) |
| /*! @} */ |
| |
| /*! @name VERSION_TOG - BCH Version Register */ |
| /*! @{ */ |
| #define BCH_VERSION_TOG_STEP_MASK (0xFFFFU) |
| #define BCH_VERSION_TOG_STEP_SHIFT (0U) |
| #define BCH_VERSION_TOG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_TOG_STEP_SHIFT)) & BCH_VERSION_TOG_STEP_MASK) |
| #define BCH_VERSION_TOG_MINOR_MASK (0xFF0000U) |
| #define BCH_VERSION_TOG_MINOR_SHIFT (16U) |
| #define BCH_VERSION_TOG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_TOG_MINOR_SHIFT)) & BCH_VERSION_TOG_MINOR_MASK) |
| #define BCH_VERSION_TOG_MAJOR_MASK (0xFF000000U) |
| #define BCH_VERSION_TOG_MAJOR_SHIFT (24U) |
| #define BCH_VERSION_TOG_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_TOG_MAJOR_SHIFT)) & BCH_VERSION_TOG_MAJOR_MASK) |
| /*! @} */ |
| |
| /*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */ |
| /*! @{ */ |
| #define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK (0x1FFU) |
| #define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT (0U) |
| #define BCH_DEBUG1_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK) |
| #define BCH_DEBUG1_RSVD_MASK (0x7FFFFE00U) |
| #define BCH_DEBUG1_RSVD_SHIFT (9U) |
| #define BCH_DEBUG1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK) |
| #define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK (0x80000000U) |
| #define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT (31U) |
| /*! DEBUG1_PREERASECHK |
| * 0b0..Turn off pre-erase check |
| * 0b1..Turn on pre-erase check |
| */ |
| #define BCH_DEBUG1_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK) |
| /*! @} */ |
| |
| /*! @name DEBUG1_SET - Hardware BCH ECC Debug Register 1 */ |
| /*! @{ */ |
| #define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK (0x1FFU) |
| #define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT (0U) |
| #define BCH_DEBUG1_SET_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK) |
| #define BCH_DEBUG1_SET_RSVD_MASK (0x7FFFFE00U) |
| #define BCH_DEBUG1_SET_RSVD_SHIFT (9U) |
| #define BCH_DEBUG1_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_SET_RSVD_SHIFT)) & BCH_DEBUG1_SET_RSVD_MASK) |
| #define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_MASK (0x80000000U) |
| #define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_SHIFT (31U) |
| /*! DEBUG1_PREERASECHK |
| * 0b0..Turn off pre-erase check |
| * 0b1..Turn on pre-erase check |
| */ |
| #define BCH_DEBUG1_SET_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_SET_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_SET_DEBUG1_PREERASECHK_MASK) |
| /*! @} */ |
| |
| /*! @name DEBUG1_CLR - Hardware BCH ECC Debug Register 1 */ |
| /*! @{ */ |
| #define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK (0x1FFU) |
| #define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT (0U) |
| #define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK) |
| #define BCH_DEBUG1_CLR_RSVD_MASK (0x7FFFFE00U) |
| #define BCH_DEBUG1_CLR_RSVD_SHIFT (9U) |
| #define BCH_DEBUG1_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_CLR_RSVD_SHIFT)) & BCH_DEBUG1_CLR_RSVD_MASK) |
| #define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_MASK (0x80000000U) |
| #define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_SHIFT (31U) |
| /*! DEBUG1_PREERASECHK |
| * 0b0..Turn off pre-erase check |
| * 0b1..Turn on pre-erase check |
| */ |
| #define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_MASK) |
| /*! @} */ |
| |
| /*! @name DEBUG1_TOG - Hardware BCH ECC Debug Register 1 */ |
| /*! @{ */ |
| #define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK (0x1FFU) |
| #define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT (0U) |
| #define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK) |
| #define BCH_DEBUG1_TOG_RSVD_MASK (0x7FFFFE00U) |
| #define BCH_DEBUG1_TOG_RSVD_SHIFT (9U) |
| #define BCH_DEBUG1_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_TOG_RSVD_SHIFT)) & BCH_DEBUG1_TOG_RSVD_MASK) |
| #define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_MASK (0x80000000U) |
| #define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_SHIFT (31U) |
| /*! DEBUG1_PREERASECHK |
| * 0b0..Turn off pre-erase check |
| * 0b1..Turn on pre-erase check |
| */ |
| #define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group BCH_Register_Masks */ |
| |
| |
| /* BCH - Peripheral instance base addresses */ |
| /** Peripheral BCH base address */ |
| #define BCH_BASE (0x33004000u) |
| /** Peripheral BCH base pointer */ |
| #define BCH ((BCH_Type *)BCH_BASE) |
| /** Array initializer of BCH peripheral base addresses */ |
| #define BCH_BASE_ADDRS { BCH_BASE } |
| /** Array initializer of BCH peripheral base pointers */ |
| #define BCH_BASE_PTRS { BCH } |
| /** Interrupt vectors for the BCH peripheral type */ |
| #define BCH_IRQS { BCH_IRQn } |
| |
| /*! |
| * @} |
| */ /* end of group BCH_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- BLK_CTL Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup BLK_CTL_Peripheral_Access_Layer BLK_CTL Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** BLK_CTL - Register Layout Typedef */ |
| typedef struct { |
| struct { /* offset: 0x0 */ |
| __IO uint32_t RW; /**< Reset Control, offset: 0x0 */ |
| __IO uint32_t SET; /**< Reset Control, offset: 0x4 */ |
| __IO uint32_t CLR; /**< Reset Control, offset: 0x8 */ |
| __IO uint32_t TOG; /**< Reset Control, offset: 0xC */ |
| } RESET_CTRL; |
| struct { /* offset: 0x10 */ |
| __IO uint32_t RW; /**< Control, offset: 0x10 */ |
| __IO uint32_t SET; /**< Control, offset: 0x14 */ |
| __IO uint32_t CLR; /**< Control, offset: 0x18 */ |
| __IO uint32_t TOG; /**< Control, offset: 0x1C */ |
| } CONTROL0; |
| struct { /* offset: 0x20 */ |
| __IO uint32_t RW; /**< Spare Control0, offset: 0x20 */ |
| __IO uint32_t SET; /**< Spare Control0, offset: 0x24 */ |
| __IO uint32_t CLR; /**< Spare Control0, offset: 0x28 */ |
| __IO uint32_t TOG; /**< Spare Control0, offset: 0x2C */ |
| } SPARE_CTRL0; |
| struct { /* offset: 0x30 */ |
| __IO uint32_t RW; /**< Spare Control1, offset: 0x30 */ |
| __IO uint32_t SET; /**< Spare Control1, offset: 0x34 */ |
| __IO uint32_t CLR; /**< Spare Control1, offset: 0x38 */ |
| __IO uint32_t TOG; /**< Spare Control1, offset: 0x3C */ |
| } SPARE_CTRL1; |
| struct { /* offset: 0x40 */ |
| __I uint32_t RW; /**< Spare Status0, offset: 0x40 */ |
| __I uint32_t SET; /**< Spare Status0, offset: 0x44 */ |
| __I uint32_t CLR; /**< Spare Status0, offset: 0x48 */ |
| __I uint32_t TOG; /**< Spare Status0, offset: 0x4C */ |
| } SPARE_STATUS0; |
| } BLK_CTL_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- BLK_CTL Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup BLK_CTL_Register_Masks BLK_CTL Register Masks |
| * @{ |
| */ |
| |
| /*! @name RESET_CTRL - Reset Control */ |
| /*! @{ */ |
| #define BLK_CTL_RESET_CTRL_B_CLK_RESETN_MASK (0x1U) |
| #define BLK_CTL_RESET_CTRL_B_CLK_RESETN_SHIFT (0U) |
| #define BLK_CTL_RESET_CTRL_B_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_RESET_CTRL_B_CLK_RESETN_SHIFT)) & BLK_CTL_RESET_CTRL_B_CLK_RESETN_MASK) |
| #define BLK_CTL_RESET_CTRL_APB_CLK_RESETN_MASK (0x2U) |
| #define BLK_CTL_RESET_CTRL_APB_CLK_RESETN_SHIFT (1U) |
| #define BLK_CTL_RESET_CTRL_APB_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_RESET_CTRL_APB_CLK_RESETN_SHIFT)) & BLK_CTL_RESET_CTRL_APB_CLK_RESETN_MASK) |
| #define BLK_CTL_RESET_CTRL_P_CLK_RESETN_MASK (0x4U) |
| #define BLK_CTL_RESET_CTRL_P_CLK_RESETN_SHIFT (2U) |
| #define BLK_CTL_RESET_CTRL_P_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_RESET_CTRL_P_CLK_RESETN_SHIFT)) & BLK_CTL_RESET_CTRL_P_CLK_RESETN_MASK) |
| #define BLK_CTL_RESET_CTRL_RTR_CLK_RESETN_MASK (0x8U) |
| #define BLK_CTL_RESET_CTRL_RTR_CLK_RESETN_SHIFT (3U) |
| #define BLK_CTL_RESET_CTRL_RTR_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_RESET_CTRL_RTR_CLK_RESETN_SHIFT)) & BLK_CTL_RESET_CTRL_RTR_CLK_RESETN_MASK) |
| #define BLK_CTL_RESET_CTRL_SPARE_CLK_RESETN_MASK (0xFF0000U) |
| #define BLK_CTL_RESET_CTRL_SPARE_CLK_RESETN_SHIFT (16U) |
| #define BLK_CTL_RESET_CTRL_SPARE_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_RESET_CTRL_SPARE_CLK_RESETN_SHIFT)) & BLK_CTL_RESET_CTRL_SPARE_CLK_RESETN_MASK) |
| /*! @} */ |
| |
| /*! @name CONTROL0 - Control */ |
| /*! @{ */ |
| #define BLK_CTL_CONTROL0_DISPMIX_REFCLK_SEL_MASK (0x30U) |
| #define BLK_CTL_CONTROL0_DISPMIX_REFCLK_SEL_SHIFT (4U) |
| #define BLK_CTL_CONTROL0_DISPMIX_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_CONTROL0_DISPMIX_REFCLK_SEL_SHIFT)) & BLK_CTL_CONTROL0_DISPMIX_REFCLK_SEL_MASK) |
| #define BLK_CTL_CONTROL0_DISPMIX_PIXCLK_SEL_MASK (0x100U) |
| #define BLK_CTL_CONTROL0_DISPMIX_PIXCLK_SEL_SHIFT (8U) |
| #define BLK_CTL_CONTROL0_DISPMIX_PIXCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_CONTROL0_DISPMIX_PIXCLK_SEL_SHIFT)) & BLK_CTL_CONTROL0_DISPMIX_PIXCLK_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name SPARE_CTRL0 - Spare Control0 */ |
| /*! @{ */ |
| #define BLK_CTL_SPARE_CTRL0_SPARE_CTRL_MASK (0xFFFFFFFFU) |
| #define BLK_CTL_SPARE_CTRL0_SPARE_CTRL_SHIFT (0U) |
| #define BLK_CTL_SPARE_CTRL0_SPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_SPARE_CTRL0_SPARE_CTRL_SHIFT)) & BLK_CTL_SPARE_CTRL0_SPARE_CTRL_MASK) |
| /*! @} */ |
| |
| /*! @name SPARE_CTRL1 - Spare Control1 */ |
| /*! @{ */ |
| #define BLK_CTL_SPARE_CTRL1_SPARE_CTRL_MASK (0xFFFFFFFFU) |
| #define BLK_CTL_SPARE_CTRL1_SPARE_CTRL_SHIFT (0U) |
| #define BLK_CTL_SPARE_CTRL1_SPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_SPARE_CTRL1_SPARE_CTRL_SHIFT)) & BLK_CTL_SPARE_CTRL1_SPARE_CTRL_MASK) |
| /*! @} */ |
| |
| /*! @name SPARE_STATUS0 - Spare Status0 */ |
| /*! @{ */ |
| #define BLK_CTL_SPARE_STATUS0_SPARE_STATUS_MASK (0xFFFFFFFFU) |
| #define BLK_CTL_SPARE_STATUS0_SPARE_STATUS_SHIFT (0U) |
| #define BLK_CTL_SPARE_STATUS0_SPARE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTL_SPARE_STATUS0_SPARE_STATUS_SHIFT)) & BLK_CTL_SPARE_STATUS0_SPARE_STATUS_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group BLK_CTL_Register_Masks */ |
| |
| |
| /* BLK_CTL - Peripheral instance base addresses */ |
| /** Peripheral DCSS__BLK_CTL base address */ |
| #define DCSS__BLK_CTL_BASE (0x32E2F000u) |
| /** Peripheral DCSS__BLK_CTL base pointer */ |
| #define DCSS__BLK_CTL ((BLK_CTL_Type *)DCSS__BLK_CTL_BASE) |
| /** Array initializer of BLK_CTL peripheral base addresses */ |
| #define BLK_CTL_BASE_ADDRS { DCSS__BLK_CTL_BASE } |
| /** Array initializer of BLK_CTL peripheral base pointers */ |
| #define BLK_CTL_BASE_PTRS { DCSS__BLK_CTL } |
| |
| /*! |
| * @} |
| */ /* end of group BLK_CTL_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- CCM Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** CCM - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t GPR0; /**< General Purpose Register, offset: 0x0 */ |
| __IO uint32_t GPR0_SET; /**< General Purpose Register, offset: 0x4 */ |
| __IO uint32_t GPR0_CLR; /**< General Purpose Register, offset: 0x8 */ |
| __IO uint32_t GPR0_TOG; /**< General Purpose Register, offset: 0xC */ |
| uint8_t RESERVED_0[2032]; |
| struct { /* offset: 0x800, array step: 0x10 */ |
| __IO uint32_t PLL_CTRL; /**< CCM PLL Control Register, array offset: 0x800, array step: 0x10 */ |
| __IO uint32_t PLL_CTRL_SET; /**< CCM PLL Control Register, array offset: 0x804, array step: 0x10 */ |
| __IO uint32_t PLL_CTRL_CLR; /**< CCM PLL Control Register, array offset: 0x808, array step: 0x10 */ |
| __IO uint32_t PLL_CTRL_TOG; /**< CCM PLL Control Register, array offset: 0x80C, array step: 0x10 */ |
| } PLL_CTRL[39]; |
| uint8_t RESERVED_1[13712]; |
| struct { /* offset: 0x4000, array step: 0x10 */ |
| __IO uint32_t CCGR; /**< CCM Clock Gating Register, array offset: 0x4000, array step: 0x10 */ |
| __IO uint32_t CCGR_SET; /**< CCM Clock Gating Register, array offset: 0x4004, array step: 0x10 */ |
| __IO uint32_t CCGR_CLR; /**< CCM Clock Gating Register, array offset: 0x4008, array step: 0x10 */ |
| __IO uint32_t CCGR_TOG; /**< CCM Clock Gating Register, array offset: 0x400C, array step: 0x10 */ |
| } CCGR[191]; |
| uint8_t RESERVED_2[13328]; |
| struct { /* offset: 0x8000, array step: 0x80 */ |
| __IO uint32_t TARGET_ROOT; /**< Target Register, array offset: 0x8000, array step: 0x80 */ |
| __IO uint32_t TARGET_ROOT_SET; /**< Target Register, array offset: 0x8004, array step: 0x80 */ |
| __IO uint32_t TARGET_ROOT_CLR; /**< Target Register, array offset: 0x8008, array step: 0x80 */ |
| __IO uint32_t TARGET_ROOT_TOG; /**< Target Register, array offset: 0x800C, array step: 0x80 */ |
| __IO uint32_t MISC; /**< Miscellaneous Register, array offset: 0x8010, array step: 0x80 */ |
| __IO uint32_t MISC_ROOT_SET; /**< Miscellaneous Register, array offset: 0x8014, array step: 0x80 */ |
| __IO uint32_t MISC_ROOT_CLR; /**< Miscellaneous Register, array offset: 0x8018, array step: 0x80 */ |
| __IO uint32_t MISC_ROOT_TOG; /**< Miscellaneous Register, array offset: 0x801C, array step: 0x80 */ |
| __IO uint32_t POST; /**< Post Divider Register, array offset: 0x8020, array step: 0x80 */ |
| __IO uint32_t POST_ROOT_SET; /**< Post Divider Register, array offset: 0x8024, array step: 0x80 */ |
| __IO uint32_t POST_ROOT_CLR; /**< Post Divider Register, array offset: 0x8028, array step: 0x80 */ |
| __IO uint32_t POST_ROOT_TOG; /**< Post Divider Register, array offset: 0x802C, array step: 0x80 */ |
| __IO uint32_t PRE; /**< Pre Divider Register, array offset: 0x8030, array step: 0x80 */ |
| __IO uint32_t PRE_ROOT_SET; /**< Pre Divider Register, array offset: 0x8034, array step: 0x80 */ |
| __IO uint32_t PRE_ROOT_CLR; /**< Pre Divider Register, array offset: 0x8038, array step: 0x80 */ |
| __IO uint32_t PRE_ROOT_TOG; /**< Pre Divider Register, array offset: 0x803C, array step: 0x80 */ |
| uint8_t RESERVED_0[48]; |
| __IO uint32_t ACCESS_CTRL; /**< Access Control Register, array offset: 0x8070, array step: 0x80 */ |
| __IO uint32_t ACCESS_CTRL_ROOT_SET; /**< Access Control Register, array offset: 0x8074, array step: 0x80 */ |
| __IO uint32_t ACCESS_CTRL_ROOT_CLR; /**< Access Control Register, array offset: 0x8078, array step: 0x80 */ |
| __IO uint32_t ACCESS_CTRL_ROOT_TOG; /**< Access Control Register, array offset: 0x807C, array step: 0x80 */ |
| } ROOT[142]; |
| } CCM_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- CCM Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CCM_Register_Masks CCM Register Masks |
| * @{ |
| */ |
| |
| /*! @name GPR0 - General Purpose Register */ |
| /*! @{ */ |
| #define CCM_GPR0_GP0_MASK (0xFFFFFFFFU) |
| #define CCM_GPR0_GP0_SHIFT (0U) |
| #define CCM_GPR0_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_GP0_SHIFT)) & CCM_GPR0_GP0_MASK) |
| /*! @} */ |
| |
| /*! @name GPR0_SET - General Purpose Register */ |
| /*! @{ */ |
| #define CCM_GPR0_SET_GP0_MASK (0xFFFFFFFFU) |
| #define CCM_GPR0_SET_GP0_SHIFT (0U) |
| #define CCM_GPR0_SET_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_SET_GP0_SHIFT)) & CCM_GPR0_SET_GP0_MASK) |
| /*! @} */ |
| |
| /*! @name GPR0_CLR - General Purpose Register */ |
| /*! @{ */ |
| #define CCM_GPR0_CLR_GP0_MASK (0xFFFFFFFFU) |
| #define CCM_GPR0_CLR_GP0_SHIFT (0U) |
| #define CCM_GPR0_CLR_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_CLR_GP0_SHIFT)) & CCM_GPR0_CLR_GP0_MASK) |
| /*! @} */ |
| |
| /*! @name GPR0_TOG - General Purpose Register */ |
| /*! @{ */ |
| #define CCM_GPR0_TOG_GP0_MASK (0xFFFFFFFFU) |
| #define CCM_GPR0_TOG_GP0_SHIFT (0U) |
| #define CCM_GPR0_TOG_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_TOG_GP0_SHIFT)) & CCM_GPR0_TOG_GP0_MASK) |
| /*! @} */ |
| |
| /*! @name PLL_CTRL - CCM PLL Control Register */ |
| /*! @{ */ |
| #define CCM_PLL_CTRL_SETTING0_MASK (0x3U) |
| #define CCM_PLL_CTRL_SETTING0_SHIFT (0U) |
| /*! SETTING0 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_PLL_CTRL_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING0_SHIFT)) & CCM_PLL_CTRL_SETTING0_MASK) |
| #define CCM_PLL_CTRL_SETTING1_MASK (0x30U) |
| #define CCM_PLL_CTRL_SETTING1_SHIFT (4U) |
| /*! SETTING1 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_PLL_CTRL_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING1_SHIFT)) & CCM_PLL_CTRL_SETTING1_MASK) |
| #define CCM_PLL_CTRL_SETTING2_MASK (0x300U) |
| #define CCM_PLL_CTRL_SETTING2_SHIFT (8U) |
| /*! SETTING2 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_PLL_CTRL_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING2_SHIFT)) & CCM_PLL_CTRL_SETTING2_MASK) |
| #define CCM_PLL_CTRL_SETTING3_MASK (0x3000U) |
| #define CCM_PLL_CTRL_SETTING3_SHIFT (12U) |
| /*! SETTING3 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_PLL_CTRL_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING3_SHIFT)) & CCM_PLL_CTRL_SETTING3_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_PLL_CTRL */ |
| #define CCM_PLL_CTRL_COUNT (39U) |
| |
| /*! @name PLL_CTRL_SET - CCM PLL Control Register */ |
| /*! @{ */ |
| #define CCM_PLL_CTRL_SET_SETTING0_MASK (0x3U) |
| #define CCM_PLL_CTRL_SET_SETTING0_SHIFT (0U) |
| /*! SETTING0 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_PLL_CTRL_SET_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING0_SHIFT)) & CCM_PLL_CTRL_SET_SETTING0_MASK) |
| #define CCM_PLL_CTRL_SET_SETTING1_MASK (0x30U) |
| #define CCM_PLL_CTRL_SET_SETTING1_SHIFT (4U) |
| /*! SETTING1 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_PLL_CTRL_SET_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING1_SHIFT)) & CCM_PLL_CTRL_SET_SETTING1_MASK) |
| #define CCM_PLL_CTRL_SET_SETTING2_MASK (0x300U) |
| #define CCM_PLL_CTRL_SET_SETTING2_SHIFT (8U) |
| /*! SETTING2 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_PLL_CTRL_SET_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING2_SHIFT)) & CCM_PLL_CTRL_SET_SETTING2_MASK) |
| #define CCM_PLL_CTRL_SET_SETTING3_MASK (0x3000U) |
| #define CCM_PLL_CTRL_SET_SETTING3_SHIFT (12U) |
| /*! SETTING3 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_PLL_CTRL_SET_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING3_SHIFT)) & CCM_PLL_CTRL_SET_SETTING3_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_PLL_CTRL_SET */ |
| #define CCM_PLL_CTRL_SET_COUNT (39U) |
| |
| /*! @name PLL_CTRL_CLR - CCM PLL Control Register */ |
| /*! @{ */ |
| #define CCM_PLL_CTRL_CLR_SETTING0_MASK (0x3U) |
| #define CCM_PLL_CTRL_CLR_SETTING0_SHIFT (0U) |
| /*! SETTING0 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_PLL_CTRL_CLR_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING0_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING0_MASK) |
| #define CCM_PLL_CTRL_CLR_SETTING1_MASK (0x30U) |
| #define CCM_PLL_CTRL_CLR_SETTING1_SHIFT (4U) |
| /*! SETTING1 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_PLL_CTRL_CLR_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING1_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING1_MASK) |
| #define CCM_PLL_CTRL_CLR_SETTING2_MASK (0x300U) |
| #define CCM_PLL_CTRL_CLR_SETTING2_SHIFT (8U) |
| /*! SETTING2 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_PLL_CTRL_CLR_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING2_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING2_MASK) |
| #define CCM_PLL_CTRL_CLR_SETTING3_MASK (0x3000U) |
| #define CCM_PLL_CTRL_CLR_SETTING3_SHIFT (12U) |
| /*! SETTING3 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_PLL_CTRL_CLR_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING3_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING3_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_PLL_CTRL_CLR */ |
| #define CCM_PLL_CTRL_CLR_COUNT (39U) |
| |
| /*! @name PLL_CTRL_TOG - CCM PLL Control Register */ |
| /*! @{ */ |
| #define CCM_PLL_CTRL_TOG_SETTING0_MASK (0x3U) |
| #define CCM_PLL_CTRL_TOG_SETTING0_SHIFT (0U) |
| /*! SETTING0 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_PLL_CTRL_TOG_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING0_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING0_MASK) |
| #define CCM_PLL_CTRL_TOG_SETTING1_MASK (0x30U) |
| #define CCM_PLL_CTRL_TOG_SETTING1_SHIFT (4U) |
| /*! SETTING1 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_PLL_CTRL_TOG_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING1_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING1_MASK) |
| #define CCM_PLL_CTRL_TOG_SETTING2_MASK (0x300U) |
| #define CCM_PLL_CTRL_TOG_SETTING2_SHIFT (8U) |
| /*! SETTING2 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_PLL_CTRL_TOG_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING2_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING2_MASK) |
| #define CCM_PLL_CTRL_TOG_SETTING3_MASK (0x3000U) |
| #define CCM_PLL_CTRL_TOG_SETTING3_SHIFT (12U) |
| /*! SETTING3 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_PLL_CTRL_TOG_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING3_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING3_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_PLL_CTRL_TOG */ |
| #define CCM_PLL_CTRL_TOG_COUNT (39U) |
| |
| /*! @name CCGR - CCM Clock Gating Register */ |
| /*! @{ */ |
| #define CCM_CCGR_SETTING0_MASK (0x3U) |
| #define CCM_CCGR_SETTING0_SHIFT (0U) |
| /*! SETTING0 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_CCGR_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING0_SHIFT)) & CCM_CCGR_SETTING0_MASK) |
| #define CCM_CCGR_SETTING1_MASK (0x30U) |
| #define CCM_CCGR_SETTING1_SHIFT (4U) |
| /*! SETTING1 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_CCGR_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING1_SHIFT)) & CCM_CCGR_SETTING1_MASK) |
| #define CCM_CCGR_SETTING2_MASK (0x300U) |
| #define CCM_CCGR_SETTING2_SHIFT (8U) |
| /*! SETTING2 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_CCGR_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING2_SHIFT)) & CCM_CCGR_SETTING2_MASK) |
| #define CCM_CCGR_SETTING3_MASK (0x3000U) |
| #define CCM_CCGR_SETTING3_SHIFT (12U) |
| /*! SETTING3 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_CCGR_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING3_SHIFT)) & CCM_CCGR_SETTING3_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_CCGR */ |
| #define CCM_CCGR_COUNT (191U) |
| |
| /*! @name CCGR_SET - CCM Clock Gating Register */ |
| /*! @{ */ |
| #define CCM_CCGR_SET_SETTING0_MASK (0x3U) |
| #define CCM_CCGR_SET_SETTING0_SHIFT (0U) |
| /*! SETTING0 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_CCGR_SET_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING0_SHIFT)) & CCM_CCGR_SET_SETTING0_MASK) |
| #define CCM_CCGR_SET_SETTING1_MASK (0x30U) |
| #define CCM_CCGR_SET_SETTING1_SHIFT (4U) |
| /*! SETTING1 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_CCGR_SET_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING1_SHIFT)) & CCM_CCGR_SET_SETTING1_MASK) |
| #define CCM_CCGR_SET_SETTING2_MASK (0x300U) |
| #define CCM_CCGR_SET_SETTING2_SHIFT (8U) |
| /*! SETTING2 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_CCGR_SET_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING2_SHIFT)) & CCM_CCGR_SET_SETTING2_MASK) |
| #define CCM_CCGR_SET_SETTING3_MASK (0x3000U) |
| #define CCM_CCGR_SET_SETTING3_SHIFT (12U) |
| /*! SETTING3 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_CCGR_SET_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING3_SHIFT)) & CCM_CCGR_SET_SETTING3_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_CCGR_SET */ |
| #define CCM_CCGR_SET_COUNT (191U) |
| |
| /*! @name CCGR_CLR - CCM Clock Gating Register */ |
| /*! @{ */ |
| #define CCM_CCGR_CLR_SETTING0_MASK (0x3U) |
| #define CCM_CCGR_CLR_SETTING0_SHIFT (0U) |
| /*! SETTING0 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_CCGR_CLR_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING0_SHIFT)) & CCM_CCGR_CLR_SETTING0_MASK) |
| #define CCM_CCGR_CLR_SETTING1_MASK (0x30U) |
| #define CCM_CCGR_CLR_SETTING1_SHIFT (4U) |
| /*! SETTING1 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_CCGR_CLR_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING1_SHIFT)) & CCM_CCGR_CLR_SETTING1_MASK) |
| #define CCM_CCGR_CLR_SETTING2_MASK (0x300U) |
| #define CCM_CCGR_CLR_SETTING2_SHIFT (8U) |
| /*! SETTING2 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_CCGR_CLR_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING2_SHIFT)) & CCM_CCGR_CLR_SETTING2_MASK) |
| #define CCM_CCGR_CLR_SETTING3_MASK (0x3000U) |
| #define CCM_CCGR_CLR_SETTING3_SHIFT (12U) |
| /*! SETTING3 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_CCGR_CLR_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING3_SHIFT)) & CCM_CCGR_CLR_SETTING3_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_CCGR_CLR */ |
| #define CCM_CCGR_CLR_COUNT (191U) |
| |
| /*! @name CCGR_TOG - CCM Clock Gating Register */ |
| /*! @{ */ |
| #define CCM_CCGR_TOG_SETTING0_MASK (0x3U) |
| #define CCM_CCGR_TOG_SETTING0_SHIFT (0U) |
| /*! SETTING0 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_CCGR_TOG_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING0_SHIFT)) & CCM_CCGR_TOG_SETTING0_MASK) |
| #define CCM_CCGR_TOG_SETTING1_MASK (0x30U) |
| #define CCM_CCGR_TOG_SETTING1_SHIFT (4U) |
| /*! SETTING1 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_CCGR_TOG_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING1_SHIFT)) & CCM_CCGR_TOG_SETTING1_MASK) |
| #define CCM_CCGR_TOG_SETTING2_MASK (0x300U) |
| #define CCM_CCGR_TOG_SETTING2_SHIFT (8U) |
| /*! SETTING2 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_CCGR_TOG_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING2_SHIFT)) & CCM_CCGR_TOG_SETTING2_MASK) |
| #define CCM_CCGR_TOG_SETTING3_MASK (0x3000U) |
| #define CCM_CCGR_TOG_SETTING3_SHIFT (12U) |
| /*! SETTING3 |
| * 0b00..Domain clocks not needed |
| * 0b01..Domain clocks needed when in RUN |
| * 0b10..Domain clocks needed when in RUN and WAIT |
| * 0b11..Domain clocks needed all the time |
| */ |
| #define CCM_CCGR_TOG_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING3_SHIFT)) & CCM_CCGR_TOG_SETTING3_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_CCGR_TOG */ |
| #define CCM_CCGR_TOG_COUNT (191U) |
| |
| /*! @name TARGET_ROOT - Target Register */ |
| /*! @{ */ |
| #define CCM_TARGET_ROOT_POST_PODF_MASK (0x3FU) |
| #define CCM_TARGET_ROOT_POST_PODF_SHIFT (0U) |
| /*! POST_PODF |
| * 0b000000..Divide by 1 |
| * 0b000001..Divide by 2 |
| * 0b000010..Divide by 3 |
| * 0b000011..Divide by 4 |
| * 0b000100..Divide by 5 |
| * 0b000101..Divide by 6 |
| * 0b111111..Divide by 64 |
| */ |
| #define CCM_TARGET_ROOT_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_POST_PODF_MASK) |
| #define CCM_TARGET_ROOT_PRE_PODF_MASK (0x70000U) |
| #define CCM_TARGET_ROOT_PRE_PODF_SHIFT (16U) |
| /*! PRE_PODF |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_TARGET_ROOT_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_PRE_PODF_MASK) |
| #define CCM_TARGET_ROOT_MUX_MASK (0x7000000U) |
| #define CCM_TARGET_ROOT_MUX_SHIFT (24U) |
| #define CCM_TARGET_ROOT_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_MUX_SHIFT)) & CCM_TARGET_ROOT_MUX_MASK) |
| #define CCM_TARGET_ROOT_ENABLE_MASK (0x10000000U) |
| #define CCM_TARGET_ROOT_ENABLE_SHIFT (28U) |
| /*! ENABLE |
| * 0b0..clock root is OFF |
| * 0b1..clock root is ON |
| */ |
| #define CCM_TARGET_ROOT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_ENABLE_SHIFT)) & CCM_TARGET_ROOT_ENABLE_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_TARGET_ROOT */ |
| #define CCM_TARGET_ROOT_COUNT (142U) |
| |
| /*! @name TARGET_ROOT_SET - Target Register */ |
| /*! @{ */ |
| #define CCM_TARGET_ROOT_SET_POST_PODF_MASK (0x3FU) |
| #define CCM_TARGET_ROOT_SET_POST_PODF_SHIFT (0U) |
| /*! POST_PODF |
| * 0b000000..Divide by 1 |
| * 0b000001..Divide by 2 |
| * 0b000010..Divide by 3 |
| * 0b000011..Divide by 4 |
| * 0b000100..Divide by 5 |
| * 0b000101..Divide by 6 |
| * 0b111111..Divide by 64 |
| */ |
| #define CCM_TARGET_ROOT_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_SET_POST_PODF_MASK) |
| #define CCM_TARGET_ROOT_SET_PRE_PODF_MASK (0x70000U) |
| #define CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT (16U) |
| /*! PRE_PODF |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_TARGET_ROOT_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_SET_PRE_PODF_MASK) |
| #define CCM_TARGET_ROOT_SET_MUX_MASK (0x7000000U) |
| #define CCM_TARGET_ROOT_SET_MUX_SHIFT (24U) |
| #define CCM_TARGET_ROOT_SET_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_MUX_SHIFT)) & CCM_TARGET_ROOT_SET_MUX_MASK) |
| #define CCM_TARGET_ROOT_SET_ENABLE_MASK (0x10000000U) |
| #define CCM_TARGET_ROOT_SET_ENABLE_SHIFT (28U) |
| /*! ENABLE |
| * 0b0..clock root is OFF |
| * 0b1..clock root is ON |
| */ |
| #define CCM_TARGET_ROOT_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_ENABLE_SHIFT)) & CCM_TARGET_ROOT_SET_ENABLE_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_TARGET_ROOT_SET */ |
| #define CCM_TARGET_ROOT_SET_COUNT (142U) |
| |
| /*! @name TARGET_ROOT_CLR - Target Register */ |
| /*! @{ */ |
| #define CCM_TARGET_ROOT_CLR_POST_PODF_MASK (0x3FU) |
| #define CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT (0U) |
| /*! POST_PODF |
| * 0b000000..Divide by 1 |
| * 0b000001..Divide by 2 |
| * 0b000010..Divide by 3 |
| * 0b000011..Divide by 4 |
| * 0b000100..Divide by 5 |
| * 0b000101..Divide by 6 |
| * 0b111111..Divide by 64 |
| */ |
| #define CCM_TARGET_ROOT_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_CLR_POST_PODF_MASK) |
| #define CCM_TARGET_ROOT_CLR_PRE_PODF_MASK (0x70000U) |
| #define CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT (16U) |
| /*! PRE_PODF |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_TARGET_ROOT_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_CLR_PRE_PODF_MASK) |
| #define CCM_TARGET_ROOT_CLR_MUX_MASK (0x7000000U) |
| #define CCM_TARGET_ROOT_CLR_MUX_SHIFT (24U) |
| #define CCM_TARGET_ROOT_CLR_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_MUX_SHIFT)) & CCM_TARGET_ROOT_CLR_MUX_MASK) |
| #define CCM_TARGET_ROOT_CLR_ENABLE_MASK (0x10000000U) |
| #define CCM_TARGET_ROOT_CLR_ENABLE_SHIFT (28U) |
| /*! ENABLE |
| * 0b0..clock root is OFF |
| * 0b1..clock root is ON |
| */ |
| #define CCM_TARGET_ROOT_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_ENABLE_SHIFT)) & CCM_TARGET_ROOT_CLR_ENABLE_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_TARGET_ROOT_CLR */ |
| #define CCM_TARGET_ROOT_CLR_COUNT (142U) |
| |
| /*! @name TARGET_ROOT_TOG - Target Register */ |
| /*! @{ */ |
| #define CCM_TARGET_ROOT_TOG_POST_PODF_MASK (0x3FU) |
| #define CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT (0U) |
| /*! POST_PODF |
| * 0b000000..Divide by 1 |
| * 0b000001..Divide by 2 |
| * 0b000010..Divide by 3 |
| * 0b000011..Divide by 4 |
| * 0b000100..Divide by 5 |
| * 0b000101..Divide by 6 |
| * 0b111111..Divide by 64 |
| */ |
| #define CCM_TARGET_ROOT_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_TOG_POST_PODF_MASK) |
| #define CCM_TARGET_ROOT_TOG_PRE_PODF_MASK (0x70000U) |
| #define CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT (16U) |
| /*! PRE_PODF |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_TARGET_ROOT_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_TOG_PRE_PODF_MASK) |
| #define CCM_TARGET_ROOT_TOG_MUX_MASK (0x7000000U) |
| #define CCM_TARGET_ROOT_TOG_MUX_SHIFT (24U) |
| #define CCM_TARGET_ROOT_TOG_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_MUX_SHIFT)) & CCM_TARGET_ROOT_TOG_MUX_MASK) |
| #define CCM_TARGET_ROOT_TOG_ENABLE_MASK (0x10000000U) |
| #define CCM_TARGET_ROOT_TOG_ENABLE_SHIFT (28U) |
| /*! ENABLE |
| * 0b0..clock root is OFF |
| * 0b1..clock root is ON |
| */ |
| #define CCM_TARGET_ROOT_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_ENABLE_SHIFT)) & CCM_TARGET_ROOT_TOG_ENABLE_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_TARGET_ROOT_TOG */ |
| #define CCM_TARGET_ROOT_TOG_COUNT (142U) |
| |
| /*! @name MISC - Miscellaneous Register */ |
| /*! @{ */ |
| #define CCM_MISC_AUTHEN_FAIL_MASK (0x1U) |
| #define CCM_MISC_AUTHEN_FAIL_SHIFT (0U) |
| #define CCM_MISC_AUTHEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_AUTHEN_FAIL_SHIFT)) & CCM_MISC_AUTHEN_FAIL_MASK) |
| #define CCM_MISC_TIMEOUT_MASK (0x10U) |
| #define CCM_MISC_TIMEOUT_SHIFT (4U) |
| #define CCM_MISC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_TIMEOUT_SHIFT)) & CCM_MISC_TIMEOUT_MASK) |
| #define CCM_MISC_VIOLATE_MASK (0x100U) |
| #define CCM_MISC_VIOLATE_SHIFT (8U) |
| #define CCM_MISC_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_VIOLATE_SHIFT)) & CCM_MISC_VIOLATE_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_MISC */ |
| #define CCM_MISC_COUNT (142U) |
| |
| /*! @name MISC_ROOT_SET - Miscellaneous Register */ |
| /*! @{ */ |
| #define CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK (0x1U) |
| #define CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT (0U) |
| #define CCM_MISC_ROOT_SET_AUTHEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK) |
| #define CCM_MISC_ROOT_SET_TIMEOUT_MASK (0x10U) |
| #define CCM_MISC_ROOT_SET_TIMEOUT_SHIFT (4U) |
| #define CCM_MISC_ROOT_SET_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_SET_TIMEOUT_MASK) |
| #define CCM_MISC_ROOT_SET_VIOLATE_MASK (0x100U) |
| #define CCM_MISC_ROOT_SET_VIOLATE_SHIFT (8U) |
| #define CCM_MISC_ROOT_SET_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_VIOLATE_SHIFT)) & CCM_MISC_ROOT_SET_VIOLATE_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_MISC_ROOT_SET */ |
| #define CCM_MISC_ROOT_SET_COUNT (142U) |
| |
| /*! @name MISC_ROOT_CLR - Miscellaneous Register */ |
| /*! @{ */ |
| #define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK (0x1U) |
| #define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT (0U) |
| #define CCM_MISC_ROOT_CLR_AUTHEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK) |
| #define CCM_MISC_ROOT_CLR_TIMEOUT_MASK (0x10U) |
| #define CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT (4U) |
| #define CCM_MISC_ROOT_CLR_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_CLR_TIMEOUT_MASK) |
| #define CCM_MISC_ROOT_CLR_VIOLATE_MASK (0x100U) |
| #define CCM_MISC_ROOT_CLR_VIOLATE_SHIFT (8U) |
| #define CCM_MISC_ROOT_CLR_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_VIOLATE_SHIFT)) & CCM_MISC_ROOT_CLR_VIOLATE_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_MISC_ROOT_CLR */ |
| #define CCM_MISC_ROOT_CLR_COUNT (142U) |
| |
| /*! @name MISC_ROOT_TOG - Miscellaneous Register */ |
| /*! @{ */ |
| #define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK (0x1U) |
| #define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT (0U) |
| #define CCM_MISC_ROOT_TOG_AUTHEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK) |
| #define CCM_MISC_ROOT_TOG_TIMEOUT_MASK (0x10U) |
| #define CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT (4U) |
| #define CCM_MISC_ROOT_TOG_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_TOG_TIMEOUT_MASK) |
| #define CCM_MISC_ROOT_TOG_VIOLATE_MASK (0x100U) |
| #define CCM_MISC_ROOT_TOG_VIOLATE_SHIFT (8U) |
| #define CCM_MISC_ROOT_TOG_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_VIOLATE_SHIFT)) & CCM_MISC_ROOT_TOG_VIOLATE_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_MISC_ROOT_TOG */ |
| #define CCM_MISC_ROOT_TOG_COUNT (142U) |
| |
| /*! @name POST - Post Divider Register */ |
| /*! @{ */ |
| #define CCM_POST_POST_PODF_MASK (0x3FU) |
| #define CCM_POST_POST_PODF_SHIFT (0U) |
| /*! POST_PODF |
| * 0b000000..Divide by 1 |
| * 0b000001..Divide by 2 |
| * 0b000010..Divide by 3 |
| * 0b000011..Divide by 4 |
| * 0b000100..Divide by 5 |
| * 0b000101..Divide by 6 |
| * 0b111111..Divide by 64 |
| */ |
| #define CCM_POST_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_POST_PODF_SHIFT)) & CCM_POST_POST_PODF_MASK) |
| #define CCM_POST_BUSY1_MASK (0x80U) |
| #define CCM_POST_BUSY1_SHIFT (7U) |
| #define CCM_POST_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_BUSY1_SHIFT)) & CCM_POST_BUSY1_MASK) |
| #define CCM_POST_SELECT_MASK (0x10000000U) |
| #define CCM_POST_SELECT_SHIFT (28U) |
| /*! SELECT |
| * 0b0..select branch A |
| * 0b1..select branch B |
| */ |
| #define CCM_POST_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_SELECT_SHIFT)) & CCM_POST_SELECT_MASK) |
| #define CCM_POST_BUSY2_MASK (0x80000000U) |
| #define CCM_POST_BUSY2_SHIFT (31U) |
| #define CCM_POST_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_BUSY2_SHIFT)) & CCM_POST_BUSY2_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_POST */ |
| #define CCM_POST_COUNT (142U) |
| |
| /*! @name POST_ROOT_SET - Post Divider Register */ |
| /*! @{ */ |
| #define CCM_POST_ROOT_SET_POST_PODF_MASK (0x3FU) |
| #define CCM_POST_ROOT_SET_POST_PODF_SHIFT (0U) |
| /*! POST_PODF |
| * 0b000000..Divide by 1 |
| * 0b000001..Divide by 2 |
| * 0b000010..Divide by 3 |
| * 0b000011..Divide by 4 |
| * 0b000100..Divide by 5 |
| * 0b000101..Divide by 6 |
| * 0b111111..Divide by 64 |
| */ |
| #define CCM_POST_ROOT_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_POST_PODF_SHIFT)) & CCM_POST_ROOT_SET_POST_PODF_MASK) |
| #define CCM_POST_ROOT_SET_BUSY1_MASK (0x80U) |
| #define CCM_POST_ROOT_SET_BUSY1_SHIFT (7U) |
| #define CCM_POST_ROOT_SET_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_BUSY1_SHIFT)) & CCM_POST_ROOT_SET_BUSY1_MASK) |
| #define CCM_POST_ROOT_SET_SELECT_MASK (0x10000000U) |
| #define CCM_POST_ROOT_SET_SELECT_SHIFT (28U) |
| /*! SELECT |
| * 0b0..select branch A |
| * 0b1..select branch B |
| */ |
| #define CCM_POST_ROOT_SET_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_SELECT_SHIFT)) & CCM_POST_ROOT_SET_SELECT_MASK) |
| #define CCM_POST_ROOT_SET_BUSY2_MASK (0x80000000U) |
| #define CCM_POST_ROOT_SET_BUSY2_SHIFT (31U) |
| #define CCM_POST_ROOT_SET_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_BUSY2_SHIFT)) & CCM_POST_ROOT_SET_BUSY2_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_POST_ROOT_SET */ |
| #define CCM_POST_ROOT_SET_COUNT (142U) |
| |
| /*! @name POST_ROOT_CLR - Post Divider Register */ |
| /*! @{ */ |
| #define CCM_POST_ROOT_CLR_POST_PODF_MASK (0x3FU) |
| #define CCM_POST_ROOT_CLR_POST_PODF_SHIFT (0U) |
| /*! POST_PODF |
| * 0b000000..Divide by 1 |
| * 0b000001..Divide by 2 |
| * 0b000010..Divide by 3 |
| * 0b000011..Divide by 4 |
| * 0b000100..Divide by 5 |
| * 0b000101..Divide by 6 |
| * 0b111111..Divide by 64 |
| */ |
| #define CCM_POST_ROOT_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_POST_PODF_SHIFT)) & CCM_POST_ROOT_CLR_POST_PODF_MASK) |
| #define CCM_POST_ROOT_CLR_BUSY1_MASK (0x80U) |
| #define CCM_POST_ROOT_CLR_BUSY1_SHIFT (7U) |
| #define CCM_POST_ROOT_CLR_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_BUSY1_SHIFT)) & CCM_POST_ROOT_CLR_BUSY1_MASK) |
| #define CCM_POST_ROOT_CLR_SELECT_MASK (0x10000000U) |
| #define CCM_POST_ROOT_CLR_SELECT_SHIFT (28U) |
| /*! SELECT |
| * 0b0..select branch A |
| * 0b1..select branch B |
| */ |
| #define CCM_POST_ROOT_CLR_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_SELECT_SHIFT)) & CCM_POST_ROOT_CLR_SELECT_MASK) |
| #define CCM_POST_ROOT_CLR_BUSY2_MASK (0x80000000U) |
| #define CCM_POST_ROOT_CLR_BUSY2_SHIFT (31U) |
| #define CCM_POST_ROOT_CLR_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_BUSY2_SHIFT)) & CCM_POST_ROOT_CLR_BUSY2_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_POST_ROOT_CLR */ |
| #define CCM_POST_ROOT_CLR_COUNT (142U) |
| |
| /*! @name POST_ROOT_TOG - Post Divider Register */ |
| /*! @{ */ |
| #define CCM_POST_ROOT_TOG_POST_PODF_MASK (0x3FU) |
| #define CCM_POST_ROOT_TOG_POST_PODF_SHIFT (0U) |
| /*! POST_PODF |
| * 0b000000..Divide by 1 |
| * 0b000001..Divide by 2 |
| * 0b000010..Divide by 3 |
| * 0b000011..Divide by 4 |
| * 0b000100..Divide by 5 |
| * 0b000101..Divide by 6 |
| * 0b111111..Divide by 64 |
| */ |
| #define CCM_POST_ROOT_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_POST_PODF_SHIFT)) & CCM_POST_ROOT_TOG_POST_PODF_MASK) |
| #define CCM_POST_ROOT_TOG_BUSY1_MASK (0x80U) |
| #define CCM_POST_ROOT_TOG_BUSY1_SHIFT (7U) |
| #define CCM_POST_ROOT_TOG_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_BUSY1_SHIFT)) & CCM_POST_ROOT_TOG_BUSY1_MASK) |
| #define CCM_POST_ROOT_TOG_SELECT_MASK (0x10000000U) |
| #define CCM_POST_ROOT_TOG_SELECT_SHIFT (28U) |
| /*! SELECT |
| * 0b0..select branch A |
| * 0b1..select branch B |
| */ |
| #define CCM_POST_ROOT_TOG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_SELECT_SHIFT)) & CCM_POST_ROOT_TOG_SELECT_MASK) |
| #define CCM_POST_ROOT_TOG_BUSY2_MASK (0x80000000U) |
| #define CCM_POST_ROOT_TOG_BUSY2_SHIFT (31U) |
| #define CCM_POST_ROOT_TOG_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_BUSY2_SHIFT)) & CCM_POST_ROOT_TOG_BUSY2_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_POST_ROOT_TOG */ |
| #define CCM_POST_ROOT_TOG_COUNT (142U) |
| |
| /*! @name PRE - Pre Divider Register */ |
| /*! @{ */ |
| #define CCM_PRE_PRE_PODF_B_MASK (0x7U) |
| #define CCM_PRE_PRE_PODF_B_SHIFT (0U) |
| /*! PRE_PODF_B |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_PRE_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_PRE_PODF_B_SHIFT)) & CCM_PRE_PRE_PODF_B_MASK) |
| #define CCM_PRE_BUSY0_MASK (0x8U) |
| #define CCM_PRE_BUSY0_SHIFT (3U) |
| #define CCM_PRE_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY0_SHIFT)) & CCM_PRE_BUSY0_MASK) |
| #define CCM_PRE_MUX_B_MASK (0x700U) |
| #define CCM_PRE_MUX_B_SHIFT (8U) |
| #define CCM_PRE_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_MUX_B_SHIFT)) & CCM_PRE_MUX_B_MASK) |
| #define CCM_PRE_EN_B_MASK (0x1000U) |
| #define CCM_PRE_EN_B_SHIFT (12U) |
| /*! EN_B |
| * 0b0..Clock shutdown |
| * 0b1..Clock ON |
| */ |
| #define CCM_PRE_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_EN_B_SHIFT)) & CCM_PRE_EN_B_MASK) |
| #define CCM_PRE_BUSY1_MASK (0x8000U) |
| #define CCM_PRE_BUSY1_SHIFT (15U) |
| #define CCM_PRE_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY1_SHIFT)) & CCM_PRE_BUSY1_MASK) |
| #define CCM_PRE_PRE_PODF_A_MASK (0x70000U) |
| #define CCM_PRE_PRE_PODF_A_SHIFT (16U) |
| /*! PRE_PODF_A |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_PRE_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_PRE_PODF_A_SHIFT)) & CCM_PRE_PRE_PODF_A_MASK) |
| #define CCM_PRE_BUSY3_MASK (0x80000U) |
| #define CCM_PRE_BUSY3_SHIFT (19U) |
| #define CCM_PRE_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY3_SHIFT)) & CCM_PRE_BUSY3_MASK) |
| #define CCM_PRE_MUX_A_MASK (0x7000000U) |
| #define CCM_PRE_MUX_A_SHIFT (24U) |
| #define CCM_PRE_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_MUX_A_SHIFT)) & CCM_PRE_MUX_A_MASK) |
| #define CCM_PRE_EN_A_MASK (0x10000000U) |
| #define CCM_PRE_EN_A_SHIFT (28U) |
| /*! EN_A |
| * 0b0..Clock shutdown |
| * 0b1..clock ON |
| */ |
| #define CCM_PRE_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_EN_A_SHIFT)) & CCM_PRE_EN_A_MASK) |
| #define CCM_PRE_BUSY4_MASK (0x80000000U) |
| #define CCM_PRE_BUSY4_SHIFT (31U) |
| #define CCM_PRE_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY4_SHIFT)) & CCM_PRE_BUSY4_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_PRE */ |
| #define CCM_PRE_COUNT (142U) |
| |
| /*! @name PRE_ROOT_SET - Pre Divider Register */ |
| /*! @{ */ |
| #define CCM_PRE_ROOT_SET_PRE_PODF_B_MASK (0x7U) |
| #define CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT (0U) |
| /*! PRE_PODF_B |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_PRE_ROOT_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_SET_PRE_PODF_B_MASK) |
| #define CCM_PRE_ROOT_SET_BUSY0_MASK (0x8U) |
| #define CCM_PRE_ROOT_SET_BUSY0_SHIFT (3U) |
| #define CCM_PRE_ROOT_SET_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY0_SHIFT)) & CCM_PRE_ROOT_SET_BUSY0_MASK) |
| #define CCM_PRE_ROOT_SET_MUX_B_MASK (0x700U) |
| #define CCM_PRE_ROOT_SET_MUX_B_SHIFT (8U) |
| #define CCM_PRE_ROOT_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_MUX_B_SHIFT)) & CCM_PRE_ROOT_SET_MUX_B_MASK) |
| #define CCM_PRE_ROOT_SET_EN_B_MASK (0x1000U) |
| #define CCM_PRE_ROOT_SET_EN_B_SHIFT (12U) |
| /*! EN_B |
| * 0b0..Clock shutdown |
| * 0b1..Clock ON |
| */ |
| #define CCM_PRE_ROOT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_EN_B_SHIFT)) & CCM_PRE_ROOT_SET_EN_B_MASK) |
| #define CCM_PRE_ROOT_SET_BUSY1_MASK (0x8000U) |
| #define CCM_PRE_ROOT_SET_BUSY1_SHIFT (15U) |
| #define CCM_PRE_ROOT_SET_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY1_SHIFT)) & CCM_PRE_ROOT_SET_BUSY1_MASK) |
| #define CCM_PRE_ROOT_SET_PRE_PODF_A_MASK (0x70000U) |
| #define CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT (16U) |
| /*! PRE_PODF_A |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_PRE_ROOT_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_SET_PRE_PODF_A_MASK) |
| #define CCM_PRE_ROOT_SET_BUSY3_MASK (0x80000U) |
| #define CCM_PRE_ROOT_SET_BUSY3_SHIFT (19U) |
| #define CCM_PRE_ROOT_SET_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY3_SHIFT)) & CCM_PRE_ROOT_SET_BUSY3_MASK) |
| #define CCM_PRE_ROOT_SET_MUX_A_MASK (0x7000000U) |
| #define CCM_PRE_ROOT_SET_MUX_A_SHIFT (24U) |
| #define CCM_PRE_ROOT_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_MUX_A_SHIFT)) & CCM_PRE_ROOT_SET_MUX_A_MASK) |
| #define CCM_PRE_ROOT_SET_EN_A_MASK (0x10000000U) |
| #define CCM_PRE_ROOT_SET_EN_A_SHIFT (28U) |
| /*! EN_A |
| * 0b0..Clock shutdown |
| * 0b1..clock ON |
| */ |
| #define CCM_PRE_ROOT_SET_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_EN_A_SHIFT)) & CCM_PRE_ROOT_SET_EN_A_MASK) |
| #define CCM_PRE_ROOT_SET_BUSY4_MASK (0x80000000U) |
| #define CCM_PRE_ROOT_SET_BUSY4_SHIFT (31U) |
| #define CCM_PRE_ROOT_SET_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY4_SHIFT)) & CCM_PRE_ROOT_SET_BUSY4_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_PRE_ROOT_SET */ |
| #define CCM_PRE_ROOT_SET_COUNT (142U) |
| |
| /*! @name PRE_ROOT_CLR - Pre Divider Register */ |
| /*! @{ */ |
| #define CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK (0x7U) |
| #define CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT (0U) |
| /*! PRE_PODF_B |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_PRE_ROOT_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK) |
| #define CCM_PRE_ROOT_CLR_BUSY0_MASK (0x8U) |
| #define CCM_PRE_ROOT_CLR_BUSY0_SHIFT (3U) |
| #define CCM_PRE_ROOT_CLR_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY0_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY0_MASK) |
| #define CCM_PRE_ROOT_CLR_MUX_B_MASK (0x700U) |
| #define CCM_PRE_ROOT_CLR_MUX_B_SHIFT (8U) |
| #define CCM_PRE_ROOT_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_MUX_B_SHIFT)) & CCM_PRE_ROOT_CLR_MUX_B_MASK) |
| #define CCM_PRE_ROOT_CLR_EN_B_MASK (0x1000U) |
| #define CCM_PRE_ROOT_CLR_EN_B_SHIFT (12U) |
| /*! EN_B |
| * 0b0..Clock shutdown |
| * 0b1..Clock ON |
| */ |
| #define CCM_PRE_ROOT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_EN_B_SHIFT)) & CCM_PRE_ROOT_CLR_EN_B_MASK) |
| #define CCM_PRE_ROOT_CLR_BUSY1_MASK (0x8000U) |
| #define CCM_PRE_ROOT_CLR_BUSY1_SHIFT (15U) |
| #define CCM_PRE_ROOT_CLR_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY1_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY1_MASK) |
| #define CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK (0x70000U) |
| #define CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT (16U) |
| /*! PRE_PODF_A |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_PRE_ROOT_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK) |
| #define CCM_PRE_ROOT_CLR_BUSY3_MASK (0x80000U) |
| #define CCM_PRE_ROOT_CLR_BUSY3_SHIFT (19U) |
| #define CCM_PRE_ROOT_CLR_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY3_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY3_MASK) |
| #define CCM_PRE_ROOT_CLR_MUX_A_MASK (0x7000000U) |
| #define CCM_PRE_ROOT_CLR_MUX_A_SHIFT (24U) |
| #define CCM_PRE_ROOT_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_MUX_A_SHIFT)) & CCM_PRE_ROOT_CLR_MUX_A_MASK) |
| #define CCM_PRE_ROOT_CLR_EN_A_MASK (0x10000000U) |
| #define CCM_PRE_ROOT_CLR_EN_A_SHIFT (28U) |
| /*! EN_A |
| * 0b0..Clock shutdown |
| * 0b1..clock ON |
| */ |
| #define CCM_PRE_ROOT_CLR_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_EN_A_SHIFT)) & CCM_PRE_ROOT_CLR_EN_A_MASK) |
| #define CCM_PRE_ROOT_CLR_BUSY4_MASK (0x80000000U) |
| #define CCM_PRE_ROOT_CLR_BUSY4_SHIFT (31U) |
| #define CCM_PRE_ROOT_CLR_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY4_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY4_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_PRE_ROOT_CLR */ |
| #define CCM_PRE_ROOT_CLR_COUNT (142U) |
| |
| /*! @name PRE_ROOT_TOG - Pre Divider Register */ |
| /*! @{ */ |
| #define CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK (0x7U) |
| #define CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT (0U) |
| /*! PRE_PODF_B |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_PRE_ROOT_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK) |
| #define CCM_PRE_ROOT_TOG_BUSY0_MASK (0x8U) |
| #define CCM_PRE_ROOT_TOG_BUSY0_SHIFT (3U) |
| #define CCM_PRE_ROOT_TOG_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY0_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY0_MASK) |
| #define CCM_PRE_ROOT_TOG_MUX_B_MASK (0x700U) |
| #define CCM_PRE_ROOT_TOG_MUX_B_SHIFT (8U) |
| #define CCM_PRE_ROOT_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_MUX_B_SHIFT)) & CCM_PRE_ROOT_TOG_MUX_B_MASK) |
| #define CCM_PRE_ROOT_TOG_EN_B_MASK (0x1000U) |
| #define CCM_PRE_ROOT_TOG_EN_B_SHIFT (12U) |
| /*! EN_B |
| * 0b0..Clock shutdown |
| * 0b1..Clock ON |
| */ |
| #define CCM_PRE_ROOT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_EN_B_SHIFT)) & CCM_PRE_ROOT_TOG_EN_B_MASK) |
| #define CCM_PRE_ROOT_TOG_BUSY1_MASK (0x8000U) |
| #define CCM_PRE_ROOT_TOG_BUSY1_SHIFT (15U) |
| #define CCM_PRE_ROOT_TOG_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY1_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY1_MASK) |
| #define CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK (0x70000U) |
| #define CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT (16U) |
| /*! PRE_PODF_A |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_PRE_ROOT_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK) |
| #define CCM_PRE_ROOT_TOG_BUSY3_MASK (0x80000U) |
| #define CCM_PRE_ROOT_TOG_BUSY3_SHIFT (19U) |
| #define CCM_PRE_ROOT_TOG_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY3_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY3_MASK) |
| #define CCM_PRE_ROOT_TOG_MUX_A_MASK (0x7000000U) |
| #define CCM_PRE_ROOT_TOG_MUX_A_SHIFT (24U) |
| #define CCM_PRE_ROOT_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_MUX_A_SHIFT)) & CCM_PRE_ROOT_TOG_MUX_A_MASK) |
| #define CCM_PRE_ROOT_TOG_EN_A_MASK (0x10000000U) |
| #define CCM_PRE_ROOT_TOG_EN_A_SHIFT (28U) |
| /*! EN_A |
| * 0b0..Clock shutdown |
| * 0b1..clock ON |
| */ |
| #define CCM_PRE_ROOT_TOG_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_EN_A_SHIFT)) & CCM_PRE_ROOT_TOG_EN_A_MASK) |
| #define CCM_PRE_ROOT_TOG_BUSY4_MASK (0x80000000U) |
| #define CCM_PRE_ROOT_TOG_BUSY4_SHIFT (31U) |
| #define CCM_PRE_ROOT_TOG_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY4_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY4_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_PRE_ROOT_TOG */ |
| #define CCM_PRE_ROOT_TOG_COUNT (142U) |
| |
| /*! @name ACCESS_CTRL - Access Control Register */ |
| /*! @{ */ |
| #define CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK (0xFU) |
| #define CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT (0U) |
| #define CCM_ACCESS_CTRL_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK) |
| #define CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK (0xF0U) |
| #define CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT (4U) |
| #define CCM_ACCESS_CTRL_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK) |
| #define CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK (0xF00U) |
| #define CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT (8U) |
| #define CCM_ACCESS_CTRL_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK) |
| #define CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK (0xF000U) |
| #define CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT (12U) |
| #define CCM_ACCESS_CTRL_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK) |
| #define CCM_ACCESS_CTRL_OWNER_ID_MASK (0x30000U) |
| #define CCM_ACCESS_CTRL_OWNER_ID_SHIFT (16U) |
| /*! OWNER_ID |
| * 0b00..domaino |
| * 0b01..domain1 |
| * 0b10..domain2 |
| * 0b11..domain3 |
| */ |
| #define CCM_ACCESS_CTRL_OWNER_ID(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_OWNER_ID_MASK) |
| #define CCM_ACCESS_CTRL_MUTEX_MASK (0x100000U) |
| #define CCM_ACCESS_CTRL_MUTEX_SHIFT (20U) |
| /*! MUTEX |
| * 0b0..Semaphore is free to take |
| * 0b1..Semaphore is taken |
| */ |
| #define CCM_ACCESS_CTRL_MUTEX(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_MUTEX_MASK) |
| #define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK (0x1000000U) |
| #define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT (24U) |
| /*! DOMAIN0_WHITELIST |
| * 0b0..Domain cannot change the setting |
| * 0b1..Domain can change the setting |
| */ |
| #define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK) |
| #define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK (0x2000000U) |
| #define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT (25U) |
| /*! DOMAIN1_WHITELIST |
| * 0b0..Domain cannot change the setting |
| * 0b1..Domain can change the setting |
| */ |
| #define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK) |
| #define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK (0x4000000U) |
| #define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT (26U) |
| /*! DOMAIN2_WHITELIST |
| * 0b0..Domain cannot change the setting |
| * 0b1..Domain can change the setting |
| */ |
| #define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK) |
| #define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK (0x8000000U) |
| #define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT (27U) |
| /*! DOMAIN3_WHITELIST |
| * 0b0..Domain cannot change the setting |
| * 0b1..Domain can change the setting |
| */ |
| #define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK) |
| #define CCM_ACCESS_CTRL_SEMA_EN_MASK (0x10000000U) |
| #define CCM_ACCESS_CTRL_SEMA_EN_SHIFT (28U) |
| /*! SEMA_EN |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define CCM_ACCESS_CTRL_SEMA_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_SEMA_EN_MASK) |
| #define CCM_ACCESS_CTRL_LOCK_MASK (0x80000000U) |
| #define CCM_ACCESS_CTRL_LOCK_SHIFT (31U) |
| /*! LOCK |
| * 0b0..Access control inactive |
| * 0b1..Access control active |
| */ |
| #define CCM_ACCESS_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_LOCK_SHIFT)) & CCM_ACCESS_CTRL_LOCK_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_ACCESS_CTRL */ |
| #define CCM_ACCESS_CTRL_COUNT (142U) |
| |
| /*! @name ACCESS_CTRL_ROOT_SET - Access Control Register */ |
| /*! @{ */ |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK (0xFU) |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT (0U) |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK (0xF0U) |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT (4U) |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK (0xF00U) |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT (8U) |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK (0xF000U) |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT (12U) |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK (0x30000U) |
| #define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT (16U) |
| /*! OWNER_ID |
| * 0b00..domaino |
| * 0b01..domain1 |
| * 0b10..domain2 |
| * 0b11..domain3 |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK (0x100000U) |
| #define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT (20U) |
| /*! MUTEX |
| * 0b0..Semaphore is free to take |
| * 0b1..Semaphore is taken |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_SET_MUTEX(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK (0x1000000U) |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT (24U) |
| /*! DOMAIN0_WHITELIST |
| * 0b0..Domain cannot change the setting |
| * 0b1..Domain can change the setting |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK (0x2000000U) |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT (25U) |
| /*! DOMAIN1_WHITELIST |
| * 0b0..Domain cannot change the setting |
| * 0b1..Domain can change the setting |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK (0x4000000U) |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT (26U) |
| /*! DOMAIN2_WHITELIST |
| * 0b0..Domain cannot change the setting |
| * 0b1..Domain can change the setting |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK (0x8000000U) |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT (27U) |
| /*! DOMAIN3_WHITELIST |
| * 0b0..Domain cannot change the setting |
| * 0b1..Domain can change the setting |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK (0x10000000U) |
| #define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT (28U) |
| /*! SEMA_EN |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK (0x80000000U) |
| #define CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT (31U) |
| /*! LOCK |
| * 0b0..Access control inactive |
| * 0b1..Access control active |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_ACCESS_CTRL_ROOT_SET */ |
| #define CCM_ACCESS_CTRL_ROOT_SET_COUNT (142U) |
| |
| /*! @name ACCESS_CTRL_ROOT_CLR - Access Control Register */ |
| /*! @{ */ |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK (0xFU) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT (0U) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK (0xF0U) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT (4U) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK (0xF00U) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT (8U) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK (0xF000U) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT (12U) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK (0x30000U) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT (16U) |
| /*! OWNER_ID |
| * 0b00..domaino |
| * 0b01..domain1 |
| * 0b10..domain2 |
| * 0b11..domain3 |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK (0x100000U) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT (20U) |
| /*! MUTEX |
| * 0b0..Semaphore is free to take |
| * 0b1..Semaphore is taken |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK (0x1000000U) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT (24U) |
| /*! DOMAIN0_WHITELIST |
| * 0b0..Domain cannot change the setting |
| * 0b1..Domain can change the setting |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK (0x2000000U) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT (25U) |
| /*! DOMAIN1_WHITELIST |
| * 0b0..Domain cannot change the setting |
| * 0b1..Domain can change the setting |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK (0x4000000U) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT (26U) |
| /*! DOMAIN2_WHITELIST |
| * 0b0..Domain cannot change the setting |
| * 0b1..Domain can change the setting |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK (0x8000000U) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT (27U) |
| /*! DOMAIN3_WHITELIST |
| * 0b0..Domain cannot change the setting |
| * 0b1..Domain can change the setting |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK (0x10000000U) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT (28U) |
| /*! SEMA_EN |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK (0x80000000U) |
| #define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT (31U) |
| /*! LOCK |
| * 0b0..Access control inactive |
| * 0b1..Access control active |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_ACCESS_CTRL_ROOT_CLR */ |
| #define CCM_ACCESS_CTRL_ROOT_CLR_COUNT (142U) |
| |
| /*! @name ACCESS_CTRL_ROOT_TOG - Access Control Register */ |
| /*! @{ */ |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK (0xFU) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT (0U) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK (0xF0U) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT (4U) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK (0xF00U) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT (8U) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK (0xF000U) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT (12U) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK (0x30000U) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT (16U) |
| /*! OWNER_ID |
| * 0b00..domaino |
| * 0b01..domain1 |
| * 0b10..domain2 |
| * 0b11..domain3 |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK (0x100000U) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT (20U) |
| /*! MUTEX |
| * 0b0..Semaphore is free to take |
| * 0b1..Semaphore is taken |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK (0x1000000U) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT (24U) |
| /*! DOMAIN0_WHITELIST |
| * 0b0..Domain cannot change the setting |
| * 0b1..Domain can change the setting |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK (0x2000000U) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT (25U) |
| /*! DOMAIN1_WHITELIST |
| * 0b0..Domain cannot change the setting |
| * 0b1..Domain can change the setting |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK (0x4000000U) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT (26U) |
| /*! DOMAIN2_WHITELIST |
| * 0b0..Domain cannot change the setting |
| * 0b1..Domain can change the setting |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK (0x8000000U) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT (27U) |
| /*! DOMAIN3_WHITELIST |
| * 0b0..Domain cannot change the setting |
| * 0b1..Domain can change the setting |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK (0x10000000U) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT (28U) |
| /*! SEMA_EN |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK (0x80000000U) |
| #define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT (31U) |
| /*! LOCK |
| * 0b0..Access control inactive |
| * 0b1..Access control active |
| */ |
| #define CCM_ACCESS_CTRL_ROOT_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK) |
| /*! @} */ |
| |
| /* The count of CCM_ACCESS_CTRL_ROOT_TOG */ |
| #define CCM_ACCESS_CTRL_ROOT_TOG_COUNT (142U) |
| |
| |
| /*! |
| * @} |
| */ /* end of group CCM_Register_Masks */ |
| |
| |
| /* CCM - Peripheral instance base addresses */ |
| /** Peripheral CCM base address */ |
| #define CCM_BASE (0x30380000u) |
| /** Peripheral CCM base pointer */ |
| #define CCM ((CCM_Type *)CCM_BASE) |
| /** Array initializer of CCM peripheral base addresses */ |
| #define CCM_BASE_ADDRS { CCM_BASE } |
| /** Array initializer of CCM peripheral base pointers */ |
| #define CCM_BASE_PTRS { CCM } |
| /** Interrupt vectors for the CCM peripheral type */ |
| #define CCM_IRQS { CCM_IRQ1_IRQn, CCM_IRQ2_IRQn } |
| |
| /*! |
| * @} |
| */ /* end of group CCM_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- CCM_ANALOG Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** CCM_ANALOG - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t AUDIO_PLL1_CFG0; /**< AUDIO PLL1 Configuration 0 Register, offset: 0x0 */ |
| __IO uint32_t AUDIO_PLL1_CFG1; /**< AUDIO PLL1 Configuration 1 Register, offset: 0x4 */ |
| __IO uint32_t AUDIO_PLL2_CFG0; /**< AUDIO PLL2 Configuration 0 Register, offset: 0x8 */ |
| __IO uint32_t AUDIO_PLL2_CFG1; /**< AUDIO PLL2 Configuration 1 Register, offset: 0xC */ |
| __IO uint32_t VIDEO_PLL1_CFG0; /**< VIDEO PLL Configuration 0 Register, offset: 0x10 */ |
| __IO uint32_t VIDEO_PLL1_CFG1; /**< VIDEO PLL Configuration 1 Register, offset: 0x14 */ |
| __IO uint32_t GPU_PLL_CFG0; /**< GPU PLL Configuration 0 Register, offset: 0x18 */ |
| __IO uint32_t GPU_PLL_CFG1; /**< GPU PLL Configuration 1 Register, offset: 0x1C */ |
| __IO uint32_t VPU_PLL_CFG0; /**< VPU PLL Configuration 0 Register, offset: 0x20 */ |
| __IO uint32_t VPU_PLL_CFG1; /**< VPU PLL Configuration 1 Register, offset: 0x24 */ |
| __IO uint32_t ARM_PLL_CFG0; /**< ARM PLL Configuration 0 Register, offset: 0x28 */ |
| __IO uint32_t ARM_PLL_CFG1; /**< ARM PLL Configuration 1 Register, offset: 0x2C */ |
| __IO uint32_t SYS_PLL1_CFG0; /**< System PLL Configuration 0 Register, offset: 0x30 */ |
| __IO uint32_t SYS_PLL1_CFG1; /**< System_PLL Configuration 1 Register, offset: 0x34 */ |
| __IO uint32_t SYS_PLL1_CFG2; /**< System_PLL Configuration 2 Register, offset: 0x38 */ |
| __IO uint32_t SYS_PLL2_CFG0; /**< System PLL Configuration 0 Register, offset: 0x3C */ |
| __IO uint32_t SYS_PLL2_CFG1; /**< System_PLL Configuration 1 Register, offset: 0x40 */ |
| __IO uint32_t SYS_PLL2_CFG2; /**< System_PLL Configuration 2 Register, offset: 0x44 */ |
| __IO uint32_t SYS_PLL3_CFG0; /**< System PLL Configuration 0 Register, offset: 0x48 */ |
| __IO uint32_t SYS_PLL3_CFG1; /**< System_PLL Configuration 1 Register, offset: 0x4C */ |
| __IO uint32_t SYS_PLL3_CFG2; /**< System_PLL Configuration 2 Register, offset: 0x50 */ |
| __IO uint32_t VIDEO_PLL2_CFG0; /**< VIDEO PLL2 Configuration 0 Register, offset: 0x54 */ |
| __IO uint32_t VIDEO_PLL2_CFG1; /**< VIDEO PLL2 Configuration 1 Register, offset: 0x58 */ |
| __IO uint32_t VIDEO_PLL2_CFG2; /**< VIDEO PLL2 Configuration 2 Register, offset: 0x5C */ |
| __IO uint32_t DRAM_PLL_CFG0; /**< DRAM PLL Configuration 0 Register, offset: 0x60 */ |
| __IO uint32_t DRAM_PLL_CFG1; /**< DRAM PLL Configuration 1 Register, offset: 0x64 */ |
| __IO uint32_t DRAM_PLL_CFG2; /**< DRAM PLL Configuration 2 Register, offset: 0x68 */ |
| __I uint32_t DIGPROG; /**< DIGPROG Register, offset: 0x6C */ |
| __IO uint32_t OSC_MISC_CFG; /**< Osc Misc Configuration Register, offset: 0x70 */ |
| __IO uint32_t PLLOUT_MONITOR_CFG; /**< PLLOUT Monitor Configuration Register, offset: 0x74 */ |
| __IO uint32_t FRAC_PLLOUT_DIV_CFG; /**< Fractional PLLOUT Divider Configuration Register, offset: 0x78 */ |
| __IO uint32_t SCCG_PLLOUT_DIV_CFG; /**< SCCG PLLOUT Divider Configuration Register, offset: 0x7C */ |
| } CCM_ANALOG_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- CCM_ANALOG Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks |
| * @{ |
| */ |
| |
| /*! @name AUDIO_PLL1_CFG0 - AUDIO PLL1 Configuration 0 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_MASK (0x1FU) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT (0U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_MASK) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_MASK (0x7E0U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_SHIFT (5U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_MASK) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_ACK_MASK (0x800U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_ACK_SHIFT (11U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_ACK_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_ACK_MASK) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_VAL_MASK (0x1000U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_VAL_SHIFT (12U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_VAL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_NEWDIV_VAL_MASK) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_COUNTCLK_SEL_MASK (0x2000U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_COUNTCLK_SEL_SHIFT (13U) |
| /*! PLL_COUNTCLK_SEL |
| * 0b0..25M_REF_CLK |
| * 0b1..27M_REF_CLK |
| */ |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_COUNTCLK_SEL_MASK) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_BYPASS_MASK (0x4000U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_BYPASS_SHIFT (14U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_BYPASS_MASK) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_SEL_MASK (0x8000U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_SEL_SHIFT (15U) |
| /*! PLL_LOCK_SEL |
| * 0b0..Select PLL lock output |
| * 0b1..Select maximum lock time counter output |
| */ |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_SEL_MASK) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_MASK (0x30000U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT (16U) |
| /*! PLL_REFCLK_SEL |
| * 0b00..25M_REF_CLK |
| * 0b01..27M_REF_CLK |
| * 0b10..HDMI_PHY_27M_CLK |
| * 0b11..CLK_P_N |
| */ |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_SEL_MASK) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_OVERRIDE_MASK (0x40000U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_OVERRIDE_SHIFT (18U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_OVERRIDE_MASK) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_MASK (0x80000U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_SHIFT (19U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_MASK) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100000U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_OVERRIDE_SHIFT (20U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_OVERRIDE_MASK) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_MASK (0x200000U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_SHIFT (21U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_MASK) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_MASK (0x80000000U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_SHIFT (31U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_MASK) |
| /*! @} */ |
| |
| /*! @name AUDIO_PLL1_CFG1 - AUDIO PLL1 Configuration 1 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_MASK (0x7FU) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_SHIFT (0U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_INT_DIV_CTL_MASK) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_MASK (0x7FFFFF80U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_SHIFT (7U) |
| #define CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_CFG1_PLL_FRAC_DIV_CTL_MASK) |
| /*! @} */ |
| |
| /*! @name AUDIO_PLL2_CFG0 - AUDIO PLL2 Configuration 0 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_OUTPUT_DIV_VAL_MASK (0x1FU) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT (0U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_OUTPUT_DIV_VAL_MASK) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_DIV_VAL_MASK (0x7E0U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_DIV_VAL_SHIFT (5U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_DIV_VAL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_DIV_VAL_MASK) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_ACK_MASK (0x800U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_ACK_SHIFT (11U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_ACK_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_ACK_MASK) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_VAL_MASK (0x1000U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_VAL_SHIFT (12U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_VAL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_NEWDIV_VAL_MASK) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_COUNTCLK_SEL_MASK (0x2000U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_COUNTCLK_SEL_SHIFT (13U) |
| /*! PLL_COUNTCLK_SEL |
| * 0b0..25M_REF_CLK |
| * 0b1..27M_REF_CLK |
| */ |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_COUNTCLK_SEL_MASK) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_BYPASS_MASK (0x4000U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_BYPASS_SHIFT (14U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_BYPASS_MASK) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_SEL_MASK (0x8000U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_SEL_SHIFT (15U) |
| /*! PLL_LOCK_SEL |
| * 0b0..Select PLL lock output |
| * 0b1..Select maximum lock time counter output |
| */ |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_SEL_MASK) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_SEL_MASK (0x30000U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_SEL_SHIFT (16U) |
| /*! PLL_REFCLK_SEL |
| * 0b00..25M_REF_CLK |
| * 0b01..27M_REF_CLK |
| * 0b10..HDMI_PHY_27M_CLK |
| * 0b11..CLK_P_N |
| */ |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_REFCLK_SEL_MASK) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_OVERRIDE_MASK (0x40000U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_OVERRIDE_SHIFT (18U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_OVERRIDE_MASK) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_MASK (0x80000U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_SHIFT (19U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_MASK) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100000U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_OVERRIDE_SHIFT (20U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_OVERRIDE_MASK) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_MASK (0x200000U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_SHIFT (21U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_MASK) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_MASK (0x80000000U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_SHIFT (31U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_LOCK_MASK) |
| /*! @} */ |
| |
| /*! @name AUDIO_PLL2_CFG1 - AUDIO PLL2 Configuration 1 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_INT_DIV_CTL_MASK (0x7FU) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_INT_DIV_CTL_SHIFT (0U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_INT_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_INT_DIV_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_INT_DIV_CTL_MASK) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_FRAC_DIV_CTL_MASK (0x7FFFFF80U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_FRAC_DIV_CTL_SHIFT (7U) |
| #define CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_FRAC_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_FRAC_DIV_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_CFG1_PLL_FRAC_DIV_CTL_MASK) |
| /*! @} */ |
| |
| /*! @name VIDEO_PLL1_CFG0 - VIDEO PLL Configuration 0 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_MASK (0x1FU) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT (0U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_OUTPUT_DIV_VAL_MASK) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_MASK (0x7E0U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_SHIFT (5U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_DIV_VAL_MASK) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_ACK_MASK (0x800U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_ACK_SHIFT (11U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_ACK_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_ACK_MASK) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_VAL_MASK (0x1000U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_VAL_SHIFT (12U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_VAL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_NEWDIV_VAL_MASK) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_COUNTCLK_SEL_MASK (0x2000U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_COUNTCLK_SEL_SHIFT (13U) |
| /*! PLL_COUNTCLK_SEL |
| * 0b0..25M_REF_CLK |
| * 0b1..27M_REF_CLK |
| */ |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_COUNTCLK_SEL_MASK) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_BYPASS_MASK (0x4000U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_BYPASS_SHIFT (14U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_BYPASS_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_BYPASS_MASK) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_SEL_MASK (0x8000U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_SEL_SHIFT (15U) |
| /*! PLL_LOCK_SEL |
| * 0b0..Select PLL lock output |
| * 0b1..Select maximum lock time counter output |
| */ |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_SEL_MASK) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_SEL_MASK (0x30000U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT (16U) |
| /*! PLL_REFCLK_SEL |
| * 0b00..25M_REF_CLK |
| * 0b01..27M_REF_CLK |
| * 0b10..HDMI_PHY_27M_CLK |
| * 0b11..CLK_P_N |
| */ |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_REFCLK_SEL_MASK) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_OVERRIDE_MASK (0x40000U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_OVERRIDE_SHIFT (18U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_OVERRIDE_MASK) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_MASK (0x80000U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_SHIFT (19U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_MASK) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100000U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_OVERRIDE_SHIFT (20U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_OVERRIDE_MASK) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_MASK (0x200000U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_SHIFT (21U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_MASK) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_MASK (0x80000000U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_SHIFT (31U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_LOCK_MASK) |
| /*! @} */ |
| |
| /*! @name VIDEO_PLL1_CFG1 - VIDEO PLL Configuration 1 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_INT_DIV_CTL_MASK (0x7FU) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_INT_DIV_CTL_SHIFT (0U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_INT_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_INT_DIV_CTL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_INT_DIV_CTL_MASK) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_FRAC_DIV_CTL_MASK (0x7FFFFF80U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_FRAC_DIV_CTL_SHIFT (7U) |
| #define CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_FRAC_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_FRAC_DIV_CTL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_CFG1_PLL_FRAC_DIV_CTL_MASK) |
| /*! @} */ |
| |
| /*! @name GPU_PLL_CFG0 - GPU PLL Configuration 0 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_MASK (0x1FU) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT (0U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_MASK) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_MASK (0x7E0U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_SHIFT (5U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_MASK) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_ACK_MASK (0x800U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_ACK_SHIFT (11U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_ACK_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_ACK_MASK) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_VAL_MASK (0x1000U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_VAL_SHIFT (12U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_VAL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_NEWDIV_VAL_MASK) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_COUNTCLK_SEL_MASK (0x2000U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT (13U) |
| /*! PLL_COUNTCLK_SEL |
| * 0b0..25M_REF_CLK |
| * 0b1..27M_REF_CLK |
| */ |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_COUNTCLK_SEL_MASK) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_BYPASS_MASK (0x4000U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_BYPASS_SHIFT (14U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_BYPASS_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_BYPASS_MASK) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_SEL_MASK (0x8000U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_SEL_SHIFT (15U) |
| /*! PLL_LOCK_SEL |
| * 0b0..Select PLL lock output |
| * 0b1..Select maximum lock time counter output |
| */ |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_SEL_MASK) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_SEL_MASK (0x30000U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_SEL_SHIFT (16U) |
| /*! PLL_REFCLK_SEL |
| * 0b00..25M_REF_CLK |
| * 0b01..27M_REF_CLK |
| * 0b10..HDMI_PHY_27M_CLK |
| * 0b11..CLK_P_N |
| */ |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_REFCLK_SEL_MASK) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_OVERRIDE_MASK (0x40000U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT (18U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_OVERRIDE_MASK) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_MASK (0x80000U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_SHIFT (19U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_MASK) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100000U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT (20U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_MASK (0x200000U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_SHIFT (21U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_MASK) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_MASK (0x80000000U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_SHIFT (31U) |
| #define CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG0_PLL_LOCK_MASK) |
| /*! @} */ |
| |
| /*! @name GPU_PLL_CFG1 - GPU PLL Configuration 1 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_GPU_PLL_CFG1_PLL_INT_DIV_CTL_MASK (0x7FU) |
| #define CCM_ANALOG_GPU_PLL_CFG1_PLL_INT_DIV_CTL_SHIFT (0U) |
| #define CCM_ANALOG_GPU_PLL_CFG1_PLL_INT_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG1_PLL_INT_DIV_CTL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG1_PLL_INT_DIV_CTL_MASK) |
| #define CCM_ANALOG_GPU_PLL_CFG1_PLL_FRAC_DIV_CTL_MASK (0x7FFFFF80U) |
| #define CCM_ANALOG_GPU_PLL_CFG1_PLL_FRAC_DIV_CTL_SHIFT (7U) |
| #define CCM_ANALOG_GPU_PLL_CFG1_PLL_FRAC_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_CFG1_PLL_FRAC_DIV_CTL_SHIFT)) & CCM_ANALOG_GPU_PLL_CFG1_PLL_FRAC_DIV_CTL_MASK) |
| /*! @} */ |
| |
| /*! @name VPU_PLL_CFG0 - VPU PLL Configuration 0 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_MASK (0x1FU) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT (0U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_OUTPUT_DIV_VAL_MASK) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_MASK (0x7E0U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_SHIFT (5U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_DIV_VAL_MASK) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_ACK_MASK (0x800U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_ACK_SHIFT (11U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_ACK_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_ACK_MASK) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_VAL_MASK (0x1000U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_VAL_SHIFT (12U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_VAL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_NEWDIV_VAL_MASK) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_COUNTCLK_SEL_MASK (0x2000U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT (13U) |
| /*! PLL_COUNTCLK_SEL |
| * 0b0..25M_REF_CLK |
| * 0b1..27M_REF_CLK |
| */ |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_COUNTCLK_SEL_MASK) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_BYPASS_MASK (0x4000U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_BYPASS_SHIFT (14U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_BYPASS_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_BYPASS_MASK) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_SEL_MASK (0x8000U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_SEL_SHIFT (15U) |
| /*! PLL_LOCK_SEL |
| * 0b0..Select PLL lock output |
| * 0b1..Select maximum lock time counter output |
| */ |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_SEL_MASK) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_SEL_MASK (0x30000U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_SEL_SHIFT (16U) |
| /*! PLL_REFCLK_SEL |
| * 0b00..25M_REF_CLK |
| * 0b01..27M_REF_CLK |
| * 0b10..HDMI_PHY_27M_CLK |
| * 0b11..CLK_P_N |
| */ |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_REFCLK_SEL_MASK) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_OVERRIDE_MASK (0x40000U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT (18U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_OVERRIDE_MASK) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_MASK (0x80000U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_SHIFT (19U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_MASK) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100000U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT (20U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_MASK (0x200000U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_SHIFT (21U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_MASK) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_MASK (0x80000000U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_SHIFT (31U) |
| #define CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG0_PLL_LOCK_MASK) |
| /*! @} */ |
| |
| /*! @name VPU_PLL_CFG1 - VPU PLL Configuration 1 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_VPU_PLL_CFG1_PLL_INT_DIV_CTL_MASK (0x7FU) |
| #define CCM_ANALOG_VPU_PLL_CFG1_PLL_INT_DIV_CTL_SHIFT (0U) |
| #define CCM_ANALOG_VPU_PLL_CFG1_PLL_INT_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG1_PLL_INT_DIV_CTL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG1_PLL_INT_DIV_CTL_MASK) |
| #define CCM_ANALOG_VPU_PLL_CFG1_PLL_FRAC_DIV_CTL_MASK (0x7FFFFF80U) |
| #define CCM_ANALOG_VPU_PLL_CFG1_PLL_FRAC_DIV_CTL_SHIFT (7U) |
| #define CCM_ANALOG_VPU_PLL_CFG1_PLL_FRAC_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_CFG1_PLL_FRAC_DIV_CTL_SHIFT)) & CCM_ANALOG_VPU_PLL_CFG1_PLL_FRAC_DIV_CTL_MASK) |
| /*! @} */ |
| |
| /*! @name ARM_PLL_CFG0 - ARM PLL Configuration 0 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_OUTPUT_DIV_VAL_MASK (0x1FU) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT (0U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_OUTPUT_DIV_VAL_MASK) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_DIV_VAL_MASK (0x7E0U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_DIV_VAL_SHIFT (5U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_DIV_VAL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_DIV_VAL_MASK) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_ACK_MASK (0x800U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_ACK_SHIFT (11U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_ACK_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_ACK_MASK) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_VAL_MASK (0x1000U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_VAL_SHIFT (12U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_VAL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_NEWDIV_VAL_MASK) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_COUNTCLK_SEL_MASK (0x2000U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT (13U) |
| /*! PLL_COUNTCLK_SEL |
| * 0b0..25M_REF_CLK |
| * 0b1..27M_REF_CLK |
| */ |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_COUNTCLK_SEL_MASK) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_BYPASS_MASK (0x4000U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_BYPASS_SHIFT (14U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_BYPASS_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_BYPASS_MASK) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_SEL_MASK (0x8000U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_SEL_SHIFT (15U) |
| /*! PLL_LOCK_SEL |
| * 0b0..Select PLL lock output |
| * 0b1..Select maximum lock time counter output |
| */ |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_SEL_MASK) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_SEL_MASK (0x30000U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_SEL_SHIFT (16U) |
| /*! PLL_REFCLK_SEL |
| * 0b00..25M_REF_CLK |
| * 0b01..27M_REF_CLK |
| * 0b10..HDMI_PHY_27M_CLK |
| * 0b11..CLK_P_N |
| */ |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_REFCLK_SEL_MASK) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_OVERRIDE_MASK (0x40000U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT (18U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_OVERRIDE_MASK) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_MASK (0x80000U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_SHIFT (19U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_MASK) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100000U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT (20U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_MASK (0x200000U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_SHIFT (21U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_MASK) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_MASK (0x80000000U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_SHIFT (31U) |
| #define CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG0_PLL_LOCK_MASK) |
| /*! @} */ |
| |
| /*! @name ARM_PLL_CFG1 - ARM PLL Configuration 1 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_ARM_PLL_CFG1_PLL_INT_DIV_CTL_MASK (0x7FU) |
| #define CCM_ANALOG_ARM_PLL_CFG1_PLL_INT_DIV_CTL_SHIFT (0U) |
| #define CCM_ANALOG_ARM_PLL_CFG1_PLL_INT_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG1_PLL_INT_DIV_CTL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG1_PLL_INT_DIV_CTL_MASK) |
| #define CCM_ANALOG_ARM_PLL_CFG1_PLL_FRAC_DIV_CTL_MASK (0x7FFFFF80U) |
| #define CCM_ANALOG_ARM_PLL_CFG1_PLL_FRAC_DIV_CTL_SHIFT (7U) |
| #define CCM_ANALOG_ARM_PLL_CFG1_PLL_FRAC_DIV_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_CFG1_PLL_FRAC_DIV_CTL_SHIFT)) & CCM_ANALOG_ARM_PLL_CFG1_PLL_FRAC_DIV_CTL_MASK) |
| /*! @} */ |
| |
| /*! @name SYS_PLL1_CFG0 - System PLL Configuration 0 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_MASK (0x3U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT (0U) |
| /*! PLL_REFCLK_SEL |
| * 0b00..25M_REF_CLK |
| * 0b01..27M_REF_CLK |
| * 0b10..HDMI_PHY_27M_CLK |
| * 0b11..CLK_P_N |
| */ |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_REFCLK_SEL_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_COUNTCLK_SEL_MASK (0x4U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_COUNTCLK_SEL_SHIFT (2U) |
| /*! PLL_COUNTCLK_SEL |
| * 0b0..25M_REF_CLK |
| * 0b1..27M_REF_CLK |
| */ |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_COUNTCLK_SEL_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_SEL_MASK (0x8U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_SEL_SHIFT (3U) |
| /*! PLL_LOCK_SEL |
| * 0b0..Select PLL lock output |
| * 0b1..Select maximum lock time counter output |
| */ |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_SEL_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS2_MASK (0x10U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS2_SHIFT (4U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS2_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS2_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1_MASK (0x20U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1_SHIFT (5U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_OVERRIDE_MASK (0x40U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_OVERRIDE_SHIFT (6U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_MASK (0x80U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_SHIFT (7U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_OVERRIDE_MASK (0x100U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_OVERRIDE_SHIFT (8U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_CLKE_MASK (0x200U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_CLKE_SHIFT (9U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_OVERRIDE_MASK (0x400U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_OVERRIDE_SHIFT (10U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_CLKE_MASK (0x800U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_CLKE_SHIFT (11U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_OVERRIDE_MASK (0x1000U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_OVERRIDE_SHIFT (12U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_CLKE_MASK (0x2000U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_CLKE_SHIFT (13U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_OVERRIDE_MASK (0x4000U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_OVERRIDE_SHIFT (14U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_CLKE_MASK (0x8000U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_CLKE_SHIFT (15U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_OVERRIDE_MASK (0x10000U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_OVERRIDE_SHIFT (16U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_CLKE_MASK (0x20000U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_CLKE_SHIFT (17U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_OVERRIDE_MASK (0x40000U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_OVERRIDE_SHIFT (18U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_CLKE_MASK (0x80000U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_CLKE_SHIFT (19U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_OVERRIDE_MASK (0x100000U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_OVERRIDE_SHIFT (20U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_CLKE_MASK (0x200000U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_CLKE_SHIFT (21U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_OVERRIDE_MASK (0x400000U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_OVERRIDE_SHIFT (22U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_CLKE_MASK (0x800000U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_CLKE_SHIFT (23U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_OVERRIDE_MASK (0x1000000U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_OVERRIDE_SHIFT (24U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_MASK (0x2000000U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_SHIFT (25U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_MASK (0x80000000U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_SHIFT (31U) |
| #define CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG0_PLL_LOCK_MASK) |
| /*! @} */ |
| |
| /*! @name SYS_PLL1_CFG1 - System_PLL Configuration 1 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSE_MASK (0x1U) |
| #define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSE_SHIFT (0U) |
| #define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSE_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMF_MASK (0x1EU) |
| #define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMF_SHIFT (1U) |
| #define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMF_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMF_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMD_MASK (0xE0U) |
| #define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMD_SHIFT (5U) |
| /*! PLL_SSMD |
| * 0b000..0.25 |
| * 0b001..0.5 |
| * 0b010..0.75 |
| * 0b011..1.0 |
| * 0b100..1.5 |
| * 0b101..2.0 |
| * 0b110..3.0 |
| * 0b111..4.0 |
| */ |
| #define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMD_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSMD_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSDS_MASK (0x100U) |
| #define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSDS_SHIFT (8U) |
| /*! PLL_SSDS |
| * 0b0..Center Spread |
| * 0b1..Down Spread |
| */ |
| #define CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSDS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSDS_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG1_PLL_SSDS_MASK) |
| /*! @} */ |
| |
| /*! @name SYS_PLL1_CFG2 - System_PLL Configuration 2 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FILTER_RANGE_MASK (0x1U) |
| #define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FILTER_RANGE_SHIFT (0U) |
| /*! PLL_FILTER_RANGE |
| * 0b0..25 to 35 MHz |
| * 0b1..35 to 54 MHz |
| */ |
| #define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FILTER_RANGE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG2_PLL_FILTER_RANGE_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG2_PLL_FILTER_RANGE_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_MASK (0x7EU) |
| #define CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT (1U) |
| #define CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG2_PLL_OUTPUT_DIV_VAL_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_MASK (0x1F80U) |
| #define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_SHIFT (7U) |
| #define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF2_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_MASK (0x7E000U) |
| #define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_SHIFT (13U) |
| #define CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG2_PLL_FEEDBACK_DIVF1_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_MASK (0x1F80000U) |
| #define CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_SHIFT (19U) |
| #define CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR2_MASK) |
| #define CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_MASK (0xE000000U) |
| #define CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_SHIFT (25U) |
| #define CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_SHIFT)) & CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_MASK) |
| /*! @} */ |
| |
| /*! @name SYS_PLL2_CFG0 - System PLL Configuration 0 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_REFCLK_SEL_MASK (0x3U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_REFCLK_SEL_SHIFT (0U) |
| /*! PLL_REFCLK_SEL |
| * 0b00..25M_REF_CLK |
| * 0b01..27M_REF_CLK |
| * 0b10..HDMI_PHY_27M_CLK |
| * 0b11..CLK_P_N |
| */ |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_REFCLK_SEL_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_COUNTCLK_SEL_MASK (0x4U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_COUNTCLK_SEL_SHIFT (2U) |
| /*! PLL_COUNTCLK_SEL |
| * 0b0..25M_REF_CLK |
| * 0b1..27M_REF_CLK |
| */ |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_COUNTCLK_SEL_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_SEL_MASK (0x8U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_SEL_SHIFT (3U) |
| /*! PLL_LOCK_SEL |
| * 0b0..Select PLL lock output |
| * 0b1..Select maximum lock time counter output |
| */ |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_SEL_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS2_MASK (0x10U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS2_SHIFT (4U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS2_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS2_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS1_MASK (0x20U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS1_SHIFT (5U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS1_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS1_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_OVERRIDE_MASK (0x40U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_OVERRIDE_SHIFT (6U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_MASK (0x80U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_SHIFT (7U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_OVERRIDE_MASK (0x100U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_OVERRIDE_SHIFT (8U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_CLKE_MASK (0x200U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_CLKE_SHIFT (9U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_OVERRIDE_MASK (0x400U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_OVERRIDE_SHIFT (10U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_CLKE_MASK (0x800U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_CLKE_SHIFT (11U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_OVERRIDE_MASK (0x1000U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_OVERRIDE_SHIFT (12U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_CLKE_MASK (0x2000U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_CLKE_SHIFT (13U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_OVERRIDE_MASK (0x4000U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_OVERRIDE_SHIFT (14U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_CLKE_MASK (0x8000U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_CLKE_SHIFT (15U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_OVERRIDE_MASK (0x10000U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_OVERRIDE_SHIFT (16U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_CLKE_MASK (0x20000U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_CLKE_SHIFT (17U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_OVERRIDE_MASK (0x40000U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_OVERRIDE_SHIFT (18U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_CLKE_MASK (0x80000U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_CLKE_SHIFT (19U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_OVERRIDE_MASK (0x100000U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_OVERRIDE_SHIFT (20U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_CLKE_MASK (0x200000U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_CLKE_SHIFT (21U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_OVERRIDE_MASK (0x400000U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_OVERRIDE_SHIFT (22U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_CLKE_MASK (0x800000U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_CLKE_SHIFT (23U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_OVERRIDE_MASK (0x1000000U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_OVERRIDE_SHIFT (24U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_MASK (0x2000000U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_SHIFT (25U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_MASK (0x80000000U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_SHIFT (31U) |
| #define CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG0_PLL_LOCK_MASK) |
| /*! @} */ |
| |
| /*! @name SYS_PLL2_CFG1 - System_PLL Configuration 1 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSE_MASK (0x1U) |
| #define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSE_SHIFT (0U) |
| #define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSE_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMF_MASK (0x1EU) |
| #define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMF_SHIFT (1U) |
| #define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMF_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMF_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMD_MASK (0xE0U) |
| #define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMD_SHIFT (5U) |
| /*! PLL_SSMD |
| * 0b000..0.25 |
| * 0b001..0.5 |
| * 0b010..0.75 |
| * 0b011..1.0 |
| * 0b100..1.5 |
| * 0b101..2.0 |
| * 0b110..3.0 |
| * 0b111..4.0 |
| */ |
| #define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMD_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSMD_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSDS_MASK (0x100U) |
| #define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSDS_SHIFT (8U) |
| /*! PLL_SSDS |
| * 0b0..Center Spread |
| * 0b1..Down Spread |
| */ |
| #define CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSDS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSDS_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG1_PLL_SSDS_MASK) |
| /*! @} */ |
| |
| /*! @name SYS_PLL2_CFG2 - System_PLL Configuration 2 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FILTER_RANGE_MASK (0x1U) |
| #define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FILTER_RANGE_SHIFT (0U) |
| /*! PLL_FILTER_RANGE |
| * 0b0..25 to 35 MHz |
| * 0b1..35 to 54 MHz |
| */ |
| #define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FILTER_RANGE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG2_PLL_FILTER_RANGE_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG2_PLL_FILTER_RANGE_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_MASK (0x7EU) |
| #define CCM_ANALOG_SYS_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT (1U) |
| #define CCM_ANALOG_SYS_PLL2_CFG2_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF2_MASK (0x1F80U) |
| #define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF2_SHIFT (7U) |
| #define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF2_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF2_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF1_MASK (0x7E000U) |
| #define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF1_SHIFT (13U) |
| #define CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF1_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG2_PLL_FEEDBACK_DIVF1_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR2_MASK (0x1F80000U) |
| #define CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR2_SHIFT (19U) |
| #define CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR2_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR2_MASK) |
| #define CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR1_MASK (0xE000000U) |
| #define CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR1_SHIFT (25U) |
| #define CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR1_SHIFT)) & CCM_ANALOG_SYS_PLL2_CFG2_PLL_REF_DIVR1_MASK) |
| /*! @} */ |
| |
| /*! @name SYS_PLL3_CFG0 - System PLL Configuration 0 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_REFCLK_SEL_MASK (0x3U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_REFCLK_SEL_SHIFT (0U) |
| /*! PLL_REFCLK_SEL |
| * 0b00..25M_REF_CLK |
| * 0b01..27M_REF_CLK |
| * 0b10..HDMI_PHY_27M_CLK |
| * 0b11..CLK_P_N |
| */ |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_REFCLK_SEL_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_COUNTCLK_SEL_MASK (0x4U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_COUNTCLK_SEL_SHIFT (2U) |
| /*! PLL_COUNTCLK_SEL |
| * 0b0..25M_REF_CLK |
| * 0b1..27M_REF_CLK |
| */ |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_COUNTCLK_SEL_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_SEL_MASK (0x8U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_SEL_SHIFT (3U) |
| /*! PLL_LOCK_SEL |
| * 0b0..Select PLL lock output |
| * 0b1..Select maximum lock time counter output |
| */ |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_SEL_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS2_MASK (0x10U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS2_SHIFT (4U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS2_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS2_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS1_MASK (0x20U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS1_SHIFT (5U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS1_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS1_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_OVERRIDE_MASK (0x40U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_OVERRIDE_SHIFT (6U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_MASK (0x80U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_SHIFT (7U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_OVERRIDE_MASK (0x100U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_OVERRIDE_SHIFT (8U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_CLKE_MASK (0x200U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_CLKE_SHIFT (9U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV20_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_OVERRIDE_MASK (0x400U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_OVERRIDE_SHIFT (10U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_CLKE_MASK (0x800U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_CLKE_SHIFT (11U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV10_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_OVERRIDE_MASK (0x1000U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_OVERRIDE_SHIFT (12U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_CLKE_MASK (0x2000U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_CLKE_SHIFT (13U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV8_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_OVERRIDE_MASK (0x4000U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_OVERRIDE_SHIFT (14U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_CLKE_MASK (0x8000U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_CLKE_SHIFT (15U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV6_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_OVERRIDE_MASK (0x10000U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_OVERRIDE_SHIFT (16U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_CLKE_MASK (0x20000U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_CLKE_SHIFT (17U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV5_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_OVERRIDE_MASK (0x40000U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_OVERRIDE_SHIFT (18U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_CLKE_MASK (0x80000U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_CLKE_SHIFT (19U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV4_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_OVERRIDE_MASK (0x100000U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_OVERRIDE_SHIFT (20U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_CLKE_MASK (0x200000U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_CLKE_SHIFT (21U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV3_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_OVERRIDE_MASK (0x400000U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_OVERRIDE_SHIFT (22U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_CLKE_MASK (0x800000U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_CLKE_SHIFT (23U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_DIV2_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_OVERRIDE_MASK (0x1000000U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_OVERRIDE_SHIFT (24U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_OVERRIDE_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_MASK (0x2000000U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_SHIFT (25U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_MASK (0x80000000U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_SHIFT (31U) |
| #define CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG0_PLL_LOCK_MASK) |
| /*! @} */ |
| |
| /*! @name SYS_PLL3_CFG1 - System_PLL Configuration 1 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSE_MASK (0x1U) |
| #define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSE_SHIFT (0U) |
| #define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSE_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMF_MASK (0x1EU) |
| #define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMF_SHIFT (1U) |
| #define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMF_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMF_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMD_MASK (0xE0U) |
| #define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMD_SHIFT (5U) |
| /*! PLL_SSMD |
| * 0b000..0.25 |
| * 0b001..0.5 |
| * 0b010..0.75 |
| * 0b011..1.0 |
| * 0b100..1.5 |
| * 0b101..2.0 |
| * 0b110..3.0 |
| * 0b111..4.0 |
| */ |
| #define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMD_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSMD_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSDS_MASK (0x100U) |
| #define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSDS_SHIFT (8U) |
| /*! PLL_SSDS |
| * 0b0..Center Spread |
| * 0b1..Down Spread |
| */ |
| #define CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSDS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSDS_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG1_PLL_SSDS_MASK) |
| /*! @} */ |
| |
| /*! @name SYS_PLL3_CFG2 - System_PLL Configuration 2 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FILTER_RANGE_MASK (0x1U) |
| #define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FILTER_RANGE_SHIFT (0U) |
| /*! PLL_FILTER_RANGE |
| * 0b0..25 to 35 MHz |
| * 0b1..35 to 54 MHz |
| */ |
| #define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FILTER_RANGE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG2_PLL_FILTER_RANGE_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG2_PLL_FILTER_RANGE_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG2_PLL_OUTPUT_DIV_VAL_MASK (0x7EU) |
| #define CCM_ANALOG_SYS_PLL3_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT (1U) |
| #define CCM_ANALOG_SYS_PLL3_CFG2_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG2_PLL_OUTPUT_DIV_VAL_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF2_MASK (0x1F80U) |
| #define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF2_SHIFT (7U) |
| #define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF2_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF2_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF1_MASK (0x7E000U) |
| #define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF1_SHIFT (13U) |
| #define CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF1_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG2_PLL_FEEDBACK_DIVF1_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR2_MASK (0x1F80000U) |
| #define CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR2_SHIFT (19U) |
| #define CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR2_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR2_MASK) |
| #define CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR1_MASK (0xE000000U) |
| #define CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR1_SHIFT (25U) |
| #define CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR1_SHIFT)) & CCM_ANALOG_SYS_PLL3_CFG2_PLL_REF_DIVR1_MASK) |
| /*! @} */ |
| |
| /*! @name VIDEO_PLL2_CFG0 - VIDEO PLL2 Configuration 0 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_REFCLK_SEL_MASK (0x3U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_REFCLK_SEL_SHIFT (0U) |
| /*! PLL_REFCLK_SEL |
| * 0b00..25M_REF_CLK |
| * 0b01..27M_REF_CLK |
| * 0b10..HDMI_PHY_27M_CLK |
| * 0b11..CLK_P_N |
| */ |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_REFCLK_SEL_MASK) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_COUNTCLK_SEL_MASK (0x4U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_COUNTCLK_SEL_SHIFT (2U) |
| /*! PLL_COUNTCLK_SEL |
| * 0b0..25M_REF_CLK |
| * 0b1..27M_REF_CLK |
| */ |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_COUNTCLK_SEL_MASK) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_SEL_MASK (0x8U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_SEL_SHIFT (3U) |
| /*! PLL_LOCK_SEL |
| * 0b0..Select PLL lock output |
| * 0b1..Select maximum lock time counter output |
| */ |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_SEL_MASK) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS2_MASK (0x10U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS2_SHIFT (4U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS2_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS2_MASK) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS1_MASK (0x20U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS1_SHIFT (5U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS1_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS1_MASK) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_OVERRIDE_MASK (0x40U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_OVERRIDE_SHIFT (6U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_OVERRIDE_MASK) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_MASK (0x80U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_SHIFT (7U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_MASK) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_OVERRIDE_SHIFT (8U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_OVERRIDE_MASK) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_MASK (0x200U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_SHIFT (9U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_MASK) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_MASK (0x80000000U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_SHIFT (31U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_LOCK_MASK) |
| /*! @} */ |
| |
| /*! @name VIDEO_PLL2_CFG1 - VIDEO PLL2 Configuration 1 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSE_MASK (0x1U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSE_SHIFT (0U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSE_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSE_MASK) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMF_MASK (0x1EU) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMF_SHIFT (1U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMF_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMF_MASK) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMD_MASK (0xE0U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMD_SHIFT (5U) |
| /*! PLL_SSMD |
| * 0b000..0.25 |
| * 0b001..0.5 |
| * 0b010..0.75 |
| * 0b011..1.0 |
| * 0b100..1.5 |
| * 0b101..2.0 |
| * 0b110..3.0 |
| * 0b111..4.0 |
| */ |
| #define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMD_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSMD_MASK) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSDS_MASK (0x100U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSDS_SHIFT (8U) |
| /*! PLL_SSDS |
| * 0b0..Center Spread |
| * 0b1..Down Spread |
| */ |
| #define CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSDS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSDS_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG1_PLL_SSDS_MASK) |
| /*! @} */ |
| |
| /*! @name VIDEO_PLL2_CFG2 - VIDEO PLL2 Configuration 2 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FILTER_RANGE_MASK (0x1U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FILTER_RANGE_SHIFT (0U) |
| /*! PLL_FILTER_RANGE |
| * 0b0..25 to 35 MHz |
| * 0b1..35 to 54 MHz |
| */ |
| #define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FILTER_RANGE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FILTER_RANGE_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FILTER_RANGE_MASK) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_MASK (0x7EU) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT (1U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_OUTPUT_DIV_VAL_MASK) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF2_MASK (0x1F80U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF2_SHIFT (7U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF2_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF2_MASK) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF1_MASK (0x7E000U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF1_SHIFT (13U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF1_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_FEEDBACK_DIVF1_MASK) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR2_MASK (0x1F80000U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR2_SHIFT (19U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR2_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR2_MASK) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR1_MASK (0xE000000U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR1_SHIFT (25U) |
| #define CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR1_SHIFT)) & CCM_ANALOG_VIDEO_PLL2_CFG2_PLL_REF_DIVR1_MASK) |
| /*! @} */ |
| |
| /*! @name DRAM_PLL_CFG0 - DRAM PLL Configuration 0 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_REFCLK_SEL_MASK (0x3U) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_REFCLK_SEL_SHIFT (0U) |
| /*! PLL_REFCLK_SEL |
| * 0b00..25M_REF_CLK |
| * 0b01..27M_REF_CLK |
| * 0b10..HDMI_PHY_27M_CLK |
| * 0b11..CLK_P_N |
| */ |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_REFCLK_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_REFCLK_SEL_MASK) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_COUNTCLK_SEL_MASK (0x4U) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT (2U) |
| /*! PLL_COUNTCLK_SEL |
| * 0b0..25M_REF_CLK |
| * 0b1..27M_REF_CLK |
| */ |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_COUNTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_COUNTCLK_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_COUNTCLK_SEL_MASK) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_SEL_MASK (0x8U) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_SEL_SHIFT (3U) |
| /*! PLL_LOCK_SEL |
| * 0b0..Select PLL lock output |
| * 0b1..Select maximum lock time counter output |
| */ |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_SEL_MASK) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS2_MASK (0x10U) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS2_SHIFT (4U) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS2_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS2_MASK) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS1_MASK (0x20U) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS1_SHIFT (5U) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS1_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS1_MASK) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_OVERRIDE_MASK (0x40U) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT (6U) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_OVERRIDE_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_OVERRIDE_MASK) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_MASK (0x80U) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_SHIFT (7U) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_MASK) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK (0x100U) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT (8U) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_OVERRIDE_MASK) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_MASK (0x200U) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_SHIFT (9U) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_MASK) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_MASK (0x80000000U) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_SHIFT (31U) |
| #define CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG0_PLL_LOCK_MASK) |
| /*! @} */ |
| |
| /*! @name DRAM_PLL_CFG1 - DRAM PLL Configuration 1 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSE_MASK (0x1U) |
| #define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSE_SHIFT (0U) |
| #define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSE_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSE_MASK) |
| #define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMF_MASK (0x1EU) |
| #define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMF_SHIFT (1U) |
| #define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMF_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMF_MASK) |
| #define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMD_MASK (0xE0U) |
| #define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMD_SHIFT (5U) |
| /*! PLL_SSMD |
| * 0b000..0.25 |
| * 0b001..0.5 |
| * 0b010..0.75 |
| * 0b011..1.0 |
| * 0b100..1.5 |
| * 0b101..2.0 |
| * 0b110..3.0 |
| * 0b111..4.0 |
| */ |
| #define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMD_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSMD_MASK) |
| #define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSDS_MASK (0x100U) |
| #define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSDS_SHIFT (8U) |
| /*! PLL_SSDS |
| * 0b0..Center Spread |
| * 0b1..Down Spread |
| */ |
| #define CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSDS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSDS_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG1_PLL_SSDS_MASK) |
| /*! @} */ |
| |
| /*! @name DRAM_PLL_CFG2 - DRAM PLL Configuration 2 Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FILTER_RANGE_MASK (0x1U) |
| #define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FILTER_RANGE_SHIFT (0U) |
| /*! PLL_FILTER_RANGE |
| * 0b0..25 to 35 MHz |
| * 0b1..35 to 54 MHz |
| */ |
| #define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FILTER_RANGE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG2_PLL_FILTER_RANGE_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG2_PLL_FILTER_RANGE_MASK) |
| #define CCM_ANALOG_DRAM_PLL_CFG2_PLL_OUTPUT_DIV_VAL_MASK (0x7EU) |
| #define CCM_ANALOG_DRAM_PLL_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT (1U) |
| #define CCM_ANALOG_DRAM_PLL_CFG2_PLL_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG2_PLL_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG2_PLL_OUTPUT_DIV_VAL_MASK) |
| #define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF2_MASK (0x1F80U) |
| #define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF2_SHIFT (7U) |
| #define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF2_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF2_MASK) |
| #define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF1_MASK (0x7E000U) |
| #define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF1_SHIFT (13U) |
| #define CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF1_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG2_PLL_FEEDBACK_DIVF1_MASK) |
| #define CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR2_MASK (0x1F80000U) |
| #define CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR2_SHIFT (19U) |
| #define CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR2(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR2_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR2_MASK) |
| #define CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR1_MASK (0xE000000U) |
| #define CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR1_SHIFT (25U) |
| #define CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR1(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR1_SHIFT)) & CCM_ANALOG_DRAM_PLL_CFG2_PLL_REF_DIVR1_MASK) |
| /*! @} */ |
| |
| /*! @name DIGPROG - DIGPROG Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_DIGPROG_DIGPROG_MINOR_MASK (0xFFU) |
| #define CCM_ANALOG_DIGPROG_DIGPROG_MINOR_SHIFT (0U) |
| #define CCM_ANALOG_DIGPROG_DIGPROG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MINOR_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MINOR_MASK) |
| #define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_MASK (0xFF00U) |
| #define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_SHIFT (8U) |
| #define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_MASK) |
| #define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_MASK (0xFF0000U) |
| #define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_SHIFT (16U) |
| #define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_MASK) |
| /*! @} */ |
| |
| /*! @name OSC_MISC_CFG - Osc Misc Configuration Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK (0x1U) |
| #define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_SHIFT (0U) |
| /*! OSC_32K_SEL |
| * 0b0..25M_REF_CLK_DIV800 |
| * 0b1..RTC |
| */ |
| #define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_SHIFT)) & CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK) |
| #define CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_OVERRIDE_MASK (0x2U) |
| #define CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_OVERRIDE_SHIFT (1U) |
| #define CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_OVERRIDE_MASK) |
| #define CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_MASK (0x4U) |
| #define CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_SHIFT (2U) |
| #define CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_SHIFT)) & CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_MASK) |
| #define CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_OVERRIDE_MASK (0x8U) |
| #define CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_OVERRIDE_SHIFT (3U) |
| #define CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_OVERRIDE_MASK) |
| #define CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_MASK (0x10U) |
| #define CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_SHIFT (4U) |
| #define CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_SHIFT)) & CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_MASK) |
| /*! @} */ |
| |
| /*! @name PLLOUT_MONITOR_CFG - PLLOUT Monitor Configuration Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CLK_SEL_MASK (0xFU) |
| #define CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CLK_SEL_SHIFT (0U) |
| #define CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CLK_SEL_SHIFT)) & CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CLK_SEL_MASK) |
| #define CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CKE_MASK (0x10U) |
| #define CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CKE_SHIFT (4U) |
| #define CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CKE_SHIFT)) & CCM_ANALOG_PLLOUT_MONITOR_CFG_PLLOUT_MONITOR_CKE_MASK) |
| /*! @} */ |
| |
| /*! @name FRAC_PLLOUT_DIV_CFG - Fractional PLLOUT Divider Configuration Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL1_DIV_VAL_MASK (0x7U) |
| #define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL1_DIV_VAL_SHIFT (0U) |
| /*! AUDIO_PLL1_DIV_VAL |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL1_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL1_DIV_VAL_SHIFT)) & CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL1_DIV_VAL_MASK) |
| #define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL2_DIV_VAL_MASK (0x70U) |
| #define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL2_DIV_VAL_SHIFT (4U) |
| /*! AUDIO_PLL2_DIV_VAL |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL2_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL2_DIV_VAL_SHIFT)) & CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_AUDIO_PLL2_DIV_VAL_MASK) |
| #define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VIDEO_PLL1_DIV_VAL_MASK (0x700U) |
| #define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VIDEO_PLL1_DIV_VAL_SHIFT (8U) |
| /*! VIDEO_PLL1_DIV_VAL |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VIDEO_PLL1_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VIDEO_PLL1_DIV_VAL_SHIFT)) & CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VIDEO_PLL1_DIV_VAL_MASK) |
| #define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_GPU_PLL_DIV_VAL_MASK (0x7000U) |
| #define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_GPU_PLL_DIV_VAL_SHIFT (12U) |
| /*! GPU_PLL_DIV_VAL |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_GPU_PLL_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_GPU_PLL_DIV_VAL_SHIFT)) & CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_GPU_PLL_DIV_VAL_MASK) |
| #define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VPU_PLL_DIV_VAL_MASK (0x70000U) |
| #define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VPU_PLL_DIV_VAL_SHIFT (16U) |
| /*! VPU_PLL_DIV_VAL |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VPU_PLL_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VPU_PLL_DIV_VAL_SHIFT)) & CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_VPU_PLL_DIV_VAL_MASK) |
| #define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_ARM_PLL_DIV_VAL_MASK (0x700000U) |
| #define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_ARM_PLL_DIV_VAL_SHIFT (20U) |
| /*! ARM_PLL_DIV_VAL |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_ARM_PLL_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_ARM_PLL_DIV_VAL_SHIFT)) & CCM_ANALOG_FRAC_PLLOUT_DIV_CFG_ARM_PLL_DIV_VAL_MASK) |
| /*! @} */ |
| |
| /*! @name SCCG_PLLOUT_DIV_CFG - SCCG PLLOUT Divider Configuration Register */ |
| /*! @{ */ |
| #define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL1_DIV_VAL_MASK (0x7U) |
| #define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL1_DIV_VAL_SHIFT (0U) |
| /*! SYSTEM_PLL1_DIV_VAL |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL1_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL1_DIV_VAL_SHIFT)) & CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL1_DIV_VAL_MASK) |
| #define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL2_DIV_VAL_MASK (0x70U) |
| #define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL2_DIV_VAL_SHIFT (4U) |
| /*! SYSTEM_PLL2_DIV_VAL |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL2_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL2_DIV_VAL_SHIFT)) & CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL2_DIV_VAL_MASK) |
| #define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL3_DIV_VAL_MASK (0x700U) |
| #define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL3_DIV_VAL_SHIFT (8U) |
| /*! SYSTEM_PLL3_DIV_VAL |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL3_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL3_DIV_VAL_SHIFT)) & CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_SYSTEM_PLL3_DIV_VAL_MASK) |
| #define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_DRAM_PLL_DIV_VAL_MASK (0x7000U) |
| #define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_DRAM_PLL_DIV_VAL_SHIFT (12U) |
| /*! DRAM_PLL_DIV_VAL |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_DRAM_PLL_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_DRAM_PLL_DIV_VAL_SHIFT)) & CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_DRAM_PLL_DIV_VAL_MASK) |
| #define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_VIDEO_PLL2_DIV_VAL_MASK (0x70000U) |
| #define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_VIDEO_PLL2_DIV_VAL_SHIFT (16U) |
| /*! VIDEO_PLL2_DIV_VAL |
| * 0b000..Divide by 1 |
| * 0b001..Divide by 2 |
| * 0b010..Divide by 3 |
| * 0b011..Divide by 4 |
| * 0b100..Divide by 5 |
| * 0b101..Divide by 6 |
| * 0b110..Divide by 7 |
| * 0b111..Divide by 8 |
| */ |
| #define CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_VIDEO_PLL2_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_VIDEO_PLL2_DIV_VAL_SHIFT)) & CCM_ANALOG_SCCG_PLLOUT_DIV_CFG_VIDEO_PLL2_DIV_VAL_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group CCM_ANALOG_Register_Masks */ |
| |
| |
| /* CCM_ANALOG - Peripheral instance base addresses */ |
| /** Peripheral CCM_ANALOG base address */ |
| #define CCM_ANALOG_BASE (0x30360000u) |
| /** Peripheral CCM_ANALOG base pointer */ |
| #define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE) |
| /** Array initializer of CCM_ANALOG peripheral base addresses */ |
| #define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE } |
| /** Array initializer of CCM_ANALOG peripheral base pointers */ |
| #define CCM_ANALOG_BASE_PTRS { CCM_ANALOG } |
| |
| /*! |
| * @} |
| */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- CTX_LD Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CTX_LD_Peripheral_Access_Layer CTX_LD Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** CTX_LD - Register Layout Typedef */ |
| typedef struct { |
| struct { /* offset: 0x0 */ |
| __IO uint32_t RW; /**< Control status register for Context Loader., offset: 0x0 */ |
| __IO uint32_t SET; /**< Control status register for Context Loader., offset: 0x4 */ |
| __IO uint32_t CLR; /**< Control status register for Context Loader., offset: 0x8 */ |
| __IO uint32_t TOG; /**< Control status register for Context Loader., offset: 0xC */ |
| } CTRL_STATUS; |
| __IO uint32_t DB_BASE_ADDR; /**< DRAM addr for double buffered register fetch., offset: 0x10 */ |
| __IO uint32_t DB_COUNT; /**< Double buffer register count, offset: 0x14 */ |
| __IO uint32_t SB_BASE_ADDR; /**< DRAM addr for single buffered registers., offset: 0x18 */ |
| __IO uint32_t SB_COUNT; /**< Single buffer register count, offset: 0x1C */ |
| __I uint32_t AHB_ERR_ADDR; /**< AHB address with error response., offset: 0x20 */ |
| } CTX_LD_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- CTX_LD Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CTX_LD_Register_Masks CTX_LD Register Masks |
| * @{ |
| */ |
| |
| /*! @name CTRL_STATUS - Control status register for Context Loader. */ |
| /*! @{ */ |
| #define CTX_LD_CTRL_STATUS_ENABLE_MASK (0x1U) |
| #define CTX_LD_CTRL_STATUS_ENABLE_SHIFT (0U) |
| #define CTX_LD_CTRL_STATUS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_ENABLE_SHIFT)) & CTX_LD_CTRL_STATUS_ENABLE_MASK) |
| #define CTX_LD_CTRL_STATUS_ARB_SEL_MASK (0x2U) |
| #define CTX_LD_CTRL_STATUS_ARB_SEL_SHIFT (1U) |
| #define CTX_LD_CTRL_STATUS_ARB_SEL(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_ARB_SEL_SHIFT)) & CTX_LD_CTRL_STATUS_ARB_SEL_MASK) |
| #define CTX_LD_CTRL_STATUS_RD_ERR_EN_MASK (0x4U) |
| #define CTX_LD_CTRL_STATUS_RD_ERR_EN_SHIFT (2U) |
| #define CTX_LD_CTRL_STATUS_RD_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_RD_ERR_EN_SHIFT)) & CTX_LD_CTRL_STATUS_RD_ERR_EN_MASK) |
| #define CTX_LD_CTRL_STATUS_DB_COMP_EN_MASK (0x8U) |
| #define CTX_LD_CTRL_STATUS_DB_COMP_EN_SHIFT (3U) |
| #define CTX_LD_CTRL_STATUS_DB_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_DB_COMP_EN_SHIFT)) & CTX_LD_CTRL_STATUS_DB_COMP_EN_MASK) |
| #define CTX_LD_CTRL_STATUS_SB_HP_COMP_EN_MASK (0x10U) |
| #define CTX_LD_CTRL_STATUS_SB_HP_COMP_EN_SHIFT (4U) |
| #define CTX_LD_CTRL_STATUS_SB_HP_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_SB_HP_COMP_EN_SHIFT)) & CTX_LD_CTRL_STATUS_SB_HP_COMP_EN_MASK) |
| #define CTX_LD_CTRL_STATUS_SB_LP_COMP_EN_MASK (0x20U) |
| #define CTX_LD_CTRL_STATUS_SB_LP_COMP_EN_SHIFT (5U) |
| #define CTX_LD_CTRL_STATUS_SB_LP_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_SB_LP_COMP_EN_SHIFT)) & CTX_LD_CTRL_STATUS_SB_LP_COMP_EN_MASK) |
| #define CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_EN_MASK (0x40U) |
| #define CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_EN_SHIFT (6U) |
| #define CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_EN(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_EN_SHIFT)) & CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_EN_MASK) |
| #define CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_EN_MASK (0x80U) |
| #define CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_EN_SHIFT (7U) |
| #define CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_EN(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_EN_SHIFT)) & CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_EN_MASK) |
| #define CTX_LD_CTRL_STATUS_AHB_ERR_EN_MASK (0x100U) |
| #define CTX_LD_CTRL_STATUS_AHB_ERR_EN_SHIFT (8U) |
| #define CTX_LD_CTRL_STATUS_AHB_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_AHB_ERR_EN_SHIFT)) & CTX_LD_CTRL_STATUS_AHB_ERR_EN_MASK) |
| #define CTX_LD_CTRL_STATUS_RD_ERR_MASK (0x10000U) |
| #define CTX_LD_CTRL_STATUS_RD_ERR_SHIFT (16U) |
| #define CTX_LD_CTRL_STATUS_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_RD_ERR_SHIFT)) & CTX_LD_CTRL_STATUS_RD_ERR_MASK) |
| #define CTX_LD_CTRL_STATUS_DB_COMP_MASK (0x20000U) |
| #define CTX_LD_CTRL_STATUS_DB_COMP_SHIFT (17U) |
| #define CTX_LD_CTRL_STATUS_DB_COMP(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_DB_COMP_SHIFT)) & CTX_LD_CTRL_STATUS_DB_COMP_MASK) |
| #define CTX_LD_CTRL_STATUS_SB_HP_COMP_MASK (0x40000U) |
| #define CTX_LD_CTRL_STATUS_SB_HP_COMP_SHIFT (18U) |
| #define CTX_LD_CTRL_STATUS_SB_HP_COMP(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_SB_HP_COMP_SHIFT)) & CTX_LD_CTRL_STATUS_SB_HP_COMP_MASK) |
| #define CTX_LD_CTRL_STATUS_SB_LP_COMP_MASK (0x80000U) |
| #define CTX_LD_CTRL_STATUS_SB_LP_COMP_SHIFT (19U) |
| #define CTX_LD_CTRL_STATUS_SB_LP_COMP(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_SB_LP_COMP_SHIFT)) & CTX_LD_CTRL_STATUS_SB_LP_COMP_MASK) |
| #define CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_MASK (0x100000U) |
| #define CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_SHIFT (20U) |
| #define CTX_LD_CTRL_STATUS_DB_PEND_SB_REC(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_SHIFT)) & CTX_LD_CTRL_STATUS_DB_PEND_SB_REC_MASK) |
| #define CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_MASK (0x200000U) |
| #define CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_SHIFT (21U) |
| #define CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_SHIFT)) & CTX_LD_CTRL_STATUS_SB_PEND_DISP_ACTIVE_MASK) |
| #define CTX_LD_CTRL_STATUS_AHB_ERR_MASK (0x400000U) |
| #define CTX_LD_CTRL_STATUS_AHB_ERR_SHIFT (22U) |
| #define CTX_LD_CTRL_STATUS_AHB_ERR(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_CTRL_STATUS_AHB_ERR_SHIFT)) & CTX_LD_CTRL_STATUS_AHB_ERR_MASK) |
| /*! @} */ |
| |
| /*! @name DB_BASE_ADDR - DRAM addr for double buffered register fetch. */ |
| /*! @{ */ |
| #define CTX_LD_DB_BASE_ADDR_DB_BASE_ADDR_MASK (0xFFFFFFFFU) |
| #define CTX_LD_DB_BASE_ADDR_DB_BASE_ADDR_SHIFT (0U) |
| #define CTX_LD_DB_BASE_ADDR_DB_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_DB_BASE_ADDR_DB_BASE_ADDR_SHIFT)) & CTX_LD_DB_BASE_ADDR_DB_BASE_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name DB_COUNT - Double buffer register count */ |
| /*! @{ */ |
| #define CTX_LD_DB_COUNT_DB_COUNT_MASK (0xFFFFU) |
| #define CTX_LD_DB_COUNT_DB_COUNT_SHIFT (0U) |
| #define CTX_LD_DB_COUNT_DB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_DB_COUNT_DB_COUNT_SHIFT)) & CTX_LD_DB_COUNT_DB_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name SB_BASE_ADDR - DRAM addr for single buffered registers. */ |
| /*! @{ */ |
| #define CTX_LD_SB_BASE_ADDR_SB_BASE_ADDR_MASK (0xFFFFFFFFU) |
| #define CTX_LD_SB_BASE_ADDR_SB_BASE_ADDR_SHIFT (0U) |
| #define CTX_LD_SB_BASE_ADDR_SB_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_SB_BASE_ADDR_SB_BASE_ADDR_SHIFT)) & CTX_LD_SB_BASE_ADDR_SB_BASE_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name SB_COUNT - Single buffer register count */ |
| /*! @{ */ |
| #define CTX_LD_SB_COUNT_HP_COUNT_MASK (0xFFFFU) |
| #define CTX_LD_SB_COUNT_HP_COUNT_SHIFT (0U) |
| #define CTX_LD_SB_COUNT_HP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_SB_COUNT_HP_COUNT_SHIFT)) & CTX_LD_SB_COUNT_HP_COUNT_MASK) |
| #define CTX_LD_SB_COUNT_LP_COUNT_MASK (0xFFFF0000U) |
| #define CTX_LD_SB_COUNT_LP_COUNT_SHIFT (16U) |
| #define CTX_LD_SB_COUNT_LP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_SB_COUNT_LP_COUNT_SHIFT)) & CTX_LD_SB_COUNT_LP_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name AHB_ERR_ADDR - AHB address with error response. */ |
| /*! @{ */ |
| #define CTX_LD_AHB_ERR_ADDR_AHB_ERR_ADDR_MASK (0xFFFFFFFFU) |
| #define CTX_LD_AHB_ERR_ADDR_AHB_ERR_ADDR_SHIFT (0U) |
| #define CTX_LD_AHB_ERR_ADDR_AHB_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CTX_LD_AHB_ERR_ADDR_AHB_ERR_ADDR_SHIFT)) & CTX_LD_AHB_ERR_ADDR_AHB_ERR_ADDR_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group CTX_LD_Register_Masks */ |
| |
| |
| /* CTX_LD - Peripheral instance base addresses */ |
| /** Peripheral DCSS__CTX_LD base address */ |
| #define DCSS__CTX_LD_BASE (0x32E23000u) |
| /** Peripheral DCSS__CTX_LD base pointer */ |
| #define DCSS__CTX_LD ((CTX_LD_Type *)DCSS__CTX_LD_BASE) |
| /** Array initializer of CTX_LD peripheral base addresses */ |
| #define CTX_LD_BASE_ADDRS { DCSS__CTX_LD_BASE } |
| /** Array initializer of CTX_LD peripheral base pointers */ |
| #define CTX_LD_BASE_PTRS { DCSS__CTX_LD } |
| |
| /*! |
| * @} |
| */ /* end of group CTX_LD_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- DDRC_REGS Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup DDRC_REGS_Peripheral_Access_Layer DDRC_REGS Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** DDRC_REGS - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t MSTR; /**< Master Register0, offset: 0x0 */ |
| __I uint32_t STAT; /**< Operating Mode Status Register, offset: 0x4 */ |
| uint8_t RESERVED_0[8]; |
| __IO uint32_t MRCTRL0; /**< Mode Register Read/Write Control Register 0., offset: 0x10 */ |
| __IO uint32_t MRCTRL1; /**< Mode Register Read/Write Control Register 1, offset: 0x14 */ |
| __I uint32_t MRSTAT; /**< Mode Register Read/Write Status Register, offset: 0x18 */ |
| __IO uint32_t MRCTRL2; /**< Mode Register Read/Write Control Register 2, offset: 0x1C */ |
| __IO uint32_t DERATEEN; /**< Temperature Derate Enable Register, offset: 0x20 */ |
| __IO uint32_t DERATEINT; /**< Temperature Derate Interval Register, offset: 0x24 */ |
| uint8_t RESERVED_1[8]; |
| __IO uint32_t PWRCTL; /**< Low Power Control Register, offset: 0x30 */ |
| __IO uint32_t PWRTMG; /**< Low Power Timing Register, offset: 0x34 */ |
| __IO uint32_t HWLPCTL; /**< Hardware Low Power Control Register, offset: 0x38 */ |
| uint8_t RESERVED_2[20]; |
| __IO uint32_t RFSHCTL0; /**< Refresh Control Register 0, offset: 0x50 */ |
| __IO uint32_t RFSHCTL1; /**< Refresh Control Register 1, offset: 0x54 */ |
| uint8_t RESERVED_3[8]; |
| __IO uint32_t RFSHCTL3; /**< Refresh Control Register 3, offset: 0x60 */ |
| __IO uint32_t RFSHTMG; /**< Refresh Timing Register, offset: 0x64 */ |
| uint8_t RESERVED_4[88]; |
| __IO uint32_t CRCPARCTL0; /**< CRC Parity Control Register0, offset: 0xC0 */ |
| __IO uint32_t CRCPARCTL1; /**< CRC Parity Control Register1, offset: 0xC4 */ |
| uint8_t RESERVED_5[4]; |
| __I uint32_t CRCPARSTAT; /**< CRC Parity Status Register, offset: 0xCC */ |
| __IO uint32_t INIT0; /**< SDRAM Initialization Register 0, offset: 0xD0 */ |
| __IO uint32_t INIT1; /**< SDRAM Initialization Register 1, offset: 0xD4 */ |
| __IO uint32_t INIT2; /**< SDRAM Initialization Register 2, offset: 0xD8 */ |
| __IO uint32_t INIT3; /**< SDRAM Initialization Register 3, offset: 0xDC */ |
| __IO uint32_t INIT4; /**< SDRAM Initialization Register 4, offset: 0xE0 */ |
| __IO uint32_t INIT5; /**< SDRAM Initialization Register 5, offset: 0xE4 */ |
| __IO uint32_t INIT6; /**< SDRAM Initialization Register 6, offset: 0xE8 */ |
| __IO uint32_t INIT7; /**< SDRAM Initialization Register 7, offset: 0xEC */ |
| __IO uint32_t DIMMCTL; /**< DIMM Control Register, offset: 0xF0 */ |
| __IO uint32_t RANKCTL; /**< Rank Control Register, offset: 0xF4 */ |
| uint8_t RESERVED_6[8]; |
| __IO uint32_t DRAMTMG0; /**< SDRAM Timing Register 0, offset: 0x100 */ |
| __IO uint32_t DRAMTMG1; /**< SDRAM Timing Register 1, offset: 0x104 */ |
| __IO uint32_t DRAMTMG2; /**< SDRAM Timing Register 2, offset: 0x108 */ |
| __IO uint32_t DRAMTMG3; /**< SDRAM Timing Register 3, offset: 0x10C */ |
| __IO uint32_t DRAMTMG4; /**< SDRAM Timing Register 4, offset: 0x110 */ |
| __IO uint32_t DRAMTMG5; /**< SDRAM Timing Register 5, offset: 0x114 */ |
| __IO uint32_t DRAMTMG6; /**< SDRAM Timing Register 6, offset: 0x118 */ |
| __IO uint32_t DRAMTMG7; /**< SDRAM Timing Register 7, offset: 0x11C */ |
| __IO uint32_t DRAMTMG8; /**< SDRAM Timing Register 8, offset: 0x120 */ |
| __IO uint32_t DRAMTMG9; /**< SDRAM Timing Register 9, offset: 0x124 */ |
| __IO uint32_t DRAMTMG10; /**< SDRAM Timing Register 10, offset: 0x128 */ |
| __IO uint32_t DRAMTMG11; /**< SDRAM Timing Register 11, offset: 0x12C */ |
| __IO uint32_t DRAMTMG12; /**< SDRAM Timing Register 12, offset: 0x130 */ |
| __IO uint32_t DRAMTMG13; /**< SDRAM Timing Register 13, offset: 0x134 */ |
| __IO uint32_t DRAMTMG14; /**< SDRAM Timing Register 14, offset: 0x138 */ |
| __IO uint32_t DRAMTMG15; /**< SDRAM Timing Register 15, offset: 0x13C */ |
| uint8_t RESERVED_7[64]; |
| __IO uint32_t ZQCTL0; /**< ZQ Control Register 0, offset: 0x180 */ |
| __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ |
| __IO uint32_t ZQCTL2; /**< ZQ Control Register 2, offset: 0x188 */ |
| __I uint32_t ZQSTAT; /**< ZQ Status Register, offset: 0x18C */ |
| __IO uint32_t DFITMG0; /**< DFI Timing Register 0, offset: 0x190 */ |
| __IO uint32_t DFITMG1; /**< DFI Timing Register 1, offset: 0x194 */ |
| __IO uint32_t DFILPCFG0; /**< DFI Low Power Configuration Register 0, offset: 0x198 */ |
| __IO uint32_t DFILPCFG1; /**< DFI Low Power Configuration Register 1, offset: 0x19C */ |
| __IO uint32_t DFIUPD0; /**< DFI Update Register 0, offset: 0x1A0 */ |
| __IO uint32_t DFIUPD1; /**< DFI Update Register 1, offset: 0x1A4 */ |
| __IO uint32_t DFIUPD2; /**< DFI Update Register 2, offset: 0x1A8 */ |
| uint8_t RESERVED_8[4]; |
| __IO uint32_t DFIMISC; /**< DFI Miscellaneous Control Register, offset: 0x1B0 */ |
| __IO uint32_t DFITMG2; /**< DFI Timing Register 2, offset: 0x1B4 */ |
| __IO uint32_t DFITMG3; /**< DFI Timing Register 3, offset: 0x1B8 */ |
| __I uint32_t DFISTAT; /**< DFI Status Register, offset: 0x1BC */ |
| __IO uint32_t DBICTL; /**< DM/DBI Control Register, offset: 0x1C0 */ |
| uint8_t RESERVED_9[60]; |
| __IO uint32_t ADDRMAP0; /**< Address Map Register 0, offset: 0x200 */ |
| __IO uint32_t ADDRMAP1; /**< Address Map Register 1, offset: 0x204 */ |
| __IO uint32_t ADDRMAP2; /**< Address Map Register 2, offset: 0x208 */ |
| __IO uint32_t ADDRMAP3; /**< Address Map Register 3, offset: 0x20C */ |
| __IO uint32_t ADDRMAP4; /**< Address Map Register 4, offset: 0x210 */ |
| __IO uint32_t ADDRMAP5; /**< Address Map Register 5, offset: 0x214 */ |
| __IO uint32_t ADDRMAP6; /**< Address Map Register 6, offset: 0x218 */ |
| __IO uint32_t ADDRMAP7; /**< Address Map Register 7, offset: 0x21C */ |
| __IO uint32_t ADDRMAP8; /**< Address Map Register 8, offset: 0x220 */ |
| __IO uint32_t ADDRMAP9; /**< Address Map Register 9, offset: 0x224 */ |
| __IO uint32_t ADDRMAP10; /**< Address Map Register 10, offset: 0x228 */ |
| __IO uint32_t ADDRMAP11; /**< Address Map Register 11, offset: 0x22C */ |
| uint8_t RESERVED_10[16]; |
| __IO uint32_t ODTCFG; /**< ODT Configuration Register, offset: 0x240 */ |
| __IO uint32_t ODTMAP; /**< ODT/Rank Map Register, offset: 0x244 */ |
| uint8_t RESERVED_11[8]; |
| __IO uint32_t SCHED; /**< Scheduler Control Register, offset: 0x250 */ |
| __IO uint32_t SCHED1; /**< Scheduler Control Register 1, offset: 0x254 */ |
| uint8_t RESERVED_12[4]; |
| __IO uint32_t PERFHPR1; /**< High Priority Read CAM Register 1, offset: 0x25C */ |
| uint8_t RESERVED_13[4]; |
| __IO uint32_t PERFLPR1; /**< Low Priority Read CAM Register 1, offset: 0x264 */ |
| uint8_t RESERVED_14[4]; |
| __IO uint32_t PERFWR1; /**< Write CAM Register 1, offset: 0x26C */ |
| uint8_t RESERVED_15[144]; |
| __IO uint32_t DBG0; /**< Debug Register 0, offset: 0x300 */ |
| __IO uint32_t DBG1; /**< Debug Register 1, offset: 0x304 */ |
| __I uint32_t DBGCAM; /**< CAM Debug Register, offset: 0x308 */ |
| __IO uint32_t DBGCMD; /**< Command Debug Register, offset: 0x30C */ |
| __I uint32_t DBGSTAT; /**< Status Debug Register, offset: 0x310 */ |
| uint8_t RESERVED_16[12]; |
| __IO uint32_t SWCTL; /**< Software Register Programming Control Enable, offset: 0x320 */ |
| __I uint32_t SWSTAT; /**< Software Register Programming Control Status, offset: 0x324 */ |
| uint8_t RESERVED_17[68]; |
| __IO uint32_t POISONCFG; /**< AXI Poison Configuration Register., offset: 0x36C */ |
| __I uint32_t POISONSTAT; /**< AXI Poison Status Register, offset: 0x370 */ |
| uint8_t RESERVED_18[136]; |
| __I uint32_t PSTAT; /**< Port Status Register, offset: 0x3FC */ |
| __IO uint32_t PCCFG; /**< Port Common Configuration Register, offset: 0x400 */ |
| __IO uint32_t PCFGR_0; /**< Port n Configuration Read Register, offset: 0x404 */ |
| __IO uint32_t PCFGW_0; /**< Port n Configuration Write Register, offset: 0x408 */ |
| uint8_t RESERVED_19[132]; |
| __IO uint32_t PCTRL_0; /**< Port n Control Register, offset: 0x490 */ |
| __IO uint32_t PCFGQOS0_0; /**< Port n Read QoS Configuration Register 0, offset: 0x494 */ |
| __IO uint32_t PCFGQOS1_0; /**< Port n Read QoS Configuration Register 1, offset: 0x498 */ |
| __IO uint32_t PCFGWQOS0_0; /**< Port n Write QoS Configuration Register 0, offset: 0x49C */ |
| __IO uint32_t PCFGWQOS1_0; /**< Port n Write QoS Configuration Register 1, offset: 0x4A0 */ |
| uint8_t RESERVED_20[7036]; |
| __IO uint32_t DERATEEN_SHADOW; /**< [SHADOW] Temperature Derate Enable Register, offset: 0x2020 */ |
| __IO uint32_t DERATEINT_SHADOW; /**< [SHADOW] Temperature Derate Interval Register, offset: 0x2024 */ |
| uint8_t RESERVED_21[40]; |
| __IO uint32_t RFSHCTL0_SHADOW; /**< [SHADOW] Refresh Control Register 0, offset: 0x2050 */ |
| uint8_t RESERVED_22[16]; |
| __IO uint32_t RFSHTMG_SHADOW; /**< [SHADOW] Refresh Timing Register, offset: 0x2064 */ |
| uint8_t RESERVED_23[116]; |
| __IO uint32_t INIT3_SHADOW; /**< [SHADOW] SDRAM Initialization Register 3, offset: 0x20DC */ |
| __IO uint32_t INIT4_SHADOW; /**< [SHADOW] SDRAM Initialization Register 4, offset: 0x20E0 */ |
| uint8_t RESERVED_24[4]; |
| __IO uint32_t INIT6_SHADOW; /**< [SHADOW] SDRAM Initialization Register 6, offset: 0x20E8 */ |
| __IO uint32_t INIT7_SHADOW; /**< [SHADOW] SDRAM Initialization Register 7, offset: 0x20EC */ |
| uint8_t RESERVED_25[16]; |
| __IO uint32_t DRAMTMG0_SHADOW; /**< [SHADOW] SDRAM Timing Register 0, offset: 0x2100 */ |
| __IO uint32_t DRAMTMG1_SHADOW; /**< [SHADOW] SDRAM Timing Register 1, offset: 0x2104 */ |
| __IO uint32_t DRAMTMG2_SHADOW; /**< [SHADOW] SDRAM Timing Register 2, offset: 0x2108 */ |
| __IO uint32_t DRAMTMG3_SHADOW; /**< [SHADOW] SDRAM Timing Register 3, offset: 0x210C */ |
| __IO uint32_t DRAMTMG4_SHADOW; /**< [SHADOW] SDRAM Timing Register 4, offset: 0x2110 */ |
| __IO uint32_t DRAMTMG5_SHADOW; /**< [SHADOW] SDRAM Timing Register 5, offset: 0x2114 */ |
| __IO uint32_t DRAMTMG6_SHADOW; /**< [SHADOW] SDRAM Timing Register 6, offset: 0x2118 */ |
| __IO uint32_t DRAMTMG7_SHADOW; /**< [SHADOW] SDRAM Timing Register 7, offset: 0x211C */ |
| __IO uint32_t DRAMTMG8_SHADOW; /**< [SHADOW] SDRAM Timing Register 8, offset: 0x2120 */ |
| __IO uint32_t DRAMTMG9_SHADOW; /**< [SHADOW] SDRAM Timing Register 9, offset: 0x2124 */ |
| __IO uint32_t DRAMTMG10_SHADOW; /**< [SHADOW] SDRAM Timing Register 10, offset: 0x2128 */ |
| __IO uint32_t DRAMTMG11_SHADOW; /**< [SHADOW] SDRAM Timing Register 11, offset: 0x212C */ |
| __IO uint32_t DRAMTMG12_SHADOW; /**< [SHADOW] SDRAM Timing Register 12, offset: 0x2130 */ |
| __IO uint32_t DRAMTMG13_SHADOW; /**< [SHADOW] SDRAM Timing Register 13, offset: 0x2134 */ |
| __IO uint32_t DRAMTMG14_SHADOW; /**< [SHADOW] SDRAM Timing Register 14, offset: 0x2138 */ |
| __IO uint32_t DRAMTMG15_SHADOW; /**< [SHADOW] SDRAM Timing Register 15, offset: 0x213C */ |
| uint8_t RESERVED_26[64]; |
| __IO uint32_t ZQCTL0_SHADOW; /**< [SHADOW] ZQ Control Register 0, offset: 0x2180 */ |
| uint8_t RESERVED_27[12]; |
| __IO uint32_t DFITMG0_SHADOW; /**< [SHADOW] DFI Timing Register 0, offset: 0x2190 */ |
| __IO uint32_t DFITMG1_SHADOW; /**< [SHADOW] DFI Timing Register 1, offset: 0x2194 */ |
| uint8_t RESERVED_28[28]; |
| __IO uint32_t DFITMG2_SHADOW; /**< [SHADOW] DFI Timing Register 2, offset: 0x21B4 */ |
| __IO uint32_t DFITMG3_SHADOW; /**< [SHADOW] DFI Timing Register 3, offset: 0x21B8 */ |
| uint8_t RESERVED_29[132]; |
| __IO uint32_t ODTCFG_SHADOW; /**< [SHADOW] ODT Configuration Register, offset: 0x2240 */ |
| } DDRC_REGS_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- DDRC_REGS Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup DDRC_REGS_Register_Masks DDRC_REGS Register Masks |
| * @{ |
| */ |
| |
| /*! @name MSTR - Master Register0 */ |
| /*! @{ */ |
| #define DDRC_REGS_MSTR_ddr3_MASK (0x1U) |
| #define DDRC_REGS_MSTR_ddr3_SHIFT (0U) |
| #define DDRC_REGS_MSTR_ddr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_ddr3_SHIFT)) & DDRC_REGS_MSTR_ddr3_MASK) |
| #define DDRC_REGS_MSTR_lpddr2_MASK (0x4U) |
| #define DDRC_REGS_MSTR_lpddr2_SHIFT (2U) |
| #define DDRC_REGS_MSTR_lpddr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_lpddr2_SHIFT)) & DDRC_REGS_MSTR_lpddr2_MASK) |
| #define DDRC_REGS_MSTR_lpddr3_MASK (0x8U) |
| #define DDRC_REGS_MSTR_lpddr3_SHIFT (3U) |
| #define DDRC_REGS_MSTR_lpddr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_lpddr3_SHIFT)) & DDRC_REGS_MSTR_lpddr3_MASK) |
| #define DDRC_REGS_MSTR_ddr4_MASK (0x10U) |
| #define DDRC_REGS_MSTR_ddr4_SHIFT (4U) |
| #define DDRC_REGS_MSTR_ddr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_ddr4_SHIFT)) & DDRC_REGS_MSTR_ddr4_MASK) |
| #define DDRC_REGS_MSTR_lpddr4_MASK (0x20U) |
| #define DDRC_REGS_MSTR_lpddr4_SHIFT (5U) |
| #define DDRC_REGS_MSTR_lpddr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_lpddr4_SHIFT)) & DDRC_REGS_MSTR_lpddr4_MASK) |
| #define DDRC_REGS_MSTR_burstchop_MASK (0x200U) |
| #define DDRC_REGS_MSTR_burstchop_SHIFT (9U) |
| #define DDRC_REGS_MSTR_burstchop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_burstchop_SHIFT)) & DDRC_REGS_MSTR_burstchop_MASK) |
| #define DDRC_REGS_MSTR_en_2t_timing_mode_MASK (0x400U) |
| #define DDRC_REGS_MSTR_en_2t_timing_mode_SHIFT (10U) |
| #define DDRC_REGS_MSTR_en_2t_timing_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_en_2t_timing_mode_SHIFT)) & DDRC_REGS_MSTR_en_2t_timing_mode_MASK) |
| #define DDRC_REGS_MSTR_geardown_mode_MASK (0x800U) |
| #define DDRC_REGS_MSTR_geardown_mode_SHIFT (11U) |
| #define DDRC_REGS_MSTR_geardown_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_geardown_mode_SHIFT)) & DDRC_REGS_MSTR_geardown_mode_MASK) |
| #define DDRC_REGS_MSTR_data_bus_width_MASK (0x3000U) |
| #define DDRC_REGS_MSTR_data_bus_width_SHIFT (12U) |
| #define DDRC_REGS_MSTR_data_bus_width(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_data_bus_width_SHIFT)) & DDRC_REGS_MSTR_data_bus_width_MASK) |
| #define DDRC_REGS_MSTR_dll_off_mode_MASK (0x8000U) |
| #define DDRC_REGS_MSTR_dll_off_mode_SHIFT (15U) |
| #define DDRC_REGS_MSTR_dll_off_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_dll_off_mode_SHIFT)) & DDRC_REGS_MSTR_dll_off_mode_MASK) |
| #define DDRC_REGS_MSTR_burst_rdwr_MASK (0xF0000U) |
| #define DDRC_REGS_MSTR_burst_rdwr_SHIFT (16U) |
| /*! burst_rdwr - SDRAM burst length used |
| * 0b0001..Burst length of 2 (only supported for mDDR) |
| * 0b0010..Burst length of 4 |
| * 0b0100..Burst length of 8 |
| * 0b1000..Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) |
| */ |
| #define DDRC_REGS_MSTR_burst_rdwr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_burst_rdwr_SHIFT)) & DDRC_REGS_MSTR_burst_rdwr_MASK) |
| #define DDRC_REGS_MSTR_frequency_ratio_MASK (0x400000U) |
| #define DDRC_REGS_MSTR_frequency_ratio_SHIFT (22U) |
| /*! frequency_ratio - Selects the Frequency Ratio |
| * 0b0..1:2 Mode |
| * 0b1..1:1 Mode |
| */ |
| #define DDRC_REGS_MSTR_frequency_ratio(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_frequency_ratio_SHIFT)) & DDRC_REGS_MSTR_frequency_ratio_MASK) |
| #define DDRC_REGS_MSTR_active_ranks_MASK (0x3000000U) |
| #define DDRC_REGS_MSTR_active_ranks_SHIFT (24U) |
| #define DDRC_REGS_MSTR_active_ranks(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_active_ranks_SHIFT)) & DDRC_REGS_MSTR_active_ranks_MASK) |
| #define DDRC_REGS_MSTR_frequency_mode_MASK (0x20000000U) |
| #define DDRC_REGS_MSTR_frequency_mode_SHIFT (29U) |
| /*! frequency_mode - Choose which registers are used. |
| * 0b0..Original Registers |
| * 0b1..Shadow Registers |
| */ |
| #define DDRC_REGS_MSTR_frequency_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_frequency_mode_SHIFT)) & DDRC_REGS_MSTR_frequency_mode_MASK) |
| #define DDRC_REGS_MSTR_device_config_MASK (0xC0000000U) |
| #define DDRC_REGS_MSTR_device_config_SHIFT (30U) |
| /*! device_config - Indicates the configuration of the device used in the system. |
| * 0b00..x4 device |
| * 0b01..x8 device |
| * 0b10..x16 device |
| * 0b11..x32 device |
| */ |
| #define DDRC_REGS_MSTR_device_config(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MSTR_device_config_SHIFT)) & DDRC_REGS_MSTR_device_config_MASK) |
| /*! @} */ |
| |
| /*! @name STAT - Operating Mode Status Register */ |
| /*! @{ */ |
| #define DDRC_REGS_STAT_operating_mode_MASK (0x7U) |
| #define DDRC_REGS_STAT_operating_mode_SHIFT (0U) |
| #define DDRC_REGS_STAT_operating_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_STAT_operating_mode_SHIFT)) & DDRC_REGS_STAT_operating_mode_MASK) |
| #define DDRC_REGS_STAT_selfref_type_MASK (0x30U) |
| #define DDRC_REGS_STAT_selfref_type_SHIFT (4U) |
| /*! selfref_type - Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. |
| * 0b00..SDRAM is not in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by CRCPARCTRL1.crc_parity_retry_enable, this also indicates SRE command is still in parity error window or retry is in-progress. |
| * 0b11..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was caused by Automatic Self Refresh only. If retry is enabled, this guarantees SRE command is executed correctly without parity error. |
| * 0b10..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was not caused solely under Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software (reg_ddrc_selfref_sw). If retry is enabled, this guarantees SRE command is executed correctly without parity |
| */ |
| #define DDRC_REGS_STAT_selfref_type(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_STAT_selfref_type_SHIFT)) & DDRC_REGS_STAT_selfref_type_MASK) |
| #define DDRC_REGS_STAT_selfref_state_MASK (0x300U) |
| #define DDRC_REGS_STAT_selfref_state_SHIFT (8U) |
| /*! selfref_state - Self refresh state. This indicates self refresh or self refresh power down state for LPDDR4. This register is used for frequency change and MRR/MRW access during self refresh. |
| * 0b00..SDRAM is not in Self Refresh. |
| * 0b01..Self refresh 1 |
| * 0b10..Self refresh power down |
| * 0b11..Self refresh |
| */ |
| #define DDRC_REGS_STAT_selfref_state(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_STAT_selfref_state_SHIFT)) & DDRC_REGS_STAT_selfref_state_MASK) |
| /*! @} */ |
| |
| /*! @name MRCTRL0 - Mode Register Read/Write Control Register 0. */ |
| /*! @{ */ |
| #define DDRC_REGS_MRCTRL0_mr_type_MASK (0x1U) |
| #define DDRC_REGS_MRCTRL0_mr_type_SHIFT (0U) |
| /*! mr_type - Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. |
| * 0b0..Write |
| * 0b1..Read |
| */ |
| #define DDRC_REGS_MRCTRL0_mr_type(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRCTRL0_mr_type_SHIFT)) & DDRC_REGS_MRCTRL0_mr_type_MASK) |
| #define DDRC_REGS_MRCTRL0_mpr_en_MASK (0x2U) |
| #define DDRC_REGS_MRCTRL0_mpr_en_SHIFT (1U) |
| /*! mpr_en - Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4). |
| * 0b0..MRS |
| * 0b1..WR/RD for MPR |
| */ |
| #define DDRC_REGS_MRCTRL0_mpr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRCTRL0_mpr_en_SHIFT)) & DDRC_REGS_MRCTRL0_mpr_en_MASK) |
| #define DDRC_REGS_MRCTRL0_pda_en_MASK (0x4U) |
| #define DDRC_REGS_MRCTRL0_pda_en_SHIFT (2U) |
| /*! pda_en - Indicates whether the mode register operation is MRS in PDA mode or not.Note that when pba_mode=1, PBA access is initiated instead of PDA access. |
| * 0b0..MRS |
| * 0b1..MRS in Per DRAM Addressability |
| */ |
| #define DDRC_REGS_MRCTRL0_pda_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRCTRL0_pda_en_SHIFT)) & DDRC_REGS_MRCTRL0_pda_en_MASK) |
| #define DDRC_REGS_MRCTRL0_sw_init_int_MASK (0x8U) |
| #define DDRC_REGS_MRCTRL0_sw_init_int_SHIFT (3U) |
| /*! sw_init_int - Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. For DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit can be used to program additional mode registers before automatic SDRAM initialization if necessary. In LPDDR4 independent channel mode, note that this must be programmed to both channels beforehand. Note that this must be cleared to 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. |
| * 0b0..Software intervention is not allowed |
| * 0b1..Software intervention is allowed |
| */ |
| #define DDRC_REGS_MRCTRL0_sw_init_int(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRCTRL0_sw_init_int_SHIFT)) & DDRC_REGS_MRCTRL0_sw_init_int_MASK) |
| #define DDRC_REGS_MRCTRL0_mr_rank_MASK (0x30U) |
| #define DDRC_REGS_MRCTRL0_mr_rank_SHIFT (4U) |
| #define DDRC_REGS_MRCTRL0_mr_rank(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRCTRL0_mr_rank_SHIFT)) & DDRC_REGS_MRCTRL0_mr_rank_MASK) |
| #define DDRC_REGS_MRCTRL0_mr_addr_MASK (0xF000U) |
| #define DDRC_REGS_MRCTRL0_mr_addr_SHIFT (12U) |
| /*! mr_addr - Address of the mode register that is to be written to. |
| * 0b0000..MR0 |
| * 0b0001..MR1 |
| * 0b0010..MR2 |
| * 0b0011..MR3 |
| * 0b0100..MR4 |
| * 0b0101..MR5 |
| * 0b0110..MR6 |
| * 0b0111..MR7 |
| */ |
| #define DDRC_REGS_MRCTRL0_mr_addr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRCTRL0_mr_addr_SHIFT)) & DDRC_REGS_MRCTRL0_mr_addr_MASK) |
| #define DDRC_REGS_MRCTRL0_pba_mode_MASK (0x40000000U) |
| #define DDRC_REGS_MRCTRL0_pba_mode_SHIFT (30U) |
| #define DDRC_REGS_MRCTRL0_pba_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRCTRL0_pba_mode_SHIFT)) & DDRC_REGS_MRCTRL0_pba_mode_MASK) |
| #define DDRC_REGS_MRCTRL0_mr_wr_MASK (0x80000000U) |
| #define DDRC_REGS_MRCTRL0_mr_wr_SHIFT (31U) |
| #define DDRC_REGS_MRCTRL0_mr_wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRCTRL0_mr_wr_SHIFT)) & DDRC_REGS_MRCTRL0_mr_wr_MASK) |
| /*! @} */ |
| |
| /*! @name MRCTRL1 - Mode Register Read/Write Control Register 1 */ |
| /*! @{ */ |
| #define DDRC_REGS_MRCTRL1_mr_data_MASK (0x3FFFFU) |
| #define DDRC_REGS_MRCTRL1_mr_data_SHIFT (0U) |
| #define DDRC_REGS_MRCTRL1_mr_data(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRCTRL1_mr_data_SHIFT)) & DDRC_REGS_MRCTRL1_mr_data_MASK) |
| /*! @} */ |
| |
| /*! @name MRSTAT - Mode Register Read/Write Status Register */ |
| /*! @{ */ |
| #define DDRC_REGS_MRSTAT_mr_wr_busy_MASK (0x1U) |
| #define DDRC_REGS_MRSTAT_mr_wr_busy_SHIFT (0U) |
| /*! mr_wr_busy - The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRC accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when 'MRSTAT.mr_wr_busy' is high. |
| * 0b0..Indicates that the SoC core can initiate a mode register write operation |
| * 0b1..Indicates that mode register write operation is in progress |
| */ |
| #define DDRC_REGS_MRSTAT_mr_wr_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRSTAT_mr_wr_busy_SHIFT)) & DDRC_REGS_MRSTAT_mr_wr_busy_MASK) |
| #define DDRC_REGS_MRSTAT_pda_done_MASK (0x100U) |
| #define DDRC_REGS_MRSTAT_pda_done_SHIFT (8U) |
| /*! pda_done - The SoC core may initiate a MR write operation in PDA/PBA mode only if this signal is low. This signal goes high when three consecutive MRS commands related to the PDA/PBA mode are issued to the SDRAM. This signal goes low when MRCTRL0.pda_en becomes 0. Therefore, it is recommended to write MRCTRL0.pda_en to 0 after this signal goes high in order to prepare to perform PDA operation next time |
| * 0b0..Indicates that mode register write operation related to PDA/PBA is in progress or has not started yet. |
| * 0b1..Indicates that mode register write operation related to PDA/PBA has competed. |
| */ |
| #define DDRC_REGS_MRSTAT_pda_done(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRSTAT_pda_done_SHIFT)) & DDRC_REGS_MRSTAT_pda_done_MASK) |
| /*! @} */ |
| |
| /*! @name MRCTRL2 - Mode Register Read/Write Control Register 2 */ |
| /*! @{ */ |
| #define DDRC_REGS_MRCTRL2_mr_device_sel_MASK (0xFFFFFFFFU) |
| #define DDRC_REGS_MRCTRL2_mr_device_sel_SHIFT (0U) |
| #define DDRC_REGS_MRCTRL2_mr_device_sel(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_MRCTRL2_mr_device_sel_SHIFT)) & DDRC_REGS_MRCTRL2_mr_device_sel_MASK) |
| /*! @} */ |
| |
| /*! @name DERATEEN - Temperature Derate Enable Register */ |
| /*! @{ */ |
| #define DDRC_REGS_DERATEEN_derate_enable_MASK (0x1U) |
| #define DDRC_REGS_DERATEEN_derate_enable_SHIFT (0U) |
| /*! derate_enable - Enables derating. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. |
| * 0b0..Timing parameter derating is disabled |
| * 0b1..Timing parameter derating is enabled using MR4 read value. |
| */ |
| #define DDRC_REGS_DERATEEN_derate_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DERATEEN_derate_enable_SHIFT)) & DDRC_REGS_DERATEEN_derate_enable_MASK) |
| #define DDRC_REGS_DERATEEN_derate_value_MASK (0x2U) |
| #define DDRC_REGS_DERATEEN_derate_value_SHIFT (1U) |
| /*! derate_value - Derate value. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For LPDDR3/4, if the period of core_ddrc_core_clk is less than 1.875ns, this register field should be set to 1; otherwise it should be set to 0. |
| * 0b0..Derating uses +1 |
| * 0b1..Derating uses +2 |
| */ |
| #define DDRC_REGS_DERATEEN_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DERATEEN_derate_value_SHIFT)) & DDRC_REGS_DERATEEN_derate_value_MASK) |
| #define DDRC_REGS_DERATEEN_derate_byte_MASK (0xF0U) |
| #define DDRC_REGS_DERATEEN_derate_byte_SHIFT (4U) |
| #define DDRC_REGS_DERATEEN_derate_byte(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DERATEEN_derate_byte_SHIFT)) & DDRC_REGS_DERATEEN_derate_byte_MASK) |
| #define DDRC_REGS_DERATEEN_rc_derate_value_MASK (0x300U) |
| #define DDRC_REGS_DERATEEN_rc_derate_value_SHIFT (8U) |
| /*! rc_derate_value - Derate value of tRC for LPDDR4. Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer. |
| * 0b00..Derating uses +1 |
| * 0b01..Derating uses +2 |
| * 0b10..Derating uses +3 |
| * 0b11..Derating uses +4 |
| */ |
| #define DDRC_REGS_DERATEEN_rc_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DERATEEN_rc_derate_value_SHIFT)) & DDRC_REGS_DERATEEN_rc_derate_value_MASK) |
| /*! @} */ |
| |
| /*! @name DERATEINT - Temperature Derate Interval Register */ |
| /*! @{ */ |
| #define DDRC_REGS_DERATEINT_mr4_read_interval_MASK (0xFFFFFFFFU) |
| #define DDRC_REGS_DERATEINT_mr4_read_interval_SHIFT (0U) |
| #define DDRC_REGS_DERATEINT_mr4_read_interval(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DERATEINT_mr4_read_interval_SHIFT)) & DDRC_REGS_DERATEINT_mr4_read_interval_MASK) |
| /*! @} */ |
| |
| /*! @name PWRCTL - Low Power Control Register */ |
| /*! @{ */ |
| #define DDRC_REGS_PWRCTL_selfref_en_MASK (0x1U) |
| #define DDRC_REGS_PWRCTL_selfref_en_SHIFT (0U) |
| #define DDRC_REGS_PWRCTL_selfref_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PWRCTL_selfref_en_SHIFT)) & DDRC_REGS_PWRCTL_selfref_en_MASK) |
| #define DDRC_REGS_PWRCTL_powerdown_en_MASK (0x2U) |
| #define DDRC_REGS_PWRCTL_powerdown_en_SHIFT (1U) |
| #define DDRC_REGS_PWRCTL_powerdown_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PWRCTL_powerdown_en_SHIFT)) & DDRC_REGS_PWRCTL_powerdown_en_MASK) |
| #define DDRC_REGS_PWRCTL_deeppowerdown_en_MASK (0x4U) |
| #define DDRC_REGS_PWRCTL_deeppowerdown_en_SHIFT (2U) |
| #define DDRC_REGS_PWRCTL_deeppowerdown_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PWRCTL_deeppowerdown_en_SHIFT)) & DDRC_REGS_PWRCTL_deeppowerdown_en_MASK) |
| #define DDRC_REGS_PWRCTL_en_dfi_dram_clk_disable_MASK (0x8U) |
| #define DDRC_REGS_PWRCTL_en_dfi_dram_clk_disable_SHIFT (3U) |
| #define DDRC_REGS_PWRCTL_en_dfi_dram_clk_disable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PWRCTL_en_dfi_dram_clk_disable_SHIFT)) & DDRC_REGS_PWRCTL_en_dfi_dram_clk_disable_MASK) |
| #define DDRC_REGS_PWRCTL_mpsm_en_MASK (0x10U) |
| #define DDRC_REGS_PWRCTL_mpsm_en_SHIFT (4U) |
| #define DDRC_REGS_PWRCTL_mpsm_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PWRCTL_mpsm_en_SHIFT)) & DDRC_REGS_PWRCTL_mpsm_en_MASK) |
| #define DDRC_REGS_PWRCTL_selfref_sw_MASK (0x20U) |
| #define DDRC_REGS_PWRCTL_selfref_sw_SHIFT (5U) |
| /*! selfref_sw - A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. |
| * 0b0..Software Exit from Self Refresh |
| * 0b1..Software Entry to Self Refresh |
| */ |
| #define DDRC_REGS_PWRCTL_selfref_sw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PWRCTL_selfref_sw_SHIFT)) & DDRC_REGS_PWRCTL_selfref_sw_MASK) |
| #define DDRC_REGS_PWRCTL_stay_in_selfref_MASK (0x40U) |
| #define DDRC_REGS_PWRCTL_stay_in_selfref_SHIFT (6U) |
| #define DDRC_REGS_PWRCTL_stay_in_selfref(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PWRCTL_stay_in_selfref_SHIFT)) & DDRC_REGS_PWRCTL_stay_in_selfref_MASK) |
| /*! @} */ |
| |
| /*! @name PWRTMG - Low Power Timing Register */ |
| /*! @{ */ |
| #define DDRC_REGS_PWRTMG_powerdown_to_x32_MASK (0x1FU) |
| #define DDRC_REGS_PWRTMG_powerdown_to_x32_SHIFT (0U) |
| #define DDRC_REGS_PWRTMG_powerdown_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PWRTMG_powerdown_to_x32_SHIFT)) & DDRC_REGS_PWRTMG_powerdown_to_x32_MASK) |
| #define DDRC_REGS_PWRTMG_t_dpd_x4096_MASK (0xFF00U) |
| #define DDRC_REGS_PWRTMG_t_dpd_x4096_SHIFT (8U) |
| #define DDRC_REGS_PWRTMG_t_dpd_x4096(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PWRTMG_t_dpd_x4096_SHIFT)) & DDRC_REGS_PWRTMG_t_dpd_x4096_MASK) |
| #define DDRC_REGS_PWRTMG_selfref_to_x32_MASK (0xFF0000U) |
| #define DDRC_REGS_PWRTMG_selfref_to_x32_SHIFT (16U) |
| #define DDRC_REGS_PWRTMG_selfref_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PWRTMG_selfref_to_x32_SHIFT)) & DDRC_REGS_PWRTMG_selfref_to_x32_MASK) |
| /*! @} */ |
| |
| /*! @name HWLPCTL - Hardware Low Power Control Register */ |
| /*! @{ */ |
| #define DDRC_REGS_HWLPCTL_hw_lp_en_MASK (0x1U) |
| #define DDRC_REGS_HWLPCTL_hw_lp_en_SHIFT (0U) |
| #define DDRC_REGS_HWLPCTL_hw_lp_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_HWLPCTL_hw_lp_en_SHIFT)) & DDRC_REGS_HWLPCTL_hw_lp_en_MASK) |
| #define DDRC_REGS_HWLPCTL_hw_lp_exit_idle_en_MASK (0x2U) |
| #define DDRC_REGS_HWLPCTL_hw_lp_exit_idle_en_SHIFT (1U) |
| #define DDRC_REGS_HWLPCTL_hw_lp_exit_idle_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_HWLPCTL_hw_lp_exit_idle_en_SHIFT)) & DDRC_REGS_HWLPCTL_hw_lp_exit_idle_en_MASK) |
| #define DDRC_REGS_HWLPCTL_hw_lp_idle_x32_MASK (0xFFF0000U) |
| #define DDRC_REGS_HWLPCTL_hw_lp_idle_x32_SHIFT (16U) |
| #define DDRC_REGS_HWLPCTL_hw_lp_idle_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_HWLPCTL_hw_lp_idle_x32_SHIFT)) & DDRC_REGS_HWLPCTL_hw_lp_idle_x32_MASK) |
| /*! @} */ |
| |
| /*! @name RFSHCTL0 - Refresh Control Register 0 */ |
| /*! @{ */ |
| #define DDRC_REGS_RFSHCTL0_per_bank_refresh_MASK (0x4U) |
| #define DDRC_REGS_RFSHCTL0_per_bank_refresh_SHIFT (2U) |
| /*! per_bank_refresh - Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 |
| * 0b1..Per bank refresh |
| * 0b0..All bank refresh |
| */ |
| #define DDRC_REGS_RFSHCTL0_per_bank_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL0_per_bank_refresh_SHIFT)) & DDRC_REGS_RFSHCTL0_per_bank_refresh_MASK) |
| #define DDRC_REGS_RFSHCTL0_refresh_burst_MASK (0x1F0U) |
| #define DDRC_REGS_RFSHCTL0_refresh_burst_SHIFT (4U) |
| #define DDRC_REGS_RFSHCTL0_refresh_burst(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL0_refresh_burst_SHIFT)) & DDRC_REGS_RFSHCTL0_refresh_burst_MASK) |
| #define DDRC_REGS_RFSHCTL0_refresh_to_x32_MASK (0x1F000U) |
| #define DDRC_REGS_RFSHCTL0_refresh_to_x32_SHIFT (12U) |
| #define DDRC_REGS_RFSHCTL0_refresh_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL0_refresh_to_x32_SHIFT)) & DDRC_REGS_RFSHCTL0_refresh_to_x32_MASK) |
| #define DDRC_REGS_RFSHCTL0_refresh_margin_MASK (0xF00000U) |
| #define DDRC_REGS_RFSHCTL0_refresh_margin_SHIFT (20U) |
| #define DDRC_REGS_RFSHCTL0_refresh_margin(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL0_refresh_margin_SHIFT)) & DDRC_REGS_RFSHCTL0_refresh_margin_MASK) |
| /*! @} */ |
| |
| /*! @name RFSHCTL1 - Refresh Control Register 1 */ |
| /*! @{ */ |
| #define DDRC_REGS_RFSHCTL1_refresh_timer0_start_value_x32_MASK (0xFFFU) |
| #define DDRC_REGS_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT (0U) |
| #define DDRC_REGS_RFSHCTL1_refresh_timer0_start_value_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT)) & DDRC_REGS_RFSHCTL1_refresh_timer0_start_value_x32_MASK) |
| #define DDRC_REGS_RFSHCTL1_refresh_timer1_start_value_x32_MASK (0xFFF0000U) |
| #define DDRC_REGS_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT (16U) |
| #define DDRC_REGS_RFSHCTL1_refresh_timer1_start_value_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT)) & DDRC_REGS_RFSHCTL1_refresh_timer1_start_value_x32_MASK) |
| /*! @} */ |
| |
| /*! @name RFSHCTL3 - Refresh Control Register 3 */ |
| /*! @{ */ |
| #define DDRC_REGS_RFSHCTL3_dis_auto_refresh_MASK (0x1U) |
| #define DDRC_REGS_RFSHCTL3_dis_auto_refresh_SHIFT (0U) |
| #define DDRC_REGS_RFSHCTL3_dis_auto_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL3_dis_auto_refresh_SHIFT)) & DDRC_REGS_RFSHCTL3_dis_auto_refresh_MASK) |
| #define DDRC_REGS_RFSHCTL3_refresh_update_level_MASK (0x2U) |
| #define DDRC_REGS_RFSHCTL3_refresh_update_level_SHIFT (1U) |
| #define DDRC_REGS_RFSHCTL3_refresh_update_level(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL3_refresh_update_level_SHIFT)) & DDRC_REGS_RFSHCTL3_refresh_update_level_MASK) |
| #define DDRC_REGS_RFSHCTL3_refresh_mode_MASK (0x70U) |
| #define DDRC_REGS_RFSHCTL3_refresh_mode_SHIFT (4U) |
| #define DDRC_REGS_RFSHCTL3_refresh_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL3_refresh_mode_SHIFT)) & DDRC_REGS_RFSHCTL3_refresh_mode_MASK) |
| /*! @} */ |
| |
| /*! @name RFSHTMG - Refresh Timing Register */ |
| /*! @{ */ |
| #define DDRC_REGS_RFSHTMG_t_rfc_min_MASK (0x3FFU) |
| #define DDRC_REGS_RFSHTMG_t_rfc_min_SHIFT (0U) |
| #define DDRC_REGS_RFSHTMG_t_rfc_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHTMG_t_rfc_min_SHIFT)) & DDRC_REGS_RFSHTMG_t_rfc_min_MASK) |
| #define DDRC_REGS_RFSHTMG_lpddr3_trefbw_en_MASK (0x8000U) |
| #define DDRC_REGS_RFSHTMG_lpddr3_trefbw_en_SHIFT (15U) |
| #define DDRC_REGS_RFSHTMG_lpddr3_trefbw_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHTMG_lpddr3_trefbw_en_SHIFT)) & DDRC_REGS_RFSHTMG_lpddr3_trefbw_en_MASK) |
| #define DDRC_REGS_RFSHTMG_t_rfc_nom_x32_MASK (0xFFF0000U) |
| #define DDRC_REGS_RFSHTMG_t_rfc_nom_x32_SHIFT (16U) |
| #define DDRC_REGS_RFSHTMG_t_rfc_nom_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHTMG_t_rfc_nom_x32_SHIFT)) & DDRC_REGS_RFSHTMG_t_rfc_nom_x32_MASK) |
| /*! @} */ |
| |
| /*! @name CRCPARCTL0 - CRC Parity Control Register0 */ |
| /*! @{ */ |
| #define DDRC_REGS_CRCPARCTL0_dfi_alert_err_int_en_MASK (0x1U) |
| #define DDRC_REGS_CRCPARCTL0_dfi_alert_err_int_en_SHIFT (0U) |
| #define DDRC_REGS_CRCPARCTL0_dfi_alert_err_int_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_CRCPARCTL0_dfi_alert_err_int_en_SHIFT)) & DDRC_REGS_CRCPARCTL0_dfi_alert_err_int_en_MASK) |
| #define DDRC_REGS_CRCPARCTL0_dfi_alert_err_int_clr_MASK (0x2U) |
| #define DDRC_REGS_CRCPARCTL0_dfi_alert_err_int_clr_SHIFT (1U) |
| #define DDRC_REGS_CRCPARCTL0_dfi_alert_err_int_clr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_CRCPARCTL0_dfi_alert_err_int_clr_SHIFT)) & DDRC_REGS_CRCPARCTL0_dfi_alert_err_int_clr_MASK) |
| #define DDRC_REGS_CRCPARCTL0_dfi_alert_err_cnt_clr_MASK (0x4U) |
| #define DDRC_REGS_CRCPARCTL0_dfi_alert_err_cnt_clr_SHIFT (2U) |
| #define DDRC_REGS_CRCPARCTL0_dfi_alert_err_cnt_clr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_CRCPARCTL0_dfi_alert_err_cnt_clr_SHIFT)) & DDRC_REGS_CRCPARCTL0_dfi_alert_err_cnt_clr_MASK) |
| /*! @} */ |
| |
| /*! @name CRCPARCTL1 - CRC Parity Control Register1 */ |
| /*! @{ */ |
| #define DDRC_REGS_CRCPARCTL1_parity_enable_MASK (0x1U) |
| #define DDRC_REGS_CRCPARCTL1_parity_enable_SHIFT (0U) |
| /*! parity_enable - C/A Parity enable register. If RCD's parity error detection or SDRAM's parity detection is enabled, this register should be 1. |
| * 0b0..Disable generation of C/A parity and disable detection of C/A parity error |
| * 0b1..Enable generation of C/A parity and detection of C/A parity error |
| */ |
| #define DDRC_REGS_CRCPARCTL1_parity_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_CRCPARCTL1_parity_enable_SHIFT)) & DDRC_REGS_CRCPARCTL1_parity_enable_MASK) |
| #define DDRC_REGS_CRCPARCTL1_crc_enable_MASK (0x10U) |
| #define DDRC_REGS_CRCPARCTL1_crc_enable_SHIFT (4U) |
| /*! crc_enable - CRC enable Register. The setting of this register should match the CRC mode register setting in the DRAM. |
| * 0b0..isable generation of CRC |
| * 0b1..Enable generation of CRC |
| */ |
| #define DDRC_REGS_CRCPARCTL1_crc_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_CRCPARCTL1_crc_enable_SHIFT)) & DDRC_REGS_CRCPARCTL1_crc_enable_MASK) |
| #define DDRC_REGS_CRCPARCTL1_crc_inc_dm_MASK (0x80U) |
| #define DDRC_REGS_CRCPARCTL1_crc_inc_dm_SHIFT (7U) |
| /*! crc_inc_dm - CRC Calculation setting register. Present only in designs configured to support DDR4. |
| * 0b0..CRC not includes DM signal |
| * 0b1..CRC includes DM signal |
| */ |
| #define DDRC_REGS_CRCPARCTL1_crc_inc_dm(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_CRCPARCTL1_crc_inc_dm_SHIFT)) & DDRC_REGS_CRCPARCTL1_crc_inc_dm_MASK) |
| #define DDRC_REGS_CRCPARCTL1_caparity_disable_before_sr_MASK (0x1000U) |
| #define DDRC_REGS_CRCPARCTL1_caparity_disable_before_sr_SHIFT (12U) |
| /*! caparity_disable_before_sr - If DDR4-SDRAM's CA parity is enabled by INIT6.mr5[2:0]!=0 and this register is set to 1, CA parity is automatically disabled before Self-Refresh entry and enabled after Self-Refresh exit by issuing MR5. - 1: CA parity is disabled before Self-Refresh entry - 0: CA parity is not disabled before Self-Refresh entry If Geardown is used by MSTR.geardown_mode=1, this register must be set to 1. If this register set to 0, DRAMTMG5.t_ckesr and DRAMTMG5.t_cksre must be increased by PL(Parity latency) |
| * 0b0..CA parity is not disabled before Self-Refresh entry |
| * 0b1..CA parity is disabled before Self-Refresh entry |
| */ |
| #define DDRC_REGS_CRCPARCTL1_caparity_disable_before_sr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_CRCPARCTL1_caparity_disable_before_sr_SHIFT)) & DDRC_REGS_CRCPARCTL1_caparity_disable_before_sr_MASK) |
| /*! @} */ |
| |
| /*! @name CRCPARSTAT - CRC Parity Status Register */ |
| /*! @{ */ |
| #define DDRC_REGS_CRCPARSTAT_dfi_alert_err_cnt_MASK (0xFFFFU) |
| #define DDRC_REGS_CRCPARSTAT_dfi_alert_err_cnt_SHIFT (0U) |
| #define DDRC_REGS_CRCPARSTAT_dfi_alert_err_cnt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_CRCPARSTAT_dfi_alert_err_cnt_SHIFT)) & DDRC_REGS_CRCPARSTAT_dfi_alert_err_cnt_MASK) |
| #define DDRC_REGS_CRCPARSTAT_dfi_alert_err_int_MASK (0x10000U) |
| #define DDRC_REGS_CRCPARSTAT_dfi_alert_err_int_SHIFT (16U) |
| #define DDRC_REGS_CRCPARSTAT_dfi_alert_err_int(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_CRCPARSTAT_dfi_alert_err_int_SHIFT)) & DDRC_REGS_CRCPARSTAT_dfi_alert_err_int_MASK) |
| /*! @} */ |
| |
| /*! @name INIT0 - SDRAM Initialization Register 0 */ |
| /*! @{ */ |
| #define DDRC_REGS_INIT0_pre_cke_x1024_MASK (0xFFFU) |
| #define DDRC_REGS_INIT0_pre_cke_x1024_SHIFT (0U) |
| #define DDRC_REGS_INIT0_pre_cke_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT0_pre_cke_x1024_SHIFT)) & DDRC_REGS_INIT0_pre_cke_x1024_MASK) |
| #define DDRC_REGS_INIT0_post_cke_x1024_MASK (0x3FF0000U) |
| #define DDRC_REGS_INIT0_post_cke_x1024_SHIFT (16U) |
| #define DDRC_REGS_INIT0_post_cke_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT0_post_cke_x1024_SHIFT)) & DDRC_REGS_INIT0_post_cke_x1024_MASK) |
| #define DDRC_REGS_INIT0_skip_dram_init_MASK (0xC0000000U) |
| #define DDRC_REGS_INIT0_skip_dram_init_SHIFT (30U) |
| /*! skip_dram_init - If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Initialization routine is skipped after power-up. Controller starts up in Normal Mode - 11 - SDRAM Initialization routine is skipped after power-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Initialization routine is run after power-up. |
| * 0b00..SDRAM Initialization routine is run after power-up |
| * 0b01..SDRAM Initialization routine is skipped after power-up |
| * 0b10..SDRAM Initialization routine is run after power-up |
| * 0b11..SDRAM Initialization routine is skipped after power-up |
| */ |
| #define DDRC_REGS_INIT0_skip_dram_init(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT0_skip_dram_init_SHIFT)) & DDRC_REGS_INIT0_skip_dram_init_MASK) |
| /*! @} */ |
| |
| /*! @name INIT1 - SDRAM Initialization Register 1 */ |
| /*! @{ */ |
| #define DDRC_REGS_INIT1_pre_ocd_x32_MASK (0xFU) |
| #define DDRC_REGS_INIT1_pre_ocd_x32_SHIFT (0U) |
| #define DDRC_REGS_INIT1_pre_ocd_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT1_pre_ocd_x32_SHIFT)) & DDRC_REGS_INIT1_pre_ocd_x32_MASK) |
| #define DDRC_REGS_INIT1_dram_rstn_x1024_MASK (0x1FF0000U) |
| #define DDRC_REGS_INIT1_dram_rstn_x1024_SHIFT (16U) |
| #define DDRC_REGS_INIT1_dram_rstn_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT1_dram_rstn_x1024_SHIFT)) & DDRC_REGS_INIT1_dram_rstn_x1024_MASK) |
| /*! @} */ |
| |
| /*! @name INIT2 - SDRAM Initialization Register 2 */ |
| /*! @{ */ |
| #define DDRC_REGS_INIT2_min_stable_clock_x1_MASK (0xFU) |
| #define DDRC_REGS_INIT2_min_stable_clock_x1_SHIFT (0U) |
| #define DDRC_REGS_INIT2_min_stable_clock_x1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT2_min_stable_clock_x1_SHIFT)) & DDRC_REGS_INIT2_min_stable_clock_x1_MASK) |
| #define DDRC_REGS_INIT2_idle_after_reset_x32_MASK (0xFF00U) |
| #define DDRC_REGS_INIT2_idle_after_reset_x32_SHIFT (8U) |
| #define DDRC_REGS_INIT2_idle_after_reset_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT2_idle_after_reset_x32_SHIFT)) & DDRC_REGS_INIT2_idle_after_reset_x32_MASK) |
| /*! @} */ |
| |
| /*! @name INIT3 - SDRAM Initialization Register 3 */ |
| /*! @{ */ |
| #define DDRC_REGS_INIT3_emr_MASK (0xFFFFU) |
| #define DDRC_REGS_INIT3_emr_SHIFT (0U) |
| #define DDRC_REGS_INIT3_emr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT3_emr_SHIFT)) & DDRC_REGS_INIT3_emr_MASK) |
| #define DDRC_REGS_INIT3_mr_MASK (0xFFFF0000U) |
| #define DDRC_REGS_INIT3_mr_SHIFT (16U) |
| #define DDRC_REGS_INIT3_mr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT3_mr_SHIFT)) & DDRC_REGS_INIT3_mr_MASK) |
| /*! @} */ |
| |
| /*! @name INIT4 - SDRAM Initialization Register 4 */ |
| /*! @{ */ |
| #define DDRC_REGS_INIT4_emr3_MASK (0xFFFFU) |
| #define DDRC_REGS_INIT4_emr3_SHIFT (0U) |
| #define DDRC_REGS_INIT4_emr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT4_emr3_SHIFT)) & DDRC_REGS_INIT4_emr3_MASK) |
| #define DDRC_REGS_INIT4_emr2_MASK (0xFFFF0000U) |
| #define DDRC_REGS_INIT4_emr2_SHIFT (16U) |
| #define DDRC_REGS_INIT4_emr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT4_emr2_SHIFT)) & DDRC_REGS_INIT4_emr2_MASK) |
| /*! @} */ |
| |
| /*! @name INIT5 - SDRAM Initialization Register 5 */ |
| /*! @{ */ |
| #define DDRC_REGS_INIT5_max_auto_init_x1024_MASK (0x3FFU) |
| #define DDRC_REGS_INIT5_max_auto_init_x1024_SHIFT (0U) |
| #define DDRC_REGS_INIT5_max_auto_init_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT5_max_auto_init_x1024_SHIFT)) & DDRC_REGS_INIT5_max_auto_init_x1024_MASK) |
| #define DDRC_REGS_INIT5_dev_zqinit_x32_MASK (0xFF0000U) |
| #define DDRC_REGS_INIT5_dev_zqinit_x32_SHIFT (16U) |
| #define DDRC_REGS_INIT5_dev_zqinit_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT5_dev_zqinit_x32_SHIFT)) & DDRC_REGS_INIT5_dev_zqinit_x32_MASK) |
| /*! @} */ |
| |
| /*! @name INIT6 - SDRAM Initialization Register 6 */ |
| /*! @{ */ |
| #define DDRC_REGS_INIT6_mr5_MASK (0xFFFFU) |
| #define DDRC_REGS_INIT6_mr5_SHIFT (0U) |
| #define DDRC_REGS_INIT6_mr5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT6_mr5_SHIFT)) & DDRC_REGS_INIT6_mr5_MASK) |
| #define DDRC_REGS_INIT6_mr4_MASK (0xFFFF0000U) |
| #define DDRC_REGS_INIT6_mr4_SHIFT (16U) |
| #define DDRC_REGS_INIT6_mr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT6_mr4_SHIFT)) & DDRC_REGS_INIT6_mr4_MASK) |
| /*! @} */ |
| |
| /*! @name INIT7 - SDRAM Initialization Register 7 */ |
| /*! @{ */ |
| #define DDRC_REGS_INIT7_mr6_MASK (0xFFFF0000U) |
| #define DDRC_REGS_INIT7_mr6_SHIFT (16U) |
| #define DDRC_REGS_INIT7_mr6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT7_mr6_SHIFT)) & DDRC_REGS_INIT7_mr6_MASK) |
| /*! @} */ |
| |
| /*! @name DIMMCTL - DIMM Control Register */ |
| /*! @{ */ |
| #define DDRC_REGS_DIMMCTL_dimm_stagger_cs_en_MASK (0x1U) |
| #define DDRC_REGS_DIMMCTL_dimm_stagger_cs_en_SHIFT (0U) |
| /*! dimm_stagger_cs_en - Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs.Even if this bit is set it does not take care of software driven MR commands (via MRCTRL0/MRCTRL1), where software is responsible to send them to separate ranks as appropriate. |
| * 0b0..Do not stagger accesses |
| * 0b1..(non-DDR4) Send all commands to even and odd ranks separately |
| * 0b1..(DDR4) Send MRS commands to each ranks separately |
| */ |
| #define DDRC_REGS_DIMMCTL_dimm_stagger_cs_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DIMMCTL_dimm_stagger_cs_en_SHIFT)) & DDRC_REGS_DIMMCTL_dimm_stagger_cs_en_MASK) |
| #define DDRC_REGS_DIMMCTL_dimm_addr_mirr_en_MASK (0x2U) |
| #define DDRC_REGS_DIMMCTL_dimm_addr_mirr_en_SHIFT (1U) |
| /*! dimm_addr_mirr_en - Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures that, for mode register accesses during the automatic initialization routine, these bits are swapped within the DDRC to compensate for this UDIMM/RDIMM/LRDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM/LRDIMM, they are swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1. |
| * 0b0..Do not implement address mirroring |
| * 0b1..For odd ranks, implement address mirroring for MRS commands to during initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM/LRDIMM implements address mirroring) |
| */ |
| #define DDRC_REGS_DIMMCTL_dimm_addr_mirr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DIMMCTL_dimm_addr_mirr_en_SHIFT)) & DDRC_REGS_DIMMCTL_dimm_addr_mirr_en_MASK) |
| #define DDRC_REGS_DIMMCTL_dimm_output_inv_en_MASK (0x4U) |
| #define DDRC_REGS_DIMMCTL_dimm_output_inv_en_SHIFT (2U) |
| /*! dimm_output_inv_en - Output Inversion Enable (for DDR4 RDIMM/LRDIMM implementations only). DDR4 RDIMM/LRDIMM implements the Output Inversion feature by default, which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the DDRC during the automatic initialization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated. For B-side mode register accesses, these bits are inverted within the DDRC to compensate for this RDIMM/LRDIMM inversion. It is recommended to set this bit always, if using DDR4 RDIMMs/LRDIMMs. Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. |
| * 0b0..Do not implement output inversion for B-side DRAMs. |
| * 0b1..Implement output inversion for B-side DRAMs. |
| */ |
| #define DDRC_REGS_DIMMCTL_dimm_output_inv_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DIMMCTL_dimm_output_inv_en_SHIFT)) & DDRC_REGS_DIMMCTL_dimm_output_inv_en_MASK) |
| #define DDRC_REGS_DIMMCTL_mrs_a17_en_MASK (0x8U) |
| #define DDRC_REGS_DIMMCTL_mrs_a17_en_SHIFT (3U) |
| /*! mrs_a17_en - Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled, this must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. |
| * 0b0..Disabled |
| * 0b1..Enabled |
| */ |
| #define DDRC_REGS_DIMMCTL_mrs_a17_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DIMMCTL_mrs_a17_en_SHIFT)) & DDRC_REGS_DIMMCTL_mrs_a17_en_MASK) |
| #define DDRC_REGS_DIMMCTL_mrs_bg1_en_MASK (0x10U) |
| #define DDRC_REGS_DIMMCTL_mrs_bg1_en_SHIFT (4U) |
| /*! mrs_bg1_en - Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output Inversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is enabled, this is applied to BG1 of even ranks and BG0 of odd ranks. |
| * 0b0..Disabled |
| * 0b1..Enabled |
| */ |
| #define DDRC_REGS_DIMMCTL_mrs_bg1_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DIMMCTL_mrs_bg1_en_SHIFT)) & DDRC_REGS_DIMMCTL_mrs_bg1_en_MASK) |
| #define DDRC_REGS_DIMMCTL_dimm_dis_bg_mirroring_MASK (0x20U) |
| #define DDRC_REGS_DIMMCTL_dimm_dis_bg_mirroring_SHIFT (5U) |
| /*! dimm_dis_bg_mirroring - Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enabled. This will be required for DDR4 DIMMs with x16 devices. |
| * 0b0..BG0 and BG1 are swapped if address mirroring is enabled. |
| * 0b1..BG0 and BG1 are NOT swapped. |
| */ |
| #define DDRC_REGS_DIMMCTL_dimm_dis_bg_mirroring(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DIMMCTL_dimm_dis_bg_mirroring_SHIFT)) & DDRC_REGS_DIMMCTL_dimm_dis_bg_mirroring_MASK) |
| #define DDRC_REGS_DIMMCTL_lrdimm_bcom_cmd_prot_MASK (0x40U) |
| #define DDRC_REGS_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT (6U) |
| #define DDRC_REGS_DIMMCTL_lrdimm_bcom_cmd_prot(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT)) & DDRC_REGS_DIMMCTL_lrdimm_bcom_cmd_prot_MASK) |
| /*! @} */ |
| |
| /*! @name RANKCTL - Rank Control Register */ |
| /*! @{ */ |
| #define DDRC_REGS_RANKCTL_max_rank_rd_MASK (0xFU) |
| #define DDRC_REGS_RANKCTL_max_rank_rd_SHIFT (0U) |
| #define DDRC_REGS_RANKCTL_max_rank_rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RANKCTL_max_rank_rd_SHIFT)) & DDRC_REGS_RANKCTL_max_rank_rd_MASK) |
| #define DDRC_REGS_RANKCTL_diff_rank_rd_gap_MASK (0xF0U) |
| #define DDRC_REGS_RANKCTL_diff_rank_rd_gap_SHIFT (4U) |
| #define DDRC_REGS_RANKCTL_diff_rank_rd_gap(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RANKCTL_diff_rank_rd_gap_SHIFT)) & DDRC_REGS_RANKCTL_diff_rank_rd_gap_MASK) |
| #define DDRC_REGS_RANKCTL_diff_rank_wr_gap_MASK (0xF00U) |
| #define DDRC_REGS_RANKCTL_diff_rank_wr_gap_SHIFT (8U) |
| #define DDRC_REGS_RANKCTL_diff_rank_wr_gap(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RANKCTL_diff_rank_wr_gap_SHIFT)) & DDRC_REGS_RANKCTL_diff_rank_wr_gap_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG0 - SDRAM Timing Register 0 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG0_t_ras_min_MASK (0x3FU) |
| #define DDRC_REGS_DRAMTMG0_t_ras_min_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG0_t_ras_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG0_t_ras_min_SHIFT)) & DDRC_REGS_DRAMTMG0_t_ras_min_MASK) |
| #define DDRC_REGS_DRAMTMG0_t_ras_max_MASK (0x7F00U) |
| #define DDRC_REGS_DRAMTMG0_t_ras_max_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG0_t_ras_max(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG0_t_ras_max_SHIFT)) & DDRC_REGS_DRAMTMG0_t_ras_max_MASK) |
| #define DDRC_REGS_DRAMTMG0_t_faw_MASK (0x3F0000U) |
| #define DDRC_REGS_DRAMTMG0_t_faw_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG0_t_faw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG0_t_faw_SHIFT)) & DDRC_REGS_DRAMTMG0_t_faw_MASK) |
| #define DDRC_REGS_DRAMTMG0_wr2pre_MASK (0x7F000000U) |
| #define DDRC_REGS_DRAMTMG0_wr2pre_SHIFT (24U) |
| #define DDRC_REGS_DRAMTMG0_wr2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG0_wr2pre_SHIFT)) & DDRC_REGS_DRAMTMG0_wr2pre_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG1 - SDRAM Timing Register 1 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG1_t_rc_MASK (0x7FU) |
| #define DDRC_REGS_DRAMTMG1_t_rc_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG1_t_rc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG1_t_rc_SHIFT)) & DDRC_REGS_DRAMTMG1_t_rc_MASK) |
| #define DDRC_REGS_DRAMTMG1_rd2pre_MASK (0x3F00U) |
| #define DDRC_REGS_DRAMTMG1_rd2pre_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG1_rd2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG1_rd2pre_SHIFT)) & DDRC_REGS_DRAMTMG1_rd2pre_MASK) |
| #define DDRC_REGS_DRAMTMG1_t_xp_MASK (0x1F0000U) |
| #define DDRC_REGS_DRAMTMG1_t_xp_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG1_t_xp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG1_t_xp_SHIFT)) & DDRC_REGS_DRAMTMG1_t_xp_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG2 - SDRAM Timing Register 2 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG2_wr2rd_MASK (0x3FU) |
| #define DDRC_REGS_DRAMTMG2_wr2rd_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG2_wr2rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG2_wr2rd_SHIFT)) & DDRC_REGS_DRAMTMG2_wr2rd_MASK) |
| #define DDRC_REGS_DRAMTMG2_rd2wr_MASK (0x3F00U) |
| #define DDRC_REGS_DRAMTMG2_rd2wr_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG2_rd2wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG2_rd2wr_SHIFT)) & DDRC_REGS_DRAMTMG2_rd2wr_MASK) |
| #define DDRC_REGS_DRAMTMG2_read_latency_MASK (0x3F0000U) |
| #define DDRC_REGS_DRAMTMG2_read_latency_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG2_read_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG2_read_latency_SHIFT)) & DDRC_REGS_DRAMTMG2_read_latency_MASK) |
| #define DDRC_REGS_DRAMTMG2_write_latency_MASK (0x3F000000U) |
| #define DDRC_REGS_DRAMTMG2_write_latency_SHIFT (24U) |
| #define DDRC_REGS_DRAMTMG2_write_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG2_write_latency_SHIFT)) & DDRC_REGS_DRAMTMG2_write_latency_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG3 - SDRAM Timing Register 3 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG3_t_mod_MASK (0x3FFU) |
| #define DDRC_REGS_DRAMTMG3_t_mod_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG3_t_mod(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG3_t_mod_SHIFT)) & DDRC_REGS_DRAMTMG3_t_mod_MASK) |
| #define DDRC_REGS_DRAMTMG3_t_mrd_MASK (0x3F000U) |
| #define DDRC_REGS_DRAMTMG3_t_mrd_SHIFT (12U) |
| #define DDRC_REGS_DRAMTMG3_t_mrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG3_t_mrd_SHIFT)) & DDRC_REGS_DRAMTMG3_t_mrd_MASK) |
| #define DDRC_REGS_DRAMTMG3_t_mrw_MASK (0x3FF00000U) |
| #define DDRC_REGS_DRAMTMG3_t_mrw_SHIFT (20U) |
| #define DDRC_REGS_DRAMTMG3_t_mrw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG3_t_mrw_SHIFT)) & DDRC_REGS_DRAMTMG3_t_mrw_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG4 - SDRAM Timing Register 4 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG4_t_rp_MASK (0x1FU) |
| #define DDRC_REGS_DRAMTMG4_t_rp_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG4_t_rp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG4_t_rp_SHIFT)) & DDRC_REGS_DRAMTMG4_t_rp_MASK) |
| #define DDRC_REGS_DRAMTMG4_t_rrd_MASK (0xF00U) |
| #define DDRC_REGS_DRAMTMG4_t_rrd_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG4_t_rrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG4_t_rrd_SHIFT)) & DDRC_REGS_DRAMTMG4_t_rrd_MASK) |
| #define DDRC_REGS_DRAMTMG4_t_ccd_MASK (0xF0000U) |
| #define DDRC_REGS_DRAMTMG4_t_ccd_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG4_t_ccd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG4_t_ccd_SHIFT)) & DDRC_REGS_DRAMTMG4_t_ccd_MASK) |
| #define DDRC_REGS_DRAMTMG4_t_rcd_MASK (0x1F000000U) |
| #define DDRC_REGS_DRAMTMG4_t_rcd_SHIFT (24U) |
| #define DDRC_REGS_DRAMTMG4_t_rcd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG4_t_rcd_SHIFT)) & DDRC_REGS_DRAMTMG4_t_rcd_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG5 - SDRAM Timing Register 5 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG5_t_cke_MASK (0x1FU) |
| #define DDRC_REGS_DRAMTMG5_t_cke_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG5_t_cke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG5_t_cke_SHIFT)) & DDRC_REGS_DRAMTMG5_t_cke_MASK) |
| #define DDRC_REGS_DRAMTMG5_t_ckesr_MASK (0x3F00U) |
| #define DDRC_REGS_DRAMTMG5_t_ckesr_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG5_t_ckesr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG5_t_ckesr_SHIFT)) & DDRC_REGS_DRAMTMG5_t_ckesr_MASK) |
| #define DDRC_REGS_DRAMTMG5_t_cksre_MASK (0xF0000U) |
| #define DDRC_REGS_DRAMTMG5_t_cksre_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG5_t_cksre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG5_t_cksre_SHIFT)) & DDRC_REGS_DRAMTMG5_t_cksre_MASK) |
| #define DDRC_REGS_DRAMTMG5_t_cksrx_MASK (0xF000000U) |
| #define DDRC_REGS_DRAMTMG5_t_cksrx_SHIFT (24U) |
| #define DDRC_REGS_DRAMTMG5_t_cksrx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG5_t_cksrx_SHIFT)) & DDRC_REGS_DRAMTMG5_t_cksrx_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG6 - SDRAM Timing Register 6 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG6_t_ckcsx_MASK (0xFU) |
| #define DDRC_REGS_DRAMTMG6_t_ckcsx_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG6_t_ckcsx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG6_t_ckcsx_SHIFT)) & DDRC_REGS_DRAMTMG6_t_ckcsx_MASK) |
| #define DDRC_REGS_DRAMTMG6_t_ckdpdx_MASK (0xF0000U) |
| #define DDRC_REGS_DRAMTMG6_t_ckdpdx_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG6_t_ckdpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG6_t_ckdpdx_SHIFT)) & DDRC_REGS_DRAMTMG6_t_ckdpdx_MASK) |
| #define DDRC_REGS_DRAMTMG6_t_ckdpde_MASK (0xF000000U) |
| #define DDRC_REGS_DRAMTMG6_t_ckdpde_SHIFT (24U) |
| #define DDRC_REGS_DRAMTMG6_t_ckdpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG6_t_ckdpde_SHIFT)) & DDRC_REGS_DRAMTMG6_t_ckdpde_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG7 - SDRAM Timing Register 7 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG7_t_ckpdx_MASK (0xFU) |
| #define DDRC_REGS_DRAMTMG7_t_ckpdx_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG7_t_ckpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG7_t_ckpdx_SHIFT)) & DDRC_REGS_DRAMTMG7_t_ckpdx_MASK) |
| #define DDRC_REGS_DRAMTMG7_t_ckpde_MASK (0xF00U) |
| #define DDRC_REGS_DRAMTMG7_t_ckpde_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG7_t_ckpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG7_t_ckpde_SHIFT)) & DDRC_REGS_DRAMTMG7_t_ckpde_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG8 - SDRAM Timing Register 8 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG8_t_xs_x32_MASK (0x7FU) |
| #define DDRC_REGS_DRAMTMG8_t_xs_x32_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG8_t_xs_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG8_t_xs_x32_SHIFT)) & DDRC_REGS_DRAMTMG8_t_xs_x32_MASK) |
| #define DDRC_REGS_DRAMTMG8_t_xs_dll_x32_MASK (0x7F00U) |
| #define DDRC_REGS_DRAMTMG8_t_xs_dll_x32_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG8_t_xs_dll_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG8_t_xs_dll_x32_SHIFT)) & DDRC_REGS_DRAMTMG8_t_xs_dll_x32_MASK) |
| #define DDRC_REGS_DRAMTMG8_t_xs_abort_x32_MASK (0x7F0000U) |
| #define DDRC_REGS_DRAMTMG8_t_xs_abort_x32_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG8_t_xs_abort_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG8_t_xs_abort_x32_SHIFT)) & DDRC_REGS_DRAMTMG8_t_xs_abort_x32_MASK) |
| #define DDRC_REGS_DRAMTMG8_t_xs_fast_x32_MASK (0x7F000000U) |
| #define DDRC_REGS_DRAMTMG8_t_xs_fast_x32_SHIFT (24U) |
| #define DDRC_REGS_DRAMTMG8_t_xs_fast_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG8_t_xs_fast_x32_SHIFT)) & DDRC_REGS_DRAMTMG8_t_xs_fast_x32_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG9 - SDRAM Timing Register 9 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG9_wr2rd_s_MASK (0x3FU) |
| #define DDRC_REGS_DRAMTMG9_wr2rd_s_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG9_wr2rd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG9_wr2rd_s_SHIFT)) & DDRC_REGS_DRAMTMG9_wr2rd_s_MASK) |
| #define DDRC_REGS_DRAMTMG9_t_rrd_s_MASK (0xF00U) |
| #define DDRC_REGS_DRAMTMG9_t_rrd_s_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG9_t_rrd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG9_t_rrd_s_SHIFT)) & DDRC_REGS_DRAMTMG9_t_rrd_s_MASK) |
| #define DDRC_REGS_DRAMTMG9_t_ccd_s_MASK (0x70000U) |
| #define DDRC_REGS_DRAMTMG9_t_ccd_s_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG9_t_ccd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG9_t_ccd_s_SHIFT)) & DDRC_REGS_DRAMTMG9_t_ccd_s_MASK) |
| #define DDRC_REGS_DRAMTMG9_ddr4_wr_preamble_MASK (0x40000000U) |
| #define DDRC_REGS_DRAMTMG9_ddr4_wr_preamble_SHIFT (30U) |
| #define DDRC_REGS_DRAMTMG9_ddr4_wr_preamble(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG9_ddr4_wr_preamble_SHIFT)) & DDRC_REGS_DRAMTMG9_ddr4_wr_preamble_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG10 - SDRAM Timing Register 10 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG10_t_gear_hold_MASK (0x3U) |
| #define DDRC_REGS_DRAMTMG10_t_gear_hold_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG10_t_gear_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG10_t_gear_hold_SHIFT)) & DDRC_REGS_DRAMTMG10_t_gear_hold_MASK) |
| #define DDRC_REGS_DRAMTMG10_t_gear_setup_MASK (0xCU) |
| #define DDRC_REGS_DRAMTMG10_t_gear_setup_SHIFT (2U) |
| #define DDRC_REGS_DRAMTMG10_t_gear_setup(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG10_t_gear_setup_SHIFT)) & DDRC_REGS_DRAMTMG10_t_gear_setup_MASK) |
| #define DDRC_REGS_DRAMTMG10_t_cmd_gear_MASK (0x1F00U) |
| #define DDRC_REGS_DRAMTMG10_t_cmd_gear_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG10_t_cmd_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG10_t_cmd_gear_SHIFT)) & DDRC_REGS_DRAMTMG10_t_cmd_gear_MASK) |
| #define DDRC_REGS_DRAMTMG10_t_sync_gear_MASK (0x1F0000U) |
| #define DDRC_REGS_DRAMTMG10_t_sync_gear_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG10_t_sync_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG10_t_sync_gear_SHIFT)) & DDRC_REGS_DRAMTMG10_t_sync_gear_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG11 - SDRAM Timing Register 11 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG11_t_ckmpe_MASK (0x1FU) |
| #define DDRC_REGS_DRAMTMG11_t_ckmpe_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG11_t_ckmpe(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG11_t_ckmpe_SHIFT)) & DDRC_REGS_DRAMTMG11_t_ckmpe_MASK) |
| #define DDRC_REGS_DRAMTMG11_t_mpx_s_MASK (0x300U) |
| #define DDRC_REGS_DRAMTMG11_t_mpx_s_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG11_t_mpx_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG11_t_mpx_s_SHIFT)) & DDRC_REGS_DRAMTMG11_t_mpx_s_MASK) |
| #define DDRC_REGS_DRAMTMG11_t_mpx_lh_MASK (0x1F0000U) |
| #define DDRC_REGS_DRAMTMG11_t_mpx_lh_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG11_t_mpx_lh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG11_t_mpx_lh_SHIFT)) & DDRC_REGS_DRAMTMG11_t_mpx_lh_MASK) |
| #define DDRC_REGS_DRAMTMG11_post_mpsm_gap_x32_MASK (0x7F000000U) |
| #define DDRC_REGS_DRAMTMG11_post_mpsm_gap_x32_SHIFT (24U) |
| #define DDRC_REGS_DRAMTMG11_post_mpsm_gap_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG11_post_mpsm_gap_x32_SHIFT)) & DDRC_REGS_DRAMTMG11_post_mpsm_gap_x32_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG12 - SDRAM Timing Register 12 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG12_t_mrd_pda_MASK (0x1FU) |
| #define DDRC_REGS_DRAMTMG12_t_mrd_pda_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG12_t_mrd_pda(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG12_t_mrd_pda_SHIFT)) & DDRC_REGS_DRAMTMG12_t_mrd_pda_MASK) |
| #define DDRC_REGS_DRAMTMG12_t_ckehcmd_MASK (0xF00U) |
| #define DDRC_REGS_DRAMTMG12_t_ckehcmd_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG12_t_ckehcmd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG12_t_ckehcmd_SHIFT)) & DDRC_REGS_DRAMTMG12_t_ckehcmd_MASK) |
| #define DDRC_REGS_DRAMTMG12_t_cmdcke_MASK (0x30000U) |
| #define DDRC_REGS_DRAMTMG12_t_cmdcke_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG12_t_cmdcke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG12_t_cmdcke_SHIFT)) & DDRC_REGS_DRAMTMG12_t_cmdcke_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG13 - SDRAM Timing Register 13 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG13_t_ppd_MASK (0x7U) |
| #define DDRC_REGS_DRAMTMG13_t_ppd_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG13_t_ppd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG13_t_ppd_SHIFT)) & DDRC_REGS_DRAMTMG13_t_ppd_MASK) |
| #define DDRC_REGS_DRAMTMG13_t_ccd_mw_MASK (0x3F0000U) |
| #define DDRC_REGS_DRAMTMG13_t_ccd_mw_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG13_t_ccd_mw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG13_t_ccd_mw_SHIFT)) & DDRC_REGS_DRAMTMG13_t_ccd_mw_MASK) |
| #define DDRC_REGS_DRAMTMG13_odtloff_MASK (0x7F000000U) |
| #define DDRC_REGS_DRAMTMG13_odtloff_SHIFT (24U) |
| #define DDRC_REGS_DRAMTMG13_odtloff(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG13_odtloff_SHIFT)) & DDRC_REGS_DRAMTMG13_odtloff_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG14 - SDRAM Timing Register 14 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG14_t_xsr_MASK (0xFFFU) |
| #define DDRC_REGS_DRAMTMG14_t_xsr_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG14_t_xsr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG14_t_xsr_SHIFT)) & DDRC_REGS_DRAMTMG14_t_xsr_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG15 - SDRAM Timing Register 15 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG15_t_stab_x32_MASK (0xFFU) |
| #define DDRC_REGS_DRAMTMG15_t_stab_x32_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG15_t_stab_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG15_t_stab_x32_SHIFT)) & DDRC_REGS_DRAMTMG15_t_stab_x32_MASK) |
| #define DDRC_REGS_DRAMTMG15_en_dfi_lp_t_stab_MASK (0x80000000U) |
| #define DDRC_REGS_DRAMTMG15_en_dfi_lp_t_stab_SHIFT (31U) |
| /*! en_dfi_lp_t_stab - Enable DFI tSTAB |
| * 0b0..Disable using tSTAB when exiting DFI LP |
| * 0b1..Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. |
| */ |
| #define DDRC_REGS_DRAMTMG15_en_dfi_lp_t_stab(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG15_en_dfi_lp_t_stab_SHIFT)) & DDRC_REGS_DRAMTMG15_en_dfi_lp_t_stab_MASK) |
| /*! @} */ |
| |
| /*! @name ZQCTL0 - ZQ Control Register 0 */ |
| /*! @{ */ |
| #define DDRC_REGS_ZQCTL0_t_zq_short_nop_MASK (0x3FFU) |
| #define DDRC_REGS_ZQCTL0_t_zq_short_nop_SHIFT (0U) |
| #define DDRC_REGS_ZQCTL0_t_zq_short_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_t_zq_short_nop_SHIFT)) & DDRC_REGS_ZQCTL0_t_zq_short_nop_MASK) |
| #define DDRC_REGS_ZQCTL0_t_zq_long_nop_MASK (0x7FF0000U) |
| #define DDRC_REGS_ZQCTL0_t_zq_long_nop_SHIFT (16U) |
| #define DDRC_REGS_ZQCTL0_t_zq_long_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_t_zq_long_nop_SHIFT)) & DDRC_REGS_ZQCTL0_t_zq_long_nop_MASK) |
| #define DDRC_REGS_ZQCTL0_dis_mpsmx_zqcl_MASK (0x10000000U) |
| #define DDRC_REGS_ZQCTL0_dis_mpsmx_zqcl_SHIFT (28U) |
| /*! dis_mpsmx_zqcl - Do not issue ZQCL command at Maximum Power Save Mode exit if the DDRC_SHARED_AC configuration parameter is set. Program it to 1'b1. The software can send ZQCS after exiting MPSM mode. |
| * 0b0..Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for designs supporting DDR4 devices. |
| * 0b1..Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. |
| */ |
| #define DDRC_REGS_ZQCTL0_dis_mpsmx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_dis_mpsmx_zqcl_SHIFT)) & DDRC_REGS_ZQCTL0_dis_mpsmx_zqcl_MASK) |
| #define DDRC_REGS_ZQCTL0_zq_resistor_shared_MASK (0x20000000U) |
| #define DDRC_REGS_ZQCTL0_zq_resistor_shared_SHIFT (29U) |
| /*! zq_resistor_shared - ZQ resistor sharing |
| * 0b0..ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. |
| * 0b1..Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. |
| */ |
| #define DDRC_REGS_ZQCTL0_zq_resistor_shared(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_zq_resistor_shared_SHIFT)) & DDRC_REGS_ZQCTL0_zq_resistor_shared_MASK) |
| #define DDRC_REGS_ZQCTL0_dis_srx_zqcl_MASK (0x40000000U) |
| #define DDRC_REGS_ZQCTL0_dis_srx_zqcl_SHIFT (30U) |
| /*! dis_srx_zqcl - Disable ZQCL/MPC |
| * 0b0..Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. |
| * 0b1..Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. |
| */ |
| #define DDRC_REGS_ZQCTL0_dis_srx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_dis_srx_zqcl_SHIFT)) & DDRC_REGS_ZQCTL0_dis_srx_zqcl_MASK) |
| #define DDRC_REGS_ZQCTL0_dis_auto_zq_MASK (0x80000000U) |
| #define DDRC_REGS_ZQCTL0_dis_auto_zq_SHIFT (31U) |
| /*! dis_auto_zq - Disable Auto ZQCS/MPC |
| * 0b0..Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024. |
| * 0b1..Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. |
| */ |
| #define DDRC_REGS_ZQCTL0_dis_auto_zq(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_dis_auto_zq_SHIFT)) & DDRC_REGS_ZQCTL0_dis_auto_zq_MASK) |
| /*! @} */ |
| |
| /*! @name ZQCTL1 - ZQ Control Register 1 */ |
| /*! @{ */ |
| #define DDRC_REGS_ZQCTL1_t_zq_short_interval_x1024_MASK (0xFFFFFU) |
| #define DDRC_REGS_ZQCTL1_t_zq_short_interval_x1024_SHIFT (0U) |
| #define DDRC_REGS_ZQCTL1_t_zq_short_interval_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL1_t_zq_short_interval_x1024_SHIFT)) & DDRC_REGS_ZQCTL1_t_zq_short_interval_x1024_MASK) |
| #define DDRC_REGS_ZQCTL1_t_zq_reset_nop_MASK (0x3FF00000U) |
| #define DDRC_REGS_ZQCTL1_t_zq_reset_nop_SHIFT (20U) |
| #define DDRC_REGS_ZQCTL1_t_zq_reset_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL1_t_zq_reset_nop_SHIFT)) & DDRC_REGS_ZQCTL1_t_zq_reset_nop_MASK) |
| /*! @} */ |
| |
| /*! @name ZQCTL2 - ZQ Control Register 2 */ |
| /*! @{ */ |
| #define DDRC_REGS_ZQCTL2_zq_reset_MASK (0x1U) |
| #define DDRC_REGS_ZQCTL2_zq_reset_SHIFT (0U) |
| #define DDRC_REGS_ZQCTL2_zq_reset(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL2_zq_reset_SHIFT)) & DDRC_REGS_ZQCTL2_zq_reset_MASK) |
| /*! @} */ |
| |
| /*! @name ZQSTAT - ZQ Status Register */ |
| /*! @{ */ |
| #define DDRC_REGS_ZQSTAT_zq_reset_busy_MASK (0x1U) |
| #define DDRC_REGS_ZQSTAT_zq_reset_busy_SHIFT (0U) |
| /*! zq_reset_busy - SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRC accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. |
| * 0b0..Indicates that the SoC core can initiate a ZQ Reset operation |
| * 0b1..Indicates that ZQ Reset operation is in progress |
| */ |
| #define DDRC_REGS_ZQSTAT_zq_reset_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQSTAT_zq_reset_busy_SHIFT)) & DDRC_REGS_ZQSTAT_zq_reset_busy_MASK) |
| /*! @} */ |
| |
| /*! @name DFITMG0 - DFI Timing Register 0 */ |
| /*! @{ */ |
| #define DDRC_REGS_DFITMG0_dfi_tphy_wrlat_MASK (0x3FU) |
| #define DDRC_REGS_DFITMG0_dfi_tphy_wrlat_SHIFT (0U) |
| #define DDRC_REGS_DFITMG0_dfi_tphy_wrlat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_dfi_tphy_wrlat_SHIFT)) & DDRC_REGS_DFITMG0_dfi_tphy_wrlat_MASK) |
| #define DDRC_REGS_DFITMG0_dfi_tphy_wrdata_MASK (0x3F00U) |
| #define DDRC_REGS_DFITMG0_dfi_tphy_wrdata_SHIFT (8U) |
| #define DDRC_REGS_DFITMG0_dfi_tphy_wrdata(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_dfi_tphy_wrdata_SHIFT)) & DDRC_REGS_DFITMG0_dfi_tphy_wrdata_MASK) |
| #define DDRC_REGS_DFITMG0_dfi_wrdata_use_sdr_MASK (0x8000U) |
| #define DDRC_REGS_DFITMG0_dfi_wrdata_use_sdr_SHIFT (15U) |
| #define DDRC_REGS_DFITMG0_dfi_wrdata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_dfi_wrdata_use_sdr_SHIFT)) & DDRC_REGS_DFITMG0_dfi_wrdata_use_sdr_MASK) |
| #define DDRC_REGS_DFITMG0_dfi_t_rddata_en_MASK (0x7F0000U) |
| #define DDRC_REGS_DFITMG0_dfi_t_rddata_en_SHIFT (16U) |
| #define DDRC_REGS_DFITMG0_dfi_t_rddata_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_dfi_t_rddata_en_SHIFT)) & DDRC_REGS_DFITMG0_dfi_t_rddata_en_MASK) |
| #define DDRC_REGS_DFITMG0_dfi_rddata_use_sdr_MASK (0x800000U) |
| #define DDRC_REGS_DFITMG0_dfi_rddata_use_sdr_SHIFT (23U) |
| #define DDRC_REGS_DFITMG0_dfi_rddata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_dfi_rddata_use_sdr_SHIFT)) & DDRC_REGS_DFITMG0_dfi_rddata_use_sdr_MASK) |
| #define DDRC_REGS_DFITMG0_dfi_t_ctrl_delay_MASK (0x1F000000U) |
| #define DDRC_REGS_DFITMG0_dfi_t_ctrl_delay_SHIFT (24U) |
| #define DDRC_REGS_DFITMG0_dfi_t_ctrl_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_dfi_t_ctrl_delay_SHIFT)) & DDRC_REGS_DFITMG0_dfi_t_ctrl_delay_MASK) |
| /*! @} */ |
| |
| /*! @name DFITMG1 - DFI Timing Register 1 */ |
| /*! @{ */ |
| #define DDRC_REGS_DFITMG1_dfi_t_dram_clk_enable_MASK (0x1FU) |
| #define DDRC_REGS_DFITMG1_dfi_t_dram_clk_enable_SHIFT (0U) |
| #define DDRC_REGS_DFITMG1_dfi_t_dram_clk_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG1_dfi_t_dram_clk_enable_SHIFT)) & DDRC_REGS_DFITMG1_dfi_t_dram_clk_enable_MASK) |
| #define DDRC_REGS_DFITMG1_dfi_t_dram_clk_disable_MASK (0x1F00U) |
| #define DDRC_REGS_DFITMG1_dfi_t_dram_clk_disable_SHIFT (8U) |
| #define DDRC_REGS_DFITMG1_dfi_t_dram_clk_disable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG1_dfi_t_dram_clk_disable_SHIFT)) & DDRC_REGS_DFITMG1_dfi_t_dram_clk_disable_MASK) |
| #define DDRC_REGS_DFITMG1_dfi_t_wrdata_delay_MASK (0x1F0000U) |
| #define DDRC_REGS_DFITMG1_dfi_t_wrdata_delay_SHIFT (16U) |
| #define DDRC_REGS_DFITMG1_dfi_t_wrdata_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG1_dfi_t_wrdata_delay_SHIFT)) & DDRC_REGS_DFITMG1_dfi_t_wrdata_delay_MASK) |
| #define DDRC_REGS_DFITMG1_dfi_t_parin_lat_MASK (0x3000000U) |
| #define DDRC_REGS_DFITMG1_dfi_t_parin_lat_SHIFT (24U) |
| #define DDRC_REGS_DFITMG1_dfi_t_parin_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG1_dfi_t_parin_lat_SHIFT)) & DDRC_REGS_DFITMG1_dfi_t_parin_lat_MASK) |
| #define DDRC_REGS_DFITMG1_dfi_t_cmd_lat_MASK (0xF0000000U) |
| #define DDRC_REGS_DFITMG1_dfi_t_cmd_lat_SHIFT (28U) |
| #define DDRC_REGS_DFITMG1_dfi_t_cmd_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG1_dfi_t_cmd_lat_SHIFT)) & DDRC_REGS_DFITMG1_dfi_t_cmd_lat_MASK) |
| /*! @} */ |
| |
| /*! @name DFILPCFG0 - DFI Low Power Configuration Register 0 */ |
| /*! @{ */ |
| #define DDRC_REGS_DFILPCFG0_dfi_lp_en_pd_MASK (0x1U) |
| #define DDRC_REGS_DFILPCFG0_dfi_lp_en_pd_SHIFT (0U) |
| #define DDRC_REGS_DFILPCFG0_dfi_lp_en_pd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFILPCFG0_dfi_lp_en_pd_SHIFT)) & DDRC_REGS_DFILPCFG0_dfi_lp_en_pd_MASK) |
| #define DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_pd_MASK (0xF0U) |
| #define DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_pd_SHIFT (4U) |
| /*! dfi_lp_wakeup_pd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: |
| * 0b0000..16 cycles |
| * 0b0001..32 cycles |
| * 0b0010..64 cycles |
| * 0b0011..128 cycles |
| * 0b0100..256 cycles |
| * 0b0101..512 cycles |
| * 0b0110..1024 cycles |
| * 0b0111..2048 cycles |
| * 0b1000..4096 cycles |
| * 0b1001..8192 cycles |
| * 0b1010..16384 cycles |
| * 0b1011..32768 cycles |
| * 0b1100..65536 cycles |
| * 0b1101..131072 cycles |
| * 0b1110..262144 cycles |
| * 0b1111..Unlimited cycles |
| */ |
| #define DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_pd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_pd_SHIFT)) & DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_pd_MASK) |
| #define DDRC_REGS_DFILPCFG0_dfi_lp_en_sr_MASK (0x100U) |
| #define DDRC_REGS_DFILPCFG0_dfi_lp_en_sr_SHIFT (8U) |
| /*! dfi_lp_en_sr - Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled |
| * 0b0..Disabled |
| * 0b1..Enabled |
| */ |
| #define DDRC_REGS_DFILPCFG0_dfi_lp_en_sr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFILPCFG0_dfi_lp_en_sr_SHIFT)) & DDRC_REGS_DFILPCFG0_dfi_lp_en_sr_MASK) |
| #define DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_sr_MASK (0xF000U) |
| #define DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_sr_SHIFT (12U) |
| /*! dfi_lp_wakeup_sr - Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: |
| * 0b0000..16 cycles |
| * 0b0001..32 cycles |
| * 0b0010..64 cycles |
| * 0b0011..128 cycles |
| * 0b0100..256 cycles |
| * 0b0101..512 cycles |
| * 0b0110..1024 cycles |
| * 0b0111..2048 cycles |
| * 0b1000..4096 cycles |
| * 0b1001..8192 cycles |
| * 0b1010..16384 cycles |
| * 0b1011..32768 cycles |
| * 0b1100..65536 cycles |
| * 0b1101..131072 cycles |
| * 0b1110..262144 cycles |
| * 0b1111..Unlimited cycles |
| */ |
| #define DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_sr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_sr_SHIFT)) & DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_sr_MASK) |
| #define DDRC_REGS_DFILPCFG0_dfi_lp_en_dpd_MASK (0x10000U) |
| #define DDRC_REGS_DFILPCFG0_dfi_lp_en_dpd_SHIFT (16U) |
| #define DDRC_REGS_DFILPCFG0_dfi_lp_en_dpd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFILPCFG0_dfi_lp_en_dpd_SHIFT)) & DDRC_REGS_DFILPCFG0_dfi_lp_en_dpd_MASK) |
| #define DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_dpd_MASK (0xF00000U) |
| #define DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_dpd_SHIFT (20U) |
| /*! dfi_lp_wakeup_dpd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices. |
| * 0b0000..16 cycles |
| * 0b0001..32 cycles |
| * 0b0010..64 cycles |
| * 0b0011..128 cycles |
| * 0b0100..256 cycles |
| * 0b0101..512 cycles |
| * 0b0110..1024 cycles |
| * 0b0111..2048 cycles |
| * 0b1000..4096 cycles |
| * 0b1001..8192 cycles |
| * 0b1010..16384 cycles |
| * 0b1011..32768 cycles |
| * 0b1100..65536 cycles |
| * 0b1101..131072 cycles |
| * 0b1110..262144 cycles |
| * 0b1111..Unlimited cycles |
| */ |
| #define DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_dpd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_dpd_SHIFT)) & DDRC_REGS_DFILPCFG0_dfi_lp_wakeup_dpd_MASK) |
| #define DDRC_REGS_DFILPCFG0_dfi_tlp_resp_MASK (0x1F000000U) |
| #define DDRC_REGS_DFILPCFG0_dfi_tlp_resp_SHIFT (24U) |
| #define DDRC_REGS_DFILPCFG0_dfi_tlp_resp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFILPCFG0_dfi_tlp_resp_SHIFT)) & DDRC_REGS_DFILPCFG0_dfi_tlp_resp_MASK) |
| /*! @} */ |
| |
| /*! @name DFILPCFG1 - DFI Low Power Configuration Register 1 */ |
| /*! @{ */ |
| #define DDRC_REGS_DFILPCFG1_dfi_lp_en_mpsm_MASK (0x1U) |
| #define DDRC_REGS_DFILPCFG1_dfi_lp_en_mpsm_SHIFT (0U) |
| #define DDRC_REGS_DFILPCFG1_dfi_lp_en_mpsm(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFILPCFG1_dfi_lp_en_mpsm_SHIFT)) & DDRC_REGS_DFILPCFG1_dfi_lp_en_mpsm_MASK) |
| #define DDRC_REGS_DFILPCFG1_dfi_lp_wakeup_mpsm_MASK (0xF0U) |
| #define DDRC_REGS_DFILPCFG1_dfi_lp_wakeup_mpsm_SHIFT (4U) |
| /*! dfi_lp_wakeup_mpsm - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: |
| * 0b0000..16 cycles |
| * 0b0001..32 cycles |
| * 0b0010..64 cycles |
| * 0b0011..128 cycles |
| * 0b0100..256 cycles |
| * 0b0101..512 cycles |
| * 0b0110..1024 cycles |
| * 0b0111..2048 cycles |
| * 0b1000..4096 cycles |
| * 0b1001..8192 cycles |
| * 0b1010..16384 cycles |
| * 0b1011..32768 cycles |
| * 0b1100..65536 cycles |
| * 0b1101..131072 cycles |
| * 0b1110..262144 cycles |
| * 0b1111..Unlimited cycles |
| */ |
| #define DDRC_REGS_DFILPCFG1_dfi_lp_wakeup_mpsm(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFILPCFG1_dfi_lp_wakeup_mpsm_SHIFT)) & DDRC_REGS_DFILPCFG1_dfi_lp_wakeup_mpsm_MASK) |
| /*! @} */ |
| |
| /*! @name DFIUPD0 - DFI Update Register 0 */ |
| /*! @{ */ |
| #define DDRC_REGS_DFIUPD0_dfi_t_ctrlup_min_MASK (0x3FFU) |
| #define DDRC_REGS_DFIUPD0_dfi_t_ctrlup_min_SHIFT (0U) |
| #define DDRC_REGS_DFIUPD0_dfi_t_ctrlup_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIUPD0_dfi_t_ctrlup_min_SHIFT)) & DDRC_REGS_DFIUPD0_dfi_t_ctrlup_min_MASK) |
| #define DDRC_REGS_DFIUPD0_dfi_t_ctrlup_max_MASK (0x3FF0000U) |
| #define DDRC_REGS_DFIUPD0_dfi_t_ctrlup_max_SHIFT (16U) |
| #define DDRC_REGS_DFIUPD0_dfi_t_ctrlup_max(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIUPD0_dfi_t_ctrlup_max_SHIFT)) & DDRC_REGS_DFIUPD0_dfi_t_ctrlup_max_MASK) |
| #define DDRC_REGS_DFIUPD0_ctrlupd_pre_srx_MASK (0x20000000U) |
| #define DDRC_REGS_DFIUPD0_ctrlupd_pre_srx_SHIFT (29U) |
| /*! ctrlupd_pre_srx - Selects dfi_ctrlupd_req requirements at SRX: - 0 : send ctrlupd after SRX - 1 : send ctrlupd before SRX If DFIUPD0.dis_auto_ctrlupd_srx=1, this register has no impact, because no dfi_ctrlupd_req will be issued when SRX. |
| * 0b0..send ctrlupd after SRX |
| * 0b1..send ctrlupd before SRX |
| */ |
| #define DDRC_REGS_DFIUPD0_ctrlupd_pre_srx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIUPD0_ctrlupd_pre_srx_SHIFT)) & DDRC_REGS_DFIUPD0_ctrlupd_pre_srx_MASK) |
| #define DDRC_REGS_DFIUPD0_dis_auto_ctrlupd_srx_MASK (0x40000000U) |
| #define DDRC_REGS_DFIUPD0_dis_auto_ctrlupd_srx_SHIFT (30U) |
| /*! dis_auto_ctrlupd_srx - Auto ctrlupd request generation |
| * 0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC at self-refresh exit. |
| * 0b0..DDRC issues a dfi_ctrlupd_req before or after exiting self-refresh, depending on DFIUPD0.ctrlupd_pre_srx. |
| */ |
| #define DDRC_REGS_DFIUPD0_dis_auto_ctrlupd_srx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIUPD0_dis_auto_ctrlupd_srx_SHIFT)) & DDRC_REGS_DFIUPD0_dis_auto_ctrlupd_srx_MASK) |
| #define DDRC_REGS_DFIUPD0_dis_auto_ctrlupd_MASK (0x80000000U) |
| #define DDRC_REGS_DFIUPD0_dis_auto_ctrlupd_SHIFT (31U) |
| /*! dis_auto_ctrlupd - automatic dfi_ctrlupd_req generation by the DDRC |
| * 0b0..DDRC issues dfi_ctrlupd_req periodically. |
| * 0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC. The core must issue the dfi_ctrlupd_req signal using register reg_ddrc_ctrlupd. |
| */ |
| #define DDRC_REGS_DFIUPD0_dis_auto_ctrlupd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIUPD0_dis_auto_ctrlupd_SHIFT)) & DDRC_REGS_DFIUPD0_dis_auto_ctrlupd_MASK) |
| /*! @} */ |
| |
| /*! @name DFIUPD1 - DFI Update Register 1 */ |
| /*! @{ */ |
| #define DDRC_REGS_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_MASK (0xFFU) |
| #define DDRC_REGS_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_SHIFT (0U) |
| #define DDRC_REGS_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_SHIFT)) & DDRC_REGS_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_MASK) |
| #define DDRC_REGS_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_MASK (0xFF0000U) |
| #define DDRC_REGS_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_SHIFT (16U) |
| #define DDRC_REGS_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_SHIFT)) & DDRC_REGS_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_MASK) |
| /*! @} */ |
| |
| /*! @name DFIUPD2 - DFI Update Register 2 */ |
| /*! @{ */ |
| #define DDRC_REGS_DFIUPD2_dfi_phyupd_en_MASK (0x80000000U) |
| #define DDRC_REGS_DFIUPD2_dfi_phyupd_en_SHIFT (31U) |
| /*! dfi_phyupd_en - Enables the support for acknowledging PHY-initiated updates: |
| * 0b0..Disabled |
| * 0b1..Enabled |
| */ |
| #define DDRC_REGS_DFIUPD2_dfi_phyupd_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIUPD2_dfi_phyupd_en_SHIFT)) & DDRC_REGS_DFIUPD2_dfi_phyupd_en_MASK) |
| /*! @} */ |
| |
| /*! @name DFIMISC - DFI Miscellaneous Control Register */ |
| /*! @{ */ |
| #define DDRC_REGS_DFIMISC_dfi_init_complete_en_MASK (0x1U) |
| #define DDRC_REGS_DFIMISC_dfi_init_complete_en_SHIFT (0U) |
| #define DDRC_REGS_DFIMISC_dfi_init_complete_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIMISC_dfi_init_complete_en_SHIFT)) & DDRC_REGS_DFIMISC_dfi_init_complete_en_MASK) |
| #define DDRC_REGS_DFIMISC_phy_dbi_mode_MASK (0x2U) |
| #define DDRC_REGS_DFIMISC_phy_dbi_mode_SHIFT (1U) |
| /*! phy_dbi_mode - DBI implemented in DDRC or PHY. Present only in designs configured to support DDR4 and LPDDR4. |
| * 0b0..DDRC implements DBI functionality. |
| * 0b1..PHY implements DBI functionality. |
| */ |
| #define DDRC_REGS_DFIMISC_phy_dbi_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIMISC_phy_dbi_mode_SHIFT)) & DDRC_REGS_DFIMISC_phy_dbi_mode_MASK) |
| #define DDRC_REGS_DFIMISC_dfi_data_cs_polarity_MASK (0x4U) |
| #define DDRC_REGS_DFIMISC_dfi_data_cs_polarity_SHIFT (2U) |
| /*! dfi_data_cs_polarity - Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. |
| * 0b0..Signals are active low |
| * 0b1..Signals are active high |
| */ |
| #define DDRC_REGS_DFIMISC_dfi_data_cs_polarity(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIMISC_dfi_data_cs_polarity_SHIFT)) & DDRC_REGS_DFIMISC_dfi_data_cs_polarity_MASK) |
| #define DDRC_REGS_DFIMISC_ctl_idle_en_MASK (0x10U) |
| #define DDRC_REGS_DFIMISC_ctl_idle_en_SHIFT (4U) |
| #define DDRC_REGS_DFIMISC_ctl_idle_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIMISC_ctl_idle_en_SHIFT)) & DDRC_REGS_DFIMISC_ctl_idle_en_MASK) |
| #define DDRC_REGS_DFIMISC_dfi_init_start_MASK (0x20U) |
| #define DDRC_REGS_DFIMISC_dfi_init_start_SHIFT (5U) |
| #define DDRC_REGS_DFIMISC_dfi_init_start(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIMISC_dfi_init_start_SHIFT)) & DDRC_REGS_DFIMISC_dfi_init_start_MASK) |
| #define DDRC_REGS_DFIMISC_dfi_frequency_MASK (0x1F00U) |
| #define DDRC_REGS_DFIMISC_dfi_frequency_SHIFT (8U) |
| #define DDRC_REGS_DFIMISC_dfi_frequency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFIMISC_dfi_frequency_SHIFT)) & DDRC_REGS_DFIMISC_dfi_frequency_MASK) |
| /*! @} */ |
| |
| /*! @name DFITMG2 - DFI Timing Register 2 */ |
| /*! @{ */ |
| #define DDRC_REGS_DFITMG2_dfi_tphy_wrcslat_MASK (0x3FU) |
| #define DDRC_REGS_DFITMG2_dfi_tphy_wrcslat_SHIFT (0U) |
| #define DDRC_REGS_DFITMG2_dfi_tphy_wrcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG2_dfi_tphy_wrcslat_SHIFT)) & DDRC_REGS_DFITMG2_dfi_tphy_wrcslat_MASK) |
| #define DDRC_REGS_DFITMG2_dfi_tphy_rdcslat_MASK (0x7F00U) |
| #define DDRC_REGS_DFITMG2_dfi_tphy_rdcslat_SHIFT (8U) |
| #define DDRC_REGS_DFITMG2_dfi_tphy_rdcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG2_dfi_tphy_rdcslat_SHIFT)) & DDRC_REGS_DFITMG2_dfi_tphy_rdcslat_MASK) |
| /*! @} */ |
| |
| /*! @name DFITMG3 - DFI Timing Register 3 */ |
| /*! @{ */ |
| #define DDRC_REGS_DFITMG3_dfi_t_geardown_delay_MASK (0x1FU) |
| #define DDRC_REGS_DFITMG3_dfi_t_geardown_delay_SHIFT (0U) |
| #define DDRC_REGS_DFITMG3_dfi_t_geardown_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG3_dfi_t_geardown_delay_SHIFT)) & DDRC_REGS_DFITMG3_dfi_t_geardown_delay_MASK) |
| /*! @} */ |
| |
| /*! @name DFISTAT - DFI Status Register */ |
| /*! @{ */ |
| #define DDRC_REGS_DFISTAT_dfi_init_complete_MASK (0x1U) |
| #define DDRC_REGS_DFISTAT_dfi_init_complete_SHIFT (0U) |
| #define DDRC_REGS_DFISTAT_dfi_init_complete(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFISTAT_dfi_init_complete_SHIFT)) & DDRC_REGS_DFISTAT_dfi_init_complete_MASK) |
| #define DDRC_REGS_DFISTAT_dfi_lp_ack_MASK (0x2U) |
| #define DDRC_REGS_DFISTAT_dfi_lp_ack_SHIFT (1U) |
| #define DDRC_REGS_DFISTAT_dfi_lp_ack(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFISTAT_dfi_lp_ack_SHIFT)) & DDRC_REGS_DFISTAT_dfi_lp_ack_MASK) |
| /*! @} */ |
| |
| /*! @name DBICTL - DM/DBI Control Register */ |
| /*! @{ */ |
| #define DDRC_REGS_DBICTL_dm_en_MASK (0x1U) |
| #define DDRC_REGS_DBICTL_dm_en_SHIFT (0U) |
| /*! dm_en - DM enable signal in DDRC. This signal must be set the same logical value as DRAM's mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR4: Set this to inverted value of MR13[5] which is opposite polarity from this signal |
| * 0b0..DM is disabled |
| * 0b1..DM is enabled |
| */ |
| #define DDRC_REGS_DBICTL_dm_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBICTL_dm_en_SHIFT)) & DDRC_REGS_DBICTL_dm_en_MASK) |
| #define DDRC_REGS_DBICTL_wr_dbi_en_MASK (0x2U) |
| #define DDRC_REGS_DBICTL_wr_dbi_en_SHIFT (1U) |
| /*! wr_dbi_en - This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7] |
| * 0b0..Write DBI is disabled |
| * 0b1..Write DBI is enabled. |
| */ |
| #define DDRC_REGS_DBICTL_wr_dbi_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBICTL_wr_dbi_en_SHIFT)) & DDRC_REGS_DBICTL_wr_dbi_en_MASK) |
| #define DDRC_REGS_DBICTL_rd_dbi_en_MASK (0x4U) |
| #define DDRC_REGS_DBICTL_rd_dbi_en_SHIFT (2U) |
| #define DDRC_REGS_DBICTL_rd_dbi_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBICTL_rd_dbi_en_SHIFT)) & DDRC_REGS_DBICTL_rd_dbi_en_MASK) |
| /*! @} */ |
| |
| /*! @name ADDRMAP0 - Address Map Register 0 */ |
| /*! @{ */ |
| #define DDRC_REGS_ADDRMAP0_addrmap_cs_bit0_MASK (0x1FU) |
| #define DDRC_REGS_ADDRMAP0_addrmap_cs_bit0_SHIFT (0U) |
| #define DDRC_REGS_ADDRMAP0_addrmap_cs_bit0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP0_addrmap_cs_bit0_SHIFT)) & DDRC_REGS_ADDRMAP0_addrmap_cs_bit0_MASK) |
| /*! @} */ |
| |
| /*! @name ADDRMAP1 - Address Map Register 1 */ |
| /*! @{ */ |
| #define DDRC_REGS_ADDRMAP1_addrmap_bank_b0_MASK (0x1FU) |
| #define DDRC_REGS_ADDRMAP1_addrmap_bank_b0_SHIFT (0U) |
| #define DDRC_REGS_ADDRMAP1_addrmap_bank_b0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP1_addrmap_bank_b0_SHIFT)) & DDRC_REGS_ADDRMAP1_addrmap_bank_b0_MASK) |
| #define DDRC_REGS_ADDRMAP1_addrmap_bank_b1_MASK (0x1F00U) |
| #define DDRC_REGS_ADDRMAP1_addrmap_bank_b1_SHIFT (8U) |
| #define DDRC_REGS_ADDRMAP1_addrmap_bank_b1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP1_addrmap_bank_b1_SHIFT)) & DDRC_REGS_ADDRMAP1_addrmap_bank_b1_MASK) |
| #define DDRC_REGS_ADDRMAP1_addrmap_bank_b2_MASK (0x1F0000U) |
| #define DDRC_REGS_ADDRMAP1_addrmap_bank_b2_SHIFT (16U) |
| #define DDRC_REGS_ADDRMAP1_addrmap_bank_b2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP1_addrmap_bank_b2_SHIFT)) & DDRC_REGS_ADDRMAP1_addrmap_bank_b2_MASK) |
| /*! @} */ |
| |
| /*! @name ADDRMAP2 - Address Map Register 2 */ |
| /*! @{ */ |
| #define DDRC_REGS_ADDRMAP2_addrmap_col_b2_MASK (0xFU) |
| #define DDRC_REGS_ADDRMAP2_addrmap_col_b2_SHIFT (0U) |
| #define DDRC_REGS_ADDRMAP2_addrmap_col_b2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP2_addrmap_col_b2_SHIFT)) & DDRC_REGS_ADDRMAP2_addrmap_col_b2_MASK) |
| #define DDRC_REGS_ADDRMAP2_addrmap_col_b3_MASK (0xF00U) |
| #define DDRC_REGS_ADDRMAP2_addrmap_col_b3_SHIFT (8U) |
| #define DDRC_REGS_ADDRMAP2_addrmap_col_b3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP2_addrmap_col_b3_SHIFT)) & DDRC_REGS_ADDRMAP2_addrmap_col_b3_MASK) |
| #define DDRC_REGS_ADDRMAP2_addrmap_col_b4_MASK (0xF0000U) |
| #define DDRC_REGS_ADDRMAP2_addrmap_col_b4_SHIFT (16U) |
| #define DDRC_REGS_ADDRMAP2_addrmap_col_b4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP2_addrmap_col_b4_SHIFT)) & DDRC_REGS_ADDRMAP2_addrmap_col_b4_MASK) |
| #define DDRC_REGS_ADDRMAP2_addrmap_col_b5_MASK (0xF000000U) |
| #define DDRC_REGS_ADDRMAP2_addrmap_col_b5_SHIFT (24U) |
| #define DDRC_REGS_ADDRMAP2_addrmap_col_b5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP2_addrmap_col_b5_SHIFT)) & DDRC_REGS_ADDRMAP2_addrmap_col_b5_MASK) |
| /*! @} */ |
| |
| /*! @name ADDRMAP3 - Address Map Register 3 */ |
| /*! @{ */ |
| #define DDRC_REGS_ADDRMAP3_addrmap_col_b6_MASK (0xFU) |
| #define DDRC_REGS_ADDRMAP3_addrmap_col_b6_SHIFT (0U) |
| #define DDRC_REGS_ADDRMAP3_addrmap_col_b6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP3_addrmap_col_b6_SHIFT)) & DDRC_REGS_ADDRMAP3_addrmap_col_b6_MASK) |
| #define DDRC_REGS_ADDRMAP3_addrmap_col_b7_MASK (0xF00U) |
| #define DDRC_REGS_ADDRMAP3_addrmap_col_b7_SHIFT (8U) |
| #define DDRC_REGS_ADDRMAP3_addrmap_col_b7(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP3_addrmap_col_b7_SHIFT)) & DDRC_REGS_ADDRMAP3_addrmap_col_b7_MASK) |
| #define DDRC_REGS_ADDRMAP3_addrmap_col_b8_MASK (0xF0000U) |
| #define DDRC_REGS_ADDRMAP3_addrmap_col_b8_SHIFT (16U) |
| #define DDRC_REGS_ADDRMAP3_addrmap_col_b8(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP3_addrmap_col_b8_SHIFT)) & DDRC_REGS_ADDRMAP3_addrmap_col_b8_MASK) |
| #define DDRC_REGS_ADDRMAP3_addrmap_col_b9_MASK (0xF000000U) |
| #define DDRC_REGS_ADDRMAP3_addrmap_col_b9_SHIFT (24U) |
| #define DDRC_REGS_ADDRMAP3_addrmap_col_b9(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP3_addrmap_col_b9_SHIFT)) & DDRC_REGS_ADDRMAP3_addrmap_col_b9_MASK) |
| /*! @} */ |
| |
| /*! @name ADDRMAP4 - Address Map Register 4 */ |
| /*! @{ */ |
| #define DDRC_REGS_ADDRMAP4_addrmap_col_b10_MASK (0xFU) |
| #define DDRC_REGS_ADDRMAP4_addrmap_col_b10_SHIFT (0U) |
| #define DDRC_REGS_ADDRMAP4_addrmap_col_b10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP4_addrmap_col_b10_SHIFT)) & DDRC_REGS_ADDRMAP4_addrmap_col_b10_MASK) |
| #define DDRC_REGS_ADDRMAP4_addrmap_col_b11_MASK (0xF00U) |
| #define DDRC_REGS_ADDRMAP4_addrmap_col_b11_SHIFT (8U) |
| #define DDRC_REGS_ADDRMAP4_addrmap_col_b11(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP4_addrmap_col_b11_SHIFT)) & DDRC_REGS_ADDRMAP4_addrmap_col_b11_MASK) |
| /*! @} */ |
| |
| /*! @name ADDRMAP5 - Address Map Register 5 */ |
| /*! @{ */ |
| #define DDRC_REGS_ADDRMAP5_addrmap_row_b0_MASK (0xFU) |
| #define DDRC_REGS_ADDRMAP5_addrmap_row_b0_SHIFT (0U) |
| #define DDRC_REGS_ADDRMAP5_addrmap_row_b0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP5_addrmap_row_b0_SHIFT)) & DDRC_REGS_ADDRMAP5_addrmap_row_b0_MASK) |
| #define DDRC_REGS_ADDRMAP5_addrmap_row_b1_MASK (0xF00U) |
| #define DDRC_REGS_ADDRMAP5_addrmap_row_b1_SHIFT (8U) |
| #define DDRC_REGS_ADDRMAP5_addrmap_row_b1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP5_addrmap_row_b1_SHIFT)) & DDRC_REGS_ADDRMAP5_addrmap_row_b1_MASK) |
| #define DDRC_REGS_ADDRMAP5_addrmap_row_b2_10_MASK (0xF0000U) |
| #define DDRC_REGS_ADDRMAP5_addrmap_row_b2_10_SHIFT (16U) |
| #define DDRC_REGS_ADDRMAP5_addrmap_row_b2_10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP5_addrmap_row_b2_10_SHIFT)) & DDRC_REGS_ADDRMAP5_addrmap_row_b2_10_MASK) |
| #define DDRC_REGS_ADDRMAP5_addrmap_row_b11_MASK (0xF000000U) |
| #define DDRC_REGS_ADDRMAP5_addrmap_row_b11_SHIFT (24U) |
| #define DDRC_REGS_ADDRMAP5_addrmap_row_b11(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP5_addrmap_row_b11_SHIFT)) & DDRC_REGS_ADDRMAP5_addrmap_row_b11_MASK) |
| /*! @} */ |
| |
| /*! @name ADDRMAP6 - Address Map Register 6 */ |
| /*! @{ */ |
| #define DDRC_REGS_ADDRMAP6_addrmap_row_b12_MASK (0xFU) |
| #define DDRC_REGS_ADDRMAP6_addrmap_row_b12_SHIFT (0U) |
| #define DDRC_REGS_ADDRMAP6_addrmap_row_b12(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP6_addrmap_row_b12_SHIFT)) & DDRC_REGS_ADDRMAP6_addrmap_row_b12_MASK) |
| #define DDRC_REGS_ADDRMAP6_addrmap_row_b13_MASK (0xF00U) |
| #define DDRC_REGS_ADDRMAP6_addrmap_row_b13_SHIFT (8U) |
| #define DDRC_REGS_ADDRMAP6_addrmap_row_b13(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP6_addrmap_row_b13_SHIFT)) & DDRC_REGS_ADDRMAP6_addrmap_row_b13_MASK) |
| #define DDRC_REGS_ADDRMAP6_addrmap_row_b14_MASK (0xF0000U) |
| #define DDRC_REGS_ADDRMAP6_addrmap_row_b14_SHIFT (16U) |
| #define DDRC_REGS_ADDRMAP6_addrmap_row_b14(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP6_addrmap_row_b14_SHIFT)) & DDRC_REGS_ADDRMAP6_addrmap_row_b14_MASK) |
| #define DDRC_REGS_ADDRMAP6_addrmap_row_b15_MASK (0xF000000U) |
| #define DDRC_REGS_ADDRMAP6_addrmap_row_b15_SHIFT (24U) |
| #define DDRC_REGS_ADDRMAP6_addrmap_row_b15(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP6_addrmap_row_b15_SHIFT)) & DDRC_REGS_ADDRMAP6_addrmap_row_b15_MASK) |
| #define DDRC_REGS_ADDRMAP6_lpddr3_6gb_12gb_MASK (0x80000000U) |
| #define DDRC_REGS_ADDRMAP6_lpddr3_6gb_12gb_SHIFT (31U) |
| #define DDRC_REGS_ADDRMAP6_lpddr3_6gb_12gb(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP6_lpddr3_6gb_12gb_SHIFT)) & DDRC_REGS_ADDRMAP6_lpddr3_6gb_12gb_MASK) |
| /*! @} */ |
| |
| /*! @name ADDRMAP7 - Address Map Register 7 */ |
| /*! @{ */ |
| #define DDRC_REGS_ADDRMAP7_addrmap_row_b16_MASK (0xFU) |
| #define DDRC_REGS_ADDRMAP7_addrmap_row_b16_SHIFT (0U) |
| #define DDRC_REGS_ADDRMAP7_addrmap_row_b16(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP7_addrmap_row_b16_SHIFT)) & DDRC_REGS_ADDRMAP7_addrmap_row_b16_MASK) |
| #define DDRC_REGS_ADDRMAP7_addrmap_row_b17_MASK (0xF00U) |
| #define DDRC_REGS_ADDRMAP7_addrmap_row_b17_SHIFT (8U) |
| #define DDRC_REGS_ADDRMAP7_addrmap_row_b17(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP7_addrmap_row_b17_SHIFT)) & DDRC_REGS_ADDRMAP7_addrmap_row_b17_MASK) |
| /*! @} */ |
| |
| /*! @name ADDRMAP8 - Address Map Register 8 */ |
| /*! @{ */ |
| #define DDRC_REGS_ADDRMAP8_addrmap_bg_b0_MASK (0x1FU) |
| #define DDRC_REGS_ADDRMAP8_addrmap_bg_b0_SHIFT (0U) |
| #define DDRC_REGS_ADDRMAP8_addrmap_bg_b0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP8_addrmap_bg_b0_SHIFT)) & DDRC_REGS_ADDRMAP8_addrmap_bg_b0_MASK) |
| #define DDRC_REGS_ADDRMAP8_addrmap_bg_b1_MASK (0x3F00U) |
| #define DDRC_REGS_ADDRMAP8_addrmap_bg_b1_SHIFT (8U) |
| #define DDRC_REGS_ADDRMAP8_addrmap_bg_b1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP8_addrmap_bg_b1_SHIFT)) & DDRC_REGS_ADDRMAP8_addrmap_bg_b1_MASK) |
| /*! @} */ |
| |
| /*! @name ADDRMAP9 - Address Map Register 9 */ |
| /*! @{ */ |
| #define DDRC_REGS_ADDRMAP9_addrmap_row_b2_MASK (0xFU) |
| #define DDRC_REGS_ADDRMAP9_addrmap_row_b2_SHIFT (0U) |
| #define DDRC_REGS_ADDRMAP9_addrmap_row_b2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP9_addrmap_row_b2_SHIFT)) & DDRC_REGS_ADDRMAP9_addrmap_row_b2_MASK) |
| #define DDRC_REGS_ADDRMAP9_addrmap_row_b3_MASK (0xF00U) |
| #define DDRC_REGS_ADDRMAP9_addrmap_row_b3_SHIFT (8U) |
| #define DDRC_REGS_ADDRMAP9_addrmap_row_b3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP9_addrmap_row_b3_SHIFT)) & DDRC_REGS_ADDRMAP9_addrmap_row_b3_MASK) |
| #define DDRC_REGS_ADDRMAP9_addrmap_row_b4_MASK (0xF0000U) |
| #define DDRC_REGS_ADDRMAP9_addrmap_row_b4_SHIFT (16U) |
| #define DDRC_REGS_ADDRMAP9_addrmap_row_b4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP9_addrmap_row_b4_SHIFT)) & DDRC_REGS_ADDRMAP9_addrmap_row_b4_MASK) |
| #define DDRC_REGS_ADDRMAP9_addrmap_row_b5_MASK (0xF000000U) |
| #define DDRC_REGS_ADDRMAP9_addrmap_row_b5_SHIFT (24U) |
| #define DDRC_REGS_ADDRMAP9_addrmap_row_b5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP9_addrmap_row_b5_SHIFT)) & DDRC_REGS_ADDRMAP9_addrmap_row_b5_MASK) |
| /*! @} */ |
| |
| /*! @name ADDRMAP10 - Address Map Register 10 */ |
| /*! @{ */ |
| #define DDRC_REGS_ADDRMAP10_addrmap_row_b6_MASK (0xFU) |
| #define DDRC_REGS_ADDRMAP10_addrmap_row_b6_SHIFT (0U) |
| #define DDRC_REGS_ADDRMAP10_addrmap_row_b6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP10_addrmap_row_b6_SHIFT)) & DDRC_REGS_ADDRMAP10_addrmap_row_b6_MASK) |
| #define DDRC_REGS_ADDRMAP10_addrmap_row_b7_MASK (0xF00U) |
| #define DDRC_REGS_ADDRMAP10_addrmap_row_b7_SHIFT (8U) |
| #define DDRC_REGS_ADDRMAP10_addrmap_row_b7(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP10_addrmap_row_b7_SHIFT)) & DDRC_REGS_ADDRMAP10_addrmap_row_b7_MASK) |
| #define DDRC_REGS_ADDRMAP10_addrmap_row_b8_MASK (0xF0000U) |
| #define DDRC_REGS_ADDRMAP10_addrmap_row_b8_SHIFT (16U) |
| #define DDRC_REGS_ADDRMAP10_addrmap_row_b8(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP10_addrmap_row_b8_SHIFT)) & DDRC_REGS_ADDRMAP10_addrmap_row_b8_MASK) |
| #define DDRC_REGS_ADDRMAP10_addrmap_row_b9_MASK (0xF000000U) |
| #define DDRC_REGS_ADDRMAP10_addrmap_row_b9_SHIFT (24U) |
| #define DDRC_REGS_ADDRMAP10_addrmap_row_b9(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP10_addrmap_row_b9_SHIFT)) & DDRC_REGS_ADDRMAP10_addrmap_row_b9_MASK) |
| /*! @} */ |
| |
| /*! @name ADDRMAP11 - Address Map Register 11 */ |
| /*! @{ */ |
| #define DDRC_REGS_ADDRMAP11_addrmap_row_b10_MASK (0xFU) |
| #define DDRC_REGS_ADDRMAP11_addrmap_row_b10_SHIFT (0U) |
| #define DDRC_REGS_ADDRMAP11_addrmap_row_b10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ADDRMAP11_addrmap_row_b10_SHIFT)) & DDRC_REGS_ADDRMAP11_addrmap_row_b10_MASK) |
| /*! @} */ |
| |
| /*! @name ODTCFG - ODT Configuration Register */ |
| /*! @{ */ |
| #define DDRC_REGS_ODTCFG_rd_odt_delay_MASK (0x7CU) |
| #define DDRC_REGS_ODTCFG_rd_odt_delay_SHIFT (2U) |
| #define DDRC_REGS_ODTCFG_rd_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTCFG_rd_odt_delay_SHIFT)) & DDRC_REGS_ODTCFG_rd_odt_delay_MASK) |
| #define DDRC_REGS_ODTCFG_rd_odt_hold_MASK (0xF00U) |
| #define DDRC_REGS_ODTCFG_rd_odt_hold_SHIFT (8U) |
| #define DDRC_REGS_ODTCFG_rd_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTCFG_rd_odt_hold_SHIFT)) & DDRC_REGS_ODTCFG_rd_odt_hold_MASK) |
| #define DDRC_REGS_ODTCFG_wr_odt_delay_MASK (0x1F0000U) |
| #define DDRC_REGS_ODTCFG_wr_odt_delay_SHIFT (16U) |
| #define DDRC_REGS_ODTCFG_wr_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTCFG_wr_odt_delay_SHIFT)) & DDRC_REGS_ODTCFG_wr_odt_delay_MASK) |
| #define DDRC_REGS_ODTCFG_wr_odt_hold_MASK (0xF000000U) |
| #define DDRC_REGS_ODTCFG_wr_odt_hold_SHIFT (24U) |
| #define DDRC_REGS_ODTCFG_wr_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTCFG_wr_odt_hold_SHIFT)) & DDRC_REGS_ODTCFG_wr_odt_hold_MASK) |
| /*! @} */ |
| |
| /*! @name ODTMAP - ODT/Rank Map Register */ |
| /*! @{ */ |
| #define DDRC_REGS_ODTMAP_rank0_wr_odt_MASK (0x3U) |
| #define DDRC_REGS_ODTMAP_rank0_wr_odt_SHIFT (0U) |
| #define DDRC_REGS_ODTMAP_rank0_wr_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTMAP_rank0_wr_odt_SHIFT)) & DDRC_REGS_ODTMAP_rank0_wr_odt_MASK) |
| #define DDRC_REGS_ODTMAP_rank0_rd_odt_MASK (0x30U) |
| #define DDRC_REGS_ODTMAP_rank0_rd_odt_SHIFT (4U) |
| #define DDRC_REGS_ODTMAP_rank0_rd_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTMAP_rank0_rd_odt_SHIFT)) & DDRC_REGS_ODTMAP_rank0_rd_odt_MASK) |
| #define DDRC_REGS_ODTMAP_rank1_wr_odt_MASK (0x300U) |
| #define DDRC_REGS_ODTMAP_rank1_wr_odt_SHIFT (8U) |
| #define DDRC_REGS_ODTMAP_rank1_wr_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTMAP_rank1_wr_odt_SHIFT)) & DDRC_REGS_ODTMAP_rank1_wr_odt_MASK) |
| #define DDRC_REGS_ODTMAP_rank1_rd_odt_MASK (0x3000U) |
| #define DDRC_REGS_ODTMAP_rank1_rd_odt_SHIFT (12U) |
| #define DDRC_REGS_ODTMAP_rank1_rd_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTMAP_rank1_rd_odt_SHIFT)) & DDRC_REGS_ODTMAP_rank1_rd_odt_MASK) |
| /*! @} */ |
| |
| /*! @name SCHED - Scheduler Control Register */ |
| /*! @{ */ |
| #define DDRC_REGS_SCHED_force_low_pri_n_MASK (0x1U) |
| #define DDRC_REGS_SCHED_force_low_pri_n_SHIFT (0U) |
| #define DDRC_REGS_SCHED_force_low_pri_n(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_SCHED_force_low_pri_n_SHIFT)) & DDRC_REGS_SCHED_force_low_pri_n_MASK) |
| #define DDRC_REGS_SCHED_prefer_write_MASK (0x2U) |
| #define DDRC_REGS_SCHED_prefer_write_SHIFT (1U) |
| #define DDRC_REGS_SCHED_prefer_write(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_SCHED_prefer_write_SHIFT)) & DDRC_REGS_SCHED_prefer_write_MASK) |
| #define DDRC_REGS_SCHED_pageclose_MASK (0x4U) |
| #define DDRC_REGS_SCHED_pageclose_SHIFT (2U) |
| #define DDRC_REGS_SCHED_pageclose(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_SCHED_pageclose_SHIFT)) & DDRC_REGS_SCHED_pageclose_MASK) |
| #define DDRC_REGS_SCHED_lpr_num_entries_MASK (0x1F00U) |
| #define DDRC_REGS_SCHED_lpr_num_entries_SHIFT (8U) |
| #define DDRC_REGS_SCHED_lpr_num_entries(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_SCHED_lpr_num_entries_SHIFT)) & DDRC_REGS_SCHED_lpr_num_entries_MASK) |
| #define DDRC_REGS_SCHED_go2critical_hysteresis_MASK (0xFF0000U) |
| #define DDRC_REGS_SCHED_go2critical_hysteresis_SHIFT (16U) |
| #define DDRC_REGS_SCHED_go2critical_hysteresis(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_SCHED_go2critical_hysteresis_SHIFT)) & DDRC_REGS_SCHED_go2critical_hysteresis_MASK) |
| #define DDRC_REGS_SCHED_rdwr_idle_gap_MASK (0x7F000000U) |
| #define DDRC_REGS_SCHED_rdwr_idle_gap_SHIFT (24U) |
| #define DDRC_REGS_SCHED_rdwr_idle_gap(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_SCHED_rdwr_idle_gap_SHIFT)) & DDRC_REGS_SCHED_rdwr_idle_gap_MASK) |
| /*! @} */ |
| |
| /*! @name SCHED1 - Scheduler Control Register 1 */ |
| /*! @{ */ |
| #define DDRC_REGS_SCHED1_pageclose_timer_MASK (0xFFU) |
| #define DDRC_REGS_SCHED1_pageclose_timer_SHIFT (0U) |
| #define DDRC_REGS_SCHED1_pageclose_timer(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_SCHED1_pageclose_timer_SHIFT)) & DDRC_REGS_SCHED1_pageclose_timer_MASK) |
| /*! @} */ |
| |
| /*! @name PERFHPR1 - High Priority Read CAM Register 1 */ |
| /*! @{ */ |
| #define DDRC_REGS_PERFHPR1_hpr_max_starve_MASK (0xFFFFU) |
| #define DDRC_REGS_PERFHPR1_hpr_max_starve_SHIFT (0U) |
| #define DDRC_REGS_PERFHPR1_hpr_max_starve(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PERFHPR1_hpr_max_starve_SHIFT)) & DDRC_REGS_PERFHPR1_hpr_max_starve_MASK) |
| #define DDRC_REGS_PERFHPR1_hpr_xact_run_length_MASK (0xFF000000U) |
| #define DDRC_REGS_PERFHPR1_hpr_xact_run_length_SHIFT (24U) |
| #define DDRC_REGS_PERFHPR1_hpr_xact_run_length(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PERFHPR1_hpr_xact_run_length_SHIFT)) & DDRC_REGS_PERFHPR1_hpr_xact_run_length_MASK) |
| /*! @} */ |
| |
| /*! @name PERFLPR1 - Low Priority Read CAM Register 1 */ |
| /*! @{ */ |
| #define DDRC_REGS_PERFLPR1_lpr_max_starve_MASK (0xFFFFU) |
| #define DDRC_REGS_PERFLPR1_lpr_max_starve_SHIFT (0U) |
| #define DDRC_REGS_PERFLPR1_lpr_max_starve(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PERFLPR1_lpr_max_starve_SHIFT)) & DDRC_REGS_PERFLPR1_lpr_max_starve_MASK) |
| #define DDRC_REGS_PERFLPR1_lpr_xact_run_length_MASK (0xFF000000U) |
| #define DDRC_REGS_PERFLPR1_lpr_xact_run_length_SHIFT (24U) |
| #define DDRC_REGS_PERFLPR1_lpr_xact_run_length(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PERFLPR1_lpr_xact_run_length_SHIFT)) & DDRC_REGS_PERFLPR1_lpr_xact_run_length_MASK) |
| /*! @} */ |
| |
| /*! @name PERFWR1 - Write CAM Register 1 */ |
| /*! @{ */ |
| #define DDRC_REGS_PERFWR1_w_max_starve_MASK (0xFFFFU) |
| #define DDRC_REGS_PERFWR1_w_max_starve_SHIFT (0U) |
| #define DDRC_REGS_PERFWR1_w_max_starve(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PERFWR1_w_max_starve_SHIFT)) & DDRC_REGS_PERFWR1_w_max_starve_MASK) |
| #define DDRC_REGS_PERFWR1_w_xact_run_length_MASK (0xFF000000U) |
| #define DDRC_REGS_PERFWR1_w_xact_run_length_SHIFT (24U) |
| #define DDRC_REGS_PERFWR1_w_xact_run_length(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PERFWR1_w_xact_run_length_SHIFT)) & DDRC_REGS_PERFWR1_w_xact_run_length_MASK) |
| /*! @} */ |
| |
| /*! @name DBG0 - Debug Register 0 */ |
| /*! @{ */ |
| #define DDRC_REGS_DBG0_dis_wc_MASK (0x1U) |
| #define DDRC_REGS_DBG0_dis_wc_SHIFT (0U) |
| #define DDRC_REGS_DBG0_dis_wc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBG0_dis_wc_SHIFT)) & DDRC_REGS_DBG0_dis_wc_MASK) |
| #define DDRC_REGS_DBG0_dis_rd_bypass_MASK (0x2U) |
| #define DDRC_REGS_DBG0_dis_rd_bypass_SHIFT (1U) |
| #define DDRC_REGS_DBG0_dis_rd_bypass(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBG0_dis_rd_bypass_SHIFT)) & DDRC_REGS_DBG0_dis_rd_bypass_MASK) |
| #define DDRC_REGS_DBG0_dis_act_bypass_MASK (0x4U) |
| #define DDRC_REGS_DBG0_dis_act_bypass_SHIFT (2U) |
| #define DDRC_REGS_DBG0_dis_act_bypass(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBG0_dis_act_bypass_SHIFT)) & DDRC_REGS_DBG0_dis_act_bypass_MASK) |
| #define DDRC_REGS_DBG0_dis_collision_page_opt_MASK (0x10U) |
| #define DDRC_REGS_DBG0_dis_collision_page_opt_SHIFT (4U) |
| #define DDRC_REGS_DBG0_dis_collision_page_opt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBG0_dis_collision_page_opt_SHIFT)) & DDRC_REGS_DBG0_dis_collision_page_opt_MASK) |
| /*! @} */ |
| |
| /*! @name DBG1 - Debug Register 1 */ |
| /*! @{ */ |
| #define DDRC_REGS_DBG1_dis_dq_MASK (0x1U) |
| #define DDRC_REGS_DBG1_dis_dq_SHIFT (0U) |
| #define DDRC_REGS_DBG1_dis_dq(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBG1_dis_dq_SHIFT)) & DDRC_REGS_DBG1_dis_dq_MASK) |
| #define DDRC_REGS_DBG1_dis_hif_MASK (0x2U) |
| #define DDRC_REGS_DBG1_dis_hif_SHIFT (1U) |
| #define DDRC_REGS_DBG1_dis_hif(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBG1_dis_hif_SHIFT)) & DDRC_REGS_DBG1_dis_hif_MASK) |
| /*! @} */ |
| |
| /*! @name DBGCAM - CAM Debug Register */ |
| /*! @{ */ |
| #define DDRC_REGS_DBGCAM_dbg_hpr_q_depth_MASK (0x3FU) |
| #define DDRC_REGS_DBGCAM_dbg_hpr_q_depth_SHIFT (0U) |
| #define DDRC_REGS_DBGCAM_dbg_hpr_q_depth(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCAM_dbg_hpr_q_depth_SHIFT)) & DDRC_REGS_DBGCAM_dbg_hpr_q_depth_MASK) |
| #define DDRC_REGS_DBGCAM_dbg_lpr_q_depth_MASK (0x3F00U) |
| #define DDRC_REGS_DBGCAM_dbg_lpr_q_depth_SHIFT (8U) |
| #define DDRC_REGS_DBGCAM_dbg_lpr_q_depth(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCAM_dbg_lpr_q_depth_SHIFT)) & DDRC_REGS_DBGCAM_dbg_lpr_q_depth_MASK) |
| #define DDRC_REGS_DBGCAM_dbg_w_q_depth_MASK (0x3F0000U) |
| #define DDRC_REGS_DBGCAM_dbg_w_q_depth_SHIFT (16U) |
| #define DDRC_REGS_DBGCAM_dbg_w_q_depth(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCAM_dbg_w_q_depth_SHIFT)) & DDRC_REGS_DBGCAM_dbg_w_q_depth_MASK) |
| #define DDRC_REGS_DBGCAM_dbg_stall_MASK (0x1000000U) |
| #define DDRC_REGS_DBGCAM_dbg_stall_SHIFT (24U) |
| #define DDRC_REGS_DBGCAM_dbg_stall(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCAM_dbg_stall_SHIFT)) & DDRC_REGS_DBGCAM_dbg_stall_MASK) |
| #define DDRC_REGS_DBGCAM_dbg_rd_q_empty_MASK (0x2000000U) |
| #define DDRC_REGS_DBGCAM_dbg_rd_q_empty_SHIFT (25U) |
| #define DDRC_REGS_DBGCAM_dbg_rd_q_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCAM_dbg_rd_q_empty_SHIFT)) & DDRC_REGS_DBGCAM_dbg_rd_q_empty_MASK) |
| #define DDRC_REGS_DBGCAM_dbg_wr_q_empty_MASK (0x4000000U) |
| #define DDRC_REGS_DBGCAM_dbg_wr_q_empty_SHIFT (26U) |
| #define DDRC_REGS_DBGCAM_dbg_wr_q_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCAM_dbg_wr_q_empty_SHIFT)) & DDRC_REGS_DBGCAM_dbg_wr_q_empty_MASK) |
| #define DDRC_REGS_DBGCAM_rd_data_pipeline_empty_MASK (0x10000000U) |
| #define DDRC_REGS_DBGCAM_rd_data_pipeline_empty_SHIFT (28U) |
| #define DDRC_REGS_DBGCAM_rd_data_pipeline_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCAM_rd_data_pipeline_empty_SHIFT)) & DDRC_REGS_DBGCAM_rd_data_pipeline_empty_MASK) |
| #define DDRC_REGS_DBGCAM_wr_data_pipeline_empty_MASK (0x20000000U) |
| #define DDRC_REGS_DBGCAM_wr_data_pipeline_empty_SHIFT (29U) |
| #define DDRC_REGS_DBGCAM_wr_data_pipeline_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCAM_wr_data_pipeline_empty_SHIFT)) & DDRC_REGS_DBGCAM_wr_data_pipeline_empty_MASK) |
| #define DDRC_REGS_DBGCAM_dbg_stall_wr_MASK (0x40000000U) |
| #define DDRC_REGS_DBGCAM_dbg_stall_wr_SHIFT (30U) |
| #define DDRC_REGS_DBGCAM_dbg_stall_wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCAM_dbg_stall_wr_SHIFT)) & DDRC_REGS_DBGCAM_dbg_stall_wr_MASK) |
| #define DDRC_REGS_DBGCAM_dbg_stall_rd_MASK (0x80000000U) |
| #define DDRC_REGS_DBGCAM_dbg_stall_rd_SHIFT (31U) |
| #define DDRC_REGS_DBGCAM_dbg_stall_rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCAM_dbg_stall_rd_SHIFT)) & DDRC_REGS_DBGCAM_dbg_stall_rd_MASK) |
| /*! @} */ |
| |
| /*! @name DBGCMD - Command Debug Register */ |
| /*! @{ */ |
| #define DDRC_REGS_DBGCMD_rank0_refresh_MASK (0x1U) |
| #define DDRC_REGS_DBGCMD_rank0_refresh_SHIFT (0U) |
| #define DDRC_REGS_DBGCMD_rank0_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCMD_rank0_refresh_SHIFT)) & DDRC_REGS_DBGCMD_rank0_refresh_MASK) |
| #define DDRC_REGS_DBGCMD_rank1_refresh_MASK (0x2U) |
| #define DDRC_REGS_DBGCMD_rank1_refresh_SHIFT (1U) |
| #define DDRC_REGS_DBGCMD_rank1_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCMD_rank1_refresh_SHIFT)) & DDRC_REGS_DBGCMD_rank1_refresh_MASK) |
| #define DDRC_REGS_DBGCMD_zq_calib_short_MASK (0x10U) |
| #define DDRC_REGS_DBGCMD_zq_calib_short_SHIFT (4U) |
| #define DDRC_REGS_DBGCMD_zq_calib_short(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCMD_zq_calib_short_SHIFT)) & DDRC_REGS_DBGCMD_zq_calib_short_MASK) |
| #define DDRC_REGS_DBGCMD_ctrlupd_MASK (0x20U) |
| #define DDRC_REGS_DBGCMD_ctrlupd_SHIFT (5U) |
| #define DDRC_REGS_DBGCMD_ctrlupd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGCMD_ctrlupd_SHIFT)) & DDRC_REGS_DBGCMD_ctrlupd_MASK) |
| /*! @} */ |
| |
| /*! @name DBGSTAT - Status Debug Register */ |
| /*! @{ */ |
| #define DDRC_REGS_DBGSTAT_rank0_refresh_busy_MASK (0x1U) |
| #define DDRC_REGS_DBGSTAT_rank0_refresh_busy_SHIFT (0U) |
| #define DDRC_REGS_DBGSTAT_rank0_refresh_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGSTAT_rank0_refresh_busy_SHIFT)) & DDRC_REGS_DBGSTAT_rank0_refresh_busy_MASK) |
| #define DDRC_REGS_DBGSTAT_rank1_refresh_busy_MASK (0x2U) |
| #define DDRC_REGS_DBGSTAT_rank1_refresh_busy_SHIFT (1U) |
| #define DDRC_REGS_DBGSTAT_rank1_refresh_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGSTAT_rank1_refresh_busy_SHIFT)) & DDRC_REGS_DBGSTAT_rank1_refresh_busy_MASK) |
| #define DDRC_REGS_DBGSTAT_zq_calib_short_busy_MASK (0x10U) |
| #define DDRC_REGS_DBGSTAT_zq_calib_short_busy_SHIFT (4U) |
| #define DDRC_REGS_DBGSTAT_zq_calib_short_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGSTAT_zq_calib_short_busy_SHIFT)) & DDRC_REGS_DBGSTAT_zq_calib_short_busy_MASK) |
| #define DDRC_REGS_DBGSTAT_ctrlupd_busy_MASK (0x20U) |
| #define DDRC_REGS_DBGSTAT_ctrlupd_busy_SHIFT (5U) |
| #define DDRC_REGS_DBGSTAT_ctrlupd_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DBGSTAT_ctrlupd_busy_SHIFT)) & DDRC_REGS_DBGSTAT_ctrlupd_busy_MASK) |
| /*! @} */ |
| |
| /*! @name SWCTL - Software Register Programming Control Enable */ |
| /*! @{ */ |
| #define DDRC_REGS_SWCTL_sw_done_MASK (0x1U) |
| #define DDRC_REGS_SWCTL_sw_done_SHIFT (0U) |
| #define DDRC_REGS_SWCTL_sw_done(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_SWCTL_sw_done_SHIFT)) & DDRC_REGS_SWCTL_sw_done_MASK) |
| /*! @} */ |
| |
| /*! @name SWSTAT - Software Register Programming Control Status */ |
| /*! @{ */ |
| #define DDRC_REGS_SWSTAT_sw_done_ack_MASK (0x1U) |
| #define DDRC_REGS_SWSTAT_sw_done_ack_SHIFT (0U) |
| #define DDRC_REGS_SWSTAT_sw_done_ack(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_SWSTAT_sw_done_ack_SHIFT)) & DDRC_REGS_SWSTAT_sw_done_ack_MASK) |
| /*! @} */ |
| |
| /*! @name POISONCFG - AXI Poison Configuration Register. */ |
| /*! @{ */ |
| #define DDRC_REGS_POISONCFG_wr_poison_slverr_en_MASK (0x1U) |
| #define DDRC_REGS_POISONCFG_wr_poison_slverr_en_SHIFT (0U) |
| #define DDRC_REGS_POISONCFG_wr_poison_slverr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_POISONCFG_wr_poison_slverr_en_SHIFT)) & DDRC_REGS_POISONCFG_wr_poison_slverr_en_MASK) |
| #define DDRC_REGS_POISONCFG_wr_poison_intr_en_MASK (0x10U) |
| #define DDRC_REGS_POISONCFG_wr_poison_intr_en_SHIFT (4U) |
| #define DDRC_REGS_POISONCFG_wr_poison_intr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_POISONCFG_wr_poison_intr_en_SHIFT)) & DDRC_REGS_POISONCFG_wr_poison_intr_en_MASK) |
| #define DDRC_REGS_POISONCFG_wr_poison_intr_clr_MASK (0x100U) |
| #define DDRC_REGS_POISONCFG_wr_poison_intr_clr_SHIFT (8U) |
| #define DDRC_REGS_POISONCFG_wr_poison_intr_clr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_POISONCFG_wr_poison_intr_clr_SHIFT)) & DDRC_REGS_POISONCFG_wr_poison_intr_clr_MASK) |
| #define DDRC_REGS_POISONCFG_rd_poison_slverr_en_MASK (0x10000U) |
| #define DDRC_REGS_POISONCFG_rd_poison_slverr_en_SHIFT (16U) |
| #define DDRC_REGS_POISONCFG_rd_poison_slverr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_POISONCFG_rd_poison_slverr_en_SHIFT)) & DDRC_REGS_POISONCFG_rd_poison_slverr_en_MASK) |
| #define DDRC_REGS_POISONCFG_rd_poison_intr_en_MASK (0x100000U) |
| #define DDRC_REGS_POISONCFG_rd_poison_intr_en_SHIFT (20U) |
| #define DDRC_REGS_POISONCFG_rd_poison_intr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_POISONCFG_rd_poison_intr_en_SHIFT)) & DDRC_REGS_POISONCFG_rd_poison_intr_en_MASK) |
| #define DDRC_REGS_POISONCFG_rd_poison_intr_clr_MASK (0x1000000U) |
| #define DDRC_REGS_POISONCFG_rd_poison_intr_clr_SHIFT (24U) |
| #define DDRC_REGS_POISONCFG_rd_poison_intr_clr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_POISONCFG_rd_poison_intr_clr_SHIFT)) & DDRC_REGS_POISONCFG_rd_poison_intr_clr_MASK) |
| /*! @} */ |
| |
| /*! @name POISONSTAT - AXI Poison Status Register */ |
| /*! @{ */ |
| #define DDRC_REGS_POISONSTAT_wr_poison_intr_0_MASK (0x1U) |
| #define DDRC_REGS_POISONSTAT_wr_poison_intr_0_SHIFT (0U) |
| #define DDRC_REGS_POISONSTAT_wr_poison_intr_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_POISONSTAT_wr_poison_intr_0_SHIFT)) & DDRC_REGS_POISONSTAT_wr_poison_intr_0_MASK) |
| #define DDRC_REGS_POISONSTAT_rd_poison_intr_0_MASK (0x10000U) |
| #define DDRC_REGS_POISONSTAT_rd_poison_intr_0_SHIFT (16U) |
| #define DDRC_REGS_POISONSTAT_rd_poison_intr_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_POISONSTAT_rd_poison_intr_0_SHIFT)) & DDRC_REGS_POISONSTAT_rd_poison_intr_0_MASK) |
| /*! @} */ |
| |
| /*! @name PSTAT - Port Status Register */ |
| /*! @{ */ |
| #define DDRC_REGS_PSTAT_rd_port_busy_0_MASK (0x1U) |
| #define DDRC_REGS_PSTAT_rd_port_busy_0_SHIFT (0U) |
| #define DDRC_REGS_PSTAT_rd_port_busy_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PSTAT_rd_port_busy_0_SHIFT)) & DDRC_REGS_PSTAT_rd_port_busy_0_MASK) |
| #define DDRC_REGS_PSTAT_wr_port_busy_0_MASK (0x10000U) |
| #define DDRC_REGS_PSTAT_wr_port_busy_0_SHIFT (16U) |
| #define DDRC_REGS_PSTAT_wr_port_busy_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PSTAT_wr_port_busy_0_SHIFT)) & DDRC_REGS_PSTAT_wr_port_busy_0_MASK) |
| /*! @} */ |
| |
| /*! @name PCCFG - Port Common Configuration Register */ |
| /*! @{ */ |
| #define DDRC_REGS_PCCFG_go2critical_en_MASK (0x1U) |
| #define DDRC_REGS_PCCFG_go2critical_en_SHIFT (0U) |
| #define DDRC_REGS_PCCFG_go2critical_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCCFG_go2critical_en_SHIFT)) & DDRC_REGS_PCCFG_go2critical_en_MASK) |
| #define DDRC_REGS_PCCFG_pagematch_limit_MASK (0x10U) |
| #define DDRC_REGS_PCCFG_pagematch_limit_SHIFT (4U) |
| #define DDRC_REGS_PCCFG_pagematch_limit(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCCFG_pagematch_limit_SHIFT)) & DDRC_REGS_PCCFG_pagematch_limit_MASK) |
| #define DDRC_REGS_PCCFG_bl_exp_mode_MASK (0x100U) |
| #define DDRC_REGS_PCCFG_bl_exp_mode_SHIFT (8U) |
| #define DDRC_REGS_PCCFG_bl_exp_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCCFG_bl_exp_mode_SHIFT)) & DDRC_REGS_PCCFG_bl_exp_mode_MASK) |
| /*! @} */ |
| |
| /*! @name PCFGR_0 - Port n Configuration Read Register */ |
| /*! @{ */ |
| #define DDRC_REGS_PCFGR_0_rd_port_priority_MASK (0x3FFU) |
| #define DDRC_REGS_PCFGR_0_rd_port_priority_SHIFT (0U) |
| #define DDRC_REGS_PCFGR_0_rd_port_priority(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGR_0_rd_port_priority_SHIFT)) & DDRC_REGS_PCFGR_0_rd_port_priority_MASK) |
| #define DDRC_REGS_PCFGR_0_rd_port_aging_en_MASK (0x1000U) |
| #define DDRC_REGS_PCFGR_0_rd_port_aging_en_SHIFT (12U) |
| #define DDRC_REGS_PCFGR_0_rd_port_aging_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGR_0_rd_port_aging_en_SHIFT)) & DDRC_REGS_PCFGR_0_rd_port_aging_en_MASK) |
| #define DDRC_REGS_PCFGR_0_rd_port_urgent_en_MASK (0x2000U) |
| #define DDRC_REGS_PCFGR_0_rd_port_urgent_en_SHIFT (13U) |
| #define DDRC_REGS_PCFGR_0_rd_port_urgent_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGR_0_rd_port_urgent_en_SHIFT)) & DDRC_REGS_PCFGR_0_rd_port_urgent_en_MASK) |
| #define DDRC_REGS_PCFGR_0_rd_port_pagematch_en_MASK (0x4000U) |
| #define DDRC_REGS_PCFGR_0_rd_port_pagematch_en_SHIFT (14U) |
| #define DDRC_REGS_PCFGR_0_rd_port_pagematch_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGR_0_rd_port_pagematch_en_SHIFT)) & DDRC_REGS_PCFGR_0_rd_port_pagematch_en_MASK) |
| #define DDRC_REGS_PCFGR_0_rdwr_ordered_en_MASK (0x10000U) |
| #define DDRC_REGS_PCFGR_0_rdwr_ordered_en_SHIFT (16U) |
| #define DDRC_REGS_PCFGR_0_rdwr_ordered_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGR_0_rdwr_ordered_en_SHIFT)) & DDRC_REGS_PCFGR_0_rdwr_ordered_en_MASK) |
| /*! @} */ |
| |
| /*! @name PCFGW_0 - Port n Configuration Write Register */ |
| /*! @{ */ |
| #define DDRC_REGS_PCFGW_0_wr_port_priority_MASK (0x3FFU) |
| #define DDRC_REGS_PCFGW_0_wr_port_priority_SHIFT (0U) |
| #define DDRC_REGS_PCFGW_0_wr_port_priority(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGW_0_wr_port_priority_SHIFT)) & DDRC_REGS_PCFGW_0_wr_port_priority_MASK) |
| #define DDRC_REGS_PCFGW_0_wr_port_aging_en_MASK (0x1000U) |
| #define DDRC_REGS_PCFGW_0_wr_port_aging_en_SHIFT (12U) |
| #define DDRC_REGS_PCFGW_0_wr_port_aging_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGW_0_wr_port_aging_en_SHIFT)) & DDRC_REGS_PCFGW_0_wr_port_aging_en_MASK) |
| #define DDRC_REGS_PCFGW_0_wr_port_urgent_en_MASK (0x2000U) |
| #define DDRC_REGS_PCFGW_0_wr_port_urgent_en_SHIFT (13U) |
| #define DDRC_REGS_PCFGW_0_wr_port_urgent_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGW_0_wr_port_urgent_en_SHIFT)) & DDRC_REGS_PCFGW_0_wr_port_urgent_en_MASK) |
| #define DDRC_REGS_PCFGW_0_wr_port_pagematch_en_MASK (0x4000U) |
| #define DDRC_REGS_PCFGW_0_wr_port_pagematch_en_SHIFT (14U) |
| #define DDRC_REGS_PCFGW_0_wr_port_pagematch_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGW_0_wr_port_pagematch_en_SHIFT)) & DDRC_REGS_PCFGW_0_wr_port_pagematch_en_MASK) |
| /*! @} */ |
| |
| /*! @name PCTRL_0 - Port n Control Register */ |
| /*! @{ */ |
| #define DDRC_REGS_PCTRL_0_port_en_MASK (0x1U) |
| #define DDRC_REGS_PCTRL_0_port_en_SHIFT (0U) |
| #define DDRC_REGS_PCTRL_0_port_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCTRL_0_port_en_SHIFT)) & DDRC_REGS_PCTRL_0_port_en_MASK) |
| /*! @} */ |
| |
| /*! @name PCFGQOS0_0 - Port n Read QoS Configuration Register 0 */ |
| /*! @{ */ |
| #define DDRC_REGS_PCFGQOS0_0_rqos_map_level1_MASK (0xFU) |
| #define DDRC_REGS_PCFGQOS0_0_rqos_map_level1_SHIFT (0U) |
| #define DDRC_REGS_PCFGQOS0_0_rqos_map_level1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGQOS0_0_rqos_map_level1_SHIFT)) & DDRC_REGS_PCFGQOS0_0_rqos_map_level1_MASK) |
| #define DDRC_REGS_PCFGQOS0_0_rqos_map_region0_MASK (0x30000U) |
| #define DDRC_REGS_PCFGQOS0_0_rqos_map_region0_SHIFT (16U) |
| #define DDRC_REGS_PCFGQOS0_0_rqos_map_region0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGQOS0_0_rqos_map_region0_SHIFT)) & DDRC_REGS_PCFGQOS0_0_rqos_map_region0_MASK) |
| #define DDRC_REGS_PCFGQOS0_0_rqos_map_region1_MASK (0x300000U) |
| #define DDRC_REGS_PCFGQOS0_0_rqos_map_region1_SHIFT (20U) |
| #define DDRC_REGS_PCFGQOS0_0_rqos_map_region1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGQOS0_0_rqos_map_region1_SHIFT)) & DDRC_REGS_PCFGQOS0_0_rqos_map_region1_MASK) |
| /*! @} */ |
| |
| /*! @name PCFGQOS1_0 - Port n Read QoS Configuration Register 1 */ |
| /*! @{ */ |
| #define DDRC_REGS_PCFGQOS1_0_rqos_map_timeoutb_MASK (0x7FFU) |
| #define DDRC_REGS_PCFGQOS1_0_rqos_map_timeoutb_SHIFT (0U) |
| #define DDRC_REGS_PCFGQOS1_0_rqos_map_timeoutb(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGQOS1_0_rqos_map_timeoutb_SHIFT)) & DDRC_REGS_PCFGQOS1_0_rqos_map_timeoutb_MASK) |
| #define DDRC_REGS_PCFGQOS1_0_rqos_map_timeoutr_MASK (0x7FF0000U) |
| #define DDRC_REGS_PCFGQOS1_0_rqos_map_timeoutr_SHIFT (16U) |
| #define DDRC_REGS_PCFGQOS1_0_rqos_map_timeoutr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGQOS1_0_rqos_map_timeoutr_SHIFT)) & DDRC_REGS_PCFGQOS1_0_rqos_map_timeoutr_MASK) |
| /*! @} */ |
| |
| /*! @name PCFGWQOS0_0 - Port n Write QoS Configuration Register 0 */ |
| /*! @{ */ |
| #define DDRC_REGS_PCFGWQOS0_0_wqos_map_level_MASK (0xFU) |
| #define DDRC_REGS_PCFGWQOS0_0_wqos_map_level_SHIFT (0U) |
| #define DDRC_REGS_PCFGWQOS0_0_wqos_map_level(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGWQOS0_0_wqos_map_level_SHIFT)) & DDRC_REGS_PCFGWQOS0_0_wqos_map_level_MASK) |
| #define DDRC_REGS_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) |
| #define DDRC_REGS_PCFGWQOS0_0_wqos_map_region0_SHIFT (16U) |
| #define DDRC_REGS_PCFGWQOS0_0_wqos_map_region0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_REGS_PCFGWQOS0_0_wqos_map_region0_MASK) |
| #define DDRC_REGS_PCFGWQOS0_0_wqos_map_region1_MASK (0x300000U) |
| #define DDRC_REGS_PCFGWQOS0_0_wqos_map_region1_SHIFT (20U) |
| #define DDRC_REGS_PCFGWQOS0_0_wqos_map_region1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGWQOS0_0_wqos_map_region1_SHIFT)) & DDRC_REGS_PCFGWQOS0_0_wqos_map_region1_MASK) |
| /*! @} */ |
| |
| /*! @name PCFGWQOS1_0 - Port n Write QoS Configuration Register 1 */ |
| /*! @{ */ |
| #define DDRC_REGS_PCFGWQOS1_0_wqos_map_timeout_MASK (0x7FFU) |
| #define DDRC_REGS_PCFGWQOS1_0_wqos_map_timeout_SHIFT (0U) |
| #define DDRC_REGS_PCFGWQOS1_0_wqos_map_timeout(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_PCFGWQOS1_0_wqos_map_timeout_SHIFT)) & DDRC_REGS_PCFGWQOS1_0_wqos_map_timeout_MASK) |
| /*! @} */ |
| |
| /*! @name DERATEEN_SHADOW - [SHADOW] Temperature Derate Enable Register */ |
| /*! @{ */ |
| #define DDRC_REGS_DERATEEN_SHADOW_derate_enable_MASK (0x1U) |
| #define DDRC_REGS_DERATEEN_SHADOW_derate_enable_SHIFT (0U) |
| #define DDRC_REGS_DERATEEN_SHADOW_derate_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DERATEEN_SHADOW_derate_enable_SHIFT)) & DDRC_REGS_DERATEEN_SHADOW_derate_enable_MASK) |
| #define DDRC_REGS_DERATEEN_SHADOW_derate_value_MASK (0x2U) |
| #define DDRC_REGS_DERATEEN_SHADOW_derate_value_SHIFT (1U) |
| #define DDRC_REGS_DERATEEN_SHADOW_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DERATEEN_SHADOW_derate_value_SHIFT)) & DDRC_REGS_DERATEEN_SHADOW_derate_value_MASK) |
| #define DDRC_REGS_DERATEEN_SHADOW_derate_byte_MASK (0xF0U) |
| #define DDRC_REGS_DERATEEN_SHADOW_derate_byte_SHIFT (4U) |
| #define DDRC_REGS_DERATEEN_SHADOW_derate_byte(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DERATEEN_SHADOW_derate_byte_SHIFT)) & DDRC_REGS_DERATEEN_SHADOW_derate_byte_MASK) |
| #define DDRC_REGS_DERATEEN_SHADOW_rc_derate_value_MASK (0x300U) |
| #define DDRC_REGS_DERATEEN_SHADOW_rc_derate_value_SHIFT (8U) |
| #define DDRC_REGS_DERATEEN_SHADOW_rc_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DERATEEN_SHADOW_rc_derate_value_SHIFT)) & DDRC_REGS_DERATEEN_SHADOW_rc_derate_value_MASK) |
| /*! @} */ |
| |
| /*! @name DERATEINT_SHADOW - [SHADOW] Temperature Derate Interval Register */ |
| /*! @{ */ |
| #define DDRC_REGS_DERATEINT_SHADOW_mr4_read_interval_MASK (0xFFFFFFFFU) |
| #define DDRC_REGS_DERATEINT_SHADOW_mr4_read_interval_SHIFT (0U) |
| #define DDRC_REGS_DERATEINT_SHADOW_mr4_read_interval(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DERATEINT_SHADOW_mr4_read_interval_SHIFT)) & DDRC_REGS_DERATEINT_SHADOW_mr4_read_interval_MASK) |
| /*! @} */ |
| |
| /*! @name RFSHCTL0_SHADOW - [SHADOW] Refresh Control Register 0 */ |
| /*! @{ */ |
| #define DDRC_REGS_RFSHCTL0_SHADOW_per_bank_refresh_MASK (0x4U) |
| #define DDRC_REGS_RFSHCTL0_SHADOW_per_bank_refresh_SHIFT (2U) |
| #define DDRC_REGS_RFSHCTL0_SHADOW_per_bank_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL0_SHADOW_per_bank_refresh_SHIFT)) & DDRC_REGS_RFSHCTL0_SHADOW_per_bank_refresh_MASK) |
| #define DDRC_REGS_RFSHCTL0_SHADOW_refresh_burst_MASK (0x1F0U) |
| #define DDRC_REGS_RFSHCTL0_SHADOW_refresh_burst_SHIFT (4U) |
| #define DDRC_REGS_RFSHCTL0_SHADOW_refresh_burst(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL0_SHADOW_refresh_burst_SHIFT)) & DDRC_REGS_RFSHCTL0_SHADOW_refresh_burst_MASK) |
| #define DDRC_REGS_RFSHCTL0_SHADOW_refresh_to_x32_MASK (0x1F000U) |
| #define DDRC_REGS_RFSHCTL0_SHADOW_refresh_to_x32_SHIFT (12U) |
| #define DDRC_REGS_RFSHCTL0_SHADOW_refresh_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL0_SHADOW_refresh_to_x32_SHIFT)) & DDRC_REGS_RFSHCTL0_SHADOW_refresh_to_x32_MASK) |
| #define DDRC_REGS_RFSHCTL0_SHADOW_refresh_margin_MASK (0xF00000U) |
| #define DDRC_REGS_RFSHCTL0_SHADOW_refresh_margin_SHIFT (20U) |
| #define DDRC_REGS_RFSHCTL0_SHADOW_refresh_margin(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHCTL0_SHADOW_refresh_margin_SHIFT)) & DDRC_REGS_RFSHCTL0_SHADOW_refresh_margin_MASK) |
| /*! @} */ |
| |
| /*! @name RFSHTMG_SHADOW - [SHADOW] Refresh Timing Register */ |
| /*! @{ */ |
| #define DDRC_REGS_RFSHTMG_SHADOW_t_rfc_min_MASK (0x3FFU) |
| #define DDRC_REGS_RFSHTMG_SHADOW_t_rfc_min_SHIFT (0U) |
| #define DDRC_REGS_RFSHTMG_SHADOW_t_rfc_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHTMG_SHADOW_t_rfc_min_SHIFT)) & DDRC_REGS_RFSHTMG_SHADOW_t_rfc_min_MASK) |
| #define DDRC_REGS_RFSHTMG_SHADOW_lpddr3_trefbw_en_MASK (0x8000U) |
| #define DDRC_REGS_RFSHTMG_SHADOW_lpddr3_trefbw_en_SHIFT (15U) |
| #define DDRC_REGS_RFSHTMG_SHADOW_lpddr3_trefbw_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHTMG_SHADOW_lpddr3_trefbw_en_SHIFT)) & DDRC_REGS_RFSHTMG_SHADOW_lpddr3_trefbw_en_MASK) |
| #define DDRC_REGS_RFSHTMG_SHADOW_t_rfc_nom_x32_MASK (0xFFF0000U) |
| #define DDRC_REGS_RFSHTMG_SHADOW_t_rfc_nom_x32_SHIFT (16U) |
| #define DDRC_REGS_RFSHTMG_SHADOW_t_rfc_nom_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_RFSHTMG_SHADOW_t_rfc_nom_x32_SHIFT)) & DDRC_REGS_RFSHTMG_SHADOW_t_rfc_nom_x32_MASK) |
| /*! @} */ |
| |
| /*! @name INIT3_SHADOW - [SHADOW] SDRAM Initialization Register 3 */ |
| /*! @{ */ |
| #define DDRC_REGS_INIT3_SHADOW_emr_MASK (0xFFFFU) |
| #define DDRC_REGS_INIT3_SHADOW_emr_SHIFT (0U) |
| #define DDRC_REGS_INIT3_SHADOW_emr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT3_SHADOW_emr_SHIFT)) & DDRC_REGS_INIT3_SHADOW_emr_MASK) |
| #define DDRC_REGS_INIT3_SHADOW_mr_MASK (0xFFFF0000U) |
| #define DDRC_REGS_INIT3_SHADOW_mr_SHIFT (16U) |
| #define DDRC_REGS_INIT3_SHADOW_mr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT3_SHADOW_mr_SHIFT)) & DDRC_REGS_INIT3_SHADOW_mr_MASK) |
| /*! @} */ |
| |
| /*! @name INIT4_SHADOW - [SHADOW] SDRAM Initialization Register 4 */ |
| /*! @{ */ |
| #define DDRC_REGS_INIT4_SHADOW_emr3_MASK (0xFFFFU) |
| #define DDRC_REGS_INIT4_SHADOW_emr3_SHIFT (0U) |
| #define DDRC_REGS_INIT4_SHADOW_emr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT4_SHADOW_emr3_SHIFT)) & DDRC_REGS_INIT4_SHADOW_emr3_MASK) |
| #define DDRC_REGS_INIT4_SHADOW_emr2_MASK (0xFFFF0000U) |
| #define DDRC_REGS_INIT4_SHADOW_emr2_SHIFT (16U) |
| #define DDRC_REGS_INIT4_SHADOW_emr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT4_SHADOW_emr2_SHIFT)) & DDRC_REGS_INIT4_SHADOW_emr2_MASK) |
| /*! @} */ |
| |
| /*! @name INIT6_SHADOW - [SHADOW] SDRAM Initialization Register 6 */ |
| /*! @{ */ |
| #define DDRC_REGS_INIT6_SHADOW_mr5_MASK (0xFFFFU) |
| #define DDRC_REGS_INIT6_SHADOW_mr5_SHIFT (0U) |
| #define DDRC_REGS_INIT6_SHADOW_mr5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT6_SHADOW_mr5_SHIFT)) & DDRC_REGS_INIT6_SHADOW_mr5_MASK) |
| #define DDRC_REGS_INIT6_SHADOW_mr4_MASK (0xFFFF0000U) |
| #define DDRC_REGS_INIT6_SHADOW_mr4_SHIFT (16U) |
| #define DDRC_REGS_INIT6_SHADOW_mr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT6_SHADOW_mr4_SHIFT)) & DDRC_REGS_INIT6_SHADOW_mr4_MASK) |
| /*! @} */ |
| |
| /*! @name INIT7_SHADOW - [SHADOW] SDRAM Initialization Register 7 */ |
| /*! @{ */ |
| #define DDRC_REGS_INIT7_SHADOW_mr6_MASK (0xFFFF0000U) |
| #define DDRC_REGS_INIT7_SHADOW_mr6_SHIFT (16U) |
| #define DDRC_REGS_INIT7_SHADOW_mr6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_INIT7_SHADOW_mr6_SHIFT)) & DDRC_REGS_INIT7_SHADOW_mr6_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG0_SHADOW - [SHADOW] SDRAM Timing Register 0 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG0_SHADOW_t_ras_min_MASK (0x3FU) |
| #define DDRC_REGS_DRAMTMG0_SHADOW_t_ras_min_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG0_SHADOW_t_ras_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG0_SHADOW_t_ras_min_SHIFT)) & DDRC_REGS_DRAMTMG0_SHADOW_t_ras_min_MASK) |
| #define DDRC_REGS_DRAMTMG0_SHADOW_t_ras_max_MASK (0x7F00U) |
| #define DDRC_REGS_DRAMTMG0_SHADOW_t_ras_max_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG0_SHADOW_t_ras_max(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG0_SHADOW_t_ras_max_SHIFT)) & DDRC_REGS_DRAMTMG0_SHADOW_t_ras_max_MASK) |
| #define DDRC_REGS_DRAMTMG0_SHADOW_t_faw_MASK (0x3F0000U) |
| #define DDRC_REGS_DRAMTMG0_SHADOW_t_faw_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG0_SHADOW_t_faw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG0_SHADOW_t_faw_SHIFT)) & DDRC_REGS_DRAMTMG0_SHADOW_t_faw_MASK) |
| #define DDRC_REGS_DRAMTMG0_SHADOW_wr2pre_MASK (0x7F000000U) |
| #define DDRC_REGS_DRAMTMG0_SHADOW_wr2pre_SHIFT (24U) |
| #define DDRC_REGS_DRAMTMG0_SHADOW_wr2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG0_SHADOW_wr2pre_SHIFT)) & DDRC_REGS_DRAMTMG0_SHADOW_wr2pre_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG1_SHADOW - [SHADOW] SDRAM Timing Register 1 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG1_SHADOW_t_rc_MASK (0x7FU) |
| #define DDRC_REGS_DRAMTMG1_SHADOW_t_rc_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG1_SHADOW_t_rc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG1_SHADOW_t_rc_SHIFT)) & DDRC_REGS_DRAMTMG1_SHADOW_t_rc_MASK) |
| #define DDRC_REGS_DRAMTMG1_SHADOW_rd2pre_MASK (0x3F00U) |
| #define DDRC_REGS_DRAMTMG1_SHADOW_rd2pre_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG1_SHADOW_rd2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG1_SHADOW_rd2pre_SHIFT)) & DDRC_REGS_DRAMTMG1_SHADOW_rd2pre_MASK) |
| #define DDRC_REGS_DRAMTMG1_SHADOW_t_xp_MASK (0x1F0000U) |
| #define DDRC_REGS_DRAMTMG1_SHADOW_t_xp_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG1_SHADOW_t_xp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG1_SHADOW_t_xp_SHIFT)) & DDRC_REGS_DRAMTMG1_SHADOW_t_xp_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG2_SHADOW - [SHADOW] SDRAM Timing Register 2 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG2_SHADOW_wr2rd_MASK (0x3FU) |
| #define DDRC_REGS_DRAMTMG2_SHADOW_wr2rd_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG2_SHADOW_wr2rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG2_SHADOW_wr2rd_SHIFT)) & DDRC_REGS_DRAMTMG2_SHADOW_wr2rd_MASK) |
| #define DDRC_REGS_DRAMTMG2_SHADOW_rd2wr_MASK (0x3F00U) |
| #define DDRC_REGS_DRAMTMG2_SHADOW_rd2wr_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG2_SHADOW_rd2wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG2_SHADOW_rd2wr_SHIFT)) & DDRC_REGS_DRAMTMG2_SHADOW_rd2wr_MASK) |
| #define DDRC_REGS_DRAMTMG2_SHADOW_read_latency_MASK (0x3F0000U) |
| #define DDRC_REGS_DRAMTMG2_SHADOW_read_latency_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG2_SHADOW_read_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG2_SHADOW_read_latency_SHIFT)) & DDRC_REGS_DRAMTMG2_SHADOW_read_latency_MASK) |
| #define DDRC_REGS_DRAMTMG2_SHADOW_write_latency_MASK (0x3F000000U) |
| #define DDRC_REGS_DRAMTMG2_SHADOW_write_latency_SHIFT (24U) |
| #define DDRC_REGS_DRAMTMG2_SHADOW_write_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG2_SHADOW_write_latency_SHIFT)) & DDRC_REGS_DRAMTMG2_SHADOW_write_latency_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG3_SHADOW - [SHADOW] SDRAM Timing Register 3 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG3_SHADOW_t_mod_MASK (0x3FFU) |
| #define DDRC_REGS_DRAMTMG3_SHADOW_t_mod_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG3_SHADOW_t_mod(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG3_SHADOW_t_mod_SHIFT)) & DDRC_REGS_DRAMTMG3_SHADOW_t_mod_MASK) |
| #define DDRC_REGS_DRAMTMG3_SHADOW_t_mrd_MASK (0x3F000U) |
| #define DDRC_REGS_DRAMTMG3_SHADOW_t_mrd_SHIFT (12U) |
| #define DDRC_REGS_DRAMTMG3_SHADOW_t_mrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG3_SHADOW_t_mrd_SHIFT)) & DDRC_REGS_DRAMTMG3_SHADOW_t_mrd_MASK) |
| #define DDRC_REGS_DRAMTMG3_SHADOW_t_mrw_MASK (0x3FF00000U) |
| #define DDRC_REGS_DRAMTMG3_SHADOW_t_mrw_SHIFT (20U) |
| #define DDRC_REGS_DRAMTMG3_SHADOW_t_mrw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG3_SHADOW_t_mrw_SHIFT)) & DDRC_REGS_DRAMTMG3_SHADOW_t_mrw_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG4_SHADOW - [SHADOW] SDRAM Timing Register 4 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG4_SHADOW_t_rp_MASK (0x1FU) |
| #define DDRC_REGS_DRAMTMG4_SHADOW_t_rp_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG4_SHADOW_t_rp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG4_SHADOW_t_rp_SHIFT)) & DDRC_REGS_DRAMTMG4_SHADOW_t_rp_MASK) |
| #define DDRC_REGS_DRAMTMG4_SHADOW_t_rrd_MASK (0xF00U) |
| #define DDRC_REGS_DRAMTMG4_SHADOW_t_rrd_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG4_SHADOW_t_rrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG4_SHADOW_t_rrd_SHIFT)) & DDRC_REGS_DRAMTMG4_SHADOW_t_rrd_MASK) |
| #define DDRC_REGS_DRAMTMG4_SHADOW_t_ccd_MASK (0xF0000U) |
| #define DDRC_REGS_DRAMTMG4_SHADOW_t_ccd_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG4_SHADOW_t_ccd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG4_SHADOW_t_ccd_SHIFT)) & DDRC_REGS_DRAMTMG4_SHADOW_t_ccd_MASK) |
| #define DDRC_REGS_DRAMTMG4_SHADOW_t_rcd_MASK (0x1F000000U) |
| #define DDRC_REGS_DRAMTMG4_SHADOW_t_rcd_SHIFT (24U) |
| #define DDRC_REGS_DRAMTMG4_SHADOW_t_rcd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG4_SHADOW_t_rcd_SHIFT)) & DDRC_REGS_DRAMTMG4_SHADOW_t_rcd_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG5_SHADOW - [SHADOW] SDRAM Timing Register 5 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG5_SHADOW_t_cke_MASK (0x1FU) |
| #define DDRC_REGS_DRAMTMG5_SHADOW_t_cke_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG5_SHADOW_t_cke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG5_SHADOW_t_cke_SHIFT)) & DDRC_REGS_DRAMTMG5_SHADOW_t_cke_MASK) |
| #define DDRC_REGS_DRAMTMG5_SHADOW_t_ckesr_MASK (0x3F00U) |
| #define DDRC_REGS_DRAMTMG5_SHADOW_t_ckesr_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG5_SHADOW_t_ckesr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG5_SHADOW_t_ckesr_SHIFT)) & DDRC_REGS_DRAMTMG5_SHADOW_t_ckesr_MASK) |
| #define DDRC_REGS_DRAMTMG5_SHADOW_t_cksre_MASK (0xF0000U) |
| #define DDRC_REGS_DRAMTMG5_SHADOW_t_cksre_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG5_SHADOW_t_cksre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG5_SHADOW_t_cksre_SHIFT)) & DDRC_REGS_DRAMTMG5_SHADOW_t_cksre_MASK) |
| #define DDRC_REGS_DRAMTMG5_SHADOW_t_cksrx_MASK (0xF000000U) |
| #define DDRC_REGS_DRAMTMG5_SHADOW_t_cksrx_SHIFT (24U) |
| #define DDRC_REGS_DRAMTMG5_SHADOW_t_cksrx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG5_SHADOW_t_cksrx_SHIFT)) & DDRC_REGS_DRAMTMG5_SHADOW_t_cksrx_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG6_SHADOW - [SHADOW] SDRAM Timing Register 6 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG6_SHADOW_t_ckcsx_MASK (0xFU) |
| #define DDRC_REGS_DRAMTMG6_SHADOW_t_ckcsx_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG6_SHADOW_t_ckcsx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG6_SHADOW_t_ckcsx_SHIFT)) & DDRC_REGS_DRAMTMG6_SHADOW_t_ckcsx_MASK) |
| #define DDRC_REGS_DRAMTMG6_SHADOW_t_ckdpdx_MASK (0xF0000U) |
| #define DDRC_REGS_DRAMTMG6_SHADOW_t_ckdpdx_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG6_SHADOW_t_ckdpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG6_SHADOW_t_ckdpdx_SHIFT)) & DDRC_REGS_DRAMTMG6_SHADOW_t_ckdpdx_MASK) |
| #define DDRC_REGS_DRAMTMG6_SHADOW_t_ckdpde_MASK (0xF000000U) |
| #define DDRC_REGS_DRAMTMG6_SHADOW_t_ckdpde_SHIFT (24U) |
| #define DDRC_REGS_DRAMTMG6_SHADOW_t_ckdpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG6_SHADOW_t_ckdpde_SHIFT)) & DDRC_REGS_DRAMTMG6_SHADOW_t_ckdpde_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG7_SHADOW - [SHADOW] SDRAM Timing Register 7 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG7_SHADOW_t_ckpdx_MASK (0xFU) |
| #define DDRC_REGS_DRAMTMG7_SHADOW_t_ckpdx_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG7_SHADOW_t_ckpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG7_SHADOW_t_ckpdx_SHIFT)) & DDRC_REGS_DRAMTMG7_SHADOW_t_ckpdx_MASK) |
| #define DDRC_REGS_DRAMTMG7_SHADOW_t_ckpde_MASK (0xF00U) |
| #define DDRC_REGS_DRAMTMG7_SHADOW_t_ckpde_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG7_SHADOW_t_ckpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG7_SHADOW_t_ckpde_SHIFT)) & DDRC_REGS_DRAMTMG7_SHADOW_t_ckpde_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG8_SHADOW - [SHADOW] SDRAM Timing Register 8 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_x32_MASK (0x7FU) |
| #define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_x32_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG8_SHADOW_t_xs_x32_SHIFT)) & DDRC_REGS_DRAMTMG8_SHADOW_t_xs_x32_MASK) |
| #define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_dll_x32_MASK (0x7F00U) |
| #define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_dll_x32_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_dll_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG8_SHADOW_t_xs_dll_x32_SHIFT)) & DDRC_REGS_DRAMTMG8_SHADOW_t_xs_dll_x32_MASK) |
| #define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_abort_x32_MASK (0x7F0000U) |
| #define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_abort_x32_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_abort_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG8_SHADOW_t_xs_abort_x32_SHIFT)) & DDRC_REGS_DRAMTMG8_SHADOW_t_xs_abort_x32_MASK) |
| #define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_fast_x32_MASK (0x7F000000U) |
| #define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_fast_x32_SHIFT (24U) |
| #define DDRC_REGS_DRAMTMG8_SHADOW_t_xs_fast_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG8_SHADOW_t_xs_fast_x32_SHIFT)) & DDRC_REGS_DRAMTMG8_SHADOW_t_xs_fast_x32_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG9_SHADOW - [SHADOW] SDRAM Timing Register 9 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG9_SHADOW_wr2rd_s_MASK (0x3FU) |
| #define DDRC_REGS_DRAMTMG9_SHADOW_wr2rd_s_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG9_SHADOW_wr2rd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG9_SHADOW_wr2rd_s_SHIFT)) & DDRC_REGS_DRAMTMG9_SHADOW_wr2rd_s_MASK) |
| #define DDRC_REGS_DRAMTMG9_SHADOW_t_rrd_s_MASK (0xF00U) |
| #define DDRC_REGS_DRAMTMG9_SHADOW_t_rrd_s_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG9_SHADOW_t_rrd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG9_SHADOW_t_rrd_s_SHIFT)) & DDRC_REGS_DRAMTMG9_SHADOW_t_rrd_s_MASK) |
| #define DDRC_REGS_DRAMTMG9_SHADOW_t_ccd_s_MASK (0x70000U) |
| #define DDRC_REGS_DRAMTMG9_SHADOW_t_ccd_s_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG9_SHADOW_t_ccd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG9_SHADOW_t_ccd_s_SHIFT)) & DDRC_REGS_DRAMTMG9_SHADOW_t_ccd_s_MASK) |
| #define DDRC_REGS_DRAMTMG9_SHADOW_ddr4_wr_preamble_MASK (0x40000000U) |
| #define DDRC_REGS_DRAMTMG9_SHADOW_ddr4_wr_preamble_SHIFT (30U) |
| #define DDRC_REGS_DRAMTMG9_SHADOW_ddr4_wr_preamble(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG9_SHADOW_ddr4_wr_preamble_SHIFT)) & DDRC_REGS_DRAMTMG9_SHADOW_ddr4_wr_preamble_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG10_SHADOW - [SHADOW] SDRAM Timing Register 10 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG10_SHADOW_t_gear_hold_MASK (0x3U) |
| #define DDRC_REGS_DRAMTMG10_SHADOW_t_gear_hold_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG10_SHADOW_t_gear_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG10_SHADOW_t_gear_hold_SHIFT)) & DDRC_REGS_DRAMTMG10_SHADOW_t_gear_hold_MASK) |
| #define DDRC_REGS_DRAMTMG10_SHADOW_t_gear_setup_MASK (0xCU) |
| #define DDRC_REGS_DRAMTMG10_SHADOW_t_gear_setup_SHIFT (2U) |
| #define DDRC_REGS_DRAMTMG10_SHADOW_t_gear_setup(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG10_SHADOW_t_gear_setup_SHIFT)) & DDRC_REGS_DRAMTMG10_SHADOW_t_gear_setup_MASK) |
| #define DDRC_REGS_DRAMTMG10_SHADOW_t_cmd_gear_MASK (0x1F00U) |
| #define DDRC_REGS_DRAMTMG10_SHADOW_t_cmd_gear_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG10_SHADOW_t_cmd_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG10_SHADOW_t_cmd_gear_SHIFT)) & DDRC_REGS_DRAMTMG10_SHADOW_t_cmd_gear_MASK) |
| #define DDRC_REGS_DRAMTMG10_SHADOW_t_sync_gear_MASK (0x1F0000U) |
| #define DDRC_REGS_DRAMTMG10_SHADOW_t_sync_gear_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG10_SHADOW_t_sync_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG10_SHADOW_t_sync_gear_SHIFT)) & DDRC_REGS_DRAMTMG10_SHADOW_t_sync_gear_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG11_SHADOW - [SHADOW] SDRAM Timing Register 11 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG11_SHADOW_t_ckmpe_MASK (0x1FU) |
| #define DDRC_REGS_DRAMTMG11_SHADOW_t_ckmpe_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG11_SHADOW_t_ckmpe(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG11_SHADOW_t_ckmpe_SHIFT)) & DDRC_REGS_DRAMTMG11_SHADOW_t_ckmpe_MASK) |
| #define DDRC_REGS_DRAMTMG11_SHADOW_t_mpx_s_MASK (0x300U) |
| #define DDRC_REGS_DRAMTMG11_SHADOW_t_mpx_s_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG11_SHADOW_t_mpx_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG11_SHADOW_t_mpx_s_SHIFT)) & DDRC_REGS_DRAMTMG11_SHADOW_t_mpx_s_MASK) |
| #define DDRC_REGS_DRAMTMG11_SHADOW_t_mpx_lh_MASK (0x1F0000U) |
| #define DDRC_REGS_DRAMTMG11_SHADOW_t_mpx_lh_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG11_SHADOW_t_mpx_lh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG11_SHADOW_t_mpx_lh_SHIFT)) & DDRC_REGS_DRAMTMG11_SHADOW_t_mpx_lh_MASK) |
| #define DDRC_REGS_DRAMTMG11_SHADOW_post_mpsm_gap_x32_MASK (0x7F000000U) |
| #define DDRC_REGS_DRAMTMG11_SHADOW_post_mpsm_gap_x32_SHIFT (24U) |
| #define DDRC_REGS_DRAMTMG11_SHADOW_post_mpsm_gap_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG11_SHADOW_post_mpsm_gap_x32_SHIFT)) & DDRC_REGS_DRAMTMG11_SHADOW_post_mpsm_gap_x32_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG12_SHADOW - [SHADOW] SDRAM Timing Register 12 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG12_SHADOW_t_mrd_pda_MASK (0x1FU) |
| #define DDRC_REGS_DRAMTMG12_SHADOW_t_mrd_pda_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG12_SHADOW_t_mrd_pda(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG12_SHADOW_t_mrd_pda_SHIFT)) & DDRC_REGS_DRAMTMG12_SHADOW_t_mrd_pda_MASK) |
| #define DDRC_REGS_DRAMTMG12_SHADOW_t_ckehcmd_MASK (0xF00U) |
| #define DDRC_REGS_DRAMTMG12_SHADOW_t_ckehcmd_SHIFT (8U) |
| #define DDRC_REGS_DRAMTMG12_SHADOW_t_ckehcmd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG12_SHADOW_t_ckehcmd_SHIFT)) & DDRC_REGS_DRAMTMG12_SHADOW_t_ckehcmd_MASK) |
| #define DDRC_REGS_DRAMTMG12_SHADOW_t_cmdcke_MASK (0x30000U) |
| #define DDRC_REGS_DRAMTMG12_SHADOW_t_cmdcke_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG12_SHADOW_t_cmdcke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG12_SHADOW_t_cmdcke_SHIFT)) & DDRC_REGS_DRAMTMG12_SHADOW_t_cmdcke_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG13_SHADOW - [SHADOW] SDRAM Timing Register 13 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG13_SHADOW_t_ppd_MASK (0x7U) |
| #define DDRC_REGS_DRAMTMG13_SHADOW_t_ppd_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG13_SHADOW_t_ppd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG13_SHADOW_t_ppd_SHIFT)) & DDRC_REGS_DRAMTMG13_SHADOW_t_ppd_MASK) |
| #define DDRC_REGS_DRAMTMG13_SHADOW_t_ccd_mw_MASK (0x3F0000U) |
| #define DDRC_REGS_DRAMTMG13_SHADOW_t_ccd_mw_SHIFT (16U) |
| #define DDRC_REGS_DRAMTMG13_SHADOW_t_ccd_mw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG13_SHADOW_t_ccd_mw_SHIFT)) & DDRC_REGS_DRAMTMG13_SHADOW_t_ccd_mw_MASK) |
| #define DDRC_REGS_DRAMTMG13_SHADOW_odtloff_MASK (0x7F000000U) |
| #define DDRC_REGS_DRAMTMG13_SHADOW_odtloff_SHIFT (24U) |
| #define DDRC_REGS_DRAMTMG13_SHADOW_odtloff(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG13_SHADOW_odtloff_SHIFT)) & DDRC_REGS_DRAMTMG13_SHADOW_odtloff_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG14_SHADOW - [SHADOW] SDRAM Timing Register 14 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG14_SHADOW_t_xsr_MASK (0xFFFU) |
| #define DDRC_REGS_DRAMTMG14_SHADOW_t_xsr_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG14_SHADOW_t_xsr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG14_SHADOW_t_xsr_SHIFT)) & DDRC_REGS_DRAMTMG14_SHADOW_t_xsr_MASK) |
| /*! @} */ |
| |
| /*! @name DRAMTMG15_SHADOW - [SHADOW] SDRAM Timing Register 15 */ |
| /*! @{ */ |
| #define DDRC_REGS_DRAMTMG15_SHADOW_t_stab_x32_MASK (0xFFU) |
| #define DDRC_REGS_DRAMTMG15_SHADOW_t_stab_x32_SHIFT (0U) |
| #define DDRC_REGS_DRAMTMG15_SHADOW_t_stab_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG15_SHADOW_t_stab_x32_SHIFT)) & DDRC_REGS_DRAMTMG15_SHADOW_t_stab_x32_MASK) |
| #define DDRC_REGS_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_MASK (0x80000000U) |
| #define DDRC_REGS_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_SHIFT (31U) |
| #define DDRC_REGS_DRAMTMG15_SHADOW_en_dfi_lp_t_stab(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_SHIFT)) & DDRC_REGS_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_MASK) |
| /*! @} */ |
| |
| /*! @name ZQCTL0_SHADOW - [SHADOW] ZQ Control Register 0 */ |
| /*! @{ */ |
| #define DDRC_REGS_ZQCTL0_SHADOW_t_zq_short_nop_MASK (0x3FFU) |
| #define DDRC_REGS_ZQCTL0_SHADOW_t_zq_short_nop_SHIFT (0U) |
| #define DDRC_REGS_ZQCTL0_SHADOW_t_zq_short_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_SHADOW_t_zq_short_nop_SHIFT)) & DDRC_REGS_ZQCTL0_SHADOW_t_zq_short_nop_MASK) |
| #define DDRC_REGS_ZQCTL0_SHADOW_t_zq_long_nop_MASK (0x7FF0000U) |
| #define DDRC_REGS_ZQCTL0_SHADOW_t_zq_long_nop_SHIFT (16U) |
| #define DDRC_REGS_ZQCTL0_SHADOW_t_zq_long_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_SHADOW_t_zq_long_nop_SHIFT)) & DDRC_REGS_ZQCTL0_SHADOW_t_zq_long_nop_MASK) |
| #define DDRC_REGS_ZQCTL0_SHADOW_dis_mpsmx_zqcl_MASK (0x10000000U) |
| #define DDRC_REGS_ZQCTL0_SHADOW_dis_mpsmx_zqcl_SHIFT (28U) |
| #define DDRC_REGS_ZQCTL0_SHADOW_dis_mpsmx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_SHADOW_dis_mpsmx_zqcl_SHIFT)) & DDRC_REGS_ZQCTL0_SHADOW_dis_mpsmx_zqcl_MASK) |
| #define DDRC_REGS_ZQCTL0_SHADOW_zq_resistor_shared_MASK (0x20000000U) |
| #define DDRC_REGS_ZQCTL0_SHADOW_zq_resistor_shared_SHIFT (29U) |
| #define DDRC_REGS_ZQCTL0_SHADOW_zq_resistor_shared(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_SHADOW_zq_resistor_shared_SHIFT)) & DDRC_REGS_ZQCTL0_SHADOW_zq_resistor_shared_MASK) |
| #define DDRC_REGS_ZQCTL0_SHADOW_dis_srx_zqcl_MASK (0x40000000U) |
| #define DDRC_REGS_ZQCTL0_SHADOW_dis_srx_zqcl_SHIFT (30U) |
| #define DDRC_REGS_ZQCTL0_SHADOW_dis_srx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_SHADOW_dis_srx_zqcl_SHIFT)) & DDRC_REGS_ZQCTL0_SHADOW_dis_srx_zqcl_MASK) |
| #define DDRC_REGS_ZQCTL0_SHADOW_dis_auto_zq_MASK (0x80000000U) |
| #define DDRC_REGS_ZQCTL0_SHADOW_dis_auto_zq_SHIFT (31U) |
| #define DDRC_REGS_ZQCTL0_SHADOW_dis_auto_zq(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ZQCTL0_SHADOW_dis_auto_zq_SHIFT)) & DDRC_REGS_ZQCTL0_SHADOW_dis_auto_zq_MASK) |
| /*! @} */ |
| |
| /*! @name DFITMG0_SHADOW - [SHADOW] DFI Timing Register 0 */ |
| /*! @{ */ |
| #define DDRC_REGS_DFITMG0_SHADOW_dfi_tphy_wrlat_MASK (0x3FU) |
| #define DDRC_REGS_DFITMG0_SHADOW_dfi_tphy_wrlat_SHIFT (0U) |
| #define DDRC_REGS_DFITMG0_SHADOW_dfi_tphy_wrlat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_SHADOW_dfi_tphy_wrlat_SHIFT)) & DDRC_REGS_DFITMG0_SHADOW_dfi_tphy_wrlat_MASK) |
| #define DDRC_REGS_DFITMG0_SHADOW_dfi_tphy_wrdata_MASK (0x3F00U) |
| #define DDRC_REGS_DFITMG0_SHADOW_dfi_tphy_wrdata_SHIFT (8U) |
| #define DDRC_REGS_DFITMG0_SHADOW_dfi_tphy_wrdata(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_SHADOW_dfi_tphy_wrdata_SHIFT)) & DDRC_REGS_DFITMG0_SHADOW_dfi_tphy_wrdata_MASK) |
| #define DDRC_REGS_DFITMG0_SHADOW_dfi_wrdata_use_sdr_MASK (0x8000U) |
| #define DDRC_REGS_DFITMG0_SHADOW_dfi_wrdata_use_sdr_SHIFT (15U) |
| #define DDRC_REGS_DFITMG0_SHADOW_dfi_wrdata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_SHADOW_dfi_wrdata_use_sdr_SHIFT)) & DDRC_REGS_DFITMG0_SHADOW_dfi_wrdata_use_sdr_MASK) |
| #define DDRC_REGS_DFITMG0_SHADOW_dfi_t_rddata_en_MASK (0x7F0000U) |
| #define DDRC_REGS_DFITMG0_SHADOW_dfi_t_rddata_en_SHIFT (16U) |
| #define DDRC_REGS_DFITMG0_SHADOW_dfi_t_rddata_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_SHADOW_dfi_t_rddata_en_SHIFT)) & DDRC_REGS_DFITMG0_SHADOW_dfi_t_rddata_en_MASK) |
| #define DDRC_REGS_DFITMG0_SHADOW_dfi_rddata_use_sdr_MASK (0x800000U) |
| #define DDRC_REGS_DFITMG0_SHADOW_dfi_rddata_use_sdr_SHIFT (23U) |
| #define DDRC_REGS_DFITMG0_SHADOW_dfi_rddata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_SHADOW_dfi_rddata_use_sdr_SHIFT)) & DDRC_REGS_DFITMG0_SHADOW_dfi_rddata_use_sdr_MASK) |
| #define DDRC_REGS_DFITMG0_SHADOW_dfi_t_ctrl_delay_MASK (0x1F000000U) |
| #define DDRC_REGS_DFITMG0_SHADOW_dfi_t_ctrl_delay_SHIFT (24U) |
| #define DDRC_REGS_DFITMG0_SHADOW_dfi_t_ctrl_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG0_SHADOW_dfi_t_ctrl_delay_SHIFT)) & DDRC_REGS_DFITMG0_SHADOW_dfi_t_ctrl_delay_MASK) |
| /*! @} */ |
| |
| /*! @name DFITMG1_SHADOW - [SHADOW] DFI Timing Register 1 */ |
| /*! @{ */ |
| #define DDRC_REGS_DFITMG1_SHADOW_dfi_t_dram_clk_enable_MASK (0x1FU) |
| #define DDRC_REGS_DFITMG1_SHADOW_dfi_t_dram_clk_enable_SHIFT (0U) |
| #define DDRC_REGS_DFITMG1_SHADOW_dfi_t_dram_clk_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG1_SHADOW_dfi_t_dram_clk_enable_SHIFT)) & DDRC_REGS_DFITMG1_SHADOW_dfi_t_dram_clk_enable_MASK) |
| #define DDRC_REGS_DFITMG1_SHADOW_dfi_t_dram_clk_disable_MASK (0x1F00U) |
| #define DDRC_REGS_DFITMG1_SHADOW_dfi_t_dram_clk_disable_SHIFT (8U) |
| #define DDRC_REGS_DFITMG1_SHADOW_dfi_t_dram_clk_disable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG1_SHADOW_dfi_t_dram_clk_disable_SHIFT)) & DDRC_REGS_DFITMG1_SHADOW_dfi_t_dram_clk_disable_MASK) |
| #define DDRC_REGS_DFITMG1_SHADOW_dfi_t_wrdata_delay_MASK (0x1F0000U) |
| #define DDRC_REGS_DFITMG1_SHADOW_dfi_t_wrdata_delay_SHIFT (16U) |
| #define DDRC_REGS_DFITMG1_SHADOW_dfi_t_wrdata_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG1_SHADOW_dfi_t_wrdata_delay_SHIFT)) & DDRC_REGS_DFITMG1_SHADOW_dfi_t_wrdata_delay_MASK) |
| #define DDRC_REGS_DFITMG1_SHADOW_dfi_t_parin_lat_MASK (0x3000000U) |
| #define DDRC_REGS_DFITMG1_SHADOW_dfi_t_parin_lat_SHIFT (24U) |
| #define DDRC_REGS_DFITMG1_SHADOW_dfi_t_parin_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG1_SHADOW_dfi_t_parin_lat_SHIFT)) & DDRC_REGS_DFITMG1_SHADOW_dfi_t_parin_lat_MASK) |
| #define DDRC_REGS_DFITMG1_SHADOW_dfi_t_cmd_lat_MASK (0xF0000000U) |
| #define DDRC_REGS_DFITMG1_SHADOW_dfi_t_cmd_lat_SHIFT (28U) |
| #define DDRC_REGS_DFITMG1_SHADOW_dfi_t_cmd_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG1_SHADOW_dfi_t_cmd_lat_SHIFT)) & DDRC_REGS_DFITMG1_SHADOW_dfi_t_cmd_lat_MASK) |
| /*! @} */ |
| |
| /*! @name DFITMG2_SHADOW - [SHADOW] DFI Timing Register 2 */ |
| /*! @{ */ |
| #define DDRC_REGS_DFITMG2_SHADOW_dfi_tphy_wrcslat_MASK (0x3FU) |
| #define DDRC_REGS_DFITMG2_SHADOW_dfi_tphy_wrcslat_SHIFT (0U) |
| #define DDRC_REGS_DFITMG2_SHADOW_dfi_tphy_wrcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG2_SHADOW_dfi_tphy_wrcslat_SHIFT)) & DDRC_REGS_DFITMG2_SHADOW_dfi_tphy_wrcslat_MASK) |
| #define DDRC_REGS_DFITMG2_SHADOW_dfi_tphy_rdcslat_MASK (0x7F00U) |
| #define DDRC_REGS_DFITMG2_SHADOW_dfi_tphy_rdcslat_SHIFT (8U) |
| #define DDRC_REGS_DFITMG2_SHADOW_dfi_tphy_rdcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG2_SHADOW_dfi_tphy_rdcslat_SHIFT)) & DDRC_REGS_DFITMG2_SHADOW_dfi_tphy_rdcslat_MASK) |
| /*! @} */ |
| |
| /*! @name DFITMG3_SHADOW - [SHADOW] DFI Timing Register 3 */ |
| /*! @{ */ |
| #define DDRC_REGS_DFITMG3_SHADOW_dfi_t_geardown_delay_MASK (0x1FU) |
| #define DDRC_REGS_DFITMG3_SHADOW_dfi_t_geardown_delay_SHIFT (0U) |
| #define DDRC_REGS_DFITMG3_SHADOW_dfi_t_geardown_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_DFITMG3_SHADOW_dfi_t_geardown_delay_SHIFT)) & DDRC_REGS_DFITMG3_SHADOW_dfi_t_geardown_delay_MASK) |
| /*! @} */ |
| |
| /*! @name ODTCFG_SHADOW - [SHADOW] ODT Configuration Register */ |
| /*! @{ */ |
| #define DDRC_REGS_ODTCFG_SHADOW_rd_odt_delay_MASK (0x7CU) |
| #define DDRC_REGS_ODTCFG_SHADOW_rd_odt_delay_SHIFT (2U) |
| #define DDRC_REGS_ODTCFG_SHADOW_rd_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTCFG_SHADOW_rd_odt_delay_SHIFT)) & DDRC_REGS_ODTCFG_SHADOW_rd_odt_delay_MASK) |
| #define DDRC_REGS_ODTCFG_SHADOW_rd_odt_hold_MASK (0xF00U) |
| #define DDRC_REGS_ODTCFG_SHADOW_rd_odt_hold_SHIFT (8U) |
| #define DDRC_REGS_ODTCFG_SHADOW_rd_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTCFG_SHADOW_rd_odt_hold_SHIFT)) & DDRC_REGS_ODTCFG_SHADOW_rd_odt_hold_MASK) |
| #define DDRC_REGS_ODTCFG_SHADOW_wr_odt_delay_MASK (0x1F0000U) |
| #define DDRC_REGS_ODTCFG_SHADOW_wr_odt_delay_SHIFT (16U) |
| #define DDRC_REGS_ODTCFG_SHADOW_wr_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTCFG_SHADOW_wr_odt_delay_SHIFT)) & DDRC_REGS_ODTCFG_SHADOW_wr_odt_delay_MASK) |
| #define DDRC_REGS_ODTCFG_SHADOW_wr_odt_hold_MASK (0xF000000U) |
| #define DDRC_REGS_ODTCFG_SHADOW_wr_odt_hold_SHIFT (24U) |
| #define DDRC_REGS_ODTCFG_SHADOW_wr_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REGS_ODTCFG_SHADOW_wr_odt_hold_SHIFT)) & DDRC_REGS_ODTCFG_SHADOW_wr_odt_hold_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group DDRC_REGS_Register_Masks */ |
| |
| |
| /* DDRC_REGS - Peripheral instance base addresses */ |
| /** Peripheral DDRC base address */ |
| #define DDRC_BASE (0x3D400000u) |
| /** Peripheral DDRC base pointer */ |
| #define DDRC ((DDRC_REGS_Type *)DDRC_BASE) |
| /** Array initializer of DDRC_REGS peripheral base addresses */ |
| #define DDRC_REGS_BASE_ADDRS { DDRC_BASE } |
| /** Array initializer of DDRC_REGS peripheral base pointers */ |
| #define DDRC_REGS_BASE_PTRS { DDRC } |
| |
| /*! |
| * @} |
| */ /* end of group DDRC_REGS_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- DEC400D Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup DEC400D_Peripheral_Access_Layer DEC400D Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** DEC400D - Register Layout Typedef */ |
| typedef struct { |
| uint8_t RESERVED_0[36]; |
| __I uint32_t GCCHIPREV; /**< Revision ID, offset: 0x24 */ |
| __I uint32_t GCCHIPDATE; /**< Release Date, offset: 0x28 */ |
| uint8_t RESERVED_1[108]; |
| __I uint32_t GCREGHICHIPPATCHREV; /**< Patch Revision, offset: 0x98 */ |
| uint8_t RESERVED_2[12]; |
| __I uint32_t GCPRODUCTID; /**< Product ID, offset: 0xA8 */ |
| uint8_t RESERVED_3[1876]; |
| __IO uint32_t GCREGAHBDECREADCONFIG[32]; /**< Decode Read Configuration, array offset: 0x800, array step: 0x4 */ |
| uint8_t RESERVED_4[128]; |
| __IO uint32_t GCREGAHBDECREADBUFFERBASE[32]; /**< Decode Read Buffer Base, array offset: 0x900, array step: 0x4 */ |
| __IO uint32_t GCREGAHBDECREADCACHEBASE[32]; /**< Decode Read Cache Base, array offset: 0x980, array step: 0x4 */ |
| uint8_t RESERVED_5[256]; |
| __IO uint32_t GCREGAHBDECCONTROL; /**< Dec400D Control, offset: 0xB00 */ |
| __I uint32_t GCREGAHBDECINTRACKNOWLEDGE; /**< Interrupt Acknowledge, offset: 0xB04 */ |
| __IO uint32_t GCREGAHBDECINTRENBL; /**< Interrupt Enable, offset: 0xB08 */ |
| __I uint32_t GCREGAHBDECTILESTATUSDEBUG; /**< Tile Status Module Debug, offset: 0xB0C */ |
| uint8_t RESERVED_6[4]; |
| __I uint32_t GCREGAHBDECDECODERDEBUG; /**< Decompression Module Debug, offset: 0xB14 */ |
| __I uint32_t GCREGAHBDECTOTALREADSIN; /**< Total Reads In, offset: 0xB18 */ |
| uint8_t RESERVED_7[4]; |
| __I uint32_t GCREGAHBDECTOTALREADBURSTSIN; /**< Total Read Data Count, offset: 0xB20 */ |
| uint8_t RESERVED_8[4]; |
| __I uint32_t GCREGAHBDECTOTALREADREQIN; /**< Total Read Request In, offset: 0xB28 */ |
| uint8_t RESERVED_9[4]; |
| __I uint32_t GCREGAHBDECTOTALREADLASTSIN; /**< Total Input Read Last Number, offset: 0xB30 */ |
| uint8_t RESERVED_10[4]; |
| __I uint32_t GCREGAHBDECTOTALREADSOUT; /**< Total Reads Out, offset: 0xB38 */ |
| uint8_t RESERVED_11[4]; |
| __I uint32_t GCREGAHBDECTOTALREADBURSTSOUT; /**< Total Read Bursts Out, offset: 0xB40 */ |
| uint8_t RESERVED_12[4]; |
| __I uint32_t GCREGAHBDECTOTALREADREQOUT; /**< Total Read Request Out, offset: 0xB48 */ |
| uint8_t RESERVED_13[4]; |
| __I uint32_t GCREGAHBDECTOTALREADLASTSOUT; /**< Total Read Last Out, offset: 0xB50 */ |
| uint8_t RESERVED_14[4]; |
| __I uint32_t GCREGAHBDECDEBUG0; /**< Debug Register 0, offset: 0xB58 */ |
| __I uint32_t GCREGAHBDECDEBUG1; /**< Debug Register 1, offset: 0xB5C */ |
| __I uint32_t GCREGAHBDECDEBUG2; /**< Debug register 2, offset: 0xB60 */ |
| __I uint32_t GCREGAHBDECDEBUG3; /**< Debug Register 3, offset: 0xB64 */ |
| __IO uint32_t GCREGAHBDECCONTROLEX; /**< GCREGAHBDECCONTROLEX, offset: 0xB68 */ |
| __IO uint32_t GCREGAHBDECSTATECOMMIT; /**< GCREGAHBDECSTATECOMMIT, offset: 0xB6C */ |
| __I uint32_t GCREGAHBDECSTATELOCK; /**< GCREGAHBDECSTATELOCK, offset: 0xB70 */ |
| uint8_t RESERVED_15[140]; |
| __IO uint32_t GCREGAHBDECREADEXCONFIG[32]; /**< Decode Read Extra Configuration, array offset: 0xC00, array step: 0x4 */ |
| __IO uint32_t GCREGAHBDECREADSTRIDE[32]; /**< Decoder Read Stride, array offset: 0xC80, array step: 0x4 */ |
| uint8_t RESERVED_16[256]; |
| __IO uint32_t GCREGAHBDECREADBUFFEREND[32]; /**< Decoder Read Buffer End, array offset: 0xE00, array step: 0x4 */ |
| } DEC400D_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- DEC400D Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup DEC400D_Register_Masks DEC400D Register Masks |
| * @{ |
| */ |
| |
| /*! @name GCCHIPREV - Revision ID */ |
| /*! @{ */ |
| #define DEC400D_GCCHIPREV_GCCHIPREV_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCCHIPREV_GCCHIPREV_SHIFT (0U) |
| #define DEC400D_GCCHIPREV_GCCHIPREV(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCCHIPREV_GCCHIPREV_SHIFT)) & DEC400D_GCCHIPREV_GCCHIPREV_MASK) |
| /*! @} */ |
| |
| /*! @name GCCHIPDATE - Release Date */ |
| /*! @{ */ |
| #define DEC400D_GCCHIPDATE_GCCHIPDATE_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCCHIPDATE_GCCHIPDATE_SHIFT (0U) |
| #define DEC400D_GCCHIPDATE_GCCHIPDATE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCCHIPDATE_GCCHIPDATE_SHIFT)) & DEC400D_GCCHIPDATE_GCCHIPDATE_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGHICHIPPATCHREV - Patch Revision */ |
| /*! @{ */ |
| #define DEC400D_GCREGHICHIPPATCHREV_GCREGHICHIPPATCHREV_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGHICHIPPATCHREV_GCREGHICHIPPATCHREV_SHIFT (0U) |
| #define DEC400D_GCREGHICHIPPATCHREV_GCREGHICHIPPATCHREV(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGHICHIPPATCHREV_GCREGHICHIPPATCHREV_SHIFT)) & DEC400D_GCREGHICHIPPATCHREV_GCREGHICHIPPATCHREV_MASK) |
| /*! @} */ |
| |
| /*! @name GCPRODUCTID - Product ID */ |
| /*! @{ */ |
| #define DEC400D_GCPRODUCTID_GCPRODUCTID_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCPRODUCTID_GCPRODUCTID_SHIFT (0U) |
| #define DEC400D_GCPRODUCTID_GCPRODUCTID(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCPRODUCTID_GCPRODUCTID_SHIFT)) & DEC400D_GCPRODUCTID_GCPRODUCTID_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGAHBDECREADCONFIG - Decode Read Configuration */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ENABLE_MASK (0x1U) |
| #define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ENABLE_SHIFT (0U) |
| /*! COMPRESSION_ENABLE - Compression Enable |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ENABLE_SHIFT)) & DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ENABLE_MASK) |
| #define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_FORMAT_MASK (0xF8U) |
| #define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_FORMAT_SHIFT (3U) |
| /*! COMPRESSION_FORMAT - Compression Format |
| * 0b00000..ARGB8 |
| */ |
| #define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_FORMAT_SHIFT)) & DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_FORMAT_MASK) |
| #define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ALIGN_MODE_MASK (0x30000U) |
| #define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ALIGN_MODE_SHIFT (16U) |
| /*! COMPRESSION_ALIGN_MODE - Compression Align Mode |
| * 0b00..ALIGN1_BYTE |
| * 0b01..ALIGN16_BYTE |
| * 0b10..ALIGN32_BYTE |
| * 0b11..ALIGN64_BYTE |
| */ |
| #define DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ALIGN_MODE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ALIGN_MODE_SHIFT)) & DEC400D_GCREGAHBDECREADCONFIG_COMPRESSION_ALIGN_MODE_MASK) |
| #define DEC400D_GCREGAHBDECREADCONFIG_TILE_ALIGN_MODE_MASK (0x1C00000U) |
| #define DEC400D_GCREGAHBDECREADCONFIG_TILE_ALIGN_MODE_SHIFT (22U) |
| /*! TILE_ALIGN_MODE - Tile Align Mode |
| * 0b000..TILE1_ALIGN |
| * 0b001..TILE2_ALIGN |
| * 0b010..TILE4_ALIGN |
| * 0b011..CBSR_ALIGN |
| */ |
| #define DEC400D_GCREGAHBDECREADCONFIG_TILE_ALIGN_MODE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADCONFIG_TILE_ALIGN_MODE_SHIFT)) & DEC400D_GCREGAHBDECREADCONFIG_TILE_ALIGN_MODE_MASK) |
| #define DEC400D_GCREGAHBDECREADCONFIG_TILE_MODE_MASK (0x3E000000U) |
| #define DEC400D_GCREGAHBDECREADCONFIG_TILE_MODE_SHIFT (25U) |
| /*! TILE_MODE - Tile Mode |
| * 0b00000..TILE8X8_XMAJOR |
| * 0b00001..TILE8X8_YMAJOR |
| * 0b00010..TILE16X4 |
| * 0b00011..TILE8X4 |
| * 0b00100..TILE4X8 |
| * 0b00101..TILE4X4 |
| * 0b00110..RASTER16X4 |
| * 0b00111..TILE64X4 |
| * 0b01000..TILE32X4 |
| * 0b01001..RASTER256X1 |
| * 0b01010..RASTER128X1 |
| * 0b01011..RASTER64X4 |
| * 0b01100..RASTER256X2 |
| * 0b01101..RASTER128X2 |
| * 0b01110..RASTER128X4 |
| * 0b01111..RASTER64X1 |
| */ |
| #define DEC400D_GCREGAHBDECREADCONFIG_TILE_MODE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADCONFIG_TILE_MODE_SHIFT)) & DEC400D_GCREGAHBDECREADCONFIG_TILE_MODE_MASK) |
| /*! @} */ |
| |
| /* The count of DEC400D_GCREGAHBDECREADCONFIG */ |
| #define DEC400D_GCREGAHBDECREADCONFIG_COUNT (32U) |
| |
| /*! @name GCREGAHBDECREADBUFFERBASE - Decode Read Buffer Base */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECREADBUFFERBASE_BUFFER_ADDRESS_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECREADBUFFERBASE_BUFFER_ADDRESS_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECREADBUFFERBASE_BUFFER_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADBUFFERBASE_BUFFER_ADDRESS_SHIFT)) & DEC400D_GCREGAHBDECREADBUFFERBASE_BUFFER_ADDRESS_MASK) |
| /*! @} */ |
| |
| /* The count of DEC400D_GCREGAHBDECREADBUFFERBASE */ |
| #define DEC400D_GCREGAHBDECREADBUFFERBASE_COUNT (32U) |
| |
| /*! @name GCREGAHBDECREADCACHEBASE - Decode Read Cache Base */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECREADCACHEBASE_CACHE_ADDRESS_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECREADCACHEBASE_CACHE_ADDRESS_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECREADCACHEBASE_CACHE_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADCACHEBASE_CACHE_ADDRESS_SHIFT)) & DEC400D_GCREGAHBDECREADCACHEBASE_CACHE_ADDRESS_MASK) |
| /*! @} */ |
| |
| /* The count of DEC400D_GCREGAHBDECREADCACHEBASE */ |
| #define DEC400D_GCREGAHBDECREADCACHEBASE_COUNT (32U) |
| |
| /*! @name GCREGAHBDECCONTROL - Dec400D Control */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECCONTROL_FLUSH_MASK (0x1U) |
| #define DEC400D_GCREGAHBDECCONTROL_FLUSH_SHIFT (0U) |
| /*! FLUSH - Flush tile status cache. |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define DEC400D_GCREGAHBDECCONTROL_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_FLUSH_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_FLUSH_MASK) |
| #define DEC400D_GCREGAHBDECCONTROL_DISABLE_COMPRESSION_MASK (0x2U) |
| #define DEC400D_GCREGAHBDECCONTROL_DISABLE_COMPRESSION_SHIFT (1U) |
| /*! DISABLE_COMPRESSION - Bypass compression for all streams. |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define DEC400D_GCREGAHBDECCONTROL_DISABLE_COMPRESSION(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_DISABLE_COMPRESSION_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_DISABLE_COMPRESSION_MASK) |
| #define DEC400D_GCREGAHBDECCONTROL_DISABLE_RAM_CLOCK_GATING_MASK (0x4U) |
| #define DEC400D_GCREGAHBDECCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT (2U) |
| /*! DISABLE_RAM_CLOCK_GATING - Disable clock gating for RAMs. |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define DEC400D_GCREGAHBDECCONTROL_DISABLE_RAM_CLOCK_GATING(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_DISABLE_RAM_CLOCK_GATING_MASK) |
| #define DEC400D_GCREGAHBDECCONTROL_DISABLE_DEBUG_REGISTERS_MASK (0x8U) |
| #define DEC400D_GCREGAHBDECCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT (3U) |
| /*! DISABLE_DEBUG_REGISTERS - Disable debug registers. |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define DEC400D_GCREGAHBDECCONTROL_DISABLE_DEBUG_REGISTERS(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_DISABLE_DEBUG_REGISTERS_MASK) |
| #define DEC400D_GCREGAHBDECCONTROL_SOFT_RESET_MASK (0x10U) |
| #define DEC400D_GCREGAHBDECCONTROL_SOFT_RESET_SHIFT (4U) |
| /*! SOFT_RESET - Soft reset the Dec400D. |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define DEC400D_GCREGAHBDECCONTROL_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_SOFT_RESET_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_SOFT_RESET_MASK) |
| #define DEC400D_GCREGAHBDECCONTROL_TILE_STATUS_READ_ID_MASK (0x7C0U) |
| #define DEC400D_GCREGAHBDECCONTROL_TILE_STATUS_READ_ID_SHIFT (6U) |
| #define DEC400D_GCREGAHBDECCONTROL_TILE_STATUS_READ_ID(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_TILE_STATUS_READ_ID_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_TILE_STATUS_READ_ID_MASK) |
| #define DEC400D_GCREGAHBDECCONTROL_DISABLE_HW_FLUSH_MASK (0x10000U) |
| #define DEC400D_GCREGAHBDECCONTROL_DISABLE_HW_FLUSH_SHIFT (16U) |
| /*! DISABLE_HW_FLUSH - Tile status cache flush through frame end pin is disabled. |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define DEC400D_GCREGAHBDECCONTROL_DISABLE_HW_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_DISABLE_HW_FLUSH_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_DISABLE_HW_FLUSH_MASK) |
| #define DEC400D_GCREGAHBDECCONTROL_CLK_DIS_MASK (0x20000U) |
| #define DEC400D_GCREGAHBDECCONTROL_CLK_DIS_SHIFT (17U) |
| /*! CLK_DIS - Disable clock. |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define DEC400D_GCREGAHBDECCONTROL_CLK_DIS(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_CLK_DIS_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_CLK_DIS_MASK) |
| #define DEC400D_GCREGAHBDECCONTROL_SW_FLUSH_ID_MASK (0xFC0000U) |
| #define DEC400D_GCREGAHBDECCONTROL_SW_FLUSH_ID_SHIFT (18U) |
| #define DEC400D_GCREGAHBDECCONTROL_SW_FLUSH_ID(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_SW_FLUSH_ID_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_SW_FLUSH_ID_MASK) |
| #define DEC400D_GCREGAHBDECCONTROL_DISABLE_MODULE_CLOCK_GATING_MASK (0x40000000U) |
| #define DEC400D_GCREGAHBDECCONTROL_DISABLE_MODULE_CLOCK_GATING_SHIFT (30U) |
| /*! DISABLE_MODULE_CLOCK_GATING - Disable clock gating for sub modules |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define DEC400D_GCREGAHBDECCONTROL_DISABLE_MODULE_CLOCK_GATING(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROL_DISABLE_MODULE_CLOCK_GATING_SHIFT)) & DEC400D_GCREGAHBDECCONTROL_DISABLE_MODULE_CLOCK_GATING_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGAHBDECINTRACKNOWLEDGE - Interrupt Acknowledge */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECINTRACKNOWLEDGE_INTR_VEC_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECINTRACKNOWLEDGE_INTR_VEC_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECINTRACKNOWLEDGE_INTR_VEC(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECINTRACKNOWLEDGE_INTR_VEC_SHIFT)) & DEC400D_GCREGAHBDECINTRACKNOWLEDGE_INTR_VEC_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGAHBDECINTRENBL - Interrupt Enable */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECINTRENBL_INTR_ENBL_VEC_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECINTRENBL_INTR_ENBL_VEC_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECINTRENBL_INTR_ENBL_VEC(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECINTRENBL_INTR_ENBL_VEC_SHIFT)) & DEC400D_GCREGAHBDECINTRENBL_INTR_ENBL_VEC_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGAHBDECTILESTATUSDEBUG - Tile Status Module Debug */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECTILESTATUSDEBUG_TILE_DEBUG_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECTILESTATUSDEBUG_TILE_DEBUG_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECTILESTATUSDEBUG_TILE_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTILESTATUSDEBUG_TILE_DEBUG_SHIFT)) & DEC400D_GCREGAHBDECTILESTATUSDEBUG_TILE_DEBUG_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGAHBDECDECODERDEBUG - Decompression Module Debug */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECDECODERDEBUG_DEC_DEBUG_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECDECODERDEBUG_DEC_DEBUG_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECDECODERDEBUG_DEC_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECDECODERDEBUG_DEC_DEBUG_SHIFT)) & DEC400D_GCREGAHBDECDECODERDEBUG_DEC_DEBUG_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGAHBDECTOTALREADSIN - Total Reads In */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECTOTALREADSIN_RDIN_COUNT_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECTOTALREADSIN_RDIN_COUNT_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECTOTALREADSIN_RDIN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADSIN_RDIN_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADSIN_RDIN_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGAHBDECTOTALREADBURSTSIN - Total Read Data Count */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECTOTALREADBURSTSIN_RDIN_BURST_COUNT_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECTOTALREADBURSTSIN_RDIN_BURST_COUNT_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECTOTALREADBURSTSIN_RDIN_BURST_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADBURSTSIN_RDIN_BURST_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADBURSTSIN_RDIN_BURST_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGAHBDECTOTALREADREQIN - Total Read Request In */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECTOTALREADREQIN_RDIN_REQ_COUNT_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECTOTALREADREQIN_RDIN_REQ_COUNT_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECTOTALREADREQIN_RDIN_REQ_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADREQIN_RDIN_REQ_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADREQIN_RDIN_REQ_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGAHBDECTOTALREADLASTSIN - Total Input Read Last Number */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECTOTALREADLASTSIN_RDIN_LAST_COUNT_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECTOTALREADLASTSIN_RDIN_LAST_COUNT_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECTOTALREADLASTSIN_RDIN_LAST_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADLASTSIN_RDIN_LAST_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADLASTSIN_RDIN_LAST_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGAHBDECTOTALREADSOUT - Total Reads Out */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECTOTALREADSOUT_RDOUT_COUNT_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECTOTALREADSOUT_RDOUT_COUNT_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECTOTALREADSOUT_RDOUT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADSOUT_RDOUT_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADSOUT_RDOUT_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGAHBDECTOTALREADBURSTSOUT - Total Read Bursts Out */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECTOTALREADBURSTSOUT_RDOUT_BURST_COUNT_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECTOTALREADBURSTSOUT_RDOUT_BURST_COUNT_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECTOTALREADBURSTSOUT_RDOUT_BURST_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADBURSTSOUT_RDOUT_BURST_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADBURSTSOUT_RDOUT_BURST_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGAHBDECTOTALREADREQOUT - Total Read Request Out */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECTOTALREADREQOUT_RDOUT_REQ_COUNT_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECTOTALREADREQOUT_RDOUT_REQ_COUNT_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECTOTALREADREQOUT_RDOUT_REQ_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADREQOUT_RDOUT_REQ_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADREQOUT_RDOUT_REQ_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGAHBDECTOTALREADLASTSOUT - Total Read Last Out */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECTOTALREADLASTSOUT_RDOUT_LAST_COUNT_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECTOTALREADLASTSOUT_RDOUT_LAST_COUNT_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECTOTALREADLASTSOUT_RDOUT_LAST_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECTOTALREADLASTSOUT_RDOUT_LAST_COUNT_SHIFT)) & DEC400D_GCREGAHBDECTOTALREADLASTSOUT_RDOUT_LAST_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGAHBDECDEBUG0 - Debug Register 0 */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECDEBUG0_DEBUG0_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECDEBUG0_DEBUG0_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECDEBUG0_DEBUG0(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECDEBUG0_DEBUG0_SHIFT)) & DEC400D_GCREGAHBDECDEBUG0_DEBUG0_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGAHBDECDEBUG1 - Debug Register 1 */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECDEBUG1_DEBUG1_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECDEBUG1_DEBUG1_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECDEBUG1_DEBUG1(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECDEBUG1_DEBUG1_SHIFT)) & DEC400D_GCREGAHBDECDEBUG1_DEBUG1_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGAHBDECDEBUG2 - Debug register 2 */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECDEBUG2_DEBUG2_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECDEBUG2_DEBUG2_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECDEBUG2_DEBUG2(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECDEBUG2_DEBUG2_SHIFT)) & DEC400D_GCREGAHBDECDEBUG2_DEBUG2_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGAHBDECDEBUG3 - Debug Register 3 */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECDEBUG3_DEBUG3_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECDEBUG3_DEBUG3_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECDEBUG3_DEBUG3(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECDEBUG3_DEBUG3_SHIFT)) & DEC400D_GCREGAHBDECDEBUG3_DEBUG3_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGAHBDECCONTROLEX - GCREGAHBDECCONTROLEX */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECCONTROLEX_GCREGAHBDECCONTROLEX_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECCONTROLEX_GCREGAHBDECCONTROLEX_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECCONTROLEX_GCREGAHBDECCONTROLEX(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECCONTROLEX_GCREGAHBDECCONTROLEX_SHIFT)) & DEC400D_GCREGAHBDECCONTROLEX_GCREGAHBDECCONTROLEX_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGAHBDECSTATECOMMIT - GCREGAHBDECSTATECOMMIT */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECSTATECOMMIT_GCREGAHBDECSTATECOMMIT_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECSTATECOMMIT_GCREGAHBDECSTATECOMMIT_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECSTATECOMMIT_GCREGAHBDECSTATECOMMIT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECSTATECOMMIT_GCREGAHBDECSTATECOMMIT_SHIFT)) & DEC400D_GCREGAHBDECSTATECOMMIT_GCREGAHBDECSTATECOMMIT_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGAHBDECSTATELOCK - GCREGAHBDECSTATELOCK */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECSTATELOCK_GCREGAHBDECSTATELOCK_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECSTATELOCK_GCREGAHBDECSTATELOCK_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECSTATELOCK_GCREGAHBDECSTATELOCK(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECSTATELOCK_GCREGAHBDECSTATELOCK_SHIFT)) & DEC400D_GCREGAHBDECSTATELOCK_GCREGAHBDECSTATELOCK_MASK) |
| /*! @} */ |
| |
| /*! @name GCREGAHBDECREADEXCONFIG - Decode Read Extra Configuration */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_CBSR_WIDTH_MASK (0xFFF8U) |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_CBSR_WIDTH_SHIFT (3U) |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_CBSR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_CBSR_WIDTH_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_CBSR_WIDTH_MASK) |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_BIT_DEPTH_MASK (0x70000U) |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_BIT_DEPTH_SHIFT (16U) |
| /*! BIT_DEPTH - Bit depth |
| * 0b000..8 bit |
| * 0b001..10 bit |
| * 0b010..12 bit |
| * 0b011..16 bit |
| */ |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_BIT_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_BIT_DEPTH_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_BIT_DEPTH_MASK) |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_TILE_Y_MASK (0x80000U) |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_TILE_Y_SHIFT (19U) |
| /*! TILE_Y - Tile Y |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_TILE_Y(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_TILE_Y_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_TILE_Y_MASK) |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_STREAM_MODE_MASK (0x1F00000U) |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_STREAM_MODE_SHIFT (20U) |
| /*! STREAM_MODE - Stream mode |
| * 0b00000..Default |
| * 0b00001..ISA_STREAM0 |
| * 0b00010..ISA_STREAM1 |
| * 0b00011..ISA_STREAM2 |
| * 0b00100..ISA_STREAM3 |
| * 0b00101..TNR_STREAM_Y |
| * 0b00110..TNR_STREAM_UV |
| * 0b00111..GDC_STREAM_Y |
| * 0b01000..GDC_STREAM_U |
| * 0b01001..GDC_STREAM_V |
| * 0b01010..VPU_SRC_Y |
| * 0b01011..VPR_SRC_UV |
| * 0b01100..VPU_REF_Y |
| * 0b01101..VPU_REF_UV |
| * 0b01110..XYZ_STREAM_AY |
| * 0b01111..XYZ_STREAM_AU |
| * 0b10000..XYZ_STREAM_AV |
| * 0b10001..XYZ_STREAM_BY |
| * 0b10010..XYZ_STREAM_BU |
| * 0b10011..XYZ_STREAM_BV |
| */ |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_STREAM_MODE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_STREAM_MODE_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_STREAM_MODE_MASK) |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_READ_MODE_MASK (0x4000000U) |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_READ_MODE_SHIFT (26U) |
| /*! TS_CACHE_READ_MODE - TS cache read mode |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_READ_MODE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_READ_MODE_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_READ_MODE_MASK) |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_PIXEL_CACHE_REPLACEMENT_MASK (0x8000000U) |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_PIXEL_CACHE_REPLACEMENT_SHIFT (27U) |
| /*! PIXEL_CACHE_REPLACEMENT - Pixel cache replacement |
| * 0b0..LRU |
| * 0b1..FIFO |
| */ |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_PIXEL_CACHE_REPLACEMENT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_PIXEL_CACHE_REPLACEMENT_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_PIXEL_CACHE_REPLACEMENT_MASK) |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_INTEL_P010_MASK (0x10000000U) |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_INTEL_P010_SHIFT (28U) |
| /*! INTEL_P010 - Intel's P010 format |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_INTEL_P010(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_INTEL_P010_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_INTEL_P010_MASK) |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_REPLACEMENT_MASK (0x20000000U) |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_REPLACEMENT_SHIFT (29U) |
| /*! TS_CACHE_REPLACEMENT - TS cache replacement |
| * 0b0..LRU |
| * 0b1..FIFO |
| */ |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_REPLACEMENT(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_REPLACEMENT_SHIFT)) & DEC400D_GCREGAHBDECREADEXCONFIG_TS_CACHE_REPLACEMENT_MASK) |
| /*! @} */ |
| |
| /* The count of DEC400D_GCREGAHBDECREADEXCONFIG */ |
| #define DEC400D_GCREGAHBDECREADEXCONFIG_COUNT (32U) |
| |
| /*! @name GCREGAHBDECREADSTRIDE - Decoder Read Stride */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECREADSTRIDE_STRIDE_MASK (0x3FFFFU) |
| #define DEC400D_GCREGAHBDECREADSTRIDE_STRIDE_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECREADSTRIDE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADSTRIDE_STRIDE_SHIFT)) & DEC400D_GCREGAHBDECREADSTRIDE_STRIDE_MASK) |
| /*! @} */ |
| |
| /* The count of DEC400D_GCREGAHBDECREADSTRIDE */ |
| #define DEC400D_GCREGAHBDECREADSTRIDE_COUNT (32U) |
| |
| /*! @name GCREGAHBDECREADBUFFEREND - Decoder Read Buffer End */ |
| /*! @{ */ |
| #define DEC400D_GCREGAHBDECREADBUFFEREND_RD_BUFF_END_MASK (0xFFFFFFFFU) |
| #define DEC400D_GCREGAHBDECREADBUFFEREND_RD_BUFF_END_SHIFT (0U) |
| #define DEC400D_GCREGAHBDECREADBUFFEREND_RD_BUFF_END(x) (((uint32_t)(((uint32_t)(x)) << DEC400D_GCREGAHBDECREADBUFFEREND_RD_BUFF_END_SHIFT)) & DEC400D_GCREGAHBDECREADBUFFEREND_RD_BUFF_END_MASK) |
| /*! @} */ |
| |
| /* The count of DEC400D_GCREGAHBDECREADBUFFEREND */ |
| #define DEC400D_GCREGAHBDECREADBUFFEREND_COUNT (32U) |
| |
| |
| /*! |
| * @} |
| */ /* end of group DEC400D_Register_Masks */ |
| |
| |
| /* DEC400D - Peripheral instance base addresses */ |
| /** Peripheral DCSS__DEC400D base address */ |
| #define DCSS__DEC400D_BASE (0x32E15000u) |
| /** Peripheral DCSS__DEC400D base pointer */ |
| #define DCSS__DEC400D ((DEC400D_Type *)DCSS__DEC400D_BASE) |
| /** Array initializer of DEC400D peripheral base addresses */ |
| #define DEC400D_BASE_ADDRS { DCSS__DEC400D_BASE } |
| /** Array initializer of DEC400D peripheral base pointers */ |
| #define DEC400D_BASE_PTRS { DCSS__DEC400D } |
| |
| /*! |
| * @} |
| */ /* end of group DEC400D_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- DPR Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup DPR_Peripheral_Access_Layer DPR Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** DPR - Register Layout Typedef */ |
| typedef struct { |
| struct { /* offset: 0x0 */ |
| __IO uint32_t RW; /**< System Control 0, offset: 0x0 */ |
| __IO uint32_t SET; /**< System Control 0, offset: 0x4 */ |
| __IO uint32_t CLR; /**< System Control 0, offset: 0x8 */ |
| __IO uint32_t TOG; /**< System Control 0, offset: 0xC */ |
| } SYSTEM_CTRL0; |
| uint8_t RESERVED_0[16]; |
| struct { /* offset: 0x20 */ |
| __IO uint32_t RW; /**< Interrupt Mask, offset: 0x20 */ |
| __IO uint32_t SET; /**< Interrupt Mask, offset: 0x24 */ |
| __IO uint32_t CLR; /**< Interrupt Mask, offset: 0x28 */ |
| __IO uint32_t TOG; /**< Interrupt Mask, offset: 0x2C */ |
| } IRQ_MASK; |
| struct { /* offset: 0x30 */ |
| __I uint32_t RW; /**< Status Register of Masked IRQ, offset: 0x30 */ |
| __I uint32_t SET; /**< Status Register of Masked IRQ, offset: 0x34 */ |
| __I uint32_t CLR; /**< Status Register of Masked IRQ, offset: 0x38 */ |
| __I uint32_t TOG; /**< Status Register of Masked IRQ, offset: 0x3C */ |
| } IRQ_MASK_STATUS; |
| struct { /* offset: 0x40 */ |
| __IO uint32_t RW; /**< Status of Non-Masked IRQ, offset: 0x40 */ |
| __IO uint32_t SET; /**< Status of Non-Masked IRQ, offset: 0x44 */ |
| __IO uint32_t CLR; /**< Status of Non-Masked IRQ, offset: 0x48 */ |
| __IO uint32_t TOG; /**< Status of Non-Masked IRQ, offset: 0x4C */ |
| } IRQ_NONMASK_STATUS; |
| struct { /* offset: 0x50 */ |
| __IO uint32_t RW; /**< Mode Control 0, offset: 0x50 */ |
| __IO uint32_t SET; /**< Mode Control 0, offset: 0x54 */ |
| __IO uint32_t CLR; /**< Mode Control 0, offset: 0x58 */ |
| __IO uint32_t TOG; /**< Mode Control 0, offset: 0x5C */ |
| } MODE_CTRL0; |
| uint8_t RESERVED_1[16]; |
| struct { /* offset: 0x70 */ |
| __IO uint32_t RW; /**< Frame Control 0, offset: 0x70 */ |
| __IO uint32_t SET; /**< Frame Control 0, offset: 0x74 */ |
| __IO uint32_t CLR; /**< Frame Control 0, offset: 0x78 */ |
| __IO uint32_t TOG; /**< Frame Control 0, offset: 0x7C */ |
| } FRAME_CTRL0; |
| uint8_t RESERVED_2[16]; |
| struct { /* offset: 0x90 */ |
| __IO uint32_t RW; /**< Frame 1-Plane Control 0, offset: 0x90 */ |
| __IO uint32_t SET; /**< Frame 1-Plane Control 0, offset: 0x94 */ |
| __IO uint32_t CLR; /**< Frame 1-Plane Control 0, offset: 0x98 */ |
| __IO uint32_t TOG; /**< Frame 1-Plane Control 0, offset: 0x9C */ |
| } FRAME_1P_CTRL0; |
| struct { /* offset: 0xA0 */ |
| __IO uint32_t RW; /**< Frame 1-Plane Pix X Control, offset: 0xA0 */ |
| __IO uint32_t SET; /**< Frame 1-Plane Pix X Control, offset: 0xA4 */ |
| __IO uint32_t CLR; /**< Frame 1-Plane Pix X Control, offset: 0xA8 */ |
| __IO uint32_t TOG; /**< Frame 1-Plane Pix X Control, offset: 0xAC */ |
| } FRAME_1P_PIX_X_CTRL; |
| struct { /* offset: 0xB0 */ |
| __IO uint32_t RW; /**< Frame 1-Plane Pix Y Control, offset: 0xB0 */ |
| __IO uint32_t SET; /**< Frame 1-Plane Pix Y Control, offset: 0xB4 */ |
| __IO uint32_t CLR; /**< Frame 1-Plane Pix Y Control, offset: 0xB8 */ |
| __IO uint32_t TOG; /**< Frame 1-Plane Pix Y Control, offset: 0xBC */ |
| } FRAME_1P_PIX_Y_CTRL; |
| struct { /* offset: 0xC0 */ |
| __IO uint32_t RW; /**< Frame 1-Plane Base Address Control 0, offset: 0xC0 */ |
| __IO uint32_t SET; /**< Frame 1-Plane Base Address Control 0, offset: 0xC4 */ |
| __IO uint32_t CLR; /**< Frame 1-Plane Base Address Control 0, offset: 0xC8 */ |
| __IO uint32_t TOG; /**< Frame 1-Plane Base Address Control 0, offset: 0xCC */ |
| } FRAME_1P_BASE_ADDR_CTRL0; |
| uint8_t RESERVED_3[16]; |
| struct { /* offset: 0xE0 */ |
| __IO uint32_t RW; /**< Frame 2-Plane Control 0, offset: 0xE0 */ |
| __IO uint32_t SET; /**< Frame 2-Plane Control 0, offset: 0xE4 */ |
| __IO uint32_t CLR; /**< Frame 2-Plane Control 0, offset: 0xE8 */ |
| __IO uint32_t TOG; /**< Frame 2-Plane Control 0, offset: 0xEC */ |
| } FRAME_2P_CTRL0; |
| struct { /* offset: 0xF0 */ |
| __IO uint32_t RW; /**< Frame 2-Plane Pix X Control, offset: 0xF0 */ |
| __IO uint32_t SET; /**< Frame 2-Plane Pix X Control, offset: 0xF4 */ |
| __IO uint32_t CLR; /**< Frame 2-Plane Pix X Control, offset: 0xF8 */ |
| __IO uint32_t TOG; /**< Frame 2-Plane Pix X Control, offset: 0xFC */ |
| } FRAME_2P_PIX_X_CTRL; |
| struct { /* offset: 0x100 */ |
| __IO uint32_t RW; /**< Frame 2-Plane Pix Y Control, offset: 0x100 */ |
| __IO uint32_t SET; /**< Frame 2-Plane Pix Y Control, offset: 0x104 */ |
| __IO uint32_t CLR; /**< Frame 2-Plane Pix Y Control, offset: 0x108 */ |
| __IO uint32_t TOG; /**< Frame 2-Plane Pix Y Control, offset: 0x10C */ |
| } FRAME_2P_PIX_Y_CTRL; |
| struct { /* offset: 0x110 */ |
| __IO uint32_t RW; /**< Frame 2-Plane Base Address Control 0, offset: 0x110 */ |
| __IO uint32_t SET; /**< Frame 2-Plane Base Address Control 0, offset: 0x114 */ |
| __IO uint32_t CLR; /**< Frame 2-Plane Base Address Control 0, offset: 0x118 */ |
| __IO uint32_t TOG; /**< Frame 2-Plane Base Address Control 0, offset: 0x11C */ |
| } FRAME_2P_BASE_ADDR_CTRL0; |
| uint8_t RESERVED_4[224]; |
| struct { /* offset: 0x200 */ |
| __IO uint32_t RW; /**< RTRAM Control 0, offset: 0x200 */ |
| __IO uint32_t SET; /**< RTRAM Control 0, offset: 0x204 */ |
| __IO uint32_t CLR; /**< RTRAM Control 0, offset: 0x208 */ |
| __IO uint32_t TOG; /**< RTRAM Control 0, offset: 0x20C */ |
| } RTRAM_CTRL0; |
| } DPR_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- DPR Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup DPR_Register_Masks DPR Register Masks |
| * @{ |
| */ |
| |
| /*! @name SYSTEM_CTRL0 - System Control 0 */ |
| /*! @{ */ |
| #define DPR_SYSTEM_CTRL0_RUN_EN_MASK (0x1U) |
| #define DPR_SYSTEM_CTRL0_RUN_EN_SHIFT (0U) |
| #define DPR_SYSTEM_CTRL0_RUN_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_RUN_EN_SHIFT)) & DPR_SYSTEM_CTRL0_RUN_EN_MASK) |
| #define DPR_SYSTEM_CTRL0_SOFT_RESET_MASK (0x2U) |
| #define DPR_SYSTEM_CTRL0_SOFT_RESET_SHIFT (1U) |
| #define DPR_SYSTEM_CTRL0_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_SOFT_RESET_SHIFT)) & DPR_SYSTEM_CTRL0_SOFT_RESET_MASK) |
| #define DPR_SYSTEM_CTRL0_REPEAT_EN_MASK (0x4U) |
| #define DPR_SYSTEM_CTRL0_REPEAT_EN_SHIFT (2U) |
| #define DPR_SYSTEM_CTRL0_REPEAT_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_REPEAT_EN_SHIFT)) & DPR_SYSTEM_CTRL0_REPEAT_EN_MASK) |
| #define DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_MASK (0x8U) |
| #define DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_SHIFT (3U) |
| #define DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_SHIFT)) & DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_MASK) |
| #define DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_MASK (0x10U) |
| #define DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_SHIFT (4U) |
| #define DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_SHIFT)) & DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_MASK) |
| #define DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_MASK (0x10000U) |
| #define DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_SHIFT (16U) |
| #define DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_SHIFT)) & DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_MASK) |
| /*! @} */ |
| |
| /*! @name IRQ_MASK - Interrupt Mask */ |
| /*! @{ */ |
| #define DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_MASK (0x1U) |
| #define DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_SHIFT (0U) |
| #define DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_SHIFT)) & DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_MASK) |
| #define DPR_IRQ_MASK_IRQ_DPR_RUN_MASK (0x2U) |
| #define DPR_IRQ_MASK_IRQ_DPR_RUN_SHIFT (1U) |
| #define DPR_IRQ_MASK_IRQ_DPR_RUN(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_DPR_RUN_SHIFT)) & DPR_IRQ_MASK_IRQ_DPR_RUN_MASK) |
| #define DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_MASK (0x4U) |
| #define DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_SHIFT (2U) |
| #define DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_SHIFT)) & DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_MASK) |
| #define DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_MASK (0x8U) |
| #define DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_SHIFT (3U) |
| #define DPR_IRQ_MASK_IRQ_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_SHIFT)) & DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_MASK) |
| #define DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_MASK (0x10U) |
| #define DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_SHIFT (4U) |
| #define DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_MASK) |
| #define DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_MASK (0x20U) |
| #define DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_SHIFT (5U) |
| #define DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_MASK) |
| #define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK (0x40U) |
| #define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT (6U) |
| #define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK) |
| #define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK (0x80U) |
| #define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT (7U) |
| #define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK) |
| /*! @} */ |
| |
| /*! @name IRQ_MASK_STATUS - Status Register of Masked IRQ */ |
| /*! @{ */ |
| #define DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_MASK (0x1U) |
| #define DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT (0U) |
| #define DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_MASK) |
| #define DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_MASK (0x2U) |
| #define DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_SHIFT (1U) |
| #define DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_MASK) |
| #define DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_MASK (0x4U) |
| #define DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_SHIFT (2U) |
| #define DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_MASK) |
| #define DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_MASK (0x8U) |
| #define DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT (3U) |
| #define DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_MASK) |
| #define DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK (0x10U) |
| #define DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT (4U) |
| #define DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK) |
| #define DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK (0x20U) |
| #define DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT (5U) |
| #define DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK) |
| #define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK (0x40U) |
| #define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT (6U) |
| #define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK) |
| #define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK (0x80U) |
| #define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT (7U) |
| #define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK) |
| /*! @} */ |
| |
| /*! @name IRQ_NONMASK_STATUS - Status of Non-Masked IRQ */ |
| /*! @{ */ |
| #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_MASK (0x1U) |
| #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT (0U) |
| #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_MASK) |
| #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_MASK (0x2U) |
| #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_SHIFT (1U) |
| #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_MASK) |
| #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_MASK (0x4U) |
| #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_SHIFT (2U) |
| #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_MASK) |
| #define DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_MASK (0x8U) |
| #define DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT (3U) |
| #define DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_MASK) |
| #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK (0x10U) |
| #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT (4U) |
| #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK) |
| #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK (0x20U) |
| #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT (5U) |
| #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK) |
| #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK (0x40U) |
| #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT (6U) |
| #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK) |
| #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK (0x80U) |
| #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT (7U) |
| #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK) |
| /*! @} */ |
| |
| /*! @name MODE_CTRL0 - Mode Control 0 */ |
| /*! @{ */ |
| #define DPR_MODE_CTRL0_RTR_3BUF_EN_MASK (0x1U) |
| #define DPR_MODE_CTRL0_RTR_3BUF_EN_SHIFT (0U) |
| #define DPR_MODE_CTRL0_RTR_3BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_RTR_3BUF_EN_SHIFT)) & DPR_MODE_CTRL0_RTR_3BUF_EN_MASK) |
| #define DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_MASK (0x2U) |
| #define DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_SHIFT (1U) |
| #define DPR_MODE_CTRL0_RTR_4LINE_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_SHIFT)) & DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_MASK) |
| #define DPR_MODE_CTRL0_TILE_TYPE_MASK (0x1CU) |
| #define DPR_MODE_CTRL0_TILE_TYPE_SHIFT (2U) |
| #define DPR_MODE_CTRL0_TILE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_TILE_TYPE_SHIFT)) & DPR_MODE_CTRL0_TILE_TYPE_MASK) |
| #define DPR_MODE_CTRL0_YUV_EN_MASK (0x40U) |
| #define DPR_MODE_CTRL0_YUV_EN_SHIFT (6U) |
| #define DPR_MODE_CTRL0_YUV_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_YUV_EN_SHIFT)) & DPR_MODE_CTRL0_YUV_EN_MASK) |
| #define DPR_MODE_CTRL0_COMP_2PLANE_EN_MASK (0x80U) |
| #define DPR_MODE_CTRL0_COMP_2PLANE_EN_SHIFT (7U) |
| #define DPR_MODE_CTRL0_COMP_2PLANE_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_COMP_2PLANE_EN_SHIFT)) & DPR_MODE_CTRL0_COMP_2PLANE_EN_MASK) |
| #define DPR_MODE_CTRL0_PIX_SIZE_MASK (0x300U) |
| #define DPR_MODE_CTRL0_PIX_SIZE_SHIFT (8U) |
| #define DPR_MODE_CTRL0_PIX_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_PIX_SIZE_SHIFT)) & DPR_MODE_CTRL0_PIX_SIZE_MASK) |
| #define DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_MASK (0x400U) |
| #define DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_SHIFT (10U) |
| #define DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_SHIFT)) & DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_MASK) |
| #define DPR_MODE_CTRL0_PIX_UV_SWAP_MASK (0x800U) |
| #define DPR_MODE_CTRL0_PIX_UV_SWAP_SHIFT (11U) |
| #define DPR_MODE_CTRL0_PIX_UV_SWAP(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_PIX_UV_SWAP_SHIFT)) & DPR_MODE_CTRL0_PIX_UV_SWAP_MASK) |
| #define DPR_MODE_CTRL0_B_COMP_SEL_MASK (0x3000U) |
| #define DPR_MODE_CTRL0_B_COMP_SEL_SHIFT (12U) |
| #define DPR_MODE_CTRL0_B_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_B_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_B_COMP_SEL_MASK) |
| #define DPR_MODE_CTRL0_G_COMP_SEL_MASK (0xC000U) |
| #define DPR_MODE_CTRL0_G_COMP_SEL_SHIFT (14U) |
| #define DPR_MODE_CTRL0_G_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_G_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_G_COMP_SEL_MASK) |
| #define DPR_MODE_CTRL0_R_COMP_SEL_MASK (0x30000U) |
| #define DPR_MODE_CTRL0_R_COMP_SEL_SHIFT (16U) |
| #define DPR_MODE_CTRL0_R_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_R_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_R_COMP_SEL_MASK) |
| #define DPR_MODE_CTRL0_A_COMP_SEL_MASK (0xC0000U) |
| #define DPR_MODE_CTRL0_A_COMP_SEL_SHIFT (18U) |
| #define DPR_MODE_CTRL0_A_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_A_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_A_COMP_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name FRAME_CTRL0 - Frame Control 0 */ |
| /*! @{ */ |
| #define DPR_FRAME_CTRL0_HFLIP_EN_MASK (0x1U) |
| #define DPR_FRAME_CTRL0_HFLIP_EN_SHIFT (0U) |
| #define DPR_FRAME_CTRL0_HFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_HFLIP_EN_SHIFT)) & DPR_FRAME_CTRL0_HFLIP_EN_MASK) |
| #define DPR_FRAME_CTRL0_VFLIP_EN_MASK (0x2U) |
| #define DPR_FRAME_CTRL0_VFLIP_EN_SHIFT (1U) |
| #define DPR_FRAME_CTRL0_VFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_VFLIP_EN_SHIFT)) & DPR_FRAME_CTRL0_VFLIP_EN_MASK) |
| #define DPR_FRAME_CTRL0_ROT_ENC_MASK (0xCU) |
| #define DPR_FRAME_CTRL0_ROT_ENC_SHIFT (2U) |
| #define DPR_FRAME_CTRL0_ROT_ENC(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_ROT_ENC_SHIFT)) & DPR_FRAME_CTRL0_ROT_ENC_MASK) |
| #define DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_MASK (0x10U) |
| #define DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_SHIFT (4U) |
| #define DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_SHIFT)) & DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_MASK) |
| #define DPR_FRAME_CTRL0_PITCH_MASK (0xFFFF0000U) |
| #define DPR_FRAME_CTRL0_PITCH_SHIFT (16U) |
| #define DPR_FRAME_CTRL0_PITCH(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_PITCH_SHIFT)) & DPR_FRAME_CTRL0_PITCH_MASK) |
| /*! @} */ |
| |
| /*! @name FRAME_1P_CTRL0 - Frame 1-Plane Control 0 */ |
| /*! @{ */ |
| #define DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_MASK (0x7U) |
| #define DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_SHIFT (0U) |
| #define DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_SHIFT)) & DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_MASK) |
| /*! @} */ |
| |
| /*! @name FRAME_1P_PIX_X_CTRL - Frame 1-Plane Pix X Control */ |
| /*! @{ */ |
| #define DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_MASK (0xFFFFU) |
| #define DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_SHIFT (0U) |
| #define DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_SHIFT)) & DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_MASK) |
| #define DPR_FRAME_1P_PIX_X_CTRL_CROP_ULC_X_MASK (0xFFFF0000U) |
| #define DPR_FRAME_1P_PIX_X_CTRL_CROP_ULC_X_SHIFT (16U) |
| #define DPR_FRAME_1P_PIX_X_CTRL_CROP_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_PIX_X_CTRL_CROP_ULC_X_SHIFT)) & DPR_FRAME_1P_PIX_X_CTRL_CROP_ULC_X_MASK) |
| /*! @} */ |
| |
| /*! @name FRAME_1P_PIX_Y_CTRL - Frame 1-Plane Pix Y Control */ |
| /*! @{ */ |
| #define DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_MASK (0xFFFFU) |
| #define DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_SHIFT (0U) |
| #define DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_SHIFT)) & DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_MASK) |
| #define DPR_FRAME_1P_PIX_Y_CTRL_CROP_ULC_Y_MASK (0xFFFF0000U) |
| #define DPR_FRAME_1P_PIX_Y_CTRL_CROP_ULC_Y_SHIFT (16U) |
| #define DPR_FRAME_1P_PIX_Y_CTRL_CROP_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_PIX_Y_CTRL_CROP_ULC_Y_SHIFT)) & DPR_FRAME_1P_PIX_Y_CTRL_CROP_ULC_Y_MASK) |
| /*! @} */ |
| |
| /*! @name FRAME_1P_BASE_ADDR_CTRL0 - Frame 1-Plane Base Address Control 0 */ |
| /*! @{ */ |
| #define DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_MASK (0xFFFFFFFFU) |
| #define DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT (0U) |
| #define DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT)) & DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name FRAME_2P_CTRL0 - Frame 2-Plane Control 0 */ |
| /*! @{ */ |
| #define DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_MASK (0x7U) |
| #define DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_SHIFT (0U) |
| #define DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_SHIFT)) & DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_MASK) |
| /*! @} */ |
| |
| /*! @name FRAME_2P_PIX_X_CTRL - Frame 2-Plane Pix X Control */ |
| /*! @{ */ |
| #define DPR_FRAME_2P_PIX_X_CTRL_NUM_X_PIX_WIDE_MASK (0xFFFFU) |
| #define DPR_FRAME_2P_PIX_X_CTRL_NUM_X_PIX_WIDE_SHIFT (0U) |
| #define DPR_FRAME_2P_PIX_X_CTRL_NUM_X_PIX_WIDE(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_PIX_X_CTRL_NUM_X_PIX_WIDE_SHIFT)) & DPR_FRAME_2P_PIX_X_CTRL_NUM_X_PIX_WIDE_MASK) |
| #define DPR_FRAME_2P_PIX_X_CTRL_CROP_ULC_X_MASK (0xFFFF0000U) |
| #define DPR_FRAME_2P_PIX_X_CTRL_CROP_ULC_X_SHIFT (16U) |
| #define DPR_FRAME_2P_PIX_X_CTRL_CROP_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_PIX_X_CTRL_CROP_ULC_X_SHIFT)) & DPR_FRAME_2P_PIX_X_CTRL_CROP_ULC_X_MASK) |
| /*! @} */ |
| |
| /*! @name FRAME_2P_PIX_Y_CTRL - Frame 2-Plane Pix Y Control */ |
| /*! @{ */ |
| #define DPR_FRAME_2P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_MASK (0xFFFFU) |
| #define DPR_FRAME_2P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_SHIFT (0U) |
| #define DPR_FRAME_2P_PIX_Y_CTRL_NUM_Y_PIX_HIGH(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_SHIFT)) & DPR_FRAME_2P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_MASK) |
| #define DPR_FRAME_2P_PIX_Y_CTRL_CROP_ULC_Y_MASK (0xFFFF0000U) |
| #define DPR_FRAME_2P_PIX_Y_CTRL_CROP_ULC_Y_SHIFT (16U) |
| #define DPR_FRAME_2P_PIX_Y_CTRL_CROP_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_PIX_Y_CTRL_CROP_ULC_Y_SHIFT)) & DPR_FRAME_2P_PIX_Y_CTRL_CROP_ULC_Y_MASK) |
| /*! @} */ |
| |
| /*! @name FRAME_2P_BASE_ADDR_CTRL0 - Frame 2-Plane Base Address Control 0 */ |
| /*! @{ */ |
| #define DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_MASK (0xFFFFFFFFU) |
| #define DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT (0U) |
| #define DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT)) & DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name RTRAM_CTRL0 - RTRAM Control 0 */ |
| /*! @{ */ |
| #define DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_MASK (0x1U) |
| #define DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_SHIFT (0U) |
| #define DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_SHIFT)) & DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_MASK) |
| #define DPR_RTRAM_CTRL0_THRES_HIGH_MASK (0xEU) |
| #define DPR_RTRAM_CTRL0_THRES_HIGH_SHIFT (1U) |
| #define DPR_RTRAM_CTRL0_THRES_HIGH(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_THRES_HIGH_SHIFT)) & DPR_RTRAM_CTRL0_THRES_HIGH_MASK) |
| #define DPR_RTRAM_CTRL0_THRES_LOW_MASK (0x70U) |
| #define DPR_RTRAM_CTRL0_THRES_LOW_SHIFT (4U) |
| #define DPR_RTRAM_CTRL0_THRES_LOW(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_THRES_LOW_SHIFT)) & DPR_RTRAM_CTRL0_THRES_LOW_MASK) |
| #define DPR_RTRAM_CTRL0_ABORT_SEL_MASK (0x80U) |
| #define DPR_RTRAM_CTRL0_ABORT_SEL_SHIFT (7U) |
| #define DPR_RTRAM_CTRL0_ABORT_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_ABORT_SEL_SHIFT)) & DPR_RTRAM_CTRL0_ABORT_SEL_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group DPR_Register_Masks */ |
| |
| |
| /* DPR - Peripheral instance base addresses */ |
| /** Peripheral DCSS__DPR1 base address */ |
| #define DCSS__DPR1_BASE (0x32E18000u) |
| /** Peripheral DCSS__DPR1 base pointer */ |
| #define DCSS__DPR1 ((DPR_Type *)DCSS__DPR1_BASE) |
| /** Peripheral DCSS__DPR2 base address */ |
| #define DCSS__DPR2_BASE (0x32E19000u) |
| /** Peripheral DCSS__DPR2 base pointer */ |
| #define DCSS__DPR2 ((DPR_Type *)DCSS__DPR2_BASE) |
| /** Peripheral DCSS__DPR3 base address */ |
| #define DCSS__DPR3_BASE (0x32E1A000u) |
| /** Peripheral DCSS__DPR3 base pointer */ |
| #define DCSS__DPR3 ((DPR_Type *)DCSS__DPR3_BASE) |
| /** Array initializer of DPR peripheral base addresses */ |
| #define DPR_BASE_ADDRS { 0u, DCSS__DPR1_BASE, DCSS__DPR2_BASE, DCSS__DPR3_BASE } |
| /** Array initializer of DPR peripheral base pointers */ |
| #define DPR_BASE_PTRS { (DPR_Type *)0u, DCSS__DPR1, DCSS__DPR2, DCSS__DPR3 } |
| |
| /*! |
| * @} |
| */ /* end of group DPR_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- DTG Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup DTG_Peripheral_Access_Layer DTG Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** DTG - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t TC_CONTROL_STATUS; /**< Timing Controller Control Register, offset: 0x0 */ |
| __IO uint32_t TC_DTG_REG1; /**< DTG lower right corner locations, offset: 0x4 */ |
| __IO uint32_t TC_DISPLAY_REG2; /**< Display Register: TOP Window Coordinates for Active display area, offset: 0x8 */ |
| __IO uint32_t TC_DISPLAY_REG3; /**< Display Register: BOTTOM Window Coordinates for Active display area, offset: 0xC */ |
| __IO uint32_t TC_CH1_REG4; /**< Channel 1 window Register: TOP Window Coordinates for channel1, offset: 0x10 */ |
| __IO uint32_t TC_CH1_REG5; /**< Channel_1 window Register: BOTTOM Window Coordinates for channel_1 window, offset: 0x14 */ |
| __IO uint32_t TC_CH2_REG6; /**< Channel 2 window Register: TOP Window Coordinates for channel_2, offset: 0x18 */ |
| __IO uint32_t TC_CH2_REG7; /**< Channel_2 window Register: BOTTOM Window Coordinates for channel_2 pixel window, offset: 0x1C */ |
| __IO uint32_t TC_CH3_REG8; /**< Channel 3 window Register: TOP Window Coordinates for channel_3, offset: 0x20 */ |
| __IO uint32_t TC_CH3_REG9; /**< Channel_3 window Register: BOTTOM Window Coordinates for channel_3 pixel window, offset: 0x24 */ |
| __IO uint32_t TC_CTX_LD_REG10; /**< Context Loader Register: Coordinates in the raster table where the context loader is started., offset: 0x28 */ |
| __IO uint32_t TC_CH1_BKRND_REG11; /**< Channel_1 background pixel color., offset: 0x2C */ |
| __IO uint32_t TC_CH2_BKRND_REG12; /**< Channel_2 background pixel color., offset: 0x30 */ |
| uint8_t RESERVED_0[4]; |
| __IO uint32_t BLENDER_DBY_EOTF_RANGEINV; /**< DBY MODE Blender control., offset: 0x38 */ |
| __IO uint32_t BLENDER_DBY_EOTF_RANGEMIN; /**< DBY MODE Blender control., offset: 0x3C */ |
| __IO uint32_t BLENDER_DBY_BDP; /**< DBY MODE blender control., offset: 0x40 */ |
| __IO uint32_t BLENDER_BKRND_I_GRAPHICS; /**< Backgound pixel color component sent to blender. Used when no valid pixels, offset: 0x44 */ |
| __IO uint32_t BLENDER_BKRND_P_GRAPHICS; /**< Backgound pixel color component sent to blender. Used when no valid pixels, offset: 0x48 */ |
| __IO uint32_t BLENDER_BKRND_T_GRAPHICS; /**< Backgound pixel color component sent to blender. Used when no valid pixels, offset: 0x4C */ |
| __IO uint32_t TC_LINE1_INT_REG13; /**< LINE1 interrupt control: Coordinate where line1 interrupt is asserted, offset: 0x50 */ |
| __IO uint32_t TC_LINE2_INT_REG14; /**< LINE2 interrupt control: Coordinate where line2 interrupt is asserted, offset: 0x54 */ |
| __IO uint32_t TC_ALPHA_DEFAULT_REG15; /**< default alpha, offset: 0x58 */ |
| __I uint32_t TC_INTERRUPT_STATUS; /**< Timing Controller interrupt status, offset: 0x5C */ |
| __IO uint32_t TC_INTRERRUPT_CONTROL_REG17; /**< Timing Controller interrupt control., offset: 0x60 */ |
| __IO uint32_t TC_CH3_BKRND_REG18; /**< Channel_3 background pixel color., offset: 0x64 */ |
| __IO uint32_t TC_INTRERRUPT_MASK; /**< Timing Controller interrupt masks, offset: 0x68 */ |
| __IO uint32_t TC_LINE3_INT_REG; /**< LINE3 interrupt control: Coordinate where line3 interrupt is asserted, offset: 0x6C */ |
| __IO uint32_t TC_LINE4_INT_REG; /**< LINE4 interrupt control: Coordinate where line4 interrupt is asserted, offset: 0x70 */ |
| __IO uint32_t TC_OL_DE_CONTROL_REG; /**< For DBY Mode: Controls the assertion and de-assertion DE signal (Overlay channel)., offset: 0x74 */ |
| __IO uint32_t TC_BL_DE_CONTROL_REG; /**< For DBY Mode: Controls the assertion and de-assertion DE signal (Base layer (BL) channel)., offset: 0x78 */ |
| __IO uint32_t TC_EL_DE_CONTROL_REG; /**< For DBY Mode: Controls the assertion and de-assertion DE signal (Enhancement layer (EL) channel)., offset: 0x7C */ |
| } DTG_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- DTG Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup DTG_Register_Masks DTG Register Masks |
| * @{ |
| */ |
| |
| /*! @name TC_CONTROL_STATUS - Timing Controller Control Register */ |
| /*! @{ */ |
| #define DTG_TC_CONTROL_STATUS_TC_VIDEO_BASE_PATH_ENABLE_MASK (0x1U) |
| #define DTG_TC_CONTROL_STATUS_TC_VIDEO_BASE_PATH_ENABLE_SHIFT (0U) |
| #define DTG_TC_CONTROL_STATUS_TC_VIDEO_BASE_PATH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_VIDEO_BASE_PATH_ENABLE_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_VIDEO_BASE_PATH_ENABLE_MASK) |
| #define DTG_TC_CONTROL_STATUS_TC_VIDEO_ENH_PATH_ENABLE_MASK (0x2U) |
| #define DTG_TC_CONTROL_STATUS_TC_VIDEO_ENH_PATH_ENABLE_SHIFT (1U) |
| #define DTG_TC_CONTROL_STATUS_TC_VIDEO_ENH_PATH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_VIDEO_ENH_PATH_ENABLE_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_VIDEO_ENH_PATH_ENABLE_MASK) |
| #define DTG_TC_CONTROL_STATUS_TC_OVERLAY_PATH_ENABLE_MASK (0x4U) |
| #define DTG_TC_CONTROL_STATUS_TC_OVERLAY_PATH_ENABLE_SHIFT (2U) |
| #define DTG_TC_CONTROL_STATUS_TC_OVERLAY_PATH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_OVERLAY_PATH_ENABLE_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_OVERLAY_PATH_ENABLE_MASK) |
| #define DTG_TC_CONTROL_STATUS_TC_OVERLAY_FIFO_DATA_MODE_MASK (0x8U) |
| #define DTG_TC_CONTROL_STATUS_TC_OVERLAY_FIFO_DATA_MODE_SHIFT (3U) |
| #define DTG_TC_CONTROL_STATUS_TC_OVERLAY_FIFO_DATA_MODE(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_OVERLAY_FIFO_DATA_MODE_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_OVERLAY_FIFO_DATA_MODE_MASK) |
| #define DTG_TC_CONTROL_STATUS_TC_BLENDER_VIDEO_ALPHA_SELECT_MASK (0x80U) |
| #define DTG_TC_CONTROL_STATUS_TC_BLENDER_VIDEO_ALPHA_SELECT_SHIFT (7U) |
| #define DTG_TC_CONTROL_STATUS_TC_BLENDER_VIDEO_ALPHA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_BLENDER_VIDEO_ALPHA_SELECT_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_BLENDER_VIDEO_ALPHA_SELECT_MASK) |
| #define DTG_TC_CONTROL_STATUS_TC_GO_MASK (0x100U) |
| #define DTG_TC_CONTROL_STATUS_TC_GO_SHIFT (8U) |
| #define DTG_TC_CONTROL_STATUS_TC_GO(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_GO_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_GO_MASK) |
| #define DTG_TC_CONTROL_STATUS_TC_DOLBY_MODE_MASK (0x200U) |
| #define DTG_TC_CONTROL_STATUS_TC_DOLBY_MODE_SHIFT (9U) |
| #define DTG_TC_CONTROL_STATUS_TC_DOLBY_MODE(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_DOLBY_MODE_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_DOLBY_MODE_MASK) |
| #define DTG_TC_CONTROL_STATUS_TC_CH1_PER_PEL_ALPHA_SEL_MASK (0x400U) |
| #define DTG_TC_CONTROL_STATUS_TC_CH1_PER_PEL_ALPHA_SEL_SHIFT (10U) |
| #define DTG_TC_CONTROL_STATUS_TC_CH1_PER_PEL_ALPHA_SEL(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_CH1_PER_PEL_ALPHA_SEL_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_CH1_PER_PEL_ALPHA_SEL_MASK) |
| #define DTG_TC_CONTROL_STATUS_TC_CSS_PIX_COMP_SWAP_MASK (0x7000U) |
| #define DTG_TC_CONTROL_STATUS_TC_CSS_PIX_COMP_SWAP_SHIFT (12U) |
| #define DTG_TC_CONTROL_STATUS_TC_CSS_PIX_COMP_SWAP(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_CSS_PIX_COMP_SWAP_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_CSS_PIX_COMP_SWAP_MASK) |
| #define DTG_TC_CONTROL_STATUS_TC_DEFAULT_OVERLAY_ALPHA_MASK (0xFF000000U) |
| #define DTG_TC_CONTROL_STATUS_TC_DEFAULT_OVERLAY_ALPHA_SHIFT (24U) |
| #define DTG_TC_CONTROL_STATUS_TC_DEFAULT_OVERLAY_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CONTROL_STATUS_TC_DEFAULT_OVERLAY_ALPHA_SHIFT)) & DTG_TC_CONTROL_STATUS_TC_DEFAULT_OVERLAY_ALPHA_MASK) |
| /*! @} */ |
| |
| /*! @name TC_DTG_REG1 - DTG lower right corner locations */ |
| /*! @{ */ |
| #define DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_X_MASK (0x1FFFU) |
| #define DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_X_SHIFT (0U) |
| #define DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_X_SHIFT)) & DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_X_MASK) |
| #define DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_Y_MASK (0x1FFF0000U) |
| #define DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_Y_SHIFT (16U) |
| #define DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_Y_SHIFT)) & DTG_TC_DTG_REG1_TC_DTG_LOWER_RIGHT_Y_MASK) |
| /*! @} */ |
| |
| /*! @name TC_DISPLAY_REG2 - Display Register: TOP Window Coordinates for Active display area */ |
| /*! @{ */ |
| #define DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_X_MASK (0x1FFFU) |
| #define DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_X_SHIFT (0U) |
| #define DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_X_SHIFT)) & DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_X_MASK) |
| #define DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_Y_MASK (0x1FFF0000U) |
| #define DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_Y_SHIFT (16U) |
| #define DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_Y_SHIFT)) & DTG_TC_DISPLAY_REG2_TC_DISPLAY_UPPER_LEFT_Y_MASK) |
| /*! @} */ |
| |
| /*! @name TC_DISPLAY_REG3 - Display Register: BOTTOM Window Coordinates for Active display area */ |
| /*! @{ */ |
| #define DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_X_MASK (0x1FFFU) |
| #define DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_X_SHIFT (0U) |
| #define DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_X_SHIFT)) & DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_X_MASK) |
| #define DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_Y_MASK (0x1FFF0000U) |
| #define DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_Y_SHIFT (16U) |
| #define DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_Y_SHIFT)) & DTG_TC_DISPLAY_REG3_TC_DISPLAY_LOWER_RIGHT_Y_MASK) |
| /*! @} */ |
| |
| /*! @name TC_CH1_REG4 - Channel 1 window Register: TOP Window Coordinates for channel1 */ |
| /*! @{ */ |
| #define DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_X_MASK (0x1FFFU) |
| #define DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_X_SHIFT (0U) |
| #define DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_X_SHIFT)) & DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_X_MASK) |
| #define DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_Y_MASK (0x1FFF0000U) |
| #define DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_Y_SHIFT (16U) |
| #define DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_Y_SHIFT)) & DTG_TC_CH1_REG4_TC_CHANNEL_1_UPPER_LEFT_Y_MASK) |
| /*! @} */ |
| |
| /*! @name TC_CH1_REG5 - Channel_1 window Register: BOTTOM Window Coordinates for channel_1 window */ |
| /*! @{ */ |
| #define DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_X_MASK (0x1FFFU) |
| #define DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_X_SHIFT (0U) |
| #define DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_X_SHIFT)) & DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_X_MASK) |
| #define DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_Y_MASK (0x1FFF0000U) |
| #define DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_Y_SHIFT (16U) |
| #define DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_Y_SHIFT)) & DTG_TC_CH1_REG5_TC_CHANNEL_1_LOWER_RIGHT_Y_MASK) |
| /*! @} */ |
| |
| /*! @name TC_CH2_REG6 - Channel 2 window Register: TOP Window Coordinates for channel_2 */ |
| /*! @{ */ |
| #define DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_X_MASK (0x1FFFU) |
| #define DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_X_SHIFT (0U) |
| #define DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_X_SHIFT)) & DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_X_MASK) |
| #define DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_Y_MASK (0x1FFF0000U) |
| #define DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_Y_SHIFT (16U) |
| #define DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_Y_SHIFT)) & DTG_TC_CH2_REG6_TC_CHANNEL_2_UPPER_LEFT_Y_MASK) |
| /*! @} */ |
| |
| /*! @name TC_CH2_REG7 - Channel_2 window Register: BOTTOM Window Coordinates for channel_2 pixel window */ |
| /*! @{ */ |
| #define DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_X_MASK (0x1FFFU) |
| #define DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_X_SHIFT (0U) |
| #define DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_X_SHIFT)) & DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_X_MASK) |
| #define DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_Y_MASK (0x1FFF0000U) |
| #define DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_Y_SHIFT (16U) |
| #define DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_Y_SHIFT)) & DTG_TC_CH2_REG7_TC_CHANNEL_2_LOWER_RIGHT_Y_MASK) |
| /*! @} */ |
| |
| /*! @name TC_CH3_REG8 - Channel 3 window Register: TOP Window Coordinates for channel_3 */ |
| /*! @{ */ |
| #define DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_X_MASK (0x1FFFU) |
| #define DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_X_SHIFT (0U) |
| #define DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_X_SHIFT)) & DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_X_MASK) |
| #define DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_Y_MASK (0x1FFF0000U) |
| #define DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_Y_SHIFT (16U) |
| #define DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_Y_SHIFT)) & DTG_TC_CH3_REG8_TC_CHANNEL_3_UPPER_LEFT_Y_MASK) |
| /*! @} */ |
| |
| /*! @name TC_CH3_REG9 - Channel_3 window Register: BOTTOM Window Coordinates for channel_3 pixel window */ |
| /*! @{ */ |
| #define DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_X_MASK (0x1FFFU) |
| #define DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_X_SHIFT (0U) |
| #define DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_X_SHIFT)) & DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_X_MASK) |
| #define DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_Y_MASK (0x1FFF0000U) |
| #define DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_Y_SHIFT (16U) |
| #define DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_Y_SHIFT)) & DTG_TC_CH3_REG9_TC_CHANNEL_3_LOWER_RIGHT_Y_MASK) |
| /*! @} */ |
| |
| /*! @name TC_CTX_LD_REG10 - Context Loader Register: Coordinates in the raster table where the context loader is started. */ |
| /*! @{ */ |
| #define DTG_TC_CTX_LD_REG10_TC_CNTXT_DB_LINE_COUNT_MASK (0x1FFFU) |
| #define DTG_TC_CTX_LD_REG10_TC_CNTXT_DB_LINE_COUNT_SHIFT (0U) |
| #define DTG_TC_CTX_LD_REG10_TC_CNTXT_DB_LINE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CTX_LD_REG10_TC_CNTXT_DB_LINE_COUNT_SHIFT)) & DTG_TC_CTX_LD_REG10_TC_CNTXT_DB_LINE_COUNT_MASK) |
| #define DTG_TC_CTX_LD_REG10_TC_CNTXT_SB_LINE_COUNT_MASK (0x1FFF0000U) |
| #define DTG_TC_CTX_LD_REG10_TC_CNTXT_SB_LINE_COUNT_SHIFT (16U) |
| #define DTG_TC_CTX_LD_REG10_TC_CNTXT_SB_LINE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CTX_LD_REG10_TC_CNTXT_SB_LINE_COUNT_SHIFT)) & DTG_TC_CTX_LD_REG10_TC_CNTXT_SB_LINE_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name TC_CH1_BKRND_REG11 - Channel_1 background pixel color. */ |
| /*! @{ */ |
| #define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_3_MASK (0x3FFU) |
| #define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_3_SHIFT (0U) |
| #define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_3(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_3_SHIFT)) & DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_3_MASK) |
| #define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_2_MASK (0xFFC00U) |
| #define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_2_SHIFT (10U) |
| #define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_2(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_2_SHIFT)) & DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_2_MASK) |
| #define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_1_MASK (0x3FF00000U) |
| #define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_1_SHIFT (20U) |
| #define DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_1(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_1_SHIFT)) & DTG_TC_CH1_BKRND_REG11_TC_CH1_BKRND_PEL_COMP_1_MASK) |
| /*! @} */ |
| |
| /*! @name TC_CH2_BKRND_REG12 - Channel_2 background pixel color. */ |
| /*! @{ */ |
| #define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_3_MASK (0x3FFU) |
| #define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_3_SHIFT (0U) |
| #define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_3(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_3_SHIFT)) & DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_3_MASK) |
| #define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_2_MASK (0xFFC00U) |
| #define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_2_SHIFT (10U) |
| #define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_2(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_2_SHIFT)) & DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_2_MASK) |
| #define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_1_MASK (0x3FF00000U) |
| #define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_1_SHIFT (20U) |
| #define DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_1(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_1_SHIFT)) & DTG_TC_CH2_BKRND_REG12_TC_CH2_BKRND_PEL_COMP_1_MASK) |
| /*! @} */ |
| |
| /*! @name BLENDER_DBY_EOTF_RANGEINV - DBY MODE Blender control. */ |
| /*! @{ */ |
| #define DTG_BLENDER_DBY_EOTF_RANGEINV_BLENDER_EOTF_RANGEINV_MASK (0x1FFFFU) |
| #define DTG_BLENDER_DBY_EOTF_RANGEINV_BLENDER_EOTF_RANGEINV_SHIFT (0U) |
| #define DTG_BLENDER_DBY_EOTF_RANGEINV_BLENDER_EOTF_RANGEINV(x) (((uint32_t)(((uint32_t)(x)) << DTG_BLENDER_DBY_EOTF_RANGEINV_BLENDER_EOTF_RANGEINV_SHIFT)) & DTG_BLENDER_DBY_EOTF_RANGEINV_BLENDER_EOTF_RANGEINV_MASK) |
| /*! @} */ |
| |
| /*! @name BLENDER_DBY_EOTF_RANGEMIN - DBY MODE Blender control. */ |
| /*! @{ */ |
| #define DTG_BLENDER_DBY_EOTF_RANGEMIN_BLENDER_EOTF_RANGEMIN_MASK (0x1FFFFU) |
| #define DTG_BLENDER_DBY_EOTF_RANGEMIN_BLENDER_EOTF_RANGEMIN_SHIFT (0U) |
| #define DTG_BLENDER_DBY_EOTF_RANGEMIN_BLENDER_EOTF_RANGEMIN(x) (((uint32_t)(((uint32_t)(x)) << DTG_BLENDER_DBY_EOTF_RANGEMIN_BLENDER_EOTF_RANGEMIN_SHIFT)) & DTG_BLENDER_DBY_EOTF_RANGEMIN_BLENDER_EOTF_RANGEMIN_MASK) |
| /*! @} */ |
| |
| /*! @name BLENDER_DBY_BDP - DBY MODE blender control. */ |
| /*! @{ */ |
| #define DTG_BLENDER_DBY_BDP_BLENDER_BDP_MASK (0x1FU) |
| #define DTG_BLENDER_DBY_BDP_BLENDER_BDP_SHIFT (0U) |
| #define DTG_BLENDER_DBY_BDP_BLENDER_BDP(x) (((uint32_t)(((uint32_t)(x)) << DTG_BLENDER_DBY_BDP_BLENDER_BDP_SHIFT)) & DTG_BLENDER_DBY_BDP_BLENDER_BDP_MASK) |
| /*! @} */ |
| |
| /*! @name BLENDER_BKRND_I_GRAPHICS - Backgound pixel color component sent to blender. Used when no valid pixels */ |
| /*! @{ */ |
| #define DTG_BLENDER_BKRND_I_GRAPHICS_BLENDER_BCKRND_I_COMP_MASK (0xFFFFFFFU) |
| #define DTG_BLENDER_BKRND_I_GRAPHICS_BLENDER_BCKRND_I_COMP_SHIFT (0U) |
| #define DTG_BLENDER_BKRND_I_GRAPHICS_BLENDER_BCKRND_I_COMP(x) (((uint32_t)(((uint32_t)(x)) << DTG_BLENDER_BKRND_I_GRAPHICS_BLENDER_BCKRND_I_COMP_SHIFT)) & DTG_BLENDER_BKRND_I_GRAPHICS_BLENDER_BCKRND_I_COMP_MASK) |
| /*! @} */ |
| |
| /*! @name BLENDER_BKRND_P_GRAPHICS - Backgound pixel color component sent to blender. Used when no valid pixels */ |
| /*! @{ */ |
| #define DTG_BLENDER_BKRND_P_GRAPHICS_BLENDER_BCKRND_P_COMP_MASK (0xFFFFFFFU) |
| #define DTG_BLENDER_BKRND_P_GRAPHICS_BLENDER_BCKRND_P_COMP_SHIFT (0U) |
| #define DTG_BLENDER_BKRND_P_GRAPHICS_BLENDER_BCKRND_P_COMP(x) (((uint32_t)(((uint32_t)(x)) << DTG_BLENDER_BKRND_P_GRAPHICS_BLENDER_BCKRND_P_COMP_SHIFT)) & DTG_BLENDER_BKRND_P_GRAPHICS_BLENDER_BCKRND_P_COMP_MASK) |
| /*! @} */ |
| |
| /*! @name BLENDER_BKRND_T_GRAPHICS - Backgound pixel color component sent to blender. Used when no valid pixels */ |
| /*! @{ */ |
| #define DTG_BLENDER_BKRND_T_GRAPHICS_BLENDER_BCKRND_T_COMP_MASK (0xFFFFFFFU) |
| #define DTG_BLENDER_BKRND_T_GRAPHICS_BLENDER_BCKRND_T_COMP_SHIFT (0U) |
| #define DTG_BLENDER_BKRND_T_GRAPHICS_BLENDER_BCKRND_T_COMP(x) (((uint32_t)(((uint32_t)(x)) << DTG_BLENDER_BKRND_T_GRAPHICS_BLENDER_BCKRND_T_COMP_SHIFT)) & DTG_BLENDER_BKRND_T_GRAPHICS_BLENDER_BCKRND_T_COMP_MASK) |
| /*! @} */ |
| |
| /*! @name TC_LINE1_INT_REG13 - LINE1 interrupt control: Coordinate where line1 interrupt is asserted */ |
| /*! @{ */ |
| #define DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_X_MASK (0x1FFFU) |
| #define DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_X_SHIFT (0U) |
| #define DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_X_SHIFT)) & DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_X_MASK) |
| #define DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_Y_MASK (0x1FFF0000U) |
| #define DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_Y_SHIFT (16U) |
| #define DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_Y_SHIFT)) & DTG_TC_LINE1_INT_REG13_TC_LINE1_INT_Y_MASK) |
| /*! @} */ |
| |
| /*! @name TC_LINE2_INT_REG14 - LINE2 interrupt control: Coordinate where line2 interrupt is asserted */ |
| /*! @{ */ |
| #define DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_X_MASK (0x1FFFU) |
| #define DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_X_SHIFT (0U) |
| #define DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_X_SHIFT)) & DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_X_MASK) |
| #define DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_Y_MASK (0x1FFF0000U) |
| #define DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_Y_SHIFT (16U) |
| #define DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_Y_SHIFT)) & DTG_TC_LINE2_INT_REG14_TC_LINE2_INT_Y_MASK) |
| /*! @} */ |
| |
| /*! @name TC_ALPHA_DEFAULT_REG15 - default alpha */ |
| /*! @{ */ |
| #define DTG_TC_ALPHA_DEFAULT_REG15_TC_ALPHA_DEF_MASK (0xFFU) |
| #define DTG_TC_ALPHA_DEFAULT_REG15_TC_ALPHA_DEF_SHIFT (0U) |
| #define DTG_TC_ALPHA_DEFAULT_REG15_TC_ALPHA_DEF(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_ALPHA_DEFAULT_REG15_TC_ALPHA_DEF_SHIFT)) & DTG_TC_ALPHA_DEFAULT_REG15_TC_ALPHA_DEF_MASK) |
| /*! @} */ |
| |
| /*! @name TC_INTERRUPT_STATUS - Timing Controller interrupt status */ |
| /*! @{ */ |
| #define DTG_TC_INTERRUPT_STATUS_TC_LINE0_INTERRUPT_MASK (0x1U) |
| #define DTG_TC_INTERRUPT_STATUS_TC_LINE0_INTERRUPT_SHIFT (0U) |
| #define DTG_TC_INTERRUPT_STATUS_TC_LINE0_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTERRUPT_STATUS_TC_LINE0_INTERRUPT_SHIFT)) & DTG_TC_INTERRUPT_STATUS_TC_LINE0_INTERRUPT_MASK) |
| #define DTG_TC_INTERRUPT_STATUS_TC_LINE1_INTERRUPT_MASK (0x2U) |
| #define DTG_TC_INTERRUPT_STATUS_TC_LINE1_INTERRUPT_SHIFT (1U) |
| #define DTG_TC_INTERRUPT_STATUS_TC_LINE1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTERRUPT_STATUS_TC_LINE1_INTERRUPT_SHIFT)) & DTG_TC_INTERRUPT_STATUS_TC_LINE1_INTERRUPT_MASK) |
| #define DTG_TC_INTERRUPT_STATUS_TC_LINE2_INTERRUPT_MASK (0x4U) |
| #define DTG_TC_INTERRUPT_STATUS_TC_LINE2_INTERRUPT_SHIFT (2U) |
| #define DTG_TC_INTERRUPT_STATUS_TC_LINE2_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTERRUPT_STATUS_TC_LINE2_INTERRUPT_SHIFT)) & DTG_TC_INTERRUPT_STATUS_TC_LINE2_INTERRUPT_MASK) |
| #define DTG_TC_INTERRUPT_STATUS_TC_LINE3_INTERRUPT_MASK (0x8U) |
| #define DTG_TC_INTERRUPT_STATUS_TC_LINE3_INTERRUPT_SHIFT (3U) |
| #define DTG_TC_INTERRUPT_STATUS_TC_LINE3_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTERRUPT_STATUS_TC_LINE3_INTERRUPT_SHIFT)) & DTG_TC_INTERRUPT_STATUS_TC_LINE3_INTERRUPT_MASK) |
| #define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH1_PANIC_INTERRUPT_MASK (0x10U) |
| #define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH1_PANIC_INTERRUPT_SHIFT (4U) |
| #define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH1_PANIC_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH1_PANIC_INTERRUPT_SHIFT)) & DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH1_PANIC_INTERRUPT_MASK) |
| #define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH2_PANIC_INTERRUPT_MASK (0x20U) |
| #define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH2_PANIC_INTERRUPT_SHIFT (5U) |
| #define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH2_PANIC_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH2_PANIC_INTERRUPT_SHIFT)) & DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH2_PANIC_INTERRUPT_MASK) |
| #define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH3_PANIC_INTERRUPT_MASK (0x40U) |
| #define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH3_PANIC_INTERRUPT_SHIFT (6U) |
| #define DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH3_PANIC_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH3_PANIC_INTERRUPT_SHIFT)) & DTG_TC_INTERRUPT_STATUS_TC_RTRAM_CH3_PANIC_INTERRUPT_MASK) |
| /*! @} */ |
| |
| /*! @name TC_INTRERRUPT_CONTROL_REG17 - Timing Controller interrupt control. */ |
| /*! @{ */ |
| #define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE0_INTERRUPT_CLR_MASK (0x1U) |
| #define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE0_INTERRUPT_CLR_SHIFT (0U) |
| #define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE0_INTERRUPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE0_INTERRUPT_CLR_SHIFT)) & DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE0_INTERRUPT_CLR_MASK) |
| #define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE1_INTERRUPT_CLR_MASK (0x2U) |
| #define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE1_INTERRUPT_CLR_SHIFT (1U) |
| #define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE1_INTERRUPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE1_INTERRUPT_CLR_SHIFT)) & DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE1_INTERRUPT_CLR_MASK) |
| #define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE2_INTERRUPT_CLR_MASK (0x4U) |
| #define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE2_INTERRUPT_CLR_SHIFT (2U) |
| #define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE2_INTERRUPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE2_INTERRUPT_CLR_SHIFT)) & DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE2_INTERRUPT_CLR_MASK) |
| #define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE3_INTERRUPT_CLR_MASK (0x8U) |
| #define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE3_INTERRUPT_CLR_SHIFT (3U) |
| #define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE3_INTERRUPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE3_INTERRUPT_CLR_SHIFT)) & DTG_TC_INTRERRUPT_CONTROL_REG17_TC_LINE3_INTERRUPT_CLR_MASK) |
| #define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH1_PANIC_INTERRUPT_CLR_MASK (0x10U) |
| #define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH1_PANIC_INTERRUPT_CLR_SHIFT (4U) |
| #define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH1_PANIC_INTERRUPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH1_PANIC_INTERRUPT_CLR_SHIFT)) & DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH1_PANIC_INTERRUPT_CLR_MASK) |
| #define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH2_PANIC_INTERRUPT_CLR_MASK (0x20U) |
| #define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH2_PANIC_INTERRUPT_CLR_SHIFT (5U) |
| #define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH2_PANIC_INTERRUPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH2_PANIC_INTERRUPT_CLR_SHIFT)) & DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH2_PANIC_INTERRUPT_CLR_MASK) |
| #define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH3_PANIC_INTERRUPT_CLR_MASK (0x40U) |
| #define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH3_PANIC_INTERRUPT_CLR_SHIFT (6U) |
| #define DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH3_PANIC_INTERRUPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH3_PANIC_INTERRUPT_CLR_SHIFT)) & DTG_TC_INTRERRUPT_CONTROL_REG17_TC_RTRAM_CH3_PANIC_INTERRUPT_CLR_MASK) |
| /*! @} */ |
| |
| /*! @name TC_CH3_BKRND_REG18 - Channel_3 background pixel color. */ |
| /*! @{ */ |
| #define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_3_MASK (0x3FFU) |
| #define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_3_SHIFT (0U) |
| #define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_3(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_3_SHIFT)) & DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_3_MASK) |
| #define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_2_MASK (0xFFC00U) |
| #define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_2_SHIFT (10U) |
| #define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_2(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_2_SHIFT)) & DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_2_MASK) |
| #define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_1_MASK (0x3FF00000U) |
| #define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_1_SHIFT (20U) |
| #define DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_1(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_1_SHIFT)) & DTG_TC_CH3_BKRND_REG18_TC_CH3_BKRND_PEL_COMP_1_MASK) |
| /*! @} */ |
| |
| /*! @name TC_INTRERRUPT_MASK - Timing Controller interrupt masks */ |
| /*! @{ */ |
| #define DTG_TC_INTRERRUPT_MASK_TC_LINE0_INT_MASK_MASK (0x1U) |
| #define DTG_TC_INTRERRUPT_MASK_TC_LINE0_INT_MASK_SHIFT (0U) |
| #define DTG_TC_INTRERRUPT_MASK_TC_LINE0_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_MASK_TC_LINE0_INT_MASK_SHIFT)) & DTG_TC_INTRERRUPT_MASK_TC_LINE0_INT_MASK_MASK) |
| #define DTG_TC_INTRERRUPT_MASK_TC_LINE1_INT_MASK_MASK (0x2U) |
| #define DTG_TC_INTRERRUPT_MASK_TC_LINE1_INT_MASK_SHIFT (1U) |
| #define DTG_TC_INTRERRUPT_MASK_TC_LINE1_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_MASK_TC_LINE1_INT_MASK_SHIFT)) & DTG_TC_INTRERRUPT_MASK_TC_LINE1_INT_MASK_MASK) |
| #define DTG_TC_INTRERRUPT_MASK_TC_LINE2_INT_MASK_MASK (0x4U) |
| #define DTG_TC_INTRERRUPT_MASK_TC_LINE2_INT_MASK_SHIFT (2U) |
| #define DTG_TC_INTRERRUPT_MASK_TC_LINE2_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_MASK_TC_LINE2_INT_MASK_SHIFT)) & DTG_TC_INTRERRUPT_MASK_TC_LINE2_INT_MASK_MASK) |
| #define DTG_TC_INTRERRUPT_MASK_TC_LINE3_INT_MASK_MASK (0x8U) |
| #define DTG_TC_INTRERRUPT_MASK_TC_LINE3_INT_MASK_SHIFT (3U) |
| #define DTG_TC_INTRERRUPT_MASK_TC_LINE3_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_MASK_TC_LINE3_INT_MASK_SHIFT)) & DTG_TC_INTRERRUPT_MASK_TC_LINE3_INT_MASK_MASK) |
| #define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH1_PANIC_INT_MASK_MASK (0x10U) |
| #define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH1_PANIC_INT_MASK_SHIFT (4U) |
| #define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH1_PANIC_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH1_PANIC_INT_MASK_SHIFT)) & DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH1_PANIC_INT_MASK_MASK) |
| #define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH2_PANIC_INT_MASK_MASK (0x20U) |
| #define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH2_PANIC_INT_MASK_SHIFT (5U) |
| #define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH2_PANIC_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH2_PANIC_INT_MASK_SHIFT)) & DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH2_PANIC_INT_MASK_MASK) |
| #define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH3_PANIC_INT_MASK_MASK (0x40U) |
| #define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH3_PANIC_INT_MASK_SHIFT (6U) |
| #define DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH3_PANIC_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH3_PANIC_INT_MASK_SHIFT)) & DTG_TC_INTRERRUPT_MASK_TC_RTRAM_CH3_PANIC_INT_MASK_MASK) |
| /*! @} */ |
| |
| /*! @name TC_LINE3_INT_REG - LINE3 interrupt control: Coordinate where line3 interrupt is asserted */ |
| /*! @{ */ |
| #define DTG_TC_LINE3_INT_REG_TC_LINE3_INT_X_MASK (0x1FFFU) |
| #define DTG_TC_LINE3_INT_REG_TC_LINE3_INT_X_SHIFT (0U) |
| #define DTG_TC_LINE3_INT_REG_TC_LINE3_INT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE3_INT_REG_TC_LINE3_INT_X_SHIFT)) & DTG_TC_LINE3_INT_REG_TC_LINE3_INT_X_MASK) |
| #define DTG_TC_LINE3_INT_REG_TC_LINE3_INT_Y_MASK (0x1FFF0000U) |
| #define DTG_TC_LINE3_INT_REG_TC_LINE3_INT_Y_SHIFT (16U) |
| #define DTG_TC_LINE3_INT_REG_TC_LINE3_INT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE3_INT_REG_TC_LINE3_INT_Y_SHIFT)) & DTG_TC_LINE3_INT_REG_TC_LINE3_INT_Y_MASK) |
| /*! @} */ |
| |
| /*! @name TC_LINE4_INT_REG - LINE4 interrupt control: Coordinate where line4 interrupt is asserted */ |
| /*! @{ */ |
| #define DTG_TC_LINE4_INT_REG_TC_LINE4_INT_X_MASK (0x1FFFU) |
| #define DTG_TC_LINE4_INT_REG_TC_LINE4_INT_X_SHIFT (0U) |
| #define DTG_TC_LINE4_INT_REG_TC_LINE4_INT_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE4_INT_REG_TC_LINE4_INT_X_SHIFT)) & DTG_TC_LINE4_INT_REG_TC_LINE4_INT_X_MASK) |
| #define DTG_TC_LINE4_INT_REG_TC_LINE4_INT_Y_MASK (0x1FFF0000U) |
| #define DTG_TC_LINE4_INT_REG_TC_LINE4_INT_Y_SHIFT (16U) |
| #define DTG_TC_LINE4_INT_REG_TC_LINE4_INT_Y(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_LINE4_INT_REG_TC_LINE4_INT_Y_SHIFT)) & DTG_TC_LINE4_INT_REG_TC_LINE4_INT_Y_MASK) |
| /*! @} */ |
| |
| /*! @name TC_OL_DE_CONTROL_REG - For DBY Mode: Controls the assertion and de-assertion DE signal (Overlay channel). */ |
| /*! @{ */ |
| #define DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_LOW_X_MASK (0x1FFFU) |
| #define DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_LOW_X_SHIFT (0U) |
| #define DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_LOW_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_LOW_X_SHIFT)) & DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_LOW_X_MASK) |
| #define DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_MASK (0x1FFF0000U) |
| #define DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_SHIFT (16U) |
| #define DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_HIGH_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_SHIFT)) & DTG_TC_OL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_MASK) |
| #define DTG_TC_OL_DE_CONTROL_REG_TC_INVERT_DE_X_MASK (0x80000000U) |
| #define DTG_TC_OL_DE_CONTROL_REG_TC_INVERT_DE_X_SHIFT (31U) |
| #define DTG_TC_OL_DE_CONTROL_REG_TC_INVERT_DE_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_OL_DE_CONTROL_REG_TC_INVERT_DE_X_SHIFT)) & DTG_TC_OL_DE_CONTROL_REG_TC_INVERT_DE_X_MASK) |
| /*! @} */ |
| |
| /*! @name TC_BL_DE_CONTROL_REG - For DBY Mode: Controls the assertion and de-assertion DE signal (Base layer (BL) channel). */ |
| /*! @{ */ |
| #define DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_LOW_X_MASK (0x1FFFU) |
| #define DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_LOW_X_SHIFT (0U) |
| #define DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_LOW_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_LOW_X_SHIFT)) & DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_LOW_X_MASK) |
| #define DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_MASK (0x1FFF0000U) |
| #define DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_SHIFT (16U) |
| #define DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_HIGH_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_SHIFT)) & DTG_TC_BL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_MASK) |
| #define DTG_TC_BL_DE_CONTROL_REG_TC_INVERT_DE_X_MASK (0x80000000U) |
| #define DTG_TC_BL_DE_CONTROL_REG_TC_INVERT_DE_X_SHIFT (31U) |
| #define DTG_TC_BL_DE_CONTROL_REG_TC_INVERT_DE_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_BL_DE_CONTROL_REG_TC_INVERT_DE_X_SHIFT)) & DTG_TC_BL_DE_CONTROL_REG_TC_INVERT_DE_X_MASK) |
| /*! @} */ |
| |
| /*! @name TC_EL_DE_CONTROL_REG - For DBY Mode: Controls the assertion and de-assertion DE signal (Enhancement layer (EL) channel). */ |
| /*! @{ */ |
| #define DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_LOW_X_MASK (0x1FFFU) |
| #define DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_LOW_X_SHIFT (0U) |
| #define DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_LOW_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_LOW_X_SHIFT)) & DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_LOW_X_MASK) |
| #define DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_MASK (0x1FFF0000U) |
| #define DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_SHIFT (16U) |
| #define DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_HIGH_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_SHIFT)) & DTG_TC_EL_DE_CONTROL_REG_TC_DE_SET_HIGH_X_MASK) |
| #define DTG_TC_EL_DE_CONTROL_REG_TC_INVERT_DE_X_MASK (0x80000000U) |
| #define DTG_TC_EL_DE_CONTROL_REG_TC_INVERT_DE_X_SHIFT (31U) |
| #define DTG_TC_EL_DE_CONTROL_REG_TC_INVERT_DE_X(x) (((uint32_t)(((uint32_t)(x)) << DTG_TC_EL_DE_CONTROL_REG_TC_INVERT_DE_X_SHIFT)) & DTG_TC_EL_DE_CONTROL_REG_TC_INVERT_DE_X_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group DTG_Register_Masks */ |
| |
| |
| /* DTG - Peripheral instance base addresses */ |
| /** Peripheral DCSS__DTG base address */ |
| #define DCSS__DTG_BASE (0x32E20000u) |
| /** Peripheral DCSS__DTG base pointer */ |
| #define DCSS__DTG ((DTG_Type *)DCSS__DTG_BASE) |
| /** Array initializer of DTG peripheral base addresses */ |
| #define DTG_BASE_ADDRS { DCSS__DTG_BASE } |
| /** Array initializer of DTG peripheral base pointers */ |
| #define DTG_BASE_PTRS { DCSS__DTG } |
| |
| /*! |
| * @} |
| */ /* end of group DTG_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- DTRC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup DTRC_Peripheral_Access_Layer DTRC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** DTRC - Register Layout Typedef */ |
| typedef struct { |
| struct { /* offset: 0x0, array step: 0x60 */ |
| __IO uint32_t FDYDSADDR; /**< Luma video data start address, array offset: 0x0, array step: 0x60 */ |
| __IO uint32_t FDCDSADDR; /**< Chroma video data start address, array offset: 0x4, array step: 0x60 */ |
| __IO uint32_t FDYTSADDR; /**< Luma table data start address, array offset: 0x8, array step: 0x60 */ |
| __IO uint32_t FDCTSADDR; /**< Chroma table data start address, array offset: 0xC, array step: 0x60 */ |
| __IO uint32_t FSIZE; /**< Frame size, array offset: 0x10, array step: 0x60 */ |
| __IO uint32_t FSYSSA; /**< Luma data slave start address, array offset: 0x14, array step: 0x60 */ |
| __IO uint32_t FSYSEA; /**< Luma data slave end address, array offset: 0x18, array step: 0x60 */ |
| __IO uint32_t FSUVSSA; /**< Chroma data slave start address, array offset: 0x1C, array step: 0x60 */ |
| __IO uint32_t FSUVSEA; /**< Chroma data slave end address, array offset: 0x20, array step: 0x60 */ |
| __IO uint32_t FCROPORIG; /**< Cropped picture origin, array offset: 0x24, array step: 0x60 */ |
| __IO uint32_t FCROPSIZE; /**< Cropped picture size, array offset: 0x28, array step: 0x60 */ |
| __IO uint32_t FDCTL; /**< Frame data control, array offset: 0x2C, array step: 0x60 */ |
| uint8_t RESERVED_0[48]; |
| } FRAME_REGISTERS[2]; |
| __IO uint32_t DTRCINTEN; /**< DTRC Interrupt enables, offset: 0xC0 */ |
| __IO uint32_t FDINTR; /**< DTRC Interrupt Requests, offset: 0xC4 */ |
| __IO uint32_t DTCTRL; /**< DTRC Control, offset: 0xC8 */ |
| __IO uint32_t ARIDR; /**< ARIDR, offset: 0xCC */ |
| __IO uint32_t DTID2DDR; /**< DTID2DDR, offset: 0xD0 */ |
| __I uint32_t DTRCCONFIG; /**< DTRCCONFIG, offset: 0xD4 */ |
| __I uint32_t DTRCVERSION; /**< DTRC Version, offset: 0xD8 */ |
| uint8_t RESERVED_0[20]; |
| __IO uint32_t PFCTRL; /**< Performance counter control, offset: 0xF0 */ |
| __IO uint32_t PFCR; /**< Performance counter, offset: 0xF4 */ |
| __IO uint32_t TOCR; /**< Time Out Cycles, offset: 0xF8 */ |
| } DTRC_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- DTRC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup DTRC_Register_Masks DTRC Register Masks |
| * @{ |
| */ |
| |
| /*! @name FDYDSADDR - Luma video data start address */ |
| /*! @{ */ |
| #define DTRC_FDYDSADDR_F0DYDSADDR_MASK (0xFFFFFFFFU) |
| #define DTRC_FDYDSADDR_F0DYDSADDR_SHIFT (0U) |
| #define DTRC_FDYDSADDR_F0DYDSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDYDSADDR_F0DYDSADDR_SHIFT)) & DTRC_FDYDSADDR_F0DYDSADDR_MASK) |
| #define DTRC_FDYDSADDR_F1DYDSADDR_MASK (0xFFFFFFFFU) |
| #define DTRC_FDYDSADDR_F1DYDSADDR_SHIFT (0U) |
| #define DTRC_FDYDSADDR_F1DYDSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDYDSADDR_F1DYDSADDR_SHIFT)) & DTRC_FDYDSADDR_F1DYDSADDR_MASK) |
| /*! @} */ |
| |
| /* The count of DTRC_FDYDSADDR */ |
| #define DTRC_FDYDSADDR_COUNT (2U) |
| |
| /*! @name FDCDSADDR - Chroma video data start address */ |
| /*! @{ */ |
| #define DTRC_FDCDSADDR_F0DCDSADDR_MASK (0xFFFFFFFFU) |
| #define DTRC_FDCDSADDR_F0DCDSADDR_SHIFT (0U) |
| #define DTRC_FDCDSADDR_F0DCDSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCDSADDR_F0DCDSADDR_SHIFT)) & DTRC_FDCDSADDR_F0DCDSADDR_MASK) |
| #define DTRC_FDCDSADDR_F1DCDSADDR_MASK (0xFFFFFFFFU) |
| #define DTRC_FDCDSADDR_F1DCDSADDR_SHIFT (0U) |
| #define DTRC_FDCDSADDR_F1DCDSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCDSADDR_F1DCDSADDR_SHIFT)) & DTRC_FDCDSADDR_F1DCDSADDR_MASK) |
| /*! @} */ |
| |
| /* The count of DTRC_FDCDSADDR */ |
| #define DTRC_FDCDSADDR_COUNT (2U) |
| |
| /*! @name FDYTSADDR - Luma table data start address */ |
| /*! @{ */ |
| #define DTRC_FDYTSADDR_F0DYTSADDR_MASK (0xFFFFFFFFU) |
| #define DTRC_FDYTSADDR_F0DYTSADDR_SHIFT (0U) |
| #define DTRC_FDYTSADDR_F0DYTSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDYTSADDR_F0DYTSADDR_SHIFT)) & DTRC_FDYTSADDR_F0DYTSADDR_MASK) |
| #define DTRC_FDYTSADDR_F1DYTSADDR_MASK (0xFFFFFFFFU) |
| #define DTRC_FDYTSADDR_F1DYTSADDR_SHIFT (0U) |
| #define DTRC_FDYTSADDR_F1DYTSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDYTSADDR_F1DYTSADDR_SHIFT)) & DTRC_FDYTSADDR_F1DYTSADDR_MASK) |
| /*! @} */ |
| |
| /* The count of DTRC_FDYTSADDR */ |
| #define DTRC_FDYTSADDR_COUNT (2U) |
| |
| /*! @name FDCTSADDR - Chroma table data start address */ |
| /*! @{ */ |
| #define DTRC_FDCTSADDR_F0DCTSADDR_MASK (0xFFFFFFFFU) |
| #define DTRC_FDCTSADDR_F0DCTSADDR_SHIFT (0U) |
| #define DTRC_FDCTSADDR_F0DCTSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTSADDR_F0DCTSADDR_SHIFT)) & DTRC_FDCTSADDR_F0DCTSADDR_MASK) |
| #define DTRC_FDCTSADDR_F1DCTSADDR_MASK (0xFFFFFFFFU) |
| #define DTRC_FDCTSADDR_F1DCTSADDR_SHIFT (0U) |
| #define DTRC_FDCTSADDR_F1DCTSADDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTSADDR_F1DCTSADDR_SHIFT)) & DTRC_FDCTSADDR_F1DCTSADDR_MASK) |
| /*! @} */ |
| |
| /* The count of DTRC_FDCTSADDR */ |
| #define DTRC_FDCTSADDR_COUNT (2U) |
| |
| /*! @name FSIZE - Frame size */ |
| /*! @{ */ |
| #define DTRC_FSIZE_F0WIDTH_MASK (0x3FFU) |
| #define DTRC_FSIZE_F0WIDTH_SHIFT (0U) |
| #define DTRC_FSIZE_F0WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSIZE_F0WIDTH_SHIFT)) & DTRC_FSIZE_F0WIDTH_MASK) |
| #define DTRC_FSIZE_F1WIDTH_MASK (0x3FFU) |
| #define DTRC_FSIZE_F1WIDTH_SHIFT (0U) |
| #define DTRC_FSIZE_F1WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSIZE_F1WIDTH_SHIFT)) & DTRC_FSIZE_F1WIDTH_MASK) |
| #define DTRC_FSIZE_F0HEIGHT_MASK (0x3FF0000U) |
| #define DTRC_FSIZE_F0HEIGHT_SHIFT (16U) |
| #define DTRC_FSIZE_F0HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSIZE_F0HEIGHT_SHIFT)) & DTRC_FSIZE_F0HEIGHT_MASK) |
| #define DTRC_FSIZE_F1HEIGHT_MASK (0x3FF0000U) |
| #define DTRC_FSIZE_F1HEIGHT_SHIFT (16U) |
| #define DTRC_FSIZE_F1HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSIZE_F1HEIGHT_SHIFT)) & DTRC_FSIZE_F1HEIGHT_MASK) |
| /*! @} */ |
| |
| /* The count of DTRC_FSIZE */ |
| #define DTRC_FSIZE_COUNT (2U) |
| |
| /*! @name FSYSSA - Luma data slave start address */ |
| /*! @{ */ |
| #define DTRC_FSYSSA_F0YSTRBYPASS_MASK (0x1U) |
| #define DTRC_FSYSSA_F0YSTRBYPASS_SHIFT (0U) |
| /*! F0YSTRBYPASS - Luma Start Tile to Raster scan Bypass |
| * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic. |
| * 0b1..All ARADDR bypasses the tile-to-rasterscan logic. |
| */ |
| #define DTRC_FSYSSA_F0YSTRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSSA_F0YSTRBYPASS_SHIFT)) & DTRC_FSYSSA_F0YSTRBYPASS_MASK) |
| #define DTRC_FSYSSA_F1YSTRBYPASS_MASK (0x1U) |
| #define DTRC_FSYSSA_F1YSTRBYPASS_SHIFT (0U) |
| /*! F1YSTRBYPASS - Luma Start Tile to Raster scan Bypass |
| * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic. |
| * 0b1..All ARADDR bypasses the tile-to-rasterscan logic. |
| */ |
| #define DTRC_FSYSSA_F1YSTRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSSA_F1YSTRBYPASS_SHIFT)) & DTRC_FSYSSA_F1YSTRBYPASS_MASK) |
| #define DTRC_FSYSSA_F0SYSSA_MASK (0xFFFFFFF0U) |
| #define DTRC_FSYSSA_F0SYSSA_SHIFT (4U) |
| #define DTRC_FSYSSA_F0SYSSA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSSA_F0SYSSA_SHIFT)) & DTRC_FSYSSA_F0SYSSA_MASK) |
| #define DTRC_FSYSSA_F1SYSSA_MASK (0xFFFFFFF0U) |
| #define DTRC_FSYSSA_F1SYSSA_SHIFT (4U) |
| #define DTRC_FSYSSA_F1SYSSA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSSA_F1SYSSA_SHIFT)) & DTRC_FSYSSA_F1SYSSA_MASK) |
| /*! @} */ |
| |
| /* The count of DTRC_FSYSSA */ |
| #define DTRC_FSYSSA_COUNT (2U) |
| |
| /*! @name FSYSEA - Luma data slave end address */ |
| /*! @{ */ |
| #define DTRC_FSYSEA_F0YETRBYPASS_MASK (0x1U) |
| #define DTRC_FSYSEA_F0YETRBYPASS_SHIFT (0U) |
| /*! F0YETRBYPASS - End Tile to Raster scan Bypass |
| * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic. |
| * 0b1..All ARADDR bypasses the tile-to-rasterscan logic. |
| */ |
| #define DTRC_FSYSEA_F0YETRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSEA_F0YETRBYPASS_SHIFT)) & DTRC_FSYSEA_F0YETRBYPASS_MASK) |
| #define DTRC_FSYSEA_F1YETRBYPASS_MASK (0x1U) |
| #define DTRC_FSYSEA_F1YETRBYPASS_SHIFT (0U) |
| /*! F1YETRBYPASS - End Tile to Raster scan Bypass |
| * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic. |
| * 0b1..All ARADDR bypasses the tile-to-rasterscan logic. |
| */ |
| #define DTRC_FSYSEA_F1YETRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSEA_F1YETRBYPASS_SHIFT)) & DTRC_FSYSEA_F1YETRBYPASS_MASK) |
| #define DTRC_FSYSEA_F0SYSEA_MASK (0xFFFFFFF0U) |
| #define DTRC_FSYSEA_F0SYSEA_SHIFT (4U) |
| #define DTRC_FSYSEA_F0SYSEA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSEA_F0SYSEA_SHIFT)) & DTRC_FSYSEA_F0SYSEA_MASK) |
| #define DTRC_FSYSEA_F1SYSEA_MASK (0xFFFFFFF0U) |
| #define DTRC_FSYSEA_F1SYSEA_SHIFT (4U) |
| #define DTRC_FSYSEA_F1SYSEA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSYSEA_F1SYSEA_SHIFT)) & DTRC_FSYSEA_F1SYSEA_MASK) |
| /*! @} */ |
| |
| /* The count of DTRC_FSYSEA */ |
| #define DTRC_FSYSEA_COUNT (2U) |
| |
| /*! @name FSUVSSA - Chroma data slave start address */ |
| /*! @{ */ |
| #define DTRC_FSUVSSA_F0CSTRBYPASS_MASK (0x1U) |
| #define DTRC_FSUVSSA_F0CSTRBYPASS_SHIFT (0U) |
| /*! F0CSTRBYPASS - Chroma Start Tile to Raster scan Bypass |
| * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic. |
| * 0b1..All ARADDR bypasses the tile-to-rasterscan logic. |
| */ |
| #define DTRC_FSUVSSA_F0CSTRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSSA_F0CSTRBYPASS_SHIFT)) & DTRC_FSUVSSA_F0CSTRBYPASS_MASK) |
| #define DTRC_FSUVSSA_F1CSTRBYPASS_MASK (0x1U) |
| #define DTRC_FSUVSSA_F1CSTRBYPASS_SHIFT (0U) |
| /*! F1CSTRBYPASS - Chroma Start Tile to Raster scan Bypass |
| * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic. |
| * 0b1..All ARADDR bypasses the tile-to-rasterscan logic. |
| */ |
| #define DTRC_FSUVSSA_F1CSTRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSSA_F1CSTRBYPASS_SHIFT)) & DTRC_FSUVSSA_F1CSTRBYPASS_MASK) |
| #define DTRC_FSUVSSA_F0SUVSSA_MASK (0xFFFFFFF0U) |
| #define DTRC_FSUVSSA_F0SUVSSA_SHIFT (4U) |
| #define DTRC_FSUVSSA_F0SUVSSA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSSA_F0SUVSSA_SHIFT)) & DTRC_FSUVSSA_F0SUVSSA_MASK) |
| #define DTRC_FSUVSSA_F1SUVSSA_MASK (0xFFFFFFF0U) |
| #define DTRC_FSUVSSA_F1SUVSSA_SHIFT (4U) |
| #define DTRC_FSUVSSA_F1SUVSSA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSSA_F1SUVSSA_SHIFT)) & DTRC_FSUVSSA_F1SUVSSA_MASK) |
| /*! @} */ |
| |
| /* The count of DTRC_FSUVSSA */ |
| #define DTRC_FSUVSSA_COUNT (2U) |
| |
| /*! @name FSUVSEA - Chroma data slave end address */ |
| /*! @{ */ |
| #define DTRC_FSUVSEA_F0CETRBYPASS_MASK (0x1U) |
| #define DTRC_FSUVSEA_F0CETRBYPASS_SHIFT (0U) |
| /*! F0CETRBYPASS - End Tile to Raster scan Bypass |
| * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic. |
| * 0b1..All ARADDR bypasses the tile-to-rasterscan logic. |
| */ |
| #define DTRC_FSUVSEA_F0CETRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSEA_F0CETRBYPASS_SHIFT)) & DTRC_FSUVSEA_F0CETRBYPASS_MASK) |
| #define DTRC_FSUVSEA_F1CETRBYPASS_MASK (0x1U) |
| #define DTRC_FSUVSEA_F1CETRBYPASS_SHIFT (0U) |
| /*! F1CETRBYPASS - End Tile to Raster scan Bypass |
| * 0b0..All ARADDR does NOT bypass the tile-to-rasterscan logic. |
| * 0b1..All ARADDR bypasses the tile-to-rasterscan logic. |
| */ |
| #define DTRC_FSUVSEA_F1CETRBYPASS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSEA_F1CETRBYPASS_SHIFT)) & DTRC_FSUVSEA_F1CETRBYPASS_MASK) |
| #define DTRC_FSUVSEA_F0SUVSEA_MASK (0xFFFFFFF0U) |
| #define DTRC_FSUVSEA_F0SUVSEA_SHIFT (4U) |
| #define DTRC_FSUVSEA_F0SUVSEA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSEA_F0SUVSEA_SHIFT)) & DTRC_FSUVSEA_F0SUVSEA_MASK) |
| #define DTRC_FSUVSEA_F1SUVSEA_MASK (0xFFFFFFF0U) |
| #define DTRC_FSUVSEA_F1SUVSEA_SHIFT (4U) |
| #define DTRC_FSUVSEA_F1SUVSEA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FSUVSEA_F1SUVSEA_SHIFT)) & DTRC_FSUVSEA_F1SUVSEA_MASK) |
| /*! @} */ |
| |
| /* The count of DTRC_FSUVSEA */ |
| #define DTRC_FSUVSEA_COUNT (2U) |
| |
| /*! @name FCROPORIG - Cropped picture origin */ |
| /*! @{ */ |
| #define DTRC_FCROPORIG_F0CROPORIGX_MASK (0x1FFFU) |
| #define DTRC_FCROPORIG_F0CROPORIGX_SHIFT (0U) |
| #define DTRC_FCROPORIG_F0CROPORIGX(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPORIG_F0CROPORIGX_SHIFT)) & DTRC_FCROPORIG_F0CROPORIGX_MASK) |
| #define DTRC_FCROPORIG_F1CROPORIGX_MASK (0x1FFFU) |
| #define DTRC_FCROPORIG_F1CROPORIGX_SHIFT (0U) |
| #define DTRC_FCROPORIG_F1CROPORIGX(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPORIG_F1CROPORIGX_SHIFT)) & DTRC_FCROPORIG_F1CROPORIGX_MASK) |
| #define DTRC_FCROPORIG_F0CROPORIGY_MASK (0x1FFF0000U) |
| #define DTRC_FCROPORIG_F0CROPORIGY_SHIFT (16U) |
| #define DTRC_FCROPORIG_F0CROPORIGY(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPORIG_F0CROPORIGY_SHIFT)) & DTRC_FCROPORIG_F0CROPORIGY_MASK) |
| #define DTRC_FCROPORIG_F1CROPORIGY_MASK (0x1FFF0000U) |
| #define DTRC_FCROPORIG_F1CROPORIGY_SHIFT (16U) |
| #define DTRC_FCROPORIG_F1CROPORIGY(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPORIG_F1CROPORIGY_SHIFT)) & DTRC_FCROPORIG_F1CROPORIGY_MASK) |
| /*! @} */ |
| |
| /* The count of DTRC_FCROPORIG */ |
| #define DTRC_FCROPORIG_COUNT (2U) |
| |
| /*! @name FCROPSIZE - Cropped picture size */ |
| /*! @{ */ |
| #define DTRC_FCROPSIZE_F0CROPWIDTH_MASK (0x1FFFU) |
| #define DTRC_FCROPSIZE_F0CROPWIDTH_SHIFT (0U) |
| #define DTRC_FCROPSIZE_F0CROPWIDTH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPSIZE_F0CROPWIDTH_SHIFT)) & DTRC_FCROPSIZE_F0CROPWIDTH_MASK) |
| #define DTRC_FCROPSIZE_F1CROPWIDTH_MASK (0x1FFFU) |
| #define DTRC_FCROPSIZE_F1CROPWIDTH_SHIFT (0U) |
| #define DTRC_FCROPSIZE_F1CROPWIDTH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPSIZE_F1CROPWIDTH_SHIFT)) & DTRC_FCROPSIZE_F1CROPWIDTH_MASK) |
| #define DTRC_FCROPSIZE_F0CROPHEIGHT_MASK (0x1FFF0000U) |
| #define DTRC_FCROPSIZE_F0CROPHEIGHT_SHIFT (16U) |
| #define DTRC_FCROPSIZE_F0CROPHEIGHT(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPSIZE_F0CROPHEIGHT_SHIFT)) & DTRC_FCROPSIZE_F0CROPHEIGHT_MASK) |
| #define DTRC_FCROPSIZE_F1CROPHEIGHT_MASK (0x1FFF0000U) |
| #define DTRC_FCROPSIZE_F1CROPHEIGHT_SHIFT (16U) |
| #define DTRC_FCROPSIZE_F1CROPHEIGHT(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FCROPSIZE_F1CROPHEIGHT_SHIFT)) & DTRC_FCROPSIZE_F1CROPHEIGHT_MASK) |
| /*! @} */ |
| |
| /* The count of DTRC_FCROPSIZE */ |
| #define DTRC_FCROPSIZE_COUNT (2U) |
| |
| /*! @name FDCTL - Frame data control */ |
| /*! @{ */ |
| #define DTRC_FDCTL_F0FRAMECFG_MASK (0x1U) |
| #define DTRC_FDCTL_F0FRAMECFG_SHIFT (0U) |
| /*! F0FRAMECFG - Frame configuration ready |
| * 0b0..Frame 0 configuration is not ready. |
| * 0b1..Frame 0 configuration is ready and decompress can start for the frame. All other configuration, such as main8/main10 are updated before setting this bit to 1. If there is no G1/G2 video transaction, set this bit to 0. |
| */ |
| #define DTRC_FDCTL_F0FRAMECFG(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F0FRAMECFG_SHIFT)) & DTRC_FDCTL_F0FRAMECFG_MASK) |
| #define DTRC_FDCTL_F1FRAMECFG_MASK (0x1U) |
| #define DTRC_FDCTL_F1FRAMECFG_SHIFT (0U) |
| /*! F1FRAMECFG - Frame configuration ready |
| * 0b0..Frame 0 configuration is not ready. |
| * 0b1..Frame 0 configuration is ready and decompress can start for the frame. All other configuration, such as main8/main10 are updated before setting this bit to 1. If there is no G1/G2 video transaction, set this bit to 0. |
| */ |
| #define DTRC_FDCTL_F1FRAMECFG(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F1FRAMECFG_SHIFT)) & DTRC_FDCTL_F1FRAMECFG_MASK) |
| #define DTRC_FDCTL_F0PIXELBITDEPTH_MASK (0x2U) |
| #define DTRC_FDCTL_F0PIXELBITDEPTH_SHIFT (1U) |
| /*! F0PIXELBITDEPTH - Pixel bit depth |
| * 0b0..10-bit pixel depth |
| * 0b1..8-bit pixel depth |
| */ |
| #define DTRC_FDCTL_F0PIXELBITDEPTH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F0PIXELBITDEPTH_SHIFT)) & DTRC_FDCTL_F0PIXELBITDEPTH_MASK) |
| #define DTRC_FDCTL_F1PIXELBITDEPTH_MASK (0x2U) |
| #define DTRC_FDCTL_F1PIXELBITDEPTH_SHIFT (1U) |
| /*! F1PIXELBITDEPTH - Pixel bit depth |
| * 0b0..10-bit pixel depth |
| * 0b1..8-bit pixel depth |
| */ |
| #define DTRC_FDCTL_F1PIXELBITDEPTH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F1PIXELBITDEPTH_SHIFT)) & DTRC_FDCTL_F1PIXELBITDEPTH_MASK) |
| #define DTRC_FDCTL_F0DECOMPRESS_MASK (0x20000U) |
| #define DTRC_FDCTL_F0DECOMPRESS_SHIFT (17U) |
| /*! F0DECOMPRESS - Decompress bypass |
| * 0b0..G2 reference frame is compressed. |
| * 0b1..G2/G1 reference frame is not compressed. |
| */ |
| #define DTRC_FDCTL_F0DECOMPRESS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F0DECOMPRESS_SHIFT)) & DTRC_FDCTL_F0DECOMPRESS_MASK) |
| #define DTRC_FDCTL_F1DECOMPRESS_MASK (0x20000U) |
| #define DTRC_FDCTL_F1DECOMPRESS_SHIFT (17U) |
| /*! F1DECOMPRESS - Decompress bypass |
| * 0b0..G2 reference frame is compressed. |
| * 0b1..G2/G1 reference frame is not compressed. |
| */ |
| #define DTRC_FDCTL_F1DECOMPRESS(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F1DECOMPRESS_SHIFT)) & DTRC_FDCTL_F1DECOMPRESS_MASK) |
| #define DTRC_FDCTL_F0CROPENABLE_MASK (0x40000U) |
| #define DTRC_FDCTL_F0CROPENABLE_SHIFT (18U) |
| #define DTRC_FDCTL_F0CROPENABLE(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F0CROPENABLE_SHIFT)) & DTRC_FDCTL_F0CROPENABLE_MASK) |
| #define DTRC_FDCTL_F1CROPENABLE_MASK (0x40000U) |
| #define DTRC_FDCTL_F1CROPENABLE_SHIFT (18U) |
| #define DTRC_FDCTL_F1CROPENABLE(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDCTL_F1CROPENABLE_SHIFT)) & DTRC_FDCTL_F1CROPENABLE_MASK) |
| /*! @} */ |
| |
| /* The count of DTRC_FDCTL */ |
| #define DTRC_FDCTL_COUNT (2U) |
| |
| /*! @name DTRCINTEN - DTRC Interrupt enables */ |
| /*! @{ */ |
| #define DTRC_DTRCINTEN_FRAMEFETCHDONE_EN_MASK (0x1U) |
| #define DTRC_DTRCINTEN_FRAMEFETCHDONE_EN_SHIFT (0U) |
| /*! FRAMEFETCHDONE_EN - Frame fetch done interrupt enable |
| * 0b0..Frame fetch done interrupt disabled. |
| * 0b1..Frame fetch done interrupt enabled. |
| */ |
| #define DTRC_DTRCINTEN_FRAMEFETCHDONE_EN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCINTEN_FRAMEFETCHDONE_EN_SHIFT)) & DTRC_DTRCINTEN_FRAMEFETCHDONE_EN_MASK) |
| #define DTRC_DTRCINTEN_BUSERROR_EN_MASK (0x2U) |
| #define DTRC_DTRCINTEN_BUSERROR_EN_SHIFT (1U) |
| /*! BUSERROR_EN - Bus error interrupt enable |
| * 0b0..Bus error interrupt disabled. |
| * 0b1..Bus error interrupt enabled. |
| */ |
| #define DTRC_DTRCINTEN_BUSERROR_EN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCINTEN_BUSERROR_EN_SHIFT)) & DTRC_DTRCINTEN_BUSERROR_EN_MASK) |
| #define DTRC_DTRCINTEN_TIMEOUT_EN_MASK (0x4U) |
| #define DTRC_DTRCINTEN_TIMEOUT_EN_SHIFT (2U) |
| /*! TIMEOUT_EN - Time out enable |
| * 0b0..Time out disabled. |
| * 0b1..Time out enabled. |
| */ |
| #define DTRC_DTRCINTEN_TIMEOUT_EN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCINTEN_TIMEOUT_EN_SHIFT)) & DTRC_DTRCINTEN_TIMEOUT_EN_MASK) |
| #define DTRC_DTRCINTEN_SLFRAMEFETCHDONE_EN_MASK (0x8U) |
| #define DTRC_DTRCINTEN_SLFRAMEFETCHDONE_EN_SHIFT (3U) |
| /*! SLFRAMEFETCHDONE_EN - Slave frame fetch done |
| * 0b0..Slave frame fetch done disabled. |
| * 0b1..Slave frame fetch done enabled. |
| */ |
| #define DTRC_DTRCINTEN_SLFRAMEFETCHDONE_EN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCINTEN_SLFRAMEFETCHDONE_EN_SHIFT)) & DTRC_DTRCINTEN_SLFRAMEFETCHDONE_EN_MASK) |
| #define DTRC_DTRCINTEN_HOTRESETFINISH_EN_MASK (0x10U) |
| #define DTRC_DTRCINTEN_HOTRESETFINISH_EN_SHIFT (4U) |
| /*! HOTRESETFINISH_EN - Hot reset finish |
| * 0b0..Hot reset finish disabled. |
| * 0b1..Hot reset finish enabled. |
| */ |
| #define DTRC_DTRCINTEN_HOTRESETFINISH_EN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCINTEN_HOTRESETFINISH_EN_SHIFT)) & DTRC_DTRCINTEN_HOTRESETFINISH_EN_MASK) |
| /*! @} */ |
| |
| /*! @name FDINTR - DTRC Interrupt Requests */ |
| /*! @{ */ |
| #define DTRC_FDINTR_FRAMEFETCHDONE_MASK (0x1U) |
| #define DTRC_FDINTR_FRAMEFETCHDONE_SHIFT (0U) |
| #define DTRC_FDINTR_FRAMEFETCHDONE(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDINTR_FRAMEFETCHDONE_SHIFT)) & DTRC_FDINTR_FRAMEFETCHDONE_MASK) |
| #define DTRC_FDINTR_BUSERROR_MASK (0x2U) |
| #define DTRC_FDINTR_BUSERROR_SHIFT (1U) |
| #define DTRC_FDINTR_BUSERROR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDINTR_BUSERROR_SHIFT)) & DTRC_FDINTR_BUSERROR_MASK) |
| #define DTRC_FDINTR_TIMEOUT_MASK (0x4U) |
| #define DTRC_FDINTR_TIMEOUT_SHIFT (2U) |
| #define DTRC_FDINTR_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDINTR_TIMEOUT_SHIFT)) & DTRC_FDINTR_TIMEOUT_MASK) |
| #define DTRC_FDINTR_SLFRAMEFETCHDONE_MASK (0x8U) |
| #define DTRC_FDINTR_SLFRAMEFETCHDONE_SHIFT (3U) |
| #define DTRC_FDINTR_SLFRAMEFETCHDONE(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDINTR_SLFRAMEFETCHDONE_SHIFT)) & DTRC_FDINTR_SLFRAMEFETCHDONE_MASK) |
| #define DTRC_FDINTR_HOTRESETFINISH_MASK (0x10U) |
| #define DTRC_FDINTR_HOTRESETFINISH_SHIFT (4U) |
| #define DTRC_FDINTR_HOTRESETFINISH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_FDINTR_HOTRESETFINISH_SHIFT)) & DTRC_FDINTR_HOTRESETFINISH_MASK) |
| /*! @} */ |
| |
| /*! @name DTCTRL - DTRC Control */ |
| /*! @{ */ |
| #define DTRC_DTCTRL_ARIDRCFG_MASK (0x3U) |
| #define DTRC_DTCTRL_ARIDRCFG_SHIFT (0U) |
| /*! ARIDRCFG - ARIDR configuration |
| * 0b00..All ARID is de-tiled. |
| * 0b01..ARID in ARIDR is de-tiled, and others are bypass. NOTE: ARID[0] specify decode luma or chroma, so 4 ARIDs in ARIDR should include both of ARID[0] ==1 and ARID[0] ==0. |
| * 0b10..ARID in ARIDR is bypass_de-tile, and others are de-tiled. |
| * 0b11..Same as 2'b01. |
| */ |
| #define DTRC_DTCTRL_ARIDRCFG(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_ARIDRCFG_SHIFT)) & DTRC_DTCTRL_ARIDRCFG_MASK) |
| #define DTRC_DTCTRL_HOTRESETTRIG_MASK (0x4U) |
| #define DTRC_DTCTRL_HOTRESETTRIG_SHIFT (2U) |
| #define DTRC_DTCTRL_HOTRESETTRIG(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_HOTRESETTRIG_SHIFT)) & DTRC_DTCTRL_HOTRESETTRIG_MASK) |
| #define DTRC_DTCTRL_G1G2DATA_MASK (0x8U) |
| #define DTRC_DTCTRL_G1G2DATA_SHIFT (3U) |
| /*! G1G2DATA - G2 or G1 source data |
| * 0b0..The source data is G2 data. |
| * 0b1..The source data is G1 tile data |
| */ |
| #define DTRC_DTCTRL_G1G2DATA(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_G1G2DATA_SHIFT)) & DTRC_DTCTRL_G1G2DATA_MASK) |
| #define DTRC_DTCTRL_AXIMAXBURSTL_MASK (0xFF0U) |
| #define DTRC_DTCTRL_AXIMAXBURSTL_SHIFT (4U) |
| #define DTRC_DTCTRL_AXIMAXBURSTL(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_AXIMAXBURSTL_SHIFT)) & DTRC_DTCTRL_AXIMAXBURSTL_MASK) |
| #define DTRC_DTCTRL_BYTESWAP_SLRAST_MASK (0xF000U) |
| #define DTRC_DTCTRL_BYTESWAP_SLRAST_SHIFT (12U) |
| #define DTRC_DTCTRL_BYTESWAP_SLRAST(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_BYTESWAP_SLRAST_SHIFT)) & DTRC_DTCTRL_BYTESWAP_SLRAST_MASK) |
| #define DTRC_DTCTRL_BYTESWAP_MCOMPTILE_MASK (0xF0000U) |
| #define DTRC_DTCTRL_BYTESWAP_MCOMPTILE_SHIFT (16U) |
| #define DTRC_DTCTRL_BYTESWAP_MCOMPTILE(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_BYTESWAP_MCOMPTILE_SHIFT)) & DTRC_DTCTRL_BYTESWAP_MCOMPTILE_MASK) |
| #define DTRC_DTCTRL_BYTESWAP_MTABLE_MASK (0xF00000U) |
| #define DTRC_DTCTRL_BYTESWAP_MTABLE_SHIFT (20U) |
| #define DTRC_DTCTRL_BYTESWAP_MTABLE(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_BYTESWAP_MTABLE_SHIFT)) & DTRC_DTCTRL_BYTESWAP_MTABLE_MASK) |
| #define DTRC_DTCTRL_BYTESWAP_M_NONG1G2_MASK (0xF000000U) |
| #define DTRC_DTCTRL_BYTESWAP_M_NONG1G2_SHIFT (24U) |
| #define DTRC_DTCTRL_BYTESWAP_M_NONG1G2(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_BYTESWAP_M_NONG1G2_SHIFT)) & DTRC_DTCTRL_BYTESWAP_M_NONG1G2_MASK) |
| #define DTRC_DTCTRL_MERGEG1G2_ARIDEN_MASK (0x10000000U) |
| #define DTRC_DTCTRL_MERGEG1G2_ARIDEN_SHIFT (28U) |
| /*! MERGEG1G2_ARIDEN - Merge G2/G1 ARID enable |
| * 0b0..G2/G1 transactions at AXI master interface use different id for table/chroma and data/luma according to DTID2DDR definition. |
| * 0b1..All G2/G1 transactions at AXI master interface use the same id configured in DTID2DDR[15:8] Please note that DTID2DDR[15:8] and DTID2DDR[7:0] still need to be set the same way as when DTCTRL[28] is 0. |
| */ |
| #define DTRC_DTCTRL_MERGEG1G2_ARIDEN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_MERGEG1G2_ARIDEN_SHIFT)) & DTRC_DTCTRL_MERGEG1G2_ARIDEN_MASK) |
| #define DTRC_DTCTRL_RAST_ENDIAN_MASK (0x20000000U) |
| #define DTRC_DTCTRL_RAST_ENDIAN_SHIFT (29U) |
| /*! RAST_ENDIAN - Raster endian mode |
| * 0b0..10-bit output format is little-endian. Byte swap setting of DTCTRL[15:12] is used. |
| * 0b1..10-bit output format is big-endian. Byte swap setting of DTCTRL[15:12] is ignored. |
| */ |
| #define DTRC_DTCTRL_RAST_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_RAST_ENDIAN_SHIFT)) & DTRC_DTCTRL_RAST_ENDIAN_MASK) |
| #define DTRC_DTCTRL_ADDR_ARID_MASK (0x40000000U) |
| #define DTRC_DTCTRL_ADDR_ARID_SHIFT (30U) |
| /*! ADDR_ARID - ADDR_ARID |
| * 0b0..By ARID (See bit[1:0] of this register). |
| * 0b1..By ARADDR |
| */ |
| #define DTRC_DTCTRL_ADDR_ARID(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_ADDR_ARID_SHIFT)) & DTRC_DTCTRL_ADDR_ARID_MASK) |
| #define DTRC_DTCTRL_FRBUFF_PTR_MASK (0x80000000U) |
| #define DTRC_DTCTRL_FRBUFF_PTR_SHIFT (31U) |
| /*! FRBUFF_PTR - FRBUFF_PTR |
| * 0b0..Configure frame 0 registers. |
| * 0b1..Configure frame 1 registers. |
| */ |
| #define DTRC_DTCTRL_FRBUFF_PTR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTCTRL_FRBUFF_PTR_SHIFT)) & DTRC_DTCTRL_FRBUFF_PTR_MASK) |
| /*! @} */ |
| |
| /*! @name ARIDR - ARIDR */ |
| /*! @{ */ |
| #define DTRC_ARIDR_ARIDR_MASK (0xFFFFFFFFU) |
| #define DTRC_ARIDR_ARIDR_SHIFT (0U) |
| #define DTRC_ARIDR_ARIDR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_ARIDR_ARIDR_SHIFT)) & DTRC_ARIDR_ARIDR_MASK) |
| /*! @} */ |
| |
| /*! @name DTID2DDR - DTID2DDR */ |
| /*! @{ */ |
| #define DTRC_DTID2DDR_ARID_COMPR_MASK (0xFFU) |
| #define DTRC_DTID2DDR_ARID_COMPR_SHIFT (0U) |
| #define DTRC_DTID2DDR_ARID_COMPR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTID2DDR_ARID_COMPR_SHIFT)) & DTRC_DTID2DDR_ARID_COMPR_MASK) |
| #define DTRC_DTID2DDR_ARID_TABLE_MASK (0xFF00U) |
| #define DTRC_DTID2DDR_ARID_TABLE_SHIFT (8U) |
| #define DTRC_DTID2DDR_ARID_TABLE(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTID2DDR_ARID_TABLE_SHIFT)) & DTRC_DTID2DDR_ARID_TABLE_MASK) |
| /*! @} */ |
| |
| /*! @name DTRCCONFIG - DTRCCONFIG */ |
| /*! @{ */ |
| #define DTRC_DTRCCONFIG_G1G2_KEEPORDER_MASK (0x2U) |
| #define DTRC_DTRCCONFIG_G1G2_KEEPORDER_SHIFT (1U) |
| /*! G1G2_KEEPORDER - G1G2_KEEPORDER |
| * 0b0..Not supported. DTRC sends out data transactions as soon as they are ready regardless of the address transactions order, The master connected to AXI slave interface must recognize the data transactions by the RID. |
| * 0b1..Supported, DTRC ensure return read data from a sequence of read transactions in the same order in which it received the address. |
| */ |
| #define DTRC_DTRCCONFIG_G1G2_KEEPORDER(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCCONFIG_G1G2_KEEPORDER_SHIFT)) & DTRC_DTRCCONFIG_G1G2_KEEPORDER_MASK) |
| #define DTRC_DTRCCONFIG_AXI_MAXBURSTL_MASK (0x4U) |
| #define DTRC_DTRCCONFIG_AXI_MAXBURSTL_SHIFT (2U) |
| /*! AXI_MAXBURSTL - AXI_MAXBURSTL |
| * 0b0..Not supported. |
| * 0b1..Supported. DTRC sends the G1/G2 relating requests with ARLEN <= (the maximum burst length - 1). The maximum burst length is set by DTCTRL[16:8]. |
| */ |
| #define DTRC_DTRCCONFIG_AXI_MAXBURSTL(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCCONFIG_AXI_MAXBURSTL_SHIFT)) & DTRC_DTRCCONFIG_AXI_MAXBURSTL_MASK) |
| #define DTRC_DTRCCONFIG_G1TILE_INPUT_MASK (0x8U) |
| #define DTRC_DTRCCONFIG_G1TILE_INPUT_SHIFT (3U) |
| /*! G1TILE_INPUT - G1TILE_INPUT |
| * 0b0..Not supported. |
| * 0b1..Supported. |
| */ |
| #define DTRC_DTRCCONFIG_G1TILE_INPUT(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCCONFIG_G1TILE_INPUT_SHIFT)) & DTRC_DTRCCONFIG_G1TILE_INPUT_MASK) |
| #define DTRC_DTRCCONFIG_MAX_PIC_WIDTH_MASK (0x30U) |
| #define DTRC_DTRCCONFIG_MAX_PIC_WIDTH_SHIFT (4U) |
| /*! MAX_PIC_WIDTH - MAX_PIC_WIDTH |
| * 0b00..4096 |
| * 0b01..1920 |
| * 0b10..Reserved. |
| * 0b11..Reserved. |
| */ |
| #define DTRC_DTRCCONFIG_MAX_PIC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCCONFIG_MAX_PIC_WIDTH_SHIFT)) & DTRC_DTRCCONFIG_MAX_PIC_WIDTH_MASK) |
| /*! @} */ |
| |
| /*! @name DTRCVERSION - DTRC Version */ |
| /*! @{ */ |
| #define DTRC_DTRCVERSION_CUST_VERSION_MASK (0xFU) |
| #define DTRC_DTRCVERSION_CUST_VERSION_SHIFT (0U) |
| #define DTRC_DTRCVERSION_CUST_VERSION(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCVERSION_CUST_VERSION_SHIFT)) & DTRC_DTRCVERSION_CUST_VERSION_MASK) |
| #define DTRC_DTRCVERSION_MINOR_MASK (0x3F0U) |
| #define DTRC_DTRCVERSION_MINOR_SHIFT (4U) |
| #define DTRC_DTRCVERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCVERSION_MINOR_SHIFT)) & DTRC_DTRCVERSION_MINOR_MASK) |
| #define DTRC_DTRCVERSION_MAJOR_MASK (0xFC00U) |
| #define DTRC_DTRCVERSION_MAJOR_SHIFT (10U) |
| #define DTRC_DTRCVERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_DTRCVERSION_MAJOR_SHIFT)) & DTRC_DTRCVERSION_MAJOR_MASK) |
| /*! @} */ |
| |
| /*! @name PFCTRL - Performance counter control */ |
| /*! @{ */ |
| #define DTRC_PFCTRL_PFC_EN_MASK (0x1U) |
| #define DTRC_PFCTRL_PFC_EN_SHIFT (0U) |
| /*! PFC_EN - PFC_EN |
| * 0b0..Performance Counter disabled. |
| * 0b1..Performance Counter enabled. |
| */ |
| #define DTRC_PFCTRL_PFC_EN(x) (((uint32_t)(((uint32_t)(x)) << DTRC_PFCTRL_PFC_EN_SHIFT)) & DTRC_PFCTRL_PFC_EN_MASK) |
| /*! @} */ |
| |
| /*! @name PFCR - Performance counter */ |
| /*! @{ */ |
| #define DTRC_PFCR_PFCR_MASK (0xFFFFFFFFU) |
| #define DTRC_PFCR_PFCR_SHIFT (0U) |
| #define DTRC_PFCR_PFCR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_PFCR_PFCR_SHIFT)) & DTRC_PFCR_PFCR_MASK) |
| /*! @} */ |
| |
| /*! @name TOCR - Time Out Cycles */ |
| /*! @{ */ |
| #define DTRC_TOCR_TOCR_MASK (0xFFFFFFFFU) |
| #define DTRC_TOCR_TOCR_SHIFT (0U) |
| #define DTRC_TOCR_TOCR(x) (((uint32_t)(((uint32_t)(x)) << DTRC_TOCR_TOCR_SHIFT)) & DTRC_TOCR_TOCR_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group DTRC_Register_Masks */ |
| |
| |
| /* DTRC - Peripheral instance base addresses */ |
| /** Peripheral DCSS__DTRC1 base address */ |
| #define DCSS__DTRC1_BASE (0x32E16000u) |
| /** Peripheral DCSS__DTRC1 base pointer */ |
| #define DCSS__DTRC1 ((DTRC_Type *)DCSS__DTRC1_BASE) |
| /** Peripheral DCSS__DTRC2 base address */ |
| #define DCSS__DTRC2_BASE (0x32E17000u) |
| /** Peripheral DCSS__DTRC2 base pointer */ |
| #define DCSS__DTRC2 ((DTRC_Type *)DCSS__DTRC2_BASE) |
| /** Array initializer of DTRC peripheral base addresses */ |
| #define DTRC_BASE_ADDRS { 0u, DCSS__DTRC1_BASE, DCSS__DTRC2_BASE } |
| /** Array initializer of DTRC peripheral base pointers */ |
| #define DTRC_BASE_PTRS { (DTRC_Type *)0u, DCSS__DTRC1, DCSS__DTRC2 } |
| |
| /*! |
| * @} |
| */ /* end of group DTRC_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- ECSPI Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ECSPI_Peripheral_Access_Layer ECSPI Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** ECSPI - Register Layout Typedef */ |
| typedef struct { |
| __I uint32_t RXDATA; /**< Receive Data Register, offset: 0x0 */ |
| __O uint32_t TXDATA; /**< Transmit Data Register, offset: 0x4 */ |
| __IO uint32_t CONREG; /**< Control Register, offset: 0x8 */ |
| __IO uint32_t CONFIGREG; /**< Config Register, offset: 0xC */ |
| __IO uint32_t INTREG; /**< Interrupt Control Register, offset: 0x10 */ |
| __IO uint32_t DMAREG; /**< DMA Control Register, offset: 0x14 */ |
| __IO uint32_t STATREG; /**< Status Register, offset: 0x18 */ |
| __IO uint32_t PERIODREG; /**< Sample Period Control Register, offset: 0x1C */ |
| __IO uint32_t TESTREG; /**< Test Control Register, offset: 0x20 */ |
| uint8_t RESERVED_0[28]; |
| __O uint32_t MSGDATA; /**< Message Data Register, offset: 0x40 */ |
| } ECSPI_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- ECSPI Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ECSPI_Register_Masks ECSPI Register Masks |
| * @{ |
| */ |
| |
| /*! @name RXDATA - Receive Data Register */ |
| /*! @{ */ |
| #define ECSPI_RXDATA_ECSPI_RXDATA_MASK (0xFFFFFFFFU) |
| #define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT (0U) |
| #define ECSPI_RXDATA_ECSPI_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_RXDATA_ECSPI_RXDATA_SHIFT)) & ECSPI_RXDATA_ECSPI_RXDATA_MASK) |
| /*! @} */ |
| |
| /*! @name TXDATA - Transmit Data Register */ |
| /*! @{ */ |
| #define ECSPI_TXDATA_ECSPI_TXDATA_MASK (0xFFFFFFFFU) |
| #define ECSPI_TXDATA_ECSPI_TXDATA_SHIFT (0U) |
| #define ECSPI_TXDATA_ECSPI_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TXDATA_ECSPI_TXDATA_SHIFT)) & ECSPI_TXDATA_ECSPI_TXDATA_MASK) |
| /*! @} */ |
| |
| /*! @name CONREG - Control Register */ |
| /*! @{ */ |
| #define ECSPI_CONREG_EN_MASK (0x1U) |
| #define ECSPI_CONREG_EN_SHIFT (0U) |
| /*! EN |
| * 0b0..Disable the block. |
| * 0b1..Enable the block. |
| */ |
| #define ECSPI_CONREG_EN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_EN_SHIFT)) & ECSPI_CONREG_EN_MASK) |
| #define ECSPI_CONREG_HT_MASK (0x2U) |
| #define ECSPI_CONREG_HT_SHIFT (1U) |
| /*! HT |
| * 0b0..Disable HT mode. |
| * 0b1..Enable HT mode. |
| */ |
| #define ECSPI_CONREG_HT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_HT_SHIFT)) & ECSPI_CONREG_HT_MASK) |
| #define ECSPI_CONREG_XCH_MASK (0x4U) |
| #define ECSPI_CONREG_XCH_SHIFT (2U) |
| /*! XCH |
| * 0b0..Idle. |
| * 0b1..Initiates exchange (write) or busy (read). |
| */ |
| #define ECSPI_CONREG_XCH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_XCH_SHIFT)) & ECSPI_CONREG_XCH_MASK) |
| #define ECSPI_CONREG_SMC_MASK (0x8U) |
| #define ECSPI_CONREG_SMC_SHIFT (3U) |
| /*! SMC |
| * 0b0..SPI Exchange Bit (XCH) controls when a SPI burst can start. Setting the XCH bit will start a SPI burst or multiple bursts. This is controlled by the SPI SS Wave Form Select (SS_CTL). Refer to XCH and SS_CTL descriptions. |
| * 0b1..Immediately starts a SPI burst when data is written in TXFIFO. |
| */ |
| #define ECSPI_CONREG_SMC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_SMC_SHIFT)) & ECSPI_CONREG_SMC_MASK) |
| #define ECSPI_CONREG_CHANNEL_MODE_MASK (0xF0U) |
| #define ECSPI_CONREG_CHANNEL_MODE_SHIFT (4U) |
| /*! CHANNEL_MODE |
| * 0b0000..Slave mode. |
| * 0b0001..Master mode. |
| */ |
| #define ECSPI_CONREG_CHANNEL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_MODE_SHIFT)) & ECSPI_CONREG_CHANNEL_MODE_MASK) |
| #define ECSPI_CONREG_POST_DIVIDER_MASK (0xF00U) |
| #define ECSPI_CONREG_POST_DIVIDER_SHIFT (8U) |
| /*! POST_DIVIDER |
| * 0b0000..Divide by 1. |
| * 0b0001..Divide by 2. |
| * 0b0010..Divide by 4. |
| * 0b1110..Divide by 2 14 . |
| * 0b1111..Divide by 2 15 . |
| */ |
| #define ECSPI_CONREG_POST_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_POST_DIVIDER_SHIFT)) & ECSPI_CONREG_POST_DIVIDER_MASK) |
| #define ECSPI_CONREG_PRE_DIVIDER_MASK (0xF000U) |
| #define ECSPI_CONREG_PRE_DIVIDER_SHIFT (12U) |
| /*! PRE_DIVIDER |
| * 0b0000..Divide by 1. |
| * 0b0001..Divide by 2. |
| * 0b0010..Divide by 3. |
| * 0b1101..Divide by 14. |
| * 0b1110..Divide by 15. |
| * 0b1111..Divide by 16. |
| */ |
| #define ECSPI_CONREG_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_PRE_DIVIDER_SHIFT)) & ECSPI_CONREG_PRE_DIVIDER_MASK) |
| #define ECSPI_CONREG_DRCTL_MASK (0x30000U) |
| #define ECSPI_CONREG_DRCTL_SHIFT (16U) |
| /*! DRCTL |
| * 0b00..The SPI_RDY signal is a don't care. |
| * 0b01..Burst will be triggered by the falling edge of the SPI_RDY signal (edge-triggered). |
| * 0b10..Burst will be triggered by a low level of the SPI_RDY signal (level-triggered). |
| * 0b11..Reserved. |
| */ |
| #define ECSPI_CONREG_DRCTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_DRCTL_SHIFT)) & ECSPI_CONREG_DRCTL_MASK) |
| #define ECSPI_CONREG_CHANNEL_SELECT_MASK (0xC0000U) |
| #define ECSPI_CONREG_CHANNEL_SELECT_SHIFT (18U) |
| /*! CHANNEL_SELECT |
| * 0b00..Channel 0 is selected. Chip Select 0 (SS0) will be asserted. |
| * 0b01..Channel 1 is selected. Chip Select 1 (SS1) will be asserted. |
| * 0b10..Channel 2 is selected. Chip Select 2 (SS2) will be asserted. |
| * 0b11..Channel 3 is selected. Chip Select 3 (SS3) will be asserted. |
| */ |
| #define ECSPI_CONREG_CHANNEL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_SELECT_SHIFT)) & ECSPI_CONREG_CHANNEL_SELECT_MASK) |
| #define ECSPI_CONREG_BURST_LENGTH_MASK (0xFFF00000U) |
| #define ECSPI_CONREG_BURST_LENGTH_SHIFT (20U) |
| /*! BURST_LENGTH |
| * 0b000000000000..A SPI burst contains the 1 LSB in a word. |
| * 0b000000000001..A SPI burst contains the 2 LSB in a word. |
| * 0b000000000010..A SPI burst contains the 3 LSB in a word. |
| * 0b000000011111..A SPI burst contains all 32 bits in a word. |
| * 0b000000100000..A SPI burst contains the 1 LSB in first word and all 32 bits in second word. |
| * 0b000000100001..A SPI burst contains the 2 LSB in first word and all 32 bits in second word. |
| * 0b111111111110..A SPI burst contains the 31 LSB in first word and 2^7 -1 words. |
| * 0b111111111111..A SPI burst contains 2^7 words. |
| */ |
| #define ECSPI_CONREG_BURST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_BURST_LENGTH_SHIFT)) & ECSPI_CONREG_BURST_LENGTH_MASK) |
| /*! @} */ |
| |
| /*! @name CONFIGREG - Config Register */ |
| /*! @{ */ |
| #define ECSPI_CONFIGREG_SCLK_PHA_MASK (0xFU) |
| #define ECSPI_CONFIGREG_SCLK_PHA_SHIFT (0U) |
| /*! SCLK_PHA |
| * 0b0000..Phase 0 operation. |
| * 0b0001..Phase 1 operation. |
| */ |
| #define ECSPI_CONFIGREG_SCLK_PHA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_PHA_SHIFT)) & ECSPI_CONFIGREG_SCLK_PHA_MASK) |
| #define ECSPI_CONFIGREG_SCLK_POL_MASK (0xF0U) |
| #define ECSPI_CONFIGREG_SCLK_POL_SHIFT (4U) |
| /*! SCLK_POL |
| * 0b0000..Active high polarity (0 = Idle). |
| * 0b0001..Active low polarity (1 = Idle). |
| */ |
| #define ECSPI_CONFIGREG_SCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_POL_SHIFT)) & ECSPI_CONFIGREG_SCLK_POL_MASK) |
| #define ECSPI_CONFIGREG_SS_CTL_MASK (0xF00U) |
| #define ECSPI_CONFIGREG_SS_CTL_SHIFT (8U) |
| /*! SS_CTL |
| * 0b0000..In master mode - only one SPI burst will be transmitted. |
| * 0b0001..In master mode - Negate Chip Select (SS) signal between SPI bursts. Multiple SPI bursts will be transmitted. The SPI transfer will automatically stop when the TXFIFO is empty. |
| * 0b0000..In slave mode - an SPI burst is completed when the number of bits received in the shift register is equal to (BURST LENGTH + 1). Only the n least-significant bits (n = BURST LENGTH[4:0] + 1) of the first received word are valid. All bits subsequent to the first received word in RXFIFO are valid. |
| * 0b0001..Reserved |
| */ |
| #define ECSPI_CONFIGREG_SS_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_CTL_SHIFT)) & ECSPI_CONFIGREG_SS_CTL_MASK) |
| #define ECSPI_CONFIGREG_SS_POL_MASK (0xF000U) |
| #define ECSPI_CONFIGREG_SS_POL_SHIFT (12U) |
| /*! SS_POL |
| * 0b0000..Active low. |
| * 0b0001..Active high. |
| */ |
| #define ECSPI_CONFIGREG_SS_POL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_POL_SHIFT)) & ECSPI_CONFIGREG_SS_POL_MASK) |
| #define ECSPI_CONFIGREG_DATA_CTL_MASK (0xF0000U) |
| #define ECSPI_CONFIGREG_DATA_CTL_SHIFT (16U) |
| /*! DATA_CTL |
| * 0b0000..Stay high. |
| * 0b0001..Stay low. |
| */ |
| #define ECSPI_CONFIGREG_DATA_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_DATA_CTL_SHIFT)) & ECSPI_CONFIGREG_DATA_CTL_MASK) |
| #define ECSPI_CONFIGREG_SCLK_CTL_MASK (0xF00000U) |
| #define ECSPI_CONFIGREG_SCLK_CTL_SHIFT (20U) |
| /*! SCLK_CTL |
| * 0b0000..Stay low. |
| * 0b0001..Stay high. |
| */ |
| #define ECSPI_CONFIGREG_SCLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_CTL_SHIFT)) & ECSPI_CONFIGREG_SCLK_CTL_MASK) |
| #define ECSPI_CONFIGREG_HT_LENGTH_MASK (0x1F000000U) |
| #define ECSPI_CONFIGREG_HT_LENGTH_SHIFT (24U) |
| #define ECSPI_CONFIGREG_HT_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_HT_LENGTH_SHIFT)) & ECSPI_CONFIGREG_HT_LENGTH_MASK) |
| /*! @} */ |
| |
| /*! @name INTREG - Interrupt Control Register */ |
| /*! @{ */ |
| #define ECSPI_INTREG_TEEN_MASK (0x1U) |
| #define ECSPI_INTREG_TEEN_SHIFT (0U) |
| /*! TEEN |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define ECSPI_INTREG_TEEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TEEN_SHIFT)) & ECSPI_INTREG_TEEN_MASK) |
| #define ECSPI_INTREG_TDREN_MASK (0x2U) |
| #define ECSPI_INTREG_TDREN_SHIFT (1U) |
| /*! TDREN |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define ECSPI_INTREG_TDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TDREN_SHIFT)) & ECSPI_INTREG_TDREN_MASK) |
| #define ECSPI_INTREG_TFEN_MASK (0x4U) |
| #define ECSPI_INTREG_TFEN_SHIFT (2U) |
| /*! TFEN |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define ECSPI_INTREG_TFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TFEN_SHIFT)) & ECSPI_INTREG_TFEN_MASK) |
| #define ECSPI_INTREG_RREN_MASK (0x8U) |
| #define ECSPI_INTREG_RREN_SHIFT (3U) |
| /*! RREN |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define ECSPI_INTREG_RREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RREN_SHIFT)) & ECSPI_INTREG_RREN_MASK) |
| #define ECSPI_INTREG_RDREN_MASK (0x10U) |
| #define ECSPI_INTREG_RDREN_SHIFT (4U) |
| /*! RDREN |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define ECSPI_INTREG_RDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RDREN_SHIFT)) & ECSPI_INTREG_RDREN_MASK) |
| #define ECSPI_INTREG_RFEN_MASK (0x20U) |
| #define ECSPI_INTREG_RFEN_SHIFT (5U) |
| /*! RFEN |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define ECSPI_INTREG_RFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RFEN_SHIFT)) & ECSPI_INTREG_RFEN_MASK) |
| #define ECSPI_INTREG_ROEN_MASK (0x40U) |
| #define ECSPI_INTREG_ROEN_SHIFT (6U) |
| /*! ROEN |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define ECSPI_INTREG_ROEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_ROEN_SHIFT)) & ECSPI_INTREG_ROEN_MASK) |
| #define ECSPI_INTREG_TCEN_MASK (0x80U) |
| #define ECSPI_INTREG_TCEN_SHIFT (7U) |
| /*! TCEN |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define ECSPI_INTREG_TCEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TCEN_SHIFT)) & ECSPI_INTREG_TCEN_MASK) |
| /*! @} */ |
| |
| /*! @name DMAREG - DMA Control Register */ |
| /*! @{ */ |
| #define ECSPI_DMAREG_TX_THRESHOLD_MASK (0x3FU) |
| #define ECSPI_DMAREG_TX_THRESHOLD_SHIFT (0U) |
| #define ECSPI_DMAREG_TX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_TX_THRESHOLD_MASK) |
| #define ECSPI_DMAREG_TEDEN_MASK (0x80U) |
| #define ECSPI_DMAREG_TEDEN_SHIFT (7U) |
| /*! TEDEN |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define ECSPI_DMAREG_TEDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TEDEN_SHIFT)) & ECSPI_DMAREG_TEDEN_MASK) |
| #define ECSPI_DMAREG_RX_THRESHOLD_MASK (0x3F0000U) |
| #define ECSPI_DMAREG_RX_THRESHOLD_SHIFT (16U) |
| #define ECSPI_DMAREG_RX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_RX_THRESHOLD_MASK) |
| #define ECSPI_DMAREG_RXDEN_MASK (0x800000U) |
| #define ECSPI_DMAREG_RXDEN_SHIFT (23U) |
| /*! RXDEN |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define ECSPI_DMAREG_RXDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXDEN_SHIFT)) & ECSPI_DMAREG_RXDEN_MASK) |
| #define ECSPI_DMAREG_RX_DMA_LENGTH_MASK (0x3F000000U) |
| #define ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT (24U) |
| #define ECSPI_DMAREG_RX_DMA_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT)) & ECSPI_DMAREG_RX_DMA_LENGTH_MASK) |
| #define ECSPI_DMAREG_RXTDEN_MASK (0x80000000U) |
| #define ECSPI_DMAREG_RXTDEN_SHIFT (31U) |
| /*! RXTDEN |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define ECSPI_DMAREG_RXTDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXTDEN_SHIFT)) & ECSPI_DMAREG_RXTDEN_MASK) |
| /*! @} */ |
| |
| /*! @name STATREG - Status Register */ |
| /*! @{ */ |
| #define ECSPI_STATREG_TE_MASK (0x1U) |
| #define ECSPI_STATREG_TE_SHIFT (0U) |
| /*! TE |
| * 0b0..TXFIFO contains one or more words. |
| * 0b1..TXFIFO is empty. |
| */ |
| #define ECSPI_STATREG_TE(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TE_SHIFT)) & ECSPI_STATREG_TE_MASK) |
| #define ECSPI_STATREG_TDR_MASK (0x2U) |
| #define ECSPI_STATREG_TDR_SHIFT (1U) |
| /*! TDR |
| * 0b0..Number of valid data slots in TXFIFO is greater than TX_THRESHOLD. |
| * 0b1..Number of valid data slots in TXFIFO is not greater than TX_THRESHOLD. |
| */ |
| #define ECSPI_STATREG_TDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TDR_SHIFT)) & ECSPI_STATREG_TDR_MASK) |
| #define ECSPI_STATREG_TF_MASK (0x4U) |
| #define ECSPI_STATREG_TF_SHIFT (2U) |
| /*! TF |
| * 0b0..TXFIFO is not Full. |
| * 0b1..TXFIFO is Full. |
| */ |
| #define ECSPI_STATREG_TF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TF_SHIFT)) & ECSPI_STATREG_TF_MASK) |
| #define ECSPI_STATREG_RR_MASK (0x8U) |
| #define ECSPI_STATREG_RR_SHIFT (3U) |
| /*! RR |
| * 0b0..No valid data in RXFIFO. |
| * 0b1..More than 1 word in RXFIFO. |
| */ |
| #define ECSPI_STATREG_RR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RR_SHIFT)) & ECSPI_STATREG_RR_MASK) |
| #define ECSPI_STATREG_RDR_MASK (0x10U) |
| #define ECSPI_STATREG_RDR_SHIFT (4U) |
| /*! RDR |
| * 0b0..When RXTDE is set - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD. |
| * 0b1..When RXTDE is set - Number of data entries in the RXFIFO is greater than RX_THRESHOLD or a DMA TAIL DMA condition exists. |
| * 0b0..When RXTDE is clear - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD. |
| * 0b1..When RXTDE is clear - Number of data entries in the RXFIFO is greater than RX_THRESHOLD. |
| */ |
| #define ECSPI_STATREG_RDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RDR_SHIFT)) & ECSPI_STATREG_RDR_MASK) |
| #define ECSPI_STATREG_RF_MASK (0x20U) |
| #define ECSPI_STATREG_RF_SHIFT (5U) |
| /*! RF |
| * 0b0..Not Full. |
| * 0b1..Full. |
| */ |
| #define ECSPI_STATREG_RF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RF_SHIFT)) & ECSPI_STATREG_RF_MASK) |
| #define ECSPI_STATREG_RO_MASK (0x40U) |
| #define ECSPI_STATREG_RO_SHIFT (6U) |
| /*! RO |
| * 0b0..RXFIFO has no overflow. |
| * 0b1..RXFIFO has overflowed. |
| */ |
| #define ECSPI_STATREG_RO(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RO_SHIFT)) & ECSPI_STATREG_RO_MASK) |
| #define ECSPI_STATREG_TC_MASK (0x80U) |
| #define ECSPI_STATREG_TC_SHIFT (7U) |
| /*! TC |
| * 0b0..Transfer in progress. |
| * 0b1..Transfer completed. |
| */ |
| #define ECSPI_STATREG_TC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TC_SHIFT)) & ECSPI_STATREG_TC_MASK) |
| /*! @} */ |
| |
| /*! @name PERIODREG - Sample Period Control Register */ |
| /*! @{ */ |
| #define ECSPI_PERIODREG_SAMPLE_PERIOD_MASK (0x7FFFU) |
| #define ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT (0U) |
| /*! SAMPLE_PERIOD |
| * 0b000000000000000..0 wait states inserted |
| * 0b000000000000001..1 wait state inserted |
| * 0b111111111111110..32766 wait states inserted |
| * 0b111111111111111..32767 wait states inserted |
| */ |
| #define ECSPI_PERIODREG_SAMPLE_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT)) & ECSPI_PERIODREG_SAMPLE_PERIOD_MASK) |
| #define ECSPI_PERIODREG_CSRC_MASK (0x8000U) |
| #define ECSPI_PERIODREG_CSRC_SHIFT (15U) |
| /*! CSRC |
| * 0b0..SPI Clock (SCLK) |
| * 0b1..Low-Frequency Reference Clock (32.768 KHz) |
| */ |
| #define ECSPI_PERIODREG_CSRC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSRC_SHIFT)) & ECSPI_PERIODREG_CSRC_MASK) |
| #define ECSPI_PERIODREG_CSD_CTL_MASK (0x3F0000U) |
| #define ECSPI_PERIODREG_CSD_CTL_SHIFT (16U) |
| #define ECSPI_PERIODREG_CSD_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSD_CTL_SHIFT)) & ECSPI_PERIODREG_CSD_CTL_MASK) |
| /*! @} */ |
| |
| /*! @name TESTREG - Test Control Register */ |
| /*! @{ */ |
| #define ECSPI_TESTREG_TXCNT_MASK (0x7FU) |
| #define ECSPI_TESTREG_TXCNT_SHIFT (0U) |
| #define ECSPI_TESTREG_TXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_TXCNT_SHIFT)) & ECSPI_TESTREG_TXCNT_MASK) |
| #define ECSPI_TESTREG_RXCNT_MASK (0x7F00U) |
| #define ECSPI_TESTREG_RXCNT_SHIFT (8U) |
| #define ECSPI_TESTREG_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_RXCNT_SHIFT)) & ECSPI_TESTREG_RXCNT_MASK) |
| #define ECSPI_TESTREG_LBC_MASK (0x80000000U) |
| #define ECSPI_TESTREG_LBC_SHIFT (31U) |
| /*! LBC |
| * 0b0..Not connected. |
| * 0b1..Transmitter and receiver sections internally connected for Loopback. |
| */ |
| #define ECSPI_TESTREG_LBC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_LBC_SHIFT)) & ECSPI_TESTREG_LBC_MASK) |
| /*! @} */ |
| |
| /*! @name MSGDATA - Message Data Register */ |
| /*! @{ */ |
| #define ECSPI_MSGDATA_ECSPI_MSGDATA_MASK (0xFFFFFFFFU) |
| #define ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT (0U) |
| #define ECSPI_MSGDATA_ECSPI_MSGDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT)) & ECSPI_MSGDATA_ECSPI_MSGDATA_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group ECSPI_Register_Masks */ |
| |
| |
| /* ECSPI - Peripheral instance base addresses */ |
| /** Peripheral ECSPI1 base address */ |
| #define ECSPI1_BASE (0x30820000u) |
| /** Peripheral ECSPI1 base pointer */ |
| #define ECSPI1 ((ECSPI_Type *)ECSPI1_BASE) |
| /** Peripheral ECSPI2 base address */ |
| #define ECSPI2_BASE (0x30830000u) |
| /** Peripheral ECSPI2 base pointer */ |
| #define ECSPI2 ((ECSPI_Type *)ECSPI2_BASE) |
| /** Peripheral ECSPI3 base address */ |
| #define ECSPI3_BASE (0x30840000u) |
| /** Peripheral ECSPI3 base pointer */ |
| #define ECSPI3 ((ECSPI_Type *)ECSPI3_BASE) |
| /** Array initializer of ECSPI peripheral base addresses */ |
| #define ECSPI_BASE_ADDRS { 0u, ECSPI1_BASE, ECSPI2_BASE, ECSPI3_BASE } |
| /** Array initializer of ECSPI peripheral base pointers */ |
| #define ECSPI_BASE_PTRS { (ECSPI_Type *)0u, ECSPI1, ECSPI2, ECSPI3 } |
| /** Interrupt vectors for the ECSPI peripheral type */ |
| #define ECSPI_IRQS { NotAvail_IRQn, ECSPI1_IRQn, ECSPI2_IRQn, ECSPI3_IRQn } |
| |
| /*! |
| * @} |
| */ /* end of group ECSPI_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- ENET Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** ENET - Register Layout Typedef */ |
| typedef struct { |
| uint8_t RESERVED_0[4]; |
| __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ |
| __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ |
| uint8_t RESERVED_1[4]; |
| __IO uint32_t RDAR; /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */ |
| __IO uint32_t TDAR; /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */ |
| uint8_t RESERVED_2[12]; |
| __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ |
| uint8_t RESERVED_3[24]; |
| __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ |
| __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ |
| uint8_t RESERVED_4[28]; |
| __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ |
| uint8_t RESERVED_5[28]; |
| __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ |
| uint8_t RESERVED_6[60]; |
| __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ |
| uint8_t RESERVED_7[28]; |
| __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ |
| __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ |
| __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ |
| __IO uint32_t TXIC[3]; /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */ |
| uint8_t RESERVED_8[4]; |
| __IO uint32_t RXIC[3]; /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */ |
| uint8_t RESERVED_9[12]; |
| __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ |
| __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ |
| __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ |
| __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ |
| uint8_t RESERVED_10[28]; |
| __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ |
| uint8_t RESERVED_11[24]; |
| __IO uint32_t RDSR1; /**< Receive Descriptor Ring 1 Start Register, offset: 0x160 */ |
| __IO uint32_t TDSR1; /**< Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164 */ |
| __IO uint32_t MRBR1; /**< Maximum Receive Buffer Size Register - Ring 1, offset: 0x168 */ |
| __IO uint32_t RDSR2; /**< Receive Descriptor Ring 2 Start Register, offset: 0x16C */ |
| __IO uint32_t TDSR2; /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170 */ |
| __IO uint32_t MRBR2; /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174 */ |
| uint8_t RESERVED_12[8]; |
| __IO uint32_t RDSR; /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */ |
| __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */ |
| __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */ |
| uint8_t RESERVED_13[4]; |
| __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ |
| __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ |
| __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ |
| __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ |
| __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ |
| __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ |
| __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ |
| __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ |
| __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ |
| uint8_t RESERVED_14[12]; |
| __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ |
| __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ |
| __IO uint32_t RCMR[2]; /**< Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4 */ |
| uint8_t RESERVED_15[8]; |
| __IO uint32_t DMACFG[2]; /**< DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4 */ |
| __IO uint32_t RDAR1; /**< Receive Descriptor Active Register - Ring 1, offset: 0x1E0 */ |
| __IO uint32_t TDAR1; /**< Transmit Descriptor Active Register - Ring 1, offset: 0x1E4 */ |
| __IO uint32_t RDAR2; /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8 */ |
| __IO uint32_t TDAR2; /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */ |
| __IO uint32_t QOS; /**< QOS Scheme, offset: 0x1F0 */ |
| uint8_t RESERVED_16[12]; |
| uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */ |
| __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ |
| __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ |
| __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ |
| __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ |
| __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ |
| __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ |
| __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ |
| __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ |
| __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ |
| __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ |
| __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ |
| __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ |
| __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ |
| __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ |
| __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ |
| __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ |
| __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ |
| uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */ |
| __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ |
| __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ |
| __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ |
| __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ |
| __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ |
| __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ |
| __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ |
| __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ |
| __I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */ |
| __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ |
| __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ |
| uint8_t RESERVED_17[12]; |
| __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ |
| __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ |
| __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ |
| __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ |
| __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ |
| __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ |
| __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ |
| __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ |
| uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */ |
| __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ |
| __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ |
| __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ |
| __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ |
| __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ |
| __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ |
| __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ |
| __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ |
| __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ |
| __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ |
| __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ |
| __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ |
| __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ |
| __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ |
| __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ |
| uint8_t RESERVED_18[284]; |
| __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ |
| __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ |
| __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ |
| __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ |
| __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ |
| __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ |
| __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ |
| uint8_t RESERVED_19[488]; |
| __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ |
| struct { /* offset: 0x608, array step: 0x8 */ |
| __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ |
| __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ |
| } CHANNEL[4]; |
| } ENET_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- ENET Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ENET_Register_Masks ENET Register Masks |
| * @{ |
| */ |
| |
| /*! @name EIR - Interrupt Event Register */ |
| /*! @{ */ |
| #define ENET_EIR_RXB1_MASK (0x1U) |
| #define ENET_EIR_RXB1_SHIFT (0U) |
| #define ENET_EIR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK) |
| #define ENET_EIR_RXF1_MASK (0x2U) |
| #define ENET_EIR_RXF1_SHIFT (1U) |
| #define ENET_EIR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK) |
| #define ENET_EIR_TXB1_MASK (0x4U) |
| #define ENET_EIR_TXB1_SHIFT (2U) |
| #define ENET_EIR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK) |
| #define ENET_EIR_TXF1_MASK (0x8U) |
| #define ENET_EIR_TXF1_SHIFT (3U) |
| #define ENET_EIR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK) |
| #define ENET_EIR_RXB2_MASK (0x10U) |
| #define ENET_EIR_RXB2_SHIFT (4U) |
| #define ENET_EIR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK) |
| #define ENET_EIR_RXF2_MASK (0x20U) |
| #define ENET_EIR_RXF2_SHIFT (5U) |
| #define ENET_EIR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK) |
| #define ENET_EIR_TXB2_MASK (0x40U) |
| #define ENET_EIR_TXB2_SHIFT (6U) |
| #define ENET_EIR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK) |
| #define ENET_EIR_TXF2_MASK (0x80U) |
| #define ENET_EIR_TXF2_SHIFT (7U) |
| #define ENET_EIR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK) |
| #define ENET_EIR_RXFLUSH_0_MASK (0x1000U) |
| #define ENET_EIR_RXFLUSH_0_SHIFT (12U) |
| #define ENET_EIR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK) |
| #define ENET_EIR_RXFLUSH_1_MASK (0x2000U) |
| #define ENET_EIR_RXFLUSH_1_SHIFT (13U) |
| #define ENET_EIR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK) |
| #define ENET_EIR_RXFLUSH_2_MASK (0x4000U) |
| #define ENET_EIR_RXFLUSH_2_SHIFT (14U) |
| #define ENET_EIR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK) |
| #define ENET_EIR_TS_TIMER_MASK (0x8000U) |
| #define ENET_EIR_TS_TIMER_SHIFT (15U) |
| #define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) |
| #define ENET_EIR_TS_AVAIL_MASK (0x10000U) |
| #define ENET_EIR_TS_AVAIL_SHIFT (16U) |
| #define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK) |
| #define ENET_EIR_WAKEUP_MASK (0x20000U) |
| #define ENET_EIR_WAKEUP_SHIFT (17U) |
| #define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK) |
| #define ENET_EIR_PLR_MASK (0x40000U) |
| #define ENET_EIR_PLR_SHIFT (18U) |
| #define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK) |
| #define ENET_EIR_UN_MASK (0x80000U) |
| #define ENET_EIR_UN_SHIFT (19U) |
| #define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK) |
| #define ENET_EIR_RL_MASK (0x100000U) |
| #define ENET_EIR_RL_SHIFT (20U) |
| #define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK) |
| #define ENET_EIR_LC_MASK (0x200000U) |
| #define ENET_EIR_LC_SHIFT (21U) |
| #define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK) |
| #define ENET_EIR_EBERR_MASK (0x400000U) |
| #define ENET_EIR_EBERR_SHIFT (22U) |
| #define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK) |
| #define ENET_EIR_MII_MASK (0x800000U) |
| #define ENET_EIR_MII_SHIFT (23U) |
| #define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK) |
| #define ENET_EIR_RXB_MASK (0x1000000U) |
| #define ENET_EIR_RXB_SHIFT (24U) |
| #define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK) |
| #define ENET_EIR_RXF_MASK (0x2000000U) |
| #define ENET_EIR_RXF_SHIFT (25U) |
| #define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK) |
| #define ENET_EIR_TXB_MASK (0x4000000U) |
| #define ENET_EIR_TXB_SHIFT (26U) |
| #define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK) |
| #define ENET_EIR_TXF_MASK (0x8000000U) |
| #define ENET_EIR_TXF_SHIFT (27U) |
| #define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK) |
| #define ENET_EIR_GRA_MASK (0x10000000U) |
| #define ENET_EIR_GRA_SHIFT (28U) |
| #define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK) |
| #define ENET_EIR_BABT_MASK (0x20000000U) |
| #define ENET_EIR_BABT_SHIFT (29U) |
| #define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK) |
| #define ENET_EIR_BABR_MASK (0x40000000U) |
| #define ENET_EIR_BABR_SHIFT (30U) |
| #define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) |
| /*! @} */ |
| |
| /*! @name EIMR - Interrupt Mask Register */ |
| /*! @{ */ |
| #define ENET_EIMR_RXB1_MASK (0x1U) |
| #define ENET_EIMR_RXB1_SHIFT (0U) |
| #define ENET_EIMR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK) |
| #define ENET_EIMR_RXF1_MASK (0x2U) |
| #define ENET_EIMR_RXF1_SHIFT (1U) |
| #define ENET_EIMR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK) |
| #define ENET_EIMR_TXB1_MASK (0x4U) |
| #define ENET_EIMR_TXB1_SHIFT (2U) |
| #define ENET_EIMR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK) |
| #define ENET_EIMR_TXF1_MASK (0x8U) |
| #define ENET_EIMR_TXF1_SHIFT (3U) |
| #define ENET_EIMR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK) |
| #define ENET_EIMR_RXB2_MASK (0x10U) |
| #define ENET_EIMR_RXB2_SHIFT (4U) |
| #define ENET_EIMR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK) |
| #define ENET_EIMR_RXF2_MASK (0x20U) |
| #define ENET_EIMR_RXF2_SHIFT (5U) |
| #define ENET_EIMR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK) |
| #define ENET_EIMR_TXB2_MASK (0x40U) |
| #define ENET_EIMR_TXB2_SHIFT (6U) |
| #define ENET_EIMR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK) |
| #define ENET_EIMR_TXF2_MASK (0x80U) |
| #define ENET_EIMR_TXF2_SHIFT (7U) |
| #define ENET_EIMR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK) |
| #define ENET_EIMR_RXFLUSH_0_MASK (0x1000U) |
| #define ENET_EIMR_RXFLUSH_0_SHIFT (12U) |
| #define ENET_EIMR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK) |
| #define ENET_EIMR_RXFLUSH_1_MASK (0x2000U) |
| #define ENET_EIMR_RXFLUSH_1_SHIFT (13U) |
| #define ENET_EIMR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK) |
| #define ENET_EIMR_RXFLUSH_2_MASK (0x4000U) |
| #define ENET_EIMR_RXFLUSH_2_SHIFT (14U) |
| #define ENET_EIMR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK) |
| #define ENET_EIMR_TS_TIMER_MASK (0x8000U) |
| #define ENET_EIMR_TS_TIMER_SHIFT (15U) |
| #define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) |
| #define ENET_EIMR_TS_AVAIL_MASK (0x10000U) |
| #define ENET_EIMR_TS_AVAIL_SHIFT (16U) |
| #define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) |
| #define ENET_EIMR_WAKEUP_MASK (0x20000U) |
| #define ENET_EIMR_WAKEUP_SHIFT (17U) |
| #define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) |
| #define ENET_EIMR_PLR_MASK (0x40000U) |
| #define ENET_EIMR_PLR_SHIFT (18U) |
| #define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) |
| #define ENET_EIMR_UN_MASK (0x80000U) |
| #define ENET_EIMR_UN_SHIFT (19U) |
| #define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) |
| #define ENET_EIMR_RL_MASK (0x100000U) |
| #define ENET_EIMR_RL_SHIFT (20U) |
| #define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) |
| #define ENET_EIMR_LC_MASK (0x200000U) |
| #define ENET_EIMR_LC_SHIFT (21U) |
| #define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) |
| #define ENET_EIMR_EBERR_MASK (0x400000U) |
| #define ENET_EIMR_EBERR_SHIFT (22U) |
| #define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) |
| #define ENET_EIMR_MII_MASK (0x800000U) |
| #define ENET_EIMR_MII_SHIFT (23U) |
| #define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) |
| #define ENET_EIMR_RXB_MASK (0x1000000U) |
| #define ENET_EIMR_RXB_SHIFT (24U) |
| #define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) |
| #define ENET_EIMR_RXF_MASK (0x2000000U) |
| #define ENET_EIMR_RXF_SHIFT (25U) |
| #define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) |
| #define ENET_EIMR_TXB_MASK (0x4000000U) |
| #define ENET_EIMR_TXB_SHIFT (26U) |
| /*! TXB - TXB Interrupt Mask |
| * 0b0..The corresponding interrupt source is masked. |
| * 0b1..The corresponding interrupt source is not masked. |
| */ |
| #define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) |
| #define ENET_EIMR_TXF_MASK (0x8000000U) |
| #define ENET_EIMR_TXF_SHIFT (27U) |
| /*! TXF - TXF Interrupt Mask |
| * 0b0..The corresponding interrupt source is masked. |
| * 0b1..The corresponding interrupt source is not masked. |
| */ |
| #define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) |
| #define ENET_EIMR_GRA_MASK (0x10000000U) |
| #define ENET_EIMR_GRA_SHIFT (28U) |
| /*! GRA - GRA Interrupt Mask |
| * 0b0..The corresponding interrupt source is masked. |
| * 0b1..The corresponding interrupt source is not masked. |
| */ |
| #define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) |
| #define ENET_EIMR_BABT_MASK (0x20000000U) |
| #define ENET_EIMR_BABT_SHIFT (29U) |
| /*! BABT - BABT Interrupt Mask |
| * 0b0..The corresponding interrupt source is masked. |
| * 0b1..The corresponding interrupt source is not masked. |
| */ |
| #define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) |
| #define ENET_EIMR_BABR_MASK (0x40000000U) |
| #define ENET_EIMR_BABR_SHIFT (30U) |
| /*! BABR - BABR Interrupt Mask |
| * 0b0..The corresponding interrupt source is masked. |
| * 0b1..The corresponding interrupt source is not masked. |
| */ |
| #define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) |
| /*! @} */ |
| |
| /*! @name RDAR - Receive Descriptor Active Register - Ring 0 */ |
| /*! @{ */ |
| #define ENET_RDAR_RDAR_MASK (0x1000000U) |
| #define ENET_RDAR_RDAR_SHIFT (24U) |
| #define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) |
| /*! @} */ |
| |
| /*! @name TDAR - Transmit Descriptor Active Register - Ring 0 */ |
| /*! @{ */ |
| #define ENET_TDAR_TDAR_MASK (0x1000000U) |
| #define ENET_TDAR_TDAR_SHIFT (24U) |
| #define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) |
| /*! @} */ |
| |
| /*! @name ECR - Ethernet Control Register */ |
| /*! @{ */ |
| #define ENET_ECR_RESET_MASK (0x1U) |
| #define ENET_ECR_RESET_SHIFT (0U) |
| #define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) |
| #define ENET_ECR_ETHEREN_MASK (0x2U) |
| #define ENET_ECR_ETHEREN_SHIFT (1U) |
| /*! ETHEREN - Ethernet Enable |
| * 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. |
| * 0b1..MAC is enabled, and reception and transmission are possible. |
| */ |
| #define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) |
| #define ENET_ECR_MAGICEN_MASK (0x4U) |
| #define ENET_ECR_MAGICEN_SHIFT (2U) |
| /*! MAGICEN - Magic Packet Detection Enable |
| * 0b0..Magic detection logic disabled. |
| * 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. |
| */ |
| #define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) |
| #define ENET_ECR_SLEEP_MASK (0x8U) |
| #define ENET_ECR_SLEEP_SHIFT (3U) |
| /*! SLEEP - Sleep Mode Enable |
| * 0b0..Normal operating mode. |
| * 0b1..Sleep mode. |
| */ |
| #define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) |
| #define ENET_ECR_EN1588_MASK (0x10U) |
| #define ENET_ECR_EN1588_SHIFT (4U) |
| /*! EN1588 - EN1588 Enable |
| * 0b0..Legacy FEC buffer descriptors and functions enabled. |
| * 0b1..Enhanced frame time-stamping functions enabled. |
| */ |
| #define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) |
| #define ENET_ECR_SPEED_MASK (0x20U) |
| #define ENET_ECR_SPEED_SHIFT (5U) |
| /*! SPEED |
| * 0b0..10/100-Mbit/s mode |
| * 0b1..1000-Mbit/s mode |
| */ |
| #define ENET_ECR_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK) |
| #define ENET_ECR_DBGEN_MASK (0x40U) |
| #define ENET_ECR_DBGEN_SHIFT (6U) |
| /*! DBGEN - Debug Enable |
| * 0b0..MAC continues operation in debug mode. |
| * 0b1..MAC enters hardware freeze mode when the processor is in debug mode. |
| */ |
| #define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) |
| #define ENET_ECR_DBSWP_MASK (0x100U) |
| #define ENET_ECR_DBSWP_SHIFT (8U) |
| /*! DBSWP - Descriptor Byte Swapping Enable |
| * 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. |
| * 0b1..The buffer descriptor bytes are swapped to support little-endian devices. |
| */ |
| #define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) |
| #define ENET_ECR_SVLANEN_MASK (0x200U) |
| #define ENET_ECR_SVLANEN_SHIFT (9U) |
| /*! SVLANEN - S-VLAN enable |
| * 0b0..Only the EtherType 0x8100 will be considered for VLAN detection. |
| * 0b1..The EtherType 0x88a8 will be considered in addition to 0x8100 (C-VLAN) to identify a VLAN frame in receive. When a VLAN frame is identified, the two bytes following the VLAN type are extracted and used by the classification match comparators, RCMRn. |
| */ |
| #define ENET_ECR_SVLANEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK) |
| #define ENET_ECR_VLANUSE2ND_MASK (0x400U) |
| #define ENET_ECR_VLANUSE2ND_SHIFT (10U) |
| /*! VLANUSE2ND - VLAN use second tag |
| * 0b0..Always extract data from the first VLAN tag if it exists. |
| * 0b1..When a double-tagged frame is detected, the data of the second tag is extracted for further processing. A double-tagged frame is defined as: The first tag can be a C-VLAN or a S-VLAN (if SVLAN_ENA = 1) The second tag must be a C-VLAN |
| */ |
| #define ENET_ECR_VLANUSE2ND(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK) |
| #define ENET_ECR_SVLANDBL_MASK (0x800U) |
| #define ENET_ECR_SVLANDBL_SHIFT (11U) |
| #define ENET_ECR_SVLANDBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK) |
| /*! @} */ |
| |
| /*! @name MMFR - MII Management Frame Register */ |
| /*! @{ */ |
| #define ENET_MMFR_DATA_MASK (0xFFFFU) |
| #define ENET_MMFR_DATA_SHIFT (0U) |
| #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) |
| #define ENET_MMFR_TA_MASK (0x30000U) |
| #define ENET_MMFR_TA_SHIFT (16U) |
| #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) |
| #define ENET_MMFR_RA_MASK (0x7C0000U) |
| #define ENET_MMFR_RA_SHIFT (18U) |
| #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) |
| #define ENET_MMFR_PA_MASK (0xF800000U) |
| #define ENET_MMFR_PA_SHIFT (23U) |
| #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) |
| #define ENET_MMFR_OP_MASK (0x30000000U) |
| #define ENET_MMFR_OP_SHIFT (28U) |
| #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) |
| #define ENET_MMFR_ST_MASK (0xC0000000U) |
| #define ENET_MMFR_ST_SHIFT (30U) |
| #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) |
| /*! @} */ |
| |
| /*! @name MSCR - MII Speed Control Register */ |
| /*! @{ */ |
| #define ENET_MSCR_MII_SPEED_MASK (0x7EU) |
| #define ENET_MSCR_MII_SPEED_SHIFT (1U) |
| #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) |
| #define ENET_MSCR_DIS_PRE_MASK (0x80U) |
| #define ENET_MSCR_DIS_PRE_SHIFT (7U) |
| /*! DIS_PRE - Disable Preamble |
| * 0b0..Preamble enabled. |
| * 0b1..Preamble (32 ones) is not prepended to the MII management frame. |
| */ |
| #define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) |
| #define ENET_MSCR_HOLDTIME_MASK (0x700U) |
| #define ENET_MSCR_HOLDTIME_SHIFT (8U) |
| /*! HOLDTIME - Hold time On MDIO Output |
| * 0b000..1 internal module clock cycle |
| * 0b001..2 internal module clock cycles |
| * 0b010..3 internal module clock cycles |
| * 0b111..8 internal module clock cycles |
| */ |
| #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) |
| /*! @} */ |
| |
| /*! @name MIBC - MIB Control Register */ |
| /*! @{ */ |
| #define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) |
| #define ENET_MIBC_MIB_CLEAR_SHIFT (29U) |
| /*! MIB_CLEAR - MIB Clear |
| * 0b0..See note above. |
| * 0b1..All statistics counters are reset to 0. |
| */ |
| #define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) |
| #define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) |
| #define ENET_MIBC_MIB_IDLE_SHIFT (30U) |
| /*! MIB_IDLE - MIB Idle |
| * 0b0..The MIB block is updating MIB counters. |
| * 0b1..The MIB block is not currently updating any MIB counters. |
| */ |
| #define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) |
| #define ENET_MIBC_MIB_DIS_MASK (0x80000000U) |
| #define ENET_MIBC_MIB_DIS_SHIFT (31U) |
| /*! MIB_DIS - Disable MIB Logic |
| * 0b0..MIB logic is enabled. |
| * 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters. |
| */ |
| #define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) |
| /*! @} */ |
| |
| /*! @name RCR - Receive Control Register */ |
| /*! @{ */ |
| #define ENET_RCR_LOOP_MASK (0x1U) |
| #define ENET_RCR_LOOP_SHIFT (0U) |
| /*! LOOP - Internal Loopback |
| * 0b0..Loopback disabled. |
| * 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. |
| */ |
| #define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) |
| #define ENET_RCR_DRT_MASK (0x2U) |
| #define ENET_RCR_DRT_SHIFT (1U) |
| /*! DRT - Disable Receive On Transmit |
| * 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. |
| * 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.) |
| */ |
| #define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) |
| #define ENET_RCR_MII_MODE_MASK (0x4U) |
| #define ENET_RCR_MII_MODE_SHIFT (2U) |
| /*! MII_MODE - Media Independent Interface Mode |
| * 0b0..Reserved. |
| * 0b1..MII or RMII mode, as indicated by the RMII_MODE field. |
| */ |
| #define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) |
| #define ENET_RCR_PROM_MASK (0x8U) |
| #define ENET_RCR_PROM_SHIFT (3U) |
| /*! PROM - Promiscuous Mode |
| * 0b0..Disabled. |
| * 0b1..Enabled. |
| */ |
| #define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) |
| #define ENET_RCR_BC_REJ_MASK (0x10U) |
| #define ENET_RCR_BC_REJ_SHIFT (4U) |
| #define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) |
| #define ENET_RCR_FCE_MASK (0x20U) |
| #define ENET_RCR_FCE_SHIFT (5U) |
| #define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) |
| #define ENET_RCR_RGMII_EN_MASK (0x40U) |
| #define ENET_RCR_RGMII_EN_SHIFT (6U) |
| /*! RGMII_EN - RGMII Mode Enable |
| * 0b0..MAC configured for non-RGMII operation |
| * 0b1..MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode. If ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode. |
| */ |
| #define ENET_RCR_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK) |
| #define ENET_RCR_RMII_MODE_MASK (0x100U) |
| #define ENET_RCR_RMII_MODE_SHIFT (8U) |
| /*! RMII_MODE - RMII Mode Enable |
| * 0b0..MAC configured for MII mode. |
| * 0b1..MAC configured for RMII operation. |
| */ |
| #define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) |
| #define ENET_RCR_RMII_10T_MASK (0x200U) |
| #define ENET_RCR_RMII_10T_SHIFT (9U) |
| /*! RMII_10T |
| * 0b0..100-Mbit/s operation. |
| * 0b1..10-Mbit/s operation. |
| */ |
| #define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) |
| #define ENET_RCR_PADEN_MASK (0x1000U) |
| #define ENET_RCR_PADEN_SHIFT (12U) |
| /*! PADEN - Enable Frame Padding Remove On Receive |
| * 0b0..No padding is removed on receive by the MAC. |
| * 0b1..Padding is removed from received frames. |
| */ |
| #define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) |
| #define ENET_RCR_PAUFWD_MASK (0x2000U) |
| #define ENET_RCR_PAUFWD_SHIFT (13U) |
| /*! PAUFWD - Terminate/Forward Pause Frames |
| * 0b0..Pause frames are terminated and discarded in the MAC. |
| * 0b1..Pause frames are forwarded to the user application. |
| */ |
| #define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) |
| #define ENET_RCR_CRCFWD_MASK (0x4000U) |
| #define ENET_RCR_CRCFWD_SHIFT (14U) |
| /*! CRCFWD - Terminate/Forward Received CRC |
| * 0b0..The CRC field of received frames is transmitted to the user application. |
| * 0b1..The CRC field is stripped from the frame. |
| */ |
| #define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) |
| #define ENET_RCR_CFEN_MASK (0x8000U) |
| #define ENET_RCR_CFEN_SHIFT (15U) |
| /*! CFEN - MAC Control Frame Enable |
| * 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. |
| * 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. |
| */ |
| #define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) |
| #define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) |
| #define ENET_RCR_MAX_FL_SHIFT (16U) |
| #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) |
| #define ENET_RCR_NLC_MASK (0x40000000U) |
| #define ENET_RCR_NLC_SHIFT (30U) |
| /*! NLC - Payload Length Check Disable |
| * 0b0..The payload length check is disabled. |
| * 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field. |
| */ |
| #define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) |
| #define ENET_RCR_GRS_MASK (0x80000000U) |
| #define ENET_RCR_GRS_SHIFT (31U) |
| #define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) |
| /*! @} */ |
| |
| /*! @name TCR - Transmit Control Register */ |
| /*! @{ */ |
| #define ENET_TCR_GTS_MASK (0x1U) |
| #define ENET_TCR_GTS_SHIFT (0U) |
| #define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) |
| #define ENET_TCR_FDEN_MASK (0x4U) |
| #define ENET_TCR_FDEN_SHIFT (2U) |
| #define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) |
| #define ENET_TCR_TFC_PAUSE_MASK (0x8U) |
| #define ENET_TCR_TFC_PAUSE_SHIFT (3U) |
| /*! TFC_PAUSE - Transmit Frame Control Pause |
| * 0b0..No PAUSE frame transmitted. |
| * 0b1..The MAC stops transmission of data frames after the current transmission is complete. |
| */ |
| #define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) |
| #define ENET_TCR_RFC_PAUSE_MASK (0x10U) |
| #define ENET_TCR_RFC_PAUSE_SHIFT (4U) |
| #define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) |
| #define ENET_TCR_ADDSEL_MASK (0xE0U) |
| #define ENET_TCR_ADDSEL_SHIFT (5U) |
| /*! ADDSEL - Source MAC Address Select On Transmit |
| * 0b000..Node MAC address programmed on PADDR1/2 registers. |
| * 0b100..Reserved. |
| * 0b101..Reserved. |
| * 0b110..Reserved. |
| */ |
| #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) |
| #define ENET_TCR_ADDINS_MASK (0x100U) |
| #define ENET_TCR_ADDINS_SHIFT (8U) |
| /*! ADDINS - Set MAC Address On Transmit |
| * 0b0..The source MAC address is not modified by the MAC. |
| * 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. |
| */ |
| #define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) |
| #define ENET_TCR_CRCFWD_MASK (0x200U) |
| #define ENET_TCR_CRCFWD_SHIFT (9U) |
| /*! CRCFWD - Forward Frame From Application With CRC |
| * 0b0..TxBD[TC] controls whether the frame has a CRC from the application. |
| * 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application. |
| */ |
| #define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) |
| /*! @} */ |
| |
| /*! @name PALR - Physical Address Lower Register */ |
| /*! @{ */ |
| #define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) |
| #define ENET_PALR_PADDR1_SHIFT (0U) |
| #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) |
| /*! @} */ |
| |
| /*! @name PAUR - Physical Address Upper Register */ |
| /*! @{ */ |
| #define ENET_PAUR_TYPE_MASK (0xFFFFU) |
| #define ENET_PAUR_TYPE_SHIFT (0U) |
| #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) |
| #define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) |
| #define ENET_PAUR_PADDR2_SHIFT (16U) |
| #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) |
| /*! @} */ |
| |
| /*! @name OPD - Opcode/Pause Duration Register */ |
| /*! @{ */ |
| #define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) |
| #define ENET_OPD_PAUSE_DUR_SHIFT (0U) |
| #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) |
| #define ENET_OPD_OPCODE_MASK (0xFFFF0000U) |
| #define ENET_OPD_OPCODE_SHIFT (16U) |
| #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) |
| /*! @} */ |
| |
| /*! @name TXIC - Transmit Interrupt Coalescing Register */ |
| /*! @{ */ |
| #define ENET_TXIC_ICTT_MASK (0xFFFFU) |
| #define ENET_TXIC_ICTT_SHIFT (0U) |
| #define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK) |
| #define ENET_TXIC_ICFT_MASK (0xFF00000U) |
| #define ENET_TXIC_ICFT_SHIFT (20U) |
| #define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK) |
| #define ENET_TXIC_ICCS_MASK (0x40000000U) |
| #define ENET_TXIC_ICCS_SHIFT (30U) |
| /*! ICCS - Interrupt Coalescing Timer Clock Source Select |
| * 0b0..Use MII/GMII TX clocks. |
| * 0b1..Use ENET system clock. |
| */ |
| #define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK) |
| #define ENET_TXIC_ICEN_MASK (0x80000000U) |
| #define ENET_TXIC_ICEN_SHIFT (31U) |
| /*! ICEN - Interrupt Coalescing Enable |
| * 0b0..Disable Interrupt coalescing. |
| * 0b1..Enable Interrupt coalescing. |
| */ |
| #define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK) |
| /*! @} */ |
| |
| /* The count of ENET_TXIC */ |
| #define ENET_TXIC_COUNT (3U) |
| |
| /*! @name RXIC - Receive Interrupt Coalescing Register */ |
| /*! @{ */ |
| #define ENET_RXIC_ICTT_MASK (0xFFFFU) |
| #define ENET_RXIC_ICTT_SHIFT (0U) |
| #define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK) |
| #define ENET_RXIC_ICFT_MASK (0xFF00000U) |
| #define ENET_RXIC_ICFT_SHIFT (20U) |
| #define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK) |
| #define ENET_RXIC_ICCS_MASK (0x40000000U) |
| #define ENET_RXIC_ICCS_SHIFT (30U) |
| /*! ICCS - Interrupt Coalescing Timer Clock Source Select |
| * 0b0..Use MII/GMII TX clocks. |
| * 0b1..Use ENET system clock. |
| */ |
| #define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK) |
| #define ENET_RXIC_ICEN_MASK (0x80000000U) |
| #define ENET_RXIC_ICEN_SHIFT (31U) |
| /*! ICEN - Interrupt Coalescing Enable |
| * 0b0..Disable Interrupt coalescing. |
| * 0b1..Enable Interrupt coalescing. |
| */ |
| #define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK) |
| /*! @} */ |
| |
| /* The count of ENET_RXIC */ |
| #define ENET_RXIC_COUNT (3U) |
| |
| /*! @name IAUR - Descriptor Individual Upper Address Register */ |
| /*! @{ */ |
| #define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) |
| #define ENET_IAUR_IADDR1_SHIFT (0U) |
| #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) |
| /*! @} */ |
| |
| /*! @name IALR - Descriptor Individual Lower Address Register */ |
| /*! @{ */ |
| #define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) |
| #define ENET_IALR_IADDR2_SHIFT (0U) |
| #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) |
| /*! @} */ |
| |
| /*! @name GAUR - Descriptor Group Upper Address Register */ |
| /*! @{ */ |
| #define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) |
| #define ENET_GAUR_GADDR1_SHIFT (0U) |
| #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) |
| /*! @} */ |
| |
| /*! @name GALR - Descriptor Group Lower Address Register */ |
| /*! @{ */ |
| #define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) |
| #define ENET_GALR_GADDR2_SHIFT (0U) |
| #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) |
| /*! @} */ |
| |
| /*! @name TFWR - Transmit FIFO Watermark Register */ |
| /*! @{ */ |
| #define ENET_TFWR_TFWR_MASK (0x3FU) |
| #define ENET_TFWR_TFWR_SHIFT (0U) |
| /*! TFWR - Transmit FIFO Write |
| * 0b000000..64 bytes written. |
| * 0b000001..64 bytes written. |
| * 0b000010..128 bytes written. |
| * 0b000011..192 bytes written. |
| * 0b111111..4032 bytes written. |
| */ |
| #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) |
| #define ENET_TFWR_STRFWD_MASK (0x100U) |
| #define ENET_TFWR_STRFWD_SHIFT (8U) |
| /*! STRFWD - Store And Forward Enable |
| * 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. |
| * 0b1..Enabled. |
| */ |
| #define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) |
| /*! @} */ |
| |
| /*! @name RDSR1 - Receive Descriptor Ring 1 Start Register */ |
| /*! @{ */ |
| #define ENET_RDSR1_R_DES_START_MASK (0xFFFFFFF8U) |
| #define ENET_RDSR1_R_DES_START_SHIFT (3U) |
| #define ENET_RDSR1_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK) |
| /*! @} */ |
| |
| /*! @name TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register */ |
| /*! @{ */ |
| #define ENET_TDSR1_X_DES_START_MASK (0xFFFFFFF8U) |
| #define ENET_TDSR1_X_DES_START_SHIFT (3U) |
| #define ENET_TDSR1_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK) |
| /*! @} */ |
| |
| /*! @name MRBR1 - Maximum Receive Buffer Size Register - Ring 1 */ |
| /*! @{ */ |
| #define ENET_MRBR1_R_BUF_SIZE_MASK (0x7F0U) |
| #define ENET_MRBR1_R_BUF_SIZE_SHIFT (4U) |
| #define ENET_MRBR1_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK) |
| /*! @} */ |
| |
| /*! @name RDSR2 - Receive Descriptor Ring 2 Start Register */ |
| /*! @{ */ |
| #define ENET_RDSR2_R_DES_START_MASK (0xFFFFFFF8U) |
| #define ENET_RDSR2_R_DES_START_SHIFT (3U) |
| #define ENET_RDSR2_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK) |
| /*! @} */ |
| |
| /*! @name TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register */ |
| /*! @{ */ |
| #define ENET_TDSR2_X_DES_START_MASK (0xFFFFFFF8U) |
| #define ENET_TDSR2_X_DES_START_SHIFT (3U) |
| #define ENET_TDSR2_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK) |
| /*! @} */ |
| |
| /*! @name MRBR2 - Maximum Receive Buffer Size Register - Ring 2 */ |
| /*! @{ */ |
| #define ENET_MRBR2_R_BUF_SIZE_MASK (0x7F0U) |
| #define ENET_MRBR2_R_BUF_SIZE_SHIFT (4U) |
| #define ENET_MRBR2_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK) |
| /*! @} */ |
| |
| /*! @name RDSR - Receive Descriptor Ring 0 Start Register */ |
| /*! @{ */ |
| #define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) |
| #define ENET_RDSR_R_DES_START_SHIFT (3U) |
| #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) |
| /*! @} */ |
| |
| /*! @name TDSR - Transmit Buffer Descriptor Ring 0 Start Register */ |
| /*! @{ */ |
| #define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) |
| #define ENET_TDSR_X_DES_START_SHIFT (3U) |
| #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) |
| /*! @} */ |
| |
| /*! @name MRBR - Maximum Receive Buffer Size Register - Ring 0 */ |
| /*! @{ */ |
| #define ENET_MRBR_R_BUF_SIZE_MASK (0x7F0U) |
| #define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) |
| #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) |
| /*! @} */ |
| |
| /*! @name RSFL - Receive FIFO Section Full Threshold */ |
| /*! @{ */ |
| #define ENET_RSFL_RX_SECTION_FULL_MASK (0x3FFU) |
| #define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) |
| #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) |
| /*! @} */ |
| |
| /*! @name RSEM - Receive FIFO Section Empty Threshold */ |
| /*! @{ */ |
| #define ENET_RSEM_RX_SECTION_EMPTY_MASK (0x3FFU) |
| #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) |
| #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) |
| #define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) |
| #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) |
| #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) |
| /*! @} */ |
| |
| /*! @name RAEM - Receive FIFO Almost Empty Threshold */ |
| /*! @{ */ |
| #define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0x3FFU) |
| #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) |
| #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) |
| /*! @} */ |
| |
| /*! @name RAFL - Receive FIFO Almost Full Threshold */ |
| /*! @{ */ |
| #define ENET_RAFL_RX_ALMOST_FULL_MASK (0x3FFU) |
| #define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) |
| #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) |
| /*! @} */ |
| |
| /*! @name TSEM - Transmit FIFO Section Empty Threshold */ |
| /*! @{ */ |
| #define ENET_TSEM_TX_SECTION_EMPTY_MASK (0x3FFU) |
| #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) |
| #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) |
| /*! @} */ |
| |
| /*! @name TAEM - Transmit FIFO Almost Empty Threshold */ |
| /*! @{ */ |
| #define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0x3FFU) |
| #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) |
| #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) |
| /*! @} */ |
| |
| /*! @name TAFL - Transmit FIFO Almost Full Threshold */ |
| /*! @{ */ |
| #define ENET_TAFL_TX_ALMOST_FULL_MASK (0x3FFU) |
| #define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) |
| #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) |
| /*! @} */ |
| |
| /*! @name TIPG - Transmit Inter-Packet Gap */ |
| /*! @{ */ |
| #define ENET_TIPG_IPG_MASK (0x1FU) |
| #define ENET_TIPG_IPG_SHIFT (0U) |
| #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) |
| /*! @} */ |
| |
| /*! @name FTRL - Frame Truncation Length */ |
| /*! @{ */ |
| #define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) |
| #define ENET_FTRL_TRUNC_FL_SHIFT (0U) |
| #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) |
| /*! @} */ |
| |
| /*! @name TACC - Transmit Accelerator Function Configuration */ |
| /*! @{ */ |
| #define ENET_TACC_SHIFT16_MASK (0x1U) |
| #define ENET_TACC_SHIFT16_SHIFT (0U) |
| /*! SHIFT16 - TX FIFO Shift-16 |
| * 0b0..Disabled. |
| * 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header. |
| */ |
| #define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) |
| #define ENET_TACC_IPCHK_MASK (0x8U) |
| #define ENET_TACC_IPCHK_SHIFT (3U) |
| /*! IPCHK |
| * 0b0..Checksum is not inserted. |
| * 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified. |
| */ |
| #define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) |
| #define ENET_TACC_PROCHK_MASK (0x10U) |
| #define ENET_TACC_PROCHK_SHIFT (4U) |
| /*! PROCHK |
| * 0b0..Checksum not inserted. |
| * 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified. |
| */ |
| #define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) |
| /*! @} */ |
| |
| /*! @name RACC - Receive Accelerator Function Configuration */ |
| /*! @{ */ |
| #define ENET_RACC_PADREM_MASK (0x1U) |
| #define ENET_RACC_PADREM_SHIFT (0U) |
| /*! PADREM - Enable Padding Removal For Short IP Frames |
| * 0b0..Padding not removed. |
| * 0b1..Any bytes following the IP payload section of the frame are removed from the frame. |
| */ |
| #define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) |
| #define ENET_RACC_IPDIS_MASK (0x2U) |
| #define ENET_RACC_IPDIS_SHIFT (1U) |
| /*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum |
| * 0b0..Frames with wrong IPv4 header checksum are not discarded. |
| * 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). |
| */ |
| #define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) |
| #define ENET_RACC_PRODIS_MASK (0x4U) |
| #define ENET_RACC_PRODIS_SHIFT (2U) |
| /*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum |
| * 0b0..Frames with wrong checksum are not discarded. |
| * 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). |
| */ |
| #define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) |
| #define ENET_RACC_LINEDIS_MASK (0x40U) |
| #define ENET_RACC_LINEDIS_SHIFT (6U) |
| /*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors |
| * 0b0..Frames with errors are not discarded. |
| * 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. |
| */ |
| #define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) |
| #define ENET_RACC_SHIFT16_MASK (0x80U) |
| #define ENET_RACC_SHIFT16_SHIFT (7U) |
| /*! SHIFT16 - RX FIFO Shift-16 |
| * 0b0..Disabled. |
| * 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. |
| */ |
| #define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) |
| /*! @} */ |
| |
| /*! @name RCMR - Receive Classification Match Register for Class n */ |
| /*! @{ */ |
| #define ENET_RCMR_CMP0_MASK (0x7U) |
| #define ENET_RCMR_CMP0_SHIFT (0U) |
| #define ENET_RCMR_CMP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK) |
| #define ENET_RCMR_CMP1_MASK (0x70U) |
| #define ENET_RCMR_CMP1_SHIFT (4U) |
| #define ENET_RCMR_CMP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK) |
| #define ENET_RCMR_CMP2_MASK (0x700U) |
| #define ENET_RCMR_CMP2_SHIFT (8U) |
| #define ENET_RCMR_CMP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK) |
| #define ENET_RCMR_CMP3_MASK (0x7000U) |
| #define ENET_RCMR_CMP3_SHIFT (12U) |
| #define ENET_RCMR_CMP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK) |
| #define ENET_RCMR_MATCHEN_MASK (0x10000U) |
| #define ENET_RCMR_MATCHEN_SHIFT (16U) |
| /*! MATCHEN - Match Enable |
| * 0b0..Disabled (default): no compares will occur and the classification indicator for this class will never assert. |
| * 0b1..The register contents are valid and a comparison with all compare values is done when a VLAN frame is received. |
| */ |
| #define ENET_RCMR_MATCHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK) |
| /*! @} */ |
| |
| /* The count of ENET_RCMR */ |
| #define ENET_RCMR_COUNT (2U) |
| |
| /*! @name DMACFG - DMA Class Based Configuration */ |
| /*! @{ */ |
| #define ENET_DMACFG_IDLE_SLOPE_MASK (0xFFFFU) |
| #define ENET_DMACFG_IDLE_SLOPE_SHIFT (0U) |
| #define ENET_DMACFG_IDLE_SLOPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK) |
| #define ENET_DMACFG_DMA_CLASS_EN_MASK (0x10000U) |
| #define ENET_DMACFG_DMA_CLASS_EN_SHIFT (16U) |
| /*! DMA_CLASS_EN - DMA class enable |
| * 0b0..The DMA controller's channel for the class is not used. Disabling the DMA controller of a class also requires disabling the class match comparator for the class (see registers RCMRn). When class 1 and class 2 queues are disabled then their frames will be placed in queue 0. |
| * 0b1..Enable the DMA controller to support the corresponding descriptor ring for this class of traffic. |
| */ |
| #define ENET_DMACFG_DMA_CLASS_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK) |
| #define ENET_DMACFG_CALC_NOIPG_MASK (0x20000U) |
| #define ENET_DMACFG_CALC_NOIPG_SHIFT (17U) |
| /*! CALC_NOIPG - Calculate no IPG |
| * 0b0..The traffic shaper function should consider 12 octets of IPG in addition to the frame data transferred for a frame when doing bandwidth calculations. This is the default. |
| * 0b1..Addition of 12 bytes for the IPG should be omitted when calculating the bandwidth (for traffic shaping, when writing a frame into the transmit FIFO, the shaper will usually consider 12 bytes of IPG for every frame as part of the bandwidth allocated by the frame. This addition can be suppressed, meaning short frames will become more bandwidth than large frames due to the relation of data to IPG overhead). |
| */ |
| #define ENET_DMACFG_CALC_NOIPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK) |
| /*! @} */ |
| |
| /* The count of ENET_DMACFG */ |
| #define ENET_DMACFG_COUNT (2U) |
| |
| /*! @name RDAR1 - Receive Descriptor Active Register - Ring 1 */ |
| /*! @{ */ |
| #define ENET_RDAR1_RDAR_MASK (0x1000000U) |
| #define ENET_RDAR1_RDAR_SHIFT (24U) |
| #define ENET_RDAR1_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK) |
| /*! @} */ |
| |
| /*! @name TDAR1 - Transmit Descriptor Active Register - Ring 1 */ |
| /*! @{ */ |
| #define ENET_TDAR1_TDAR_MASK (0x1000000U) |
| #define ENET_TDAR1_TDAR_SHIFT (24U) |
| #define ENET_TDAR1_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK) |
| /*! @} */ |
| |
| /*! @name RDAR2 - Receive Descriptor Active Register - Ring 2 */ |
| /*! @{ */ |
| #define ENET_RDAR2_RDAR_MASK (0x1000000U) |
| #define ENET_RDAR2_RDAR_SHIFT (24U) |
| #define ENET_RDAR2_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK) |
| /*! @} */ |
| |
| /*! @name TDAR2 - Transmit Descriptor Active Register - Ring 2 */ |
| /*! @{ */ |
| #define ENET_TDAR2_TDAR_MASK (0x1000000U) |
| #define ENET_TDAR2_TDAR_SHIFT (24U) |
| #define ENET_TDAR2_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR2_TDAR_SHIFT)) & ENET_TDAR2_TDAR_MASK) |
| /*! @} */ |
| |
| /*! @name QOS - QOS Scheme */ |
| /*! @{ */ |
| #define ENET_QOS_TX_SCHEME_MASK (0x7U) |
| #define ENET_QOS_TX_SCHEME_SHIFT (0U) |
| /*! TX_SCHEME - TX scheme configuration |
| * 0b000..Credit-based scheme |
| * 0b001..Round-robin scheme |
| */ |
| #define ENET_QOS_TX_SCHEME(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK) |
| #define ENET_QOS_RX_FLUSH0_MASK (0x8U) |
| #define ENET_QOS_RX_FLUSH0_SHIFT (3U) |
| /*! RX_FLUSH0 - RX Flush Ring 0 |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define ENET_QOS_RX_FLUSH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK) |
| #define ENET_QOS_RX_FLUSH1_MASK (0x10U) |
| #define ENET_QOS_RX_FLUSH1_SHIFT (4U) |
| /*! RX_FLUSH1 - RX Flush Ring 1 |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define ENET_QOS_RX_FLUSH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK) |
| #define ENET_QOS_RX_FLUSH2_MASK (0x20U) |
| #define ENET_QOS_RX_FLUSH2_SHIFT (5U) |
| /*! RX_FLUSH2 - RX Flush Ring 2 |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define ENET_QOS_RX_FLUSH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) |
| #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) |
| #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) |
| #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) |
| #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) |
| #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) |
| #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) |
| #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) |
| #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) |
| #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) |
| #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) |
| #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) |
| #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) |
| #define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) |
| #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) |
| #define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) |
| #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_T_COL - Tx Collision Count Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) |
| #define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) |
| #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) |
| #define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) |
| #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) |
| #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) |
| #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) |
| #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) |
| #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) |
| #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) |
| #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) |
| #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) |
| #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) |
| #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) |
| #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) |
| #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) |
| #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) |
| #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) |
| #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) |
| /*! @} */ |
| |
| /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ |
| /*! @{ */ |
| #define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) |
| #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) |
| #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ |
| /*! @{ */ |
| #define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) |
| #define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) |
| #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ |
| /*! @{ */ |
| #define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) |
| #define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) |
| #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ |
| /*! @{ */ |
| #define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) |
| #define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) |
| #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ |
| /*! @{ */ |
| #define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) |
| #define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) |
| #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ |
| /*! @{ */ |
| #define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) |
| #define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) |
| #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ |
| /*! @{ */ |
| #define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) |
| #define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) |
| #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ |
| /*! @{ */ |
| #define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) |
| #define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) |
| #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name IEEE_T_SQE - Reserved Statistic Register */ |
| /*! @{ */ |
| #define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU) |
| #define ENET_IEEE_T_SQE_COUNT_SHIFT (0U) |
| #define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ |
| /*! @{ */ |
| #define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) |
| #define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) |
| #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ |
| /*! @{ */ |
| #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) |
| #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) |
| #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) |
| #define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) |
| #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) |
| #define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) |
| #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) |
| #define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) |
| #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) |
| #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) |
| #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) |
| #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) |
| #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) |
| #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) |
| #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) |
| #define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) |
| #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) |
| #define ENET_RMON_R_JAB_COUNT_SHIFT (0U) |
| #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) |
| #define ENET_RMON_R_P64_COUNT_SHIFT (0U) |
| #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) |
| #define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) |
| #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) |
| #define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) |
| #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) |
| #define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) |
| #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) |
| #define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) |
| #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) |
| #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) |
| #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) |
| #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) |
| #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ |
| /*! @{ */ |
| #define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) |
| #define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) |
| #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ |
| /*! @{ */ |
| #define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) |
| #define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) |
| #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ |
| /*! @{ */ |
| #define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) |
| #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) |
| #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ |
| /*! @{ */ |
| #define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) |
| #define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) |
| #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ |
| /*! @{ */ |
| #define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) |
| #define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) |
| #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ |
| /*! @{ */ |
| #define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) |
| #define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) |
| #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ |
| /*! @{ */ |
| #define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) |
| #define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) |
| #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ |
| /*! @{ */ |
| #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) |
| #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) |
| #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name ATCR - Adjustable Timer Control Register */ |
| /*! @{ */ |
| #define ENET_ATCR_EN_MASK (0x1U) |
| #define ENET_ATCR_EN_SHIFT (0U) |
| /*! EN - Enable Timer |
| * 0b0..The timer stops at the current value. |
| * 0b1..The timer starts incrementing. |
| */ |
| #define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) |
| #define ENET_ATCR_OFFEN_MASK (0x4U) |
| #define ENET_ATCR_OFFEN_SHIFT (2U) |
| /*! OFFEN - Enable One-Shot Offset Event |
| * 0b0..Disable. |
| * 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field. |
| */ |
| #define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) |
| #define ENET_ATCR_OFFRST_MASK (0x8U) |
| #define ENET_ATCR_OFFRST_SHIFT (3U) |
| /*! OFFRST - Reset Timer On Offset Event |
| * 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. |
| * 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. |
| */ |
| #define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) |
| #define ENET_ATCR_PEREN_MASK (0x10U) |
| #define ENET_ATCR_PEREN_SHIFT (4U) |
| /*! PEREN - Enable Periodical Event |
| * 0b0..Disable. |
| * 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details. |
| */ |
| #define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) |
| #define ENET_ATCR_PINPER_MASK (0x80U) |
| #define ENET_ATCR_PINPER_SHIFT (7U) |
| /*! PINPER |
| * 0b0..Disable. |
| * 0b1..Enable. |
| */ |
| #define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) |
| #define ENET_ATCR_RESTART_MASK (0x200U) |
| #define ENET_ATCR_RESTART_SHIFT (9U) |
| #define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) |
| #define ENET_ATCR_CAPTURE_MASK (0x800U) |
| #define ENET_ATCR_CAPTURE_SHIFT (11U) |
| /*! CAPTURE - Capture Timer Value |
| * 0b0..No effect. |
| * 0b1..The current time is captured and can be read from the ATVR register. |
| */ |
| #define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) |
| #define ENET_ATCR_SLAVE_MASK (0x2000U) |
| #define ENET_ATCR_SLAVE_SHIFT (13U) |
| /*! SLAVE - Enable Timer Slave Mode |
| * 0b0..The timer is active and all configuration fields in this register are relevant. |
| * 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. |
| */ |
| #define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) |
| /*! @} */ |
| |
| /*! @name ATVR - Timer Value Register */ |
| /*! @{ */ |
| #define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) |
| #define ENET_ATVR_ATIME_SHIFT (0U) |
| #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) |
| /*! @} */ |
| |
| /*! @name ATOFF - Timer Offset Register */ |
| /*! @{ */ |
| #define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) |
| #define ENET_ATOFF_OFFSET_SHIFT (0U) |
| #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name ATPER - Timer Period Register */ |
| /*! @{ */ |
| #define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) |
| #define ENET_ATPER_PERIOD_SHIFT (0U) |
| #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) |
| /*! @} */ |
| |
| /*! @name ATCOR - Timer Correction Register */ |
| /*! @{ */ |
| #define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) |
| #define ENET_ATCOR_COR_SHIFT (0U) |
| #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) |
| /*! @} */ |
| |
| /*! @name ATINC - Time-Stamping Clock Period Register */ |
| /*! @{ */ |
| #define ENET_ATINC_INC_MASK (0x7FU) |
| #define ENET_ATINC_INC_SHIFT (0U) |
| #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) |
| #define ENET_ATINC_INC_CORR_MASK (0x7F00U) |
| #define ENET_ATINC_INC_CORR_SHIFT (8U) |
| #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) |
| /*! @} */ |
| |
| /*! @name ATSTMP - Timestamp of Last Transmitted Frame */ |
| /*! @{ */ |
| #define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) |
| #define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) |
| #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) |
| /*! @} */ |
| |
| /*! @name TGSR - Timer Global Status Register */ |
| /*! @{ */ |
| #define ENET_TGSR_TF0_MASK (0x1U) |
| #define ENET_TGSR_TF0_SHIFT (0U) |
| /*! TF0 - Copy Of Timer Flag For Channel 0 |
| * 0b0..Timer Flag for Channel 0 is clear |
| * 0b1..Timer Flag for Channel 0 is set |
| */ |
| #define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) |
| #define ENET_TGSR_TF1_MASK (0x2U) |
| #define ENET_TGSR_TF1_SHIFT (1U) |
| /*! TF1 - Copy Of Timer Flag For Channel 1 |
| * 0b0..Timer Flag for Channel 1 is clear |
| * 0b1..Timer Flag for Channel 1 is set |
| */ |
| #define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) |
| #define ENET_TGSR_TF2_MASK (0x4U) |
| #define ENET_TGSR_TF2_SHIFT (2U) |
| /*! TF2 - Copy Of Timer Flag For Channel 2 |
| * 0b0..Timer Flag for Channel 2 is clear |
| * 0b1..Timer Flag for Channel 2 is set |
| */ |
| #define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) |
| #define ENET_TGSR_TF3_MASK (0x8U) |
| #define ENET_TGSR_TF3_SHIFT (3U) |
| /*! TF3 - Copy Of Timer Flag For Channel 3 |
| * 0b0..Timer Flag for Channel 3 is clear |
| * 0b1..Timer Flag for Channel 3 is set |
| */ |
| #define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) |
| /*! @} */ |
| |
| /*! @name TCSR - Timer Control Status Register */ |
| /*! @{ */ |
| #define ENET_TCSR_TDRE_MASK (0x1U) |
| #define ENET_TCSR_TDRE_SHIFT (0U) |
| /*! TDRE - Timer DMA Request Enable |
| * 0b0..DMA request is disabled |
| * 0b1..DMA request is enabled |
| */ |
| #define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) |
| #define ENET_TCSR_TMODE_MASK (0x3CU) |
| #define ENET_TCSR_TMODE_SHIFT (2U) |
| /*! TMODE - Timer Mode |
| * 0b0000..Timer Channel is disabled. |
| * 0b0001..Timer Channel is configured for Input Capture on rising edge. |
| * 0b0010..Timer Channel is configured for Input Capture on falling edge. |
| * 0b0011..Timer Channel is configured for Input Capture on both edges. |
| * 0b0100..Timer Channel is configured for Output Compare - software only. |
| * 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. |
| * 0b0110..Timer Channel is configured for Output Compare - clear output on compare. |
| * 0b0111..Timer Channel is configured for Output Compare - set output on compare. |
| * 0b1000..Reserved |
| * 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. |
| * 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. |
| * 0b110x..Reserved |
| * 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. |
| * 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle. |
| */ |
| #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) |
| #define ENET_TCSR_TIE_MASK (0x40U) |
| #define ENET_TCSR_TIE_SHIFT (6U) |
| /*! TIE - Timer Interrupt Enable |
| * 0b0..Interrupt is disabled |
| * 0b1..Interrupt is enabled |
| */ |
| #define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) |
| #define ENET_TCSR_TF_MASK (0x80U) |
| #define ENET_TCSR_TF_SHIFT (7U) |
| /*! TF - Timer Flag |
| * 0b0..Input Capture or Output Compare has not occurred. |
| * 0b1..Input Capture or Output Compare has occurred. |
| */ |
| #define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) |
| /*! @} */ |
| |
| /* The count of ENET_TCSR */ |
| #define ENET_TCSR_COUNT (4U) |
| |
| /*! @name TCCR - Timer Compare Capture Register */ |
| /*! @{ */ |
| #define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) |
| #define ENET_TCCR_TCC_SHIFT (0U) |
| #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) |
| /*! @} */ |
| |
| /* The count of ENET_TCCR */ |
| #define ENET_TCCR_COUNT (4U) |
| |
| |
| /*! |
| * @} |
| */ /* end of group ENET_Register_Masks */ |
| |
| |
| /* ENET - Peripheral instance base addresses */ |
| /** Peripheral ENET base address */ |
| #define ENET_BASE (0x30BE0000u) |
| /** Peripheral ENET base pointer */ |
| #define ENET ((ENET_Type *)ENET_BASE) |
| /** Array initializer of ENET peripheral base addresses */ |
| #define ENET_BASE_ADDRS { ENET_BASE } |
| /** Array initializer of ENET peripheral base pointers */ |
| #define ENET_BASE_PTRS { ENET } |
| /** Interrupt vectors for the ENET peripheral type */ |
| #define ENET_Transmit_IRQS { ENET_IRQn } |
| #define ENET_Receive_IRQS { ENET_IRQn } |
| #define ENET_Error_IRQS { ENET_IRQn } |
| #define ENET_1588_Timer_IRQS { ENET_IRQn } |
| /* ENET Buffer Descriptor and Buffer Address Alignment. */ |
| #define ENET_BUFF_ALIGNMENT (64U) |
| |
| |
| /*! |
| * @} |
| */ /* end of group ENET_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** GPC - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t LPCR_A53_BSC; /**< Basic Low power control register of A53 platform, offset: 0x0 */ |
| __IO uint32_t LPCR_A53_AD; /**< Advanced Low power control register of A53 platform, offset: 0x4 */ |
| __IO uint32_t LPCR_M4; /**< Low power control register of CPU1, offset: 0x8 */ |
| uint8_t RESERVED_0[8]; |
| __IO uint32_t SLPCR; /**< System low power control register, offset: 0x14 */ |
| __IO uint32_t MST_CPU_MAPPING; /**< MASTER LPM Handshake, offset: 0x18 */ |
| uint8_t RESERVED_1[4]; |
| __IO uint32_t MLPCR; /**< Memory low power control register, offset: 0x20 */ |
| __IO uint32_t PGC_ACK_SEL_A53; /**< PGC acknowledge signal selection of A53 platform, offset: 0x24 */ |
| __IO uint32_t PGC_ACK_SEL_M4; /**< PGC acknowledge signal selection of M4 platform, offset: 0x28 */ |
| __IO uint32_t MISC; /**< GPC Miscellaneous register, offset: 0x2C */ |
| __IO uint32_t IMR_CORE0_A53[4]; /**< IRQ masking register 1 of A53 core0..IRQ masking register 4 of A53 core0, array offset: 0x30, array step: 0x4 */ |
| __IO uint32_t IMR_CORE1_A53[4]; /**< IRQ masking register 1 of A53 core1..IRQ masking register 4 of A53 core1, array offset: 0x40, array step: 0x4 */ |
| __IO uint32_t IMR_M4[4]; /**< IRQ masking register 1 of M4..IRQ masking register 4 of M4, array offset: 0x50, array step: 0x4 */ |
| uint8_t RESERVED_2[16]; |
| __I uint32_t ISR_A53[4]; /**< IRQ status register 1 of A53..IRQ status register 4 of A53, array offset: 0x70, array step: 0x4 */ |
| __I uint32_t ISR_M4[4]; /**< IRQ status register 1 of M4..IRQ status register 4 of M4, array offset: 0x80, array step: 0x4 */ |
| uint8_t RESERVED_3[32]; |
| __IO uint32_t SLT0_CFG; /**< Slot configure register for A53 core, offset: 0xB0 */ |
| __IO uint32_t SLT1_CFG; /**< Slot configure register for A53 core, offset: 0xB4 */ |
| __IO uint32_t SLT2_CFG; /**< Slot configure register for A53 core, offset: 0xB8 */ |
| __IO uint32_t SLT3_CFG; /**< Slot configure register for A53 core, offset: 0xBC */ |
| __IO uint32_t SLT4_CFG; /**< Slot configure register for A53 core, offset: 0xC0 */ |
| __IO uint32_t SLT5_CFG; /**< Slot configure register for A53 core, offset: 0xC4 */ |
| __IO uint32_t SLT6_CFG; /**< Slot configure register for A53 core, offset: 0xC8 */ |
| __IO uint32_t SLT7_CFG; /**< Slot configure register for A53 core, offset: 0xCC */ |
| __IO uint32_t SLT8_CFG; /**< Slot configure register for A53 core, offset: 0xD0 */ |
| __IO uint32_t SLT9_CFG; /**< Slot configure register for A53 core, offset: 0xD4 */ |
| __IO uint32_t SLT10_CFG; /**< Slot configure register for A53 core, offset: 0xD8 */ |
| __IO uint32_t SLT11_CFG; /**< Slot configure register for A53 core, offset: 0xDC */ |
| __IO uint32_t SLT12_CFG; /**< Slot configure register for A53 core, offset: 0xE0 */ |
| __IO uint32_t SLT13_CFG; /**< Slot configure register for A53 core, offset: 0xE4 */ |
| __IO uint32_t SLT14_CFG; /**< Slot configure register for A53 core, offset: 0xE8 */ |
| __IO uint32_t PGC_CPU_0_1_MAPPING; /**< PGC CPU mapping, offset: 0xEC */ |
| __IO uint32_t CPU_PGC_SW_PUP_REQ; /**< CPU PGC software power up trigger, offset: 0xF0 */ |
| __IO uint32_t MIX_PGC_SW_PUP_REQ; /**< MIX PGC software power up trigger, offset: 0xF4 */ |
| __IO uint32_t PU_PGC_SW_PUP_REQ; /**< PU PGC software up trigger, offset: 0xF8 */ |
| __IO uint32_t CPU_PGC_SW_PDN_REQ; /**< CPU PGC software down trigger, offset: 0xFC */ |
| __IO uint32_t MIX_PGC_SW_PDN_REQ; /**< MIX PGC software power down trigger, offset: 0x100 */ |
| __IO uint32_t PU_PGC_SW_PDN_REQ; /**< PU PGC software down trigger, offset: 0x104 */ |
| __IO uint32_t LPCR_A53_BSC2; /**< Basic Low power control register of A53 platform, offset: 0x108 */ |
| uint8_t RESERVED_4[36]; |
| __I uint32_t CPU_PGC_PUP_STATUS1; /**< CPU PGC software up trigger status1, offset: 0x130 */ |
| __I uint32_t A53_MIX_PGC_PUP_STATUS[3]; /**< A53 MIX software up trigger status register, array offset: 0x134, array step: 0x4 */ |
| __I uint32_t M4_MIX_PGC_PUP_STATUS[3]; /**< M4 MIX PGC software up trigger status register, array offset: 0x140, array step: 0x4 */ |
| __I uint32_t A53_PU_PGC_PUP_STATUS[3]; /**< A53 PU software up trigger status register, array offset: 0x14C, array step: 0x4 */ |
| __I uint32_t M4_PU_PGC_PUP_STATUS[3]; /**< M4 PU PGC software up trigger status register, array offset: 0x158, array step: 0x4 */ |
| uint8_t RESERVED_5[12]; |
| __IO uint32_t CPU_PGC_PDN_STATUS1; /**< CPU PGC software dn trigger status1, offset: 0x170 */ |
| __I uint32_t A53_MIX_PGC_PDN_STATUS[3]; /**< A53 MIX software down trigger status register, array offset: 0x174, array step: 0x4 */ |
| __I uint32_t M4_MIX_PGC_PDN_STATUS[3]; /**< M4 MIX PGC software power down trigger status register, array offset: 0x180, array step: 0x4 */ |
| __I uint32_t A53_PU_PGC_PDN_STATUS[3]; /**< A53 PU PGC software down trigger status, array offset: 0x18C, array step: 0x4 */ |
| __I uint32_t M4_PU_PGC_PDN_STATUS[3]; /**< M4 PU PGC software down trigger status, array offset: 0x198, array step: 0x4 */ |
| uint8_t RESERVED_6[12]; |
| __IO uint32_t A53_MIX_PDN_FLG; /**< A53 MIX PDN FLG, offset: 0x1B0 */ |
| __IO uint32_t A53_PU_PDN_FLG; /**< A53 PU PDN FLG, offset: 0x1B4 */ |
| __IO uint32_t M4_MIX_PDN_FLG; /**< M4 MIX PDN FLG, offset: 0x1B8 */ |
| __IO uint32_t M4_PU_PDN_FLG; /**< M4 PU PDN FLG, offset: 0x1BC */ |
| __IO uint32_t IMR_CORE2_A53[4]; /**< IRQ masking register 1 of A53 core2..IRQ masking register 4 of A53 core2, array offset: 0x1C0, array step: 0x4 */ |
| __IO uint32_t IMR_CORE3_A53[4]; /**< IRQ masking register 1 of A53 core3..IRQ masking register 4 of A53 core3, array offset: 0x1D0, array step: 0x4 */ |
| __IO uint32_t ACK_SEL_A53_PU; /**< PGC acknowledge signal selection of A53 platform for PUs, offset: 0x1E0 */ |
| __IO uint32_t ACK_SEL_M4_PU; /**< PGC acknowledge signal selection of M4 platform for PUs, offset: 0x1E4 */ |
| __IO uint32_t SLT15_CFG; /**< Slot configure register for A53 core, offset: 0x1E8 */ |
| __IO uint32_t SLT16_CFG; /**< Slot configure register for A53 core, offset: 0x1EC */ |
| __IO uint32_t SLT17_CFG; /**< Slot configure register for A53 core, offset: 0x1F0 */ |
| __IO uint32_t SLT18_CFG; /**< Slot configure register for A53 core, offset: 0x1F4 */ |
| __IO uint32_t SLT19_CFG; /**< Slot configure register for A53 core, offset: 0x1F8 */ |
| __IO uint32_t PU_PWRHSK; /**< Power handshake register, offset: 0x1FC */ |
| __IO uint32_t SLT_CFG_PU[20]; /**< Slot configure register for PUs, array offset: 0x200, array step: 0x4 */ |
| } GPC_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPC_Register_Masks GPC Register Masks |
| * @{ |
| */ |
| |
| /*! @name LPCR_A53_BSC - Basic Low power control register of A53 platform */ |
| /*! @{ */ |
| #define GPC_LPCR_A53_BSC_LPM0_MASK (0x3U) |
| #define GPC_LPCR_A53_BSC_LPM0_SHIFT (0U) |
| /*! LPM0 |
| * 0b00..Remain in RUN mode |
| * 0b01..Transfer to WAIT mode |
| * 0b10..Transfer to STOP mode |
| * 0b11..Reserved |
| */ |
| #define GPC_LPCR_A53_BSC_LPM0(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_LPM0_SHIFT)) & GPC_LPCR_A53_BSC_LPM0_MASK) |
| #define GPC_LPCR_A53_BSC_LPM1_MASK (0xCU) |
| #define GPC_LPCR_A53_BSC_LPM1_SHIFT (2U) |
| /*! LPM1 |
| * 0b00..Remain in RUN mode |
| * 0b01..Transfer to WAIT mode |
| * 0b10..Transfer to STOP mode |
| * 0b11..Reserved |
| */ |
| #define GPC_LPCR_A53_BSC_LPM1(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_LPM1_SHIFT)) & GPC_LPCR_A53_BSC_LPM1_MASK) |
| #define GPC_LPCR_A53_BSC_MST_LPM_HSK_MASK_MASK (0x40U) |
| #define GPC_LPCR_A53_BSC_MST_LPM_HSK_MASK_SHIFT (6U) |
| /*! MST_LPM_HSK_MASK - MASTER0 LPM handshake mask |
| * 0b0..enable MASTER0 LPM handshake, wait ACK from MASTER0 |
| * 0b1..disable MASKTER0 LPM handshake, mask ACK from MASTER0 |
| */ |
| #define GPC_LPCR_A53_BSC_MST_LPM_HSK_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MST_LPM_HSK_MASK_SHIFT)) & GPC_LPCR_A53_BSC_MST_LPM_HSK_MASK_MASK) |
| #define GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_MASK (0x4000U) |
| #define GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_SHIFT (14U) |
| /*! CPU_CLK_ON_LPM |
| * 0b0..A53 clock disabled on wait/stop mode |
| * 0b1..A53 clock enabled on wait/stop mode |
| */ |
| #define GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_SHIFT)) & GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_MASK) |
| #define GPC_LPCR_A53_BSC_MASK_CORE0_WFI_MASK (0x10000U) |
| #define GPC_LPCR_A53_BSC_MASK_CORE0_WFI_SHIFT (16U) |
| /*! MASK_CORE0_WFI |
| * 0b0..WFI for CORE0 is not masked |
| * 0b1..WFI for CORE0 is masked |
| */ |
| #define GPC_LPCR_A53_BSC_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE0_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE0_WFI_MASK) |
| #define GPC_LPCR_A53_BSC_MASK_CORE1_WFI_MASK (0x20000U) |
| #define GPC_LPCR_A53_BSC_MASK_CORE1_WFI_SHIFT (17U) |
| /*! MASK_CORE1_WFI |
| * 0b0..WFI for CORE1 is not masked |
| * 0b1..WFI for CORE1 is masked |
| */ |
| #define GPC_LPCR_A53_BSC_MASK_CORE1_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE1_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE1_WFI_MASK) |
| #define GPC_LPCR_A53_BSC_MASK_CORE2_WFI_MASK (0x40000U) |
| #define GPC_LPCR_A53_BSC_MASK_CORE2_WFI_SHIFT (18U) |
| /*! MASK_CORE2_WFI |
| * 0b0..WFI for CORE2 is not masked |
| * 0b1..WFI for CORE2 is masked |
| */ |
| #define GPC_LPCR_A53_BSC_MASK_CORE2_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE2_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE2_WFI_MASK) |
| #define GPC_LPCR_A53_BSC_MASK_CORE3_WFI_MASK (0x80000U) |
| #define GPC_LPCR_A53_BSC_MASK_CORE3_WFI_SHIFT (19U) |
| /*! MASK_CORE3_WFI |
| * 0b0..WFI for CORE3 is not masked |
| * 0b1..WFI for CORE3 is masked |
| */ |
| #define GPC_LPCR_A53_BSC_MASK_CORE3_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE3_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE3_WFI_MASK) |
| #define GPC_LPCR_A53_BSC_IRQ_SRC_C2_MASK (0x400000U) |
| #define GPC_LPCR_A53_BSC_IRQ_SRC_C2_SHIFT (22U) |
| /*! IRQ_SRC_C2 |
| * 0b0..core2 wakeup source from external INT[127:0], masked by IMR1. See Power Up Process for A53 Platform for more specific information. |
| * 0b1..core2 wakeup source from external GIC(nFIQ[1]/nIRQ[1]), SCU should not be powered down during low power mode when this bit is set to 1'b1. |
| */ |
| #define GPC_LPCR_A53_BSC_IRQ_SRC_C2(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C2_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C2_MASK) |
| #define GPC_LPCR_A53_BSC_IRQ_SRC_C3_MASK (0x800000U) |
| #define GPC_LPCR_A53_BSC_IRQ_SRC_C3_SHIFT (23U) |
| /*! IRQ_SRC_C3 |
| * 0b0..core3 wakeup source from external INT[127:0], masked by IMR1. See Power Up Process for A53 Platform for more specific information. |
| * 0b1..core3 wakeup source from external GIC(nFIQ[1]/nIRQ[1]), SCU should not be powered down during low power mode when this bit is set to 1'b1. |
| */ |
| #define GPC_LPCR_A53_BSC_IRQ_SRC_C3(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C3_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C3_MASK) |
| #define GPC_LPCR_A53_BSC_MASK_SCU_WFI_MASK (0x1000000U) |
| #define GPC_LPCR_A53_BSC_MASK_SCU_WFI_SHIFT (24U) |
| /*! MASK_SCU_WFI |
| * 0b0..WFI for SCU is not masked |
| * 0b1..WFI for SCU is masked |
| */ |
| #define GPC_LPCR_A53_BSC_MASK_SCU_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_SCU_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_SCU_WFI_MASK) |
| #define GPC_LPCR_A53_BSC_MASK_L2CC_WFI_MASK (0x4000000U) |
| #define GPC_LPCR_A53_BSC_MASK_L2CC_WFI_SHIFT (26U) |
| /*! MASK_L2CC_WFI |
| * 0b0..WFI for L2 cache controller is not masked |
| * 0b1..WFI for L2 cache controller is masked |
| */ |
| #define GPC_LPCR_A53_BSC_MASK_L2CC_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_L2CC_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_L2CC_WFI_MASK) |
| #define GPC_LPCR_A53_BSC_IRQ_SRC_C0_MASK (0x10000000U) |
| #define GPC_LPCR_A53_BSC_IRQ_SRC_C0_SHIFT (28U) |
| /*! IRQ_SRC_C0 |
| * 0b0..core0 wakeup source from external INT[127:0], masked by IMR0 refer to "Power up process for A53 platform" for more specific information |
| * 0b1..core0 wakeup source from GIC(nFIQ[0]/nIRQ[0] ), SCU should not be power down during low power mode when this bit is set to 1'b1 |
| */ |
| #define GPC_LPCR_A53_BSC_IRQ_SRC_C0(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C0_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C0_MASK) |
| #define GPC_LPCR_A53_BSC_IRQ_SRC_C1_MASK (0x20000000U) |
| #define GPC_LPCR_A53_BSC_IRQ_SRC_C1_SHIFT (29U) |
| /*! IRQ_SRC_C1 |
| * 0b0..core1 wakeup source from external INT[127:0], masked by IMR1 refer to "Power up process for A53 platform" for more specific information |
| * 0b1..core1 wakeup source from GIC(nFIQ[1]/nIRQ[1] ), SCU should not be power down during low power mode when this bit is set to 1'b1 |
| */ |
| #define GPC_LPCR_A53_BSC_IRQ_SRC_C1(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C1_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C1_MASK) |
| #define GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_MASK (0x40000000U) |
| #define GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_SHIFT (30U) |
| /*! IRQ_SRC_A53_WUP |
| * 0b0..LPM wakeup source be "OR" result of LPCR_A53_BSC[IRQ_SRC_C0]/LPCR_A53_BSC[IRQ_SRC_C1]/LPCR_A53_BSC[IRQ_SRC_C2]/LPCR_A53_BSC[IRQ_SRC_C3] setting |
| * 0b1..LPM wakeup source from external INT[127:0], masked by IMR0 |
| */ |
| #define GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_MASK) |
| #define GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_MASK (0x80000000U) |
| #define GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_SHIFT (31U) |
| /*! MASK_DSM_TRIGGER |
| * 0b0..DSM trigger of A53 platform will not be masked |
| * 0b1..DSM trigger of A53 platform will be masked |
| */ |
| #define GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_SHIFT)) & GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_MASK) |
| /*! @} */ |
| |
| /*! @name LPCR_A53_AD - Advanced Low power control register of A53 platform */ |
| /*! @{ */ |
| #define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_MASK (0x1U) |
| #define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_SHIFT (0U) |
| /*! EN_C0_WFI_PDN |
| * 0b0..CORE0 will not be power down with WFI request |
| * 0b1..CORE0 will be power down with WFI request |
| */ |
| #define GPC_LPCR_A53_AD_EN_C0_WFI_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_WFI_PDN_MASK) |
| #define GPC_LPCR_A53_AD_EN_C0_PDN_MASK (0x2U) |
| #define GPC_LPCR_A53_AD_EN_C0_PDN_SHIFT (1U) |
| /*! EN_C0_PDN |
| * 0b0..CORE0 will not be power down with low power mode request |
| * 0b1..CORE0 will be power down with low power mode request |
| */ |
| #define GPC_LPCR_A53_AD_EN_C0_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_PDN_MASK) |
| #define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_MASK (0x4U) |
| #define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_SHIFT (2U) |
| /*! EN_C1_WFI_PDN |
| * 0b0..CORE1 will not be power down with WFI request |
| * 0b1..CORE1 will be power down with WFI request |
| */ |
| #define GPC_LPCR_A53_AD_EN_C1_WFI_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_WFI_PDN_MASK) |
| #define GPC_LPCR_A53_AD_EN_C1_PDN_MASK (0x8U) |
| #define GPC_LPCR_A53_AD_EN_C1_PDN_SHIFT (3U) |
| /*! EN_C1_PDN |
| * 0b0..CORE1 will not be power down with low power mode request |
| * 0b1..CORE1 will be power down with low power mode request |
| */ |
| #define GPC_LPCR_A53_AD_EN_C1_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_PDN_MASK) |
| #define GPC_LPCR_A53_AD_EN_PLAT_PDN_MASK (0x10U) |
| #define GPC_LPCR_A53_AD_EN_PLAT_PDN_SHIFT (4U) |
| /*! EN_PLAT_PDN |
| * 0b0..SCU and L2 cache RAM will not be power down with low power mode request |
| * 0b1..SCU and L2 cache RAM will be power down with low power mode request |
| */ |
| #define GPC_LPCR_A53_AD_EN_PLAT_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_PLAT_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_PLAT_PDN_MASK) |
| #define GPC_LPCR_A53_AD_EN_L2_WFI_PDN_MASK (0x20U) |
| #define GPC_LPCR_A53_AD_EN_L2_WFI_PDN_SHIFT (5U) |
| /*! EN_L2_WFI_PDN |
| * 0b0..SCU and L2 will not be power down with WFI request |
| * 0b1..SCU and L2 will be power down with WFI request (default) |
| */ |
| #define GPC_LPCR_A53_AD_EN_L2_WFI_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_L2_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_L2_WFI_PDN_MASK) |
| #define GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_MASK (0x100U) |
| #define GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_SHIFT (8U) |
| /*! EN_C0_IRQ_PUP |
| * 0b0..CORE0 will power up with IRQ request |
| * 0b1..CORE0 will not power up with IRQ request |
| */ |
| #define GPC_LPCR_A53_AD_EN_C0_IRQ_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_MASK) |
| #define GPC_LPCR_A53_AD_EN_C0_PUP_MASK (0x200U) |
| #define GPC_LPCR_A53_AD_EN_C0_PUP_SHIFT (9U) |
| /*! EN_C0_PUP |
| * 0b0..CORE0 will power up with low power mode request |
| * 0b1..CORE0 will not power up with low power mode request |
| */ |
| #define GPC_LPCR_A53_AD_EN_C0_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_PUP_MASK) |
| #define GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_MASK (0x400U) |
| #define GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_SHIFT (10U) |
| /*! EN_C1_IRQ_PUP |
| * 0b0..CORE1 will power up with IRQ request |
| * 0b1..CORE1 will not power up with IRQ request |
| */ |
| #define GPC_LPCR_A53_AD_EN_C1_IRQ_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_MASK) |
| #define GPC_LPCR_A53_AD_EN_C1_PUP_MASK (0x800U) |
| #define GPC_LPCR_A53_AD_EN_C1_PUP_SHIFT (11U) |
| /*! EN_C1_PUP |
| * 0b0..CORE1 will not power up with low power mode request (only used wake up from CPU01_OFF mode) |
| * 0b1..CORE1 will power up with low power mode request |
| */ |
| #define GPC_LPCR_A53_AD_EN_C1_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_PUP_MASK) |
| #define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_MASK (0x10000U) |
| #define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_SHIFT (16U) |
| /*! EN_C2_WFI_PDN |
| * 0b0..CORE2 will not be power down with WFI request |
| * 0b1..CORE2 will be power down with WFI request |
| */ |
| #define GPC_LPCR_A53_AD_EN_C2_WFI_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_WFI_PDN_MASK) |
| #define GPC_LPCR_A53_AD_EN_C2_PDN_MASK (0x20000U) |
| #define GPC_LPCR_A53_AD_EN_C2_PDN_SHIFT (17U) |
| /*! EN_C2_PDN |
| * 0b0..CORE2 will not be power down with low power mode request |
| * 0b1..CORE2 will be power down with low power mode request |
| */ |
| #define GPC_LPCR_A53_AD_EN_C2_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_PDN_MASK) |
| #define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_MASK (0x40000U) |
| #define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_SHIFT (18U) |
| /*! EN_C3_WFI_PDN |
| * 0b0..CORE3 will not be power down with WFI request |
| * 0b1..CORE3 will be power down with WFI request |
| */ |
| #define GPC_LPCR_A53_AD_EN_C3_WFI_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_WFI_PDN_MASK) |
| #define GPC_LPCR_A53_AD_EN_C3_PDN_MASK (0x80000U) |
| #define GPC_LPCR_A53_AD_EN_C3_PDN_SHIFT (19U) |
| /*! EN_C3_PDN |
| * 0b0..CORE3 will not be power down with low power mode request |
| * 0b1..CORE3 will be power down with low power mode request |
| */ |
| #define GPC_LPCR_A53_AD_EN_C3_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_PDN_MASK) |
| #define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS_MASK (0x100000U) |
| #define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS_SHIFT (20U) |
| /*! EN_C0_WFI_PDN_DIS |
| * 0b0..Disnable WFI power down core0 |
| * 0b1..Enable WFI power down core0 |
| */ |
| #define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS_MASK) |
| #define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS_MASK (0x200000U) |
| #define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS_SHIFT (21U) |
| /*! EN_C1_WFI_PDN_DIS |
| * 0b0..Disnable WFI power down core1 |
| * 0b1..Enable WFI power down core1 |
| */ |
| #define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS_MASK) |
| #define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS_MASK (0x400000U) |
| #define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS_SHIFT (22U) |
| /*! EN_C2_WFI_PDN_DIS |
| * 0b0..Disnable WFI power down core2 |
| * 0b1..Enable WFI power down core2 |
| */ |
| #define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS_MASK) |
| #define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS_MASK (0x800000U) |
| #define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS_SHIFT (23U) |
| /*! EN_C3_WFI_PDN_DIS |
| * 0b0..Disnable WFI power down core3 |
| * 0b1..Enable WFI power down core3 |
| */ |
| #define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS_MASK) |
| #define GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_MASK (0x1000000U) |
| #define GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_SHIFT (24U) |
| /*! EN_C2_IRQ_PUP |
| * 0b0..CORE2 will power up with IRQ request |
| * 0b1..CORE2 will not power up with IRQ request |
| */ |
| #define GPC_LPCR_A53_AD_EN_C2_IRQ_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_MASK) |
| #define GPC_LPCR_A53_AD_EN_C2_PUP_MASK (0x2000000U) |
| #define GPC_LPCR_A53_AD_EN_C2_PUP_SHIFT (25U) |
| /*! EN_C2_PUP |
| * 0b0..CORE2 will power up with lower power mode request |
| * 0b1..CORE2 will not power up with low power mode request (only used wake up from CPU_OFF) |
| */ |
| #define GPC_LPCR_A53_AD_EN_C2_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_PUP_MASK) |
| #define GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_MASK (0x4000000U) |
| #define GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_SHIFT (26U) |
| /*! EN_C3_IRQ_PUP |
| * 0b0..CORE3 will power up with IRQ request |
| * 0b1..CORE3 will not power up with IRQ request |
| */ |
| #define GPC_LPCR_A53_AD_EN_C3_IRQ_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_MASK) |
| #define GPC_LPCR_A53_AD_EN_C3_PUP_MASK (0x8000000U) |
| #define GPC_LPCR_A53_AD_EN_C3_PUP_SHIFT (27U) |
| /*! EN_C3_PUP |
| * 0b0..CORE3 will power up with lower power mode request |
| * 0b1..CORE3 will not power up with low power mode request (only used wake up from CPU_OFF) |
| */ |
| #define GPC_LPCR_A53_AD_EN_C3_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_PUP_MASK) |
| #define GPC_LPCR_A53_AD_L2PGE_MASK (0x80000000U) |
| #define GPC_LPCR_A53_AD_L2PGE_SHIFT (31U) |
| /*! L2PGE |
| * 0b0..L2 cache RAM will power down with SCU power domain in A53 platform (used for ALL_OFF mode) |
| * 0b1..L2 cache RAM will not power down with SCU power domain in A53 platform (used for ALL_OFF mode) |
| */ |
| #define GPC_LPCR_A53_AD_L2PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_L2PGE_SHIFT)) & GPC_LPCR_A53_AD_L2PGE_MASK) |
| /*! @} */ |
| |
| /*! @name LPCR_M4 - Low power control register of CPU1 */ |
| /*! @{ */ |
| #define GPC_LPCR_M4_LPM0_MASK (0x3U) |
| #define GPC_LPCR_M4_LPM0_SHIFT (0U) |
| /*! LPM0 |
| * 0b00..Remain in RUN mode |
| * 0b01..Transfer to WAIT mode |
| * 0b10..Transfer to STOP mode |
| * 0b11..Reserved |
| */ |
| #define GPC_LPCR_M4_LPM0(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M4_LPM0_SHIFT)) & GPC_LPCR_M4_LPM0_MASK) |
| #define GPC_LPCR_M4_EN_M4_PDN_MASK (0x4U) |
| #define GPC_LPCR_M4_EN_M4_PDN_SHIFT (2U) |
| #define GPC_LPCR_M4_EN_M4_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M4_EN_M4_PDN_SHIFT)) & GPC_LPCR_M4_EN_M4_PDN_MASK) |
| #define GPC_LPCR_M4_EN_M4_PUP_MASK (0x8U) |
| #define GPC_LPCR_M4_EN_M4_PUP_SHIFT (3U) |
| #define GPC_LPCR_M4_EN_M4_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M4_EN_M4_PUP_SHIFT)) & GPC_LPCR_M4_EN_M4_PUP_MASK) |
| #define GPC_LPCR_M4_CPU_CLK_ON_LPM_MASK (0x4000U) |
| #define GPC_LPCR_M4_CPU_CLK_ON_LPM_SHIFT (14U) |
| /*! CPU_CLK_ON_LPM |
| * 0b0..M4 clock disabled on wait/stop mode. |
| * 0b1..M4 clock enabled on wait/stop mode. |
| */ |
| #define GPC_LPCR_M4_CPU_CLK_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M4_CPU_CLK_ON_LPM_SHIFT)) & GPC_LPCR_M4_CPU_CLK_ON_LPM_MASK) |
| #define GPC_LPCR_M4_MASK_M4_WFI_MASK (0x10000U) |
| #define GPC_LPCR_M4_MASK_M4_WFI_SHIFT (16U) |
| /*! MASK_M4_WFI |
| * 0b0..WFI for M4 is not masked |
| * 0b1..WFI for M4 is masked |
| */ |
| #define GPC_LPCR_M4_MASK_M4_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M4_MASK_M4_WFI_SHIFT)) & GPC_LPCR_M4_MASK_M4_WFI_MASK) |
| #define GPC_LPCR_M4_MASK_DSM_TRIGGER_MASK (0x80000000U) |
| #define GPC_LPCR_M4_MASK_DSM_TRIGGER_SHIFT (31U) |
| /*! MASK_DSM_TRIGGER |
| * 0b0..DSM trigger of M4 platform will not be masked |
| * 0b1..DSM trigger of M4 platform will be masked |
| */ |
| #define GPC_LPCR_M4_MASK_DSM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M4_MASK_DSM_TRIGGER_SHIFT)) & GPC_LPCR_M4_MASK_DSM_TRIGGER_MASK) |
| /*! @} */ |
| |
| /*! @name SLPCR - System low power control register */ |
| /*! @{ */ |
| #define GPC_SLPCR_BYPASS_PMIC_READY_MASK (0x1U) |
| #define GPC_SLPCR_BYPASS_PMIC_READY_SHIFT (0U) |
| /*! BYPASS_PMIC_READY |
| * 0b0..Don't bypass the PMIC_READY signal - GPC will wait for its assertion during exit of low power mode if standby voltage was enabled |
| * 0b1..Bypass the PMIC_READY signal - GPC will wait for its assertion during exit of low power mode if standby voltage was enabled |
| */ |
| #define GPC_SLPCR_BYPASS_PMIC_READY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_BYPASS_PMIC_READY_SHIFT)) & GPC_SLPCR_BYPASS_PMIC_READY_MASK) |
| #define GPC_SLPCR_SBYOS_MASK (0x2U) |
| #define GPC_SLPCR_SBYOS_SHIFT (1U) |
| /*! SBYOS |
| * 0b0..On chip oscillator will not be powered down, after next entrance to DSM. |
| * 0b1..On chip oscillator will be powered down, after next entrance to DSM. When returning from DSM, external oscillator will be enabled again, on chip oscillator will return to oscillator mode , and after oscnt count GPC will continue with the exit from DSM process. |
| */ |
| #define GPC_SLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_SBYOS_SHIFT)) & GPC_SLPCR_SBYOS_MASK) |
| #define GPC_SLPCR_VSTBY_MASK (0x4U) |
| #define GPC_SLPCR_VSTBY_SHIFT (2U) |
| /*! VSTBY |
| * 0b0..Voltage will not be changed to standby voltage after next entrance to stop mode. (PMIC_STBY_REQ will remain negated - '0') |
| * 0b1..Voltage will be changed to standby voltage after next entrance to stop mode. |
| */ |
| #define GPC_SLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_VSTBY_SHIFT)) & GPC_SLPCR_VSTBY_MASK) |
| #define GPC_SLPCR_STBY_COUNT_MASK (0x38U) |
| #define GPC_SLPCR_STBY_COUNT_SHIFT (3U) |
| /*! STBY_COUNT |
| * 0b000..GPC will wait 4 ckil clock cycles |
| * 0b001..GPC will wait 8 ckil clock cycles |
| * 0b010..GPC will wait 16 ckil clock cycles |
| * 0b011..GPC will wait 32 ckil clock cycles |
| * 0b100..GPC will wait 64 ckil clock cycles |
| * 0b101..GPC will wait 128 ckil clock cycles |
| * 0b110..GPC will wait 256 ckil clock cycles |
| * 0b111..GPC will wait 512 ckil clock cycles |
| */ |
| #define GPC_SLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_STBY_COUNT_SHIFT)) & GPC_SLPCR_STBY_COUNT_MASK) |
| #define GPC_SLPCR_COSC_PWRDOWN_MASK (0x40U) |
| #define GPC_SLPCR_COSC_PWRDOWN_SHIFT (6U) |
| /*! COSC_PWRDOWN |
| * 0b0..On-chip oscillator will not be powered down, i.e. cosc_pwrdown = 0 |
| * 0b1..On-chip oscillator will be powered down, i.e. cosc_pwrdown = 1 |
| */ |
| #define GPC_SLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_COSC_PWRDOWN_SHIFT)) & GPC_SLPCR_COSC_PWRDOWN_MASK) |
| #define GPC_SLPCR_COSC_EN_MASK (0x80U) |
| #define GPC_SLPCR_COSC_EN_SHIFT (7U) |
| /*! COSC_EN |
| * 0b0..Disable on-chip oscillator |
| * 0b1..Enable on-chip oscillator |
| */ |
| #define GPC_SLPCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_COSC_EN_SHIFT)) & GPC_SLPCR_COSC_EN_MASK) |
| #define GPC_SLPCR_OSCCNT_MASK (0xFF00U) |
| #define GPC_SLPCR_OSCCNT_SHIFT (8U) |
| /*! OSCCNT |
| * 0b00000000..count 1 ckil |
| * 0b11111111..count 256 ckils |
| */ |
| #define GPC_SLPCR_OSCCNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_OSCCNT_SHIFT)) & GPC_SLPCR_OSCCNT_MASK) |
| #define GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_MASK (0x10000U) |
| #define GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_SHIFT (16U) |
| #define GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_SHIFT)) & GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_MASK) |
| #define GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_MASK (0x20000U) |
| #define GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_SHIFT (17U) |
| #define GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_SHIFT)) & GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_MASK) |
| #define GPC_SLPCR_EN_M4_FASTWUP_WAIT_MODE_MASK (0x40000U) |
| #define GPC_SLPCR_EN_M4_FASTWUP_WAIT_MODE_SHIFT (18U) |
| #define GPC_SLPCR_EN_M4_FASTWUP_WAIT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_M4_FASTWUP_WAIT_MODE_SHIFT)) & GPC_SLPCR_EN_M4_FASTWUP_WAIT_MODE_MASK) |
| #define GPC_SLPCR_EN_M4_FASTWUP_STOP_MODE_MASK (0x80000U) |
| #define GPC_SLPCR_EN_M4_FASTWUP_STOP_MODE_SHIFT (19U) |
| #define GPC_SLPCR_EN_M4_FASTWUP_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_M4_FASTWUP_STOP_MODE_SHIFT)) & GPC_SLPCR_EN_M4_FASTWUP_STOP_MODE_MASK) |
| #define GPC_SLPCR_DISABLE_A53_IS_DSM_MASK (0x800000U) |
| #define GPC_SLPCR_DISABLE_A53_IS_DSM_SHIFT (23U) |
| /*! DISABLE_A53_IS_DSM |
| * 0b0..Enable A53 isolation signal in DSM |
| * 0b1..Disable A53 isolation signal in DSM |
| */ |
| #define GPC_SLPCR_DISABLE_A53_IS_DSM(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_DISABLE_A53_IS_DSM_SHIFT)) & GPC_SLPCR_DISABLE_A53_IS_DSM_MASK) |
| #define GPC_SLPCR_REG_BYPASS_COUNT_MASK (0x3F000000U) |
| #define GPC_SLPCR_REG_BYPASS_COUNT_SHIFT (24U) |
| /*! REG_BYPASS_COUNT |
| * 0b000000..no delay |
| * 0b000001..1 CKIL clock period delay |
| * 0b111111..63 CKIL clock period delay |
| */ |
| #define GPC_SLPCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_REG_BYPASS_COUNT_SHIFT)) & GPC_SLPCR_REG_BYPASS_COUNT_MASK) |
| #define GPC_SLPCR_RBC_EN_MASK (0x40000000U) |
| #define GPC_SLPCR_RBC_EN_SHIFT (30U) |
| /*! RBC_EN |
| * 0b0..REG_BYPASS_COUNTER disabled |
| * 0b1..REG_BYPASS_COUNTER enabled |
| */ |
| #define GPC_SLPCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_RBC_EN_SHIFT)) & GPC_SLPCR_RBC_EN_MASK) |
| #define GPC_SLPCR_EN_DSM_MASK (0x80000000U) |
| #define GPC_SLPCR_EN_DSM_SHIFT (31U) |
| /*! EN_DSM |
| * 0b0..DSM disabled |
| * 0b1..DSM enabled |
| */ |
| #define GPC_SLPCR_EN_DSM(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_DSM_SHIFT)) & GPC_SLPCR_EN_DSM_MASK) |
| /*! @} */ |
| |
| /*! @name MST_CPU_MAPPING - MASTER LPM Handshake */ |
| /*! @{ */ |
| #define GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_MASK (0x1U) |
| #define GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_SHIFT (0U) |
| /*! MST0_CPU_MAPPING - MASTER0 CPU Mapping |
| * 0b0..GPC will not send out power off requirement |
| * 0b1..GPC will send out power off requirement |
| */ |
| #define GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_SHIFT)) & GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_MASK) |
| #define GPC_MST_CPU_MAPPING_MEMLP_RET_PGEN_MASK (0xFFFFFFFEU) |
| #define GPC_MST_CPU_MAPPING_MEMLP_RET_PGEN_SHIFT (1U) |
| #define GPC_MST_CPU_MAPPING_MEMLP_RET_PGEN(x) (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MEMLP_RET_PGEN_SHIFT)) & GPC_MST_CPU_MAPPING_MEMLP_RET_PGEN_MASK) |
| /*! @} */ |
| |
| /*! @name MLPCR - Memory low power control register */ |
| /*! @{ */ |
| #define GPC_MLPCR_MEMLP_CTL_DIS_MASK (0x1U) |
| #define GPC_MLPCR_MEMLP_CTL_DIS_SHIFT (0U) |
| /*! MEMLP_CTL_DIS |
| * 0b0..Enable RAM low power control |
| * 0b1..Disable RAM low power control |
| */ |
| #define GPC_MLPCR_MEMLP_CTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_CTL_DIS_SHIFT)) & GPC_MLPCR_MEMLP_CTL_DIS_MASK) |
| #define GPC_MLPCR_MEMLP_RET_SEL_MASK (0x2U) |
| #define GPC_MLPCR_MEMLP_RET_SEL_SHIFT (1U) |
| /*! MEMLP_RET_SEL |
| * 0b0..retention mode 2 |
| * 0b1..retention mode 1 |
| */ |
| #define GPC_MLPCR_MEMLP_RET_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_RET_SEL_SHIFT)) & GPC_MLPCR_MEMLP_RET_SEL_MASK) |
| #define GPC_MLPCR_ROMLP_PDN_DIS_MASK (0x4U) |
| #define GPC_MLPCR_ROMLP_PDN_DIS_SHIFT (2U) |
| /*! ROMLP_PDN_DIS |
| * 0b0..Enable ROM shut down control(should also enable RAM low power control); |
| * 0b1..Disable ROM shut down control |
| */ |
| #define GPC_MLPCR_ROMLP_PDN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_ROMLP_PDN_DIS_SHIFT)) & GPC_MLPCR_ROMLP_PDN_DIS_MASK) |
| #define GPC_MLPCR_MEMLP_ENT_CNT_MASK (0xFF00U) |
| #define GPC_MLPCR_MEMLP_ENT_CNT_SHIFT (8U) |
| #define GPC_MLPCR_MEMLP_ENT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_ENT_CNT_SHIFT)) & GPC_MLPCR_MEMLP_ENT_CNT_MASK) |
| #define GPC_MLPCR_MEM_EXT_CNT_MASK (0xFF0000U) |
| #define GPC_MLPCR_MEM_EXT_CNT_SHIFT (16U) |
| #define GPC_MLPCR_MEM_EXT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEM_EXT_CNT_SHIFT)) & GPC_MLPCR_MEM_EXT_CNT_MASK) |
| #define GPC_MLPCR_MEMLP_RET_PGEN_MASK (0xFF000000U) |
| #define GPC_MLPCR_MEMLP_RET_PGEN_SHIFT (24U) |
| #define GPC_MLPCR_MEMLP_RET_PGEN(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_RET_PGEN_SHIFT)) & GPC_MLPCR_MEMLP_RET_PGEN_MASK) |
| /*! @} */ |
| |
| /*! @name PGC_ACK_SEL_A53 - PGC acknowledge signal selection of A53 platform */ |
| /*! @{ */ |
| #define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_MASK (0x1U) |
| #define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_SHIFT (0U) |
| #define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_MASK) |
| #define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_MASK (0x2U) |
| #define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_SHIFT (1U) |
| #define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_MASK) |
| #define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_MASK (0x4U) |
| #define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_SHIFT (2U) |
| #define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_MASK) |
| #define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_MASK (0x2000U) |
| #define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_SHIFT (13U) |
| #define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_MASK) |
| #define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_MASK (0x4000U) |
| #define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_SHIFT (14U) |
| #define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_MASK) |
| #define GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_MASK (0x8000U) |
| #define GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_SHIFT (15U) |
| #define GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_MASK) |
| #define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_MASK (0x10000U) |
| #define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_SHIFT (16U) |
| #define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_MASK) |
| #define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_MASK (0x20000U) |
| #define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_SHIFT (17U) |
| #define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_MASK) |
| #define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_MASK (0x40000U) |
| #define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_SHIFT (18U) |
| #define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_MASK) |
| #define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_MASK (0x20000000U) |
| #define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_SHIFT (29U) |
| #define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_MASK) |
| #define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_MASK (0x40000000U) |
| #define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_SHIFT (30U) |
| #define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_MASK) |
| #define GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_MASK (0x80000000U) |
| #define GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_SHIFT (31U) |
| #define GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_MASK) |
| /*! @} */ |
| |
| /*! @name PGC_ACK_SEL_M4 - PGC acknowledge signal selection of M4 platform */ |
| /*! @{ */ |
| #define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PDN_ACK_MASK (0x1U) |
| #define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PDN_ACK_SHIFT (0U) |
| #define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PDN_ACK_MASK) |
| #define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK_MASK (0x8000U) |
| #define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK_SHIFT (15U) |
| #define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK_MASK) |
| #define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PUP_ACK_MASK (0x10000U) |
| #define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PUP_ACK_SHIFT (16U) |
| #define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PUP_ACK_MASK) |
| #define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK_MASK (0x80000000U) |
| #define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK_SHIFT (31U) |
| #define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK_MASK) |
| /*! @} */ |
| |
| /*! @name MISC - GPC Miscellaneous register */ |
| /*! @{ */ |
| #define GPC_MISC_M4_SLEEP_HOLD_REQ_B_MASK (0x1U) |
| #define GPC_MISC_M4_SLEEP_HOLD_REQ_B_SHIFT (0U) |
| /*! M4_SLEEP_HOLD_REQ_B |
| * 0b0..Hold M4 platform in sleep mode. This bit is a software control bit to M4 platform. |
| * 0b1..Don't hold M4 platform in sleep mode. |
| */ |
| #define GPC_MISC_M4_SLEEP_HOLD_REQ_B(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_M4_SLEEP_HOLD_REQ_B_SHIFT)) & GPC_MISC_M4_SLEEP_HOLD_REQ_B_MASK) |
| #define GPC_MISC_A53_SLEEP_HOLD_REQ_B_MASK (0x2U) |
| #define GPC_MISC_A53_SLEEP_HOLD_REQ_B_SHIFT (1U) |
| /*! A53_SLEEP_HOLD_REQ_B |
| * 0b0..Hold A53 platform in sleep mode. This bit is a software control bit to A53 platform. |
| * 0b1..Don't hold A53 platform in sleep mode. |
| */ |
| #define GPC_MISC_A53_SLEEP_HOLD_REQ_B(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_A53_SLEEP_HOLD_REQ_B_SHIFT)) & GPC_MISC_A53_SLEEP_HOLD_REQ_B_MASK) |
| #define GPC_MISC_GPC_IRQ_MASK_MASK (0x20U) |
| #define GPC_MISC_GPC_IRQ_MASK_SHIFT (5U) |
| /*! GPC_IRQ_MASK |
| * 0b0..Not masked |
| * 0b1..Interrupt / event is masked |
| */ |
| #define GPC_MISC_GPC_IRQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_GPC_IRQ_MASK_SHIFT)) & GPC_MISC_GPC_IRQ_MASK_MASK) |
| #define GPC_MISC_M4_PDN_REQ_MASK_MASK (0x100U) |
| #define GPC_MISC_M4_PDN_REQ_MASK_SHIFT (8U) |
| /*! M4_PDN_REQ_MASK |
| * 0b0..M4 power down request to virtual M4 PGC will be masked. |
| * 0b1..M4 power down request to virtual M4 PGC will not be masked. Set this bit to 1'b1 when M4 virtual PGC is used. |
| */ |
| #define GPC_MISC_M4_PDN_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_M4_PDN_REQ_MASK_SHIFT)) & GPC_MISC_M4_PDN_REQ_MASK_MASK) |
| #define GPC_MISC_A53_BYPASS_PUP_MASK_MASK (0x1000000U) |
| #define GPC_MISC_A53_BYPASS_PUP_MASK_SHIFT (24U) |
| #define GPC_MISC_A53_BYPASS_PUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_A53_BYPASS_PUP_MASK_SHIFT)) & GPC_MISC_A53_BYPASS_PUP_MASK_MASK) |
| #define GPC_MISC_M4_BYPASS_PUP_MASK_MASK (0x2000000U) |
| #define GPC_MISC_M4_BYPASS_PUP_MASK_SHIFT (25U) |
| #define GPC_MISC_M4_BYPASS_PUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_M4_BYPASS_PUP_MASK_SHIFT)) & GPC_MISC_M4_BYPASS_PUP_MASK_MASK) |
| /*! @} */ |
| |
| /*! @name IMR_CORE0_A53 - IRQ masking register 1 of A53 core0..IRQ masking register 4 of A53 core0 */ |
| /*! @{ */ |
| #define GPC_IMR_CORE0_A53_IMR1_CORE0_A53_MASK (0xFFFFFFFFU) |
| #define GPC_IMR_CORE0_A53_IMR1_CORE0_A53_SHIFT (0U) |
| /*! IMR1_CORE0_A53 |
| * 0b00000000000000000000000000000000..IRQ not masked |
| * 0b00000000000000000000000000000001..IRQ masked |
| */ |
| #define GPC_IMR_CORE0_A53_IMR1_CORE0_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR1_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR1_CORE0_A53_MASK) |
| #define GPC_IMR_CORE0_A53_IMR2_CORE0_A53_MASK (0xFFFFFFFFU) |
| #define GPC_IMR_CORE0_A53_IMR2_CORE0_A53_SHIFT (0U) |
| /*! IMR2_CORE0_A53 |
| * 0b00000000000000000000000000000000..IRQ not masked |
| * 0b00000000000000000000000000000001..IRQ masked |
| */ |
| #define GPC_IMR_CORE0_A53_IMR2_CORE0_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR2_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR2_CORE0_A53_MASK) |
| #define GPC_IMR_CORE0_A53_IMR3_CORE0_A53_MASK (0xFFFFFFFFU) |
| #define GPC_IMR_CORE0_A53_IMR3_CORE0_A53_SHIFT (0U) |
| /*! IMR3_CORE0_A53 |
| * 0b00000000000000000000000000000000..IRQ not masked |
| * 0b00000000000000000000000000000001..IRQ masked |
| */ |
| #define GPC_IMR_CORE0_A53_IMR3_CORE0_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR3_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR3_CORE0_A53_MASK) |
| #define GPC_IMR_CORE0_A53_IMR4_CORE0_A53_MASK (0xFFFFFFFFU) |
| #define GPC_IMR_CORE0_A53_IMR4_CORE0_A53_SHIFT (0U) |
| /*! IMR4_CORE0_A53 |
| * 0b00000000000000000000000000000000..IRQ not masked |
| * 0b00000000000000000000000000000001..IRQ masked |
| */ |
| #define GPC_IMR_CORE0_A53_IMR4_CORE0_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR4_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR4_CORE0_A53_MASK) |
| /*! @} */ |
| |
| /* The count of GPC_IMR_CORE0_A53 */ |
| #define GPC_IMR_CORE0_A53_COUNT (4U) |
| |
| /*! @name IMR_CORE1_A53 - IRQ masking register 1 of A53 core1..IRQ masking register 4 of A53 core1 */ |
| /*! @{ */ |
| #define GPC_IMR_CORE1_A53_IMR1_CORE1_A53_MASK (0xFFFFFFFFU) |
| #define GPC_IMR_CORE1_A53_IMR1_CORE1_A53_SHIFT (0U) |
| /*! IMR1_CORE1_A53 |
| * 0b00000000000000000000000000000000..IRQ not masked |
| * 0b00000000000000000000000000000001..IRQ masked |
| */ |
| #define GPC_IMR_CORE1_A53_IMR1_CORE1_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR1_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR1_CORE1_A53_MASK) |
| #define GPC_IMR_CORE1_A53_IMR2_CORE1_A53_MASK (0xFFFFFFFFU) |
| #define GPC_IMR_CORE1_A53_IMR2_CORE1_A53_SHIFT (0U) |
| /*! IMR2_CORE1_A53 |
| * 0b00000000000000000000000000000000..IRQ not masked |
| * 0b00000000000000000000000000000001..IRQ masked |
| */ |
| #define GPC_IMR_CORE1_A53_IMR2_CORE1_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR2_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR2_CORE1_A53_MASK) |
| #define GPC_IMR_CORE1_A53_IMR3_CORE1_A53_MASK (0xFFFFFFFFU) |
| #define GPC_IMR_CORE1_A53_IMR3_CORE1_A53_SHIFT (0U) |
| /*! IMR3_CORE1_A53 |
| * 0b00000000000000000000000000000000..IRQ not masked |
| * 0b00000000000000000000000000000001..IRQ masked |
| */ |
| #define GPC_IMR_CORE1_A53_IMR3_CORE1_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR3_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR3_CORE1_A53_MASK) |
| #define GPC_IMR_CORE1_A53_IMR4_CORE1_A53_MASK (0xFFFFFFFFU) |
| #define GPC_IMR_CORE1_A53_IMR4_CORE1_A53_SHIFT (0U) |
| /*! IMR4_CORE1_A53 |
| * 0b00000000000000000000000000000000..IRQ not masked |
| * 0b00000000000000000000000000000001..IRQ masked |
| */ |
| #define GPC_IMR_CORE1_A53_IMR4_CORE1_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR4_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR4_CORE1_A53_MASK) |
| /*! @} */ |
| |
| /* The count of GPC_IMR_CORE1_A53 */ |
| #define GPC_IMR_CORE1_A53_COUNT (4U) |
| |
| /*! @name IMR_M4 - IRQ masking register 1 of M4..IRQ masking register 4 of M4 */ |
| /*! @{ */ |
| #define GPC_IMR_M4_IMR1_M4_MASK (0xFFFFFFFFU) |
| #define GPC_IMR_M4_IMR1_M4_SHIFT (0U) |
| /*! IMR1_M4 |
| * 0b00000000000000000000000000000000..IRQ not masked |
| * 0b00000000000000000000000000000001..IRQ masked |
| */ |
| #define GPC_IMR_M4_IMR1_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M4_IMR1_M4_SHIFT)) & GPC_IMR_M4_IMR1_M4_MASK) |
| #define GPC_IMR_M4_IMR2_M4_MASK (0xFFFFFFFFU) |
| #define GPC_IMR_M4_IMR2_M4_SHIFT (0U) |
| /*! IMR2_M4 |
| * 0b00000000000000000000000000000000..IRQ not masked |
| * 0b00000000000000000000000000000001..IRQ masked |
| */ |
| #define GPC_IMR_M4_IMR2_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M4_IMR2_M4_SHIFT)) & GPC_IMR_M4_IMR2_M4_MASK) |
| #define GPC_IMR_M4_IMR3_M4_MASK (0xFFFFFFFFU) |
| #define GPC_IMR_M4_IMR3_M4_SHIFT (0U) |
| /*! IMR3_M4 |
| * 0b00000000000000000000000000000000..IRQ not masked |
| * 0b00000000000000000000000000000001..IRQ masked |
| */ |
| #define GPC_IMR_M4_IMR3_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M4_IMR3_M4_SHIFT)) & GPC_IMR_M4_IMR3_M4_MASK) |
| #define GPC_IMR_M4_IMR4_M4_MASK (0xFFFFFFFFU) |
| #define GPC_IMR_M4_IMR4_M4_SHIFT (0U) |
| /*! IMR4_M4 |
| * 0b00000000000000000000000000000000..IRQ not masked |
| * 0b00000000000000000000000000000001..IRQ masked |
| */ |
| #define GPC_IMR_M4_IMR4_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M4_IMR4_M4_SHIFT)) & GPC_IMR_M4_IMR4_M4_MASK) |
| /*! @} */ |
| |
| /* The count of GPC_IMR_M4 */ |
| #define GPC_IMR_M4_COUNT (4U) |
| |
| /*! @name ISR_A53 - IRQ status register 1 of A53..IRQ status register 4 of A53 */ |
| /*! @{ */ |
| #define GPC_ISR_A53_ISR1_A53_MASK (0xFFFFFFFFU) |
| #define GPC_ISR_A53_ISR1_A53_SHIFT (0U) |
| #define GPC_ISR_A53_ISR1_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR1_A53_SHIFT)) & GPC_ISR_A53_ISR1_A53_MASK) |
| #define GPC_ISR_A53_ISR2_A53_MASK (0xFFFFFFFFU) |
| #define GPC_ISR_A53_ISR2_A53_SHIFT (0U) |
| #define GPC_ISR_A53_ISR2_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR2_A53_SHIFT)) & GPC_ISR_A53_ISR2_A53_MASK) |
| #define GPC_ISR_A53_ISR3_A53_MASK (0xFFFFFFFFU) |
| #define GPC_ISR_A53_ISR3_A53_SHIFT (0U) |
| #define GPC_ISR_A53_ISR3_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR3_A53_SHIFT)) & GPC_ISR_A53_ISR3_A53_MASK) |
| #define GPC_ISR_A53_ISR4_A53_MASK (0xFFFFFFFFU) |
| #define GPC_ISR_A53_ISR4_A53_SHIFT (0U) |
| #define GPC_ISR_A53_ISR4_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR4_A53_SHIFT)) & GPC_ISR_A53_ISR4_A53_MASK) |
| /*! @} */ |
| |
| /* The count of GPC_ISR_A53 */ |
| #define GPC_ISR_A53_COUNT (4U) |
| |
| /*! @name ISR_M4 - IRQ status register 1 of M4..IRQ status register 4 of M4 */ |
| /*! @{ */ |
| #define GPC_ISR_M4_ISR1_M4_MASK (0xFFFFFFFFU) |
| #define GPC_ISR_M4_ISR1_M4_SHIFT (0U) |
| #define GPC_ISR_M4_ISR1_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M4_ISR1_M4_SHIFT)) & GPC_ISR_M4_ISR1_M4_MASK) |
| #define GPC_ISR_M4_ISR2_M4_MASK (0xFFFFFFFFU) |
| #define GPC_ISR_M4_ISR2_M4_SHIFT (0U) |
| #define GPC_ISR_M4_ISR2_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M4_ISR2_M4_SHIFT)) & GPC_ISR_M4_ISR2_M4_MASK) |
| #define GPC_ISR_M4_ISR3_M4_MASK (0xFFFFFFFFU) |
| #define GPC_ISR_M4_ISR3_M4_SHIFT (0U) |
| #define GPC_ISR_M4_ISR3_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M4_ISR3_M4_SHIFT)) & GPC_ISR_M4_ISR3_M4_MASK) |
| #define GPC_ISR_M4_ISR4_M4_MASK (0xFFFFFFFFU) |
| #define GPC_ISR_M4_ISR4_M4_SHIFT (0U) |
| #define GPC_ISR_M4_ISR4_M4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M4_ISR4_M4_SHIFT)) & GPC_ISR_M4_ISR4_M4_MASK) |
| /*! @} */ |
| |
| /* The count of GPC_ISR_M4 */ |
| #define GPC_ISR_M4_COUNT (4U) |
| |
| /*! @name SLT0_CFG - Slot configure register for A53 core */ |
| /*! @{ */ |
| #define GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) |
| #define GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) |
| #define GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) |
| #define GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) |
| #define GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) |
| #define GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) |
| #define GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) |
| #define GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) |
| #define GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) |
| #define GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) |
| #define GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) |
| #define GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) |
| #define GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) |
| #define GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) |
| #define GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) |
| #define GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) |
| #define GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) |
| #define GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) |
| #define GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) |
| #define GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) |
| #define GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL_MASK) |
| /*! @} */ |
| |
| /*! @name SLT1_CFG - Slot configure register for A53 core */ |
| /*! @{ */ |
| #define GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) |
| #define GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) |
| #define GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) |
| #define GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) |
| #define GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) |
| #define GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) |
| #define GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) |
| #define GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) |
| #define GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) |
| #define GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) |
| #define GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) |
| #define GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) |
| #define GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) |
| #define GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) |
| #define GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) |
| #define GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) |
| #define GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) |
| #define GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) |
| #define GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) |
| #define GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) |
| #define GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL_MASK) |
| /*! @} */ |
| |
| /*! @name SLT2_CFG - Slot configure register for A53 core */ |
| /*! @{ */ |
| #define GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) |
| #define GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) |
| #define GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) |
| #define GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) |
| #define GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) |
| #define GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) |
| #define GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) |
| #define GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) |
| #define GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) |
| #define GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) |
| #define GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) |
| #define GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) |
| #define GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) |
| #define GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) |
| #define GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) |
| #define GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) |
| #define GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) |
| #define GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) |
| #define GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) |
| #define GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) |
| #define GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL_MASK) |
| /*! @} */ |
| |
| /*! @name SLT3_CFG - Slot configure register for A53 core */ |
| /*! @{ */ |
| #define GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) |
| #define GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) |
| #define GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) |
| #define GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) |
| #define GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) |
| #define GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) |
| #define GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) |
| #define GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) |
| #define GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) |
| #define GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) |
| #define GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) |
| #define GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) |
| #define GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) |
| #define GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) |
| #define GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) |
| #define GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) |
| #define GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) |
| #define GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) |
| #define GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) |
| #define GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) |
| #define GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL_MASK) |
| /*! @} */ |
| |
| /*! @name SLT4_CFG - Slot configure register for A53 core */ |
| /*! @{ */ |
| #define GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) |
| #define GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) |
| #define GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) |
| #define GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) |
| #define GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) |
| #define GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) |
| #define GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) |
| #define GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) |
| #define GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) |
| #define GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) |
| #define GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) |
| #define GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) |
| #define GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) |
| #define GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) |
| #define GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) |
| #define GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) |
| #define GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) |
| #define GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) |
| #define GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) |
| #define GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) |
| #define GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL_MASK) |
| /*! @} */ |
| |
| /*! @name SLT5_CFG - Slot configure register for A53 core */ |
| /*! @{ */ |
| #define GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) |
| #define GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) |
| #define GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) |
| #define GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) |
| #define GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) |
| #define GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) |
| #define GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) |
| #define GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) |
| #define GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) |
| #define GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) |
| #define GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) |
| #define GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) |
| #define GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) |
| #define GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) |
| #define GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) |
| #define GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) |
| #define GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) |
| #define GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) |
| #define GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) |
| #define GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) |
| #define GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL_MASK) |
| /*! @} */ |
| |
| /*! @name SLT6_CFG - Slot configure register for A53 core */ |
| /*! @{ */ |
| #define GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) |
| #define GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) |
| #define GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) |
| #define GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) |
| #define GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) |
| #define GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) |
| #define GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) |
| #define GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) |
| #define GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) |
| #define GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) |
| #define GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) |
| #define GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) |
| #define GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) |
| #define GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) |
| #define GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) |
| #define GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) |
| #define GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) |
| #define GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) |
| #define GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) |
| #define GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) |
| #define GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL_MASK) |
| /*! @} */ |
| |
| /*! @name SLT7_CFG - Slot configure register for A53 core */ |
| /*! @{ */ |
| #define GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) |
| #define GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) |
| #define GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) |
| #define GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) |
| #define GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) |
| #define GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) |
| #define GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) |
| #define GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) |
| #define GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) |
| #define GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) |
| #define GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) |
| #define GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) |
| #define GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) |
| #define GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) |
| #define GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) |
| #define GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) |
| #define GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) |
| #define GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) |
| #define GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) |
| #define GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) |
| #define GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL_MASK) |
| /*! @} */ |
| |
| /*! @name SLT8_CFG - Slot configure register for A53 core */ |
| /*! @{ */ |
| #define GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) |
| #define GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) |
| #define GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) |
| #define GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) |
| #define GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) |
| #define GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) |
| #define GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) |
| #define GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) |
| #define GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) |
| #define GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) |
| #define GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) |
| #define GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) |
| #define GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) |
| #define GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) |
| #define GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) |
| #define GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) |
| #define GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) |
| #define GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) |
| #define GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) |
| #define GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) |
| #define GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL_MASK) |
| /*! @} */ |
| |
| /*! @name SLT9_CFG - Slot configure register for A53 core */ |
| /*! @{ */ |
| #define GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) |
| #define GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) |
| #define GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) |
| #define GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) |
| #define GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) |
| #define GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) |
| #define GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) |
| #define GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) |
| #define GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) |
| #define GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) |
| #define GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) |
| #define GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) |
| #define GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) |
| #define GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) |
| #define GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) |
| #define GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) |
| #define GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) |
| #define GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) |
| #define GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) |
| #define GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) |
| #define GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL_MASK) |
| /*! @} */ |
| |
| /*! @name SLT10_CFG - Slot configure register for A53 core */ |
| /*! @{ */ |
| #define GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) |
| #define GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) |
| #define GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) |
| #define GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) |
| #define GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) |
| #define GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) |
| #define GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) |
| #define GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) |
| #define GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) |
| #define GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) |
| #define GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) |
| #define GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) |
| #define GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) |
| #define GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) |
| #define GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) |
| #define GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) |
| #define GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) |
| #define GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) |
| #define GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) |
| #define GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) |
| #define GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL_MASK) |
| /*! @} */ |
| |
| /*! @name SLT11_CFG - Slot configure register for A53 core */ |
| /*! @{ */ |
| #define GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) |
| #define GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) |
| #define GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) |
| #define GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) |
| #define GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) |
| #define GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) |
| #define GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) |
| #define GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) |
| #define GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) |
| #define GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) |
| #define GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) |
| #define GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) |
| #define GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) |
| #define GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) |
| #define GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) |
| #define GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) |
| #define GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) |
| #define GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) |
| #define GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) |
| #define GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) |
| #define GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL_MASK) |
| /*! @} */ |
| |
| /*! @name SLT12_CFG - Slot configure register for A53 core */ |
| /*! @{ */ |
| #define GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) |
| #define GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) |
| #define GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) |
| #define GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) |
| #define GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) |
| #define GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) |
| #define GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) |
| #define GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) |
| #define GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) |
| #define GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) |
| #define GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) |
| #define GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) |
| #define GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) |
| #define GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) |
| #define GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) |
| #define GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) |
| #define GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) |
| #define GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) |
| #define GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) |
| #define GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) |
| #define GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL_MASK) |
| /*! @} */ |
| |
| /*! @name SLT13_CFG - Slot configure register for A53 core */ |
| /*! @{ */ |
| #define GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) |
| #define GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) |
| #define GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) |
| #define GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) |
| #define GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) |
| #define GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) |
| #define GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) |
| #define GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) |
| #define GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) |
| #define GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) |
| #define GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) |
| #define GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) |
| #define GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) |
| #define GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) |
| #define GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) |
| #define GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) |
| #define GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) |
| #define GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) |
| #define GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) |
| #define GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) |
| #define GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL_MASK) |
| /*! @} */ |
| |
| /*! @name SLT14_CFG - Slot configure register for A53 core */ |
| /*! @{ */ |
| #define GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) |
| #define GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) |
| #define GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) |
| #define GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) |
| #define GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) |
| #define GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) |
| #define GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) |
| #define GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) |
| #define GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) |
| #define GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) |
| #define GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) |
| #define GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) |
| #define GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) |
| #define GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) |
| #define GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) |
| #define GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) |
| #define GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) |
| #define GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) |
| #define GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) |
| #define GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) |
| #define GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL_MASK) |
| /*! @} */ |
| |
| /*! @name PGC_CPU_0_1_MAPPING - PGC CPU mapping */ |
| /*! @{ */ |
| #define GPC_PGC_CPU_0_1_MAPPING_MF_A53_DOMAIN_MASK (0x1U) |
| #define GPC_PGC_CPU_0_1_MAPPING_MF_A53_DOMAIN_SHIFT (0U) |
| #define GPC_PGC_CPU_0_1_MAPPING_MF_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MF_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MF_A53_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN_MASK (0x4U) |
| #define GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN_SHIFT (2U) |
| #define GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_PCIE_A53_DOMAIN_MASK (0x8U) |
| #define GPC_PGC_CPU_0_1_MAPPING_PCIE_A53_DOMAIN_SHIFT (3U) |
| #define GPC_PGC_CPU_0_1_MAPPING_PCIE_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_PCIE_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_PCIE_A53_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN_MASK (0x10U) |
| #define GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN_SHIFT (4U) |
| #define GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_OTG2_A53_DOMAIN_MASK (0x20U) |
| #define GPC_PGC_CPU_0_1_MAPPING_OTG2_A53_DOMAIN_SHIFT (5U) |
| #define GPC_PGC_CPU_0_1_MAPPING_OTG2_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_OTG2_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_OTG2_A53_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN_MASK (0x80U) |
| #define GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN_SHIFT (7U) |
| #define GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_DDR2_A53_DOMAIN_MASK (0x100U) |
| #define GPC_PGC_CPU_0_1_MAPPING_DDR2_A53_DOMAIN_SHIFT (8U) |
| #define GPC_PGC_CPU_0_1_MAPPING_DDR2_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DDR2_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_DDR2_A53_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN_MASK (0x200U) |
| #define GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN_SHIFT (9U) |
| #define GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_VPU_A53_DOMAIN_MASK (0x400U) |
| #define GPC_PGC_CPU_0_1_MAPPING_VPU_A53_DOMAIN_SHIFT (10U) |
| #define GPC_PGC_CPU_0_1_MAPPING_VPU_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_VPU_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_VPU_A53_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_HDMI_A53_DOMAIN_MASK (0x800U) |
| #define GPC_PGC_CPU_0_1_MAPPING_HDMI_A53_DOMAIN_SHIFT (11U) |
| #define GPC_PGC_CPU_0_1_MAPPING_HDMI_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_HDMI_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_HDMI_A53_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_DISP_A53_DOMAIN_MASK (0x1000U) |
| #define GPC_PGC_CPU_0_1_MAPPING_DISP_A53_DOMAIN_SHIFT (12U) |
| #define GPC_PGC_CPU_0_1_MAPPING_DISP_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DISP_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_DISP_A53_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_A53_DOMAIN_MASK (0x2000U) |
| #define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_A53_DOMAIN_SHIFT (13U) |
| #define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_A53_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_A53_DOMAIN_MASK (0x4000U) |
| #define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_A53_DOMAIN_SHIFT (14U) |
| #define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_A53_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_PCIE2_A53_DOMAIN_MASK (0x8000U) |
| #define GPC_PGC_CPU_0_1_MAPPING_PCIE2_A53_DOMAIN_SHIFT (15U) |
| #define GPC_PGC_CPU_0_1_MAPPING_PCIE2_A53_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_PCIE2_A53_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_PCIE2_A53_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_MF_M4_DOMAIN_MASK (0x10000U) |
| #define GPC_PGC_CPU_0_1_MAPPING_MF_M4_DOMAIN_SHIFT (16U) |
| #define GPC_PGC_CPU_0_1_MAPPING_MF_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MF_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MF_M4_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_MIPI_M4_DOMAIN_MASK (0x40000U) |
| #define GPC_PGC_CPU_0_1_MAPPING_MIPI_M4_DOMAIN_SHIFT (18U) |
| #define GPC_PGC_CPU_0_1_MAPPING_MIPI_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MIPI_M4_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_PCIE_M4_DOMAIN_MASK (0x80000U) |
| #define GPC_PGC_CPU_0_1_MAPPING_PCIE_M4_DOMAIN_SHIFT (19U) |
| #define GPC_PGC_CPU_0_1_MAPPING_PCIE_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_PCIE_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_PCIE_M4_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_OTG1_M4_DOMAIN_MASK (0x100000U) |
| #define GPC_PGC_CPU_0_1_MAPPING_OTG1_M4_DOMAIN_SHIFT (20U) |
| #define GPC_PGC_CPU_0_1_MAPPING_OTG1_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_OTG1_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_OTG1_M4_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_OTG2_M4_DOMAIN_MASK (0x200000U) |
| #define GPC_PGC_CPU_0_1_MAPPING_OTG2_M4_DOMAIN_SHIFT (21U) |
| #define GPC_PGC_CPU_0_1_MAPPING_OTG2_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_OTG2_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_OTG2_M4_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_DDR1_M4_DOMAIN_MASK (0x800000U) |
| #define GPC_PGC_CPU_0_1_MAPPING_DDR1_M4_DOMAIN_SHIFT (23U) |
| #define GPC_PGC_CPU_0_1_MAPPING_DDR1_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DDR1_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_DDR1_M4_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_DDR2_M4_DOMAIN_MASK (0x1000000U) |
| #define GPC_PGC_CPU_0_1_MAPPING_DDR2_M4_DOMAIN_SHIFT (24U) |
| #define GPC_PGC_CPU_0_1_MAPPING_DDR2_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DDR2_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_DDR2_M4_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_GPU_M4_DOMAIN_MASK (0x2000000U) |
| #define GPC_PGC_CPU_0_1_MAPPING_GPU_M4_DOMAIN_SHIFT (25U) |
| #define GPC_PGC_CPU_0_1_MAPPING_GPU_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_GPU_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_GPU_M4_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_VPU_M4_DOMAIN_MASK (0x4000000U) |
| #define GPC_PGC_CPU_0_1_MAPPING_VPU_M4_DOMAIN_SHIFT (26U) |
| #define GPC_PGC_CPU_0_1_MAPPING_VPU_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_VPU_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_VPU_M4_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_HDMI_M4_DOMAIN_MASK (0x8000000U) |
| #define GPC_PGC_CPU_0_1_MAPPING_HDMI_M4_DOMAIN_SHIFT (27U) |
| #define GPC_PGC_CPU_0_1_MAPPING_HDMI_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_HDMI_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_HDMI_M4_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_DISP_M4_DOMAIN_MASK (0x10000000U) |
| #define GPC_PGC_CPU_0_1_MAPPING_DISP_M4_DOMAIN_SHIFT (28U) |
| #define GPC_PGC_CPU_0_1_MAPPING_DISP_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DISP_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_DISP_M4_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_M4_DOMAIN_MASK (0x20000000U) |
| #define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_M4_DOMAIN_SHIFT (29U) |
| #define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI1_M4_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_M4_DOMAIN_MASK (0x40000000U) |
| #define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_M4_DOMAIN_SHIFT (30U) |
| #define GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_MIPI_CSI2_M4_DOMAIN_MASK) |
| #define GPC_PGC_CPU_0_1_MAPPING_PCIE2_M4_DOMAIN_MASK (0x80000000U) |
| #define GPC_PGC_CPU_0_1_MAPPING_PCIE2_M4_DOMAIN_SHIFT (31U) |
| #define GPC_PGC_CPU_0_1_MAPPING_PCIE2_M4_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_PCIE2_M4_DOMAIN_SHIFT)) & GPC_PGC_CPU_0_1_MAPPING_PCIE2_M4_DOMAIN_MASK) |
| /*! @} */ |
| |
| /*! @name CPU_PGC_SW_PUP_REQ - CPU PGC software power up trigger */ |
| /*! @{ */ |
| #define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_MASK (0x1U) |
| #define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_SHIFT (0U) |
| #define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_MASK) |
| #define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_MASK (0x2U) |
| #define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_SHIFT (1U) |
| #define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_MASK) |
| #define GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_MASK (0x4U) |
| #define GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_SHIFT (2U) |
| #define GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_MASK) |
| #define GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_MASK (0x8U) |
| #define GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_SHIFT (3U) |
| #define GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_MASK) |
| #define GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_MASK (0x10U) |
| #define GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_SHIFT (4U) |
| #define GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name MIX_PGC_SW_PUP_REQ - MIX PGC software power up trigger */ |
| /*! @{ */ |
| #define GPC_MIX_PGC_SW_PUP_REQ_MIX_SW_PUP_REQ_MASK (0x1U) |
| #define GPC_MIX_PGC_SW_PUP_REQ_MIX_SW_PUP_REQ_SHIFT (0U) |
| #define GPC_MIX_PGC_SW_PUP_REQ_MIX_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_MIX_PGC_SW_PUP_REQ_MIX_SW_PUP_REQ_SHIFT)) & GPC_MIX_PGC_SW_PUP_REQ_MIX_SW_PUP_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name PU_PGC_SW_PUP_REQ - PU PGC software up trigger */ |
| /*! @{ */ |
| #define GPC_PU_PGC_SW_PUP_REQ_MIPI_SW_PUP_REQ_MASK (0x1U) |
| #define GPC_PU_PGC_SW_PUP_REQ_MIPI_SW_PUP_REQ_SHIFT (0U) |
| #define GPC_PU_PGC_SW_PUP_REQ_MIPI_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_MIPI_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_MIPI_SW_PUP_REQ_MASK) |
| #define GPC_PU_PGC_SW_PUP_REQ_PCIE_SW_PUP_REQ_MASK (0x2U) |
| #define GPC_PU_PGC_SW_PUP_REQ_PCIE_SW_PUP_REQ_SHIFT (1U) |
| #define GPC_PU_PGC_SW_PUP_REQ_PCIE_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_PCIE_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_PCIE_SW_PUP_REQ_MASK) |
| #define GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ_MASK (0x4U) |
| #define GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ_SHIFT (2U) |
| #define GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ_MASK) |
| #define GPC_PU_PGC_SW_PUP_REQ_USB_OTG2_SW_PUP_REQ_MASK (0x8U) |
| #define GPC_PU_PGC_SW_PUP_REQ_USB_OTG2_SW_PUP_REQ_SHIFT (3U) |
| #define GPC_PU_PGC_SW_PUP_REQ_USB_OTG2_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_USB_OTG2_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_USB_OTG2_SW_PUP_REQ_MASK) |
| #define GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_MASK (0x20U) |
| #define GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_SHIFT (5U) |
| #define GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_MASK) |
| #define GPC_PU_PGC_SW_PUP_REQ_DDR2_SW_PUP_REQ_MASK (0x40U) |
| #define GPC_PU_PGC_SW_PUP_REQ_DDR2_SW_PUP_REQ_SHIFT (6U) |
| #define GPC_PU_PGC_SW_PUP_REQ_DDR2_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_DDR2_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_DDR2_SW_PUP_REQ_MASK) |
| #define GPC_PU_PGC_SW_PUP_REQ_GPU_SW_PUP_REQ_MASK (0x80U) |
| #define GPC_PU_PGC_SW_PUP_REQ_GPU_SW_PUP_REQ_SHIFT (7U) |
| #define GPC_PU_PGC_SW_PUP_REQ_GPU_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_GPU_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_GPU_SW_PUP_REQ_MASK) |
| #define GPC_PU_PGC_SW_PUP_REQ_VPU_SW_PUP_REQ_MASK (0x100U) |
| #define GPC_PU_PGC_SW_PUP_REQ_VPU_SW_PUP_REQ_SHIFT (8U) |
| #define GPC_PU_PGC_SW_PUP_REQ_VPU_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_VPU_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_VPU_SW_PUP_REQ_MASK) |
| #define GPC_PU_PGC_SW_PUP_REQ_HDMI_SW_PUP_REQ_MASK (0x200U) |
| #define GPC_PU_PGC_SW_PUP_REQ_HDMI_SW_PUP_REQ_SHIFT (9U) |
| #define GPC_PU_PGC_SW_PUP_REQ_HDMI_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_HDMI_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_HDMI_SW_PUP_REQ_MASK) |
| #define GPC_PU_PGC_SW_PUP_REQ_DISP_SW_PUP_REQ_MASK (0x400U) |
| #define GPC_PU_PGC_SW_PUP_REQ_DISP_SW_PUP_REQ_SHIFT (10U) |
| #define GPC_PU_PGC_SW_PUP_REQ_DISP_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_DISP_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_DISP_SW_PUP_REQ_MASK) |
| #define GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI1_SW_PUP_REQ_MASK (0x800U) |
| #define GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI1_SW_PUP_REQ_SHIFT (11U) |
| #define GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI1_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI1_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI1_SW_PUP_REQ_MASK) |
| #define GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI2_SW_PUP_REQ_MASK (0x1000U) |
| #define GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI2_SW_PUP_REQ_SHIFT (12U) |
| #define GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI2_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI2_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_MIPI_CSI2_SW_PUP_REQ_MASK) |
| #define GPC_PU_PGC_SW_PUP_REQ_PCIE2_SW_PUP_REQ_MASK (0x2000U) |
| #define GPC_PU_PGC_SW_PUP_REQ_PCIE2_SW_PUP_REQ_SHIFT (13U) |
| #define GPC_PU_PGC_SW_PUP_REQ_PCIE2_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_PCIE2_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_PCIE2_SW_PUP_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name CPU_PGC_SW_PDN_REQ - CPU PGC software down trigger */ |
| /*! @{ */ |
| #define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_MASK (0x1U) |
| #define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_SHIFT (0U) |
| #define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_MASK) |
| #define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_MASK (0x2U) |
| #define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_SHIFT (1U) |
| #define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_MASK) |
| #define GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PDN_REQ_MASK (0x4U) |
| #define GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PDN_REQ_SHIFT (2U) |
| #define GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PDN_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PDN_REQ_MASK) |
| #define GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PUP_REQ_MASK (0x8U) |
| #define GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PUP_REQ_SHIFT (3U) |
| #define GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PUP_REQ_MASK) |
| #define GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_MASK (0x10U) |
| #define GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_SHIFT (4U) |
| #define GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name MIX_PGC_SW_PDN_REQ - MIX PGC software power down trigger */ |
| /*! @{ */ |
| #define GPC_MIX_PGC_SW_PDN_REQ_MIX_SW_PDN_REQ_MASK (0x1U) |
| #define GPC_MIX_PGC_SW_PDN_REQ_MIX_SW_PDN_REQ_SHIFT (0U) |
| #define GPC_MIX_PGC_SW_PDN_REQ_MIX_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_MIX_PGC_SW_PDN_REQ_MIX_SW_PDN_REQ_SHIFT)) & GPC_MIX_PGC_SW_PDN_REQ_MIX_SW_PDN_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name PU_PGC_SW_PDN_REQ - PU PGC software down trigger */ |
| /*! @{ */ |
| #define GPC_PU_PGC_SW_PDN_REQ_MIPI_SW_PDN_REQ_MASK (0x1U) |
| #define GPC_PU_PGC_SW_PDN_REQ_MIPI_SW_PDN_REQ_SHIFT (0U) |
| #define GPC_PU_PGC_SW_PDN_REQ_MIPI_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_MIPI_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_MIPI_SW_PDN_REQ_MASK) |
| #define GPC_PU_PGC_SW_PDN_REQ_PCIE_SW_PDN_REQ_MASK (0x2U) |
| #define GPC_PU_PGC_SW_PDN_REQ_PCIE_SW_PDN_REQ_SHIFT (1U) |
| #define GPC_PU_PGC_SW_PDN_REQ_PCIE_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_PCIE_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_PCIE_SW_PDN_REQ_MASK) |
| #define GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ_MASK (0x4U) |
| #define GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ_SHIFT (2U) |
| #define GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ_MASK) |
| #define GPC_PU_PGC_SW_PDN_REQ_USB_OTG2_SW_PDN_REQ_MASK (0x8U) |
| #define GPC_PU_PGC_SW_PDN_REQ_USB_OTG2_SW_PDN_REQ_SHIFT (3U) |
| #define GPC_PU_PGC_SW_PDN_REQ_USB_OTG2_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_USB_OTG2_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_USB_OTG2_SW_PDN_REQ_MASK) |
| #define GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ_MASK (0x20U) |
| #define GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ_SHIFT (5U) |
| #define GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ_MASK) |
| #define GPC_PU_PGC_SW_PDN_REQ_DDR2_SW_PDN_REQ_MASK (0x40U) |
| #define GPC_PU_PGC_SW_PDN_REQ_DDR2_SW_PDN_REQ_SHIFT (6U) |
| #define GPC_PU_PGC_SW_PDN_REQ_DDR2_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_DDR2_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_DDR2_SW_PDN_REQ_MASK) |
| #define GPC_PU_PGC_SW_PDN_REQ_GPU_SW_PDN_REQ_MASK (0x80U) |
| #define GPC_PU_PGC_SW_PDN_REQ_GPU_SW_PDN_REQ_SHIFT (7U) |
| #define GPC_PU_PGC_SW_PDN_REQ_GPU_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_GPU_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_GPU_SW_PDN_REQ_MASK) |
| #define GPC_PU_PGC_SW_PDN_REQ_VPU_SW_PDN_REQ_MASK (0x100U) |
| #define GPC_PU_PGC_SW_PDN_REQ_VPU_SW_PDN_REQ_SHIFT (8U) |
| #define GPC_PU_PGC_SW_PDN_REQ_VPU_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_VPU_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_VPU_SW_PDN_REQ_MASK) |
| #define GPC_PU_PGC_SW_PDN_REQ_HDMI_SW_PDN_REQ_MASK (0x200U) |
| #define GPC_PU_PGC_SW_PDN_REQ_HDMI_SW_PDN_REQ_SHIFT (9U) |
| #define GPC_PU_PGC_SW_PDN_REQ_HDMI_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_HDMI_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_HDMI_SW_PDN_REQ_MASK) |
| #define GPC_PU_PGC_SW_PDN_REQ_DISP_SW_PDN_REQ_MASK (0x400U) |
| #define GPC_PU_PGC_SW_PDN_REQ_DISP_SW_PDN_REQ_SHIFT (10U) |
| #define GPC_PU_PGC_SW_PDN_REQ_DISP_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_DISP_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_DISP_SW_PDN_REQ_MASK) |
| #define GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI1_SW_PDN_REQ_MASK (0x800U) |
| #define GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI1_SW_PDN_REQ_SHIFT (11U) |
| #define GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI1_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI1_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI1_SW_PDN_REQ_MASK) |
| #define GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI2_SW_PDN_REQ_MASK (0x1000U) |
| #define GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI2_SW_PDN_REQ_SHIFT (12U) |
| #define GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI2_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI2_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_MIPI_CSI2_SW_PDN_REQ_MASK) |
| #define GPC_PU_PGC_SW_PDN_REQ_PCIE2_SW_PDN_REQ_MASK (0x2000U) |
| #define GPC_PU_PGC_SW_PDN_REQ_PCIE2_SW_PDN_REQ_SHIFT (13U) |
| #define GPC_PU_PGC_SW_PDN_REQ_PCIE2_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_PCIE2_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_PCIE2_SW_PDN_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name LPCR_A53_BSC2 - Basic Low power control register of A53 platform */ |
| /*! @{ */ |
| #define GPC_LPCR_A53_BSC2_LPM2_MASK (0x3U) |
| #define GPC_LPCR_A53_BSC2_LPM2_SHIFT (0U) |
| /*! LPM2 |
| * 0b00..Remain in RUN mode |
| * 0b01..Transfer to WAIT mode |
| * 0b10..Transfer to STOP mode |
| * 0b11..Reserved |
| */ |
| #define GPC_LPCR_A53_BSC2_LPM2(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC2_LPM2_SHIFT)) & GPC_LPCR_A53_BSC2_LPM2_MASK) |
| #define GPC_LPCR_A53_BSC2_LPM3_MASK (0xCU) |
| #define GPC_LPCR_A53_BSC2_LPM3_SHIFT (2U) |
| /*! LPM3 |
| * 0b00..Remain in RUN mode |
| * 0b01..Transfer to WAIT mode |
| * 0b10..Transfer to STOP mode |
| * 0b11..Reserved |
| */ |
| #define GPC_LPCR_A53_BSC2_LPM3(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC2_LPM3_SHIFT)) & GPC_LPCR_A53_BSC2_LPM3_MASK) |
| /*! @} */ |
| |
| /*! @name CPU_PGC_PUP_STATUS1 - CPU PGC software up trigger status1 */ |
| /*! @{ */ |
| #define GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_MASK (0x1U) |
| #define GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_SHIFT (0U) |
| #define GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_MASK) |
| #define GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_MASK (0x2U) |
| #define GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_SHIFT (1U) |
| #define GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_MASK) |
| #define GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_STATUS_MASK (0x4U) |
| #define GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_STATUS_SHIFT (2U) |
| #define GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_STATUS_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_STATUS_MASK) |
| #define GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_MASK (0x8U) |
| #define GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_SHIFT (3U) |
| #define GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_MASK) |
| #define GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_REQ_MASK (0x10U) |
| #define GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_REQ_SHIFT (4U) |
| #define GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_REQ_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name A53_MIX_PGC_PUP_STATUS - A53 MIX software up trigger status register */ |
| /*! @{ */ |
| #define GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_MASK (0x1U) |
| #define GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_SHIFT (0U) |
| #define GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_SHIFT)) & GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_MASK) |
| /*! @} */ |
| |
| /* The count of GPC_A53_MIX_PGC_PUP_STATUS */ |
| #define GPC_A53_MIX_PGC_PUP_STATUS_COUNT (3U) |
| |
| /*! @name M4_MIX_PGC_PUP_STATUS - M4 MIX PGC software up trigger status register */ |
| /*! @{ */ |
| #define GPC_M4_MIX_PGC_PUP_STATUS_M4_MIX_PGC_PUP_STATUS_MASK (0x1U) |
| #define GPC_M4_MIX_PGC_PUP_STATUS_M4_MIX_PGC_PUP_STATUS_SHIFT (0U) |
| #define GPC_M4_MIX_PGC_PUP_STATUS_M4_MIX_PGC_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_MIX_PGC_PUP_STATUS_M4_MIX_PGC_PUP_STATUS_SHIFT)) & GPC_M4_MIX_PGC_PUP_STATUS_M4_MIX_PGC_PUP_STATUS_MASK) |
| /*! @} */ |
| |
| /* The count of GPC_M4_MIX_PGC_PUP_STATUS */ |
| #define GPC_M4_MIX_PGC_PUP_STATUS_COUNT (3U) |
| |
| /*! @name A53_PU_PGC_PUP_STATUS - A53 PU software up trigger status register */ |
| /*! @{ */ |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PUP_STATUS_MASK (0x1U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PUP_STATUS_SHIFT (0U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PUP_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PUP_STATUS_MASK (0x2U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PUP_STATUS_SHIFT (1U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PUP_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS_MASK (0x4U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS_SHIFT (2U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG2_PUP_STATUS_MASK (0x8U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG2_PUP_STATUS_SHIFT (3U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_OTG2_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_OTG2_PUP_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS_MASK (0x20U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS_SHIFT (5U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_PUP_STATUS_MASK (0x80U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_PUP_STATUS_SHIFT (7U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_PUP_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_PUP_STATUS_MASK (0x100U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_PUP_STATUS_SHIFT (8U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_PUP_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PUP_STATUS_MASK (0x200U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PUP_STATUS_SHIFT (9U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PUP_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_DISP_PUP_STATUS_MASK (0x400U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_DISP_PUP_STATUS_SHIFT (10U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_DISP_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_DISP_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_DISP_PUP_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI1_PUP_STATUS_MASK (0x800U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI1_PUP_STATUS_SHIFT (11U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI1_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI1_PUP_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI2_PUP_STATUS_MASK (0x1000U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI2_PUP_STATUS_SHIFT (12U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI2_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_CSI2_PUP_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE2_PUP_STATUS_MASK (0x2000U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE2_PUP_STATUS_SHIFT (13U) |
| #define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE2_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE2_PUP_STATUS_MASK) |
| /*! @} */ |
| |
| /* The count of GPC_A53_PU_PGC_PUP_STATUS */ |
| #define GPC_A53_PU_PGC_PUP_STATUS_COUNT (3U) |
| |
| /*! @name M4_PU_PGC_PUP_STATUS - M4 PU PGC software up trigger status register */ |
| /*! @{ */ |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_PUP_STATUS_MASK (0x1U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_PUP_STATUS_SHIFT (0U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_PUP_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE_PUP_STATUS_MASK (0x2U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE_PUP_STATUS_SHIFT (1U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE_PUP_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_OTG1_PUP_STATUS_MASK (0x4U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_OTG1_PUP_STATUS_SHIFT (2U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_OTG1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_OTG1_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_OTG1_PUP_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_OTG2_PUP_STATUS_MASK (0x8U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_OTG2_PUP_STATUS_SHIFT (3U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_OTG2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_OTG2_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_OTG2_PUP_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_DDR1_PUP_STATUS_MASK (0x20U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_DDR1_PUP_STATUS_SHIFT (5U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_DDR1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_DDR1_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_DDR1_PUP_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_GPU_PUP_STATUS_MASK (0x80U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_GPU_PUP_STATUS_SHIFT (7U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_GPU_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_GPU_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_GPU_PUP_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_VPU_PUP_STATUS_MASK (0x100U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_VPU_PUP_STATUS_SHIFT (8U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_VPU_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_VPU_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_VPU_PUP_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_HDMI_PUP_STATUS_MASK (0x200U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_HDMI_PUP_STATUS_SHIFT (9U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_HDMI_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_HDMI_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_HDMI_PUP_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_DISP_PUP_STATUS_MASK (0x400U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_DISP_PUP_STATUS_SHIFT (10U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_DISP_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_DISP_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_DISP_PUP_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI1_PUP_STATUS_MASK (0x800U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI1_PUP_STATUS_SHIFT (11U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI1_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI1_PUP_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI2_PUP_STATUS_MASK (0x1000U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI2_PUP_STATUS_SHIFT (12U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI2_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_CSI2_PUP_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE2_PUP_STATUS_MASK (0x2000U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE2_PUP_STATUS_SHIFT (13U) |
| #define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE2_PUP_STATUS_SHIFT)) & GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE2_PUP_STATUS_MASK) |
| /*! @} */ |
| |
| /* The count of GPC_M4_PU_PGC_PUP_STATUS */ |
| #define GPC_M4_PU_PGC_PUP_STATUS_COUNT (3U) |
| |
| /*! @name CPU_PGC_PDN_STATUS1 - CPU PGC software dn trigger status1 */ |
| /*! @{ */ |
| #define GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_MASK (0x1U) |
| #define GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_SHIFT (0U) |
| #define GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_MASK) |
| #define GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_MASK (0x2U) |
| #define GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_SHIFT (1U) |
| #define GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_MASK) |
| #define GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_STATUS_MASK (0x4U) |
| #define GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_STATUS_SHIFT (2U) |
| #define GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_STATUS_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_STATUS_MASK) |
| #define GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_MASK (0x8U) |
| #define GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_SHIFT (3U) |
| #define GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_MASK) |
| #define GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_REQ_MASK (0x10U) |
| #define GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_REQ_SHIFT (4U) |
| #define GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_REQ_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_REQ_MASK) |
| /*! @} */ |
| |
| /*! @name A53_MIX_PGC_PDN_STATUS - A53 MIX software down trigger status register */ |
| /*! @{ */ |
| #define GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_MASK (0x1U) |
| #define GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_SHIFT (0U) |
| #define GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_SHIFT)) & GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_MASK) |
| /*! @} */ |
| |
| /* The count of GPC_A53_MIX_PGC_PDN_STATUS */ |
| #define GPC_A53_MIX_PGC_PDN_STATUS_COUNT (3U) |
| |
| /*! @name M4_MIX_PGC_PDN_STATUS - M4 MIX PGC software power down trigger status register */ |
| /*! @{ */ |
| #define GPC_M4_MIX_PGC_PDN_STATUS_M4_MIX_PGC_PDN_STATUS_MASK (0x1U) |
| #define GPC_M4_MIX_PGC_PDN_STATUS_M4_MIX_PGC_PDN_STATUS_SHIFT (0U) |
| #define GPC_M4_MIX_PGC_PDN_STATUS_M4_MIX_PGC_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_MIX_PGC_PDN_STATUS_M4_MIX_PGC_PDN_STATUS_SHIFT)) & GPC_M4_MIX_PGC_PDN_STATUS_M4_MIX_PGC_PDN_STATUS_MASK) |
| /*! @} */ |
| |
| /* The count of GPC_M4_MIX_PGC_PDN_STATUS */ |
| #define GPC_M4_MIX_PGC_PDN_STATUS_COUNT (3U) |
| |
| /*! @name A53_PU_PGC_PDN_STATUS - A53 PU PGC software down trigger status */ |
| /*! @{ */ |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PDN_STATUS_MASK (0x1U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PDN_STATUS_SHIFT (0U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PDN_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE_PDN_STATUS_MASK (0x2U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE_PDN_STATUS_SHIFT (1U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE_PDN_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS_MASK (0x4U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS_SHIFT (2U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG2_PDN_STATUS_MASK (0x8U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG2_PDN_STATUS_SHIFT (3U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_OTG2_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_OTG2_PDN_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS_MASK (0x20U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS_SHIFT (5U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_PDN_STATUS_MASK (0x80U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_PDN_STATUS_SHIFT (7U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_PDN_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_PDN_STATUS_MASK (0x100U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_PDN_STATUS_SHIFT (8U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_PDN_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PDN_STATUS_MASK (0x200U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PDN_STATUS_SHIFT (9U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PDN_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_DISP_PDN_STATUS_MASK (0x400U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_DISP_PDN_STATUS_SHIFT (10U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_DISP_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_DISP_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_DISP_PDN_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI1_PDN_STATUS_MASK (0x800U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI1_PDN_STATUS_SHIFT (11U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI1_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI1_PDN_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI2_PDN_STATUS_MASK (0x1000U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI2_PDN_STATUS_SHIFT (12U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI2_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_CSI2_PDN_STATUS_MASK) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE2_PDN_STATUS_MASK (0x2000U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE2_PDN_STATUS_SHIFT (13U) |
| #define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE2_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_PCIE2_PDN_STATUS_MASK) |
| /*! @} */ |
| |
| /* The count of GPC_A53_PU_PGC_PDN_STATUS */ |
| #define GPC_A53_PU_PGC_PDN_STATUS_COUNT (3U) |
| |
| /*! @name M4_PU_PGC_PDN_STATUS - M4 PU PGC software down trigger status */ |
| /*! @{ */ |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_PDN_STATUS_MASK (0x1U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_PDN_STATUS_SHIFT (0U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_PDN_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE_PDN_STATUS_MASK (0x2U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE_PDN_STATUS_SHIFT (1U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE_PDN_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_OTG1_PDN_STATUS_MASK (0x4U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_OTG1_PDN_STATUS_SHIFT (2U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_OTG1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_OTG1_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_OTG1_PDN_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_OTG2_PDN_STATUS_MASK (0x8U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_OTG2_PDN_STATUS_SHIFT (3U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_OTG2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_OTG2_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_OTG2_PDN_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_DDR1_PDN_STATUS_MASK (0x20U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_DDR1_PDN_STATUS_SHIFT (5U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_DDR1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_DDR1_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_DDR1_PDN_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_GPU_PDN_STATUS_MASK (0x80U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_GPU_PDN_STATUS_SHIFT (7U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_GPU_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_GPU_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_GPU_PDN_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_VPU_PDN_STATUS_MASK (0x100U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_VPU_PDN_STATUS_SHIFT (8U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_VPU_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_VPU_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_VPU_PDN_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_HDMI_PDN_STATUS_MASK (0x200U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_HDMI_PDN_STATUS_SHIFT (9U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_HDMI_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_HDMI_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_HDMI_PDN_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_DISP_PDN_STATUS_MASK (0x400U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_DISP_PDN_STATUS_SHIFT (10U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_DISP_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_DISP_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_DISP_PDN_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI1_PDN_STATUS_MASK (0x800U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI1_PDN_STATUS_SHIFT (11U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI1_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI1_PDN_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI2_PDN_STATUS_MASK (0x1000U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI2_PDN_STATUS_SHIFT (12U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI2_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_MIPI_CSI2_PDN_STATUS_MASK) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE2_PDN_STATUS_MASK (0x2000U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE2_PDN_STATUS_SHIFT (13U) |
| #define GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE2_PDN_STATUS_SHIFT)) & GPC_M4_PU_PGC_PDN_STATUS_M4_PCIE2_PDN_STATUS_MASK) |
| /*! @} */ |
| |
| /* The count of GPC_M4_PU_PGC_PDN_STATUS */ |
| #define GPC_M4_PU_PGC_PDN_STATUS_COUNT (3U) |
| |
| /*! @name A53_MIX_PDN_FLG - A53 MIX PDN FLG */ |
| /*! @{ */ |
| #define GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_MASK (0x1U) |
| #define GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_SHIFT (0U) |
| #define GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_SHIFT)) & GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_MASK) |
| /*! @} */ |
| |
| /*! @name A53_PU_PDN_FLG - A53 PU PDN FLG */ |
| /*! @{ */ |
| #define GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_MASK (0x3FFFU) |
| #define GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_SHIFT (0U) |
| #define GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_SHIFT)) & GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_MASK) |
| /*! @} */ |
| |
| /*! @name M4_MIX_PDN_FLG - M4 MIX PDN FLG */ |
| /*! @{ */ |
| #define GPC_M4_MIX_PDN_FLG_M4_MIX_PDN_FLAG_MASK (0x1U) |
| #define GPC_M4_MIX_PDN_FLG_M4_MIX_PDN_FLAG_SHIFT (0U) |
| #define GPC_M4_MIX_PDN_FLG_M4_MIX_PDN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_MIX_PDN_FLG_M4_MIX_PDN_FLAG_SHIFT)) & GPC_M4_MIX_PDN_FLG_M4_MIX_PDN_FLAG_MASK) |
| /*! @} */ |
| |
| /*! @name M4_PU_PDN_FLG - M4 PU PDN FLG */ |
| /*! @{ */ |
| #define GPC_M4_PU_PDN_FLG_M4_PU_PDN_FLG_MASK (0x3FFFU) |
| #define GPC_M4_PU_PDN_FLG_M4_PU_PDN_FLG_SHIFT (0U) |
| #define GPC_M4_PU_PDN_FLG_M4_PU_PDN_FLG(x) (((uint32_t)(((uint32_t)(x)) << GPC_M4_PU_PDN_FLG_M4_PU_PDN_FLG_SHIFT)) & GPC_M4_PU_PDN_FLG_M4_PU_PDN_FLG_MASK) |
| /*! @} */ |
| |
| /*! @name IMR_CORE2_A53 - IRQ masking register 1 of A53 core2..IRQ masking register 4 of A53 core2 */ |
| /*! @{ */ |
| #define GPC_IMR_CORE2_A53_IMR1_CORE2_A53_MASK (0xFFFFFFFFU) |
| #define GPC_IMR_CORE2_A53_IMR1_CORE2_A53_SHIFT (0U) |
| /*! IMR1_CORE2_A53 |
| * 0b00000000000000000000000000000000..IRQ not masked |
| * 0b00000000000000000000000000000001..IRQ masked |
| */ |
| #define GPC_IMR_CORE2_A53_IMR1_CORE2_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR1_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR1_CORE2_A53_MASK) |
| #define GPC_IMR_CORE2_A53_IMR2_CORE2_A53_MASK (0xFFFFFFFFU) |
| #define GPC_IMR_CORE2_A53_IMR2_CORE2_A53_SHIFT (0U) |
| /*! IMR2_CORE2_A53 |
| * 0b00000000000000000000000000000000..IRQ not masked |
| * 0b00000000000000000000000000000001..IRQ masked |
| */ |
| #define GPC_IMR_CORE2_A53_IMR2_CORE2_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR2_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR2_CORE2_A53_MASK) |
| #define GPC_IMR_CORE2_A53_IMR3_CORE2_A53_MASK (0xFFFFFFFFU) |
| #define GPC_IMR_CORE2_A53_IMR3_CORE2_A53_SHIFT (0U) |
| /*! IMR3_CORE2_A53 |
| * 0b00000000000000000000000000000000..IRQ not masked |
| * 0b00000000000000000000000000000001..IRQ masked |
| */ |
| #define GPC_IMR_CORE2_A53_IMR3_CORE2_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR3_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR3_CORE2_A53_MASK) |
| #define GPC_IMR_CORE2_A53_IMR4_CORE2_A53_MASK (0xFFFFFFFFU) |
| #define GPC_IMR_CORE2_A53_IMR4_CORE2_A53_SHIFT (0U) |
| /*! IMR4_CORE2_A53 |
| * 0b00000000000000000000000000000000..IRQ not masked |
| * 0b00000000000000000000000000000001..IRQ masked |
| */ |
| #define GPC_IMR_CORE2_A53_IMR4_CORE2_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR4_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR4_CORE2_A53_MASK) |
| /*! @} */ |
| |
| /* The count of GPC_IMR_CORE2_A53 */ |
| #define GPC_IMR_CORE2_A53_COUNT (4U) |
| |
| /*! @name IMR_CORE3_A53 - IRQ masking register 1 of A53 core3..IRQ masking register 4 of A53 core3 */ |
| /*! @{ */ |
| #define GPC_IMR_CORE3_A53_IMR1_CORE3_A53_MASK (0xFFFFFFFFU) |
| #define GPC_IMR_CORE3_A53_IMR1_CORE3_A53_SHIFT (0U) |
| /*! IMR1_CORE3_A53 |
| * 0b00000000000000000000000000000000..IRQ not masked |
| * 0b00000000000000000000000000000001..IRQ masked |
| */ |
| #define GPC_IMR_CORE3_A53_IMR1_CORE3_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR1_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR1_CORE3_A53_MASK) |
| #define GPC_IMR_CORE3_A53_IMR2_CORE3_A53_MASK (0xFFFFFFFFU) |
| #define GPC_IMR_CORE3_A53_IMR2_CORE3_A53_SHIFT (0U) |
| /*! IMR2_CORE3_A53 |
| * 0b00000000000000000000000000000000..IRQ not masked |
| * 0b00000000000000000000000000000001..IRQ masked |
| */ |
| #define GPC_IMR_CORE3_A53_IMR2_CORE3_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR2_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR2_CORE3_A53_MASK) |
| #define GPC_IMR_CORE3_A53_IMR3_CORE3_A53_MASK (0xFFFFFFFFU) |
| #define GPC_IMR_CORE3_A53_IMR3_CORE3_A53_SHIFT (0U) |
| /*! IMR3_CORE3_A53 |
| * 0b00000000000000000000000000000000..IRQ not masked |
| * 0b00000000000000000000000000000001..IRQ masked |
| */ |
| #define GPC_IMR_CORE3_A53_IMR3_CORE3_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR3_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR3_CORE3_A53_MASK) |
| #define GPC_IMR_CORE3_A53_IMR4_CORE3_A53_MASK (0xFFFFFFFFU) |
| #define GPC_IMR_CORE3_A53_IMR4_CORE3_A53_SHIFT (0U) |
| /*! IMR4_CORE3_A53 |
| * 0b00000000000000000000000000000000..IRQ not masked |
| * 0b00000000000000000000000000000001..IRQ masked |
| */ |
| #define GPC_IMR_CORE3_A53_IMR4_CORE3_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR4_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR4_CORE3_A53_MASK) |
| /*! @} */ |
| |
| /* The count of GPC_IMR_CORE3_A53 */ |
| #define GPC_IMR_CORE3_A53_COUNT (4U) |
| |
| /*! @name ACK_SEL_A53_PU - PGC acknowledge signal selection of A53 platform for PUs */ |
| /*! @{ */ |
| #define GPC_ACK_SEL_A53_PU_MF_PGC_PDN_ACK_MASK (0x1U) |
| #define GPC_ACK_SEL_A53_PU_MF_PGC_PDN_ACK_SHIFT (0U) |
| #define GPC_ACK_SEL_A53_PU_MF_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MF_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MF_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK_MASK (0x4U) |
| #define GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK_SHIFT (2U) |
| #define GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_PCIE_PGC_PDN_ACK_MASK (0x8U) |
| #define GPC_ACK_SEL_A53_PU_PCIE_PGC_PDN_ACK_SHIFT (3U) |
| #define GPC_ACK_SEL_A53_PU_PCIE_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_PCIE_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_PCIE_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK_MASK (0x10U) |
| #define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK_SHIFT (4U) |
| #define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PDN_ACK_MASK (0x20U) |
| #define GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PDN_ACK_SHIFT (5U) |
| #define GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK_MASK (0x80U) |
| #define GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK_SHIFT (7U) |
| #define GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_DDR2_PGC_PDN_ACK_MASK (0x100U) |
| #define GPC_ACK_SEL_A53_PU_DDR2_PGC_PDN_ACK_SHIFT (8U) |
| #define GPC_ACK_SEL_A53_PU_DDR2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DDR2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_DDR2_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_GPU_PGC_PDN_ACK_MASK (0x200U) |
| #define GPC_ACK_SEL_A53_PU_GPU_PGC_PDN_ACK_SHIFT (9U) |
| #define GPC_ACK_SEL_A53_PU_GPU_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPU_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_GPU_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_VPU_PGC_PDN_ACK_MASK (0x400U) |
| #define GPC_ACK_SEL_A53_PU_VPU_PGC_PDN_ACK_SHIFT (10U) |
| #define GPC_ACK_SEL_A53_PU_VPU_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPU_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPU_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_HDMI_PGC_PDN_ACK_MASK (0x800U) |
| #define GPC_ACK_SEL_A53_PU_HDMI_PGC_PDN_ACK_SHIFT (11U) |
| #define GPC_ACK_SEL_A53_PU_HDMI_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_HDMI_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_HDMI_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_DISP_PGC_PDN_ACK_MASK (0x1000U) |
| #define GPC_ACK_SEL_A53_PU_DISP_PGC_PDN_ACK_SHIFT (12U) |
| #define GPC_ACK_SEL_A53_PU_DISP_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DISP_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_DISP_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PDN_ACK_MASK (0x2000U) |
| #define GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PDN_ACK_SHIFT (13U) |
| #define GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PDN_ACK_MASK (0x4000U) |
| #define GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PDN_ACK_SHIFT (14U) |
| #define GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_PCIE2_PGC_PDN_ACK_MASK (0x8000U) |
| #define GPC_ACK_SEL_A53_PU_PCIE2_PGC_PDN_ACK_SHIFT (15U) |
| #define GPC_ACK_SEL_A53_PU_PCIE2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_PCIE2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_PCIE2_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_MF_PGC_PUP_ACK_MASK (0x10000U) |
| #define GPC_ACK_SEL_A53_PU_MF_PGC_PUP_ACK_SHIFT (16U) |
| #define GPC_ACK_SEL_A53_PU_MF_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MF_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MF_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK_MASK (0x40000U) |
| #define GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK_SHIFT (18U) |
| #define GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_PCIE_PGC_PUP_ACK_MASK (0x80000U) |
| #define GPC_ACK_SEL_A53_PU_PCIE_PGC_PUP_ACK_SHIFT (19U) |
| #define GPC_ACK_SEL_A53_PU_PCIE_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_PCIE_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_PCIE_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK_MASK (0x100000U) |
| #define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK_SHIFT (20U) |
| #define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PUP_ACK_MASK (0x200000U) |
| #define GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PUP_ACK_SHIFT (21U) |
| #define GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_USB_OTG2_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK_MASK (0x800000U) |
| #define GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK_SHIFT (23U) |
| #define GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_DDR2_PGC_PUP_ACK_MASK (0x1000000U) |
| #define GPC_ACK_SEL_A53_PU_DDR2_PGC_PUP_ACK_SHIFT (24U) |
| #define GPC_ACK_SEL_A53_PU_DDR2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DDR2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_DDR2_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_GPU_PGC_PUP_ACK_MASK (0x2000000U) |
| #define GPC_ACK_SEL_A53_PU_GPU_PGC_PUP_ACK_SHIFT (25U) |
| #define GPC_ACK_SEL_A53_PU_GPU_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPU_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_GPU_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_VPU_PGC_PUP_ACK_MASK (0x4000000U) |
| #define GPC_ACK_SEL_A53_PU_VPU_PGC_PUP_ACK_SHIFT (26U) |
| #define GPC_ACK_SEL_A53_PU_VPU_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPU_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPU_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_HDMI_PGC_PUP_ACK_MASK (0x8000000U) |
| #define GPC_ACK_SEL_A53_PU_HDMI_PGC_PUP_ACK_SHIFT (27U) |
| #define GPC_ACK_SEL_A53_PU_HDMI_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_HDMI_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_HDMI_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_DISP_PGC_PUP_ACK_MASK (0x10000000U) |
| #define GPC_ACK_SEL_A53_PU_DISP_PGC_PUP_ACK_SHIFT (28U) |
| #define GPC_ACK_SEL_A53_PU_DISP_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DISP_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_DISP_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PUP_ACK_MASK (0x20000000U) |
| #define GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PUP_ACK_SHIFT (29U) |
| #define GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_CSI1_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PUP_ACK_MASK (0x40000000U) |
| #define GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PUP_ACK_SHIFT (30U) |
| #define GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_CSI2_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_A53_PU_PCIE2_PGC_PUP_ACK_MASK (0x80000000U) |
| #define GPC_ACK_SEL_A53_PU_PCIE2_PGC_PUP_ACK_SHIFT (31U) |
| #define GPC_ACK_SEL_A53_PU_PCIE2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_PCIE2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_PCIE2_PGC_PUP_ACK_MASK) |
| /*! @} */ |
| |
| /*! @name ACK_SEL_M4_PU - PGC acknowledge signal selection of M4 platform for PUs */ |
| /*! @{ */ |
| #define GPC_ACK_SEL_M4_PU_MF_PGC_PDN_ACK_MASK (0x1U) |
| #define GPC_ACK_SEL_M4_PU_MF_PGC_PDN_ACK_SHIFT (0U) |
| #define GPC_ACK_SEL_M4_PU_MF_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MF_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MF_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_MIPI_PGC_PDN_ACK_MASK (0x4U) |
| #define GPC_ACK_SEL_M4_PU_MIPI_PGC_PDN_ACK_SHIFT (2U) |
| #define GPC_ACK_SEL_M4_PU_MIPI_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MIPI_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MIPI_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_PCIE_PGC_PDN_ACK_MASK (0x8U) |
| #define GPC_ACK_SEL_M4_PU_PCIE_PGC_PDN_ACK_SHIFT (3U) |
| #define GPC_ACK_SEL_M4_PU_PCIE_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_PCIE_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_PCIE_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PDN_ACK_MASK (0x10U) |
| #define GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PDN_ACK_SHIFT (4U) |
| #define GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PDN_ACK_MASK (0x20U) |
| #define GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PDN_ACK_SHIFT (5U) |
| #define GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_DDR1_PGC_PDN_ACK_MASK (0x80U) |
| #define GPC_ACK_SEL_M4_PU_DDR1_PGC_PDN_ACK_SHIFT (7U) |
| #define GPC_ACK_SEL_M4_PU_DDR1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_DDR1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_DDR1_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_DDR2_PGC_PDN_ACK_MASK (0x100U) |
| #define GPC_ACK_SEL_M4_PU_DDR2_PGC_PDN_ACK_SHIFT (8U) |
| #define GPC_ACK_SEL_M4_PU_DDR2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_DDR2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_DDR2_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_GPU_PGC_PDN_ACK_MASK (0x200U) |
| #define GPC_ACK_SEL_M4_PU_GPU_PGC_PDN_ACK_SHIFT (9U) |
| #define GPC_ACK_SEL_M4_PU_GPU_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_GPU_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_GPU_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_VPU_PGC_PDN_ACK_MASK (0x400U) |
| #define GPC_ACK_SEL_M4_PU_VPU_PGC_PDN_ACK_SHIFT (10U) |
| #define GPC_ACK_SEL_M4_PU_VPU_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_VPU_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_VPU_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_HDMI_PGC_PDN_ACK_MASK (0x800U) |
| #define GPC_ACK_SEL_M4_PU_HDMI_PGC_PDN_ACK_SHIFT (11U) |
| #define GPC_ACK_SEL_M4_PU_HDMI_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_HDMI_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_HDMI_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_DISP_PGC_PDN_ACK_MASK (0x1000U) |
| #define GPC_ACK_SEL_M4_PU_DISP_PGC_PDN_ACK_SHIFT (12U) |
| #define GPC_ACK_SEL_M4_PU_DISP_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_DISP_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_DISP_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PDN_ACK_MASK (0x2000U) |
| #define GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PDN_ACK_SHIFT (13U) |
| #define GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PDN_ACK_MASK (0x4000U) |
| #define GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PDN_ACK_SHIFT (14U) |
| #define GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_PCIE2_PGC_PDN_ACK_MASK (0x8000U) |
| #define GPC_ACK_SEL_M4_PU_PCIE2_PGC_PDN_ACK_SHIFT (15U) |
| #define GPC_ACK_SEL_M4_PU_PCIE2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_PCIE2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_PCIE2_PGC_PDN_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_MF_PGC_PUP_ACK_MASK (0x10000U) |
| #define GPC_ACK_SEL_M4_PU_MF_PGC_PUP_ACK_SHIFT (16U) |
| #define GPC_ACK_SEL_M4_PU_MF_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MF_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MF_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_MIPI_PGC_PUP_ACK_MASK (0x40000U) |
| #define GPC_ACK_SEL_M4_PU_MIPI_PGC_PUP_ACK_SHIFT (18U) |
| #define GPC_ACK_SEL_M4_PU_MIPI_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MIPI_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MIPI_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_PCIE_PGC_PUP_ACK_MASK (0x80000U) |
| #define GPC_ACK_SEL_M4_PU_PCIE_PGC_PUP_ACK_SHIFT (19U) |
| #define GPC_ACK_SEL_M4_PU_PCIE_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_PCIE_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_PCIE_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PUP_ACK_MASK (0x100000U) |
| #define GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PUP_ACK_SHIFT (20U) |
| #define GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_USB_OTG1_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PUP_ACK_MASK (0x200000U) |
| #define GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PUP_ACK_SHIFT (21U) |
| #define GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_USB_OTG2_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_DDR1_PGC_PUP_ACK_MASK (0x800000U) |
| #define GPC_ACK_SEL_M4_PU_DDR1_PGC_PUP_ACK_SHIFT (23U) |
| #define GPC_ACK_SEL_M4_PU_DDR1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_DDR1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_DDR1_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_DDR2_PGC_PUP_ACK_MASK (0x1000000U) |
| #define GPC_ACK_SEL_M4_PU_DDR2_PGC_PUP_ACK_SHIFT (24U) |
| #define GPC_ACK_SEL_M4_PU_DDR2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_DDR2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_DDR2_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_GPU_PGC_PUP_ACK_MASK (0x2000000U) |
| #define GPC_ACK_SEL_M4_PU_GPU_PGC_PUP_ACK_SHIFT (25U) |
| #define GPC_ACK_SEL_M4_PU_GPU_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_GPU_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_GPU_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_VPU_PGC_PUP_ACK_MASK (0x4000000U) |
| #define GPC_ACK_SEL_M4_PU_VPU_PGC_PUP_ACK_SHIFT (26U) |
| #define GPC_ACK_SEL_M4_PU_VPU_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_VPU_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_VPU_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_HDMI_PGC_PUP_ACK_MASK (0x8000000U) |
| #define GPC_ACK_SEL_M4_PU_HDMI_PGC_PUP_ACK_SHIFT (27U) |
| #define GPC_ACK_SEL_M4_PU_HDMI_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_HDMI_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_HDMI_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_DISP_PGC_PUP_ACK_MASK (0x10000000U) |
| #define GPC_ACK_SEL_M4_PU_DISP_PGC_PUP_ACK_SHIFT (28U) |
| #define GPC_ACK_SEL_M4_PU_DISP_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_DISP_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_DISP_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PUP_ACK_MASK (0x20000000U) |
| #define GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PUP_ACK_SHIFT (29U) |
| #define GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MIPI_CSI1_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PUP_ACK_MASK (0x40000000U) |
| #define GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PUP_ACK_SHIFT (30U) |
| #define GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_MIPI_CSI2_PGC_PUP_ACK_MASK) |
| #define GPC_ACK_SEL_M4_PU_PCIE2_PGC_PUP_ACK_MASK (0x80000000U) |
| #define GPC_ACK_SEL_M4_PU_PCIE2_PGC_PUP_ACK_SHIFT (31U) |
| #define GPC_ACK_SEL_M4_PU_PCIE2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M4_PU_PCIE2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M4_PU_PCIE2_PGC_PUP_ACK_MASK) |
| /*! @} */ |
| |
| /*! @name SLT15_CFG - Slot configure register for A53 core */ |
| /*! @{ */ |
| #define GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) |
| #define GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) |
| #define GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) |
| #define GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) |
| #define GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) |
| #define GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) |
| #define GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) |
| #define GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) |
| #define GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) |
| #define GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) |
| #define GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) |
| #define GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) |
| #define GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) |
| #define GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) |
| #define GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) |
| #define GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) |
| #define GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) |
| #define GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) |
| #define GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) |
| #define GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) |
| #define GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL_MASK) |
| /*! @} */ |
| |
| /*! @name SLT16_CFG - Slot configure register for A53 core */ |
| /*! @{ */ |
| #define GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) |
| #define GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) |
| #define GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) |
| #define GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) |
| #define GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) |
| #define GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) |
| #define GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) |
| #define GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) |
| #define GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) |
| #define GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) |
| #define GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) |
| #define GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) |
| #define GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) |
| #define GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) |
| #define GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) |
| #define GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) |
| #define GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) |
| #define GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) |
| #define GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) |
| #define GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) |
| #define GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL_MASK) |
| /*! @} */ |
| |
| /*! @name SLT17_CFG - Slot configure register for A53 core */ |
| /*! @{ */ |
| #define GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) |
| #define GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) |
| #define GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) |
| #define GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) |
| #define GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) |
| #define GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) |
| #define GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) |
| #define GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) |
| #define GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) |
| #define GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) |
| #define GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) |
| #define GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) |
| #define GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) |
| #define GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) |
| #define GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) |
| #define GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) |
| #define GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) |
| #define GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) |
| #define GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) |
| #define GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) |
| #define GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL_MASK) |
| /*! @} */ |
| |
| /*! @name SLT18_CFG - Slot configure register for A53 core */ |
| /*! @{ */ |
| #define GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) |
| #define GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) |
| #define GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) |
| #define GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) |
| #define GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) |
| #define GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) |
| #define GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) |
| #define GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) |
| #define GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) |
| #define GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) |
| #define GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) |
| #define GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) |
| #define GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) |
| #define GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) |
| #define GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) |
| #define GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) |
| #define GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) |
| #define GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) |
| #define GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) |
| #define GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) |
| #define GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL_MASK) |
| /*! @} */ |
| |
| /*! @name SLT19_CFG - Slot configure register for A53 core */ |
| /*! @{ */ |
| #define GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U) |
| #define GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U) |
| #define GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U) |
| #define GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U) |
| #define GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U) |
| #define GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U) |
| #define GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U) |
| #define GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U) |
| #define GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U) |
| #define GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U) |
| #define GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U) |
| #define GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U) |
| #define GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U) |
| #define GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U) |
| #define GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U) |
| #define GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U) |
| #define GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U) |
| #define GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U) |
| #define GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U) |
| #define GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U) |
| #define GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL_MASK) |
| /*! @} */ |
| |
| /*! @name PU_PWRHSK - Power handshake register */ |
| /*! @{ */ |
| #define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_MASK (0x1U) |
| #define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_SHIFT (0U) |
| #define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_MASK) |
| #define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_MASK (0x2U) |
| #define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_SHIFT (1U) |
| #define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_MASK) |
| #define GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSREQ_MASK (0x4U) |
| #define GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSREQ_SHIFT (2U) |
| #define GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSREQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSREQ_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSREQ_MASK) |
| #define GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSREQ_MASK (0x8U) |
| #define GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSREQ_SHIFT (3U) |
| #define GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSREQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSREQ_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSREQ_MASK) |
| #define GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNREQN_MASK (0x10U) |
| #define GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNREQN_SHIFT (4U) |
| #define GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNREQN_MASK) |
| #define GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNREQN_MASK (0x20U) |
| #define GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNREQN_SHIFT (5U) |
| #define GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNREQN_MASK) |
| #define GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNREQN_MASK (0x40U) |
| #define GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNREQN_SHIFT (6U) |
| #define GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNREQN_MASK) |
| #define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK_MASK (0x10000U) |
| #define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK_SHIFT (16U) |
| #define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK_MASK) |
| #define GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE_MASK (0x20000U) |
| #define GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE_SHIFT (17U) |
| #define GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE_MASK) |
| #define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK_MASK (0x40000U) |
| #define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK_SHIFT (18U) |
| #define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK_MASK) |
| #define GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE_MASK (0x80000U) |
| #define GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE_SHIFT (19U) |
| #define GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE_MASK) |
| #define GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSACK_MASK (0x100000U) |
| #define GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSACK_SHIFT (20U) |
| #define GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSACK_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR2_CORE_CSYSACK_MASK) |
| #define GPC_PU_PWRHSK_GPC_DDR2_CORE_CACTIVE_MASK (0x200000U) |
| #define GPC_PU_PWRHSK_GPC_DDR2_CORE_CACTIVE_SHIFT (21U) |
| #define GPC_PU_PWRHSK_GPC_DDR2_CORE_CACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR2_CORE_CACTIVE_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR2_CORE_CACTIVE_MASK) |
| #define GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSACK_MASK (0x400000U) |
| #define GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSACK_SHIFT (22U) |
| #define GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSACK_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR2_AXI_CSYSACK_MASK) |
| #define GPC_PU_PWRHSK_GPC_DDR2_AXI_CACTIVE_MASK (0x800000U) |
| #define GPC_PU_PWRHSK_GPC_DDR2_AXI_CACTIVE_SHIFT (23U) |
| #define GPC_PU_PWRHSK_GPC_DDR2_AXI_CACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR2_AXI_CACTIVE_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR2_AXI_CACTIVE_MASK) |
| #define GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNACKN_MASK (0x1000000U) |
| #define GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNACKN_SHIFT (24U) |
| #define GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_DISPMIX_PWRDNACKN_MASK) |
| #define GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNACKN_MASK (0x2000000U) |
| #define GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNACKN_SHIFT (25U) |
| #define GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_VPUMIX_PWRDNACKN_MASK) |
| #define GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNACKN_MASK (0x4000000U) |
| #define GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNACKN_SHIFT (26U) |
| #define GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_GPUMIX_PWRDNACKN_MASK) |
| /*! @} */ |
| |
| /*! @name SLT_CFG_PU - Slot configure register for PUs */ |
| /*! @{ */ |
| #define GPC_SLT_CFG_PU_MF_PDN_SLOT_CONTROL_MASK (0x1U) |
| #define GPC_SLT_CFG_PU_MF_PDN_SLOT_CONTROL_SHIFT (0U) |
| #define GPC_SLT_CFG_PU_MF_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MF_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MF_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_MF_PUP_SLOT_CONTROL_MASK (0x2U) |
| #define GPC_SLT_CFG_PU_MF_PUP_SLOT_CONTROL_SHIFT (1U) |
| #define GPC_SLT_CFG_PU_MF_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MF_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MF_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL_MASK (0x4U) |
| #define GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL_SHIFT (2U) |
| #define GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL_MASK (0x8U) |
| #define GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL_SHIFT (3U) |
| #define GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_PCIE_PDN_SLOT_CONTROL_MASK (0x10U) |
| #define GPC_SLT_CFG_PU_PCIE_PDN_SLOT_CONTROL_SHIFT (4U) |
| #define GPC_SLT_CFG_PU_PCIE_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_PCIE_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_PCIE_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_PCIE_PUP_SLOT_CONTROL_MASK (0x20U) |
| #define GPC_SLT_CFG_PU_PCIE_PUP_SLOT_CONTROL_SHIFT (5U) |
| #define GPC_SLT_CFG_PU_PCIE_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_PCIE_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_PCIE_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL_MASK (0x40U) |
| #define GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL_SHIFT (6U) |
| #define GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL_MASK (0x80U) |
| #define GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL_SHIFT (7U) |
| #define GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_OTG2_PDN_SLOT_CONTROL_MASK (0x100U) |
| #define GPC_SLT_CFG_PU_OTG2_PDN_SLOT_CONTROL_SHIFT (8U) |
| #define GPC_SLT_CFG_PU_OTG2_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_OTG2_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_OTG2_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_OTG2_PUP_SLOT_CONTROL_MASK (0x200U) |
| #define GPC_SLT_CFG_PU_OTG2_PUP_SLOT_CONTROL_SHIFT (9U) |
| #define GPC_SLT_CFG_PU_OTG2_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_OTG2_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_OTG2_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_M4_PDN_SLOT_CONTROL_MASK (0x1000U) |
| #define GPC_SLT_CFG_PU_M4_PDN_SLOT_CONTROL_SHIFT (12U) |
| #define GPC_SLT_CFG_PU_M4_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_M4_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_M4_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_M4_PUP_SLOT_CONTROL_MASK (0x2000U) |
| #define GPC_SLT_CFG_PU_M4_PUP_SLOT_CONTROL_SHIFT (13U) |
| #define GPC_SLT_CFG_PU_M4_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_M4_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_M4_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL_MASK (0x4000U) |
| #define GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL_SHIFT (14U) |
| #define GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL_MASK (0x8000U) |
| #define GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL_SHIFT (15U) |
| #define GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_DDR2_PDN_SLOT_CONTROL_MASK (0x10000U) |
| #define GPC_SLT_CFG_PU_DDR2_PDN_SLOT_CONTROL_SHIFT (16U) |
| #define GPC_SLT_CFG_PU_DDR2_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DDR2_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_DDR2_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_DDR2_PUP_SLOT_CONTROL_MASK (0x20000U) |
| #define GPC_SLT_CFG_PU_DDR2_PUP_SLOT_CONTROL_SHIFT (17U) |
| #define GPC_SLT_CFG_PU_DDR2_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DDR2_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_DDR2_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_GPU_PDN_SLOT_CONTROL_MASK (0x40000U) |
| #define GPC_SLT_CFG_PU_GPU_PDN_SLOT_CONTROL_SHIFT (18U) |
| #define GPC_SLT_CFG_PU_GPU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_GPU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_GPU_PUP_SLOT_CONTROL_MASK (0x80000U) |
| #define GPC_SLT_CFG_PU_GPU_PUP_SLOT_CONTROL_SHIFT (19U) |
| #define GPC_SLT_CFG_PU_GPU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_GPU_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_VPU_PDN_SLOT_CONTROL_MASK (0x100000U) |
| #define GPC_SLT_CFG_PU_VPU_PDN_SLOT_CONTROL_SHIFT (20U) |
| #define GPC_SLT_CFG_PU_VPU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPU_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_VPU_PUP_SLOT_CONTROL_MASK (0x200000U) |
| #define GPC_SLT_CFG_PU_VPU_PUP_SLOT_CONTROL_SHIFT (21U) |
| #define GPC_SLT_CFG_PU_VPU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPU_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_HDMI_PDN_SLOT_CONTROL_MASK (0x400000U) |
| #define GPC_SLT_CFG_PU_HDMI_PDN_SLOT_CONTROL_SHIFT (22U) |
| #define GPC_SLT_CFG_PU_HDMI_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_HDMI_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_HDMI_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_HDMI_PUP_SLOT_CONTROL_MASK (0x800000U) |
| #define GPC_SLT_CFG_PU_HDMI_PUP_SLOT_CONTROL_SHIFT (23U) |
| #define GPC_SLT_CFG_PU_HDMI_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_HDMI_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_HDMI_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_DISP_PDN_SLOT_CONTROL_MASK (0x1000000U) |
| #define GPC_SLT_CFG_PU_DISP_PDN_SLOT_CONTROL_SHIFT (24U) |
| #define GPC_SLT_CFG_PU_DISP_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DISP_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_DISP_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_DISP_PUP_SLOT_CONTROL_MASK (0x2000000U) |
| #define GPC_SLT_CFG_PU_DISP_PUP_SLOT_CONTROL_SHIFT (25U) |
| #define GPC_SLT_CFG_PU_DISP_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DISP_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_DISP_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_MIPI_CSI1_PDN_SLOT_CONTROL_MASK (0x4000000U) |
| #define GPC_SLT_CFG_PU_MIPI_CSI1_PDN_SLOT_CONTROL_SHIFT (26U) |
| #define GPC_SLT_CFG_PU_MIPI_CSI1_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_CSI1_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_CSI1_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_MIPI_CSI1_PUP_SLOT_CONTROL_MASK (0x8000000U) |
| #define GPC_SLT_CFG_PU_MIPI_CSI1_PUP_SLOT_CONTROL_SHIFT (27U) |
| #define GPC_SLT_CFG_PU_MIPI_CSI1_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_CSI1_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_CSI1_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_MIPI_CSI2_PDN_SLOT_CONTROL_MASK (0x10000000U) |
| #define GPC_SLT_CFG_PU_MIPI_CSI2_PDN_SLOT_CONTROL_SHIFT (28U) |
| #define GPC_SLT_CFG_PU_MIPI_CSI2_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_CSI2_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_CSI2_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_MIPI_CSI2_PUP_SLOT_CONTROL_MASK (0x20000000U) |
| #define GPC_SLT_CFG_PU_MIPI_CSI2_PUP_SLOT_CONTROL_SHIFT (29U) |
| #define GPC_SLT_CFG_PU_MIPI_CSI2_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_CSI2_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_CSI2_PUP_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_PCIE2_PDN_SLOT_CONTROL_MASK (0x40000000U) |
| #define GPC_SLT_CFG_PU_PCIE2_PDN_SLOT_CONTROL_SHIFT (30U) |
| #define GPC_SLT_CFG_PU_PCIE2_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_PCIE2_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_PCIE2_PDN_SLOT_CONTROL_MASK) |
| #define GPC_SLT_CFG_PU_PCIE2_PUP_SLOT_CONTROL_MASK (0x80000000U) |
| #define GPC_SLT_CFG_PU_PCIE2_PUP_SLOT_CONTROL_SHIFT (31U) |
| #define GPC_SLT_CFG_PU_PCIE2_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_PCIE2_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_PCIE2_PUP_SLOT_CONTROL_MASK) |
| /*! @} */ |
| |
| /* The count of GPC_SLT_CFG_PU */ |
| #define GPC_SLT_CFG_PU_COUNT (20U) |
| |
| |
| /*! |
| * @} |
| */ /* end of group GPC_Register_Masks */ |
| |
| |
| /* GPC - Peripheral instance base addresses */ |
| /** Peripheral GPC base address */ |
| #define GPC_BASE (0x303A0000u) |
| /** Peripheral GPC base pointer */ |
| #define GPC ((GPC_Type *)GPC_BASE) |
| /** Array initializer of GPC peripheral base addresses */ |
| #define GPC_BASE_ADDRS { GPC_BASE } |
| /** Array initializer of GPC peripheral base pointers */ |
| #define GPC_BASE_PTRS { GPC } |
| /** Interrupt vectors for the GPC peripheral type */ |
| #define GPC_IRQS { GPC_IRQn } |
| |
| /*! |
| * @} |
| */ /* end of group GPC_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPC_PGC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPC_PGC_Peripheral_Access_Layer GPC_PGC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** GPC_PGC - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t A53CORE0_CTRL; /**< GPC PGC Control Register, offset: 0x0 */ |
| __IO uint32_t A53CORE0_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x4 */ |
| __IO uint32_t A53CORE0_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x8 */ |
| __IO uint32_t A53CORE0_SR; /**< GPC PGC Status Register, offset: 0xC */ |
| __IO uint32_t A53CORE0_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x10 */ |
| uint8_t RESERVED_0[44]; |
| __IO uint32_t A53CORE1_CTRL; /**< GPC PGC Control Register, offset: 0x40 */ |
| __IO uint32_t A53CORE1_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x44 */ |
| __IO uint32_t A53CORE1_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x48 */ |
| __IO uint32_t A53CORE1_SR; /**< GPC PGC Status Register, offset: 0x4C */ |
| __IO uint32_t A53CORE1_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x50 */ |
| uint8_t RESERVED_1[44]; |
| __IO uint32_t A53CORE2_CTRL; /**< GPC PGC Control Register, offset: 0x80 */ |
| __IO uint32_t A53CORE2_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x84 */ |
| __IO uint32_t A53CORE2_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x88 */ |
| __IO uint32_t A53CORE2_SR; /**< GPC PGC Status Register, offset: 0x8C */ |
| __IO uint32_t A53CORE2_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x90 */ |
| uint8_t RESERVED_2[44]; |
| __IO uint32_t A53CORE3_CTRL; /**< GPC PGC Control Register, offset: 0xC0 */ |
| __IO uint32_t A53CORE3_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0xC4 */ |
| __IO uint32_t A53CORE3_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0xC8 */ |
| __IO uint32_t A53CORE3_SR; /**< GPC PGC Status Register, offset: 0xCC */ |
| __IO uint32_t A53CORE3_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0xD0 */ |
| uint8_t RESERVED_3[44]; |
| __IO uint32_t A53SCU_CTRL; /**< GPC PGC Control Register, offset: 0x100 */ |
| __IO uint32_t A53SCU_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x104 */ |
| __IO uint32_t A53SCU_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x108 */ |
| __IO uint32_t A53SCU_SR; /**< GPC PGC Status Register, offset: 0x10C */ |
| __IO uint32_t A53SCU_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x110 */ |
| uint8_t RESERVED_4[236]; |
| __IO uint32_t MIX_CTRL; /**< GPC PGC Control Register, offset: 0x200 */ |
| __IO uint32_t MIX_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x204 */ |
| __IO uint32_t MIX_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x208 */ |
| __IO uint32_t MIX_SR; /**< GPC PGC Status Register, offset: 0x20C */ |
| __IO uint32_t MIX_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x210 */ |
| uint8_t RESERVED_5[492]; |
| __IO uint32_t PU0_CTRL; /**< GPC PGC Control Register, offset: 0x400 */ |
| __IO uint32_t PU0_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x404 */ |
| __IO uint32_t PU0_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x408 */ |
| __IO uint32_t PU0_SR; /**< GPC PGC Status Register, offset: 0x40C */ |
| __IO uint32_t PU0_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x410 */ |
| uint8_t RESERVED_6[44]; |
| __IO uint32_t PU1_CTRL; /**< GPC PGC Control Register, offset: 0x440 */ |
| __IO uint32_t PU1_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x444 */ |
| __IO uint32_t PU1_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x448 */ |
| __IO uint32_t PU1_SR; /**< GPC PGC Status Register, offset: 0x44C */ |
| __IO uint32_t PU1_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x450 */ |
| uint8_t RESERVED_7[44]; |
| __IO uint32_t PU2_CTRL; /**< GPC PGC Control Register, offset: 0x480 */ |
| __IO uint32_t PU2_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x484 */ |
| __IO uint32_t PU2_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x488 */ |
| __IO uint32_t PU2_SR; /**< GPC PGC Status Register, offset: 0x48C */ |
| __IO uint32_t PU2_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x490 */ |
| uint8_t RESERVED_8[44]; |
| __IO uint32_t PU3_CTRL; /**< GPC PGC Control Register, offset: 0x4C0 */ |
| __IO uint32_t PU3_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x4C4 */ |
| __IO uint32_t PU3_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x4C8 */ |
| __IO uint32_t PU3_SR; /**< GPC PGC Status Register, offset: 0x4CC */ |
| __IO uint32_t PU3_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x4D0 */ |
| uint8_t RESERVED_9[44]; |
| __IO uint32_t PU4_CTRL; /**< GPC PGC Control Register, offset: 0x500 */ |
| __IO uint32_t PU4_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x504 */ |
| __IO uint32_t PU4_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x508 */ |
| __IO uint32_t PU4_SR; /**< GPC PGC Status Register, offset: 0x50C */ |
| __IO uint32_t PU4_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x510 */ |
| uint8_t RESERVED_10[44]; |
| __IO uint32_t PU5_CTRL; /**< GPC PGC Control Register, offset: 0x540 */ |
| __IO uint32_t PU5_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x544 */ |
| __IO uint32_t PU5_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x548 */ |
| __IO uint32_t PU5_SR; /**< GPC PGC Status Register, offset: 0x54C */ |
| __IO uint32_t PU5_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x550 */ |
| uint8_t RESERVED_11[44]; |
| __IO uint32_t PU6_CTRL; /**< GPC PGC Control Register, offset: 0x580 */ |
| __IO uint32_t PU6_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x584 */ |
| __IO uint32_t PU6_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x588 */ |
| __IO uint32_t PU6_SR; /**< GPC PGC Status Register, offset: 0x58C */ |
| __IO uint32_t PU6_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x590 */ |
| uint8_t RESERVED_12[44]; |
| __IO uint32_t PU7_CTRL; /**< GPC PGC Control Register, offset: 0x5C0 */ |
| __IO uint32_t PU7_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x5C4 */ |
| __IO uint32_t PU7_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x5C8 */ |
| __IO uint32_t PU7_SR; /**< GPC PGC Status Register, offset: 0x5CC */ |
| __IO uint32_t PU7_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x5D0 */ |
| uint8_t RESERVED_13[44]; |
| __IO uint32_t PU8_CTRL; /**< GPC PGC Control Register, offset: 0x600 */ |
| __IO uint32_t PU8_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x604 */ |
| __IO uint32_t PU8_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x608 */ |
| __IO uint32_t PU8_SR; /**< GPC PGC Status Register, offset: 0x60C */ |
| __IO uint32_t PU8_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x610 */ |
| uint8_t RESERVED_14[44]; |
| __IO uint32_t PU9_CTRL; /**< GPC PGC Control Register, offset: 0x640 */ |
| __IO uint32_t PU9_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x644 */ |
| __IO uint32_t PU9_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x648 */ |
| __IO uint32_t PU9_SR; /**< GPC PGC Status Register, offset: 0x64C */ |
| __IO uint32_t PU9_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x650 */ |
| uint8_t RESERVED_15[44]; |
| __IO uint32_t PU10_CTRL; /**< GPC PGC Control Register, offset: 0x680 */ |
| __IO uint32_t PU10_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x684 */ |
| __IO uint32_t PU10_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x688 */ |
| __IO uint32_t PU10_SR; /**< GPC PGC Status Register, offset: 0x68C */ |
| __IO uint32_t PU10_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x690 */ |
| uint8_t RESERVED_16[44]; |
| __IO uint32_t PU11_CTRL; /**< GPC PGC Control Register, offset: 0x6C0 */ |
| __IO uint32_t PU11_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x6C4 */ |
| __IO uint32_t PU11_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x6C8 */ |
| __IO uint32_t PU11_SR; /**< GPC PGC Status Register, offset: 0x6CC */ |
| __IO uint32_t PU11_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x6D0 */ |
| uint8_t RESERVED_17[44]; |
| __IO uint32_t PU12_CTRL; /**< GPC PGC Control Register, offset: 0x700 */ |
| __IO uint32_t PU12_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x704 */ |
| __IO uint32_t PU12_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x708 */ |
| __IO uint32_t PU12_SR; /**< GPC PGC Status Register, offset: 0x70C */ |
| __IO uint32_t PU12_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x710 */ |
| uint8_t RESERVED_18[44]; |
| __IO uint32_t PU13_CTRL; /**< GPC PGC Control Register, offset: 0x740 */ |
| __IO uint32_t PU13_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x744 */ |
| __IO uint32_t PU13_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x748 */ |
| __IO uint32_t PU13_SR; /**< GPC PGC Status Register, offset: 0x74C */ |
| __IO uint32_t PU13_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x750 */ |
| } GPC_PGC_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPC_PGC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPC_PGC_Register_Masks GPC_PGC Register Masks |
| * @{ |
| */ |
| |
| /*! @name A53CORE0_CTRL - GPC PGC Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53CORE0_CTRL_PCR_MASK (0x1U) |
| #define GPC_PGC_A53CORE0_CTRL_PCR_SHIFT (0U) |
| /*! PCR |
| * 0b0..Do not switch off power even if pdn_req is asserted. |
| * 0b1..Switch off power when pdn_req is asserted. |
| */ |
| #define GPC_PGC_A53CORE0_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_CTRL_PCR_SHIFT)) & GPC_PGC_A53CORE0_CTRL_PCR_MASK) |
| #define GPC_PGC_A53CORE0_CTRL_L2RSTDIS_MASK (0x7EU) |
| #define GPC_PGC_A53CORE0_CTRL_L2RSTDIS_SHIFT (1U) |
| #define GPC_PGC_A53CORE0_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_A53CORE0_CTRL_L2RSTDIS_MASK) |
| #define GPC_PGC_A53CORE0_CTRL_DFTRAM_TCD1_MASK (0x3F00U) |
| #define GPC_PGC_A53CORE0_CTRL_DFTRAM_TCD1_SHIFT (8U) |
| #define GPC_PGC_A53CORE0_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_A53CORE0_CTRL_DFTRAM_TCD1_MASK) |
| #define GPC_PGC_A53CORE0_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) |
| #define GPC_PGC_A53CORE0_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) |
| #define GPC_PGC_A53CORE0_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_A53CORE0_CTRL_L2RETN_TCD1_TDR_MASK) |
| #define GPC_PGC_A53CORE0_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) |
| #define GPC_PGC_A53CORE0_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) |
| #define GPC_PGC_A53CORE0_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_A53CORE0_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) |
| /*! @} */ |
| |
| /*! @name A53CORE0_PUPSCR - GPC PGC Up Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53CORE0_PUPSCR_SW_MASK (0x3FU) |
| #define GPC_PGC_A53CORE0_PUPSCR_SW_SHIFT (0U) |
| #define GPC_PGC_A53CORE0_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PUPSCR_SW_SHIFT)) & GPC_PGC_A53CORE0_PUPSCR_SW_MASK) |
| #define GPC_PGC_A53CORE0_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) |
| #define GPC_PGC_A53CORE0_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) |
| #define GPC_PGC_A53CORE0_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE0_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_A53CORE0_PUPSCR_SW2ISO_MASK (0x7FFF80U) |
| #define GPC_PGC_A53CORE0_PUPSCR_SW2ISO_SHIFT (7U) |
| #define GPC_PGC_A53CORE0_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_A53CORE0_PUPSCR_SW2ISO_MASK) |
| #define GPC_PGC_A53CORE0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) |
| #define GPC_PGC_A53CORE0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) |
| #define GPC_PGC_A53CORE0_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name A53CORE0_PDNSCR - GPC PGC Down Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53CORE0_PDNSCR_ISO_MASK (0x3FU) |
| #define GPC_PGC_A53CORE0_PDNSCR_ISO_SHIFT (0U) |
| #define GPC_PGC_A53CORE0_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PDNSCR_ISO_SHIFT)) & GPC_PGC_A53CORE0_PDNSCR_ISO_MASK) |
| #define GPC_PGC_A53CORE0_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) |
| #define GPC_PGC_A53CORE0_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) |
| #define GPC_PGC_A53CORE0_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE0_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_A53CORE0_PDNSCR_ISO2SW_MASK (0x3F00U) |
| #define GPC_PGC_A53CORE0_PDNSCR_ISO2SW_SHIFT (8U) |
| #define GPC_PGC_A53CORE0_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_A53CORE0_PDNSCR_ISO2SW_MASK) |
| #define GPC_PGC_A53CORE0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) |
| #define GPC_PGC_A53CORE0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) |
| #define GPC_PGC_A53CORE0_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) |
| #define GPC_PGC_A53CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) |
| #define GPC_PGC_A53CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) |
| #define GPC_PGC_A53CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_A53CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name A53CORE0_SR - GPC PGC Status Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53CORE0_SR_PSR_MASK (0x1U) |
| #define GPC_PGC_A53CORE0_SR_PSR_SHIFT (0U) |
| /*! PSR |
| * 0b0..The target subsystem was not powered down for the previous power-down request. |
| * 0b1..The target subsystem was powered down for the previous power-down request. |
| */ |
| #define GPC_PGC_A53CORE0_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_SR_PSR_SHIFT)) & GPC_PGC_A53CORE0_SR_PSR_MASK) |
| #define GPC_PGC_A53CORE0_SR_L2RETN_FLAG_MASK (0x2U) |
| #define GPC_PGC_A53CORE0_SR_L2RETN_FLAG_SHIFT (1U) |
| /*! L2RETN_FLAG |
| * 0b0..A53 is not wakeup from L2 retention mode. |
| * 0b1..A53 is wakeup from L2 retention mode. |
| */ |
| #define GPC_PGC_A53CORE0_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_A53CORE0_SR_L2RETN_FLAG_MASK) |
| #define GPC_PGC_A53CORE0_SR_ALLOFF_FLAG_MASK (0x4U) |
| #define GPC_PGC_A53CORE0_SR_ALLOFF_FLAG_SHIFT (2U) |
| /*! ALLOFF_FLAG |
| * 0b0..A53 is not wakeup from ALL_OFF mode. |
| * 0b1..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_A53CORE0_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_A53CORE0_SR_ALLOFF_FLAG_MASK) |
| #define GPC_PGC_A53CORE0_SR_PUP_CLK_DIV_SEL_MASK (0x78U) |
| #define GPC_PGC_A53CORE0_SR_PUP_CLK_DIV_SEL_SHIFT (3U) |
| /*! PUP_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_A53CORE0_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE0_SR_PUP_CLK_DIV_SEL_MASK) |
| #define GPC_PGC_A53CORE0_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) |
| #define GPC_PGC_A53CORE0_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) |
| #define GPC_PGC_A53CORE0_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_A53CORE0_SR_L2RSTDIS_DEASSERT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name A53CORE0_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53CORE0_AUXSW_SW2_MASK (0x3FU) |
| #define GPC_PGC_A53CORE0_AUXSW_SW2_SHIFT (0U) |
| #define GPC_PGC_A53CORE0_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_AUXSW_SW2_SHIFT)) & GPC_PGC_A53CORE0_AUXSW_SW2_MASK) |
| #define GPC_PGC_A53CORE0_AUXSW_ISO2SW2_MASK (0x3F00U) |
| #define GPC_PGC_A53CORE0_AUXSW_ISO2SW2_SHIFT (8U) |
| /*! ISO2SW2 |
| * 0b000000..A53 is not wakeup from ALL_OFF mode. |
| * 0b000001..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_A53CORE0_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_A53CORE0_AUXSW_ISO2SW2_MASK) |
| #define GPC_PGC_A53CORE0_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) |
| #define GPC_PGC_A53CORE0_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) |
| /*! PDN_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_A53CORE0_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE0_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE0_AUXSW_PDN_CLK_DIV_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name A53CORE1_CTRL - GPC PGC Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53CORE1_CTRL_PCR_MASK (0x1U) |
| #define GPC_PGC_A53CORE1_CTRL_PCR_SHIFT (0U) |
| /*! PCR |
| * 0b0..Do not switch off power even if pdn_req is asserted. |
| * 0b1..Switch off power when pdn_req is asserted. |
| */ |
| #define GPC_PGC_A53CORE1_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_CTRL_PCR_SHIFT)) & GPC_PGC_A53CORE1_CTRL_PCR_MASK) |
| #define GPC_PGC_A53CORE1_CTRL_L2RSTDIS_MASK (0x7EU) |
| #define GPC_PGC_A53CORE1_CTRL_L2RSTDIS_SHIFT (1U) |
| #define GPC_PGC_A53CORE1_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_A53CORE1_CTRL_L2RSTDIS_MASK) |
| #define GPC_PGC_A53CORE1_CTRL_DFTRAM_TCD1_MASK (0x3F00U) |
| #define GPC_PGC_A53CORE1_CTRL_DFTRAM_TCD1_SHIFT (8U) |
| #define GPC_PGC_A53CORE1_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_A53CORE1_CTRL_DFTRAM_TCD1_MASK) |
| #define GPC_PGC_A53CORE1_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) |
| #define GPC_PGC_A53CORE1_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) |
| #define GPC_PGC_A53CORE1_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_A53CORE1_CTRL_L2RETN_TCD1_TDR_MASK) |
| #define GPC_PGC_A53CORE1_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) |
| #define GPC_PGC_A53CORE1_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) |
| #define GPC_PGC_A53CORE1_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_A53CORE1_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) |
| /*! @} */ |
| |
| /*! @name A53CORE1_PUPSCR - GPC PGC Up Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53CORE1_PUPSCR_SW_MASK (0x3FU) |
| #define GPC_PGC_A53CORE1_PUPSCR_SW_SHIFT (0U) |
| #define GPC_PGC_A53CORE1_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PUPSCR_SW_SHIFT)) & GPC_PGC_A53CORE1_PUPSCR_SW_MASK) |
| #define GPC_PGC_A53CORE1_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) |
| #define GPC_PGC_A53CORE1_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) |
| #define GPC_PGC_A53CORE1_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE1_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_A53CORE1_PUPSCR_SW2ISO_MASK (0x7FFF80U) |
| #define GPC_PGC_A53CORE1_PUPSCR_SW2ISO_SHIFT (7U) |
| #define GPC_PGC_A53CORE1_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_A53CORE1_PUPSCR_SW2ISO_MASK) |
| #define GPC_PGC_A53CORE1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) |
| #define GPC_PGC_A53CORE1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) |
| #define GPC_PGC_A53CORE1_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name A53CORE1_PDNSCR - GPC PGC Down Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53CORE1_PDNSCR_ISO_MASK (0x3FU) |
| #define GPC_PGC_A53CORE1_PDNSCR_ISO_SHIFT (0U) |
| #define GPC_PGC_A53CORE1_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PDNSCR_ISO_SHIFT)) & GPC_PGC_A53CORE1_PDNSCR_ISO_MASK) |
| #define GPC_PGC_A53CORE1_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) |
| #define GPC_PGC_A53CORE1_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) |
| #define GPC_PGC_A53CORE1_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE1_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_A53CORE1_PDNSCR_ISO2SW_MASK (0x3F00U) |
| #define GPC_PGC_A53CORE1_PDNSCR_ISO2SW_SHIFT (8U) |
| #define GPC_PGC_A53CORE1_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_A53CORE1_PDNSCR_ISO2SW_MASK) |
| #define GPC_PGC_A53CORE1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) |
| #define GPC_PGC_A53CORE1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) |
| #define GPC_PGC_A53CORE1_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) |
| #define GPC_PGC_A53CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) |
| #define GPC_PGC_A53CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) |
| #define GPC_PGC_A53CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_A53CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name A53CORE1_SR - GPC PGC Status Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53CORE1_SR_PSR_MASK (0x1U) |
| #define GPC_PGC_A53CORE1_SR_PSR_SHIFT (0U) |
| /*! PSR |
| * 0b0..The target subsystem was not powered down for the previous power-down request. |
| * 0b1..The target subsystem was powered down for the previous power-down request. |
| */ |
| #define GPC_PGC_A53CORE1_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_SR_PSR_SHIFT)) & GPC_PGC_A53CORE1_SR_PSR_MASK) |
| #define GPC_PGC_A53CORE1_SR_L2RETN_FLAG_MASK (0x2U) |
| #define GPC_PGC_A53CORE1_SR_L2RETN_FLAG_SHIFT (1U) |
| /*! L2RETN_FLAG |
| * 0b0..A53 is not wakeup from L2 retention mode. |
| * 0b1..A53 is wakeup from L2 retention mode. |
| */ |
| #define GPC_PGC_A53CORE1_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_A53CORE1_SR_L2RETN_FLAG_MASK) |
| #define GPC_PGC_A53CORE1_SR_ALLOFF_FLAG_MASK (0x4U) |
| #define GPC_PGC_A53CORE1_SR_ALLOFF_FLAG_SHIFT (2U) |
| /*! ALLOFF_FLAG |
| * 0b0..A53 is not wakeup from ALL_OFF mode. |
| * 0b1..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_A53CORE1_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_A53CORE1_SR_ALLOFF_FLAG_MASK) |
| #define GPC_PGC_A53CORE1_SR_PUP_CLK_DIV_SEL_MASK (0x78U) |
| #define GPC_PGC_A53CORE1_SR_PUP_CLK_DIV_SEL_SHIFT (3U) |
| /*! PUP_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_A53CORE1_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE1_SR_PUP_CLK_DIV_SEL_MASK) |
| #define GPC_PGC_A53CORE1_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) |
| #define GPC_PGC_A53CORE1_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) |
| #define GPC_PGC_A53CORE1_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_A53CORE1_SR_L2RSTDIS_DEASSERT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name A53CORE1_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53CORE1_AUXSW_SW2_MASK (0x3FU) |
| #define GPC_PGC_A53CORE1_AUXSW_SW2_SHIFT (0U) |
| #define GPC_PGC_A53CORE1_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_AUXSW_SW2_SHIFT)) & GPC_PGC_A53CORE1_AUXSW_SW2_MASK) |
| #define GPC_PGC_A53CORE1_AUXSW_ISO2SW2_MASK (0x3F00U) |
| #define GPC_PGC_A53CORE1_AUXSW_ISO2SW2_SHIFT (8U) |
| /*! ISO2SW2 |
| * 0b000000..A53 is not wakeup from ALL_OFF mode. |
| * 0b000001..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_A53CORE1_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_A53CORE1_AUXSW_ISO2SW2_MASK) |
| #define GPC_PGC_A53CORE1_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) |
| #define GPC_PGC_A53CORE1_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) |
| /*! PDN_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_A53CORE1_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE1_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE1_AUXSW_PDN_CLK_DIV_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name A53CORE2_CTRL - GPC PGC Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53CORE2_CTRL_PCR_MASK (0x1U) |
| #define GPC_PGC_A53CORE2_CTRL_PCR_SHIFT (0U) |
| /*! PCR |
| * 0b0..Do not switch off power even if pdn_req is asserted. |
| * 0b1..Switch off power when pdn_req is asserted. |
| */ |
| #define GPC_PGC_A53CORE2_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_CTRL_PCR_SHIFT)) & GPC_PGC_A53CORE2_CTRL_PCR_MASK) |
| #define GPC_PGC_A53CORE2_CTRL_L2RSTDIS_MASK (0x7EU) |
| #define GPC_PGC_A53CORE2_CTRL_L2RSTDIS_SHIFT (1U) |
| #define GPC_PGC_A53CORE2_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_A53CORE2_CTRL_L2RSTDIS_MASK) |
| #define GPC_PGC_A53CORE2_CTRL_DFTRAM_TCD1_MASK (0x3F00U) |
| #define GPC_PGC_A53CORE2_CTRL_DFTRAM_TCD1_SHIFT (8U) |
| #define GPC_PGC_A53CORE2_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_A53CORE2_CTRL_DFTRAM_TCD1_MASK) |
| #define GPC_PGC_A53CORE2_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) |
| #define GPC_PGC_A53CORE2_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) |
| #define GPC_PGC_A53CORE2_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_A53CORE2_CTRL_L2RETN_TCD1_TDR_MASK) |
| #define GPC_PGC_A53CORE2_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) |
| #define GPC_PGC_A53CORE2_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) |
| #define GPC_PGC_A53CORE2_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_A53CORE2_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) |
| /*! @} */ |
| |
| /*! @name A53CORE2_PUPSCR - GPC PGC Up Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53CORE2_PUPSCR_SW_MASK (0x3FU) |
| #define GPC_PGC_A53CORE2_PUPSCR_SW_SHIFT (0U) |
| #define GPC_PGC_A53CORE2_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PUPSCR_SW_SHIFT)) & GPC_PGC_A53CORE2_PUPSCR_SW_MASK) |
| #define GPC_PGC_A53CORE2_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) |
| #define GPC_PGC_A53CORE2_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) |
| #define GPC_PGC_A53CORE2_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE2_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_A53CORE2_PUPSCR_SW2ISO_MASK (0x7FFF80U) |
| #define GPC_PGC_A53CORE2_PUPSCR_SW2ISO_SHIFT (7U) |
| #define GPC_PGC_A53CORE2_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_A53CORE2_PUPSCR_SW2ISO_MASK) |
| #define GPC_PGC_A53CORE2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) |
| #define GPC_PGC_A53CORE2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) |
| #define GPC_PGC_A53CORE2_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name A53CORE2_PDNSCR - GPC PGC Down Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53CORE2_PDNSCR_ISO_MASK (0x3FU) |
| #define GPC_PGC_A53CORE2_PDNSCR_ISO_SHIFT (0U) |
| #define GPC_PGC_A53CORE2_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PDNSCR_ISO_SHIFT)) & GPC_PGC_A53CORE2_PDNSCR_ISO_MASK) |
| #define GPC_PGC_A53CORE2_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) |
| #define GPC_PGC_A53CORE2_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) |
| #define GPC_PGC_A53CORE2_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE2_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_A53CORE2_PDNSCR_ISO2SW_MASK (0x3F00U) |
| #define GPC_PGC_A53CORE2_PDNSCR_ISO2SW_SHIFT (8U) |
| #define GPC_PGC_A53CORE2_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_A53CORE2_PDNSCR_ISO2SW_MASK) |
| #define GPC_PGC_A53CORE2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) |
| #define GPC_PGC_A53CORE2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) |
| #define GPC_PGC_A53CORE2_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) |
| #define GPC_PGC_A53CORE2_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) |
| #define GPC_PGC_A53CORE2_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) |
| #define GPC_PGC_A53CORE2_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_A53CORE2_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name A53CORE2_SR - GPC PGC Status Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53CORE2_SR_PSR_MASK (0x1U) |
| #define GPC_PGC_A53CORE2_SR_PSR_SHIFT (0U) |
| /*! PSR |
| * 0b0..The target subsystem was not powered down for the previous power-down request. |
| * 0b1..The target subsystem was powered down for the previous power-down request. |
| */ |
| #define GPC_PGC_A53CORE2_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_SR_PSR_SHIFT)) & GPC_PGC_A53CORE2_SR_PSR_MASK) |
| #define GPC_PGC_A53CORE2_SR_L2RETN_FLAG_MASK (0x2U) |
| #define GPC_PGC_A53CORE2_SR_L2RETN_FLAG_SHIFT (1U) |
| /*! L2RETN_FLAG |
| * 0b0..A53 is not wakeup from L2 retention mode. |
| * 0b1..A53 is wakeup from L2 retention mode. |
| */ |
| #define GPC_PGC_A53CORE2_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_A53CORE2_SR_L2RETN_FLAG_MASK) |
| #define GPC_PGC_A53CORE2_SR_ALLOFF_FLAG_MASK (0x4U) |
| #define GPC_PGC_A53CORE2_SR_ALLOFF_FLAG_SHIFT (2U) |
| /*! ALLOFF_FLAG |
| * 0b0..A53 is not wakeup from ALL_OFF mode. |
| * 0b1..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_A53CORE2_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_A53CORE2_SR_ALLOFF_FLAG_MASK) |
| #define GPC_PGC_A53CORE2_SR_PUP_CLK_DIV_SEL_MASK (0x78U) |
| #define GPC_PGC_A53CORE2_SR_PUP_CLK_DIV_SEL_SHIFT (3U) |
| /*! PUP_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_A53CORE2_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE2_SR_PUP_CLK_DIV_SEL_MASK) |
| #define GPC_PGC_A53CORE2_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) |
| #define GPC_PGC_A53CORE2_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) |
| #define GPC_PGC_A53CORE2_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_A53CORE2_SR_L2RSTDIS_DEASSERT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name A53CORE2_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53CORE2_AUXSW_SW2_MASK (0x3FU) |
| #define GPC_PGC_A53CORE2_AUXSW_SW2_SHIFT (0U) |
| #define GPC_PGC_A53CORE2_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_AUXSW_SW2_SHIFT)) & GPC_PGC_A53CORE2_AUXSW_SW2_MASK) |
| #define GPC_PGC_A53CORE2_AUXSW_ISO2SW2_MASK (0x3F00U) |
| #define GPC_PGC_A53CORE2_AUXSW_ISO2SW2_SHIFT (8U) |
| /*! ISO2SW2 |
| * 0b000000..A53 is not wakeup from ALL_OFF mode. |
| * 0b000001..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_A53CORE2_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_A53CORE2_AUXSW_ISO2SW2_MASK) |
| #define GPC_PGC_A53CORE2_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) |
| #define GPC_PGC_A53CORE2_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) |
| /*! PDN_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_A53CORE2_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE2_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE2_AUXSW_PDN_CLK_DIV_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name A53CORE3_CTRL - GPC PGC Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53CORE3_CTRL_PCR_MASK (0x1U) |
| #define GPC_PGC_A53CORE3_CTRL_PCR_SHIFT (0U) |
| /*! PCR |
| * 0b0..Do not switch off power even if pdn_req is asserted. |
| * 0b1..Switch off power when pdn_req is asserted. |
| */ |
| #define GPC_PGC_A53CORE3_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_CTRL_PCR_SHIFT)) & GPC_PGC_A53CORE3_CTRL_PCR_MASK) |
| #define GPC_PGC_A53CORE3_CTRL_L2RSTDIS_MASK (0x7EU) |
| #define GPC_PGC_A53CORE3_CTRL_L2RSTDIS_SHIFT (1U) |
| #define GPC_PGC_A53CORE3_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_A53CORE3_CTRL_L2RSTDIS_MASK) |
| #define GPC_PGC_A53CORE3_CTRL_DFTRAM_TCD1_MASK (0x3F00U) |
| #define GPC_PGC_A53CORE3_CTRL_DFTRAM_TCD1_SHIFT (8U) |
| #define GPC_PGC_A53CORE3_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_A53CORE3_CTRL_DFTRAM_TCD1_MASK) |
| #define GPC_PGC_A53CORE3_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) |
| #define GPC_PGC_A53CORE3_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) |
| #define GPC_PGC_A53CORE3_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_A53CORE3_CTRL_L2RETN_TCD1_TDR_MASK) |
| #define GPC_PGC_A53CORE3_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) |
| #define GPC_PGC_A53CORE3_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) |
| #define GPC_PGC_A53CORE3_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_A53CORE3_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) |
| /*! @} */ |
| |
| /*! @name A53CORE3_PUPSCR - GPC PGC Up Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53CORE3_PUPSCR_SW_MASK (0x3FU) |
| #define GPC_PGC_A53CORE3_PUPSCR_SW_SHIFT (0U) |
| #define GPC_PGC_A53CORE3_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PUPSCR_SW_SHIFT)) & GPC_PGC_A53CORE3_PUPSCR_SW_MASK) |
| #define GPC_PGC_A53CORE3_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) |
| #define GPC_PGC_A53CORE3_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) |
| #define GPC_PGC_A53CORE3_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE3_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_A53CORE3_PUPSCR_SW2ISO_MASK (0x7FFF80U) |
| #define GPC_PGC_A53CORE3_PUPSCR_SW2ISO_SHIFT (7U) |
| #define GPC_PGC_A53CORE3_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_A53CORE3_PUPSCR_SW2ISO_MASK) |
| #define GPC_PGC_A53CORE3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) |
| #define GPC_PGC_A53CORE3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) |
| #define GPC_PGC_A53CORE3_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name A53CORE3_PDNSCR - GPC PGC Down Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53CORE3_PDNSCR_ISO_MASK (0x3FU) |
| #define GPC_PGC_A53CORE3_PDNSCR_ISO_SHIFT (0U) |
| #define GPC_PGC_A53CORE3_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PDNSCR_ISO_SHIFT)) & GPC_PGC_A53CORE3_PDNSCR_ISO_MASK) |
| #define GPC_PGC_A53CORE3_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) |
| #define GPC_PGC_A53CORE3_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) |
| #define GPC_PGC_A53CORE3_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53CORE3_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_A53CORE3_PDNSCR_ISO2SW_MASK (0x3F00U) |
| #define GPC_PGC_A53CORE3_PDNSCR_ISO2SW_SHIFT (8U) |
| #define GPC_PGC_A53CORE3_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_A53CORE3_PDNSCR_ISO2SW_MASK) |
| #define GPC_PGC_A53CORE3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) |
| #define GPC_PGC_A53CORE3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) |
| #define GPC_PGC_A53CORE3_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53CORE3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) |
| #define GPC_PGC_A53CORE3_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) |
| #define GPC_PGC_A53CORE3_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) |
| #define GPC_PGC_A53CORE3_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_A53CORE3_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name A53CORE3_SR - GPC PGC Status Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53CORE3_SR_PSR_MASK (0x1U) |
| #define GPC_PGC_A53CORE3_SR_PSR_SHIFT (0U) |
| /*! PSR |
| * 0b0..The target subsystem was not powered down for the previous power-down request. |
| * 0b1..The target subsystem was powered down for the previous power-down request. |
| */ |
| #define GPC_PGC_A53CORE3_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_SR_PSR_SHIFT)) & GPC_PGC_A53CORE3_SR_PSR_MASK) |
| #define GPC_PGC_A53CORE3_SR_L2RETN_FLAG_MASK (0x2U) |
| #define GPC_PGC_A53CORE3_SR_L2RETN_FLAG_SHIFT (1U) |
| /*! L2RETN_FLAG |
| * 0b0..A53 is not wakeup from L2 retention mode. |
| * 0b1..A53 is wakeup from L2 retention mode. |
| */ |
| #define GPC_PGC_A53CORE3_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_A53CORE3_SR_L2RETN_FLAG_MASK) |
| #define GPC_PGC_A53CORE3_SR_ALLOFF_FLAG_MASK (0x4U) |
| #define GPC_PGC_A53CORE3_SR_ALLOFF_FLAG_SHIFT (2U) |
| /*! ALLOFF_FLAG |
| * 0b0..A53 is not wakeup from ALL_OFF mode. |
| * 0b1..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_A53CORE3_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_A53CORE3_SR_ALLOFF_FLAG_MASK) |
| #define GPC_PGC_A53CORE3_SR_PUP_CLK_DIV_SEL_MASK (0x78U) |
| #define GPC_PGC_A53CORE3_SR_PUP_CLK_DIV_SEL_SHIFT (3U) |
| /*! PUP_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_A53CORE3_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE3_SR_PUP_CLK_DIV_SEL_MASK) |
| #define GPC_PGC_A53CORE3_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) |
| #define GPC_PGC_A53CORE3_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) |
| #define GPC_PGC_A53CORE3_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_A53CORE3_SR_L2RSTDIS_DEASSERT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name A53CORE3_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53CORE3_AUXSW_SW2_MASK (0x3FU) |
| #define GPC_PGC_A53CORE3_AUXSW_SW2_SHIFT (0U) |
| #define GPC_PGC_A53CORE3_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_AUXSW_SW2_SHIFT)) & GPC_PGC_A53CORE3_AUXSW_SW2_MASK) |
| #define GPC_PGC_A53CORE3_AUXSW_ISO2SW2_MASK (0x3F00U) |
| #define GPC_PGC_A53CORE3_AUXSW_ISO2SW2_SHIFT (8U) |
| /*! ISO2SW2 |
| * 0b000000..A53 is not wakeup from ALL_OFF mode. |
| * 0b000001..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_A53CORE3_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_A53CORE3_AUXSW_ISO2SW2_MASK) |
| #define GPC_PGC_A53CORE3_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) |
| #define GPC_PGC_A53CORE3_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) |
| /*! PDN_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_A53CORE3_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53CORE3_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53CORE3_AUXSW_PDN_CLK_DIV_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name A53SCU_CTRL - GPC PGC Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53SCU_CTRL_PCR_MASK (0x1U) |
| #define GPC_PGC_A53SCU_CTRL_PCR_SHIFT (0U) |
| /*! PCR |
| * 0b0..Do not switch off power even if pdn_req is asserted. |
| * 0b1..Switch off power when pdn_req is asserted. |
| */ |
| #define GPC_PGC_A53SCU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_PCR_SHIFT)) & GPC_PGC_A53SCU_CTRL_PCR_MASK) |
| #define GPC_PGC_A53SCU_CTRL_L2RSTDIS_MASK (0x7EU) |
| #define GPC_PGC_A53SCU_CTRL_L2RSTDIS_SHIFT (1U) |
| #define GPC_PGC_A53SCU_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_A53SCU_CTRL_L2RSTDIS_MASK) |
| #define GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_MASK (0x3F00U) |
| #define GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_SHIFT (8U) |
| #define GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_MASK) |
| #define GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) |
| #define GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) |
| #define GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_MASK) |
| #define GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) |
| #define GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) |
| #define GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) |
| /*! @} */ |
| |
| /*! @name A53SCU_PUPSCR - GPC PGC Up Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53SCU_PUPSCR_SW_MASK (0x3FU) |
| #define GPC_PGC_A53SCU_PUPSCR_SW_SHIFT (0U) |
| #define GPC_PGC_A53SCU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PUPSCR_SW_SHIFT)) & GPC_PGC_A53SCU_PUPSCR_SW_MASK) |
| #define GPC_PGC_A53SCU_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) |
| #define GPC_PGC_A53SCU_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) |
| #define GPC_PGC_A53SCU_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53SCU_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_A53SCU_PUPSCR_SW2ISO_MASK (0x7FFF80U) |
| #define GPC_PGC_A53SCU_PUPSCR_SW2ISO_SHIFT (7U) |
| #define GPC_PGC_A53SCU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_A53SCU_PUPSCR_SW2ISO_MASK) |
| #define GPC_PGC_A53SCU_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) |
| #define GPC_PGC_A53SCU_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) |
| #define GPC_PGC_A53SCU_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53SCU_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name A53SCU_PDNSCR - GPC PGC Down Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53SCU_PDNSCR_ISO_MASK (0x3FU) |
| #define GPC_PGC_A53SCU_PDNSCR_ISO_SHIFT (0U) |
| #define GPC_PGC_A53SCU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_ISO_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_ISO_MASK) |
| #define GPC_PGC_A53SCU_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) |
| #define GPC_PGC_A53SCU_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) |
| #define GPC_PGC_A53SCU_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_A53SCU_PDNSCR_ISO2SW_MASK (0x3F00U) |
| #define GPC_PGC_A53SCU_PDNSCR_ISO2SW_SHIFT (8U) |
| #define GPC_PGC_A53SCU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_ISO2SW_MASK) |
| #define GPC_PGC_A53SCU_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) |
| #define GPC_PGC_A53SCU_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) |
| #define GPC_PGC_A53SCU_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) |
| #define GPC_PGC_A53SCU_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) |
| #define GPC_PGC_A53SCU_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) |
| #define GPC_PGC_A53SCU_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name A53SCU_SR - GPC PGC Status Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53SCU_SR_PSR_MASK (0x1U) |
| #define GPC_PGC_A53SCU_SR_PSR_SHIFT (0U) |
| /*! PSR |
| * 0b0..The target subsystem was not powered down for the previous power-down request. |
| * 0b1..The target subsystem was powered down for the previous power-down request. |
| */ |
| #define GPC_PGC_A53SCU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_PSR_SHIFT)) & GPC_PGC_A53SCU_SR_PSR_MASK) |
| #define GPC_PGC_A53SCU_SR_L2RETN_FLAG_MASK (0x2U) |
| #define GPC_PGC_A53SCU_SR_L2RETN_FLAG_SHIFT (1U) |
| /*! L2RETN_FLAG |
| * 0b0..A53 is not wakeup from L2 retention mode. |
| * 0b1..A53 is wakeup from L2 retention mode. |
| */ |
| #define GPC_PGC_A53SCU_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_A53SCU_SR_L2RETN_FLAG_MASK) |
| #define GPC_PGC_A53SCU_SR_ALLOFF_FLAG_MASK (0x4U) |
| #define GPC_PGC_A53SCU_SR_ALLOFF_FLAG_SHIFT (2U) |
| /*! ALLOFF_FLAG |
| * 0b0..A53 is not wakeup from ALL_OFF mode. |
| * 0b1..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_A53SCU_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_A53SCU_SR_ALLOFF_FLAG_MASK) |
| #define GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_MASK (0x78U) |
| #define GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_SHIFT (3U) |
| /*! PUP_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_MASK) |
| #define GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) |
| #define GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) |
| #define GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name A53SCU_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_A53SCU_AUXSW_SW2_MASK (0x3FU) |
| #define GPC_PGC_A53SCU_AUXSW_SW2_SHIFT (0U) |
| #define GPC_PGC_A53SCU_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_AUXSW_SW2_SHIFT)) & GPC_PGC_A53SCU_AUXSW_SW2_MASK) |
| #define GPC_PGC_A53SCU_AUXSW_ISO2SW2_MASK (0x3F00U) |
| #define GPC_PGC_A53SCU_AUXSW_ISO2SW2_SHIFT (8U) |
| /*! ISO2SW2 |
| * 0b000000..A53 is not wakeup from ALL_OFF mode. |
| * 0b000001..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_A53SCU_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_A53SCU_AUXSW_ISO2SW2_MASK) |
| #define GPC_PGC_A53SCU_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) |
| #define GPC_PGC_A53SCU_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) |
| /*! PDN_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_A53SCU_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53SCU_AUXSW_PDN_CLK_DIV_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name MIX_CTRL - GPC PGC Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_MIX_CTRL_MIX_PCR_MASK (0x1U) |
| #define GPC_PGC_MIX_CTRL_MIX_PCR_SHIFT (0U) |
| /*! MIX_PCR |
| * 0b0..Do not switch off power even if pdn_req is asserted. |
| * 0b1..Switch off power when pdn_req is asserted. |
| */ |
| #define GPC_PGC_MIX_CTRL_MIX_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_CTRL_MIX_PCR_SHIFT)) & GPC_PGC_MIX_CTRL_MIX_PCR_MASK) |
| #define GPC_PGC_MIX_CTRL_L2RSTDIS_MASK (0x7EU) |
| #define GPC_PGC_MIX_CTRL_L2RSTDIS_SHIFT (1U) |
| #define GPC_PGC_MIX_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_MIX_CTRL_L2RSTDIS_MASK) |
| #define GPC_PGC_MIX_CTRL_DFTRAM_TCD1_MASK (0x3F00U) |
| #define GPC_PGC_MIX_CTRL_DFTRAM_TCD1_SHIFT (8U) |
| #define GPC_PGC_MIX_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_MIX_CTRL_DFTRAM_TCD1_MASK) |
| #define GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) |
| #define GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) |
| #define GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR_MASK) |
| #define GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) |
| #define GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) |
| #define GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) |
| /*! @} */ |
| |
| /*! @name MIX_PUPSCR - GPC PGC Up Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_MIX_PUPSCR_SW_MASK (0x3FU) |
| #define GPC_PGC_MIX_PUPSCR_SW_SHIFT (0U) |
| #define GPC_PGC_MIX_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PUPSCR_SW_SHIFT)) & GPC_PGC_MIX_PUPSCR_SW_MASK) |
| #define GPC_PGC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) |
| #define GPC_PGC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) |
| #define GPC_PGC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_MIX_PUPSCR_SW2ISO_MASK (0x7FFF80U) |
| #define GPC_PGC_MIX_PUPSCR_SW2ISO_SHIFT (7U) |
| #define GPC_PGC_MIX_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_MIX_PUPSCR_SW2ISO_MASK) |
| #define GPC_PGC_MIX_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) |
| #define GPC_PGC_MIX_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) |
| #define GPC_PGC_MIX_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_MIX_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name MIX_PDNSCR - GPC PGC Down Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_MIX_PDNSCR_ISO_MASK (0x3FU) |
| #define GPC_PGC_MIX_PDNSCR_ISO_SHIFT (0U) |
| #define GPC_PGC_MIX_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PDNSCR_ISO_SHIFT)) & GPC_PGC_MIX_PDNSCR_ISO_MASK) |
| #define GPC_PGC_MIX_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) |
| #define GPC_PGC_MIX_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) |
| #define GPC_PGC_MIX_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_MIX_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_MIX_PDNSCR_ISO2SW_MASK (0x3F00U) |
| #define GPC_PGC_MIX_PDNSCR_ISO2SW_SHIFT (8U) |
| #define GPC_PGC_MIX_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_MIX_PDNSCR_ISO2SW_MASK) |
| #define GPC_PGC_MIX_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) |
| #define GPC_PGC_MIX_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) |
| #define GPC_PGC_MIX_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_MIX_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) |
| #define GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) |
| #define GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) |
| #define GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name MIX_SR - GPC PGC Status Register */ |
| /*! @{ */ |
| #define GPC_PGC_MIX_SR_PSR_MASK (0x1U) |
| #define GPC_PGC_MIX_SR_PSR_SHIFT (0U) |
| /*! PSR |
| * 0b0..The target subsystem was not powered down for the previous power-down request. |
| * 0b1..The target subsystem was powered down for the previous power-down request. |
| */ |
| #define GPC_PGC_MIX_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_SR_PSR_SHIFT)) & GPC_PGC_MIX_SR_PSR_MASK) |
| #define GPC_PGC_MIX_SR_L2RETN_FLAG_MASK (0x2U) |
| #define GPC_PGC_MIX_SR_L2RETN_FLAG_SHIFT (1U) |
| /*! L2RETN_FLAG |
| * 0b0..A53 is not wakeup from L2 retention mode. |
| * 0b1..A53 is wakeup from L2 retention mode. |
| */ |
| #define GPC_PGC_MIX_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_MIX_SR_L2RETN_FLAG_MASK) |
| #define GPC_PGC_MIX_SR_ALLOFF_FLAG_MASK (0x4U) |
| #define GPC_PGC_MIX_SR_ALLOFF_FLAG_SHIFT (2U) |
| /*! ALLOFF_FLAG |
| * 0b0..A53 is not wakeup from ALL_OFF mode. |
| * 0b1..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_MIX_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_MIX_SR_ALLOFF_FLAG_MASK) |
| #define GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL_MASK (0x78U) |
| #define GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL_SHIFT (3U) |
| /*! PUP_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL_MASK) |
| #define GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) |
| #define GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) |
| #define GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name MIX_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_MIX_AUXSW_SW2_MASK (0x3FU) |
| #define GPC_PGC_MIX_AUXSW_SW2_SHIFT (0U) |
| #define GPC_PGC_MIX_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_AUXSW_SW2_SHIFT)) & GPC_PGC_MIX_AUXSW_SW2_MASK) |
| #define GPC_PGC_MIX_AUXSW_ISO2SW2_MASK (0x3F00U) |
| #define GPC_PGC_MIX_AUXSW_ISO2SW2_SHIFT (8U) |
| /*! ISO2SW2 |
| * 0b000000..A53 is not wakeup from ALL_OFF mode. |
| * 0b000001..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_MIX_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_MIX_AUXSW_ISO2SW2_MASK) |
| #define GPC_PGC_MIX_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) |
| #define GPC_PGC_MIX_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) |
| /*! PDN_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_MIX_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_MIX_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_MIX_AUXSW_PDN_CLK_DIV_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name PU0_CTRL - GPC PGC Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU0_CTRL_PCR_MASK (0x1U) |
| #define GPC_PGC_PU0_CTRL_PCR_SHIFT (0U) |
| /*! PCR |
| * 0b0..Do not switch off power even if pdn_req is asserted. |
| * 0b1..Switch off power when pdn_req is asserted. |
| */ |
| #define GPC_PGC_PU0_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_CTRL_PCR_SHIFT)) & GPC_PGC_PU0_CTRL_PCR_MASK) |
| #define GPC_PGC_PU0_CTRL_L2RSTDIS_MASK (0x7EU) |
| #define GPC_PGC_PU0_CTRL_L2RSTDIS_SHIFT (1U) |
| #define GPC_PGC_PU0_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU0_CTRL_L2RSTDIS_MASK) |
| #define GPC_PGC_PU0_CTRL_DFTRAM_TCD1_MASK (0x3F00U) |
| #define GPC_PGC_PU0_CTRL_DFTRAM_TCD1_SHIFT (8U) |
| #define GPC_PGC_PU0_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU0_CTRL_DFTRAM_TCD1_MASK) |
| #define GPC_PGC_PU0_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) |
| #define GPC_PGC_PU0_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) |
| #define GPC_PGC_PU0_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU0_CTRL_L2RETN_TCD1_TDR_MASK) |
| #define GPC_PGC_PU0_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) |
| #define GPC_PGC_PU0_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) |
| #define GPC_PGC_PU0_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU0_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) |
| /*! @} */ |
| |
| /*! @name PU0_PUPSCR - GPC PGC Up Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU0_PUPSCR_SW_MASK (0x3FU) |
| #define GPC_PGC_PU0_PUPSCR_SW_SHIFT (0U) |
| #define GPC_PGC_PU0_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PUPSCR_SW_SHIFT)) & GPC_PGC_PU0_PUPSCR_SW_MASK) |
| #define GPC_PGC_PU0_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) |
| #define GPC_PGC_PU0_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) |
| #define GPC_PGC_PU0_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU0_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU0_PUPSCR_SW2ISO_MASK (0x7FFF80U) |
| #define GPC_PGC_PU0_PUPSCR_SW2ISO_SHIFT (7U) |
| #define GPC_PGC_PU0_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU0_PUPSCR_SW2ISO_MASK) |
| #define GPC_PGC_PU0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) |
| #define GPC_PGC_PU0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) |
| #define GPC_PGC_PU0_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU0_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU0_PDNSCR - GPC PGC Down Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU0_PDNSCR_ISO_MASK (0x3FU) |
| #define GPC_PGC_PU0_PDNSCR_ISO_SHIFT (0U) |
| #define GPC_PGC_PU0_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU0_PDNSCR_ISO_MASK) |
| #define GPC_PGC_PU0_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) |
| #define GPC_PGC_PU0_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) |
| #define GPC_PGC_PU0_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU0_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU0_PDNSCR_ISO2SW_MASK (0x3F00U) |
| #define GPC_PGC_PU0_PDNSCR_ISO2SW_SHIFT (8U) |
| #define GPC_PGC_PU0_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU0_PDNSCR_ISO2SW_MASK) |
| #define GPC_PGC_PU0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) |
| #define GPC_PGC_PU0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) |
| #define GPC_PGC_PU0_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU0_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) |
| #define GPC_PGC_PU0_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) |
| #define GPC_PGC_PU0_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) |
| #define GPC_PGC_PU0_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU0_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU0_SR - GPC PGC Status Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU0_SR_PSR_MASK (0x1U) |
| #define GPC_PGC_PU0_SR_PSR_SHIFT (0U) |
| /*! PSR |
| * 0b0..The target subsystem was not powered down for the previous power-down request. |
| * 0b1..The target subsystem was powered down for the previous power-down request. |
| */ |
| #define GPC_PGC_PU0_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_SR_PSR_SHIFT)) & GPC_PGC_PU0_SR_PSR_MASK) |
| #define GPC_PGC_PU0_SR_L2RETN_FLAG_MASK (0x2U) |
| #define GPC_PGC_PU0_SR_L2RETN_FLAG_SHIFT (1U) |
| /*! L2RETN_FLAG |
| * 0b0..A53 is not wakeup from L2 retention mode. |
| * 0b1..A53 is wakeup from L2 retention mode. |
| */ |
| #define GPC_PGC_PU0_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU0_SR_L2RETN_FLAG_MASK) |
| #define GPC_PGC_PU0_SR_ALLOFF_FLAG_MASK (0x4U) |
| #define GPC_PGC_PU0_SR_ALLOFF_FLAG_SHIFT (2U) |
| /*! ALLOFF_FLAG |
| * 0b0..A53 is not wakeup from ALL_OFF mode. |
| * 0b1..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU0_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU0_SR_ALLOFF_FLAG_MASK) |
| #define GPC_PGC_PU0_SR_PUP_CLK_DIV_SEL_MASK (0x78U) |
| #define GPC_PGC_PU0_SR_PUP_CLK_DIV_SEL_SHIFT (3U) |
| /*! PUP_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU0_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU0_SR_PUP_CLK_DIV_SEL_MASK) |
| #define GPC_PGC_PU0_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) |
| #define GPC_PGC_PU0_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) |
| #define GPC_PGC_PU0_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU0_SR_L2RSTDIS_DEASSERT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU0_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU0_AUXSW_SW2_MASK (0x3FU) |
| #define GPC_PGC_PU0_AUXSW_SW2_SHIFT (0U) |
| #define GPC_PGC_PU0_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_AUXSW_SW2_SHIFT)) & GPC_PGC_PU0_AUXSW_SW2_MASK) |
| #define GPC_PGC_PU0_AUXSW_ISO2SW2_MASK (0x3F00U) |
| #define GPC_PGC_PU0_AUXSW_ISO2SW2_SHIFT (8U) |
| /*! ISO2SW2 |
| * 0b000000..A53 is not wakeup from ALL_OFF mode. |
| * 0b000001..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU0_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU0_AUXSW_ISO2SW2_MASK) |
| #define GPC_PGC_PU0_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) |
| #define GPC_PGC_PU0_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) |
| /*! PDN_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU0_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU0_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU0_AUXSW_PDN_CLK_DIV_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name PU1_CTRL - GPC PGC Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU1_CTRL_PCR_MASK (0x1U) |
| #define GPC_PGC_PU1_CTRL_PCR_SHIFT (0U) |
| /*! PCR |
| * 0b0..Do not switch off power even if pdn_req is asserted. |
| * 0b1..Switch off power when pdn_req is asserted. |
| */ |
| #define GPC_PGC_PU1_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_CTRL_PCR_SHIFT)) & GPC_PGC_PU1_CTRL_PCR_MASK) |
| #define GPC_PGC_PU1_CTRL_L2RSTDIS_MASK (0x7EU) |
| #define GPC_PGC_PU1_CTRL_L2RSTDIS_SHIFT (1U) |
| #define GPC_PGC_PU1_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU1_CTRL_L2RSTDIS_MASK) |
| #define GPC_PGC_PU1_CTRL_DFTRAM_TCD1_MASK (0x3F00U) |
| #define GPC_PGC_PU1_CTRL_DFTRAM_TCD1_SHIFT (8U) |
| #define GPC_PGC_PU1_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU1_CTRL_DFTRAM_TCD1_MASK) |
| #define GPC_PGC_PU1_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) |
| #define GPC_PGC_PU1_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) |
| #define GPC_PGC_PU1_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU1_CTRL_L2RETN_TCD1_TDR_MASK) |
| #define GPC_PGC_PU1_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) |
| #define GPC_PGC_PU1_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) |
| #define GPC_PGC_PU1_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU1_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) |
| /*! @} */ |
| |
| /*! @name PU1_PUPSCR - GPC PGC Up Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU1_PUPSCR_SW_MASK (0x3FU) |
| #define GPC_PGC_PU1_PUPSCR_SW_SHIFT (0U) |
| #define GPC_PGC_PU1_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PUPSCR_SW_SHIFT)) & GPC_PGC_PU1_PUPSCR_SW_MASK) |
| #define GPC_PGC_PU1_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) |
| #define GPC_PGC_PU1_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) |
| #define GPC_PGC_PU1_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU1_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU1_PUPSCR_SW2ISO_MASK (0x7FFF80U) |
| #define GPC_PGC_PU1_PUPSCR_SW2ISO_SHIFT (7U) |
| #define GPC_PGC_PU1_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU1_PUPSCR_SW2ISO_MASK) |
| #define GPC_PGC_PU1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) |
| #define GPC_PGC_PU1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) |
| #define GPC_PGC_PU1_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU1_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU1_PDNSCR - GPC PGC Down Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU1_PDNSCR_ISO_MASK (0x3FU) |
| #define GPC_PGC_PU1_PDNSCR_ISO_SHIFT (0U) |
| #define GPC_PGC_PU1_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU1_PDNSCR_ISO_MASK) |
| #define GPC_PGC_PU1_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) |
| #define GPC_PGC_PU1_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) |
| #define GPC_PGC_PU1_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU1_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU1_PDNSCR_ISO2SW_MASK (0x3F00U) |
| #define GPC_PGC_PU1_PDNSCR_ISO2SW_SHIFT (8U) |
| #define GPC_PGC_PU1_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU1_PDNSCR_ISO2SW_MASK) |
| #define GPC_PGC_PU1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) |
| #define GPC_PGC_PU1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) |
| #define GPC_PGC_PU1_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU1_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) |
| #define GPC_PGC_PU1_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) |
| #define GPC_PGC_PU1_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) |
| #define GPC_PGC_PU1_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU1_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU1_SR - GPC PGC Status Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU1_SR_PSR_MASK (0x1U) |
| #define GPC_PGC_PU1_SR_PSR_SHIFT (0U) |
| /*! PSR |
| * 0b0..The target subsystem was not powered down for the previous power-down request. |
| * 0b1..The target subsystem was powered down for the previous power-down request. |
| */ |
| #define GPC_PGC_PU1_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_SR_PSR_SHIFT)) & GPC_PGC_PU1_SR_PSR_MASK) |
| #define GPC_PGC_PU1_SR_L2RETN_FLAG_MASK (0x2U) |
| #define GPC_PGC_PU1_SR_L2RETN_FLAG_SHIFT (1U) |
| /*! L2RETN_FLAG |
| * 0b0..A53 is not wakeup from L2 retention mode. |
| * 0b1..A53 is wakeup from L2 retention mode. |
| */ |
| #define GPC_PGC_PU1_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU1_SR_L2RETN_FLAG_MASK) |
| #define GPC_PGC_PU1_SR_ALLOFF_FLAG_MASK (0x4U) |
| #define GPC_PGC_PU1_SR_ALLOFF_FLAG_SHIFT (2U) |
| /*! ALLOFF_FLAG |
| * 0b0..A53 is not wakeup from ALL_OFF mode. |
| * 0b1..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU1_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU1_SR_ALLOFF_FLAG_MASK) |
| #define GPC_PGC_PU1_SR_PUP_CLK_DIV_SEL_MASK (0x78U) |
| #define GPC_PGC_PU1_SR_PUP_CLK_DIV_SEL_SHIFT (3U) |
| /*! PUP_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU1_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU1_SR_PUP_CLK_DIV_SEL_MASK) |
| #define GPC_PGC_PU1_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) |
| #define GPC_PGC_PU1_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) |
| #define GPC_PGC_PU1_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU1_SR_L2RSTDIS_DEASSERT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU1_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU1_AUXSW_SW2_MASK (0x3FU) |
| #define GPC_PGC_PU1_AUXSW_SW2_SHIFT (0U) |
| #define GPC_PGC_PU1_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_AUXSW_SW2_SHIFT)) & GPC_PGC_PU1_AUXSW_SW2_MASK) |
| #define GPC_PGC_PU1_AUXSW_ISO2SW2_MASK (0x3F00U) |
| #define GPC_PGC_PU1_AUXSW_ISO2SW2_SHIFT (8U) |
| /*! ISO2SW2 |
| * 0b000000..A53 is not wakeup from ALL_OFF mode. |
| * 0b000001..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU1_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU1_AUXSW_ISO2SW2_MASK) |
| #define GPC_PGC_PU1_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) |
| #define GPC_PGC_PU1_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) |
| /*! PDN_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU1_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU1_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU1_AUXSW_PDN_CLK_DIV_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name PU2_CTRL - GPC PGC Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU2_CTRL_PCR_MASK (0x1U) |
| #define GPC_PGC_PU2_CTRL_PCR_SHIFT (0U) |
| /*! PCR |
| * 0b0..Do not switch off power even if pdn_req is asserted. |
| * 0b1..Switch off power when pdn_req is asserted. |
| */ |
| #define GPC_PGC_PU2_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_CTRL_PCR_SHIFT)) & GPC_PGC_PU2_CTRL_PCR_MASK) |
| #define GPC_PGC_PU2_CTRL_L2RSTDIS_MASK (0x7EU) |
| #define GPC_PGC_PU2_CTRL_L2RSTDIS_SHIFT (1U) |
| #define GPC_PGC_PU2_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU2_CTRL_L2RSTDIS_MASK) |
| #define GPC_PGC_PU2_CTRL_DFTRAM_TCD1_MASK (0x3F00U) |
| #define GPC_PGC_PU2_CTRL_DFTRAM_TCD1_SHIFT (8U) |
| #define GPC_PGC_PU2_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU2_CTRL_DFTRAM_TCD1_MASK) |
| #define GPC_PGC_PU2_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) |
| #define GPC_PGC_PU2_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) |
| #define GPC_PGC_PU2_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU2_CTRL_L2RETN_TCD1_TDR_MASK) |
| #define GPC_PGC_PU2_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) |
| #define GPC_PGC_PU2_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) |
| #define GPC_PGC_PU2_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU2_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) |
| /*! @} */ |
| |
| /*! @name PU2_PUPSCR - GPC PGC Up Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU2_PUPSCR_SW_MASK (0x3FU) |
| #define GPC_PGC_PU2_PUPSCR_SW_SHIFT (0U) |
| #define GPC_PGC_PU2_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PUPSCR_SW_SHIFT)) & GPC_PGC_PU2_PUPSCR_SW_MASK) |
| #define GPC_PGC_PU2_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) |
| #define GPC_PGC_PU2_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) |
| #define GPC_PGC_PU2_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU2_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU2_PUPSCR_SW2ISO_MASK (0x7FFF80U) |
| #define GPC_PGC_PU2_PUPSCR_SW2ISO_SHIFT (7U) |
| #define GPC_PGC_PU2_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU2_PUPSCR_SW2ISO_MASK) |
| #define GPC_PGC_PU2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) |
| #define GPC_PGC_PU2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) |
| #define GPC_PGC_PU2_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU2_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU2_PDNSCR - GPC PGC Down Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU2_PDNSCR_ISO_MASK (0x3FU) |
| #define GPC_PGC_PU2_PDNSCR_ISO_SHIFT (0U) |
| #define GPC_PGC_PU2_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU2_PDNSCR_ISO_MASK) |
| #define GPC_PGC_PU2_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) |
| #define GPC_PGC_PU2_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) |
| #define GPC_PGC_PU2_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU2_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU2_PDNSCR_ISO2SW_MASK (0x3F00U) |
| #define GPC_PGC_PU2_PDNSCR_ISO2SW_SHIFT (8U) |
| #define GPC_PGC_PU2_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU2_PDNSCR_ISO2SW_MASK) |
| #define GPC_PGC_PU2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) |
| #define GPC_PGC_PU2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) |
| #define GPC_PGC_PU2_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU2_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) |
| #define GPC_PGC_PU2_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) |
| #define GPC_PGC_PU2_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) |
| #define GPC_PGC_PU2_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU2_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU2_SR - GPC PGC Status Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU2_SR_PSR_MASK (0x1U) |
| #define GPC_PGC_PU2_SR_PSR_SHIFT (0U) |
| /*! PSR |
| * 0b0..The target subsystem was not powered down for the previous power-down request. |
| * 0b1..The target subsystem was powered down for the previous power-down request. |
| */ |
| #define GPC_PGC_PU2_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_SR_PSR_SHIFT)) & GPC_PGC_PU2_SR_PSR_MASK) |
| #define GPC_PGC_PU2_SR_L2RETN_FLAG_MASK (0x2U) |
| #define GPC_PGC_PU2_SR_L2RETN_FLAG_SHIFT (1U) |
| /*! L2RETN_FLAG |
| * 0b0..A53 is not wakeup from L2 retention mode. |
| * 0b1..A53 is wakeup from L2 retention mode. |
| */ |
| #define GPC_PGC_PU2_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU2_SR_L2RETN_FLAG_MASK) |
| #define GPC_PGC_PU2_SR_ALLOFF_FLAG_MASK (0x4U) |
| #define GPC_PGC_PU2_SR_ALLOFF_FLAG_SHIFT (2U) |
| /*! ALLOFF_FLAG |
| * 0b0..A53 is not wakeup from ALL_OFF mode. |
| * 0b1..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU2_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU2_SR_ALLOFF_FLAG_MASK) |
| #define GPC_PGC_PU2_SR_PUP_CLK_DIV_SEL_MASK (0x78U) |
| #define GPC_PGC_PU2_SR_PUP_CLK_DIV_SEL_SHIFT (3U) |
| /*! PUP_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU2_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU2_SR_PUP_CLK_DIV_SEL_MASK) |
| #define GPC_PGC_PU2_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) |
| #define GPC_PGC_PU2_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) |
| #define GPC_PGC_PU2_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU2_SR_L2RSTDIS_DEASSERT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU2_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU2_AUXSW_SW2_MASK (0x3FU) |
| #define GPC_PGC_PU2_AUXSW_SW2_SHIFT (0U) |
| #define GPC_PGC_PU2_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_AUXSW_SW2_SHIFT)) & GPC_PGC_PU2_AUXSW_SW2_MASK) |
| #define GPC_PGC_PU2_AUXSW_ISO2SW2_MASK (0x3F00U) |
| #define GPC_PGC_PU2_AUXSW_ISO2SW2_SHIFT (8U) |
| /*! ISO2SW2 |
| * 0b000000..A53 is not wakeup from ALL_OFF mode. |
| * 0b000001..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU2_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU2_AUXSW_ISO2SW2_MASK) |
| #define GPC_PGC_PU2_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) |
| #define GPC_PGC_PU2_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) |
| /*! PDN_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU2_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU2_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU2_AUXSW_PDN_CLK_DIV_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name PU3_CTRL - GPC PGC Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU3_CTRL_PCR_MASK (0x1U) |
| #define GPC_PGC_PU3_CTRL_PCR_SHIFT (0U) |
| /*! PCR |
| * 0b0..Do not switch off power even if pdn_req is asserted. |
| * 0b1..Switch off power when pdn_req is asserted. |
| */ |
| #define GPC_PGC_PU3_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_CTRL_PCR_SHIFT)) & GPC_PGC_PU3_CTRL_PCR_MASK) |
| #define GPC_PGC_PU3_CTRL_L2RSTDIS_MASK (0x7EU) |
| #define GPC_PGC_PU3_CTRL_L2RSTDIS_SHIFT (1U) |
| #define GPC_PGC_PU3_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU3_CTRL_L2RSTDIS_MASK) |
| #define GPC_PGC_PU3_CTRL_DFTRAM_TCD1_MASK (0x3F00U) |
| #define GPC_PGC_PU3_CTRL_DFTRAM_TCD1_SHIFT (8U) |
| #define GPC_PGC_PU3_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU3_CTRL_DFTRAM_TCD1_MASK) |
| #define GPC_PGC_PU3_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) |
| #define GPC_PGC_PU3_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) |
| #define GPC_PGC_PU3_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU3_CTRL_L2RETN_TCD1_TDR_MASK) |
| #define GPC_PGC_PU3_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) |
| #define GPC_PGC_PU3_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) |
| #define GPC_PGC_PU3_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU3_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) |
| /*! @} */ |
| |
| /*! @name PU3_PUPSCR - GPC PGC Up Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU3_PUPSCR_SW_MASK (0x3FU) |
| #define GPC_PGC_PU3_PUPSCR_SW_SHIFT (0U) |
| #define GPC_PGC_PU3_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PUPSCR_SW_SHIFT)) & GPC_PGC_PU3_PUPSCR_SW_MASK) |
| #define GPC_PGC_PU3_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) |
| #define GPC_PGC_PU3_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) |
| #define GPC_PGC_PU3_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU3_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU3_PUPSCR_SW2ISO_MASK (0x7FFF80U) |
| #define GPC_PGC_PU3_PUPSCR_SW2ISO_SHIFT (7U) |
| #define GPC_PGC_PU3_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU3_PUPSCR_SW2ISO_MASK) |
| #define GPC_PGC_PU3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) |
| #define GPC_PGC_PU3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) |
| #define GPC_PGC_PU3_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU3_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU3_PDNSCR - GPC PGC Down Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU3_PDNSCR_ISO_MASK (0x3FU) |
| #define GPC_PGC_PU3_PDNSCR_ISO_SHIFT (0U) |
| #define GPC_PGC_PU3_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU3_PDNSCR_ISO_MASK) |
| #define GPC_PGC_PU3_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) |
| #define GPC_PGC_PU3_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) |
| #define GPC_PGC_PU3_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU3_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU3_PDNSCR_ISO2SW_MASK (0x3F00U) |
| #define GPC_PGC_PU3_PDNSCR_ISO2SW_SHIFT (8U) |
| #define GPC_PGC_PU3_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU3_PDNSCR_ISO2SW_MASK) |
| #define GPC_PGC_PU3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) |
| #define GPC_PGC_PU3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) |
| #define GPC_PGC_PU3_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU3_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) |
| #define GPC_PGC_PU3_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) |
| #define GPC_PGC_PU3_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) |
| #define GPC_PGC_PU3_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU3_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU3_SR - GPC PGC Status Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU3_SR_PSR_MASK (0x1U) |
| #define GPC_PGC_PU3_SR_PSR_SHIFT (0U) |
| /*! PSR |
| * 0b0..The target subsystem was not powered down for the previous power-down request. |
| * 0b1..The target subsystem was powered down for the previous power-down request. |
| */ |
| #define GPC_PGC_PU3_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_SR_PSR_SHIFT)) & GPC_PGC_PU3_SR_PSR_MASK) |
| #define GPC_PGC_PU3_SR_L2RETN_FLAG_MASK (0x2U) |
| #define GPC_PGC_PU3_SR_L2RETN_FLAG_SHIFT (1U) |
| /*! L2RETN_FLAG |
| * 0b0..A53 is not wakeup from L2 retention mode. |
| * 0b1..A53 is wakeup from L2 retention mode. |
| */ |
| #define GPC_PGC_PU3_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU3_SR_L2RETN_FLAG_MASK) |
| #define GPC_PGC_PU3_SR_ALLOFF_FLAG_MASK (0x4U) |
| #define GPC_PGC_PU3_SR_ALLOFF_FLAG_SHIFT (2U) |
| /*! ALLOFF_FLAG |
| * 0b0..A53 is not wakeup from ALL_OFF mode. |
| * 0b1..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU3_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU3_SR_ALLOFF_FLAG_MASK) |
| #define GPC_PGC_PU3_SR_PUP_CLK_DIV_SEL_MASK (0x78U) |
| #define GPC_PGC_PU3_SR_PUP_CLK_DIV_SEL_SHIFT (3U) |
| /*! PUP_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU3_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU3_SR_PUP_CLK_DIV_SEL_MASK) |
| #define GPC_PGC_PU3_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) |
| #define GPC_PGC_PU3_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) |
| #define GPC_PGC_PU3_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU3_SR_L2RSTDIS_DEASSERT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU3_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU3_AUXSW_SW2_MASK (0x3FU) |
| #define GPC_PGC_PU3_AUXSW_SW2_SHIFT (0U) |
| #define GPC_PGC_PU3_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_AUXSW_SW2_SHIFT)) & GPC_PGC_PU3_AUXSW_SW2_MASK) |
| #define GPC_PGC_PU3_AUXSW_ISO2SW2_MASK (0x3F00U) |
| #define GPC_PGC_PU3_AUXSW_ISO2SW2_SHIFT (8U) |
| /*! ISO2SW2 |
| * 0b000000..A53 is not wakeup from ALL_OFF mode. |
| * 0b000001..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU3_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU3_AUXSW_ISO2SW2_MASK) |
| #define GPC_PGC_PU3_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) |
| #define GPC_PGC_PU3_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) |
| /*! PDN_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU3_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU3_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU3_AUXSW_PDN_CLK_DIV_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name PU4_CTRL - GPC PGC Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU4_CTRL_PCR_MASK (0x1U) |
| #define GPC_PGC_PU4_CTRL_PCR_SHIFT (0U) |
| /*! PCR |
| * 0b0..Do not switch off power even if pdn_req is asserted. |
| * 0b1..Switch off power when pdn_req is asserted. |
| */ |
| #define GPC_PGC_PU4_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_CTRL_PCR_SHIFT)) & GPC_PGC_PU4_CTRL_PCR_MASK) |
| #define GPC_PGC_PU4_CTRL_L2RSTDIS_MASK (0x7EU) |
| #define GPC_PGC_PU4_CTRL_L2RSTDIS_SHIFT (1U) |
| #define GPC_PGC_PU4_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU4_CTRL_L2RSTDIS_MASK) |
| #define GPC_PGC_PU4_CTRL_DFTRAM_TCD1_MASK (0x3F00U) |
| #define GPC_PGC_PU4_CTRL_DFTRAM_TCD1_SHIFT (8U) |
| #define GPC_PGC_PU4_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU4_CTRL_DFTRAM_TCD1_MASK) |
| #define GPC_PGC_PU4_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) |
| #define GPC_PGC_PU4_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) |
| #define GPC_PGC_PU4_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU4_CTRL_L2RETN_TCD1_TDR_MASK) |
| #define GPC_PGC_PU4_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) |
| #define GPC_PGC_PU4_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) |
| #define GPC_PGC_PU4_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU4_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) |
| /*! @} */ |
| |
| /*! @name PU4_PUPSCR - GPC PGC Up Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU4_PUPSCR_SW_MASK (0x3FU) |
| #define GPC_PGC_PU4_PUPSCR_SW_SHIFT (0U) |
| #define GPC_PGC_PU4_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PUPSCR_SW_SHIFT)) & GPC_PGC_PU4_PUPSCR_SW_MASK) |
| #define GPC_PGC_PU4_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) |
| #define GPC_PGC_PU4_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) |
| #define GPC_PGC_PU4_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU4_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU4_PUPSCR_SW2ISO_MASK (0x7FFF80U) |
| #define GPC_PGC_PU4_PUPSCR_SW2ISO_SHIFT (7U) |
| #define GPC_PGC_PU4_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU4_PUPSCR_SW2ISO_MASK) |
| #define GPC_PGC_PU4_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) |
| #define GPC_PGC_PU4_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) |
| #define GPC_PGC_PU4_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU4_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU4_PDNSCR - GPC PGC Down Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU4_PDNSCR_ISO_MASK (0x3FU) |
| #define GPC_PGC_PU4_PDNSCR_ISO_SHIFT (0U) |
| #define GPC_PGC_PU4_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU4_PDNSCR_ISO_MASK) |
| #define GPC_PGC_PU4_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) |
| #define GPC_PGC_PU4_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) |
| #define GPC_PGC_PU4_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU4_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU4_PDNSCR_ISO2SW_MASK (0x3F00U) |
| #define GPC_PGC_PU4_PDNSCR_ISO2SW_SHIFT (8U) |
| #define GPC_PGC_PU4_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU4_PDNSCR_ISO2SW_MASK) |
| #define GPC_PGC_PU4_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) |
| #define GPC_PGC_PU4_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) |
| #define GPC_PGC_PU4_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU4_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) |
| #define GPC_PGC_PU4_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) |
| #define GPC_PGC_PU4_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) |
| #define GPC_PGC_PU4_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU4_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU4_SR - GPC PGC Status Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU4_SR_PSR_MASK (0x1U) |
| #define GPC_PGC_PU4_SR_PSR_SHIFT (0U) |
| /*! PSR |
| * 0b0..The target subsystem was not powered down for the previous power-down request. |
| * 0b1..The target subsystem was powered down for the previous power-down request. |
| */ |
| #define GPC_PGC_PU4_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_SR_PSR_SHIFT)) & GPC_PGC_PU4_SR_PSR_MASK) |
| #define GPC_PGC_PU4_SR_L2RETN_FLAG_MASK (0x2U) |
| #define GPC_PGC_PU4_SR_L2RETN_FLAG_SHIFT (1U) |
| /*! L2RETN_FLAG |
| * 0b0..A53 is not wakeup from L2 retention mode. |
| * 0b1..A53 is wakeup from L2 retention mode. |
| */ |
| #define GPC_PGC_PU4_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU4_SR_L2RETN_FLAG_MASK) |
| #define GPC_PGC_PU4_SR_ALLOFF_FLAG_MASK (0x4U) |
| #define GPC_PGC_PU4_SR_ALLOFF_FLAG_SHIFT (2U) |
| /*! ALLOFF_FLAG |
| * 0b0..A53 is not wakeup from ALL_OFF mode. |
| * 0b1..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU4_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU4_SR_ALLOFF_FLAG_MASK) |
| #define GPC_PGC_PU4_SR_PUP_CLK_DIV_SEL_MASK (0x78U) |
| #define GPC_PGC_PU4_SR_PUP_CLK_DIV_SEL_SHIFT (3U) |
| /*! PUP_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU4_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU4_SR_PUP_CLK_DIV_SEL_MASK) |
| #define GPC_PGC_PU4_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) |
| #define GPC_PGC_PU4_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) |
| #define GPC_PGC_PU4_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU4_SR_L2RSTDIS_DEASSERT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU4_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU4_AUXSW_SW2_MASK (0x3FU) |
| #define GPC_PGC_PU4_AUXSW_SW2_SHIFT (0U) |
| #define GPC_PGC_PU4_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_AUXSW_SW2_SHIFT)) & GPC_PGC_PU4_AUXSW_SW2_MASK) |
| #define GPC_PGC_PU4_AUXSW_ISO2SW2_MASK (0x3F00U) |
| #define GPC_PGC_PU4_AUXSW_ISO2SW2_SHIFT (8U) |
| /*! ISO2SW2 |
| * 0b000000..A53 is not wakeup from ALL_OFF mode. |
| * 0b000001..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU4_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU4_AUXSW_ISO2SW2_MASK) |
| #define GPC_PGC_PU4_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) |
| #define GPC_PGC_PU4_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) |
| /*! PDN_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU4_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU4_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU4_AUXSW_PDN_CLK_DIV_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name PU5_CTRL - GPC PGC Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU5_CTRL_PCR_MASK (0x1U) |
| #define GPC_PGC_PU5_CTRL_PCR_SHIFT (0U) |
| /*! PCR |
| * 0b0..Do not switch off power even if pdn_req is asserted. |
| * 0b1..Switch off power when pdn_req is asserted. |
| */ |
| #define GPC_PGC_PU5_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_CTRL_PCR_SHIFT)) & GPC_PGC_PU5_CTRL_PCR_MASK) |
| #define GPC_PGC_PU5_CTRL_L2RSTDIS_MASK (0x7EU) |
| #define GPC_PGC_PU5_CTRL_L2RSTDIS_SHIFT (1U) |
| #define GPC_PGC_PU5_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU5_CTRL_L2RSTDIS_MASK) |
| #define GPC_PGC_PU5_CTRL_DFTRAM_TCD1_MASK (0x3F00U) |
| #define GPC_PGC_PU5_CTRL_DFTRAM_TCD1_SHIFT (8U) |
| #define GPC_PGC_PU5_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU5_CTRL_DFTRAM_TCD1_MASK) |
| #define GPC_PGC_PU5_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) |
| #define GPC_PGC_PU5_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) |
| #define GPC_PGC_PU5_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU5_CTRL_L2RETN_TCD1_TDR_MASK) |
| #define GPC_PGC_PU5_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) |
| #define GPC_PGC_PU5_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) |
| #define GPC_PGC_PU5_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU5_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) |
| /*! @} */ |
| |
| /*! @name PU5_PUPSCR - GPC PGC Up Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU5_PUPSCR_SW_MASK (0x3FU) |
| #define GPC_PGC_PU5_PUPSCR_SW_SHIFT (0U) |
| #define GPC_PGC_PU5_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PUPSCR_SW_SHIFT)) & GPC_PGC_PU5_PUPSCR_SW_MASK) |
| #define GPC_PGC_PU5_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) |
| #define GPC_PGC_PU5_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) |
| #define GPC_PGC_PU5_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU5_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU5_PUPSCR_SW2ISO_MASK (0x7FFF80U) |
| #define GPC_PGC_PU5_PUPSCR_SW2ISO_SHIFT (7U) |
| #define GPC_PGC_PU5_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU5_PUPSCR_SW2ISO_MASK) |
| #define GPC_PGC_PU5_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) |
| #define GPC_PGC_PU5_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) |
| #define GPC_PGC_PU5_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU5_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU5_PDNSCR - GPC PGC Down Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU5_PDNSCR_ISO_MASK (0x3FU) |
| #define GPC_PGC_PU5_PDNSCR_ISO_SHIFT (0U) |
| #define GPC_PGC_PU5_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU5_PDNSCR_ISO_MASK) |
| #define GPC_PGC_PU5_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) |
| #define GPC_PGC_PU5_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) |
| #define GPC_PGC_PU5_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU5_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU5_PDNSCR_ISO2SW_MASK (0x3F00U) |
| #define GPC_PGC_PU5_PDNSCR_ISO2SW_SHIFT (8U) |
| #define GPC_PGC_PU5_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU5_PDNSCR_ISO2SW_MASK) |
| #define GPC_PGC_PU5_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) |
| #define GPC_PGC_PU5_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) |
| #define GPC_PGC_PU5_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU5_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) |
| #define GPC_PGC_PU5_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) |
| #define GPC_PGC_PU5_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) |
| #define GPC_PGC_PU5_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU5_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU5_SR - GPC PGC Status Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU5_SR_PSR_MASK (0x1U) |
| #define GPC_PGC_PU5_SR_PSR_SHIFT (0U) |
| /*! PSR |
| * 0b0..The target subsystem was not powered down for the previous power-down request. |
| * 0b1..The target subsystem was powered down for the previous power-down request. |
| */ |
| #define GPC_PGC_PU5_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_SR_PSR_SHIFT)) & GPC_PGC_PU5_SR_PSR_MASK) |
| #define GPC_PGC_PU5_SR_L2RETN_FLAG_MASK (0x2U) |
| #define GPC_PGC_PU5_SR_L2RETN_FLAG_SHIFT (1U) |
| /*! L2RETN_FLAG |
| * 0b0..A53 is not wakeup from L2 retention mode. |
| * 0b1..A53 is wakeup from L2 retention mode. |
| */ |
| #define GPC_PGC_PU5_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU5_SR_L2RETN_FLAG_MASK) |
| #define GPC_PGC_PU5_SR_ALLOFF_FLAG_MASK (0x4U) |
| #define GPC_PGC_PU5_SR_ALLOFF_FLAG_SHIFT (2U) |
| /*! ALLOFF_FLAG |
| * 0b0..A53 is not wakeup from ALL_OFF mode. |
| * 0b1..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU5_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU5_SR_ALLOFF_FLAG_MASK) |
| #define GPC_PGC_PU5_SR_PUP_CLK_DIV_SEL_MASK (0x78U) |
| #define GPC_PGC_PU5_SR_PUP_CLK_DIV_SEL_SHIFT (3U) |
| /*! PUP_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU5_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU5_SR_PUP_CLK_DIV_SEL_MASK) |
| #define GPC_PGC_PU5_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) |
| #define GPC_PGC_PU5_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) |
| #define GPC_PGC_PU5_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU5_SR_L2RSTDIS_DEASSERT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU5_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU5_AUXSW_SW2_MASK (0x3FU) |
| #define GPC_PGC_PU5_AUXSW_SW2_SHIFT (0U) |
| #define GPC_PGC_PU5_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_AUXSW_SW2_SHIFT)) & GPC_PGC_PU5_AUXSW_SW2_MASK) |
| #define GPC_PGC_PU5_AUXSW_ISO2SW2_MASK (0x3F00U) |
| #define GPC_PGC_PU5_AUXSW_ISO2SW2_SHIFT (8U) |
| /*! ISO2SW2 |
| * 0b000000..A53 is not wakeup from ALL_OFF mode. |
| * 0b000001..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU5_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU5_AUXSW_ISO2SW2_MASK) |
| #define GPC_PGC_PU5_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) |
| #define GPC_PGC_PU5_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) |
| /*! PDN_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU5_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU5_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU5_AUXSW_PDN_CLK_DIV_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name PU6_CTRL - GPC PGC Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU6_CTRL_PCR_MASK (0x1U) |
| #define GPC_PGC_PU6_CTRL_PCR_SHIFT (0U) |
| /*! PCR |
| * 0b0..Do not switch off power even if pdn_req is asserted. |
| * 0b1..Switch off power when pdn_req is asserted. |
| */ |
| #define GPC_PGC_PU6_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_CTRL_PCR_SHIFT)) & GPC_PGC_PU6_CTRL_PCR_MASK) |
| #define GPC_PGC_PU6_CTRL_L2RSTDIS_MASK (0x7EU) |
| #define GPC_PGC_PU6_CTRL_L2RSTDIS_SHIFT (1U) |
| #define GPC_PGC_PU6_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU6_CTRL_L2RSTDIS_MASK) |
| #define GPC_PGC_PU6_CTRL_DFTRAM_TCD1_MASK (0x3F00U) |
| #define GPC_PGC_PU6_CTRL_DFTRAM_TCD1_SHIFT (8U) |
| #define GPC_PGC_PU6_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU6_CTRL_DFTRAM_TCD1_MASK) |
| #define GPC_PGC_PU6_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) |
| #define GPC_PGC_PU6_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) |
| #define GPC_PGC_PU6_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU6_CTRL_L2RETN_TCD1_TDR_MASK) |
| #define GPC_PGC_PU6_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) |
| #define GPC_PGC_PU6_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) |
| #define GPC_PGC_PU6_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU6_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) |
| /*! @} */ |
| |
| /*! @name PU6_PUPSCR - GPC PGC Up Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU6_PUPSCR_SW_MASK (0x3FU) |
| #define GPC_PGC_PU6_PUPSCR_SW_SHIFT (0U) |
| #define GPC_PGC_PU6_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PUPSCR_SW_SHIFT)) & GPC_PGC_PU6_PUPSCR_SW_MASK) |
| #define GPC_PGC_PU6_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) |
| #define GPC_PGC_PU6_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) |
| #define GPC_PGC_PU6_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU6_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU6_PUPSCR_SW2ISO_MASK (0x7FFF80U) |
| #define GPC_PGC_PU6_PUPSCR_SW2ISO_SHIFT (7U) |
| #define GPC_PGC_PU6_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU6_PUPSCR_SW2ISO_MASK) |
| #define GPC_PGC_PU6_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) |
| #define GPC_PGC_PU6_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) |
| #define GPC_PGC_PU6_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU6_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU6_PDNSCR - GPC PGC Down Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU6_PDNSCR_ISO_MASK (0x3FU) |
| #define GPC_PGC_PU6_PDNSCR_ISO_SHIFT (0U) |
| #define GPC_PGC_PU6_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU6_PDNSCR_ISO_MASK) |
| #define GPC_PGC_PU6_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) |
| #define GPC_PGC_PU6_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) |
| #define GPC_PGC_PU6_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU6_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU6_PDNSCR_ISO2SW_MASK (0x3F00U) |
| #define GPC_PGC_PU6_PDNSCR_ISO2SW_SHIFT (8U) |
| #define GPC_PGC_PU6_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU6_PDNSCR_ISO2SW_MASK) |
| #define GPC_PGC_PU6_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) |
| #define GPC_PGC_PU6_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) |
| #define GPC_PGC_PU6_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU6_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) |
| #define GPC_PGC_PU6_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) |
| #define GPC_PGC_PU6_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) |
| #define GPC_PGC_PU6_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU6_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU6_SR - GPC PGC Status Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU6_SR_PSR_MASK (0x1U) |
| #define GPC_PGC_PU6_SR_PSR_SHIFT (0U) |
| /*! PSR |
| * 0b0..The target subsystem was not powered down for the previous power-down request. |
| * 0b1..The target subsystem was powered down for the previous power-down request. |
| */ |
| #define GPC_PGC_PU6_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_SR_PSR_SHIFT)) & GPC_PGC_PU6_SR_PSR_MASK) |
| #define GPC_PGC_PU6_SR_L2RETN_FLAG_MASK (0x2U) |
| #define GPC_PGC_PU6_SR_L2RETN_FLAG_SHIFT (1U) |
| /*! L2RETN_FLAG |
| * 0b0..A53 is not wakeup from L2 retention mode. |
| * 0b1..A53 is wakeup from L2 retention mode. |
| */ |
| #define GPC_PGC_PU6_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU6_SR_L2RETN_FLAG_MASK) |
| #define GPC_PGC_PU6_SR_ALLOFF_FLAG_MASK (0x4U) |
| #define GPC_PGC_PU6_SR_ALLOFF_FLAG_SHIFT (2U) |
| /*! ALLOFF_FLAG |
| * 0b0..A53 is not wakeup from ALL_OFF mode. |
| * 0b1..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU6_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU6_SR_ALLOFF_FLAG_MASK) |
| #define GPC_PGC_PU6_SR_PUP_CLK_DIV_SEL_MASK (0x78U) |
| #define GPC_PGC_PU6_SR_PUP_CLK_DIV_SEL_SHIFT (3U) |
| /*! PUP_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU6_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU6_SR_PUP_CLK_DIV_SEL_MASK) |
| #define GPC_PGC_PU6_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) |
| #define GPC_PGC_PU6_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) |
| #define GPC_PGC_PU6_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU6_SR_L2RSTDIS_DEASSERT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU6_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU6_AUXSW_SW2_MASK (0x3FU) |
| #define GPC_PGC_PU6_AUXSW_SW2_SHIFT (0U) |
| #define GPC_PGC_PU6_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_AUXSW_SW2_SHIFT)) & GPC_PGC_PU6_AUXSW_SW2_MASK) |
| #define GPC_PGC_PU6_AUXSW_ISO2SW2_MASK (0x3F00U) |
| #define GPC_PGC_PU6_AUXSW_ISO2SW2_SHIFT (8U) |
| /*! ISO2SW2 |
| * 0b000000..A53 is not wakeup from ALL_OFF mode. |
| * 0b000001..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU6_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU6_AUXSW_ISO2SW2_MASK) |
| #define GPC_PGC_PU6_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) |
| #define GPC_PGC_PU6_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) |
| /*! PDN_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU6_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU6_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU6_AUXSW_PDN_CLK_DIV_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name PU7_CTRL - GPC PGC Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU7_CTRL_PCR_MASK (0x1U) |
| #define GPC_PGC_PU7_CTRL_PCR_SHIFT (0U) |
| /*! PCR |
| * 0b0..Do not switch off power even if pdn_req is asserted. |
| * 0b1..Switch off power when pdn_req is asserted. |
| */ |
| #define GPC_PGC_PU7_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_CTRL_PCR_SHIFT)) & GPC_PGC_PU7_CTRL_PCR_MASK) |
| #define GPC_PGC_PU7_CTRL_L2RSTDIS_MASK (0x7EU) |
| #define GPC_PGC_PU7_CTRL_L2RSTDIS_SHIFT (1U) |
| #define GPC_PGC_PU7_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU7_CTRL_L2RSTDIS_MASK) |
| #define GPC_PGC_PU7_CTRL_DFTRAM_TCD1_MASK (0x3F00U) |
| #define GPC_PGC_PU7_CTRL_DFTRAM_TCD1_SHIFT (8U) |
| #define GPC_PGC_PU7_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU7_CTRL_DFTRAM_TCD1_MASK) |
| #define GPC_PGC_PU7_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) |
| #define GPC_PGC_PU7_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) |
| #define GPC_PGC_PU7_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU7_CTRL_L2RETN_TCD1_TDR_MASK) |
| #define GPC_PGC_PU7_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) |
| #define GPC_PGC_PU7_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) |
| #define GPC_PGC_PU7_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU7_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) |
| /*! @} */ |
| |
| /*! @name PU7_PUPSCR - GPC PGC Up Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU7_PUPSCR_SW_MASK (0x3FU) |
| #define GPC_PGC_PU7_PUPSCR_SW_SHIFT (0U) |
| #define GPC_PGC_PU7_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PUPSCR_SW_SHIFT)) & GPC_PGC_PU7_PUPSCR_SW_MASK) |
| #define GPC_PGC_PU7_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) |
| #define GPC_PGC_PU7_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) |
| #define GPC_PGC_PU7_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU7_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU7_PUPSCR_SW2ISO_MASK (0x7FFF80U) |
| #define GPC_PGC_PU7_PUPSCR_SW2ISO_SHIFT (7U) |
| #define GPC_PGC_PU7_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU7_PUPSCR_SW2ISO_MASK) |
| #define GPC_PGC_PU7_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) |
| #define GPC_PGC_PU7_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) |
| #define GPC_PGC_PU7_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU7_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU7_PDNSCR - GPC PGC Down Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU7_PDNSCR_ISO_MASK (0x3FU) |
| #define GPC_PGC_PU7_PDNSCR_ISO_SHIFT (0U) |
| #define GPC_PGC_PU7_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU7_PDNSCR_ISO_MASK) |
| #define GPC_PGC_PU7_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) |
| #define GPC_PGC_PU7_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) |
| #define GPC_PGC_PU7_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU7_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU7_PDNSCR_ISO2SW_MASK (0x3F00U) |
| #define GPC_PGC_PU7_PDNSCR_ISO2SW_SHIFT (8U) |
| #define GPC_PGC_PU7_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU7_PDNSCR_ISO2SW_MASK) |
| #define GPC_PGC_PU7_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) |
| #define GPC_PGC_PU7_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) |
| #define GPC_PGC_PU7_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU7_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) |
| #define GPC_PGC_PU7_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) |
| #define GPC_PGC_PU7_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) |
| #define GPC_PGC_PU7_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU7_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU7_SR - GPC PGC Status Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU7_SR_PSR_MASK (0x1U) |
| #define GPC_PGC_PU7_SR_PSR_SHIFT (0U) |
| /*! PSR |
| * 0b0..The target subsystem was not powered down for the previous power-down request. |
| * 0b1..The target subsystem was powered down for the previous power-down request. |
| */ |
| #define GPC_PGC_PU7_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_SR_PSR_SHIFT)) & GPC_PGC_PU7_SR_PSR_MASK) |
| #define GPC_PGC_PU7_SR_L2RETN_FLAG_MASK (0x2U) |
| #define GPC_PGC_PU7_SR_L2RETN_FLAG_SHIFT (1U) |
| /*! L2RETN_FLAG |
| * 0b0..A53 is not wakeup from L2 retention mode. |
| * 0b1..A53 is wakeup from L2 retention mode. |
| */ |
| #define GPC_PGC_PU7_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU7_SR_L2RETN_FLAG_MASK) |
| #define GPC_PGC_PU7_SR_ALLOFF_FLAG_MASK (0x4U) |
| #define GPC_PGC_PU7_SR_ALLOFF_FLAG_SHIFT (2U) |
| /*! ALLOFF_FLAG |
| * 0b0..A53 is not wakeup from ALL_OFF mode. |
| * 0b1..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU7_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU7_SR_ALLOFF_FLAG_MASK) |
| #define GPC_PGC_PU7_SR_PUP_CLK_DIV_SEL_MASK (0x78U) |
| #define GPC_PGC_PU7_SR_PUP_CLK_DIV_SEL_SHIFT (3U) |
| /*! PUP_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU7_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU7_SR_PUP_CLK_DIV_SEL_MASK) |
| #define GPC_PGC_PU7_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) |
| #define GPC_PGC_PU7_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) |
| #define GPC_PGC_PU7_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU7_SR_L2RSTDIS_DEASSERT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU7_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU7_AUXSW_SW2_MASK (0x3FU) |
| #define GPC_PGC_PU7_AUXSW_SW2_SHIFT (0U) |
| #define GPC_PGC_PU7_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_AUXSW_SW2_SHIFT)) & GPC_PGC_PU7_AUXSW_SW2_MASK) |
| #define GPC_PGC_PU7_AUXSW_ISO2SW2_MASK (0x3F00U) |
| #define GPC_PGC_PU7_AUXSW_ISO2SW2_SHIFT (8U) |
| /*! ISO2SW2 |
| * 0b000000..A53 is not wakeup from ALL_OFF mode. |
| * 0b000001..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU7_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU7_AUXSW_ISO2SW2_MASK) |
| #define GPC_PGC_PU7_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) |
| #define GPC_PGC_PU7_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) |
| /*! PDN_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU7_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU7_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU7_AUXSW_PDN_CLK_DIV_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name PU8_CTRL - GPC PGC Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU8_CTRL_PCR_MASK (0x1U) |
| #define GPC_PGC_PU8_CTRL_PCR_SHIFT (0U) |
| /*! PCR |
| * 0b0..Do not switch off power even if pdn_req is asserted. |
| * 0b1..Switch off power when pdn_req is asserted. |
| */ |
| #define GPC_PGC_PU8_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_CTRL_PCR_SHIFT)) & GPC_PGC_PU8_CTRL_PCR_MASK) |
| #define GPC_PGC_PU8_CTRL_L2RSTDIS_MASK (0x7EU) |
| #define GPC_PGC_PU8_CTRL_L2RSTDIS_SHIFT (1U) |
| #define GPC_PGC_PU8_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU8_CTRL_L2RSTDIS_MASK) |
| #define GPC_PGC_PU8_CTRL_DFTRAM_TCD1_MASK (0x3F00U) |
| #define GPC_PGC_PU8_CTRL_DFTRAM_TCD1_SHIFT (8U) |
| #define GPC_PGC_PU8_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU8_CTRL_DFTRAM_TCD1_MASK) |
| #define GPC_PGC_PU8_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) |
| #define GPC_PGC_PU8_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) |
| #define GPC_PGC_PU8_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU8_CTRL_L2RETN_TCD1_TDR_MASK) |
| #define GPC_PGC_PU8_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) |
| #define GPC_PGC_PU8_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) |
| #define GPC_PGC_PU8_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU8_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) |
| /*! @} */ |
| |
| /*! @name PU8_PUPSCR - GPC PGC Up Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU8_PUPSCR_SW_MASK (0x3FU) |
| #define GPC_PGC_PU8_PUPSCR_SW_SHIFT (0U) |
| #define GPC_PGC_PU8_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PUPSCR_SW_SHIFT)) & GPC_PGC_PU8_PUPSCR_SW_MASK) |
| #define GPC_PGC_PU8_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) |
| #define GPC_PGC_PU8_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) |
| #define GPC_PGC_PU8_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU8_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU8_PUPSCR_SW2ISO_MASK (0x7FFF80U) |
| #define GPC_PGC_PU8_PUPSCR_SW2ISO_SHIFT (7U) |
| #define GPC_PGC_PU8_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU8_PUPSCR_SW2ISO_MASK) |
| #define GPC_PGC_PU8_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) |
| #define GPC_PGC_PU8_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) |
| #define GPC_PGC_PU8_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU8_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU8_PDNSCR - GPC PGC Down Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU8_PDNSCR_ISO_MASK (0x3FU) |
| #define GPC_PGC_PU8_PDNSCR_ISO_SHIFT (0U) |
| #define GPC_PGC_PU8_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU8_PDNSCR_ISO_MASK) |
| #define GPC_PGC_PU8_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) |
| #define GPC_PGC_PU8_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) |
| #define GPC_PGC_PU8_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU8_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU8_PDNSCR_ISO2SW_MASK (0x3F00U) |
| #define GPC_PGC_PU8_PDNSCR_ISO2SW_SHIFT (8U) |
| #define GPC_PGC_PU8_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU8_PDNSCR_ISO2SW_MASK) |
| #define GPC_PGC_PU8_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) |
| #define GPC_PGC_PU8_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) |
| #define GPC_PGC_PU8_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU8_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) |
| #define GPC_PGC_PU8_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) |
| #define GPC_PGC_PU8_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) |
| #define GPC_PGC_PU8_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU8_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU8_SR - GPC PGC Status Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU8_SR_PSR_MASK (0x1U) |
| #define GPC_PGC_PU8_SR_PSR_SHIFT (0U) |
| /*! PSR |
| * 0b0..The target subsystem was not powered down for the previous power-down request. |
| * 0b1..The target subsystem was powered down for the previous power-down request. |
| */ |
| #define GPC_PGC_PU8_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_SR_PSR_SHIFT)) & GPC_PGC_PU8_SR_PSR_MASK) |
| #define GPC_PGC_PU8_SR_L2RETN_FLAG_MASK (0x2U) |
| #define GPC_PGC_PU8_SR_L2RETN_FLAG_SHIFT (1U) |
| /*! L2RETN_FLAG |
| * 0b0..A53 is not wakeup from L2 retention mode. |
| * 0b1..A53 is wakeup from L2 retention mode. |
| */ |
| #define GPC_PGC_PU8_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU8_SR_L2RETN_FLAG_MASK) |
| #define GPC_PGC_PU8_SR_ALLOFF_FLAG_MASK (0x4U) |
| #define GPC_PGC_PU8_SR_ALLOFF_FLAG_SHIFT (2U) |
| /*! ALLOFF_FLAG |
| * 0b0..A53 is not wakeup from ALL_OFF mode. |
| * 0b1..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU8_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU8_SR_ALLOFF_FLAG_MASK) |
| #define GPC_PGC_PU8_SR_PUP_CLK_DIV_SEL_MASK (0x78U) |
| #define GPC_PGC_PU8_SR_PUP_CLK_DIV_SEL_SHIFT (3U) |
| /*! PUP_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU8_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU8_SR_PUP_CLK_DIV_SEL_MASK) |
| #define GPC_PGC_PU8_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) |
| #define GPC_PGC_PU8_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) |
| #define GPC_PGC_PU8_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU8_SR_L2RSTDIS_DEASSERT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU8_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU8_AUXSW_SW2_MASK (0x3FU) |
| #define GPC_PGC_PU8_AUXSW_SW2_SHIFT (0U) |
| #define GPC_PGC_PU8_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_AUXSW_SW2_SHIFT)) & GPC_PGC_PU8_AUXSW_SW2_MASK) |
| #define GPC_PGC_PU8_AUXSW_ISO2SW2_MASK (0x3F00U) |
| #define GPC_PGC_PU8_AUXSW_ISO2SW2_SHIFT (8U) |
| /*! ISO2SW2 |
| * 0b000000..A53 is not wakeup from ALL_OFF mode. |
| * 0b000001..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU8_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU8_AUXSW_ISO2SW2_MASK) |
| #define GPC_PGC_PU8_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) |
| #define GPC_PGC_PU8_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) |
| /*! PDN_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU8_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU8_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU8_AUXSW_PDN_CLK_DIV_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name PU9_CTRL - GPC PGC Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU9_CTRL_PCR_MASK (0x1U) |
| #define GPC_PGC_PU9_CTRL_PCR_SHIFT (0U) |
| /*! PCR |
| * 0b0..Do not switch off power even if pdn_req is asserted. |
| * 0b1..Switch off power when pdn_req is asserted. |
| */ |
| #define GPC_PGC_PU9_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_CTRL_PCR_SHIFT)) & GPC_PGC_PU9_CTRL_PCR_MASK) |
| #define GPC_PGC_PU9_CTRL_L2RSTDIS_MASK (0x7EU) |
| #define GPC_PGC_PU9_CTRL_L2RSTDIS_SHIFT (1U) |
| #define GPC_PGC_PU9_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU9_CTRL_L2RSTDIS_MASK) |
| #define GPC_PGC_PU9_CTRL_DFTRAM_TCD1_MASK (0x3F00U) |
| #define GPC_PGC_PU9_CTRL_DFTRAM_TCD1_SHIFT (8U) |
| #define GPC_PGC_PU9_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU9_CTRL_DFTRAM_TCD1_MASK) |
| #define GPC_PGC_PU9_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) |
| #define GPC_PGC_PU9_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) |
| #define GPC_PGC_PU9_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU9_CTRL_L2RETN_TCD1_TDR_MASK) |
| #define GPC_PGC_PU9_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) |
| #define GPC_PGC_PU9_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) |
| #define GPC_PGC_PU9_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU9_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) |
| /*! @} */ |
| |
| /*! @name PU9_PUPSCR - GPC PGC Up Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU9_PUPSCR_SW_MASK (0x3FU) |
| #define GPC_PGC_PU9_PUPSCR_SW_SHIFT (0U) |
| #define GPC_PGC_PU9_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PUPSCR_SW_SHIFT)) & GPC_PGC_PU9_PUPSCR_SW_MASK) |
| #define GPC_PGC_PU9_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) |
| #define GPC_PGC_PU9_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) |
| #define GPC_PGC_PU9_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU9_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU9_PUPSCR_SW2ISO_MASK (0x7FFF80U) |
| #define GPC_PGC_PU9_PUPSCR_SW2ISO_SHIFT (7U) |
| #define GPC_PGC_PU9_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU9_PUPSCR_SW2ISO_MASK) |
| #define GPC_PGC_PU9_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) |
| #define GPC_PGC_PU9_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) |
| #define GPC_PGC_PU9_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU9_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU9_PDNSCR - GPC PGC Down Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU9_PDNSCR_ISO_MASK (0x3FU) |
| #define GPC_PGC_PU9_PDNSCR_ISO_SHIFT (0U) |
| #define GPC_PGC_PU9_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU9_PDNSCR_ISO_MASK) |
| #define GPC_PGC_PU9_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) |
| #define GPC_PGC_PU9_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) |
| #define GPC_PGC_PU9_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU9_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU9_PDNSCR_ISO2SW_MASK (0x3F00U) |
| #define GPC_PGC_PU9_PDNSCR_ISO2SW_SHIFT (8U) |
| #define GPC_PGC_PU9_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU9_PDNSCR_ISO2SW_MASK) |
| #define GPC_PGC_PU9_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) |
| #define GPC_PGC_PU9_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) |
| #define GPC_PGC_PU9_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU9_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) |
| #define GPC_PGC_PU9_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) |
| #define GPC_PGC_PU9_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) |
| #define GPC_PGC_PU9_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU9_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU9_SR - GPC PGC Status Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU9_SR_PSR_MASK (0x1U) |
| #define GPC_PGC_PU9_SR_PSR_SHIFT (0U) |
| /*! PSR |
| * 0b0..The target subsystem was not powered down for the previous power-down request. |
| * 0b1..The target subsystem was powered down for the previous power-down request. |
| */ |
| #define GPC_PGC_PU9_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_SR_PSR_SHIFT)) & GPC_PGC_PU9_SR_PSR_MASK) |
| #define GPC_PGC_PU9_SR_L2RETN_FLAG_MASK (0x2U) |
| #define GPC_PGC_PU9_SR_L2RETN_FLAG_SHIFT (1U) |
| /*! L2RETN_FLAG |
| * 0b0..A53 is not wakeup from L2 retention mode. |
| * 0b1..A53 is wakeup from L2 retention mode. |
| */ |
| #define GPC_PGC_PU9_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU9_SR_L2RETN_FLAG_MASK) |
| #define GPC_PGC_PU9_SR_ALLOFF_FLAG_MASK (0x4U) |
| #define GPC_PGC_PU9_SR_ALLOFF_FLAG_SHIFT (2U) |
| /*! ALLOFF_FLAG |
| * 0b0..A53 is not wakeup from ALL_OFF mode. |
| * 0b1..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU9_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU9_SR_ALLOFF_FLAG_MASK) |
| #define GPC_PGC_PU9_SR_PUP_CLK_DIV_SEL_MASK (0x78U) |
| #define GPC_PGC_PU9_SR_PUP_CLK_DIV_SEL_SHIFT (3U) |
| /*! PUP_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU9_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU9_SR_PUP_CLK_DIV_SEL_MASK) |
| #define GPC_PGC_PU9_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) |
| #define GPC_PGC_PU9_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) |
| #define GPC_PGC_PU9_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU9_SR_L2RSTDIS_DEASSERT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU9_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU9_AUXSW_SW2_MASK (0x3FU) |
| #define GPC_PGC_PU9_AUXSW_SW2_SHIFT (0U) |
| #define GPC_PGC_PU9_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_AUXSW_SW2_SHIFT)) & GPC_PGC_PU9_AUXSW_SW2_MASK) |
| #define GPC_PGC_PU9_AUXSW_ISO2SW2_MASK (0x3F00U) |
| #define GPC_PGC_PU9_AUXSW_ISO2SW2_SHIFT (8U) |
| /*! ISO2SW2 |
| * 0b000000..A53 is not wakeup from ALL_OFF mode. |
| * 0b000001..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU9_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU9_AUXSW_ISO2SW2_MASK) |
| #define GPC_PGC_PU9_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) |
| #define GPC_PGC_PU9_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) |
| /*! PDN_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU9_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU9_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU9_AUXSW_PDN_CLK_DIV_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name PU10_CTRL - GPC PGC Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU10_CTRL_PCR_MASK (0x1U) |
| #define GPC_PGC_PU10_CTRL_PCR_SHIFT (0U) |
| /*! PCR |
| * 0b0..Do not switch off power even if pdn_req is asserted. |
| * 0b1..Switch off power when pdn_req is asserted. |
| */ |
| #define GPC_PGC_PU10_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_CTRL_PCR_SHIFT)) & GPC_PGC_PU10_CTRL_PCR_MASK) |
| #define GPC_PGC_PU10_CTRL_L2RSTDIS_MASK (0x7EU) |
| #define GPC_PGC_PU10_CTRL_L2RSTDIS_SHIFT (1U) |
| #define GPC_PGC_PU10_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU10_CTRL_L2RSTDIS_MASK) |
| #define GPC_PGC_PU10_CTRL_DFTRAM_TCD1_MASK (0x3F00U) |
| #define GPC_PGC_PU10_CTRL_DFTRAM_TCD1_SHIFT (8U) |
| #define GPC_PGC_PU10_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU10_CTRL_DFTRAM_TCD1_MASK) |
| #define GPC_PGC_PU10_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) |
| #define GPC_PGC_PU10_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) |
| #define GPC_PGC_PU10_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU10_CTRL_L2RETN_TCD1_TDR_MASK) |
| #define GPC_PGC_PU10_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) |
| #define GPC_PGC_PU10_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) |
| #define GPC_PGC_PU10_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU10_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) |
| /*! @} */ |
| |
| /*! @name PU10_PUPSCR - GPC PGC Up Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU10_PUPSCR_SW_MASK (0x3FU) |
| #define GPC_PGC_PU10_PUPSCR_SW_SHIFT (0U) |
| #define GPC_PGC_PU10_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PUPSCR_SW_SHIFT)) & GPC_PGC_PU10_PUPSCR_SW_MASK) |
| #define GPC_PGC_PU10_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) |
| #define GPC_PGC_PU10_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) |
| #define GPC_PGC_PU10_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU10_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU10_PUPSCR_SW2ISO_MASK (0x7FFF80U) |
| #define GPC_PGC_PU10_PUPSCR_SW2ISO_SHIFT (7U) |
| #define GPC_PGC_PU10_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU10_PUPSCR_SW2ISO_MASK) |
| #define GPC_PGC_PU10_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) |
| #define GPC_PGC_PU10_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) |
| #define GPC_PGC_PU10_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU10_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU10_PDNSCR - GPC PGC Down Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU10_PDNSCR_ISO_MASK (0x3FU) |
| #define GPC_PGC_PU10_PDNSCR_ISO_SHIFT (0U) |
| #define GPC_PGC_PU10_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU10_PDNSCR_ISO_MASK) |
| #define GPC_PGC_PU10_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) |
| #define GPC_PGC_PU10_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) |
| #define GPC_PGC_PU10_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU10_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU10_PDNSCR_ISO2SW_MASK (0x3F00U) |
| #define GPC_PGC_PU10_PDNSCR_ISO2SW_SHIFT (8U) |
| #define GPC_PGC_PU10_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU10_PDNSCR_ISO2SW_MASK) |
| #define GPC_PGC_PU10_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) |
| #define GPC_PGC_PU10_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) |
| #define GPC_PGC_PU10_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU10_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) |
| #define GPC_PGC_PU10_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) |
| #define GPC_PGC_PU10_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) |
| #define GPC_PGC_PU10_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU10_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU10_SR - GPC PGC Status Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU10_SR_PSR_MASK (0x1U) |
| #define GPC_PGC_PU10_SR_PSR_SHIFT (0U) |
| /*! PSR |
| * 0b0..The target subsystem was not powered down for the previous power-down request. |
| * 0b1..The target subsystem was powered down for the previous power-down request. |
| */ |
| #define GPC_PGC_PU10_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_SR_PSR_SHIFT)) & GPC_PGC_PU10_SR_PSR_MASK) |
| #define GPC_PGC_PU10_SR_L2RETN_FLAG_MASK (0x2U) |
| #define GPC_PGC_PU10_SR_L2RETN_FLAG_SHIFT (1U) |
| /*! L2RETN_FLAG |
| * 0b0..A53 is not wakeup from L2 retention mode. |
| * 0b1..A53 is wakeup from L2 retention mode. |
| */ |
| #define GPC_PGC_PU10_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU10_SR_L2RETN_FLAG_MASK) |
| #define GPC_PGC_PU10_SR_ALLOFF_FLAG_MASK (0x4U) |
| #define GPC_PGC_PU10_SR_ALLOFF_FLAG_SHIFT (2U) |
| /*! ALLOFF_FLAG |
| * 0b0..A53 is not wakeup from ALL_OFF mode. |
| * 0b1..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU10_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU10_SR_ALLOFF_FLAG_MASK) |
| #define GPC_PGC_PU10_SR_PUP_CLK_DIV_SEL_MASK (0x78U) |
| #define GPC_PGC_PU10_SR_PUP_CLK_DIV_SEL_SHIFT (3U) |
| /*! PUP_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU10_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU10_SR_PUP_CLK_DIV_SEL_MASK) |
| #define GPC_PGC_PU10_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) |
| #define GPC_PGC_PU10_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) |
| #define GPC_PGC_PU10_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU10_SR_L2RSTDIS_DEASSERT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU10_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU10_AUXSW_SW2_MASK (0x3FU) |
| #define GPC_PGC_PU10_AUXSW_SW2_SHIFT (0U) |
| #define GPC_PGC_PU10_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_AUXSW_SW2_SHIFT)) & GPC_PGC_PU10_AUXSW_SW2_MASK) |
| #define GPC_PGC_PU10_AUXSW_ISO2SW2_MASK (0x3F00U) |
| #define GPC_PGC_PU10_AUXSW_ISO2SW2_SHIFT (8U) |
| /*! ISO2SW2 |
| * 0b000000..A53 is not wakeup from ALL_OFF mode. |
| * 0b000001..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU10_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU10_AUXSW_ISO2SW2_MASK) |
| #define GPC_PGC_PU10_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) |
| #define GPC_PGC_PU10_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) |
| /*! PDN_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU10_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU10_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU10_AUXSW_PDN_CLK_DIV_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name PU11_CTRL - GPC PGC Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU11_CTRL_PCR_MASK (0x1U) |
| #define GPC_PGC_PU11_CTRL_PCR_SHIFT (0U) |
| /*! PCR |
| * 0b0..Do not switch off power even if pdn_req is asserted. |
| * 0b1..Switch off power when pdn_req is asserted. |
| */ |
| #define GPC_PGC_PU11_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_CTRL_PCR_SHIFT)) & GPC_PGC_PU11_CTRL_PCR_MASK) |
| #define GPC_PGC_PU11_CTRL_L2RSTDIS_MASK (0x7EU) |
| #define GPC_PGC_PU11_CTRL_L2RSTDIS_SHIFT (1U) |
| #define GPC_PGC_PU11_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU11_CTRL_L2RSTDIS_MASK) |
| #define GPC_PGC_PU11_CTRL_DFTRAM_TCD1_MASK (0x3F00U) |
| #define GPC_PGC_PU11_CTRL_DFTRAM_TCD1_SHIFT (8U) |
| #define GPC_PGC_PU11_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU11_CTRL_DFTRAM_TCD1_MASK) |
| #define GPC_PGC_PU11_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) |
| #define GPC_PGC_PU11_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) |
| #define GPC_PGC_PU11_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU11_CTRL_L2RETN_TCD1_TDR_MASK) |
| #define GPC_PGC_PU11_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) |
| #define GPC_PGC_PU11_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) |
| #define GPC_PGC_PU11_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU11_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) |
| /*! @} */ |
| |
| /*! @name PU11_PUPSCR - GPC PGC Up Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU11_PUPSCR_SW_MASK (0x3FU) |
| #define GPC_PGC_PU11_PUPSCR_SW_SHIFT (0U) |
| #define GPC_PGC_PU11_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PUPSCR_SW_SHIFT)) & GPC_PGC_PU11_PUPSCR_SW_MASK) |
| #define GPC_PGC_PU11_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) |
| #define GPC_PGC_PU11_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) |
| #define GPC_PGC_PU11_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU11_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU11_PUPSCR_SW2ISO_MASK (0x7FFF80U) |
| #define GPC_PGC_PU11_PUPSCR_SW2ISO_SHIFT (7U) |
| #define GPC_PGC_PU11_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU11_PUPSCR_SW2ISO_MASK) |
| #define GPC_PGC_PU11_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) |
| #define GPC_PGC_PU11_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) |
| #define GPC_PGC_PU11_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU11_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU11_PDNSCR - GPC PGC Down Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU11_PDNSCR_ISO_MASK (0x3FU) |
| #define GPC_PGC_PU11_PDNSCR_ISO_SHIFT (0U) |
| #define GPC_PGC_PU11_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU11_PDNSCR_ISO_MASK) |
| #define GPC_PGC_PU11_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) |
| #define GPC_PGC_PU11_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) |
| #define GPC_PGC_PU11_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU11_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU11_PDNSCR_ISO2SW_MASK (0x3F00U) |
| #define GPC_PGC_PU11_PDNSCR_ISO2SW_SHIFT (8U) |
| #define GPC_PGC_PU11_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU11_PDNSCR_ISO2SW_MASK) |
| #define GPC_PGC_PU11_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) |
| #define GPC_PGC_PU11_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) |
| #define GPC_PGC_PU11_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU11_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) |
| #define GPC_PGC_PU11_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) |
| #define GPC_PGC_PU11_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) |
| #define GPC_PGC_PU11_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU11_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU11_SR - GPC PGC Status Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU11_SR_PSR_MASK (0x1U) |
| #define GPC_PGC_PU11_SR_PSR_SHIFT (0U) |
| /*! PSR |
| * 0b0..The target subsystem was not powered down for the previous power-down request. |
| * 0b1..The target subsystem was powered down for the previous power-down request. |
| */ |
| #define GPC_PGC_PU11_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_SR_PSR_SHIFT)) & GPC_PGC_PU11_SR_PSR_MASK) |
| #define GPC_PGC_PU11_SR_L2RETN_FLAG_MASK (0x2U) |
| #define GPC_PGC_PU11_SR_L2RETN_FLAG_SHIFT (1U) |
| /*! L2RETN_FLAG |
| * 0b0..A53 is not wakeup from L2 retention mode. |
| * 0b1..A53 is wakeup from L2 retention mode. |
| */ |
| #define GPC_PGC_PU11_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU11_SR_L2RETN_FLAG_MASK) |
| #define GPC_PGC_PU11_SR_ALLOFF_FLAG_MASK (0x4U) |
| #define GPC_PGC_PU11_SR_ALLOFF_FLAG_SHIFT (2U) |
| /*! ALLOFF_FLAG |
| * 0b0..A53 is not wakeup from ALL_OFF mode. |
| * 0b1..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU11_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU11_SR_ALLOFF_FLAG_MASK) |
| #define GPC_PGC_PU11_SR_PUP_CLK_DIV_SEL_MASK (0x78U) |
| #define GPC_PGC_PU11_SR_PUP_CLK_DIV_SEL_SHIFT (3U) |
| /*! PUP_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU11_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU11_SR_PUP_CLK_DIV_SEL_MASK) |
| #define GPC_PGC_PU11_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) |
| #define GPC_PGC_PU11_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) |
| #define GPC_PGC_PU11_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU11_SR_L2RSTDIS_DEASSERT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU11_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU11_AUXSW_SW2_MASK (0x3FU) |
| #define GPC_PGC_PU11_AUXSW_SW2_SHIFT (0U) |
| #define GPC_PGC_PU11_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_AUXSW_SW2_SHIFT)) & GPC_PGC_PU11_AUXSW_SW2_MASK) |
| #define GPC_PGC_PU11_AUXSW_ISO2SW2_MASK (0x3F00U) |
| #define GPC_PGC_PU11_AUXSW_ISO2SW2_SHIFT (8U) |
| /*! ISO2SW2 |
| * 0b000000..A53 is not wakeup from ALL_OFF mode. |
| * 0b000001..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU11_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU11_AUXSW_ISO2SW2_MASK) |
| #define GPC_PGC_PU11_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) |
| #define GPC_PGC_PU11_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) |
| /*! PDN_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU11_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU11_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU11_AUXSW_PDN_CLK_DIV_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name PU12_CTRL - GPC PGC Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU12_CTRL_PCR_MASK (0x1U) |
| #define GPC_PGC_PU12_CTRL_PCR_SHIFT (0U) |
| /*! PCR |
| * 0b0..Do not switch off power even if pdn_req is asserted. |
| * 0b1..Switch off power when pdn_req is asserted. |
| */ |
| #define GPC_PGC_PU12_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_CTRL_PCR_SHIFT)) & GPC_PGC_PU12_CTRL_PCR_MASK) |
| #define GPC_PGC_PU12_CTRL_L2RSTDIS_MASK (0x7EU) |
| #define GPC_PGC_PU12_CTRL_L2RSTDIS_SHIFT (1U) |
| #define GPC_PGC_PU12_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU12_CTRL_L2RSTDIS_MASK) |
| #define GPC_PGC_PU12_CTRL_DFTRAM_TCD1_MASK (0x3F00U) |
| #define GPC_PGC_PU12_CTRL_DFTRAM_TCD1_SHIFT (8U) |
| #define GPC_PGC_PU12_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU12_CTRL_DFTRAM_TCD1_MASK) |
| #define GPC_PGC_PU12_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) |
| #define GPC_PGC_PU12_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) |
| #define GPC_PGC_PU12_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU12_CTRL_L2RETN_TCD1_TDR_MASK) |
| #define GPC_PGC_PU12_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) |
| #define GPC_PGC_PU12_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) |
| #define GPC_PGC_PU12_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU12_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) |
| /*! @} */ |
| |
| /*! @name PU12_PUPSCR - GPC PGC Up Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU12_PUPSCR_SW_MASK (0x3FU) |
| #define GPC_PGC_PU12_PUPSCR_SW_SHIFT (0U) |
| #define GPC_PGC_PU12_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PUPSCR_SW_SHIFT)) & GPC_PGC_PU12_PUPSCR_SW_MASK) |
| #define GPC_PGC_PU12_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) |
| #define GPC_PGC_PU12_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) |
| #define GPC_PGC_PU12_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU12_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU12_PUPSCR_SW2ISO_MASK (0x7FFF80U) |
| #define GPC_PGC_PU12_PUPSCR_SW2ISO_SHIFT (7U) |
| #define GPC_PGC_PU12_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU12_PUPSCR_SW2ISO_MASK) |
| #define GPC_PGC_PU12_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) |
| #define GPC_PGC_PU12_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) |
| #define GPC_PGC_PU12_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU12_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU12_PDNSCR - GPC PGC Down Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU12_PDNSCR_ISO_MASK (0x3FU) |
| #define GPC_PGC_PU12_PDNSCR_ISO_SHIFT (0U) |
| #define GPC_PGC_PU12_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU12_PDNSCR_ISO_MASK) |
| #define GPC_PGC_PU12_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) |
| #define GPC_PGC_PU12_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) |
| #define GPC_PGC_PU12_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU12_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU12_PDNSCR_ISO2SW_MASK (0x3F00U) |
| #define GPC_PGC_PU12_PDNSCR_ISO2SW_SHIFT (8U) |
| #define GPC_PGC_PU12_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU12_PDNSCR_ISO2SW_MASK) |
| #define GPC_PGC_PU12_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) |
| #define GPC_PGC_PU12_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) |
| #define GPC_PGC_PU12_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU12_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) |
| #define GPC_PGC_PU12_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) |
| #define GPC_PGC_PU12_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) |
| #define GPC_PGC_PU12_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU12_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU12_SR - GPC PGC Status Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU12_SR_PSR_MASK (0x1U) |
| #define GPC_PGC_PU12_SR_PSR_SHIFT (0U) |
| /*! PSR |
| * 0b0..The target subsystem was not powered down for the previous power-down request. |
| * 0b1..The target subsystem was powered down for the previous power-down request. |
| */ |
| #define GPC_PGC_PU12_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_SR_PSR_SHIFT)) & GPC_PGC_PU12_SR_PSR_MASK) |
| #define GPC_PGC_PU12_SR_L2RETN_FLAG_MASK (0x2U) |
| #define GPC_PGC_PU12_SR_L2RETN_FLAG_SHIFT (1U) |
| /*! L2RETN_FLAG |
| * 0b0..A53 is not wakeup from L2 retention mode. |
| * 0b1..A53 is wakeup from L2 retention mode. |
| */ |
| #define GPC_PGC_PU12_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU12_SR_L2RETN_FLAG_MASK) |
| #define GPC_PGC_PU12_SR_ALLOFF_FLAG_MASK (0x4U) |
| #define GPC_PGC_PU12_SR_ALLOFF_FLAG_SHIFT (2U) |
| /*! ALLOFF_FLAG |
| * 0b0..A53 is not wakeup from ALL_OFF mode. |
| * 0b1..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU12_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU12_SR_ALLOFF_FLAG_MASK) |
| #define GPC_PGC_PU12_SR_PUP_CLK_DIV_SEL_MASK (0x78U) |
| #define GPC_PGC_PU12_SR_PUP_CLK_DIV_SEL_SHIFT (3U) |
| /*! PUP_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU12_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU12_SR_PUP_CLK_DIV_SEL_MASK) |
| #define GPC_PGC_PU12_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) |
| #define GPC_PGC_PU12_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) |
| #define GPC_PGC_PU12_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU12_SR_L2RSTDIS_DEASSERT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU12_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU12_AUXSW_SW2_MASK (0x3FU) |
| #define GPC_PGC_PU12_AUXSW_SW2_SHIFT (0U) |
| #define GPC_PGC_PU12_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_AUXSW_SW2_SHIFT)) & GPC_PGC_PU12_AUXSW_SW2_MASK) |
| #define GPC_PGC_PU12_AUXSW_ISO2SW2_MASK (0x3F00U) |
| #define GPC_PGC_PU12_AUXSW_ISO2SW2_SHIFT (8U) |
| /*! ISO2SW2 |
| * 0b000000..A53 is not wakeup from ALL_OFF mode. |
| * 0b000001..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU12_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU12_AUXSW_ISO2SW2_MASK) |
| #define GPC_PGC_PU12_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) |
| #define GPC_PGC_PU12_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) |
| /*! PDN_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU12_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU12_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU12_AUXSW_PDN_CLK_DIV_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name PU13_CTRL - GPC PGC Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU13_CTRL_PCR_MASK (0x1U) |
| #define GPC_PGC_PU13_CTRL_PCR_SHIFT (0U) |
| /*! PCR |
| * 0b0..Do not switch off power even if pdn_req is asserted. |
| * 0b1..Switch off power when pdn_req is asserted. |
| */ |
| #define GPC_PGC_PU13_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_CTRL_PCR_SHIFT)) & GPC_PGC_PU13_CTRL_PCR_MASK) |
| #define GPC_PGC_PU13_CTRL_L2RSTDIS_MASK (0x7EU) |
| #define GPC_PGC_PU13_CTRL_L2RSTDIS_SHIFT (1U) |
| #define GPC_PGC_PU13_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU13_CTRL_L2RSTDIS_MASK) |
| #define GPC_PGC_PU13_CTRL_DFTRAM_TCD1_MASK (0x3F00U) |
| #define GPC_PGC_PU13_CTRL_DFTRAM_TCD1_SHIFT (8U) |
| #define GPC_PGC_PU13_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU13_CTRL_DFTRAM_TCD1_MASK) |
| #define GPC_PGC_PU13_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U) |
| #define GPC_PGC_PU13_CTRL_L2RETN_TCD1_TDR_SHIFT (16U) |
| #define GPC_PGC_PU13_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU13_CTRL_L2RETN_TCD1_TDR_MASK) |
| #define GPC_PGC_PU13_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U) |
| #define GPC_PGC_PU13_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U) |
| #define GPC_PGC_PU13_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU13_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) |
| /*! @} */ |
| |
| /*! @name PU13_PUPSCR - GPC PGC Up Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU13_PUPSCR_SW_MASK (0x3FU) |
| #define GPC_PGC_PU13_PUPSCR_SW_SHIFT (0U) |
| #define GPC_PGC_PU13_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PUPSCR_SW_SHIFT)) & GPC_PGC_PU13_PUPSCR_SW_MASK) |
| #define GPC_PGC_PU13_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U) |
| #define GPC_PGC_PU13_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U) |
| #define GPC_PGC_PU13_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU13_PUPSCR_PUP_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU13_PUPSCR_SW2ISO_MASK (0x7FFF80U) |
| #define GPC_PGC_PU13_PUPSCR_SW2ISO_SHIFT (7U) |
| #define GPC_PGC_PU13_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU13_PUPSCR_SW2ISO_MASK) |
| #define GPC_PGC_PU13_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK (0xFF800000U) |
| #define GPC_PGC_PU13_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT (23U) |
| #define GPC_PGC_PU13_PUPSCR_PUP_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PUPSCR_PUP_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU13_PUPSCR_PUP_SCALL_SCALLOUT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU13_PDNSCR - GPC PGC Down Sequence Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU13_PDNSCR_ISO_MASK (0x3FU) |
| #define GPC_PGC_PU13_PDNSCR_ISO_SHIFT (0U) |
| #define GPC_PGC_PU13_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU13_PDNSCR_ISO_MASK) |
| #define GPC_PGC_PU13_PDNSCR_PDN_WAIT_SCALL_OUT_MASK (0x80U) |
| #define GPC_PGC_PU13_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT (7U) |
| #define GPC_PGC_PU13_PDNSCR_PDN_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PDNSCR_PDN_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_PU13_PDNSCR_PDN_WAIT_SCALL_OUT_MASK) |
| #define GPC_PGC_PU13_PDNSCR_ISO2SW_MASK (0x3F00U) |
| #define GPC_PGC_PU13_PDNSCR_ISO2SW_SHIFT (8U) |
| #define GPC_PGC_PU13_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU13_PDNSCR_ISO2SW_MASK) |
| #define GPC_PGC_PU13_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK (0xFF0000U) |
| #define GPC_PGC_PU13_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT (16U) |
| #define GPC_PGC_PU13_PDNSCR_PDN_SCALL_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PDNSCR_PDN_SCALL_SCALLOUT_CNT_SHIFT)) & GPC_PGC_PU13_PDNSCR_PDN_SCALL_SCALLOUT_CNT_MASK) |
| #define GPC_PGC_PU13_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK (0xFF000000U) |
| #define GPC_PGC_PU13_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT (24U) |
| #define GPC_PGC_PU13_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT)) & GPC_PGC_PU13_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU13_SR - GPC PGC Status Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU13_SR_PSR_MASK (0x1U) |
| #define GPC_PGC_PU13_SR_PSR_SHIFT (0U) |
| /*! PSR |
| * 0b0..The target subsystem was not powered down for the previous power-down request. |
| * 0b1..The target subsystem was powered down for the previous power-down request. |
| */ |
| #define GPC_PGC_PU13_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_SR_PSR_SHIFT)) & GPC_PGC_PU13_SR_PSR_MASK) |
| #define GPC_PGC_PU13_SR_L2RETN_FLAG_MASK (0x2U) |
| #define GPC_PGC_PU13_SR_L2RETN_FLAG_SHIFT (1U) |
| /*! L2RETN_FLAG |
| * 0b0..A53 is not wakeup from L2 retention mode. |
| * 0b1..A53 is wakeup from L2 retention mode. |
| */ |
| #define GPC_PGC_PU13_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU13_SR_L2RETN_FLAG_MASK) |
| #define GPC_PGC_PU13_SR_ALLOFF_FLAG_MASK (0x4U) |
| #define GPC_PGC_PU13_SR_ALLOFF_FLAG_SHIFT (2U) |
| /*! ALLOFF_FLAG |
| * 0b0..A53 is not wakeup from ALL_OFF mode. |
| * 0b1..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU13_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU13_SR_ALLOFF_FLAG_MASK) |
| #define GPC_PGC_PU13_SR_PUP_CLK_DIV_SEL_MASK (0x78U) |
| #define GPC_PGC_PU13_SR_PUP_CLK_DIV_SEL_SHIFT (3U) |
| /*! PUP_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU13_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU13_SR_PUP_CLK_DIV_SEL_MASK) |
| #define GPC_PGC_PU13_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U) |
| #define GPC_PGC_PU13_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U) |
| #define GPC_PGC_PU13_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU13_SR_L2RSTDIS_DEASSERT_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name PU13_AUXSW - GPC PGC Auxiliary Power Switch Control Register */ |
| /*! @{ */ |
| #define GPC_PGC_PU13_AUXSW_SW2_MASK (0x3FU) |
| #define GPC_PGC_PU13_AUXSW_SW2_SHIFT (0U) |
| #define GPC_PGC_PU13_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_AUXSW_SW2_SHIFT)) & GPC_PGC_PU13_AUXSW_SW2_MASK) |
| #define GPC_PGC_PU13_AUXSW_ISO2SW2_MASK (0x3F00U) |
| #define GPC_PGC_PU13_AUXSW_ISO2SW2_SHIFT (8U) |
| /*! ISO2SW2 |
| * 0b000000..A53 is not wakeup from ALL_OFF mode. |
| * 0b000001..A53 is wakeup from ALL_OFF mode. |
| */ |
| #define GPC_PGC_PU13_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_AUXSW_ISO2SW2_SHIFT)) & GPC_PGC_PU13_AUXSW_ISO2SW2_MASK) |
| #define GPC_PGC_PU13_AUXSW_PDN_CLK_DIV_SEL_MASK (0xF0000U) |
| #define GPC_PGC_PU13_AUXSW_PDN_CLK_DIV_SEL_SHIFT (16U) |
| /*! PDN_CLK_DIV_SEL |
| * 0b0000..1 |
| * 0b0001..1/2 count_clk |
| * 0b0010..1/4 count_clk |
| * 0b0011..1/8 count_clk |
| * 0b0100..1/16 count_clk |
| * 0b0101..1/32 count_clk |
| * 0b0110..1/64 count_clk |
| * 0b0111..1/128 count_clk |
| * 0b1000..1/256 count_clk |
| * 0b1001..1/512 count_clk |
| * 0b1010..1/1024 count_clk |
| * 0b1011..1/2056 count_clk |
| * 0b1100..1/4096 count_clk |
| * 0b1101..1/8192 count_clk |
| * 0b1110..1/16384 count_clk |
| * 0b1111..1/32768 count_clk |
| */ |
| #define GPC_PGC_PU13_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU13_AUXSW_PDN_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU13_AUXSW_PDN_CLK_DIV_SEL_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group GPC_PGC_Register_Masks */ |
| |
| |
| /* GPC_PGC - Peripheral instance base addresses */ |
| /** Peripheral GPC_PGC base address */ |
| #define GPC_PGC_BASE (0x303A0800u) |
| /** Peripheral GPC_PGC base pointer */ |
| #define GPC_PGC ((GPC_PGC_Type *)GPC_PGC_BASE) |
| /** Array initializer of GPC_PGC peripheral base addresses */ |
| #define GPC_PGC_BASE_ADDRS { GPC_PGC_BASE } |
| /** Array initializer of GPC_PGC peripheral base pointers */ |
| #define GPC_PGC_BASE_PTRS { GPC_PGC } |
| |
| /*! |
| * @} |
| */ /* end of group GPC_PGC_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPIO Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** GPIO - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ |
| __IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */ |
| __I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */ |
| __IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */ |
| __IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */ |
| __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ |
| __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */ |
| __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */ |
| } GPIO_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPIO Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPIO_Register_Masks GPIO Register Masks |
| * @{ |
| */ |
| |
| /*! @name DR - GPIO data register */ |
| /*! @{ */ |
| #define GPIO_DR_DR_MASK (0xFFFFFFFFU) |
| #define GPIO_DR_DR_SHIFT (0U) |
| #define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK) |
| /*! @} */ |
| |
| /*! @name GDIR - GPIO direction register */ |
| /*! @{ */ |
| #define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU) |
| #define GPIO_GDIR_GDIR_SHIFT (0U) |
| /*! GDIR |
| * 0b00000000000000000000000000000000..GPIO is configured as input. |
| * 0b00000000000000000000000000000001..GPIO is configured as output. |
| */ |
| #define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK) |
| /*! @} */ |
| |
| /*! @name PSR - GPIO pad status register */ |
| /*! @{ */ |
| #define GPIO_PSR_PSR_MASK (0xFFFFFFFFU) |
| #define GPIO_PSR_PSR_SHIFT (0U) |
| #define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK) |
| /*! @} */ |
| |
| /*! @name ICR1 - GPIO interrupt configuration register1 */ |
| /*! @{ */ |
| #define GPIO_ICR1_ICR0_MASK (0x3U) |
| #define GPIO_ICR1_ICR0_SHIFT (0U) |
| /*! ICR0 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK) |
| #define GPIO_ICR1_ICR1_MASK (0xCU) |
| #define GPIO_ICR1_ICR1_SHIFT (2U) |
| /*! ICR1 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK) |
| #define GPIO_ICR1_ICR2_MASK (0x30U) |
| #define GPIO_ICR1_ICR2_SHIFT (4U) |
| /*! ICR2 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK) |
| #define GPIO_ICR1_ICR3_MASK (0xC0U) |
| #define GPIO_ICR1_ICR3_SHIFT (6U) |
| /*! ICR3 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK) |
| #define GPIO_ICR1_ICR4_MASK (0x300U) |
| #define GPIO_ICR1_ICR4_SHIFT (8U) |
| /*! ICR4 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK) |
| #define GPIO_ICR1_ICR5_MASK (0xC00U) |
| #define GPIO_ICR1_ICR5_SHIFT (10U) |
| /*! ICR5 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK) |
| #define GPIO_ICR1_ICR6_MASK (0x3000U) |
| #define GPIO_ICR1_ICR6_SHIFT (12U) |
| /*! ICR6 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK) |
| #define GPIO_ICR1_ICR7_MASK (0xC000U) |
| #define GPIO_ICR1_ICR7_SHIFT (14U) |
| /*! ICR7 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK) |
| #define GPIO_ICR1_ICR8_MASK (0x30000U) |
| #define GPIO_ICR1_ICR8_SHIFT (16U) |
| /*! ICR8 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK) |
| #define GPIO_ICR1_ICR9_MASK (0xC0000U) |
| #define GPIO_ICR1_ICR9_SHIFT (18U) |
| /*! ICR9 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK) |
| #define GPIO_ICR1_ICR10_MASK (0x300000U) |
| #define GPIO_ICR1_ICR10_SHIFT (20U) |
| /*! ICR10 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK) |
| #define GPIO_ICR1_ICR11_MASK (0xC00000U) |
| #define GPIO_ICR1_ICR11_SHIFT (22U) |
| /*! ICR11 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK) |
| #define GPIO_ICR1_ICR12_MASK (0x3000000U) |
| #define GPIO_ICR1_ICR12_SHIFT (24U) |
| /*! ICR12 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK) |
| #define GPIO_ICR1_ICR13_MASK (0xC000000U) |
| #define GPIO_ICR1_ICR13_SHIFT (26U) |
| /*! ICR13 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK) |
| #define GPIO_ICR1_ICR14_MASK (0x30000000U) |
| #define GPIO_ICR1_ICR14_SHIFT (28U) |
| /*! ICR14 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK) |
| #define GPIO_ICR1_ICR15_MASK (0xC0000000U) |
| #define GPIO_ICR1_ICR15_SHIFT (30U) |
| /*! ICR15 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK) |
| /*! @} */ |
| |
| /*! @name ICR2 - GPIO interrupt configuration register2 */ |
| /*! @{ */ |
| #define GPIO_ICR2_ICR16_MASK (0x3U) |
| #define GPIO_ICR2_ICR16_SHIFT (0U) |
| /*! ICR16 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK) |
| #define GPIO_ICR2_ICR17_MASK (0xCU) |
| #define GPIO_ICR2_ICR17_SHIFT (2U) |
| /*! ICR17 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK) |
| #define GPIO_ICR2_ICR18_MASK (0x30U) |
| #define GPIO_ICR2_ICR18_SHIFT (4U) |
| /*! ICR18 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK) |
| #define GPIO_ICR2_ICR19_MASK (0xC0U) |
| #define GPIO_ICR2_ICR19_SHIFT (6U) |
| /*! ICR19 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK) |
| #define GPIO_ICR2_ICR20_MASK (0x300U) |
| #define GPIO_ICR2_ICR20_SHIFT (8U) |
| /*! ICR20 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK) |
| #define GPIO_ICR2_ICR21_MASK (0xC00U) |
| #define GPIO_ICR2_ICR21_SHIFT (10U) |
| /*! ICR21 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK) |
| #define GPIO_ICR2_ICR22_MASK (0x3000U) |
| #define GPIO_ICR2_ICR22_SHIFT (12U) |
| /*! ICR22 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK) |
| #define GPIO_ICR2_ICR23_MASK (0xC000U) |
| #define GPIO_ICR2_ICR23_SHIFT (14U) |
| /*! ICR23 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK) |
| #define GPIO_ICR2_ICR24_MASK (0x30000U) |
| #define GPIO_ICR2_ICR24_SHIFT (16U) |
| /*! ICR24 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK) |
| #define GPIO_ICR2_ICR25_MASK (0xC0000U) |
| #define GPIO_ICR2_ICR25_SHIFT (18U) |
| /*! ICR25 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK) |
| #define GPIO_ICR2_ICR26_MASK (0x300000U) |
| #define GPIO_ICR2_ICR26_SHIFT (20U) |
| /*! ICR26 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK) |
| #define GPIO_ICR2_ICR27_MASK (0xC00000U) |
| #define GPIO_ICR2_ICR27_SHIFT (22U) |
| /*! ICR27 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK) |
| #define GPIO_ICR2_ICR28_MASK (0x3000000U) |
| #define GPIO_ICR2_ICR28_SHIFT (24U) |
| /*! ICR28 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK) |
| #define GPIO_ICR2_ICR29_MASK (0xC000000U) |
| #define GPIO_ICR2_ICR29_SHIFT (26U) |
| /*! ICR29 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK) |
| #define GPIO_ICR2_ICR30_MASK (0x30000000U) |
| #define GPIO_ICR2_ICR30_SHIFT (28U) |
| /*! ICR30 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK) |
| #define GPIO_ICR2_ICR31_MASK (0xC0000000U) |
| #define GPIO_ICR2_ICR31_SHIFT (30U) |
| /*! ICR31 |
| * 0b00..Interrupt n is low-level sensitive. |
| * 0b01..Interrupt n is high-level sensitive. |
| * 0b10..Interrupt n is rising-edge sensitive. |
| * 0b11..Interrupt n is falling-edge sensitive. |
| */ |
| #define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK) |
| /*! @} */ |
| |
| /*! @name IMR - GPIO interrupt mask register */ |
| /*! @{ */ |
| #define GPIO_IMR_IMR_MASK (0xFFFFFFFFU) |
| #define GPIO_IMR_IMR_SHIFT (0U) |
| /*! IMR |
| * 0b00000000000000000000000000000000..Interrupt n is disabled. |
| * 0b00000000000000000000000000000001..Interrupt n is enabled. |
| */ |
| #define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK) |
| /*! @} */ |
| |
| /*! @name ISR - GPIO interrupt status register */ |
| /*! @{ */ |
| #define GPIO_ISR_ISR_MASK (0xFFFFFFFFU) |
| #define GPIO_ISR_ISR_SHIFT (0U) |
| #define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK) |
| /*! @} */ |
| |
| /*! @name EDGE_SEL - GPIO edge select register */ |
| /*! @{ */ |
| #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU) |
| #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U) |
| #define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group GPIO_Register_Masks */ |
| |
| |
| /* GPIO - Peripheral instance base addresses */ |
| /** Peripheral GPIO1 base address */ |
| #define GPIO1_BASE (0x30200000u) |
| /** Peripheral GPIO1 base pointer */ |
| #define GPIO1 ((GPIO_Type *)GPIO1_BASE) |
| /** Peripheral GPIO2 base address */ |
| #define GPIO2_BASE (0x30210000u) |
| /** Peripheral GPIO2 base pointer */ |
| #define GPIO2 ((GPIO_Type *)GPIO2_BASE) |
| /** Peripheral GPIO3 base address */ |
| #define GPIO3_BASE (0x30220000u) |
| /** Peripheral GPIO3 base pointer */ |
| #define GPIO3 ((GPIO_Type *)GPIO3_BASE) |
| /** Peripheral GPIO4 base address */ |
| #define GPIO4_BASE (0x30230000u) |
| /** Peripheral GPIO4 base pointer */ |
| #define GPIO4 ((GPIO_Type *)GPIO4_BASE) |
| /** Peripheral GPIO5 base address */ |
| #define GPIO5_BASE (0x30240000u) |
| /** Peripheral GPIO5 base pointer */ |
| #define GPIO5 ((GPIO_Type *)GPIO5_BASE) |
| /** Array initializer of GPIO peripheral base addresses */ |
| #define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } |
| /** Array initializer of GPIO peripheral base pointers */ |
| #define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } |
| /** Interrupt vectors for the GPIO peripheral type */ |
| #define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } |
| #define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn } |
| #define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn } |
| |
| /*! |
| * @} |
| */ /* end of group GPIO_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPMI Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPMI_Peripheral_Access_Layer GPMI Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** GPMI - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t CTRL0; /**< GPMI Control Register 0 Description, offset: 0x0 */ |
| __IO uint32_t CTRL0_SET; /**< GPMI Control Register 0 Description, offset: 0x4 */ |
| __IO uint32_t CTRL0_CLR; /**< GPMI Control Register 0 Description, offset: 0x8 */ |
| __IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset: 0xC */ |
| __IO uint32_t COMPARE; /**< GPMI Compare Register Description, offset: 0x10 */ |
| uint8_t RESERVED_0[12]; |
| __IO uint32_t ECCCTRL; /**< GPMI Integrated ECC Control Register Description, offset: 0x20 */ |
| __IO uint32_t ECCCTRL_SET; /**< GPMI Integrated ECC Control Register Description, offset: 0x24 */ |
| __IO uint32_t ECCCTRL_CLR; /**< GPMI Integrated ECC Control Register Description, offset: 0x28 */ |
| __IO uint32_t ECCCTRL_TOG; /**< GPMI Integrated ECC Control Register Description, offset: 0x2C */ |
| __IO uint32_t ECCCOUNT; /**< GPMI Integrated ECC Transfer Count Register Description, offset: 0x30 */ |
| uint8_t RESERVED_1[12]; |
| __IO uint32_t PAYLOAD; /**< GPMI Payload Address Register Description, offset: 0x40 */ |
| uint8_t RESERVED_2[12]; |
| __IO uint32_t AUXILIARY; /**< GPMI Auxiliary Address Register Description, offset: 0x50 */ |
| uint8_t RESERVED_3[12]; |
| __IO uint32_t CTRL1; /**< GPMI Control Register 1 Description, offset: 0x60 */ |
| __IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset: 0x64 */ |
| __IO uint32_t CTRL1_CLR; /**< GPMI Control Register 1 Description, offset: 0x68 */ |
| __IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset: 0x6C */ |
| __IO uint32_t TIMING0; /**< GPMI Timing Register 0 Description, offset: 0x70 */ |
| uint8_t RESERVED_4[12]; |
| __IO uint32_t TIMING1; /**< GPMI Timing Register 1 Description, offset: 0x80 */ |
| uint8_t RESERVED_5[12]; |
| __IO uint32_t TIMING2; /**< GPMI Timing Register 2 Description, offset: 0x90 */ |
| uint8_t RESERVED_6[12]; |
| __IO uint32_t DATA; /**< GPMI DMA Data Transfer Register Description, offset: 0xA0 */ |
| uint8_t RESERVED_7[12]; |
| __I uint32_t STAT; /**< GPMI Status Register Description, offset: 0xB0 */ |
| uint8_t RESERVED_8[12]; |
| __I uint32_t DEBUGr; /**< GPMI Debug Information Register Description, offset: 0xC0 */ |
| uint8_t RESERVED_9[12]; |
| __I uint32_t VERSION; /**< GPMI Version Register Description, offset: 0xD0 */ |
| uint8_t RESERVED_10[12]; |
| __IO uint32_t DEBUG2; /**< GPMI Debug2 Information Register Description, offset: 0xE0 */ |
| uint8_t RESERVED_11[12]; |
| __I uint32_t DEBUG3; /**< GPMI Debug3 Information Register Description, offset: 0xF0 */ |
| uint8_t RESERVED_12[12]; |
| __IO uint32_t READ_DDR_DLL_CTRL; /**< GPMI Double Rate Read DLL Control Register Description, offset: 0x100 */ |
| uint8_t RESERVED_13[12]; |
| __IO uint32_t WRITE_DDR_DLL_CTRL; /**< GPMI Double Rate Write DLL Control Register Description, offset: 0x110 */ |
| uint8_t RESERVED_14[12]; |
| __I uint32_t READ_DDR_DLL_STS; /**< GPMI Double Rate Read DLL Status Register Description, offset: 0x120 */ |
| uint8_t RESERVED_15[12]; |
| __I uint32_t WRITE_DDR_DLL_STS; /**< GPMI Double Rate Write DLL Status Register Description, offset: 0x130 */ |
| } GPMI_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPMI Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPMI_Register_Masks GPMI Register Masks |
| * @{ |
| */ |
| |
| /*! @name CTRL0 - GPMI Control Register 0 Description */ |
| /*! @{ */ |
| #define GPMI_CTRL0_XFER_COUNT_MASK (0xFFFFU) |
| #define GPMI_CTRL0_XFER_COUNT_SHIFT (0U) |
| #define GPMI_CTRL0_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_XFER_COUNT_SHIFT)) & GPMI_CTRL0_XFER_COUNT_MASK) |
| #define GPMI_CTRL0_ADDRESS_INCREMENT_MASK (0x10000U) |
| #define GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT (16U) |
| /*! ADDRESS_INCREMENT |
| * 0b0..Address does not increment. |
| * 0b1..Increment address. |
| */ |
| #define GPMI_CTRL0_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_ADDRESS_INCREMENT_MASK) |
| #define GPMI_CTRL0_ADDRESS_MASK (0xE0000U) |
| #define GPMI_CTRL0_ADDRESS_SHIFT (17U) |
| #define GPMI_CTRL0_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_SHIFT)) & GPMI_CTRL0_ADDRESS_MASK) |
| #define GPMI_CTRL0_CS_MASK (0x700000U) |
| #define GPMI_CTRL0_CS_SHIFT (20U) |
| #define GPMI_CTRL0_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CS_SHIFT)) & GPMI_CTRL0_CS_MASK) |
| #define GPMI_CTRL0_WORD_LENGTH_MASK (0x800000U) |
| #define GPMI_CTRL0_WORD_LENGTH_SHIFT (23U) |
| /*! WORD_LENGTH |
| * 0b0..Reserved. |
| * 0b1..8-bit Data Bus mode. |
| */ |
| #define GPMI_CTRL0_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_WORD_LENGTH_MASK) |
| #define GPMI_CTRL0_COMMAND_MODE_MASK (0x3000000U) |
| #define GPMI_CTRL0_COMMAND_MODE_SHIFT (24U) |
| /*! COMMAND_MODE |
| * 0b00..Write mode. |
| * 0b01..Read Mode. |
| * 0b10..Read and Compare Mode (setting sense flop). |
| * 0b11..Wait for Ready. |
| */ |
| #define GPMI_CTRL0_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_COMMAND_MODE_MASK) |
| #define GPMI_CTRL0_UDMA_MASK (0x4000000U) |
| #define GPMI_CTRL0_UDMA_SHIFT (26U) |
| /*! UDMA |
| * 0b0..Use ATA-PIO mode on the external bus. |
| * 0b1..Use ATA-Ultra DMA mode on the external bus. |
| */ |
| #define GPMI_CTRL0_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_UDMA_SHIFT)) & GPMI_CTRL0_UDMA_MASK) |
| #define GPMI_CTRL0_LOCK_CS_MASK (0x8000000U) |
| #define GPMI_CTRL0_LOCK_CS_SHIFT (27U) |
| #define GPMI_CTRL0_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_LOCK_CS_SHIFT)) & GPMI_CTRL0_LOCK_CS_MASK) |
| #define GPMI_CTRL0_DEV_IRQ_EN_MASK (0x10000000U) |
| #define GPMI_CTRL0_DEV_IRQ_EN_SHIFT (28U) |
| #define GPMI_CTRL0_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_DEV_IRQ_EN_MASK) |
| #define GPMI_CTRL0_RUN_MASK (0x20000000U) |
| #define GPMI_CTRL0_RUN_SHIFT (29U) |
| #define GPMI_CTRL0_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_RUN_SHIFT)) & GPMI_CTRL0_RUN_MASK) |
| #define GPMI_CTRL0_CLKGATE_MASK (0x40000000U) |
| #define GPMI_CTRL0_CLKGATE_SHIFT (30U) |
| #define GPMI_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLKGATE_SHIFT)) & GPMI_CTRL0_CLKGATE_MASK) |
| #define GPMI_CTRL0_SFTRST_MASK (0x80000000U) |
| #define GPMI_CTRL0_SFTRST_SHIFT (31U) |
| #define GPMI_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SFTRST_SHIFT)) & GPMI_CTRL0_SFTRST_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL0_SET - GPMI Control Register 0 Description */ |
| /*! @{ */ |
| #define GPMI_CTRL0_SET_XFER_COUNT_MASK (0xFFFFU) |
| #define GPMI_CTRL0_SET_XFER_COUNT_SHIFT (0U) |
| #define GPMI_CTRL0_SET_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_XFER_COUNT_SHIFT)) & GPMI_CTRL0_SET_XFER_COUNT_MASK) |
| #define GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK (0x10000U) |
| #define GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT (16U) |
| /*! ADDRESS_INCREMENT |
| * 0b0..Address does not increment. |
| * 0b1..Increment address. |
| */ |
| #define GPMI_CTRL0_SET_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK) |
| #define GPMI_CTRL0_SET_ADDRESS_MASK (0xE0000U) |
| #define GPMI_CTRL0_SET_ADDRESS_SHIFT (17U) |
| #define GPMI_CTRL0_SET_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_MASK) |
| #define GPMI_CTRL0_SET_CS_MASK (0x700000U) |
| #define GPMI_CTRL0_SET_CS_SHIFT (20U) |
| #define GPMI_CTRL0_SET_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CS_SHIFT)) & GPMI_CTRL0_SET_CS_MASK) |
| #define GPMI_CTRL0_SET_WORD_LENGTH_MASK (0x800000U) |
| #define GPMI_CTRL0_SET_WORD_LENGTH_SHIFT (23U) |
| /*! WORD_LENGTH |
| * 0b0..Reserved. |
| * 0b1..8-bit Data Bus mode. |
| */ |
| #define GPMI_CTRL0_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_SET_WORD_LENGTH_MASK) |
| #define GPMI_CTRL0_SET_COMMAND_MODE_MASK (0x3000000U) |
| #define GPMI_CTRL0_SET_COMMAND_MODE_SHIFT (24U) |
| /*! COMMAND_MODE |
| * 0b00..Write mode. |
| * 0b01..Read Mode. |
| * 0b10..Read and Compare Mode (setting sense flop). |
| * 0b11..Wait for Ready. |
| */ |
| #define GPMI_CTRL0_SET_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_SET_COMMAND_MODE_MASK) |
| #define GPMI_CTRL0_SET_UDMA_MASK (0x4000000U) |
| #define GPMI_CTRL0_SET_UDMA_SHIFT (26U) |
| /*! UDMA |
| * 0b0..Use ATA-PIO mode on the external bus. |
| * 0b1..Use ATA-Ultra DMA mode on the external bus. |
| */ |
| #define GPMI_CTRL0_SET_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_UDMA_SHIFT)) & GPMI_CTRL0_SET_UDMA_MASK) |
| #define GPMI_CTRL0_SET_LOCK_CS_MASK (0x8000000U) |
| #define GPMI_CTRL0_SET_LOCK_CS_SHIFT (27U) |
| #define GPMI_CTRL0_SET_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_LOCK_CS_SHIFT)) & GPMI_CTRL0_SET_LOCK_CS_MASK) |
| #define GPMI_CTRL0_SET_DEV_IRQ_EN_MASK (0x10000000U) |
| #define GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT (28U) |
| #define GPMI_CTRL0_SET_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_SET_DEV_IRQ_EN_MASK) |
| #define GPMI_CTRL0_SET_RUN_MASK (0x20000000U) |
| #define GPMI_CTRL0_SET_RUN_SHIFT (29U) |
| #define GPMI_CTRL0_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_RUN_SHIFT)) & GPMI_CTRL0_SET_RUN_MASK) |
| #define GPMI_CTRL0_SET_CLKGATE_MASK (0x40000000U) |
| #define GPMI_CTRL0_SET_CLKGATE_SHIFT (30U) |
| #define GPMI_CTRL0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CLKGATE_SHIFT)) & GPMI_CTRL0_SET_CLKGATE_MASK) |
| #define GPMI_CTRL0_SET_SFTRST_MASK (0x80000000U) |
| #define GPMI_CTRL0_SET_SFTRST_SHIFT (31U) |
| #define GPMI_CTRL0_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_SFTRST_SHIFT)) & GPMI_CTRL0_SET_SFTRST_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL0_CLR - GPMI Control Register 0 Description */ |
| /*! @{ */ |
| #define GPMI_CTRL0_CLR_XFER_COUNT_MASK (0xFFFFU) |
| #define GPMI_CTRL0_CLR_XFER_COUNT_SHIFT (0U) |
| #define GPMI_CTRL0_CLR_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_XFER_COUNT_SHIFT)) & GPMI_CTRL0_CLR_XFER_COUNT_MASK) |
| #define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK (0x10000U) |
| #define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT (16U) |
| /*! ADDRESS_INCREMENT |
| * 0b0..Address does not increment. |
| * 0b1..Increment address. |
| */ |
| #define GPMI_CTRL0_CLR_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK) |
| #define GPMI_CTRL0_CLR_ADDRESS_MASK (0xE0000U) |
| #define GPMI_CTRL0_CLR_ADDRESS_SHIFT (17U) |
| #define GPMI_CTRL0_CLR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_MASK) |
| #define GPMI_CTRL0_CLR_CS_MASK (0x700000U) |
| #define GPMI_CTRL0_CLR_CS_SHIFT (20U) |
| #define GPMI_CTRL0_CLR_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CS_SHIFT)) & GPMI_CTRL0_CLR_CS_MASK) |
| #define GPMI_CTRL0_CLR_WORD_LENGTH_MASK (0x800000U) |
| #define GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT (23U) |
| /*! WORD_LENGTH |
| * 0b0..Reserved. |
| * 0b1..8-bit Data Bus mode. |
| */ |
| #define GPMI_CTRL0_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_CLR_WORD_LENGTH_MASK) |
| #define GPMI_CTRL0_CLR_COMMAND_MODE_MASK (0x3000000U) |
| #define GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT (24U) |
| /*! COMMAND_MODE |
| * 0b00..Write mode. |
| * 0b01..Read Mode. |
| * 0b10..Read and Compare Mode (setting sense flop). |
| * 0b11..Wait for Ready. |
| */ |
| #define GPMI_CTRL0_CLR_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_CLR_COMMAND_MODE_MASK) |
| #define GPMI_CTRL0_CLR_UDMA_MASK (0x4000000U) |
| #define GPMI_CTRL0_CLR_UDMA_SHIFT (26U) |
| /*! UDMA |
| * 0b0..Use ATA-PIO mode on the external bus. |
| * 0b1..Use ATA-Ultra DMA mode on the external bus. |
| */ |
| #define GPMI_CTRL0_CLR_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_UDMA_SHIFT)) & GPMI_CTRL0_CLR_UDMA_MASK) |
| #define GPMI_CTRL0_CLR_LOCK_CS_MASK (0x8000000U) |
| #define GPMI_CTRL0_CLR_LOCK_CS_SHIFT (27U) |
| #define GPMI_CTRL0_CLR_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_LOCK_CS_SHIFT)) & GPMI_CTRL0_CLR_LOCK_CS_MASK) |
| #define GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK (0x10000000U) |
| #define GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT (28U) |
| #define GPMI_CTRL0_CLR_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK) |
| #define GPMI_CTRL0_CLR_RUN_MASK (0x20000000U) |
| #define GPMI_CTRL0_CLR_RUN_SHIFT (29U) |
| #define GPMI_CTRL0_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_RUN_SHIFT)) & GPMI_CTRL0_CLR_RUN_MASK) |
| #define GPMI_CTRL0_CLR_CLKGATE_MASK (0x40000000U) |
| #define GPMI_CTRL0_CLR_CLKGATE_SHIFT (30U) |
| #define GPMI_CTRL0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CLKGATE_SHIFT)) & GPMI_CTRL0_CLR_CLKGATE_MASK) |
| #define GPMI_CTRL0_CLR_SFTRST_MASK (0x80000000U) |
| #define GPMI_CTRL0_CLR_SFTRST_SHIFT (31U) |
| #define GPMI_CTRL0_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_SFTRST_SHIFT)) & GPMI_CTRL0_CLR_SFTRST_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL0_TOG - GPMI Control Register 0 Description */ |
| /*! @{ */ |
| #define GPMI_CTRL0_TOG_XFER_COUNT_MASK (0xFFFFU) |
| #define GPMI_CTRL0_TOG_XFER_COUNT_SHIFT (0U) |
| #define GPMI_CTRL0_TOG_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_XFER_COUNT_SHIFT)) & GPMI_CTRL0_TOG_XFER_COUNT_MASK) |
| #define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK (0x10000U) |
| #define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT (16U) |
| /*! ADDRESS_INCREMENT |
| * 0b0..Address does not increment. |
| * 0b1..Increment address. |
| */ |
| #define GPMI_CTRL0_TOG_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK) |
| #define GPMI_CTRL0_TOG_ADDRESS_MASK (0xE0000U) |
| #define GPMI_CTRL0_TOG_ADDRESS_SHIFT (17U) |
| #define GPMI_CTRL0_TOG_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_MASK) |
| #define GPMI_CTRL0_TOG_CS_MASK (0x700000U) |
| #define GPMI_CTRL0_TOG_CS_SHIFT (20U) |
| #define GPMI_CTRL0_TOG_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CS_SHIFT)) & GPMI_CTRL0_TOG_CS_MASK) |
| #define GPMI_CTRL0_TOG_WORD_LENGTH_MASK (0x800000U) |
| #define GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT (23U) |
| /*! WORD_LENGTH |
| * 0b0..Reserved. |
| * 0b1..8-bit Data Bus mode. |
| */ |
| #define GPMI_CTRL0_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_TOG_WORD_LENGTH_MASK) |
| #define GPMI_CTRL0_TOG_COMMAND_MODE_MASK (0x3000000U) |
| #define GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT (24U) |
| /*! COMMAND_MODE |
| * 0b00..Write mode. |
| * 0b01..Read Mode. |
| * 0b10..Read and Compare Mode (setting sense flop). |
| * 0b11..Wait for Ready. |
| */ |
| #define GPMI_CTRL0_TOG_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_TOG_COMMAND_MODE_MASK) |
| #define GPMI_CTRL0_TOG_UDMA_MASK (0x4000000U) |
| #define GPMI_CTRL0_TOG_UDMA_SHIFT (26U) |
| /*! UDMA |
| * 0b0..Use ATA-PIO mode on the external bus. |
| * 0b1..Use ATA-Ultra DMA mode on the external bus. |
| */ |
| #define GPMI_CTRL0_TOG_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_UDMA_SHIFT)) & GPMI_CTRL0_TOG_UDMA_MASK) |
| #define GPMI_CTRL0_TOG_LOCK_CS_MASK (0x8000000U) |
| #define GPMI_CTRL0_TOG_LOCK_CS_SHIFT (27U) |
| #define GPMI_CTRL0_TOG_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_LOCK_CS_SHIFT)) & GPMI_CTRL0_TOG_LOCK_CS_MASK) |
| #define GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK (0x10000000U) |
| #define GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT (28U) |
| #define GPMI_CTRL0_TOG_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK) |
| #define GPMI_CTRL0_TOG_RUN_MASK (0x20000000U) |
| #define GPMI_CTRL0_TOG_RUN_SHIFT (29U) |
| #define GPMI_CTRL0_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_RUN_SHIFT)) & GPMI_CTRL0_TOG_RUN_MASK) |
| #define GPMI_CTRL0_TOG_CLKGATE_MASK (0x40000000U) |
| #define GPMI_CTRL0_TOG_CLKGATE_SHIFT (30U) |
| #define GPMI_CTRL0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CLKGATE_SHIFT)) & GPMI_CTRL0_TOG_CLKGATE_MASK) |
| #define GPMI_CTRL0_TOG_SFTRST_MASK (0x80000000U) |
| #define GPMI_CTRL0_TOG_SFTRST_SHIFT (31U) |
| #define GPMI_CTRL0_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_SFTRST_SHIFT)) & GPMI_CTRL0_TOG_SFTRST_MASK) |
| /*! @} */ |
| |
| /*! @name COMPARE - GPMI Compare Register Description */ |
| /*! @{ */ |
| #define GPMI_COMPARE_REFERENCE_MASK (0xFFFFU) |
| #define GPMI_COMPARE_REFERENCE_SHIFT (0U) |
| #define GPMI_COMPARE_REFERENCE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_REFERENCE_SHIFT)) & GPMI_COMPARE_REFERENCE_MASK) |
| #define GPMI_COMPARE_MASK_MASK (0xFFFF0000U) |
| #define GPMI_COMPARE_MASK_SHIFT (16U) |
| #define GPMI_COMPARE_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_MASK_SHIFT)) & GPMI_COMPARE_MASK_MASK) |
| /*! @} */ |
| |
| /*! @name ECCCTRL - GPMI Integrated ECC Control Register Description */ |
| /*! @{ */ |
| #define GPMI_ECCCTRL_BUFFER_MASK_MASK (0x1FFU) |
| #define GPMI_ECCCTRL_BUFFER_MASK_SHIFT (0U) |
| #define GPMI_ECCCTRL_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_BUFFER_MASK_MASK) |
| #define GPMI_ECCCTRL_RANDOMIZER_TYPE_MASK (0x600U) |
| #define GPMI_ECCCTRL_RANDOMIZER_TYPE_SHIFT (9U) |
| /*! RANDOMIZER_TYPE |
| * 0b00..Type 0 |
| * 0b01..Type 1 |
| */ |
| #define GPMI_ECCCTRL_RANDOMIZER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_RANDOMIZER_TYPE_MASK) |
| #define GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK (0x800U) |
| #define GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT (11U) |
| /*! RANDOMIZER_ENABLE |
| * 0b0..disable |
| * 0b1..enable |
| */ |
| #define GPMI_ECCCTRL_RANDOMIZER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK) |
| #define GPMI_ECCCTRL_ENABLE_ECC_MASK (0x1000U) |
| #define GPMI_ECCCTRL_ENABLE_ECC_SHIFT (12U) |
| #define GPMI_ECCCTRL_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_ENABLE_ECC_MASK) |
| #define GPMI_ECCCTRL_ECC_CMD_MASK (0x6000U) |
| #define GPMI_ECCCTRL_ECC_CMD_SHIFT (13U) |
| #define GPMI_ECCCTRL_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_ECC_CMD_MASK) |
| #define GPMI_ECCCTRL_RSVD2_MASK (0x8000U) |
| #define GPMI_ECCCTRL_RSVD2_SHIFT (15U) |
| #define GPMI_ECCCTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RSVD2_SHIFT)) & GPMI_ECCCTRL_RSVD2_MASK) |
| #define GPMI_ECCCTRL_HANDLE_MASK (0xFFFF0000U) |
| #define GPMI_ECCCTRL_HANDLE_SHIFT (16U) |
| #define GPMI_ECCCTRL_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_HANDLE_SHIFT)) & GPMI_ECCCTRL_HANDLE_MASK) |
| /*! @} */ |
| |
| /*! @name ECCCTRL_SET - GPMI Integrated ECC Control Register Description */ |
| /*! @{ */ |
| #define GPMI_ECCCTRL_SET_BUFFER_MASK_MASK (0x1FFU) |
| #define GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT (0U) |
| #define GPMI_ECCCTRL_SET_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_SET_BUFFER_MASK_MASK) |
| #define GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_MASK (0x600U) |
| #define GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_SHIFT (9U) |
| /*! RANDOMIZER_TYPE |
| * 0b00..Type 0 |
| * 0b01..Type 1 |
| */ |
| #define GPMI_ECCCTRL_SET_RANDOMIZER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_MASK) |
| #define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_MASK (0x800U) |
| #define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_SHIFT (11U) |
| /*! RANDOMIZER_ENABLE |
| * 0b0..disable |
| * 0b1..enable |
| */ |
| #define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_MASK) |
| #define GPMI_ECCCTRL_SET_ENABLE_ECC_MASK (0x1000U) |
| #define GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT (12U) |
| #define GPMI_ECCCTRL_SET_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_SET_ENABLE_ECC_MASK) |
| #define GPMI_ECCCTRL_SET_ECC_CMD_MASK (0x6000U) |
| #define GPMI_ECCCTRL_SET_ECC_CMD_SHIFT (13U) |
| #define GPMI_ECCCTRL_SET_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_SET_ECC_CMD_MASK) |
| #define GPMI_ECCCTRL_SET_RSVD2_MASK (0x8000U) |
| #define GPMI_ECCCTRL_SET_RSVD2_SHIFT (15U) |
| #define GPMI_ECCCTRL_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RSVD2_SHIFT)) & GPMI_ECCCTRL_SET_RSVD2_MASK) |
| #define GPMI_ECCCTRL_SET_HANDLE_MASK (0xFFFF0000U) |
| #define GPMI_ECCCTRL_SET_HANDLE_SHIFT (16U) |
| #define GPMI_ECCCTRL_SET_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_HANDLE_SHIFT)) & GPMI_ECCCTRL_SET_HANDLE_MASK) |
| /*! @} */ |
| |
| /*! @name ECCCTRL_CLR - GPMI Integrated ECC Control Register Description */ |
| /*! @{ */ |
| #define GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK (0x1FFU) |
| #define GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT (0U) |
| #define GPMI_ECCCTRL_CLR_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK) |
| #define GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_MASK (0x600U) |
| #define GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_SHIFT (9U) |
| /*! RANDOMIZER_TYPE |
| * 0b00..Type 0 |
| * 0b01..Type 1 |
| */ |
| #define GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_MASK) |
| #define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_MASK (0x800U) |
| #define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_SHIFT (11U) |
| /*! RANDOMIZER_ENABLE |
| * 0b0..disable |
| * 0b1..enable |
| */ |
| #define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_MASK) |
| #define GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK (0x1000U) |
| #define GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT (12U) |
| #define GPMI_ECCCTRL_CLR_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK) |
| #define GPMI_ECCCTRL_CLR_ECC_CMD_MASK (0x6000U) |
| #define GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT (13U) |
| #define GPMI_ECCCTRL_CLR_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_CLR_ECC_CMD_MASK) |
| #define GPMI_ECCCTRL_CLR_RSVD2_MASK (0x8000U) |
| #define GPMI_ECCCTRL_CLR_RSVD2_SHIFT (15U) |
| #define GPMI_ECCCTRL_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RSVD2_SHIFT)) & GPMI_ECCCTRL_CLR_RSVD2_MASK) |
| #define GPMI_ECCCTRL_CLR_HANDLE_MASK (0xFFFF0000U) |
| #define GPMI_ECCCTRL_CLR_HANDLE_SHIFT (16U) |
| #define GPMI_ECCCTRL_CLR_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_HANDLE_SHIFT)) & GPMI_ECCCTRL_CLR_HANDLE_MASK) |
| /*! @} */ |
| |
| /*! @name ECCCTRL_TOG - GPMI Integrated ECC Control Register Description */ |
| /*! @{ */ |
| #define GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK (0x1FFU) |
| #define GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT (0U) |
| #define GPMI_ECCCTRL_TOG_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK) |
| #define GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_MASK (0x600U) |
| #define GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_SHIFT (9U) |
| /*! RANDOMIZER_TYPE |
| * 0b00..Type 0 |
| * 0b01..Type 1 |
| */ |
| #define GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_MASK) |
| #define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_MASK (0x800U) |
| #define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_SHIFT (11U) |
| /*! RANDOMIZER_ENABLE |
| * 0b0..disable |
| * 0b1..enable |
| */ |
| #define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_MASK) |
| #define GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK (0x1000U) |
| #define GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT (12U) |
| #define GPMI_ECCCTRL_TOG_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK) |
| #define GPMI_ECCCTRL_TOG_ECC_CMD_MASK (0x6000U) |
| #define GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT (13U) |
| #define GPMI_ECCCTRL_TOG_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_TOG_ECC_CMD_MASK) |
| #define GPMI_ECCCTRL_TOG_RSVD2_MASK (0x8000U) |
| #define GPMI_ECCCTRL_TOG_RSVD2_SHIFT (15U) |
| #define GPMI_ECCCTRL_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RSVD2_SHIFT)) & GPMI_ECCCTRL_TOG_RSVD2_MASK) |
| #define GPMI_ECCCTRL_TOG_HANDLE_MASK (0xFFFF0000U) |
| #define GPMI_ECCCTRL_TOG_HANDLE_SHIFT (16U) |
| #define GPMI_ECCCTRL_TOG_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_HANDLE_SHIFT)) & GPMI_ECCCTRL_TOG_HANDLE_MASK) |
| /*! @} */ |
| |
| /*! @name ECCCOUNT - GPMI Integrated ECC Transfer Count Register Description */ |
| /*! @{ */ |
| #define GPMI_ECCCOUNT_COUNT_MASK (0xFFFFU) |
| #define GPMI_ECCCOUNT_COUNT_SHIFT (0U) |
| #define GPMI_ECCCOUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_COUNT_SHIFT)) & GPMI_ECCCOUNT_COUNT_MASK) |
| #define GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK (0xFF0000U) |
| #define GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT (16U) |
| #define GPMI_ECCCOUNT_RANDOMIZER_PAGE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT)) & GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK) |
| /*! @} */ |
| |
| /*! @name PAYLOAD - GPMI Payload Address Register Description */ |
| /*! @{ */ |
| #define GPMI_PAYLOAD_RSVD0_MASK (0x3U) |
| #define GPMI_PAYLOAD_RSVD0_SHIFT (0U) |
| #define GPMI_PAYLOAD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_RSVD0_SHIFT)) & GPMI_PAYLOAD_RSVD0_MASK) |
| #define GPMI_PAYLOAD_ADDRESS_MASK (0xFFFFFFFCU) |
| #define GPMI_PAYLOAD_ADDRESS_SHIFT (2U) |
| #define GPMI_PAYLOAD_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_ADDRESS_SHIFT)) & GPMI_PAYLOAD_ADDRESS_MASK) |
| /*! @} */ |
| |
| /*! @name AUXILIARY - GPMI Auxiliary Address Register Description */ |
| /*! @{ */ |
| #define GPMI_AUXILIARY_RSVD0_MASK (0x3U) |
| #define GPMI_AUXILIARY_RSVD0_SHIFT (0U) |
| #define GPMI_AUXILIARY_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_RSVD0_SHIFT)) & GPMI_AUXILIARY_RSVD0_MASK) |
| #define GPMI_AUXILIARY_ADDRESS_MASK (0xFFFFFFFCU) |
| #define GPMI_AUXILIARY_ADDRESS_SHIFT (2U) |
| #define GPMI_AUXILIARY_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_ADDRESS_SHIFT)) & GPMI_AUXILIARY_ADDRESS_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL1 - GPMI Control Register 1 Description */ |
| /*! @{ */ |
| #define GPMI_CTRL1_GPMI_MODE_MASK (0x1U) |
| #define GPMI_CTRL1_GPMI_MODE_SHIFT (0U) |
| /*! GPMI_MODE |
| * 0b0..NAND mode. |
| * 0b1..ATA mode. |
| */ |
| #define GPMI_CTRL1_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_MODE_SHIFT)) & GPMI_CTRL1_GPMI_MODE_MASK) |
| #define GPMI_CTRL1_CAMERA_MODE_MASK (0x2U) |
| #define GPMI_CTRL1_CAMERA_MODE_SHIFT (1U) |
| #define GPMI_CTRL1_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CAMERA_MODE_MASK) |
| #define GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK (0x4U) |
| #define GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT (2U) |
| /*! ATA_IRQRDY_POLARITY |
| * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. |
| * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. |
| */ |
| #define GPMI_CTRL1_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK) |
| #define GPMI_CTRL1_DEV_RESET_MASK (0x8U) |
| #define GPMI_CTRL1_DEV_RESET_SHIFT (3U) |
| /*! DEV_RESET |
| * 0b0..NANDF_WP_B pin is held low (asserted). |
| * 0b1..NANDF_WP_B pin is held high (de-asserted). |
| */ |
| #define GPMI_CTRL1_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_RESET_SHIFT)) & GPMI_CTRL1_DEV_RESET_MASK) |
| #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) |
| #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) |
| #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK) |
| #define GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK (0x80U) |
| #define GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT (7U) |
| #define GPMI_CTRL1_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK) |
| #define GPMI_CTRL1_BURST_EN_MASK (0x100U) |
| #define GPMI_CTRL1_BURST_EN_SHIFT (8U) |
| #define GPMI_CTRL1_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BURST_EN_SHIFT)) & GPMI_CTRL1_BURST_EN_MASK) |
| #define GPMI_CTRL1_TIMEOUT_IRQ_MASK (0x200U) |
| #define GPMI_CTRL1_TIMEOUT_IRQ_SHIFT (9U) |
| #define GPMI_CTRL1_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_MASK) |
| #define GPMI_CTRL1_DEV_IRQ_MASK (0x400U) |
| #define GPMI_CTRL1_DEV_IRQ_SHIFT (10U) |
| #define GPMI_CTRL1_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_IRQ_SHIFT)) & GPMI_CTRL1_DEV_IRQ_MASK) |
| #define GPMI_CTRL1_DMA2ECC_MODE_MASK (0x800U) |
| #define GPMI_CTRL1_DMA2ECC_MODE_SHIFT (11U) |
| #define GPMI_CTRL1_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_DMA2ECC_MODE_MASK) |
| #define GPMI_CTRL1_RDN_DELAY_MASK (0xF000U) |
| #define GPMI_CTRL1_RDN_DELAY_SHIFT (12U) |
| #define GPMI_CTRL1_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_RDN_DELAY_SHIFT)) & GPMI_CTRL1_RDN_DELAY_MASK) |
| #define GPMI_CTRL1_HALF_PERIOD_MASK (0x10000U) |
| #define GPMI_CTRL1_HALF_PERIOD_SHIFT (16U) |
| #define GPMI_CTRL1_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_HALF_PERIOD_MASK) |
| #define GPMI_CTRL1_DLL_ENABLE_MASK (0x20000U) |
| #define GPMI_CTRL1_DLL_ENABLE_SHIFT (17U) |
| #define GPMI_CTRL1_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_DLL_ENABLE_MASK) |
| #define GPMI_CTRL1_BCH_MODE_MASK (0x40000U) |
| #define GPMI_CTRL1_BCH_MODE_SHIFT (18U) |
| #define GPMI_CTRL1_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BCH_MODE_SHIFT)) & GPMI_CTRL1_BCH_MODE_MASK) |
| #define GPMI_CTRL1_GANGED_RDYBUSY_MASK (0x80000U) |
| #define GPMI_CTRL1_GANGED_RDYBUSY_SHIFT (19U) |
| #define GPMI_CTRL1_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_GANGED_RDYBUSY_MASK) |
| #define GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK (0x100000U) |
| #define GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT (20U) |
| #define GPMI_CTRL1_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK) |
| #define GPMI_CTRL1_TEST_TRIGGER_MASK (0x200000U) |
| #define GPMI_CTRL1_TEST_TRIGGER_SHIFT (21U) |
| /*! TEST_TRIGGER |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define GPMI_CTRL1_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TEST_TRIGGER_MASK) |
| #define GPMI_CTRL1_WRN_DLY_SEL_MASK (0xC00000U) |
| #define GPMI_CTRL1_WRN_DLY_SEL_SHIFT (22U) |
| #define GPMI_CTRL1_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_WRN_DLY_SEL_MASK) |
| #define GPMI_CTRL1_DECOUPLE_CS_MASK (0x1000000U) |
| #define GPMI_CTRL1_DECOUPLE_CS_SHIFT (24U) |
| #define GPMI_CTRL1_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_DECOUPLE_CS_MASK) |
| #define GPMI_CTRL1_SSYNCMODE_MASK (0x2000000U) |
| #define GPMI_CTRL1_SSYNCMODE_SHIFT (25U) |
| #define GPMI_CTRL1_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SSYNCMODE_MASK) |
| #define GPMI_CTRL1_UPDATE_CS_MASK (0x4000000U) |
| #define GPMI_CTRL1_UPDATE_CS_SHIFT (26U) |
| #define GPMI_CTRL1_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_UPDATE_CS_SHIFT)) & GPMI_CTRL1_UPDATE_CS_MASK) |
| #define GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK (0x8000000U) |
| #define GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT (27U) |
| /*! GPMI_CLK_DIV2_EN |
| * 0b0..internal factor-2 clock divider is disabled |
| * 0b1..internal factor-2 clock divider is enabled. |
| */ |
| #define GPMI_CTRL1_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK) |
| #define GPMI_CTRL1_TOGGLE_MODE_MASK (0x10000000U) |
| #define GPMI_CTRL1_TOGGLE_MODE_SHIFT (28U) |
| #define GPMI_CTRL1_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOGGLE_MODE_MASK) |
| #define GPMI_CTRL1_WRITE_CLK_STOP_MASK (0x20000000U) |
| #define GPMI_CTRL1_WRITE_CLK_STOP_SHIFT (29U) |
| #define GPMI_CTRL1_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_WRITE_CLK_STOP_MASK) |
| #define GPMI_CTRL1_SSYNC_CLK_STOP_MASK (0x40000000U) |
| #define GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT (30U) |
| #define GPMI_CTRL1_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SSYNC_CLK_STOP_MASK) |
| #define GPMI_CTRL1_DEV_CLK_STOP_MASK (0x80000000U) |
| #define GPMI_CTRL1_DEV_CLK_STOP_SHIFT (31U) |
| #define GPMI_CTRL1_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_DEV_CLK_STOP_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL1_SET - GPMI Control Register 1 Description */ |
| /*! @{ */ |
| #define GPMI_CTRL1_SET_GPMI_MODE_MASK (0x1U) |
| #define GPMI_CTRL1_SET_GPMI_MODE_SHIFT (0U) |
| /*! GPMI_MODE |
| * 0b0..NAND mode. |
| * 0b1..ATA mode. |
| */ |
| #define GPMI_CTRL1_SET_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_MODE_SHIFT)) & GPMI_CTRL1_SET_GPMI_MODE_MASK) |
| #define GPMI_CTRL1_SET_CAMERA_MODE_MASK (0x2U) |
| #define GPMI_CTRL1_SET_CAMERA_MODE_SHIFT (1U) |
| #define GPMI_CTRL1_SET_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_SET_CAMERA_MODE_MASK) |
| #define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK (0x4U) |
| #define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT (2U) |
| /*! ATA_IRQRDY_POLARITY |
| * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. |
| * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. |
| */ |
| #define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK) |
| #define GPMI_CTRL1_SET_DEV_RESET_MASK (0x8U) |
| #define GPMI_CTRL1_SET_DEV_RESET_SHIFT (3U) |
| /*! DEV_RESET |
| * 0b0..NANDF_WP_B pin is held low (asserted). |
| * 0b1..NANDF_WP_B pin is held high (de-asserted). |
| */ |
| #define GPMI_CTRL1_SET_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_RESET_SHIFT)) & GPMI_CTRL1_SET_DEV_RESET_MASK) |
| #define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) |
| #define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) |
| #define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK) |
| #define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK (0x80U) |
| #define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT (7U) |
| #define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK) |
| #define GPMI_CTRL1_SET_BURST_EN_MASK (0x100U) |
| #define GPMI_CTRL1_SET_BURST_EN_SHIFT (8U) |
| #define GPMI_CTRL1_SET_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BURST_EN_SHIFT)) & GPMI_CTRL1_SET_BURST_EN_MASK) |
| #define GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK (0x200U) |
| #define GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT (9U) |
| #define GPMI_CTRL1_SET_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK) |
| #define GPMI_CTRL1_SET_DEV_IRQ_MASK (0x400U) |
| #define GPMI_CTRL1_SET_DEV_IRQ_SHIFT (10U) |
| #define GPMI_CTRL1_SET_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_IRQ_SHIFT)) & GPMI_CTRL1_SET_DEV_IRQ_MASK) |
| #define GPMI_CTRL1_SET_DMA2ECC_MODE_MASK (0x800U) |
| #define GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT (11U) |
| #define GPMI_CTRL1_SET_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_SET_DMA2ECC_MODE_MASK) |
| #define GPMI_CTRL1_SET_RDN_DELAY_MASK (0xF000U) |
| #define GPMI_CTRL1_SET_RDN_DELAY_SHIFT (12U) |
| #define GPMI_CTRL1_SET_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_RDN_DELAY_SHIFT)) & GPMI_CTRL1_SET_RDN_DELAY_MASK) |
| #define GPMI_CTRL1_SET_HALF_PERIOD_MASK (0x10000U) |
| #define GPMI_CTRL1_SET_HALF_PERIOD_SHIFT (16U) |
| #define GPMI_CTRL1_SET_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_SET_HALF_PERIOD_MASK) |
| #define GPMI_CTRL1_SET_DLL_ENABLE_MASK (0x20000U) |
| #define GPMI_CTRL1_SET_DLL_ENABLE_SHIFT (17U) |
| #define GPMI_CTRL1_SET_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_SET_DLL_ENABLE_MASK) |
| #define GPMI_CTRL1_SET_BCH_MODE_MASK (0x40000U) |
| #define GPMI_CTRL1_SET_BCH_MODE_SHIFT (18U) |
| #define GPMI_CTRL1_SET_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BCH_MODE_SHIFT)) & GPMI_CTRL1_SET_BCH_MODE_MASK) |
| #define GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK (0x80000U) |
| #define GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT (19U) |
| #define GPMI_CTRL1_SET_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK) |
| #define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK (0x100000U) |
| #define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT (20U) |
| #define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK) |
| #define GPMI_CTRL1_SET_TEST_TRIGGER_MASK (0x200000U) |
| #define GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT (21U) |
| /*! TEST_TRIGGER |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define GPMI_CTRL1_SET_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_SET_TEST_TRIGGER_MASK) |
| #define GPMI_CTRL1_SET_WRN_DLY_SEL_MASK (0xC00000U) |
| #define GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT (22U) |
| #define GPMI_CTRL1_SET_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_SET_WRN_DLY_SEL_MASK) |
| #define GPMI_CTRL1_SET_DECOUPLE_CS_MASK (0x1000000U) |
| #define GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT (24U) |
| #define GPMI_CTRL1_SET_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_SET_DECOUPLE_CS_MASK) |
| #define GPMI_CTRL1_SET_SSYNCMODE_MASK (0x2000000U) |
| #define GPMI_CTRL1_SET_SSYNCMODE_SHIFT (25U) |
| #define GPMI_CTRL1_SET_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SET_SSYNCMODE_MASK) |
| #define GPMI_CTRL1_SET_UPDATE_CS_MASK (0x4000000U) |
| #define GPMI_CTRL1_SET_UPDATE_CS_SHIFT (26U) |
| #define GPMI_CTRL1_SET_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_UPDATE_CS_SHIFT)) & GPMI_CTRL1_SET_UPDATE_CS_MASK) |
| #define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK (0x8000000U) |
| #define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT (27U) |
| /*! GPMI_CLK_DIV2_EN |
| * 0b0..internal factor-2 clock divider is disabled |
| * 0b1..internal factor-2 clock divider is enabled. |
| */ |
| #define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK) |
| #define GPMI_CTRL1_SET_TOGGLE_MODE_MASK (0x10000000U) |
| #define GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT (28U) |
| #define GPMI_CTRL1_SET_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_SET_TOGGLE_MODE_MASK) |
| #define GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK (0x20000000U) |
| #define GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT (29U) |
| #define GPMI_CTRL1_SET_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK) |
| #define GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK (0x40000000U) |
| #define GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT (30U) |
| #define GPMI_CTRL1_SET_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK) |
| #define GPMI_CTRL1_SET_DEV_CLK_STOP_MASK (0x80000000U) |
| #define GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT (31U) |
| #define GPMI_CTRL1_SET_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_DEV_CLK_STOP_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL1_CLR - GPMI Control Register 1 Description */ |
| /*! @{ */ |
| #define GPMI_CTRL1_CLR_GPMI_MODE_MASK (0x1U) |
| #define GPMI_CTRL1_CLR_GPMI_MODE_SHIFT (0U) |
| /*! GPMI_MODE |
| * 0b0..NAND mode. |
| * 0b1..ATA mode. |
| */ |
| #define GPMI_CTRL1_CLR_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_MODE_SHIFT)) & GPMI_CTRL1_CLR_GPMI_MODE_MASK) |
| #define GPMI_CTRL1_CLR_CAMERA_MODE_MASK (0x2U) |
| #define GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT (1U) |
| #define GPMI_CTRL1_CLR_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CLR_CAMERA_MODE_MASK) |
| #define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK (0x4U) |
| #define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT (2U) |
| /*! ATA_IRQRDY_POLARITY |
| * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. |
| * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. |
| */ |
| #define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK) |
| #define GPMI_CTRL1_CLR_DEV_RESET_MASK (0x8U) |
| #define GPMI_CTRL1_CLR_DEV_RESET_SHIFT (3U) |
| /*! DEV_RESET |
| * 0b0..NANDF_WP_B pin is held low (asserted). |
| * 0b1..NANDF_WP_B pin is held high (de-asserted). |
| */ |
| #define GPMI_CTRL1_CLR_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_RESET_SHIFT)) & GPMI_CTRL1_CLR_DEV_RESET_MASK) |
| #define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) |
| #define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) |
| #define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK) |
| #define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK (0x80U) |
| #define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT (7U) |
| #define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK) |
| #define GPMI_CTRL1_CLR_BURST_EN_MASK (0x100U) |
| #define GPMI_CTRL1_CLR_BURST_EN_SHIFT (8U) |
| #define GPMI_CTRL1_CLR_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BURST_EN_SHIFT)) & GPMI_CTRL1_CLR_BURST_EN_MASK) |
| #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK (0x200U) |
| #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT (9U) |
| #define GPMI_CTRL1_CLR_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK) |
| #define GPMI_CTRL1_CLR_DEV_IRQ_MASK (0x400U) |
| #define GPMI_CTRL1_CLR_DEV_IRQ_SHIFT (10U) |
| #define GPMI_CTRL1_CLR_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_IRQ_SHIFT)) & GPMI_CTRL1_CLR_DEV_IRQ_MASK) |
| #define GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK (0x800U) |
| #define GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT (11U) |
| #define GPMI_CTRL1_CLR_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK) |
| #define GPMI_CTRL1_CLR_RDN_DELAY_MASK (0xF000U) |
| #define GPMI_CTRL1_CLR_RDN_DELAY_SHIFT (12U) |
| #define GPMI_CTRL1_CLR_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_RDN_DELAY_SHIFT)) & GPMI_CTRL1_CLR_RDN_DELAY_MASK) |
| #define GPMI_CTRL1_CLR_HALF_PERIOD_MASK (0x10000U) |
| #define GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT (16U) |
| #define GPMI_CTRL1_CLR_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_CLR_HALF_PERIOD_MASK) |
| #define GPMI_CTRL1_CLR_DLL_ENABLE_MASK (0x20000U) |
| #define GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT (17U) |
| #define GPMI_CTRL1_CLR_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_CLR_DLL_ENABLE_MASK) |
| #define GPMI_CTRL1_CLR_BCH_MODE_MASK (0x40000U) |
| #define GPMI_CTRL1_CLR_BCH_MODE_SHIFT (18U) |
| #define GPMI_CTRL1_CLR_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BCH_MODE_SHIFT)) & GPMI_CTRL1_CLR_BCH_MODE_MASK) |
| #define GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK (0x80000U) |
| #define GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT (19U) |
| #define GPMI_CTRL1_CLR_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK) |
| #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK (0x100000U) |
| #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT (20U) |
| #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK) |
| #define GPMI_CTRL1_CLR_TEST_TRIGGER_MASK (0x200000U) |
| #define GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT (21U) |
| /*! TEST_TRIGGER |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define GPMI_CTRL1_CLR_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_CLR_TEST_TRIGGER_MASK) |
| #define GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK (0xC00000U) |
| #define GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT (22U) |
| #define GPMI_CTRL1_CLR_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK) |
| #define GPMI_CTRL1_CLR_DECOUPLE_CS_MASK (0x1000000U) |
| #define GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT (24U) |
| #define GPMI_CTRL1_CLR_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_CLR_DECOUPLE_CS_MASK) |
| #define GPMI_CTRL1_CLR_SSYNCMODE_MASK (0x2000000U) |
| #define GPMI_CTRL1_CLR_SSYNCMODE_SHIFT (25U) |
| #define GPMI_CTRL1_CLR_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNCMODE_SHIFT)) & GPMI_CTRL1_CLR_SSYNCMODE_MASK) |
| #define GPMI_CTRL1_CLR_UPDATE_CS_MASK (0x4000000U) |
| #define GPMI_CTRL1_CLR_UPDATE_CS_SHIFT (26U) |
| #define GPMI_CTRL1_CLR_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_UPDATE_CS_SHIFT)) & GPMI_CTRL1_CLR_UPDATE_CS_MASK) |
| #define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK (0x8000000U) |
| #define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT (27U) |
| /*! GPMI_CLK_DIV2_EN |
| * 0b0..internal factor-2 clock divider is disabled |
| * 0b1..internal factor-2 clock divider is enabled. |
| */ |
| #define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK) |
| #define GPMI_CTRL1_CLR_TOGGLE_MODE_MASK (0x10000000U) |
| #define GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT (28U) |
| #define GPMI_CTRL1_CLR_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_CLR_TOGGLE_MODE_MASK) |
| #define GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK (0x20000000U) |
| #define GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT (29U) |
| #define GPMI_CTRL1_CLR_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK) |
| #define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK (0x40000000U) |
| #define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT (30U) |
| #define GPMI_CTRL1_CLR_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK) |
| #define GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK (0x80000000U) |
| #define GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT (31U) |
| #define GPMI_CTRL1_CLR_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL1_TOG - GPMI Control Register 1 Description */ |
| /*! @{ */ |
| #define GPMI_CTRL1_TOG_GPMI_MODE_MASK (0x1U) |
| #define GPMI_CTRL1_TOG_GPMI_MODE_SHIFT (0U) |
| /*! GPMI_MODE |
| * 0b0..NAND mode. |
| * 0b1..ATA mode. |
| */ |
| #define GPMI_CTRL1_TOG_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_MODE_SHIFT)) & GPMI_CTRL1_TOG_GPMI_MODE_MASK) |
| #define GPMI_CTRL1_TOG_CAMERA_MODE_MASK (0x2U) |
| #define GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT (1U) |
| #define GPMI_CTRL1_TOG_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_TOG_CAMERA_MODE_MASK) |
| #define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK (0x4U) |
| #define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT (2U) |
| /*! ATA_IRQRDY_POLARITY |
| * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. |
| * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. |
| */ |
| #define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK) |
| #define GPMI_CTRL1_TOG_DEV_RESET_MASK (0x8U) |
| #define GPMI_CTRL1_TOG_DEV_RESET_SHIFT (3U) |
| /*! DEV_RESET |
| * 0b0..NANDF_WP_B pin is held low (asserted). |
| * 0b1..NANDF_WP_B pin is held high (de-asserted). |
| */ |
| #define GPMI_CTRL1_TOG_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_RESET_SHIFT)) & GPMI_CTRL1_TOG_DEV_RESET_MASK) |
| #define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) |
| #define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) |
| #define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK) |
| #define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK (0x80U) |
| #define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT (7U) |
| #define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK) |
| #define GPMI_CTRL1_TOG_BURST_EN_MASK (0x100U) |
| #define GPMI_CTRL1_TOG_BURST_EN_SHIFT (8U) |
| #define GPMI_CTRL1_TOG_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BURST_EN_SHIFT)) & GPMI_CTRL1_TOG_BURST_EN_MASK) |
| #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK (0x200U) |
| #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT (9U) |
| #define GPMI_CTRL1_TOG_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK) |
| #define GPMI_CTRL1_TOG_DEV_IRQ_MASK (0x400U) |
| #define GPMI_CTRL1_TOG_DEV_IRQ_SHIFT (10U) |
| #define GPMI_CTRL1_TOG_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_IRQ_SHIFT)) & GPMI_CTRL1_TOG_DEV_IRQ_MASK) |
| #define GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK (0x800U) |
| #define GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT (11U) |
| #define GPMI_CTRL1_TOG_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK) |
| #define GPMI_CTRL1_TOG_RDN_DELAY_MASK (0xF000U) |
| #define GPMI_CTRL1_TOG_RDN_DELAY_SHIFT (12U) |
| #define GPMI_CTRL1_TOG_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_RDN_DELAY_SHIFT)) & GPMI_CTRL1_TOG_RDN_DELAY_MASK) |
| #define GPMI_CTRL1_TOG_HALF_PERIOD_MASK (0x10000U) |
| #define GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT (16U) |
| #define GPMI_CTRL1_TOG_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_TOG_HALF_PERIOD_MASK) |
| #define GPMI_CTRL1_TOG_DLL_ENABLE_MASK (0x20000U) |
| #define GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT (17U) |
| #define GPMI_CTRL1_TOG_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_TOG_DLL_ENABLE_MASK) |
| #define GPMI_CTRL1_TOG_BCH_MODE_MASK (0x40000U) |
| #define GPMI_CTRL1_TOG_BCH_MODE_SHIFT (18U) |
| #define GPMI_CTRL1_TOG_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BCH_MODE_SHIFT)) & GPMI_CTRL1_TOG_BCH_MODE_MASK) |
| #define GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK (0x80000U) |
| #define GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT (19U) |
| #define GPMI_CTRL1_TOG_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK) |
| #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK (0x100000U) |
| #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT (20U) |
| #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK) |
| #define GPMI_CTRL1_TOG_TEST_TRIGGER_MASK (0x200000U) |
| #define GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT (21U) |
| /*! TEST_TRIGGER |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define GPMI_CTRL1_TOG_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TOG_TEST_TRIGGER_MASK) |
| #define GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK (0xC00000U) |
| #define GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT (22U) |
| #define GPMI_CTRL1_TOG_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK) |
| #define GPMI_CTRL1_TOG_DECOUPLE_CS_MASK (0x1000000U) |
| #define GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT (24U) |
| #define GPMI_CTRL1_TOG_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_TOG_DECOUPLE_CS_MASK) |
| #define GPMI_CTRL1_TOG_SSYNCMODE_MASK (0x2000000U) |
| #define GPMI_CTRL1_TOG_SSYNCMODE_SHIFT (25U) |
| #define GPMI_CTRL1_TOG_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNCMODE_SHIFT)) & GPMI_CTRL1_TOG_SSYNCMODE_MASK) |
| #define GPMI_CTRL1_TOG_UPDATE_CS_MASK (0x4000000U) |
| #define GPMI_CTRL1_TOG_UPDATE_CS_SHIFT (26U) |
| #define GPMI_CTRL1_TOG_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_UPDATE_CS_SHIFT)) & GPMI_CTRL1_TOG_UPDATE_CS_MASK) |
| #define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK (0x8000000U) |
| #define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT (27U) |
| /*! GPMI_CLK_DIV2_EN |
| * 0b0..internal factor-2 clock divider is disabled |
| * 0b1..internal factor-2 clock divider is enabled. |
| */ |
| #define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK) |
| #define GPMI_CTRL1_TOG_TOGGLE_MODE_MASK (0x10000000U) |
| #define GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT (28U) |
| #define GPMI_CTRL1_TOG_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOG_TOGGLE_MODE_MASK) |
| #define GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK (0x20000000U) |
| #define GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT (29U) |
| #define GPMI_CTRL1_TOG_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK) |
| #define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK (0x40000000U) |
| #define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT (30U) |
| #define GPMI_CTRL1_TOG_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK) |
| #define GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK (0x80000000U) |
| #define GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT (31U) |
| #define GPMI_CTRL1_TOG_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK) |
| /*! @} */ |
| |
| /*! @name TIMING0 - GPMI Timing Register 0 Description */ |
| /*! @{ */ |
| #define GPMI_TIMING0_DATA_SETUP_MASK (0xFFU) |
| #define GPMI_TIMING0_DATA_SETUP_SHIFT (0U) |
| #define GPMI_TIMING0_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_SETUP_SHIFT)) & GPMI_TIMING0_DATA_SETUP_MASK) |
| #define GPMI_TIMING0_DATA_HOLD_MASK (0xFF00U) |
| #define GPMI_TIMING0_DATA_HOLD_SHIFT (8U) |
| #define GPMI_TIMING0_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_HOLD_SHIFT)) & GPMI_TIMING0_DATA_HOLD_MASK) |
| #define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xFF0000U) |
| #define GPMI_TIMING0_ADDRESS_SETUP_SHIFT (16U) |
| #define GPMI_TIMING0_ADDRESS_SETUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_ADDRESS_SETUP_SHIFT)) & GPMI_TIMING0_ADDRESS_SETUP_MASK) |
| #define GPMI_TIMING0_RSVD1_MASK (0xFF000000U) |
| #define GPMI_TIMING0_RSVD1_SHIFT (24U) |
| #define GPMI_TIMING0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_RSVD1_SHIFT)) & GPMI_TIMING0_RSVD1_MASK) |
| /*! @} */ |
| |
| /*! @name TIMING1 - GPMI Timing Register 1 Description */ |
| /*! @{ */ |
| #define GPMI_TIMING1_RSVD1_MASK (0xFFFFU) |
| #define GPMI_TIMING1_RSVD1_SHIFT (0U) |
| #define GPMI_TIMING1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_RSVD1_SHIFT)) & GPMI_TIMING1_RSVD1_MASK) |
| #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xFFFF0000U) |
| #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT (16U) |
| #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT)) & GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK) |
| /*! @} */ |
| |
| /*! @name TIMING2 - GPMI Timing Register 2 Description */ |
| /*! @{ */ |
| #define GPMI_TIMING2_DATA_PAUSE_MASK (0xFU) |
| #define GPMI_TIMING2_DATA_PAUSE_SHIFT (0U) |
| #define GPMI_TIMING2_DATA_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_DATA_PAUSE_SHIFT)) & GPMI_TIMING2_DATA_PAUSE_MASK) |
| #define GPMI_TIMING2_CMDADD_PAUSE_MASK (0xF0U) |
| #define GPMI_TIMING2_CMDADD_PAUSE_SHIFT (4U) |
| #define GPMI_TIMING2_CMDADD_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CMDADD_PAUSE_SHIFT)) & GPMI_TIMING2_CMDADD_PAUSE_MASK) |
| #define GPMI_TIMING2_POSTAMBLE_DELAY_MASK (0xF00U) |
| #define GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT (8U) |
| #define GPMI_TIMING2_POSTAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_POSTAMBLE_DELAY_MASK) |
| #define GPMI_TIMING2_PREAMBLE_DELAY_MASK (0xF000U) |
| #define GPMI_TIMING2_PREAMBLE_DELAY_SHIFT (12U) |
| #define GPMI_TIMING2_PREAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_PREAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_PREAMBLE_DELAY_MASK) |
| #define GPMI_TIMING2_CE_DELAY_MASK (0x1F0000U) |
| #define GPMI_TIMING2_CE_DELAY_SHIFT (16U) |
| #define GPMI_TIMING2_CE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CE_DELAY_SHIFT)) & GPMI_TIMING2_CE_DELAY_MASK) |
| #define GPMI_TIMING2_RSVD0_MASK (0xE00000U) |
| #define GPMI_TIMING2_RSVD0_SHIFT (21U) |
| #define GPMI_TIMING2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_RSVD0_SHIFT)) & GPMI_TIMING2_RSVD0_MASK) |
| #define GPMI_TIMING2_READ_LATENCY_MASK (0x7000000U) |
| #define GPMI_TIMING2_READ_LATENCY_SHIFT (24U) |
| /*! READ_LATENCY |
| * 0b000..READ LATENCY is 0 |
| * 0b001..READ LATENCY is 1 |
| * 0b010..READ LATENCY is 2 |
| * 0b011..READ LATENCY is 3 |
| * 0b100..READ LATENCY is 4 |
| * 0b101..READ LATENCY is 5 |
| */ |
| #define GPMI_TIMING2_READ_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_READ_LATENCY_SHIFT)) & GPMI_TIMING2_READ_LATENCY_MASK) |
| #define GPMI_TIMING2_TCR_MASK (0x18000000U) |
| #define GPMI_TIMING2_TCR_SHIFT (27U) |
| #define GPMI_TIMING2_TCR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TCR_SHIFT)) & GPMI_TIMING2_TCR_MASK) |
| #define GPMI_TIMING2_TRPSTH_MASK (0xE0000000U) |
| #define GPMI_TIMING2_TRPSTH_SHIFT (29U) |
| #define GPMI_TIMING2_TRPSTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TRPSTH_SHIFT)) & GPMI_TIMING2_TRPSTH_MASK) |
| /*! @} */ |
| |
| /*! @name DATA - GPMI DMA Data Transfer Register Description */ |
| /*! @{ */ |
| #define GPMI_DATA_DATA_MASK (0xFFFFFFFFU) |
| #define GPMI_DATA_DATA_SHIFT (0U) |
| #define GPMI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DATA_DATA_SHIFT)) & GPMI_DATA_DATA_MASK) |
| /*! @} */ |
| |
| /*! @name STAT - GPMI Status Register Description */ |
| /*! @{ */ |
| #define GPMI_STAT_PRESENT_MASK (0x1U) |
| #define GPMI_STAT_PRESENT_SHIFT (0U) |
| /*! PRESENT |
| * 0b0..GPMI is not present in this product. |
| * 0b1..GPMI is present is in this product. |
| */ |
| #define GPMI_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_PRESENT_SHIFT)) & GPMI_STAT_PRESENT_MASK) |
| #define GPMI_STAT_FIFO_FULL_MASK (0x2U) |
| #define GPMI_STAT_FIFO_FULL_SHIFT (1U) |
| /*! FIFO_FULL |
| * 0b0..FIFO is not full. |
| * 0b1..FIFO is full. |
| */ |
| #define GPMI_STAT_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_FULL_SHIFT)) & GPMI_STAT_FIFO_FULL_MASK) |
| #define GPMI_STAT_FIFO_EMPTY_MASK (0x4U) |
| #define GPMI_STAT_FIFO_EMPTY_SHIFT (2U) |
| /*! FIFO_EMPTY |
| * 0b0..FIFO is not empty. |
| * 0b1..FIFO is empty. |
| */ |
| #define GPMI_STAT_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_EMPTY_SHIFT)) & GPMI_STAT_FIFO_EMPTY_MASK) |
| #define GPMI_STAT_INVALID_BUFFER_MASK_MASK (0x8U) |
| #define GPMI_STAT_INVALID_BUFFER_MASK_SHIFT (3U) |
| /*! INVALID_BUFFER_MASK |
| * 0b0..ECC Buffer Mask is not invalid. |
| * 0b1..ECC Buffer Mask is invalid. |
| */ |
| #define GPMI_STAT_INVALID_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_INVALID_BUFFER_MASK_SHIFT)) & GPMI_STAT_INVALID_BUFFER_MASK_MASK) |
| #define GPMI_STAT_ATA_IRQ_MASK (0x10U) |
| #define GPMI_STAT_ATA_IRQ_SHIFT (4U) |
| #define GPMI_STAT_ATA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_ATA_IRQ_SHIFT)) & GPMI_STAT_ATA_IRQ_MASK) |
| #define GPMI_STAT_RSVD1_MASK (0xE0U) |
| #define GPMI_STAT_RSVD1_SHIFT (5U) |
| #define GPMI_STAT_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RSVD1_SHIFT)) & GPMI_STAT_RSVD1_MASK) |
| #define GPMI_STAT_DEV0_ERROR_MASK (0x100U) |
| #define GPMI_STAT_DEV0_ERROR_SHIFT (8U) |
| /*! DEV0_ERROR |
| * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 0. |
| * 0b1..An Error has occurred on ATA/NAND Device accessed by |
| */ |
| #define GPMI_STAT_DEV0_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV0_ERROR_SHIFT)) & GPMI_STAT_DEV0_ERROR_MASK) |
| #define GPMI_STAT_DEV1_ERROR_MASK (0x200U) |
| #define GPMI_STAT_DEV1_ERROR_SHIFT (9U) |
| /*! DEV1_ERROR |
| * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 1. |
| * 0b1..An Error has occurred on ATA/NAND Device accessed by |
| */ |
| #define GPMI_STAT_DEV1_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV1_ERROR_SHIFT)) & GPMI_STAT_DEV1_ERROR_MASK) |
| #define GPMI_STAT_DEV2_ERROR_MASK (0x400U) |
| #define GPMI_STAT_DEV2_ERROR_SHIFT (10U) |
| /*! DEV2_ERROR |
| * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 2. |
| * 0b1..An Error has occurred on ATA/NAND Device accessed by |
| */ |
| #define GPMI_STAT_DEV2_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV2_ERROR_SHIFT)) & GPMI_STAT_DEV2_ERROR_MASK) |
| #define GPMI_STAT_DEV3_ERROR_MASK (0x800U) |
| #define GPMI_STAT_DEV3_ERROR_SHIFT (11U) |
| /*! DEV3_ERROR |
| * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 3. |
| * 0b1..An Error has occurred on ATA/NAND Device accessed by |
| */ |
| #define GPMI_STAT_DEV3_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV3_ERROR_SHIFT)) & GPMI_STAT_DEV3_ERROR_MASK) |
| #define GPMI_STAT_DEV4_ERROR_MASK (0x1000U) |
| #define GPMI_STAT_DEV4_ERROR_SHIFT (12U) |
| /*! DEV4_ERROR |
| * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 4. |
| * 0b1..An Error has occurred on ATA/NAND Device accessed by |
| */ |
| #define GPMI_STAT_DEV4_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV4_ERROR_SHIFT)) & GPMI_STAT_DEV4_ERROR_MASK) |
| #define GPMI_STAT_DEV5_ERROR_MASK (0x2000U) |
| #define GPMI_STAT_DEV5_ERROR_SHIFT (13U) |
| /*! DEV5_ERROR |
| * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 5. |
| * 0b1..An Error has occurred on ATA/NAND Device accessed by |
| */ |
| #define GPMI_STAT_DEV5_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV5_ERROR_SHIFT)) & GPMI_STAT_DEV5_ERROR_MASK) |
| #define GPMI_STAT_DEV6_ERROR_MASK (0x4000U) |
| #define GPMI_STAT_DEV6_ERROR_SHIFT (14U) |
| /*! DEV6_ERROR |
| * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 6. |
| * 0b1..An Error has occurred on ATA/NAND Device accessed by |
| */ |
| #define GPMI_STAT_DEV6_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV6_ERROR_SHIFT)) & GPMI_STAT_DEV6_ERROR_MASK) |
| #define GPMI_STAT_DEV7_ERROR_MASK (0x8000U) |
| #define GPMI_STAT_DEV7_ERROR_SHIFT (15U) |
| /*! DEV7_ERROR |
| * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 7. |
| * 0b1..An Error has occurred on ATA/NAND Device accessed by |
| */ |
| #define GPMI_STAT_DEV7_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV7_ERROR_SHIFT)) & GPMI_STAT_DEV7_ERROR_MASK) |
| #define GPMI_STAT_RDY_TIMEOUT_MASK (0xFF0000U) |
| #define GPMI_STAT_RDY_TIMEOUT_SHIFT (16U) |
| #define GPMI_STAT_RDY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RDY_TIMEOUT_SHIFT)) & GPMI_STAT_RDY_TIMEOUT_MASK) |
| #define GPMI_STAT_READY_BUSY_MASK (0xFF000000U) |
| #define GPMI_STAT_READY_BUSY_SHIFT (24U) |
| #define GPMI_STAT_READY_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_READY_BUSY_SHIFT)) & GPMI_STAT_READY_BUSY_MASK) |
| /*! @} */ |
| |
| /*! @name DEBUG - GPMI Debug Information Register Description */ |
| /*! @{ */ |
| #define GPMI_DEBUG_CMD_END_MASK (0xFFU) |
| #define GPMI_DEBUG_CMD_END_SHIFT (0U) |
| #define GPMI_DEBUG_CMD_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_CMD_END_SHIFT)) & GPMI_DEBUG_CMD_END_MASK) |
| #define GPMI_DEBUG_DMAREQ_MASK (0xFF00U) |
| #define GPMI_DEBUG_DMAREQ_SHIFT (8U) |
| #define GPMI_DEBUG_DMAREQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMAREQ_SHIFT)) & GPMI_DEBUG_DMAREQ_MASK) |
| #define GPMI_DEBUG_DMA_SENSE_MASK (0xFF0000U) |
| #define GPMI_DEBUG_DMA_SENSE_SHIFT (16U) |
| #define GPMI_DEBUG_DMA_SENSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMA_SENSE_SHIFT)) & GPMI_DEBUG_DMA_SENSE_MASK) |
| #define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xFF000000U) |
| #define GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT (24U) |
| #define GPMI_DEBUG_WAIT_FOR_READY_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT)) & GPMI_DEBUG_WAIT_FOR_READY_END_MASK) |
| /*! @} */ |
| |
| /*! @name VERSION - GPMI Version Register Description */ |
| /*! @{ */ |
| #define GPMI_VERSION_STEP_MASK (0xFFFFU) |
| #define GPMI_VERSION_STEP_SHIFT (0U) |
| #define GPMI_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_STEP_SHIFT)) & GPMI_VERSION_STEP_MASK) |
| #define GPMI_VERSION_MINOR_MASK (0xFF0000U) |
| #define GPMI_VERSION_MINOR_SHIFT (16U) |
| #define GPMI_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MINOR_SHIFT)) & GPMI_VERSION_MINOR_MASK) |
| #define GPMI_VERSION_MAJOR_MASK (0xFF000000U) |
| #define GPMI_VERSION_MAJOR_SHIFT (24U) |
| #define GPMI_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MAJOR_SHIFT)) & GPMI_VERSION_MAJOR_MASK) |
| /*! @} */ |
| |
| /*! @name DEBUG2 - GPMI Debug2 Information Register Description */ |
| /*! @{ */ |
| #define GPMI_DEBUG2_RDN_TAP_MASK (0x3FU) |
| #define GPMI_DEBUG2_RDN_TAP_SHIFT (0U) |
| #define GPMI_DEBUG2_RDN_TAP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RDN_TAP_SHIFT)) & GPMI_DEBUG2_RDN_TAP_MASK) |
| #define GPMI_DEBUG2_UPDATE_WINDOW_MASK (0x40U) |
| #define GPMI_DEBUG2_UPDATE_WINDOW_SHIFT (6U) |
| #define GPMI_DEBUG2_UPDATE_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UPDATE_WINDOW_SHIFT)) & GPMI_DEBUG2_UPDATE_WINDOW_MASK) |
| #define GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK (0x80U) |
| #define GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT (7U) |
| #define GPMI_DEBUG2_VIEW_DELAYED_RDN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT)) & GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK) |
| #define GPMI_DEBUG2_SYND2GPMI_READY_MASK (0x100U) |
| #define GPMI_DEBUG2_SYND2GPMI_READY_SHIFT (8U) |
| #define GPMI_DEBUG2_SYND2GPMI_READY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_READY_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_READY_MASK) |
| #define GPMI_DEBUG2_SYND2GPMI_VALID_MASK (0x200U) |
| #define GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT (9U) |
| #define GPMI_DEBUG2_SYND2GPMI_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_VALID_MASK) |
| #define GPMI_DEBUG2_GPMI2SYND_READY_MASK (0x400U) |
| #define GPMI_DEBUG2_GPMI2SYND_READY_SHIFT (10U) |
| #define GPMI_DEBUG2_GPMI2SYND_READY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_READY_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_READY_MASK) |
| #define GPMI_DEBUG2_GPMI2SYND_VALID_MASK (0x800U) |
| #define GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT (11U) |
| #define GPMI_DEBUG2_GPMI2SYND_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_VALID_MASK) |
| #define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xF000U) |
| #define GPMI_DEBUG2_SYND2GPMI_BE_SHIFT (12U) |
| #define GPMI_DEBUG2_SYND2GPMI_BE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_BE_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_BE_MASK) |
| #define GPMI_DEBUG2_MAIN_STATE_MASK (0xF0000U) |
| #define GPMI_DEBUG2_MAIN_STATE_SHIFT (16U) |
| #define GPMI_DEBUG2_MAIN_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_MAIN_STATE_SHIFT)) & GPMI_DEBUG2_MAIN_STATE_MASK) |
| #define GPMI_DEBUG2_PIN_STATE_MASK (0x700000U) |
| #define GPMI_DEBUG2_PIN_STATE_SHIFT (20U) |
| #define GPMI_DEBUG2_PIN_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_PIN_STATE_SHIFT)) & GPMI_DEBUG2_PIN_STATE_MASK) |
| #define GPMI_DEBUG2_BUSY_MASK (0x800000U) |
| #define GPMI_DEBUG2_BUSY_SHIFT (23U) |
| #define GPMI_DEBUG2_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_BUSY_SHIFT)) & GPMI_DEBUG2_BUSY_MASK) |
| #define GPMI_DEBUG2_UDMA_STATE_MASK (0xF000000U) |
| #define GPMI_DEBUG2_UDMA_STATE_SHIFT (24U) |
| #define GPMI_DEBUG2_UDMA_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UDMA_STATE_SHIFT)) & GPMI_DEBUG2_UDMA_STATE_MASK) |
| #define GPMI_DEBUG2_RSVD1_MASK (0xF0000000U) |
| #define GPMI_DEBUG2_RSVD1_SHIFT (28U) |
| #define GPMI_DEBUG2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RSVD1_SHIFT)) & GPMI_DEBUG2_RSVD1_MASK) |
| /*! @} */ |
| |
| /*! @name DEBUG3 - GPMI Debug3 Information Register Description */ |
| /*! @{ */ |
| #define GPMI_DEBUG3_DEV_WORD_CNTR_MASK (0xFFFFU) |
| #define GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT (0U) |
| #define GPMI_DEBUG3_DEV_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_DEV_WORD_CNTR_MASK) |
| #define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xFFFF0000U) |
| #define GPMI_DEBUG3_APB_WORD_CNTR_SHIFT (16U) |
| #define GPMI_DEBUG3_APB_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_APB_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_APB_WORD_CNTR_MASK) |
| /*! @} */ |
| |
| /*! @name READ_DDR_DLL_CTRL - GPMI Double Rate Read DLL Control Register Description */ |
| /*! @{ */ |
| #define GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK (0x1U) |
| #define GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT (0U) |
| #define GPMI_READ_DDR_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK) |
| #define GPMI_READ_DDR_DLL_CTRL_RESET_MASK (0x2U) |
| #define GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT (1U) |
| #define GPMI_READ_DDR_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RESET_MASK) |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK) |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK) |
| #define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U) |
| #define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U) |
| #define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK) |
| #define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U) |
| #define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U) |
| #define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK) |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U) |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U) |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK) |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U) |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U) |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) |
| #define GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U) |
| #define GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT (18U) |
| #define GPMI_READ_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK) |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK) |
| #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) |
| #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) |
| #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK) |
| /*! @} */ |
| |
| /*! @name WRITE_DDR_DLL_CTRL - GPMI Double Rate Write DLL Control Register Description */ |
| /*! @{ */ |
| #define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK (0x1U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT (0U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK) |
| #define GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK (0x2U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT (1U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK) |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK) |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK) |
| #define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK) |
| #define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK) |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK) |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) |
| #define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT (18U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK) |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK) |
| #define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) |
| #define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK) |
| /*! @} */ |
| |
| /*! @name READ_DDR_DLL_STS - GPMI Double Rate Read DLL Status Register Description */ |
| /*! @{ */ |
| #define GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK (0x1U) |
| #define GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT (0U) |
| #define GPMI_READ_DDR_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK) |
| #define GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU) |
| #define GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT (1U) |
| #define GPMI_READ_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK) |
| #define GPMI_READ_DDR_DLL_STS_RSVD0_MASK (0xFE00U) |
| #define GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT (9U) |
| #define GPMI_READ_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD0_MASK) |
| #define GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK (0x10000U) |
| #define GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT (16U) |
| #define GPMI_READ_DDR_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK) |
| #define GPMI_READ_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U) |
| #define GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT (17U) |
| #define GPMI_READ_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_SEL_MASK) |
| #define GPMI_READ_DDR_DLL_STS_RSVD1_MASK (0xFE000000U) |
| #define GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT (25U) |
| #define GPMI_READ_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD1_MASK) |
| /*! @} */ |
| |
| /*! @name WRITE_DDR_DLL_STS - GPMI Double Rate Write DLL Status Register Description */ |
| /*! @{ */ |
| #define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK (0x1U) |
| #define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT (0U) |
| #define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK) |
| #define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU) |
| #define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT (1U) |
| #define GPMI_WRITE_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK) |
| #define GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK (0xFE00U) |
| #define GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT (9U) |
| #define GPMI_WRITE_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK) |
| #define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK (0x10000U) |
| #define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT (16U) |
| #define GPMI_WRITE_DDR_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK) |
| #define GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U) |
| #define GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT (17U) |
| #define GPMI_WRITE_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK) |
| #define GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK (0xFE000000U) |
| #define GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT (25U) |
| #define GPMI_WRITE_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group GPMI_Register_Masks */ |
| |
| |
| /* GPMI - Peripheral instance base addresses */ |
| /** Peripheral GPMI base address */ |
| #define GPMI_BASE (0x33002000u) |
| /** Peripheral GPMI base pointer */ |
| #define GPMI ((GPMI_Type *)GPMI_BASE) |
| /** Array initializer of GPMI peripheral base addresses */ |
| #define GPMI_BASE_ADDRS { GPMI_BASE } |
| /** Array initializer of GPMI peripheral base pointers */ |
| #define GPMI_BASE_PTRS { GPMI } |
| /** Interrupt vectors for the GPMI peripheral type */ |
| #define GPMI_IRQS { GPMI_IRQn } |
| |
| /*! |
| * @} |
| */ /* end of group GPMI_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPT Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** GPT - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */ |
| __IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */ |
| __IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */ |
| __IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */ |
| __IO uint32_t OCR[3]; /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */ |
| __I uint32_t ICR[2]; /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */ |
| __I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */ |
| } GPT_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPT Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPT_Register_Masks GPT Register Masks |
| * @{ |
| */ |
| |
| /*! @name CR - GPT Control Register */ |
| /*! @{ */ |
| #define GPT_CR_EN_MASK (0x1U) |
| #define GPT_CR_EN_SHIFT (0U) |
| /*! EN |
| * 0b0..GPT is disabled. |
| * 0b1..GPT is enabled. |
| */ |
| #define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) |
| #define GPT_CR_ENMOD_MASK (0x2U) |
| #define GPT_CR_ENMOD_SHIFT (1U) |
| /*! ENMOD |
| * 0b0..GPT counter will retain its value when it is disabled. |
| * 0b1..GPT counter value is reset to 0 when it is disabled. |
| */ |
| #define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK) |
| #define GPT_CR_DBGEN_MASK (0x4U) |
| #define GPT_CR_DBGEN_SHIFT (2U) |
| /*! DBGEN |
| * 0b0..GPT is disabled in debug mode. |
| * 0b1..GPT is enabled in debug mode. |
| */ |
| #define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK) |
| #define GPT_CR_WAITEN_MASK (0x8U) |
| #define GPT_CR_WAITEN_SHIFT (3U) |
| /*! WAITEN |
| * 0b0..GPT is disabled in wait mode. |
| * 0b1..GPT is enabled in wait mode. |
| */ |
| #define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK) |
| #define GPT_CR_DOZEEN_MASK (0x10U) |
| #define GPT_CR_DOZEEN_SHIFT (4U) |
| /*! DOZEEN |
| * 0b0..GPT is disabled in doze mode. |
| * 0b1..GPT is enabled in doze mode. |
| */ |
| #define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK) |
| #define GPT_CR_STOPEN_MASK (0x20U) |
| #define GPT_CR_STOPEN_SHIFT (5U) |
| /*! STOPEN |
| * 0b0..GPT is disabled in Stop mode. |
| * 0b1..GPT is enabled in Stop mode. |
| */ |
| #define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK) |
| #define GPT_CR_CLKSRC_MASK (0x1C0U) |
| #define GPT_CR_CLKSRC_SHIFT (6U) |
| /*! CLKSRC |
| * 0b000..No clock |
| * 0b001..Peripheral Clock (ipg_clk) |
| * 0b010..High Frequency Reference Clock (ipg_clk_highfreq) |
| * 0b011..External Clock |
| * 0b100..Low Frequency Reference Clock (ipg_clk_32k) |
| * 0b101..Crystal oscillator as Reference Clock (ipg_clk_24M) |
| */ |
| #define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK) |
| #define GPT_CR_FRR_MASK (0x200U) |
| #define GPT_CR_FRR_SHIFT (9U) |
| /*! FRR |
| * 0b0..Restart mode |
| * 0b1..Free-Run mode |
| */ |
| #define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK) |
| #define GPT_CR_EN_24M_MASK (0x400U) |
| #define GPT_CR_EN_24M_SHIFT (10U) |
| /*! EN_24M |
| * 0b0..24M clock disabled |
| * 0b1..24M clock enabled |
| */ |
| #define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK) |
| #define GPT_CR_SWR_MASK (0x8000U) |
| #define GPT_CR_SWR_SHIFT (15U) |
| /*! SWR |
| * 0b0..GPT is not in reset state |
| * 0b1..GPT is in reset state |
| */ |
| #define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK) |
| #define GPT_CR_IM1_MASK (0x30000U) |
| #define GPT_CR_IM1_SHIFT (16U) |
| #define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK) |
| #define GPT_CR_IM2_MASK (0xC0000U) |
| #define GPT_CR_IM2_SHIFT (18U) |
| /*! IM2 |
| * 0b00..capture disabled |
| * 0b01..capture on rising edge only |
| * 0b10..capture on falling edge only |
| * 0b11..capture on both edges |
| */ |
| #define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK) |
| #define GPT_CR_OM1_MASK (0x700000U) |
| #define GPT_CR_OM1_SHIFT (20U) |
| #define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK) |
| #define GPT_CR_OM2_MASK (0x3800000U) |
| #define GPT_CR_OM2_SHIFT (23U) |
| #define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK) |
| #define GPT_CR_OM3_MASK (0x1C000000U) |
| #define GPT_CR_OM3_SHIFT (26U) |
| /*! OM3 |
| * 0b000..Output disconnected. No response on pin. |
| * 0b001..Toggle output pin |
| * 0b010..Clear output pin |
| * 0b011..Set output pin |
| * 0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin. |
| */ |
| #define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK) |
| #define GPT_CR_FO1_MASK (0x20000000U) |
| #define GPT_CR_FO1_SHIFT (29U) |
| #define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK) |
| #define GPT_CR_FO2_MASK (0x40000000U) |
| #define GPT_CR_FO2_SHIFT (30U) |
| #define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK) |
| #define GPT_CR_FO3_MASK (0x80000000U) |
| #define GPT_CR_FO3_SHIFT (31U) |
| /*! FO3 |
| * 0b0..Writing a 0 has no effect. |
| * 0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set. |
| */ |
| #define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) |
| /*! @} */ |
| |
| /*! @name PR - GPT Prescaler Register */ |
| /*! @{ */ |
| #define GPT_PR_PRESCALER_MASK (0xFFFU) |
| #define GPT_PR_PRESCALER_SHIFT (0U) |
| /*! PRESCALER |
| * 0b000000000000..Divide by 1 |
| * 0b000000000001..Divide by 2 |
| * 0b111111111111..Divide by 4096 |
| */ |
| #define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK) |
| #define GPT_PR_PRESCALER24M_MASK (0xF000U) |
| #define GPT_PR_PRESCALER24M_SHIFT (12U) |
| /*! PRESCALER24M |
| * 0b0000..Divide by 1 |
| * 0b0001..Divide by 2 |
| * 0b1111..Divide by 16 |
| */ |
| #define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK) |
| /*! @} */ |
| |
| /*! @name SR - GPT Status Register */ |
| /*! @{ */ |
| #define GPT_SR_OF1_MASK (0x1U) |
| #define GPT_SR_OF1_SHIFT (0U) |
| #define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) |
| #define GPT_SR_OF2_MASK (0x2U) |
| #define GPT_SR_OF2_SHIFT (1U) |
| #define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK) |
| #define GPT_SR_OF3_MASK (0x4U) |
| #define GPT_SR_OF3_SHIFT (2U) |
| /*! OF3 |
| * 0b0..Compare event has not occurred. |
| * 0b1..Compare event has occurred. |
| */ |
| #define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK) |
| #define GPT_SR_IF1_MASK (0x8U) |
| #define GPT_SR_IF1_SHIFT (3U) |
| #define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK) |
| #define GPT_SR_IF2_MASK (0x10U) |
| #define GPT_SR_IF2_SHIFT (4U) |
| /*! IF2 |
| * 0b0..Capture event has not occurred. |
| * 0b1..Capture event has occurred. |
| */ |
| #define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK) |
| #define GPT_SR_ROV_MASK (0x20U) |
| #define GPT_SR_ROV_SHIFT (5U) |
| /*! ROV |
| * 0b0..Rollover has not occurred. |
| * 0b1..Rollover has occurred. |
| */ |
| #define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK) |
| /*! @} */ |
| |
| /*! @name IR - GPT Interrupt Register */ |
| /*! @{ */ |
| #define GPT_IR_OF1IE_MASK (0x1U) |
| #define GPT_IR_OF1IE_SHIFT (0U) |
| #define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) |
| #define GPT_IR_OF2IE_MASK (0x2U) |
| #define GPT_IR_OF2IE_SHIFT (1U) |
| #define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK) |
| #define GPT_IR_OF3IE_MASK (0x4U) |
| #define GPT_IR_OF3IE_SHIFT (2U) |
| /*! OF3IE |
| * 0b0..Output Compare Channel n interrupt is disabled. |
| * 0b1..Output Compare Channel n interrupt is enabled. |
| */ |
| #define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK) |
| #define GPT_IR_IF1IE_MASK (0x8U) |
| #define GPT_IR_IF1IE_SHIFT (3U) |
| #define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK) |
| #define GPT_IR_IF2IE_MASK (0x10U) |
| #define GPT_IR_IF2IE_SHIFT (4U) |
| /*! IF2IE |
| * 0b0..IF2IE Input Capture n Interrupt Enable is disabled. |
| * 0b1..IF2IE Input Capture n Interrupt Enable is enabled. |
| */ |
| #define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK) |
| #define GPT_IR_ROVIE_MASK (0x20U) |
| #define GPT_IR_ROVIE_SHIFT (5U) |
| /*! ROVIE |
| * 0b0..Rollover interrupt is disabled. |
| * 0b1..Rollover interrupt enabled. |
| */ |
| #define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) |
| /*! @} */ |
| |
| /*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */ |
| /*! @{ */ |
| #define GPT_OCR_COMP_MASK (0xFFFFFFFFU) |
| #define GPT_OCR_COMP_SHIFT (0U) |
| #define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK) |
| /*! @} */ |
| |
| /* The count of GPT_OCR */ |
| #define GPT_OCR_COUNT (3U) |
| |
| /*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */ |
| /*! @{ */ |
| #define GPT_ICR_CAPT_MASK (0xFFFFFFFFU) |
| #define GPT_ICR_CAPT_SHIFT (0U) |
| #define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK) |
| /*! @} */ |
| |
| /* The count of GPT_ICR */ |
| #define GPT_ICR_COUNT (2U) |
| |
| /*! @name CNT - GPT Counter Register */ |
| /*! @{ */ |
| #define GPT_CNT_COUNT_MASK (0xFFFFFFFFU) |
| #define GPT_CNT_COUNT_SHIFT (0U) |
| #define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group GPT_Register_Masks */ |
| |
| |
| /* GPT - Peripheral instance base addresses */ |
| /** Peripheral GPT1 base address */ |
| #define GPT1_BASE (0x302D0000u) |
| /** Peripheral GPT1 base pointer */ |
| #define GPT1 ((GPT_Type *)GPT1_BASE) |
| /** Peripheral GPT2 base address */ |
| #define GPT2_BASE (0x302E0000u) |
| /** Peripheral GPT2 base pointer */ |
| #define GPT2 ((GPT_Type *)GPT2_BASE) |
| /** Peripheral GPT3 base address */ |
| #define GPT3_BASE (0x302F0000u) |
| /** Peripheral GPT3 base pointer */ |
| #define GPT3 ((GPT_Type *)GPT3_BASE) |
| /** Peripheral GPT4 base address */ |
| #define GPT4_BASE (0x30700000u) |
| /** Peripheral GPT4 base pointer */ |
| #define GPT4 ((GPT_Type *)GPT4_BASE) |
| /** Peripheral GPT5 base address */ |
| #define GPT5_BASE (0x306F0000u) |
| /** Peripheral GPT5 base pointer */ |
| #define GPT5 ((GPT_Type *)GPT5_BASE) |
| /** Peripheral GPT6 base address */ |
| #define GPT6_BASE (0x306E0000u) |
| /** Peripheral GPT6 base pointer */ |
| #define GPT6 ((GPT_Type *)GPT6_BASE) |
| /** Array initializer of GPT peripheral base addresses */ |
| #define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE, GPT5_BASE, GPT6_BASE } |
| /** Array initializer of GPT peripheral base pointers */ |
| #define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2, GPT3, GPT4, GPT5, GPT6 } |
| /** Interrupt vectors for the GPT peripheral type */ |
| #define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn, GPT3_IRQn, GPT4_IRQn, GPT5_IRQn, GPT6_IRQn } |
| |
| /*! |
| * @} |
| */ /* end of group GPT_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- HDMI_TX Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup HDMI_TX_Peripheral_Access_Layer HDMI_TX Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** HDMI_TX - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t APB_CTRL; /**< , offset: 0x0 */ |
| __IO uint32_t XT_INT_CTRL; /**< , offset: 0x4 */ |
| __I uint32_t MAILBOX_FULL_ADDR; /**< , offset: 0x8 */ |
| __I uint32_t MAILBOX_EMPTY_ADDR; /**< , offset: 0xC */ |
| __IO uint32_t MAILBOX0_WR_DATA; /**< , offset: 0x10 */ |
| __I uint32_t MAILBOX0_RD_DATA; /**< , offset: 0x14 */ |
| __I uint32_t KEEP_ALIVE; /**< , offset: 0x18 */ |
| __I uint32_t VER_L; /**< , offset: 0x1C */ |
| __I uint32_t VER_H; /**< , offset: 0x20 */ |
| __I uint32_t VER_LIB_L_ADDR; /**< , offset: 0x24 */ |
| __I uint32_t VER_LIB_H_ADDR; /**< , offset: 0x28 */ |
| __I uint32_t SW_DEBUG_L; /**< , offset: 0x2C */ |
| __I uint32_t SW_DEBUG_H; /**< , offset: 0x30 */ |
| __IO uint32_t MAILBOX_INT_MASK; /**< , offset: 0x34 */ |
| __I uint32_t MAILBOX_INT_STATUS; /**< , offset: 0x38 */ |
| __IO uint32_t SW_CLK_L; /**< , offset: 0x3C */ |
| __IO uint32_t SW_CLK_H; /**< , offset: 0x40 */ |
| __I uint32_t SW_EVENTS0; /**< , offset: 0x44 */ |
| __I uint32_t SW_EVENTS1; /**< , offset: 0x48 */ |
| __I uint32_t SW_EVENTS2; /**< , offset: 0x4C */ |
| __I uint32_t SW_EVENTS3; /**< , offset: 0x50 */ |
| uint8_t RESERVED_0[12]; |
| __IO uint32_t XT_OCD_CTRL; /**< , offset: 0x60 */ |
| __I uint32_t XT_OCD_CTRL_RO; /**< , offset: 0x64 */ |
| uint8_t RESERVED_1[4]; |
| __IO uint32_t APB_INT_MASK; /**< , offset: 0x6C */ |
| __I uint32_t APB_STATUS_MASK; /**< , offset: 0x70 */ |
| uint8_t RESERVED_2[196492]; |
| __IO uint32_t AUDIO_SRC_CNTL; /**< , offset: 0x30000 */ |
| __IO uint32_t AUDIO_SRC_CNFG; /**< , offset: 0x30004 */ |
| __IO uint32_t COM_CH_STTS_BITS; /**< , offset: 0x30008 */ |
| __IO uint32_t STTS_BIT_CH01; /**< , offset: 0x3000C */ |
| __IO uint32_t STTS_BIT_CH23; /**< , offset: 0x30010 */ |
| __IO uint32_t STTS_BIT_CH45; /**< , offset: 0x30014 */ |
| __IO uint32_t STTS_BIT_CH67; /**< , offset: 0x30018 */ |
| __IO uint32_t STTS_BIT_CH89; /**< , offset: 0x3001C */ |
| __IO uint32_t STTS_BIT_CH1011; /**< , offset: 0x30020 */ |
| __IO uint32_t STTS_BIT_CH1213; /**< , offset: 0x30024 */ |
| __IO uint32_t STTS_BIT_CH1415; /**< , offset: 0x30028 */ |
| __IO uint32_t STTS_BIT_CH1617; /**< , offset: 0x3002C */ |
| __IO uint32_t STTS_BIT_CH1819; /**< , offset: 0x30030 */ |
| __IO uint32_t STTS_BIT_CH2021; /**< , offset: 0x30034 */ |
| __IO uint32_t STTS_BIT_CH2223; /**< , offset: 0x30038 */ |
| __IO uint32_t STTS_BIT_CH2425; /**< , offset: 0x3003C */ |
| __IO uint32_t STTS_BIT_CH2627; /**< , offset: 0x30040 */ |
| __IO uint32_t STTS_BIT_CH2829; /**< , offset: 0x30044 */ |
| __IO uint32_t STTS_BIT_CH3031; /**< , offset: 0x30048 */ |
| __IO uint32_t SPDIF_CTRL_ADDR; /**< , offset: 0x3004C */ |
| __I uint32_t SPDIF_CH1_CS_3100_ADDR; /**< , offset: 0x30050 */ |
| __I uint32_t SPDIF_CH1_CS_6332_ADDR; /**< , offset: 0x30054 */ |
| __I uint32_t SPDIF_CH1_CS_9564_ADDR; /**< , offset: 0x30058 */ |
| __I uint32_t SPDIF_CH1_CS_12796_ADDR; /**< , offset: 0x3005C */ |
| __I uint32_t SPDIF_CH1_CS_159128_ADDR; /**< , offset: 0x30060 */ |
| __I uint32_t SPDIF_CH1_CS_191160_ADDR; /**< , offset: 0x30064 */ |
| __I uint32_t SPDIF_CH2_CS_3100_ADDR; /**< , offset: 0x30068 */ |
| __I uint32_t SPDIF_CH2_CS_6332_ADDR; /**< , offset: 0x3006C */ |
| __I uint32_t SPDIF_CH2_CS_9564_ADDR; /**< , offset: 0x30070 */ |
| __I uint32_t SPDIF_CH2_CS_12796_ADDR; /**< , offset: 0x30074 */ |
| __I uint32_t SPDIF_CH2_CS_159128_ADDR; /**< , offset: 0x30078 */ |
| __I uint32_t SPDIF_CH2_CS_191160_ADDR; /**< , offset: 0x3007C */ |
| __IO uint32_t SMPL2PKT_CNTL; /**< , offset: 0x30080 */ |
| __IO uint32_t SMPL2PKT_CNFG; /**< , offset: 0x30084 */ |
| __IO uint32_t FIFO_CNTL; /**< , offset: 0x30088 */ |
| __I uint32_t FIFO_STTS; /**< , offset: 0x3008C */ |
| __IO uint32_t SUB_PCKT_THRSH; /**< , offset: 0x30090 */ |
| uint8_t RESERVED_3[1900]; |
| __IO uint32_t SOURCE_PIF_WR_ADDR; /**< , offset: 0x30800 */ |
| __IO uint32_t SOURCE_PIF_WR_REQ; /**< , offset: 0x30804 */ |
| __IO uint32_t SOURCE_PIF_RD_ADDR; /**< , offset: 0x30808 */ |
| __IO uint32_t SOURCE_PIF_RD_REQ; /**< , offset: 0x3080C */ |
| __IO uint32_t SOURCE_PIF_DATA_WR; /**< , offset: 0x30810 */ |
| __I uint32_t SOURCE_PIF_DATA_RD; /**< , offset: 0x30814 */ |
| __IO uint32_t SOURCE_PIF_FIFO1_FLUSH; /**< , offset: 0x30818 */ |
| __IO uint32_t SOURCE_PIF_FIFO2_FLUSH; /**< , offset: 0x3081C */ |
| __I uint32_t SOURCE_PIF_STATUS; /**< , offset: 0x30820 */ |
| __I uint32_t SOURCE_PIF_INTERRUPT_SOURCE; /**< , offset: 0x30824 */ |
| __IO uint32_t SOURCE_PIF_INTERRUPT_MASK; /**< , offset: 0x30828 */ |
| __IO uint32_t SOURCE_PIF_PKT_ALLOC_REG; /**< , offset: 0x3082C */ |
| __IO uint32_t SOURCE_PIF_PKT_ALLOC_WR_EN; /**< , offset: 0x30830 */ |
| __IO uint32_t SOURCE_PIF_SW_RESET; /**< , offset: 0x30834 */ |
| } HDMI_TX_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- HDMI_TX Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup HDMI_TX_Register_Masks HDMI_TX Register Masks |
| * @{ |
| */ |
| |
| /*! @name APB_CTRL - */ |
| /*! @{ */ |
| #define HDMI_TX_APB_CTRL_apb_xt_reset_MASK (0x1U) |
| #define HDMI_TX_APB_CTRL_apb_xt_reset_SHIFT (0U) |
| #define HDMI_TX_APB_CTRL_apb_xt_reset(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_CTRL_apb_xt_reset_SHIFT)) & HDMI_TX_APB_CTRL_apb_xt_reset_MASK) |
| #define HDMI_TX_APB_CTRL_apb_dram_path_MASK (0x2U) |
| #define HDMI_TX_APB_CTRL_apb_dram_path_SHIFT (1U) |
| #define HDMI_TX_APB_CTRL_apb_dram_path(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_CTRL_apb_dram_path_SHIFT)) & HDMI_TX_APB_CTRL_apb_dram_path_MASK) |
| #define HDMI_TX_APB_CTRL_apb_iram_path_MASK (0x4U) |
| #define HDMI_TX_APB_CTRL_apb_iram_path_SHIFT (2U) |
| #define HDMI_TX_APB_CTRL_apb_iram_path(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_CTRL_apb_iram_path_SHIFT)) & HDMI_TX_APB_CTRL_apb_iram_path_MASK) |
| #define HDMI_TX_APB_CTRL_reserved_0_MASK (0xFFFFFFF8U) |
| #define HDMI_TX_APB_CTRL_reserved_0_SHIFT (3U) |
| #define HDMI_TX_APB_CTRL_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_CTRL_reserved_0_SHIFT)) & HDMI_TX_APB_CTRL_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name XT_INT_CTRL - */ |
| /*! @{ */ |
| #define HDMI_TX_XT_INT_CTRL_xt_int_polarity_MASK (0x3U) |
| #define HDMI_TX_XT_INT_CTRL_xt_int_polarity_SHIFT (0U) |
| #define HDMI_TX_XT_INT_CTRL_xt_int_polarity(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_XT_INT_CTRL_xt_int_polarity_SHIFT)) & HDMI_TX_XT_INT_CTRL_xt_int_polarity_MASK) |
| #define HDMI_TX_XT_INT_CTRL_reserved_0_MASK (0xFFFFFFFCU) |
| #define HDMI_TX_XT_INT_CTRL_reserved_0_SHIFT (2U) |
| #define HDMI_TX_XT_INT_CTRL_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_XT_INT_CTRL_reserved_0_SHIFT)) & HDMI_TX_XT_INT_CTRL_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name MAILBOX_FULL_ADDR - */ |
| /*! @{ */ |
| #define HDMI_TX_MAILBOX_FULL_ADDR_mailbox_full_MASK (0x1U) |
| #define HDMI_TX_MAILBOX_FULL_ADDR_mailbox_full_SHIFT (0U) |
| #define HDMI_TX_MAILBOX_FULL_ADDR_mailbox_full(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_FULL_ADDR_mailbox_full_SHIFT)) & HDMI_TX_MAILBOX_FULL_ADDR_mailbox_full_MASK) |
| #define HDMI_TX_MAILBOX_FULL_ADDR_reserved_0_MASK (0xFFFFFFFEU) |
| #define HDMI_TX_MAILBOX_FULL_ADDR_reserved_0_SHIFT (1U) |
| #define HDMI_TX_MAILBOX_FULL_ADDR_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_FULL_ADDR_reserved_0_SHIFT)) & HDMI_TX_MAILBOX_FULL_ADDR_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name MAILBOX_EMPTY_ADDR - */ |
| /*! @{ */ |
| #define HDMI_TX_MAILBOX_EMPTY_ADDR_mailbox_empty_MASK (0x1U) |
| #define HDMI_TX_MAILBOX_EMPTY_ADDR_mailbox_empty_SHIFT (0U) |
| #define HDMI_TX_MAILBOX_EMPTY_ADDR_mailbox_empty(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_EMPTY_ADDR_mailbox_empty_SHIFT)) & HDMI_TX_MAILBOX_EMPTY_ADDR_mailbox_empty_MASK) |
| #define HDMI_TX_MAILBOX_EMPTY_ADDR_reserved_0_MASK (0xFFFFFFFEU) |
| #define HDMI_TX_MAILBOX_EMPTY_ADDR_reserved_0_SHIFT (1U) |
| #define HDMI_TX_MAILBOX_EMPTY_ADDR_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_EMPTY_ADDR_reserved_0_SHIFT)) & HDMI_TX_MAILBOX_EMPTY_ADDR_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name MAILBOX0_WR_DATA - */ |
| /*! @{ */ |
| #define HDMI_TX_MAILBOX0_WR_DATA_mailbox0_wr_data_MASK (0xFFU) |
| #define HDMI_TX_MAILBOX0_WR_DATA_mailbox0_wr_data_SHIFT (0U) |
| #define HDMI_TX_MAILBOX0_WR_DATA_mailbox0_wr_data(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX0_WR_DATA_mailbox0_wr_data_SHIFT)) & HDMI_TX_MAILBOX0_WR_DATA_mailbox0_wr_data_MASK) |
| #define HDMI_TX_MAILBOX0_WR_DATA_reserved_0_MASK (0xFFFFFF00U) |
| #define HDMI_TX_MAILBOX0_WR_DATA_reserved_0_SHIFT (8U) |
| #define HDMI_TX_MAILBOX0_WR_DATA_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX0_WR_DATA_reserved_0_SHIFT)) & HDMI_TX_MAILBOX0_WR_DATA_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name MAILBOX0_RD_DATA - */ |
| /*! @{ */ |
| #define HDMI_TX_MAILBOX0_RD_DATA_mailbox0_rd_data_MASK (0xFFU) |
| #define HDMI_TX_MAILBOX0_RD_DATA_mailbox0_rd_data_SHIFT (0U) |
| #define HDMI_TX_MAILBOX0_RD_DATA_mailbox0_rd_data(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX0_RD_DATA_mailbox0_rd_data_SHIFT)) & HDMI_TX_MAILBOX0_RD_DATA_mailbox0_rd_data_MASK) |
| #define HDMI_TX_MAILBOX0_RD_DATA_reserved_0_MASK (0xFFFFFF00U) |
| #define HDMI_TX_MAILBOX0_RD_DATA_reserved_0_SHIFT (8U) |
| #define HDMI_TX_MAILBOX0_RD_DATA_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX0_RD_DATA_reserved_0_SHIFT)) & HDMI_TX_MAILBOX0_RD_DATA_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name KEEP_ALIVE - */ |
| /*! @{ */ |
| #define HDMI_TX_KEEP_ALIVE_keep_alive_cnt_MASK (0xFFU) |
| #define HDMI_TX_KEEP_ALIVE_keep_alive_cnt_SHIFT (0U) |
| #define HDMI_TX_KEEP_ALIVE_keep_alive_cnt(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_KEEP_ALIVE_keep_alive_cnt_SHIFT)) & HDMI_TX_KEEP_ALIVE_keep_alive_cnt_MASK) |
| #define HDMI_TX_KEEP_ALIVE_reserved_0_MASK (0xFFFFFF00U) |
| #define HDMI_TX_KEEP_ALIVE_reserved_0_SHIFT (8U) |
| #define HDMI_TX_KEEP_ALIVE_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_KEEP_ALIVE_reserved_0_SHIFT)) & HDMI_TX_KEEP_ALIVE_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name VER_L - */ |
| /*! @{ */ |
| #define HDMI_TX_VER_L_ver_lsb_MASK (0xFFU) |
| #define HDMI_TX_VER_L_ver_lsb_SHIFT (0U) |
| #define HDMI_TX_VER_L_ver_lsb(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_L_ver_lsb_SHIFT)) & HDMI_TX_VER_L_ver_lsb_MASK) |
| #define HDMI_TX_VER_L_reserved_0_MASK (0xFFFFFF00U) |
| #define HDMI_TX_VER_L_reserved_0_SHIFT (8U) |
| #define HDMI_TX_VER_L_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_L_reserved_0_SHIFT)) & HDMI_TX_VER_L_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name VER_H - */ |
| /*! @{ */ |
| #define HDMI_TX_VER_H_ver_msb_MASK (0xFFU) |
| #define HDMI_TX_VER_H_ver_msb_SHIFT (0U) |
| #define HDMI_TX_VER_H_ver_msb(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_H_ver_msb_SHIFT)) & HDMI_TX_VER_H_ver_msb_MASK) |
| #define HDMI_TX_VER_H_reserved_0_MASK (0xFFFFFF00U) |
| #define HDMI_TX_VER_H_reserved_0_SHIFT (8U) |
| #define HDMI_TX_VER_H_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_H_reserved_0_SHIFT)) & HDMI_TX_VER_H_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name VER_LIB_L_ADDR - */ |
| /*! @{ */ |
| #define HDMI_TX_VER_LIB_L_ADDR_sw_lib_ver_l_MASK (0xFFU) |
| #define HDMI_TX_VER_LIB_L_ADDR_sw_lib_ver_l_SHIFT (0U) |
| #define HDMI_TX_VER_LIB_L_ADDR_sw_lib_ver_l(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_LIB_L_ADDR_sw_lib_ver_l_SHIFT)) & HDMI_TX_VER_LIB_L_ADDR_sw_lib_ver_l_MASK) |
| #define HDMI_TX_VER_LIB_L_ADDR_reserved_0_MASK (0xFFFFFF00U) |
| #define HDMI_TX_VER_LIB_L_ADDR_reserved_0_SHIFT (8U) |
| #define HDMI_TX_VER_LIB_L_ADDR_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_LIB_L_ADDR_reserved_0_SHIFT)) & HDMI_TX_VER_LIB_L_ADDR_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name VER_LIB_H_ADDR - */ |
| /*! @{ */ |
| #define HDMI_TX_VER_LIB_H_ADDR_sw_lib_ver_h_MASK (0xFFU) |
| #define HDMI_TX_VER_LIB_H_ADDR_sw_lib_ver_h_SHIFT (0U) |
| #define HDMI_TX_VER_LIB_H_ADDR_sw_lib_ver_h(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_LIB_H_ADDR_sw_lib_ver_h_SHIFT)) & HDMI_TX_VER_LIB_H_ADDR_sw_lib_ver_h_MASK) |
| #define HDMI_TX_VER_LIB_H_ADDR_reserved_0_MASK (0xFFFFFF00U) |
| #define HDMI_TX_VER_LIB_H_ADDR_reserved_0_SHIFT (8U) |
| #define HDMI_TX_VER_LIB_H_ADDR_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_VER_LIB_H_ADDR_reserved_0_SHIFT)) & HDMI_TX_VER_LIB_H_ADDR_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SW_DEBUG_L - */ |
| /*! @{ */ |
| #define HDMI_TX_SW_DEBUG_L_sw_debug_7_0_MASK (0xFFU) |
| #define HDMI_TX_SW_DEBUG_L_sw_debug_7_0_SHIFT (0U) |
| #define HDMI_TX_SW_DEBUG_L_sw_debug_7_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_DEBUG_L_sw_debug_7_0_SHIFT)) & HDMI_TX_SW_DEBUG_L_sw_debug_7_0_MASK) |
| #define HDMI_TX_SW_DEBUG_L_reserved_0_MASK (0xFFFFFF00U) |
| #define HDMI_TX_SW_DEBUG_L_reserved_0_SHIFT (8U) |
| #define HDMI_TX_SW_DEBUG_L_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_DEBUG_L_reserved_0_SHIFT)) & HDMI_TX_SW_DEBUG_L_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SW_DEBUG_H - */ |
| /*! @{ */ |
| #define HDMI_TX_SW_DEBUG_H_sw_debug_15_8_MASK (0xFFU) |
| #define HDMI_TX_SW_DEBUG_H_sw_debug_15_8_SHIFT (0U) |
| #define HDMI_TX_SW_DEBUG_H_sw_debug_15_8(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_DEBUG_H_sw_debug_15_8_SHIFT)) & HDMI_TX_SW_DEBUG_H_sw_debug_15_8_MASK) |
| #define HDMI_TX_SW_DEBUG_H_reserved_0_MASK (0xFFFFFF00U) |
| #define HDMI_TX_SW_DEBUG_H_reserved_0_SHIFT (8U) |
| #define HDMI_TX_SW_DEBUG_H_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_DEBUG_H_reserved_0_SHIFT)) & HDMI_TX_SW_DEBUG_H_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name MAILBOX_INT_MASK - */ |
| /*! @{ */ |
| #define HDMI_TX_MAILBOX_INT_MASK_mailbox_int_mask_MASK (0x3U) |
| #define HDMI_TX_MAILBOX_INT_MASK_mailbox_int_mask_SHIFT (0U) |
| #define HDMI_TX_MAILBOX_INT_MASK_mailbox_int_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_INT_MASK_mailbox_int_mask_SHIFT)) & HDMI_TX_MAILBOX_INT_MASK_mailbox_int_mask_MASK) |
| #define HDMI_TX_MAILBOX_INT_MASK_reserved_0_MASK (0xFFFFFFFCU) |
| #define HDMI_TX_MAILBOX_INT_MASK_reserved_0_SHIFT (2U) |
| #define HDMI_TX_MAILBOX_INT_MASK_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_INT_MASK_reserved_0_SHIFT)) & HDMI_TX_MAILBOX_INT_MASK_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name MAILBOX_INT_STATUS - */ |
| /*! @{ */ |
| #define HDMI_TX_MAILBOX_INT_STATUS_mailbox_int_status_MASK (0x3U) |
| #define HDMI_TX_MAILBOX_INT_STATUS_mailbox_int_status_SHIFT (0U) |
| #define HDMI_TX_MAILBOX_INT_STATUS_mailbox_int_status(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_INT_STATUS_mailbox_int_status_SHIFT)) & HDMI_TX_MAILBOX_INT_STATUS_mailbox_int_status_MASK) |
| #define HDMI_TX_MAILBOX_INT_STATUS_reserved_0_MASK (0xFFFFFFFCU) |
| #define HDMI_TX_MAILBOX_INT_STATUS_reserved_0_SHIFT (2U) |
| #define HDMI_TX_MAILBOX_INT_STATUS_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_MAILBOX_INT_STATUS_reserved_0_SHIFT)) & HDMI_TX_MAILBOX_INT_STATUS_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SW_CLK_L - */ |
| /*! @{ */ |
| #define HDMI_TX_SW_CLK_L_sw_clock_val_l_MASK (0xFFU) |
| #define HDMI_TX_SW_CLK_L_sw_clock_val_l_SHIFT (0U) |
| #define HDMI_TX_SW_CLK_L_sw_clock_val_l(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_CLK_L_sw_clock_val_l_SHIFT)) & HDMI_TX_SW_CLK_L_sw_clock_val_l_MASK) |
| #define HDMI_TX_SW_CLK_L_reserved_0_MASK (0xFFFFFF00U) |
| #define HDMI_TX_SW_CLK_L_reserved_0_SHIFT (8U) |
| #define HDMI_TX_SW_CLK_L_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_CLK_L_reserved_0_SHIFT)) & HDMI_TX_SW_CLK_L_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SW_CLK_H - */ |
| /*! @{ */ |
| #define HDMI_TX_SW_CLK_H_sw_clock_val_h_MASK (0xFFU) |
| #define HDMI_TX_SW_CLK_H_sw_clock_val_h_SHIFT (0U) |
| #define HDMI_TX_SW_CLK_H_sw_clock_val_h(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_CLK_H_sw_clock_val_h_SHIFT)) & HDMI_TX_SW_CLK_H_sw_clock_val_h_MASK) |
| #define HDMI_TX_SW_CLK_H_reserved_0_MASK (0xFFFFFF00U) |
| #define HDMI_TX_SW_CLK_H_reserved_0_SHIFT (8U) |
| #define HDMI_TX_SW_CLK_H_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_CLK_H_reserved_0_SHIFT)) & HDMI_TX_SW_CLK_H_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SW_EVENTS0 - */ |
| /*! @{ */ |
| #define HDMI_TX_SW_EVENTS0_sw_events7_0_MASK (0xFFU) |
| #define HDMI_TX_SW_EVENTS0_sw_events7_0_SHIFT (0U) |
| #define HDMI_TX_SW_EVENTS0_sw_events7_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS0_sw_events7_0_SHIFT)) & HDMI_TX_SW_EVENTS0_sw_events7_0_MASK) |
| #define HDMI_TX_SW_EVENTS0_reserved_0_MASK (0xFFFFFF00U) |
| #define HDMI_TX_SW_EVENTS0_reserved_0_SHIFT (8U) |
| #define HDMI_TX_SW_EVENTS0_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS0_reserved_0_SHIFT)) & HDMI_TX_SW_EVENTS0_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SW_EVENTS1 - */ |
| /*! @{ */ |
| #define HDMI_TX_SW_EVENTS1_sw_events15_8_MASK (0xFFU) |
| #define HDMI_TX_SW_EVENTS1_sw_events15_8_SHIFT (0U) |
| #define HDMI_TX_SW_EVENTS1_sw_events15_8(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS1_sw_events15_8_SHIFT)) & HDMI_TX_SW_EVENTS1_sw_events15_8_MASK) |
| #define HDMI_TX_SW_EVENTS1_reserved_0_MASK (0xFFFFFF00U) |
| #define HDMI_TX_SW_EVENTS1_reserved_0_SHIFT (8U) |
| #define HDMI_TX_SW_EVENTS1_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS1_reserved_0_SHIFT)) & HDMI_TX_SW_EVENTS1_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SW_EVENTS2 - */ |
| /*! @{ */ |
| #define HDMI_TX_SW_EVENTS2_sw_events23_16_MASK (0xFFU) |
| #define HDMI_TX_SW_EVENTS2_sw_events23_16_SHIFT (0U) |
| #define HDMI_TX_SW_EVENTS2_sw_events23_16(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS2_sw_events23_16_SHIFT)) & HDMI_TX_SW_EVENTS2_sw_events23_16_MASK) |
| #define HDMI_TX_SW_EVENTS2_reserved_0_MASK (0xFFFFFF00U) |
| #define HDMI_TX_SW_EVENTS2_reserved_0_SHIFT (8U) |
| #define HDMI_TX_SW_EVENTS2_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS2_reserved_0_SHIFT)) & HDMI_TX_SW_EVENTS2_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SW_EVENTS3 - */ |
| /*! @{ */ |
| #define HDMI_TX_SW_EVENTS3_sw_events31_24_MASK (0xFFU) |
| #define HDMI_TX_SW_EVENTS3_sw_events31_24_SHIFT (0U) |
| #define HDMI_TX_SW_EVENTS3_sw_events31_24(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS3_sw_events31_24_SHIFT)) & HDMI_TX_SW_EVENTS3_sw_events31_24_MASK) |
| #define HDMI_TX_SW_EVENTS3_reserved_0_MASK (0xFFFFFF00U) |
| #define HDMI_TX_SW_EVENTS3_reserved_0_SHIFT (8U) |
| #define HDMI_TX_SW_EVENTS3_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SW_EVENTS3_reserved_0_SHIFT)) & HDMI_TX_SW_EVENTS3_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name XT_OCD_CTRL - */ |
| /*! @{ */ |
| #define HDMI_TX_XT_OCD_CTRL_xt_dreset_MASK (0x1U) |
| #define HDMI_TX_XT_OCD_CTRL_xt_dreset_SHIFT (0U) |
| #define HDMI_TX_XT_OCD_CTRL_xt_dreset(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_XT_OCD_CTRL_xt_dreset_SHIFT)) & HDMI_TX_XT_OCD_CTRL_xt_dreset_MASK) |
| #define HDMI_TX_XT_OCD_CTRL_xt_ocdhaltonreset_MASK (0x2U) |
| #define HDMI_TX_XT_OCD_CTRL_xt_ocdhaltonreset_SHIFT (1U) |
| #define HDMI_TX_XT_OCD_CTRL_xt_ocdhaltonreset(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_XT_OCD_CTRL_xt_ocdhaltonreset_SHIFT)) & HDMI_TX_XT_OCD_CTRL_xt_ocdhaltonreset_MASK) |
| #define HDMI_TX_XT_OCD_CTRL_reserved_0_MASK (0xFFFFFFFCU) |
| #define HDMI_TX_XT_OCD_CTRL_reserved_0_SHIFT (2U) |
| #define HDMI_TX_XT_OCD_CTRL_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_XT_OCD_CTRL_reserved_0_SHIFT)) & HDMI_TX_XT_OCD_CTRL_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name XT_OCD_CTRL_RO - */ |
| /*! @{ */ |
| #define HDMI_TX_XT_OCD_CTRL_RO_xt_xocdmode_MASK (0x1U) |
| #define HDMI_TX_XT_OCD_CTRL_RO_xt_xocdmode_SHIFT (0U) |
| #define HDMI_TX_XT_OCD_CTRL_RO_xt_xocdmode(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_XT_OCD_CTRL_RO_xt_xocdmode_SHIFT)) & HDMI_TX_XT_OCD_CTRL_RO_xt_xocdmode_MASK) |
| #define HDMI_TX_XT_OCD_CTRL_RO_reserved_0_MASK (0xFFFFFFFEU) |
| #define HDMI_TX_XT_OCD_CTRL_RO_reserved_0_SHIFT (1U) |
| #define HDMI_TX_XT_OCD_CTRL_RO_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_XT_OCD_CTRL_RO_reserved_0_SHIFT)) & HDMI_TX_XT_OCD_CTRL_RO_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name APB_INT_MASK - */ |
| /*! @{ */ |
| #define HDMI_TX_APB_INT_MASK_apb_intr_mask_MASK (0x7U) |
| #define HDMI_TX_APB_INT_MASK_apb_intr_mask_SHIFT (0U) |
| #define HDMI_TX_APB_INT_MASK_apb_intr_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_INT_MASK_apb_intr_mask_SHIFT)) & HDMI_TX_APB_INT_MASK_apb_intr_mask_MASK) |
| #define HDMI_TX_APB_INT_MASK_reserved_0_MASK (0xFFFFFFF8U) |
| #define HDMI_TX_APB_INT_MASK_reserved_0_SHIFT (3U) |
| #define HDMI_TX_APB_INT_MASK_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_INT_MASK_reserved_0_SHIFT)) & HDMI_TX_APB_INT_MASK_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name APB_STATUS_MASK - */ |
| /*! @{ */ |
| #define HDMI_TX_APB_STATUS_MASK_apb_intr_status_MASK (0x7U) |
| #define HDMI_TX_APB_STATUS_MASK_apb_intr_status_SHIFT (0U) |
| #define HDMI_TX_APB_STATUS_MASK_apb_intr_status(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_STATUS_MASK_apb_intr_status_SHIFT)) & HDMI_TX_APB_STATUS_MASK_apb_intr_status_MASK) |
| #define HDMI_TX_APB_STATUS_MASK_reserved_0_MASK (0xFFFFFFF8U) |
| #define HDMI_TX_APB_STATUS_MASK_reserved_0_SHIFT (3U) |
| #define HDMI_TX_APB_STATUS_MASK_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_APB_STATUS_MASK_reserved_0_SHIFT)) & HDMI_TX_APB_STATUS_MASK_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name AUDIO_SRC_CNTL - */ |
| /*! @{ */ |
| #define HDMI_TX_AUDIO_SRC_CNTL_sw_rst_MASK (0x1U) |
| #define HDMI_TX_AUDIO_SRC_CNTL_sw_rst_SHIFT (0U) |
| #define HDMI_TX_AUDIO_SRC_CNTL_sw_rst(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_sw_rst_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_sw_rst_MASK) |
| #define HDMI_TX_AUDIO_SRC_CNTL_i2s_dec_start_MASK (0x2U) |
| #define HDMI_TX_AUDIO_SRC_CNTL_i2s_dec_start_SHIFT (1U) |
| #define HDMI_TX_AUDIO_SRC_CNTL_i2s_dec_start(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_i2s_dec_start_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_i2s_dec_start_MASK) |
| #define HDMI_TX_AUDIO_SRC_CNTL_i2s_block_start_force_MASK (0x4U) |
| #define HDMI_TX_AUDIO_SRC_CNTL_i2s_block_start_force_SHIFT (2U) |
| #define HDMI_TX_AUDIO_SRC_CNTL_i2s_block_start_force(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_i2s_block_start_force_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_i2s_block_start_force_MASK) |
| #define HDMI_TX_AUDIO_SRC_CNTL_spdif_ts_en_MASK (0x8U) |
| #define HDMI_TX_AUDIO_SRC_CNTL_spdif_ts_en_SHIFT (3U) |
| #define HDMI_TX_AUDIO_SRC_CNTL_spdif_ts_en(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_spdif_ts_en_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_spdif_ts_en_MASK) |
| #define HDMI_TX_AUDIO_SRC_CNTL_i2s_ts_en_MASK (0x10U) |
| #define HDMI_TX_AUDIO_SRC_CNTL_i2s_ts_en_SHIFT (4U) |
| #define HDMI_TX_AUDIO_SRC_CNTL_i2s_ts_en(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_i2s_ts_en_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_i2s_ts_en_MASK) |
| #define HDMI_TX_AUDIO_SRC_CNTL_valid_bits_force_MASK (0x20U) |
| #define HDMI_TX_AUDIO_SRC_CNTL_valid_bits_force_SHIFT (5U) |
| #define HDMI_TX_AUDIO_SRC_CNTL_valid_bits_force(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_valid_bits_force_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_valid_bits_force_MASK) |
| #define HDMI_TX_AUDIO_SRC_CNTL_valid_all_MASK (0x40U) |
| #define HDMI_TX_AUDIO_SRC_CNTL_valid_all_SHIFT (6U) |
| #define HDMI_TX_AUDIO_SRC_CNTL_valid_all(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_valid_all_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_valid_all_MASK) |
| #define HDMI_TX_AUDIO_SRC_CNTL_reserved_0_MASK (0xFFFFFF80U) |
| #define HDMI_TX_AUDIO_SRC_CNTL_reserved_0_SHIFT (7U) |
| #define HDMI_TX_AUDIO_SRC_CNTL_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNTL_reserved_0_SHIFT)) & HDMI_TX_AUDIO_SRC_CNTL_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name AUDIO_SRC_CNFG - */ |
| /*! @{ */ |
| #define HDMI_TX_AUDIO_SRC_CNFG_low_index_msb_MASK (0x1U) |
| #define HDMI_TX_AUDIO_SRC_CNFG_low_index_msb_SHIFT (0U) |
| #define HDMI_TX_AUDIO_SRC_CNFG_low_index_msb(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_low_index_msb_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_low_index_msb_MASK) |
| #define HDMI_TX_AUDIO_SRC_CNFG_ws_polarity_MASK (0x2U) |
| #define HDMI_TX_AUDIO_SRC_CNFG_ws_polarity_SHIFT (1U) |
| #define HDMI_TX_AUDIO_SRC_CNFG_ws_polarity(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_ws_polarity_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_ws_polarity_MASK) |
| #define HDMI_TX_AUDIO_SRC_CNFG_audio_ch_num_MASK (0x7CU) |
| #define HDMI_TX_AUDIO_SRC_CNFG_audio_ch_num_SHIFT (2U) |
| #define HDMI_TX_AUDIO_SRC_CNFG_audio_ch_num(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_audio_ch_num_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_audio_ch_num_MASK) |
| #define HDMI_TX_AUDIO_SRC_CNFG_audio_sample_just_MASK (0x180U) |
| #define HDMI_TX_AUDIO_SRC_CNFG_audio_sample_just_SHIFT (7U) |
| #define HDMI_TX_AUDIO_SRC_CNFG_audio_sample_just(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_audio_sample_just_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_audio_sample_just_MASK) |
| #define HDMI_TX_AUDIO_SRC_CNFG_audio_sample_width_MASK (0x600U) |
| #define HDMI_TX_AUDIO_SRC_CNFG_audio_sample_width_SHIFT (9U) |
| #define HDMI_TX_AUDIO_SRC_CNFG_audio_sample_width(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_audio_sample_width_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_audio_sample_width_MASK) |
| #define HDMI_TX_AUDIO_SRC_CNFG_trans_smpl_width_MASK (0x1800U) |
| #define HDMI_TX_AUDIO_SRC_CNFG_trans_smpl_width_SHIFT (11U) |
| #define HDMI_TX_AUDIO_SRC_CNFG_trans_smpl_width(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_trans_smpl_width_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_trans_smpl_width_MASK) |
| #define HDMI_TX_AUDIO_SRC_CNFG_audio_channel_type_MASK (0x1E000U) |
| #define HDMI_TX_AUDIO_SRC_CNFG_audio_channel_type_SHIFT (13U) |
| #define HDMI_TX_AUDIO_SRC_CNFG_audio_channel_type(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_audio_channel_type_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_audio_channel_type_MASK) |
| #define HDMI_TX_AUDIO_SRC_CNFG_i2s_dec_port_en_MASK (0x1E0000U) |
| #define HDMI_TX_AUDIO_SRC_CNFG_i2s_dec_port_en_SHIFT (17U) |
| #define HDMI_TX_AUDIO_SRC_CNFG_i2s_dec_port_en(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_i2s_dec_port_en_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_i2s_dec_port_en_MASK) |
| #define HDMI_TX_AUDIO_SRC_CNFG_reserved_0_MASK (0xFFE00000U) |
| #define HDMI_TX_AUDIO_SRC_CNFG_reserved_0_SHIFT (21U) |
| #define HDMI_TX_AUDIO_SRC_CNFG_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_AUDIO_SRC_CNFG_reserved_0_SHIFT)) & HDMI_TX_AUDIO_SRC_CNFG_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name COM_CH_STTS_BITS - */ |
| /*! @{ */ |
| #define HDMI_TX_COM_CH_STTS_BITS_Byte0_MASK (0xFFU) |
| #define HDMI_TX_COM_CH_STTS_BITS_Byte0_SHIFT (0U) |
| #define HDMI_TX_COM_CH_STTS_BITS_Byte0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_COM_CH_STTS_BITS_Byte0_SHIFT)) & HDMI_TX_COM_CH_STTS_BITS_Byte0_MASK) |
| #define HDMI_TX_COM_CH_STTS_BITS_Category_Code_MASK (0xFF00U) |
| #define HDMI_TX_COM_CH_STTS_BITS_Category_Code_SHIFT (8U) |
| #define HDMI_TX_COM_CH_STTS_BITS_Category_Code(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_COM_CH_STTS_BITS_Category_Code_SHIFT)) & HDMI_TX_COM_CH_STTS_BITS_Category_Code_MASK) |
| #define HDMI_TX_COM_CH_STTS_BITS_Sampling_Freq_MASK (0xF0000U) |
| #define HDMI_TX_COM_CH_STTS_BITS_Sampling_Freq_SHIFT (16U) |
| #define HDMI_TX_COM_CH_STTS_BITS_Sampling_Freq(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_COM_CH_STTS_BITS_Sampling_Freq_SHIFT)) & HDMI_TX_COM_CH_STTS_BITS_Sampling_Freq_MASK) |
| #define HDMI_TX_COM_CH_STTS_BITS_Clock_accuracy_MASK (0xF00000U) |
| #define HDMI_TX_COM_CH_STTS_BITS_Clock_accuracy_SHIFT (20U) |
| #define HDMI_TX_COM_CH_STTS_BITS_Clock_accuracy(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_COM_CH_STTS_BITS_Clock_accuracy_SHIFT)) & HDMI_TX_COM_CH_STTS_BITS_Clock_accuracy_MASK) |
| #define HDMI_TX_COM_CH_STTS_BITS_Original_samp_freq_MASK (0xF000000U) |
| #define HDMI_TX_COM_CH_STTS_BITS_Original_samp_freq_SHIFT (24U) |
| #define HDMI_TX_COM_CH_STTS_BITS_Original_samp_freq(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_COM_CH_STTS_BITS_Original_samp_freq_SHIFT)) & HDMI_TX_COM_CH_STTS_BITS_Original_samp_freq_MASK) |
| #define HDMI_TX_COM_CH_STTS_BITS_reserved_0_MASK (0xF0000000U) |
| #define HDMI_TX_COM_CH_STTS_BITS_reserved_0_SHIFT (28U) |
| #define HDMI_TX_COM_CH_STTS_BITS_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_COM_CH_STTS_BITS_reserved_0_SHIFT)) & HDMI_TX_COM_CH_STTS_BITS_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name STTS_BIT_CH01 - */ |
| /*! @{ */ |
| #define HDMI_TX_STTS_BIT_CH01_source_num_ch0_MASK (0xFU) |
| #define HDMI_TX_STTS_BIT_CH01_source_num_ch0_SHIFT (0U) |
| #define HDMI_TX_STTS_BIT_CH01_source_num_ch0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_source_num_ch0_SHIFT)) & HDMI_TX_STTS_BIT_CH01_source_num_ch0_MASK) |
| #define HDMI_TX_STTS_BIT_CH01_channel_num_ch0_MASK (0xF0U) |
| #define HDMI_TX_STTS_BIT_CH01_channel_num_ch0_SHIFT (4U) |
| #define HDMI_TX_STTS_BIT_CH01_channel_num_ch0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_channel_num_ch0_SHIFT)) & HDMI_TX_STTS_BIT_CH01_channel_num_ch0_MASK) |
| #define HDMI_TX_STTS_BIT_CH01_word_length_ch0_MASK (0xF00U) |
| #define HDMI_TX_STTS_BIT_CH01_word_length_ch0_SHIFT (8U) |
| #define HDMI_TX_STTS_BIT_CH01_word_length_ch0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_word_length_ch0_SHIFT)) & HDMI_TX_STTS_BIT_CH01_word_length_ch0_MASK) |
| #define HDMI_TX_STTS_BIT_CH01_source_num_ch1_MASK (0xF000U) |
| #define HDMI_TX_STTS_BIT_CH01_source_num_ch1_SHIFT (12U) |
| #define HDMI_TX_STTS_BIT_CH01_source_num_ch1(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_source_num_ch1_SHIFT)) & HDMI_TX_STTS_BIT_CH01_source_num_ch1_MASK) |
| #define HDMI_TX_STTS_BIT_CH01_channel_num_ch1_MASK (0xF0000U) |
| #define HDMI_TX_STTS_BIT_CH01_channel_num_ch1_SHIFT (16U) |
| #define HDMI_TX_STTS_BIT_CH01_channel_num_ch1(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_channel_num_ch1_SHIFT)) & HDMI_TX_STTS_BIT_CH01_channel_num_ch1_MASK) |
| #define HDMI_TX_STTS_BIT_CH01_word_length_ch1_MASK (0xF00000U) |
| #define HDMI_TX_STTS_BIT_CH01_word_length_ch1_SHIFT (20U) |
| #define HDMI_TX_STTS_BIT_CH01_word_length_ch1(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_word_length_ch1_SHIFT)) & HDMI_TX_STTS_BIT_CH01_word_length_ch1_MASK) |
| #define HDMI_TX_STTS_BIT_CH01_valid_bits1_0_MASK (0x3000000U) |
| #define HDMI_TX_STTS_BIT_CH01_valid_bits1_0_SHIFT (24U) |
| #define HDMI_TX_STTS_BIT_CH01_valid_bits1_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_valid_bits1_0_SHIFT)) & HDMI_TX_STTS_BIT_CH01_valid_bits1_0_MASK) |
| #define HDMI_TX_STTS_BIT_CH01_reserved_0_MASK (0xFC000000U) |
| #define HDMI_TX_STTS_BIT_CH01_reserved_0_SHIFT (26U) |
| #define HDMI_TX_STTS_BIT_CH01_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH01_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH01_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name STTS_BIT_CH23 - */ |
| /*! @{ */ |
| #define HDMI_TX_STTS_BIT_CH23_source_num_ch2_MASK (0xFU) |
| #define HDMI_TX_STTS_BIT_CH23_source_num_ch2_SHIFT (0U) |
| #define HDMI_TX_STTS_BIT_CH23_source_num_ch2(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_source_num_ch2_SHIFT)) & HDMI_TX_STTS_BIT_CH23_source_num_ch2_MASK) |
| #define HDMI_TX_STTS_BIT_CH23_channel_num_ch2_MASK (0xF0U) |
| #define HDMI_TX_STTS_BIT_CH23_channel_num_ch2_SHIFT (4U) |
| #define HDMI_TX_STTS_BIT_CH23_channel_num_ch2(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_channel_num_ch2_SHIFT)) & HDMI_TX_STTS_BIT_CH23_channel_num_ch2_MASK) |
| #define HDMI_TX_STTS_BIT_CH23_word_length_ch2_MASK (0xF00U) |
| #define HDMI_TX_STTS_BIT_CH23_word_length_ch2_SHIFT (8U) |
| #define HDMI_TX_STTS_BIT_CH23_word_length_ch2(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_word_length_ch2_SHIFT)) & HDMI_TX_STTS_BIT_CH23_word_length_ch2_MASK) |
| #define HDMI_TX_STTS_BIT_CH23_source_num_ch3_MASK (0xF000U) |
| #define HDMI_TX_STTS_BIT_CH23_source_num_ch3_SHIFT (12U) |
| #define HDMI_TX_STTS_BIT_CH23_source_num_ch3(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_source_num_ch3_SHIFT)) & HDMI_TX_STTS_BIT_CH23_source_num_ch3_MASK) |
| #define HDMI_TX_STTS_BIT_CH23_channel_num_ch3_MASK (0xF0000U) |
| #define HDMI_TX_STTS_BIT_CH23_channel_num_ch3_SHIFT (16U) |
| #define HDMI_TX_STTS_BIT_CH23_channel_num_ch3(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_channel_num_ch3_SHIFT)) & HDMI_TX_STTS_BIT_CH23_channel_num_ch3_MASK) |
| #define HDMI_TX_STTS_BIT_CH23_word_length_ch3_MASK (0xF00000U) |
| #define HDMI_TX_STTS_BIT_CH23_word_length_ch3_SHIFT (20U) |
| #define HDMI_TX_STTS_BIT_CH23_word_length_ch3(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_word_length_ch3_SHIFT)) & HDMI_TX_STTS_BIT_CH23_word_length_ch3_MASK) |
| #define HDMI_TX_STTS_BIT_CH23_valid_bits3_2_MASK (0x3000000U) |
| #define HDMI_TX_STTS_BIT_CH23_valid_bits3_2_SHIFT (24U) |
| #define HDMI_TX_STTS_BIT_CH23_valid_bits3_2(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_valid_bits3_2_SHIFT)) & HDMI_TX_STTS_BIT_CH23_valid_bits3_2_MASK) |
| #define HDMI_TX_STTS_BIT_CH23_reserved_0_MASK (0xFC000000U) |
| #define HDMI_TX_STTS_BIT_CH23_reserved_0_SHIFT (26U) |
| #define HDMI_TX_STTS_BIT_CH23_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH23_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH23_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name STTS_BIT_CH45 - */ |
| /*! @{ */ |
| #define HDMI_TX_STTS_BIT_CH45_source_num_ch4_MASK (0xFU) |
| #define HDMI_TX_STTS_BIT_CH45_source_num_ch4_SHIFT (0U) |
| #define HDMI_TX_STTS_BIT_CH45_source_num_ch4(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_source_num_ch4_SHIFT)) & HDMI_TX_STTS_BIT_CH45_source_num_ch4_MASK) |
| #define HDMI_TX_STTS_BIT_CH45_channel_num_ch4_MASK (0xF0U) |
| #define HDMI_TX_STTS_BIT_CH45_channel_num_ch4_SHIFT (4U) |
| #define HDMI_TX_STTS_BIT_CH45_channel_num_ch4(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_channel_num_ch4_SHIFT)) & HDMI_TX_STTS_BIT_CH45_channel_num_ch4_MASK) |
| #define HDMI_TX_STTS_BIT_CH45_word_length_ch4_MASK (0xF00U) |
| #define HDMI_TX_STTS_BIT_CH45_word_length_ch4_SHIFT (8U) |
| #define HDMI_TX_STTS_BIT_CH45_word_length_ch4(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_word_length_ch4_SHIFT)) & HDMI_TX_STTS_BIT_CH45_word_length_ch4_MASK) |
| #define HDMI_TX_STTS_BIT_CH45_source_num_ch5_MASK (0xF000U) |
| #define HDMI_TX_STTS_BIT_CH45_source_num_ch5_SHIFT (12U) |
| #define HDMI_TX_STTS_BIT_CH45_source_num_ch5(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_source_num_ch5_SHIFT)) & HDMI_TX_STTS_BIT_CH45_source_num_ch5_MASK) |
| #define HDMI_TX_STTS_BIT_CH45_channel_num_ch5_MASK (0xF0000U) |
| #define HDMI_TX_STTS_BIT_CH45_channel_num_ch5_SHIFT (16U) |
| #define HDMI_TX_STTS_BIT_CH45_channel_num_ch5(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_channel_num_ch5_SHIFT)) & HDMI_TX_STTS_BIT_CH45_channel_num_ch5_MASK) |
| #define HDMI_TX_STTS_BIT_CH45_word_length_ch5_MASK (0xF00000U) |
| #define HDMI_TX_STTS_BIT_CH45_word_length_ch5_SHIFT (20U) |
| #define HDMI_TX_STTS_BIT_CH45_word_length_ch5(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_word_length_ch5_SHIFT)) & HDMI_TX_STTS_BIT_CH45_word_length_ch5_MASK) |
| #define HDMI_TX_STTS_BIT_CH45_valid_bits5_4_MASK (0x3000000U) |
| #define HDMI_TX_STTS_BIT_CH45_valid_bits5_4_SHIFT (24U) |
| #define HDMI_TX_STTS_BIT_CH45_valid_bits5_4(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_valid_bits5_4_SHIFT)) & HDMI_TX_STTS_BIT_CH45_valid_bits5_4_MASK) |
| #define HDMI_TX_STTS_BIT_CH45_reserved_0_MASK (0xFC000000U) |
| #define HDMI_TX_STTS_BIT_CH45_reserved_0_SHIFT (26U) |
| #define HDMI_TX_STTS_BIT_CH45_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH45_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH45_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name STTS_BIT_CH67 - */ |
| /*! @{ */ |
| #define HDMI_TX_STTS_BIT_CH67_source_num_ch6_MASK (0xFU) |
| #define HDMI_TX_STTS_BIT_CH67_source_num_ch6_SHIFT (0U) |
| #define HDMI_TX_STTS_BIT_CH67_source_num_ch6(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_source_num_ch6_SHIFT)) & HDMI_TX_STTS_BIT_CH67_source_num_ch6_MASK) |
| #define HDMI_TX_STTS_BIT_CH67_channel_num_ch6_MASK (0xF0U) |
| #define HDMI_TX_STTS_BIT_CH67_channel_num_ch6_SHIFT (4U) |
| #define HDMI_TX_STTS_BIT_CH67_channel_num_ch6(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_channel_num_ch6_SHIFT)) & HDMI_TX_STTS_BIT_CH67_channel_num_ch6_MASK) |
| #define HDMI_TX_STTS_BIT_CH67_word_length_ch6_MASK (0xF00U) |
| #define HDMI_TX_STTS_BIT_CH67_word_length_ch6_SHIFT (8U) |
| #define HDMI_TX_STTS_BIT_CH67_word_length_ch6(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_word_length_ch6_SHIFT)) & HDMI_TX_STTS_BIT_CH67_word_length_ch6_MASK) |
| #define HDMI_TX_STTS_BIT_CH67_source_num_ch7_MASK (0xF000U) |
| #define HDMI_TX_STTS_BIT_CH67_source_num_ch7_SHIFT (12U) |
| #define HDMI_TX_STTS_BIT_CH67_source_num_ch7(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_source_num_ch7_SHIFT)) & HDMI_TX_STTS_BIT_CH67_source_num_ch7_MASK) |
| #define HDMI_TX_STTS_BIT_CH67_channel_num_ch7_MASK (0xF0000U) |
| #define HDMI_TX_STTS_BIT_CH67_channel_num_ch7_SHIFT (16U) |
| #define HDMI_TX_STTS_BIT_CH67_channel_num_ch7(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_channel_num_ch7_SHIFT)) & HDMI_TX_STTS_BIT_CH67_channel_num_ch7_MASK) |
| #define HDMI_TX_STTS_BIT_CH67_word_length_ch7_MASK (0xF00000U) |
| #define HDMI_TX_STTS_BIT_CH67_word_length_ch7_SHIFT (20U) |
| #define HDMI_TX_STTS_BIT_CH67_word_length_ch7(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_word_length_ch7_SHIFT)) & HDMI_TX_STTS_BIT_CH67_word_length_ch7_MASK) |
| #define HDMI_TX_STTS_BIT_CH67_valid_bits7_6_MASK (0x3000000U) |
| #define HDMI_TX_STTS_BIT_CH67_valid_bits7_6_SHIFT (24U) |
| #define HDMI_TX_STTS_BIT_CH67_valid_bits7_6(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_valid_bits7_6_SHIFT)) & HDMI_TX_STTS_BIT_CH67_valid_bits7_6_MASK) |
| #define HDMI_TX_STTS_BIT_CH67_reserved_0_MASK (0xFC000000U) |
| #define HDMI_TX_STTS_BIT_CH67_reserved_0_SHIFT (26U) |
| #define HDMI_TX_STTS_BIT_CH67_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH67_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH67_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name STTS_BIT_CH89 - */ |
| /*! @{ */ |
| #define HDMI_TX_STTS_BIT_CH89_source_num_ch8_MASK (0xFU) |
| #define HDMI_TX_STTS_BIT_CH89_source_num_ch8_SHIFT (0U) |
| #define HDMI_TX_STTS_BIT_CH89_source_num_ch8(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_source_num_ch8_SHIFT)) & HDMI_TX_STTS_BIT_CH89_source_num_ch8_MASK) |
| #define HDMI_TX_STTS_BIT_CH89_channel_num_ch8_MASK (0xF0U) |
| #define HDMI_TX_STTS_BIT_CH89_channel_num_ch8_SHIFT (4U) |
| #define HDMI_TX_STTS_BIT_CH89_channel_num_ch8(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_channel_num_ch8_SHIFT)) & HDMI_TX_STTS_BIT_CH89_channel_num_ch8_MASK) |
| #define HDMI_TX_STTS_BIT_CH89_word_length_ch8_MASK (0xF00U) |
| #define HDMI_TX_STTS_BIT_CH89_word_length_ch8_SHIFT (8U) |
| #define HDMI_TX_STTS_BIT_CH89_word_length_ch8(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_word_length_ch8_SHIFT)) & HDMI_TX_STTS_BIT_CH89_word_length_ch8_MASK) |
| #define HDMI_TX_STTS_BIT_CH89_source_num_ch9_MASK (0xF000U) |
| #define HDMI_TX_STTS_BIT_CH89_source_num_ch9_SHIFT (12U) |
| #define HDMI_TX_STTS_BIT_CH89_source_num_ch9(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_source_num_ch9_SHIFT)) & HDMI_TX_STTS_BIT_CH89_source_num_ch9_MASK) |
| #define HDMI_TX_STTS_BIT_CH89_channel_num_ch9_MASK (0xF0000U) |
| #define HDMI_TX_STTS_BIT_CH89_channel_num_ch9_SHIFT (16U) |
| #define HDMI_TX_STTS_BIT_CH89_channel_num_ch9(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_channel_num_ch9_SHIFT)) & HDMI_TX_STTS_BIT_CH89_channel_num_ch9_MASK) |
| #define HDMI_TX_STTS_BIT_CH89_word_length_ch9_MASK (0xF00000U) |
| #define HDMI_TX_STTS_BIT_CH89_word_length_ch9_SHIFT (20U) |
| #define HDMI_TX_STTS_BIT_CH89_word_length_ch9(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_word_length_ch9_SHIFT)) & HDMI_TX_STTS_BIT_CH89_word_length_ch9_MASK) |
| #define HDMI_TX_STTS_BIT_CH89_valid_bits9_8_MASK (0x3000000U) |
| #define HDMI_TX_STTS_BIT_CH89_valid_bits9_8_SHIFT (24U) |
| #define HDMI_TX_STTS_BIT_CH89_valid_bits9_8(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_valid_bits9_8_SHIFT)) & HDMI_TX_STTS_BIT_CH89_valid_bits9_8_MASK) |
| #define HDMI_TX_STTS_BIT_CH89_reserved_0_MASK (0xFC000000U) |
| #define HDMI_TX_STTS_BIT_CH89_reserved_0_SHIFT (26U) |
| #define HDMI_TX_STTS_BIT_CH89_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH89_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH89_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name STTS_BIT_CH1011 - */ |
| /*! @{ */ |
| #define HDMI_TX_STTS_BIT_CH1011_source_num_ch10_MASK (0xFU) |
| #define HDMI_TX_STTS_BIT_CH1011_source_num_ch10_SHIFT (0U) |
| #define HDMI_TX_STTS_BIT_CH1011_source_num_ch10(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_source_num_ch10_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_source_num_ch10_MASK) |
| #define HDMI_TX_STTS_BIT_CH1011_channel_num_ch10_MASK (0xF0U) |
| #define HDMI_TX_STTS_BIT_CH1011_channel_num_ch10_SHIFT (4U) |
| #define HDMI_TX_STTS_BIT_CH1011_channel_num_ch10(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_channel_num_ch10_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_channel_num_ch10_MASK) |
| #define HDMI_TX_STTS_BIT_CH1011_word_length_ch10_MASK (0xF00U) |
| #define HDMI_TX_STTS_BIT_CH1011_word_length_ch10_SHIFT (8U) |
| #define HDMI_TX_STTS_BIT_CH1011_word_length_ch10(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_word_length_ch10_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_word_length_ch10_MASK) |
| #define HDMI_TX_STTS_BIT_CH1011_source_num_ch11_MASK (0xF000U) |
| #define HDMI_TX_STTS_BIT_CH1011_source_num_ch11_SHIFT (12U) |
| #define HDMI_TX_STTS_BIT_CH1011_source_num_ch11(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_source_num_ch11_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_source_num_ch11_MASK) |
| #define HDMI_TX_STTS_BIT_CH1011_channel_num_ch11_MASK (0xF0000U) |
| #define HDMI_TX_STTS_BIT_CH1011_channel_num_ch11_SHIFT (16U) |
| #define HDMI_TX_STTS_BIT_CH1011_channel_num_ch11(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_channel_num_ch11_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_channel_num_ch11_MASK) |
| #define HDMI_TX_STTS_BIT_CH1011_word_length_ch11_MASK (0xF00000U) |
| #define HDMI_TX_STTS_BIT_CH1011_word_length_ch11_SHIFT (20U) |
| #define HDMI_TX_STTS_BIT_CH1011_word_length_ch11(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_word_length_ch11_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_word_length_ch11_MASK) |
| #define HDMI_TX_STTS_BIT_CH1011_valid_bits11_10_MASK (0x3000000U) |
| #define HDMI_TX_STTS_BIT_CH1011_valid_bits11_10_SHIFT (24U) |
| #define HDMI_TX_STTS_BIT_CH1011_valid_bits11_10(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_valid_bits11_10_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_valid_bits11_10_MASK) |
| #define HDMI_TX_STTS_BIT_CH1011_reserved_0_MASK (0xFC000000U) |
| #define HDMI_TX_STTS_BIT_CH1011_reserved_0_SHIFT (26U) |
| #define HDMI_TX_STTS_BIT_CH1011_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1011_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH1011_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name STTS_BIT_CH1213 - */ |
| /*! @{ */ |
| #define HDMI_TX_STTS_BIT_CH1213_source_num_ch12_MASK (0xFU) |
| #define HDMI_TX_STTS_BIT_CH1213_source_num_ch12_SHIFT (0U) |
| #define HDMI_TX_STTS_BIT_CH1213_source_num_ch12(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_source_num_ch12_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_source_num_ch12_MASK) |
| #define HDMI_TX_STTS_BIT_CH1213_channel_num_ch12_MASK (0xF0U) |
| #define HDMI_TX_STTS_BIT_CH1213_channel_num_ch12_SHIFT (4U) |
| #define HDMI_TX_STTS_BIT_CH1213_channel_num_ch12(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_channel_num_ch12_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_channel_num_ch12_MASK) |
| #define HDMI_TX_STTS_BIT_CH1213_word_length_ch12_MASK (0xF00U) |
| #define HDMI_TX_STTS_BIT_CH1213_word_length_ch12_SHIFT (8U) |
| #define HDMI_TX_STTS_BIT_CH1213_word_length_ch12(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_word_length_ch12_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_word_length_ch12_MASK) |
| #define HDMI_TX_STTS_BIT_CH1213_source_num_ch13_MASK (0xF000U) |
| #define HDMI_TX_STTS_BIT_CH1213_source_num_ch13_SHIFT (12U) |
| #define HDMI_TX_STTS_BIT_CH1213_source_num_ch13(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_source_num_ch13_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_source_num_ch13_MASK) |
| #define HDMI_TX_STTS_BIT_CH1213_channel_num_ch13_MASK (0xF0000U) |
| #define HDMI_TX_STTS_BIT_CH1213_channel_num_ch13_SHIFT (16U) |
| #define HDMI_TX_STTS_BIT_CH1213_channel_num_ch13(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_channel_num_ch13_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_channel_num_ch13_MASK) |
| #define HDMI_TX_STTS_BIT_CH1213_word_length_ch13_MASK (0xF00000U) |
| #define HDMI_TX_STTS_BIT_CH1213_word_length_ch13_SHIFT (20U) |
| #define HDMI_TX_STTS_BIT_CH1213_word_length_ch13(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_word_length_ch13_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_word_length_ch13_MASK) |
| #define HDMI_TX_STTS_BIT_CH1213_valid_bits13_12_MASK (0x3000000U) |
| #define HDMI_TX_STTS_BIT_CH1213_valid_bits13_12_SHIFT (24U) |
| #define HDMI_TX_STTS_BIT_CH1213_valid_bits13_12(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_valid_bits13_12_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_valid_bits13_12_MASK) |
| #define HDMI_TX_STTS_BIT_CH1213_reserved_0_MASK (0xFC000000U) |
| #define HDMI_TX_STTS_BIT_CH1213_reserved_0_SHIFT (26U) |
| #define HDMI_TX_STTS_BIT_CH1213_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1213_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH1213_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name STTS_BIT_CH1415 - */ |
| /*! @{ */ |
| #define HDMI_TX_STTS_BIT_CH1415_source_num_ch14_MASK (0xFU) |
| #define HDMI_TX_STTS_BIT_CH1415_source_num_ch14_SHIFT (0U) |
| #define HDMI_TX_STTS_BIT_CH1415_source_num_ch14(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_source_num_ch14_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_source_num_ch14_MASK) |
| #define HDMI_TX_STTS_BIT_CH1415_channel_num_ch14_MASK (0xF0U) |
| #define HDMI_TX_STTS_BIT_CH1415_channel_num_ch14_SHIFT (4U) |
| #define HDMI_TX_STTS_BIT_CH1415_channel_num_ch14(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_channel_num_ch14_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_channel_num_ch14_MASK) |
| #define HDMI_TX_STTS_BIT_CH1415_word_length_ch14_MASK (0xF00U) |
| #define HDMI_TX_STTS_BIT_CH1415_word_length_ch14_SHIFT (8U) |
| #define HDMI_TX_STTS_BIT_CH1415_word_length_ch14(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_word_length_ch14_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_word_length_ch14_MASK) |
| #define HDMI_TX_STTS_BIT_CH1415_source_num_ch15_MASK (0xF000U) |
| #define HDMI_TX_STTS_BIT_CH1415_source_num_ch15_SHIFT (12U) |
| #define HDMI_TX_STTS_BIT_CH1415_source_num_ch15(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_source_num_ch15_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_source_num_ch15_MASK) |
| #define HDMI_TX_STTS_BIT_CH1415_channel_num_ch15_MASK (0xF0000U) |
| #define HDMI_TX_STTS_BIT_CH1415_channel_num_ch15_SHIFT (16U) |
| #define HDMI_TX_STTS_BIT_CH1415_channel_num_ch15(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_channel_num_ch15_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_channel_num_ch15_MASK) |
| #define HDMI_TX_STTS_BIT_CH1415_word_length_ch15_MASK (0xF00000U) |
| #define HDMI_TX_STTS_BIT_CH1415_word_length_ch15_SHIFT (20U) |
| #define HDMI_TX_STTS_BIT_CH1415_word_length_ch15(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_word_length_ch15_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_word_length_ch15_MASK) |
| #define HDMI_TX_STTS_BIT_CH1415_valid_bits15_14_MASK (0x3000000U) |
| #define HDMI_TX_STTS_BIT_CH1415_valid_bits15_14_SHIFT (24U) |
| #define HDMI_TX_STTS_BIT_CH1415_valid_bits15_14(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_valid_bits15_14_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_valid_bits15_14_MASK) |
| #define HDMI_TX_STTS_BIT_CH1415_reserved_0_MASK (0xFC000000U) |
| #define HDMI_TX_STTS_BIT_CH1415_reserved_0_SHIFT (26U) |
| #define HDMI_TX_STTS_BIT_CH1415_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1415_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH1415_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name STTS_BIT_CH1617 - */ |
| /*! @{ */ |
| #define HDMI_TX_STTS_BIT_CH1617_source_num_ch16_MASK (0xFU) |
| #define HDMI_TX_STTS_BIT_CH1617_source_num_ch16_SHIFT (0U) |
| #define HDMI_TX_STTS_BIT_CH1617_source_num_ch16(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_source_num_ch16_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_source_num_ch16_MASK) |
| #define HDMI_TX_STTS_BIT_CH1617_channel_num_ch16_MASK (0xF0U) |
| #define HDMI_TX_STTS_BIT_CH1617_channel_num_ch16_SHIFT (4U) |
| #define HDMI_TX_STTS_BIT_CH1617_channel_num_ch16(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_channel_num_ch16_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_channel_num_ch16_MASK) |
| #define HDMI_TX_STTS_BIT_CH1617_word_length_ch16_MASK (0xF00U) |
| #define HDMI_TX_STTS_BIT_CH1617_word_length_ch16_SHIFT (8U) |
| #define HDMI_TX_STTS_BIT_CH1617_word_length_ch16(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_word_length_ch16_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_word_length_ch16_MASK) |
| #define HDMI_TX_STTS_BIT_CH1617_source_num_ch17_MASK (0xF000U) |
| #define HDMI_TX_STTS_BIT_CH1617_source_num_ch17_SHIFT (12U) |
| #define HDMI_TX_STTS_BIT_CH1617_source_num_ch17(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_source_num_ch17_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_source_num_ch17_MASK) |
| #define HDMI_TX_STTS_BIT_CH1617_channel_num_ch17_MASK (0xF0000U) |
| #define HDMI_TX_STTS_BIT_CH1617_channel_num_ch17_SHIFT (16U) |
| #define HDMI_TX_STTS_BIT_CH1617_channel_num_ch17(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_channel_num_ch17_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_channel_num_ch17_MASK) |
| #define HDMI_TX_STTS_BIT_CH1617_word_length_ch17_MASK (0xF00000U) |
| #define HDMI_TX_STTS_BIT_CH1617_word_length_ch17_SHIFT (20U) |
| #define HDMI_TX_STTS_BIT_CH1617_word_length_ch17(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_word_length_ch17_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_word_length_ch17_MASK) |
| #define HDMI_TX_STTS_BIT_CH1617_valid_bits17_16_MASK (0x3000000U) |
| #define HDMI_TX_STTS_BIT_CH1617_valid_bits17_16_SHIFT (24U) |
| #define HDMI_TX_STTS_BIT_CH1617_valid_bits17_16(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_valid_bits17_16_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_valid_bits17_16_MASK) |
| #define HDMI_TX_STTS_BIT_CH1617_reserved_0_MASK (0xFC000000U) |
| #define HDMI_TX_STTS_BIT_CH1617_reserved_0_SHIFT (26U) |
| #define HDMI_TX_STTS_BIT_CH1617_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1617_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH1617_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name STTS_BIT_CH1819 - */ |
| /*! @{ */ |
| #define HDMI_TX_STTS_BIT_CH1819_source_num_ch18_MASK (0xFU) |
| #define HDMI_TX_STTS_BIT_CH1819_source_num_ch18_SHIFT (0U) |
| #define HDMI_TX_STTS_BIT_CH1819_source_num_ch18(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_source_num_ch18_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_source_num_ch18_MASK) |
| #define HDMI_TX_STTS_BIT_CH1819_channel_num_ch18_MASK (0xF0U) |
| #define HDMI_TX_STTS_BIT_CH1819_channel_num_ch18_SHIFT (4U) |
| #define HDMI_TX_STTS_BIT_CH1819_channel_num_ch18(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_channel_num_ch18_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_channel_num_ch18_MASK) |
| #define HDMI_TX_STTS_BIT_CH1819_word_length_ch18_MASK (0xF00U) |
| #define HDMI_TX_STTS_BIT_CH1819_word_length_ch18_SHIFT (8U) |
| #define HDMI_TX_STTS_BIT_CH1819_word_length_ch18(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_word_length_ch18_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_word_length_ch18_MASK) |
| #define HDMI_TX_STTS_BIT_CH1819_source_num_ch19_MASK (0xF000U) |
| #define HDMI_TX_STTS_BIT_CH1819_source_num_ch19_SHIFT (12U) |
| #define HDMI_TX_STTS_BIT_CH1819_source_num_ch19(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_source_num_ch19_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_source_num_ch19_MASK) |
| #define HDMI_TX_STTS_BIT_CH1819_channel_num_ch19_MASK (0xF0000U) |
| #define HDMI_TX_STTS_BIT_CH1819_channel_num_ch19_SHIFT (16U) |
| #define HDMI_TX_STTS_BIT_CH1819_channel_num_ch19(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_channel_num_ch19_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_channel_num_ch19_MASK) |
| #define HDMI_TX_STTS_BIT_CH1819_word_length_ch19_MASK (0xF00000U) |
| #define HDMI_TX_STTS_BIT_CH1819_word_length_ch19_SHIFT (20U) |
| #define HDMI_TX_STTS_BIT_CH1819_word_length_ch19(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_word_length_ch19_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_word_length_ch19_MASK) |
| #define HDMI_TX_STTS_BIT_CH1819_valid_bits19_18_MASK (0x3000000U) |
| #define HDMI_TX_STTS_BIT_CH1819_valid_bits19_18_SHIFT (24U) |
| #define HDMI_TX_STTS_BIT_CH1819_valid_bits19_18(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_valid_bits19_18_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_valid_bits19_18_MASK) |
| #define HDMI_TX_STTS_BIT_CH1819_reserved_0_MASK (0xFC000000U) |
| #define HDMI_TX_STTS_BIT_CH1819_reserved_0_SHIFT (26U) |
| #define HDMI_TX_STTS_BIT_CH1819_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH1819_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH1819_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name STTS_BIT_CH2021 - */ |
| /*! @{ */ |
| #define HDMI_TX_STTS_BIT_CH2021_source_num_ch20_MASK (0xFU) |
| #define HDMI_TX_STTS_BIT_CH2021_source_num_ch20_SHIFT (0U) |
| #define HDMI_TX_STTS_BIT_CH2021_source_num_ch20(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_source_num_ch20_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_source_num_ch20_MASK) |
| #define HDMI_TX_STTS_BIT_CH2021_channel_num_ch20_MASK (0xF0U) |
| #define HDMI_TX_STTS_BIT_CH2021_channel_num_ch20_SHIFT (4U) |
| #define HDMI_TX_STTS_BIT_CH2021_channel_num_ch20(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_channel_num_ch20_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_channel_num_ch20_MASK) |
| #define HDMI_TX_STTS_BIT_CH2021_word_length_ch20_MASK (0xF00U) |
| #define HDMI_TX_STTS_BIT_CH2021_word_length_ch20_SHIFT (8U) |
| #define HDMI_TX_STTS_BIT_CH2021_word_length_ch20(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_word_length_ch20_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_word_length_ch20_MASK) |
| #define HDMI_TX_STTS_BIT_CH2021_source_num_ch21_MASK (0xF000U) |
| #define HDMI_TX_STTS_BIT_CH2021_source_num_ch21_SHIFT (12U) |
| #define HDMI_TX_STTS_BIT_CH2021_source_num_ch21(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_source_num_ch21_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_source_num_ch21_MASK) |
| #define HDMI_TX_STTS_BIT_CH2021_channel_num_ch21_MASK (0xF0000U) |
| #define HDMI_TX_STTS_BIT_CH2021_channel_num_ch21_SHIFT (16U) |
| #define HDMI_TX_STTS_BIT_CH2021_channel_num_ch21(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_channel_num_ch21_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_channel_num_ch21_MASK) |
| #define HDMI_TX_STTS_BIT_CH2021_word_length_ch21_MASK (0xF00000U) |
| #define HDMI_TX_STTS_BIT_CH2021_word_length_ch21_SHIFT (20U) |
| #define HDMI_TX_STTS_BIT_CH2021_word_length_ch21(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_word_length_ch21_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_word_length_ch21_MASK) |
| #define HDMI_TX_STTS_BIT_CH2021_valid_bits21_20_MASK (0x3000000U) |
| #define HDMI_TX_STTS_BIT_CH2021_valid_bits21_20_SHIFT (24U) |
| #define HDMI_TX_STTS_BIT_CH2021_valid_bits21_20(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_valid_bits21_20_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_valid_bits21_20_MASK) |
| #define HDMI_TX_STTS_BIT_CH2021_reserved_0_MASK (0xFC000000U) |
| #define HDMI_TX_STTS_BIT_CH2021_reserved_0_SHIFT (26U) |
| #define HDMI_TX_STTS_BIT_CH2021_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2021_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH2021_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name STTS_BIT_CH2223 - */ |
| /*! @{ */ |
| #define HDMI_TX_STTS_BIT_CH2223_source_num_ch22_MASK (0xFU) |
| #define HDMI_TX_STTS_BIT_CH2223_source_num_ch22_SHIFT (0U) |
| #define HDMI_TX_STTS_BIT_CH2223_source_num_ch22(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_source_num_ch22_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_source_num_ch22_MASK) |
| #define HDMI_TX_STTS_BIT_CH2223_channel_num_ch22_MASK (0xF0U) |
| #define HDMI_TX_STTS_BIT_CH2223_channel_num_ch22_SHIFT (4U) |
| #define HDMI_TX_STTS_BIT_CH2223_channel_num_ch22(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_channel_num_ch22_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_channel_num_ch22_MASK) |
| #define HDMI_TX_STTS_BIT_CH2223_word_length_ch22_MASK (0xF00U) |
| #define HDMI_TX_STTS_BIT_CH2223_word_length_ch22_SHIFT (8U) |
| #define HDMI_TX_STTS_BIT_CH2223_word_length_ch22(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_word_length_ch22_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_word_length_ch22_MASK) |
| #define HDMI_TX_STTS_BIT_CH2223_source_num_ch23_MASK (0xF000U) |
| #define HDMI_TX_STTS_BIT_CH2223_source_num_ch23_SHIFT (12U) |
| #define HDMI_TX_STTS_BIT_CH2223_source_num_ch23(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_source_num_ch23_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_source_num_ch23_MASK) |
| #define HDMI_TX_STTS_BIT_CH2223_channel_num_ch23_MASK (0xF0000U) |
| #define HDMI_TX_STTS_BIT_CH2223_channel_num_ch23_SHIFT (16U) |
| #define HDMI_TX_STTS_BIT_CH2223_channel_num_ch23(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_channel_num_ch23_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_channel_num_ch23_MASK) |
| #define HDMI_TX_STTS_BIT_CH2223_word_length_ch23_MASK (0xF00000U) |
| #define HDMI_TX_STTS_BIT_CH2223_word_length_ch23_SHIFT (20U) |
| #define HDMI_TX_STTS_BIT_CH2223_word_length_ch23(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_word_length_ch23_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_word_length_ch23_MASK) |
| #define HDMI_TX_STTS_BIT_CH2223_valid_bits23_22_MASK (0x3000000U) |
| #define HDMI_TX_STTS_BIT_CH2223_valid_bits23_22_SHIFT (24U) |
| #define HDMI_TX_STTS_BIT_CH2223_valid_bits23_22(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_valid_bits23_22_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_valid_bits23_22_MASK) |
| #define HDMI_TX_STTS_BIT_CH2223_reserved_0_MASK (0xFC000000U) |
| #define HDMI_TX_STTS_BIT_CH2223_reserved_0_SHIFT (26U) |
| #define HDMI_TX_STTS_BIT_CH2223_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2223_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH2223_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name STTS_BIT_CH2425 - */ |
| /*! @{ */ |
| #define HDMI_TX_STTS_BIT_CH2425_source_num_ch24_MASK (0xFU) |
| #define HDMI_TX_STTS_BIT_CH2425_source_num_ch24_SHIFT (0U) |
| #define HDMI_TX_STTS_BIT_CH2425_source_num_ch24(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_source_num_ch24_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_source_num_ch24_MASK) |
| #define HDMI_TX_STTS_BIT_CH2425_channel_num_ch24_MASK (0xF0U) |
| #define HDMI_TX_STTS_BIT_CH2425_channel_num_ch24_SHIFT (4U) |
| #define HDMI_TX_STTS_BIT_CH2425_channel_num_ch24(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_channel_num_ch24_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_channel_num_ch24_MASK) |
| #define HDMI_TX_STTS_BIT_CH2425_word_length_ch24_MASK (0xF00U) |
| #define HDMI_TX_STTS_BIT_CH2425_word_length_ch24_SHIFT (8U) |
| #define HDMI_TX_STTS_BIT_CH2425_word_length_ch24(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_word_length_ch24_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_word_length_ch24_MASK) |
| #define HDMI_TX_STTS_BIT_CH2425_source_num_ch25_MASK (0xF000U) |
| #define HDMI_TX_STTS_BIT_CH2425_source_num_ch25_SHIFT (12U) |
| #define HDMI_TX_STTS_BIT_CH2425_source_num_ch25(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_source_num_ch25_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_source_num_ch25_MASK) |
| #define HDMI_TX_STTS_BIT_CH2425_channel_num_ch25_MASK (0xF0000U) |
| #define HDMI_TX_STTS_BIT_CH2425_channel_num_ch25_SHIFT (16U) |
| #define HDMI_TX_STTS_BIT_CH2425_channel_num_ch25(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_channel_num_ch25_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_channel_num_ch25_MASK) |
| #define HDMI_TX_STTS_BIT_CH2425_word_length_ch25_MASK (0xF00000U) |
| #define HDMI_TX_STTS_BIT_CH2425_word_length_ch25_SHIFT (20U) |
| #define HDMI_TX_STTS_BIT_CH2425_word_length_ch25(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_word_length_ch25_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_word_length_ch25_MASK) |
| #define HDMI_TX_STTS_BIT_CH2425_valid_bits25_24_MASK (0x3000000U) |
| #define HDMI_TX_STTS_BIT_CH2425_valid_bits25_24_SHIFT (24U) |
| #define HDMI_TX_STTS_BIT_CH2425_valid_bits25_24(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_valid_bits25_24_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_valid_bits25_24_MASK) |
| #define HDMI_TX_STTS_BIT_CH2425_reserved_0_MASK (0xFC000000U) |
| #define HDMI_TX_STTS_BIT_CH2425_reserved_0_SHIFT (26U) |
| #define HDMI_TX_STTS_BIT_CH2425_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2425_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH2425_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name STTS_BIT_CH2627 - */ |
| /*! @{ */ |
| #define HDMI_TX_STTS_BIT_CH2627_source_num_ch26_MASK (0xFU) |
| #define HDMI_TX_STTS_BIT_CH2627_source_num_ch26_SHIFT (0U) |
| #define HDMI_TX_STTS_BIT_CH2627_source_num_ch26(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_source_num_ch26_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_source_num_ch26_MASK) |
| #define HDMI_TX_STTS_BIT_CH2627_channel_num_ch26_MASK (0xF0U) |
| #define HDMI_TX_STTS_BIT_CH2627_channel_num_ch26_SHIFT (4U) |
| #define HDMI_TX_STTS_BIT_CH2627_channel_num_ch26(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_channel_num_ch26_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_channel_num_ch26_MASK) |
| #define HDMI_TX_STTS_BIT_CH2627_word_length_ch26_MASK (0xF00U) |
| #define HDMI_TX_STTS_BIT_CH2627_word_length_ch26_SHIFT (8U) |
| #define HDMI_TX_STTS_BIT_CH2627_word_length_ch26(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_word_length_ch26_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_word_length_ch26_MASK) |
| #define HDMI_TX_STTS_BIT_CH2627_source_num_ch27_MASK (0xF000U) |
| #define HDMI_TX_STTS_BIT_CH2627_source_num_ch27_SHIFT (12U) |
| #define HDMI_TX_STTS_BIT_CH2627_source_num_ch27(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_source_num_ch27_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_source_num_ch27_MASK) |
| #define HDMI_TX_STTS_BIT_CH2627_channel_num_ch27_MASK (0xF0000U) |
| #define HDMI_TX_STTS_BIT_CH2627_channel_num_ch27_SHIFT (16U) |
| #define HDMI_TX_STTS_BIT_CH2627_channel_num_ch27(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_channel_num_ch27_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_channel_num_ch27_MASK) |
| #define HDMI_TX_STTS_BIT_CH2627_word_length_ch27_MASK (0xF00000U) |
| #define HDMI_TX_STTS_BIT_CH2627_word_length_ch27_SHIFT (20U) |
| #define HDMI_TX_STTS_BIT_CH2627_word_length_ch27(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_word_length_ch27_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_word_length_ch27_MASK) |
| #define HDMI_TX_STTS_BIT_CH2627_valid_bits27_26_MASK (0x3000000U) |
| #define HDMI_TX_STTS_BIT_CH2627_valid_bits27_26_SHIFT (24U) |
| #define HDMI_TX_STTS_BIT_CH2627_valid_bits27_26(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_valid_bits27_26_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_valid_bits27_26_MASK) |
| #define HDMI_TX_STTS_BIT_CH2627_reserved_0_MASK (0xFC000000U) |
| #define HDMI_TX_STTS_BIT_CH2627_reserved_0_SHIFT (26U) |
| #define HDMI_TX_STTS_BIT_CH2627_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2627_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH2627_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name STTS_BIT_CH2829 - */ |
| /*! @{ */ |
| #define HDMI_TX_STTS_BIT_CH2829_source_num_ch28_MASK (0xFU) |
| #define HDMI_TX_STTS_BIT_CH2829_source_num_ch28_SHIFT (0U) |
| #define HDMI_TX_STTS_BIT_CH2829_source_num_ch28(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_source_num_ch28_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_source_num_ch28_MASK) |
| #define HDMI_TX_STTS_BIT_CH2829_channel_num_ch28_MASK (0xF0U) |
| #define HDMI_TX_STTS_BIT_CH2829_channel_num_ch28_SHIFT (4U) |
| #define HDMI_TX_STTS_BIT_CH2829_channel_num_ch28(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_channel_num_ch28_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_channel_num_ch28_MASK) |
| #define HDMI_TX_STTS_BIT_CH2829_word_length_ch28_MASK (0xF00U) |
| #define HDMI_TX_STTS_BIT_CH2829_word_length_ch28_SHIFT (8U) |
| #define HDMI_TX_STTS_BIT_CH2829_word_length_ch28(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_word_length_ch28_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_word_length_ch28_MASK) |
| #define HDMI_TX_STTS_BIT_CH2829_source_num_ch29_MASK (0xF000U) |
| #define HDMI_TX_STTS_BIT_CH2829_source_num_ch29_SHIFT (12U) |
| #define HDMI_TX_STTS_BIT_CH2829_source_num_ch29(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_source_num_ch29_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_source_num_ch29_MASK) |
| #define HDMI_TX_STTS_BIT_CH2829_channel_num_ch29_MASK (0xF0000U) |
| #define HDMI_TX_STTS_BIT_CH2829_channel_num_ch29_SHIFT (16U) |
| #define HDMI_TX_STTS_BIT_CH2829_channel_num_ch29(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_channel_num_ch29_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_channel_num_ch29_MASK) |
| #define HDMI_TX_STTS_BIT_CH2829_word_length_ch29_MASK (0xF00000U) |
| #define HDMI_TX_STTS_BIT_CH2829_word_length_ch29_SHIFT (20U) |
| #define HDMI_TX_STTS_BIT_CH2829_word_length_ch29(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_word_length_ch29_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_word_length_ch29_MASK) |
| #define HDMI_TX_STTS_BIT_CH2829_valid_bits29_28_MASK (0x3000000U) |
| #define HDMI_TX_STTS_BIT_CH2829_valid_bits29_28_SHIFT (24U) |
| #define HDMI_TX_STTS_BIT_CH2829_valid_bits29_28(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_valid_bits29_28_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_valid_bits29_28_MASK) |
| #define HDMI_TX_STTS_BIT_CH2829_reserved_0_MASK (0xFC000000U) |
| #define HDMI_TX_STTS_BIT_CH2829_reserved_0_SHIFT (26U) |
| #define HDMI_TX_STTS_BIT_CH2829_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH2829_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH2829_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name STTS_BIT_CH3031 - */ |
| /*! @{ */ |
| #define HDMI_TX_STTS_BIT_CH3031_source_num_ch30_MASK (0xFU) |
| #define HDMI_TX_STTS_BIT_CH3031_source_num_ch30_SHIFT (0U) |
| #define HDMI_TX_STTS_BIT_CH3031_source_num_ch30(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_source_num_ch30_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_source_num_ch30_MASK) |
| #define HDMI_TX_STTS_BIT_CH3031_channel_num_ch30_MASK (0xF0U) |
| #define HDMI_TX_STTS_BIT_CH3031_channel_num_ch30_SHIFT (4U) |
| #define HDMI_TX_STTS_BIT_CH3031_channel_num_ch30(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_channel_num_ch30_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_channel_num_ch30_MASK) |
| #define HDMI_TX_STTS_BIT_CH3031_word_length_ch30_MASK (0xF00U) |
| #define HDMI_TX_STTS_BIT_CH3031_word_length_ch30_SHIFT (8U) |
| #define HDMI_TX_STTS_BIT_CH3031_word_length_ch30(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_word_length_ch30_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_word_length_ch30_MASK) |
| #define HDMI_TX_STTS_BIT_CH3031_source_num_ch31_MASK (0xF000U) |
| #define HDMI_TX_STTS_BIT_CH3031_source_num_ch31_SHIFT (12U) |
| #define HDMI_TX_STTS_BIT_CH3031_source_num_ch31(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_source_num_ch31_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_source_num_ch31_MASK) |
| #define HDMI_TX_STTS_BIT_CH3031_channel_num_ch31_MASK (0xF0000U) |
| #define HDMI_TX_STTS_BIT_CH3031_channel_num_ch31_SHIFT (16U) |
| #define HDMI_TX_STTS_BIT_CH3031_channel_num_ch31(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_channel_num_ch31_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_channel_num_ch31_MASK) |
| #define HDMI_TX_STTS_BIT_CH3031_word_length_ch31_MASK (0xF00000U) |
| #define HDMI_TX_STTS_BIT_CH3031_word_length_ch31_SHIFT (20U) |
| #define HDMI_TX_STTS_BIT_CH3031_word_length_ch31(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_word_length_ch31_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_word_length_ch31_MASK) |
| #define HDMI_TX_STTS_BIT_CH3031_valid_bits31_30_MASK (0x3000000U) |
| #define HDMI_TX_STTS_BIT_CH3031_valid_bits31_30_SHIFT (24U) |
| #define HDMI_TX_STTS_BIT_CH3031_valid_bits31_30(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_valid_bits31_30_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_valid_bits31_30_MASK) |
| #define HDMI_TX_STTS_BIT_CH3031_reserved_0_MASK (0xFC000000U) |
| #define HDMI_TX_STTS_BIT_CH3031_reserved_0_SHIFT (26U) |
| #define HDMI_TX_STTS_BIT_CH3031_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_STTS_BIT_CH3031_reserved_0_SHIFT)) & HDMI_TX_STTS_BIT_CH3031_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SPDIF_CTRL_ADDR - */ |
| /*! @{ */ |
| #define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_avg_win_MASK (0x7U) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_avg_win_SHIFT (0U) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_avg_win(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_avg_win_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_avg_win_MASK) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_thrsh_MASK (0x7F8U) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_thrsh_SHIFT (3U) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_thrsh(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_thrsh_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_thrsh_MASK) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_spdif_fifo_mid_range_MASK (0x7F800U) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_spdif_fifo_mid_range_SHIFT (11U) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_spdif_fifo_mid_range(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_spdif_fifo_mid_range_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_spdif_fifo_mid_range_MASK) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_bypass_MASK (0x80000U) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_bypass_SHIFT (19U) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_bypass(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_bypass_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_bypass_MASK) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_spdif_avg_sel_MASK (0x100000U) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_spdif_avg_sel_SHIFT (20U) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_spdif_avg_sel(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_spdif_avg_sel_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_spdif_avg_sel_MASK) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_spdif_enable_MASK (0x200000U) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_spdif_enable_SHIFT (21U) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_spdif_enable(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_spdif_enable_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_spdif_enable_MASK) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_status_MASK (0x3C00000U) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_status_SHIFT (22U) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_status(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_status_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_spdif_jitter_status_MASK) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_reserved_0_MASK (0xFC000000U) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_reserved_0_SHIFT (26U) |
| #define HDMI_TX_SPDIF_CTRL_ADDR_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CTRL_ADDR_reserved_0_SHIFT)) & HDMI_TX_SPDIF_CTRL_ADDR_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SPDIF_CH1_CS_3100_ADDR - */ |
| /*! @{ */ |
| #define HDMI_TX_SPDIF_CH1_CS_3100_ADDR_spdif_ch1_st_stts_bits3100_MASK (0xFFFFFFFFU) |
| #define HDMI_TX_SPDIF_CH1_CS_3100_ADDR_spdif_ch1_st_stts_bits3100_SHIFT (0U) |
| #define HDMI_TX_SPDIF_CH1_CS_3100_ADDR_spdif_ch1_st_stts_bits3100(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH1_CS_3100_ADDR_spdif_ch1_st_stts_bits3100_SHIFT)) & HDMI_TX_SPDIF_CH1_CS_3100_ADDR_spdif_ch1_st_stts_bits3100_MASK) |
| /*! @} */ |
| |
| /*! @name SPDIF_CH1_CS_6332_ADDR - */ |
| /*! @{ */ |
| #define HDMI_TX_SPDIF_CH1_CS_6332_ADDR_spdif_ch1_st_stts_bits6332_MASK (0xFFFFFFFFU) |
| #define HDMI_TX_SPDIF_CH1_CS_6332_ADDR_spdif_ch1_st_stts_bits6332_SHIFT (0U) |
| #define HDMI_TX_SPDIF_CH1_CS_6332_ADDR_spdif_ch1_st_stts_bits6332(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH1_CS_6332_ADDR_spdif_ch1_st_stts_bits6332_SHIFT)) & HDMI_TX_SPDIF_CH1_CS_6332_ADDR_spdif_ch1_st_stts_bits6332_MASK) |
| /*! @} */ |
| |
| /*! @name SPDIF_CH1_CS_9564_ADDR - */ |
| /*! @{ */ |
| #define HDMI_TX_SPDIF_CH1_CS_9564_ADDR_spdif_ch1_st_stts_bits9564_MASK (0xFFFFFFFFU) |
| #define HDMI_TX_SPDIF_CH1_CS_9564_ADDR_spdif_ch1_st_stts_bits9564_SHIFT (0U) |
| #define HDMI_TX_SPDIF_CH1_CS_9564_ADDR_spdif_ch1_st_stts_bits9564(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH1_CS_9564_ADDR_spdif_ch1_st_stts_bits9564_SHIFT)) & HDMI_TX_SPDIF_CH1_CS_9564_ADDR_spdif_ch1_st_stts_bits9564_MASK) |
| /*! @} */ |
| |
| /*! @name SPDIF_CH1_CS_12796_ADDR - */ |
| /*! @{ */ |
| #define HDMI_TX_SPDIF_CH1_CS_12796_ADDR_spdif_ch1_st_stts_bits12796_MASK (0xFFFFFFFFU) |
| #define HDMI_TX_SPDIF_CH1_CS_12796_ADDR_spdif_ch1_st_stts_bits12796_SHIFT (0U) |
| #define HDMI_TX_SPDIF_CH1_CS_12796_ADDR_spdif_ch1_st_stts_bits12796(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH1_CS_12796_ADDR_spdif_ch1_st_stts_bits12796_SHIFT)) & HDMI_TX_SPDIF_CH1_CS_12796_ADDR_spdif_ch1_st_stts_bits12796_MASK) |
| /*! @} */ |
| |
| /*! @name SPDIF_CH1_CS_159128_ADDR - */ |
| /*! @{ */ |
| #define HDMI_TX_SPDIF_CH1_CS_159128_ADDR_spdif_ch1_st_stts_bits159128_MASK (0xFFFFFFFFU) |
| #define HDMI_TX_SPDIF_CH1_CS_159128_ADDR_spdif_ch1_st_stts_bits159128_SHIFT (0U) |
| #define HDMI_TX_SPDIF_CH1_CS_159128_ADDR_spdif_ch1_st_stts_bits159128(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH1_CS_159128_ADDR_spdif_ch1_st_stts_bits159128_SHIFT)) & HDMI_TX_SPDIF_CH1_CS_159128_ADDR_spdif_ch1_st_stts_bits159128_MASK) |
| /*! @} */ |
| |
| /*! @name SPDIF_CH1_CS_191160_ADDR - */ |
| /*! @{ */ |
| #define HDMI_TX_SPDIF_CH1_CS_191160_ADDR_spdif_ch1_st_stts_bits191160_MASK (0xFFFFFFFFU) |
| #define HDMI_TX_SPDIF_CH1_CS_191160_ADDR_spdif_ch1_st_stts_bits191160_SHIFT (0U) |
| #define HDMI_TX_SPDIF_CH1_CS_191160_ADDR_spdif_ch1_st_stts_bits191160(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH1_CS_191160_ADDR_spdif_ch1_st_stts_bits191160_SHIFT)) & HDMI_TX_SPDIF_CH1_CS_191160_ADDR_spdif_ch1_st_stts_bits191160_MASK) |
| /*! @} */ |
| |
| /*! @name SPDIF_CH2_CS_3100_ADDR - */ |
| /*! @{ */ |
| #define HDMI_TX_SPDIF_CH2_CS_3100_ADDR_spdif_ch2_st_stts_bits3100_MASK (0xFFFFFFFFU) |
| #define HDMI_TX_SPDIF_CH2_CS_3100_ADDR_spdif_ch2_st_stts_bits3100_SHIFT (0U) |
| #define HDMI_TX_SPDIF_CH2_CS_3100_ADDR_spdif_ch2_st_stts_bits3100(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH2_CS_3100_ADDR_spdif_ch2_st_stts_bits3100_SHIFT)) & HDMI_TX_SPDIF_CH2_CS_3100_ADDR_spdif_ch2_st_stts_bits3100_MASK) |
| /*! @} */ |
| |
| /*! @name SPDIF_CH2_CS_6332_ADDR - */ |
| /*! @{ */ |
| #define HDMI_TX_SPDIF_CH2_CS_6332_ADDR_spdif_ch2_st_stts_bits6332_MASK (0xFFFFFFFFU) |
| #define HDMI_TX_SPDIF_CH2_CS_6332_ADDR_spdif_ch2_st_stts_bits6332_SHIFT (0U) |
| #define HDMI_TX_SPDIF_CH2_CS_6332_ADDR_spdif_ch2_st_stts_bits6332(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH2_CS_6332_ADDR_spdif_ch2_st_stts_bits6332_SHIFT)) & HDMI_TX_SPDIF_CH2_CS_6332_ADDR_spdif_ch2_st_stts_bits6332_MASK) |
| /*! @} */ |
| |
| /*! @name SPDIF_CH2_CS_9564_ADDR - */ |
| /*! @{ */ |
| #define HDMI_TX_SPDIF_CH2_CS_9564_ADDR_spdif_ch2_st_stts_bits9564_MASK (0xFFFFFFFFU) |
| #define HDMI_TX_SPDIF_CH2_CS_9564_ADDR_spdif_ch2_st_stts_bits9564_SHIFT (0U) |
| #define HDMI_TX_SPDIF_CH2_CS_9564_ADDR_spdif_ch2_st_stts_bits9564(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH2_CS_9564_ADDR_spdif_ch2_st_stts_bits9564_SHIFT)) & HDMI_TX_SPDIF_CH2_CS_9564_ADDR_spdif_ch2_st_stts_bits9564_MASK) |
| /*! @} */ |
| |
| /*! @name SPDIF_CH2_CS_12796_ADDR - */ |
| /*! @{ */ |
| #define HDMI_TX_SPDIF_CH2_CS_12796_ADDR_spdif_ch2_st_stts_bits12796_MASK (0xFFFFFFFFU) |
| #define HDMI_TX_SPDIF_CH2_CS_12796_ADDR_spdif_ch2_st_stts_bits12796_SHIFT (0U) |
| #define HDMI_TX_SPDIF_CH2_CS_12796_ADDR_spdif_ch2_st_stts_bits12796(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH2_CS_12796_ADDR_spdif_ch2_st_stts_bits12796_SHIFT)) & HDMI_TX_SPDIF_CH2_CS_12796_ADDR_spdif_ch2_st_stts_bits12796_MASK) |
| /*! @} */ |
| |
| /*! @name SPDIF_CH2_CS_159128_ADDR - */ |
| /*! @{ */ |
| #define HDMI_TX_SPDIF_CH2_CS_159128_ADDR_spdif_ch2_st_stts_bits159128_MASK (0xFFFFFFFFU) |
| #define HDMI_TX_SPDIF_CH2_CS_159128_ADDR_spdif_ch2_st_stts_bits159128_SHIFT (0U) |
| #define HDMI_TX_SPDIF_CH2_CS_159128_ADDR_spdif_ch2_st_stts_bits159128(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH2_CS_159128_ADDR_spdif_ch2_st_stts_bits159128_SHIFT)) & HDMI_TX_SPDIF_CH2_CS_159128_ADDR_spdif_ch2_st_stts_bits159128_MASK) |
| /*! @} */ |
| |
| /*! @name SPDIF_CH2_CS_191160_ADDR - */ |
| /*! @{ */ |
| #define HDMI_TX_SPDIF_CH2_CS_191160_ADDR_spdif_ch2_st_stts_bits191160_MASK (0xFFFFFFFFU) |
| #define HDMI_TX_SPDIF_CH2_CS_191160_ADDR_spdif_ch2_st_stts_bits191160_SHIFT (0U) |
| #define HDMI_TX_SPDIF_CH2_CS_191160_ADDR_spdif_ch2_st_stts_bits191160(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SPDIF_CH2_CS_191160_ADDR_spdif_ch2_st_stts_bits191160_SHIFT)) & HDMI_TX_SPDIF_CH2_CS_191160_ADDR_spdif_ch2_st_stts_bits191160_MASK) |
| /*! @} */ |
| |
| /*! @name SMPL2PKT_CNTL - */ |
| /*! @{ */ |
| #define HDMI_TX_SMPL2PKT_CNTL_sw_rst_MASK (0x1U) |
| #define HDMI_TX_SMPL2PKT_CNTL_sw_rst_SHIFT (0U) |
| #define HDMI_TX_SMPL2PKT_CNTL_sw_rst(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNTL_sw_rst_SHIFT)) & HDMI_TX_SMPL2PKT_CNTL_sw_rst_MASK) |
| #define HDMI_TX_SMPL2PKT_CNTL_smpl2pkt_en_MASK (0x2U) |
| #define HDMI_TX_SMPL2PKT_CNTL_smpl2pkt_en_SHIFT (1U) |
| #define HDMI_TX_SMPL2PKT_CNTL_smpl2pkt_en(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNTL_smpl2pkt_en_SHIFT)) & HDMI_TX_SMPL2PKT_CNTL_smpl2pkt_en_MASK) |
| #define HDMI_TX_SMPL2PKT_CNTL_reserved_0_MASK (0xFFFFFFFCU) |
| #define HDMI_TX_SMPL2PKT_CNTL_reserved_0_SHIFT (2U) |
| #define HDMI_TX_SMPL2PKT_CNTL_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNTL_reserved_0_SHIFT)) & HDMI_TX_SMPL2PKT_CNTL_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SMPL2PKT_CNFG - */ |
| /*! @{ */ |
| #define HDMI_TX_SMPL2PKT_CNFG_max_num_ch_MASK (0x1FU) |
| #define HDMI_TX_SMPL2PKT_CNFG_max_num_ch_SHIFT (0U) |
| #define HDMI_TX_SMPL2PKT_CNFG_max_num_ch(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_max_num_ch_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_max_num_ch_MASK) |
| #define HDMI_TX_SMPL2PKT_CNFG_num_of_i2s_ports_MASK (0x60U) |
| #define HDMI_TX_SMPL2PKT_CNFG_num_of_i2s_ports_SHIFT (5U) |
| #define HDMI_TX_SMPL2PKT_CNFG_num_of_i2s_ports(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_num_of_i2s_ports_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_num_of_i2s_ports_MASK) |
| #define HDMI_TX_SMPL2PKT_CNFG_audio_type_MASK (0x780U) |
| #define HDMI_TX_SMPL2PKT_CNFG_audio_type_SHIFT (7U) |
| #define HDMI_TX_SMPL2PKT_CNFG_audio_type(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_audio_type_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_audio_type_MASK) |
| #define HDMI_TX_SMPL2PKT_CNFG_cfg_sub_pckt_num_MASK (0x3800U) |
| #define HDMI_TX_SMPL2PKT_CNFG_cfg_sub_pckt_num_SHIFT (11U) |
| #define HDMI_TX_SMPL2PKT_CNFG_cfg_sub_pckt_num(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_cfg_sub_pckt_num_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_cfg_sub_pckt_num_MASK) |
| #define HDMI_TX_SMPL2PKT_CNFG_cfg_block_lpcm_first_pkt_MASK (0x4000U) |
| #define HDMI_TX_SMPL2PKT_CNFG_cfg_block_lpcm_first_pkt_SHIFT (14U) |
| #define HDMI_TX_SMPL2PKT_CNFG_cfg_block_lpcm_first_pkt(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_cfg_block_lpcm_first_pkt_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_cfg_block_lpcm_first_pkt_MASK) |
| #define HDMI_TX_SMPL2PKT_CNFG_cfg_en_auto_sub_pckt_num_MASK (0x8000U) |
| #define HDMI_TX_SMPL2PKT_CNFG_cfg_en_auto_sub_pckt_num_SHIFT (15U) |
| #define HDMI_TX_SMPL2PKT_CNFG_cfg_en_auto_sub_pckt_num(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_cfg_en_auto_sub_pckt_num_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_cfg_en_auto_sub_pckt_num_MASK) |
| #define HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_MASK (0xF0000U) |
| #define HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_SHIFT (16U) |
| #define HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_MASK) |
| #define HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_force_MASK (0x100000U) |
| #define HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_force_SHIFT (20U) |
| #define HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_force(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_force_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_cfg_sample_present_force_MASK) |
| #define HDMI_TX_SMPL2PKT_CNFG_reserved_0_MASK (0xFFE00000U) |
| #define HDMI_TX_SMPL2PKT_CNFG_reserved_0_SHIFT (21U) |
| #define HDMI_TX_SMPL2PKT_CNFG_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SMPL2PKT_CNFG_reserved_0_SHIFT)) & HDMI_TX_SMPL2PKT_CNFG_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name FIFO_CNTL - */ |
| /*! @{ */ |
| #define HDMI_TX_FIFO_CNTL_fifo_sw_rst_MASK (0x1U) |
| #define HDMI_TX_FIFO_CNTL_fifo_sw_rst_SHIFT (0U) |
| #define HDMI_TX_FIFO_CNTL_fifo_sw_rst(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_CNTL_fifo_sw_rst_SHIFT)) & HDMI_TX_FIFO_CNTL_fifo_sw_rst_MASK) |
| #define HDMI_TX_FIFO_CNTL_sync_wr_to_ch_zero_MASK (0x2U) |
| #define HDMI_TX_FIFO_CNTL_sync_wr_to_ch_zero_SHIFT (1U) |
| #define HDMI_TX_FIFO_CNTL_sync_wr_to_ch_zero(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_CNTL_sync_wr_to_ch_zero_SHIFT)) & HDMI_TX_FIFO_CNTL_sync_wr_to_ch_zero_MASK) |
| #define HDMI_TX_FIFO_CNTL_fifo_dir_MASK (0x4U) |
| #define HDMI_TX_FIFO_CNTL_fifo_dir_SHIFT (2U) |
| #define HDMI_TX_FIFO_CNTL_fifo_dir(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_CNTL_fifo_dir_SHIFT)) & HDMI_TX_FIFO_CNTL_fifo_dir_MASK) |
| #define HDMI_TX_FIFO_CNTL_fifo_empty_calc_MASK (0x8U) |
| #define HDMI_TX_FIFO_CNTL_fifo_empty_calc_SHIFT (3U) |
| #define HDMI_TX_FIFO_CNTL_fifo_empty_calc(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_CNTL_fifo_empty_calc_SHIFT)) & HDMI_TX_FIFO_CNTL_fifo_empty_calc_MASK) |
| #define HDMI_TX_FIFO_CNTL_cfg_dis_port3_MASK (0x10U) |
| #define HDMI_TX_FIFO_CNTL_cfg_dis_port3_SHIFT (4U) |
| #define HDMI_TX_FIFO_CNTL_cfg_dis_port3(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_CNTL_cfg_dis_port3_SHIFT)) & HDMI_TX_FIFO_CNTL_cfg_dis_port3_MASK) |
| #define HDMI_TX_FIFO_CNTL_reserved_0_MASK (0xFFFFFFE0U) |
| #define HDMI_TX_FIFO_CNTL_reserved_0_SHIFT (5U) |
| #define HDMI_TX_FIFO_CNTL_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_CNTL_reserved_0_SHIFT)) & HDMI_TX_FIFO_CNTL_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name FIFO_STTS - */ |
| /*! @{ */ |
| #define HDMI_TX_FIFO_STTS_wfull_MASK (0x1U) |
| #define HDMI_TX_FIFO_STTS_wfull_SHIFT (0U) |
| #define HDMI_TX_FIFO_STTS_wfull(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_STTS_wfull_SHIFT)) & HDMI_TX_FIFO_STTS_wfull_MASK) |
| #define HDMI_TX_FIFO_STTS_rempty_MASK (0x2U) |
| #define HDMI_TX_FIFO_STTS_rempty_SHIFT (1U) |
| #define HDMI_TX_FIFO_STTS_rempty(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_STTS_rempty_SHIFT)) & HDMI_TX_FIFO_STTS_rempty_MASK) |
| #define HDMI_TX_FIFO_STTS_overrun_MASK (0x4U) |
| #define HDMI_TX_FIFO_STTS_overrun_SHIFT (2U) |
| #define HDMI_TX_FIFO_STTS_overrun(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_STTS_overrun_SHIFT)) & HDMI_TX_FIFO_STTS_overrun_MASK) |
| #define HDMI_TX_FIFO_STTS_underrun_MASK (0x8U) |
| #define HDMI_TX_FIFO_STTS_underrun_SHIFT (3U) |
| #define HDMI_TX_FIFO_STTS_underrun(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_STTS_underrun_SHIFT)) & HDMI_TX_FIFO_STTS_underrun_MASK) |
| #define HDMI_TX_FIFO_STTS_reserved_0_MASK (0xFFFFFFF0U) |
| #define HDMI_TX_FIFO_STTS_reserved_0_SHIFT (4U) |
| #define HDMI_TX_FIFO_STTS_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_FIFO_STTS_reserved_0_SHIFT)) & HDMI_TX_FIFO_STTS_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SUB_PCKT_THRSH - */ |
| /*! @{ */ |
| #define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh1_MASK (0xFFU) |
| #define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh1_SHIFT (0U) |
| #define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh1(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh1_SHIFT)) & HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh1_MASK) |
| #define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh2_MASK (0xFF00U) |
| #define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh2_SHIFT (8U) |
| #define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh2(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh2_SHIFT)) & HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh2_MASK) |
| #define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh3_MASK (0xFF0000U) |
| #define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh3_SHIFT (16U) |
| #define HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh3(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh3_SHIFT)) & HDMI_TX_SUB_PCKT_THRSH_cfg_mem_fifo_thrsh3_MASK) |
| #define HDMI_TX_SUB_PCKT_THRSH_reserved_0_MASK (0xFF000000U) |
| #define HDMI_TX_SUB_PCKT_THRSH_reserved_0_SHIFT (24U) |
| #define HDMI_TX_SUB_PCKT_THRSH_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SUB_PCKT_THRSH_reserved_0_SHIFT)) & HDMI_TX_SUB_PCKT_THRSH_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SOURCE_PIF_WR_ADDR - */ |
| /*! @{ */ |
| #define HDMI_TX_SOURCE_PIF_WR_ADDR_wr_addr_MASK (0xFU) |
| #define HDMI_TX_SOURCE_PIF_WR_ADDR_wr_addr_SHIFT (0U) |
| #define HDMI_TX_SOURCE_PIF_WR_ADDR_wr_addr(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_WR_ADDR_wr_addr_SHIFT)) & HDMI_TX_SOURCE_PIF_WR_ADDR_wr_addr_MASK) |
| #define HDMI_TX_SOURCE_PIF_WR_ADDR_reserved_0_MASK (0xFFFFFFF0U) |
| #define HDMI_TX_SOURCE_PIF_WR_ADDR_reserved_0_SHIFT (4U) |
| #define HDMI_TX_SOURCE_PIF_WR_ADDR_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_WR_ADDR_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_WR_ADDR_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SOURCE_PIF_WR_REQ - */ |
| /*! @{ */ |
| #define HDMI_TX_SOURCE_PIF_WR_REQ_host_wr_MASK (0x1U) |
| #define HDMI_TX_SOURCE_PIF_WR_REQ_host_wr_SHIFT (0U) |
| #define HDMI_TX_SOURCE_PIF_WR_REQ_host_wr(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_WR_REQ_host_wr_SHIFT)) & HDMI_TX_SOURCE_PIF_WR_REQ_host_wr_MASK) |
| #define HDMI_TX_SOURCE_PIF_WR_REQ_reserved_0_MASK (0xFFFFFFFEU) |
| #define HDMI_TX_SOURCE_PIF_WR_REQ_reserved_0_SHIFT (1U) |
| #define HDMI_TX_SOURCE_PIF_WR_REQ_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_WR_REQ_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_WR_REQ_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SOURCE_PIF_RD_ADDR - */ |
| /*! @{ */ |
| #define HDMI_TX_SOURCE_PIF_RD_ADDR_rd_addr_MASK (0xFU) |
| #define HDMI_TX_SOURCE_PIF_RD_ADDR_rd_addr_SHIFT (0U) |
| #define HDMI_TX_SOURCE_PIF_RD_ADDR_rd_addr(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_RD_ADDR_rd_addr_SHIFT)) & HDMI_TX_SOURCE_PIF_RD_ADDR_rd_addr_MASK) |
| #define HDMI_TX_SOURCE_PIF_RD_ADDR_reserved_0_MASK (0xFFFFFFF0U) |
| #define HDMI_TX_SOURCE_PIF_RD_ADDR_reserved_0_SHIFT (4U) |
| #define HDMI_TX_SOURCE_PIF_RD_ADDR_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_RD_ADDR_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_RD_ADDR_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SOURCE_PIF_RD_REQ - */ |
| /*! @{ */ |
| #define HDMI_TX_SOURCE_PIF_RD_REQ_host_rd_MASK (0x1U) |
| #define HDMI_TX_SOURCE_PIF_RD_REQ_host_rd_SHIFT (0U) |
| #define HDMI_TX_SOURCE_PIF_RD_REQ_host_rd(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_RD_REQ_host_rd_SHIFT)) & HDMI_TX_SOURCE_PIF_RD_REQ_host_rd_MASK) |
| #define HDMI_TX_SOURCE_PIF_RD_REQ_reserved_0_MASK (0xFFFFFFFEU) |
| #define HDMI_TX_SOURCE_PIF_RD_REQ_reserved_0_SHIFT (1U) |
| #define HDMI_TX_SOURCE_PIF_RD_REQ_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_RD_REQ_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_RD_REQ_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SOURCE_PIF_DATA_WR - */ |
| /*! @{ */ |
| #define HDMI_TX_SOURCE_PIF_DATA_WR_data_wr_MASK (0xFFFFFFFFU) |
| #define HDMI_TX_SOURCE_PIF_DATA_WR_data_wr_SHIFT (0U) |
| #define HDMI_TX_SOURCE_PIF_DATA_WR_data_wr(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_DATA_WR_data_wr_SHIFT)) & HDMI_TX_SOURCE_PIF_DATA_WR_data_wr_MASK) |
| /*! @} */ |
| |
| /*! @name SOURCE_PIF_DATA_RD - */ |
| /*! @{ */ |
| #define HDMI_TX_SOURCE_PIF_DATA_RD_fifo2_data_out_MASK (0xFFFFFFFFU) |
| #define HDMI_TX_SOURCE_PIF_DATA_RD_fifo2_data_out_SHIFT (0U) |
| #define HDMI_TX_SOURCE_PIF_DATA_RD_fifo2_data_out(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_DATA_RD_fifo2_data_out_SHIFT)) & HDMI_TX_SOURCE_PIF_DATA_RD_fifo2_data_out_MASK) |
| /*! @} */ |
| |
| /*! @name SOURCE_PIF_FIFO1_FLUSH - */ |
| /*! @{ */ |
| #define HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_fifo1_flush_MASK (0x1U) |
| #define HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_fifo1_flush_SHIFT (0U) |
| #define HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_fifo1_flush(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_fifo1_flush_SHIFT)) & HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_fifo1_flush_MASK) |
| #define HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_reserved_0_MASK (0xFFFFFFFEU) |
| #define HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_reserved_0_SHIFT (1U) |
| #define HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_FIFO1_FLUSH_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SOURCE_PIF_FIFO2_FLUSH - */ |
| /*! @{ */ |
| #define HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_fifo2_flush_MASK (0x1U) |
| #define HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_fifo2_flush_SHIFT (0U) |
| #define HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_fifo2_flush(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_fifo2_flush_SHIFT)) & HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_fifo2_flush_MASK) |
| #define HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_reserved_0_MASK (0xFFFFFFFEU) |
| #define HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_reserved_0_SHIFT (1U) |
| #define HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_FIFO2_FLUSH_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SOURCE_PIF_STATUS - */ |
| /*! @{ */ |
| #define HDMI_TX_SOURCE_PIF_STATUS_source_pkt_mem_ctrl_fsm_state_MASK (0x3U) |
| #define HDMI_TX_SOURCE_PIF_STATUS_source_pkt_mem_ctrl_fsm_state_SHIFT (0U) |
| #define HDMI_TX_SOURCE_PIF_STATUS_source_pkt_mem_ctrl_fsm_state(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_STATUS_source_pkt_mem_ctrl_fsm_state_SHIFT)) & HDMI_TX_SOURCE_PIF_STATUS_source_pkt_mem_ctrl_fsm_state_MASK) |
| #define HDMI_TX_SOURCE_PIF_STATUS_fifo1_full_MASK (0x4U) |
| #define HDMI_TX_SOURCE_PIF_STATUS_fifo1_full_SHIFT (2U) |
| #define HDMI_TX_SOURCE_PIF_STATUS_fifo1_full(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_STATUS_fifo1_full_SHIFT)) & HDMI_TX_SOURCE_PIF_STATUS_fifo1_full_MASK) |
| #define HDMI_TX_SOURCE_PIF_STATUS_fifo2_empty_MASK (0x8U) |
| #define HDMI_TX_SOURCE_PIF_STATUS_fifo2_empty_SHIFT (3U) |
| #define HDMI_TX_SOURCE_PIF_STATUS_fifo2_empty(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_STATUS_fifo2_empty_SHIFT)) & HDMI_TX_SOURCE_PIF_STATUS_fifo2_empty_MASK) |
| #define HDMI_TX_SOURCE_PIF_STATUS_reserved_0_MASK (0xFFFFFFF0U) |
| #define HDMI_TX_SOURCE_PIF_STATUS_reserved_0_SHIFT (4U) |
| #define HDMI_TX_SOURCE_PIF_STATUS_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_STATUS_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_STATUS_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SOURCE_PIF_INTERRUPT_SOURCE - */ |
| /*! @{ */ |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_wr_done_int_MASK (0x1U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_wr_done_int_SHIFT (0U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_wr_done_int(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_wr_done_int_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_wr_done_int_MASK) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_rd_done_int_MASK (0x2U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_rd_done_int_SHIFT (1U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_rd_done_int(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_rd_done_int_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_host_rd_done_int_MASK) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_nonvalid_type_requested_int_MASK (0x4U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_nonvalid_type_requested_int_SHIFT (2U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_nonvalid_type_requested_int(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_nonvalid_type_requested_int_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_nonvalid_type_requested_int_MASK) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_pslverr_MASK (0x8U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_pslverr_SHIFT (3U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_pslverr(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_pslverr_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_pslverr_MASK) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_done_MASK (0x10U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_done_SHIFT (4U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_done(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_done_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_done_MASK) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_error_MASK (0x20U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_error_SHIFT (5U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_error(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_error_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_alloc_wr_error_MASK) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_overflow_MASK (0x40U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_overflow_SHIFT (6U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_overflow(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_overflow_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_overflow_MASK) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_underflow_MASK (0x80U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_underflow_SHIFT (7U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_underflow(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_underflow_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo1_underflow_MASK) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_overflow_MASK (0x100U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_overflow_SHIFT (8U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_overflow(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_overflow_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_overflow_MASK) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_underflow_MASK (0x200U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_underflow_SHIFT (9U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_underflow(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_underflow_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_fifo2_underflow_MASK) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_reserved_0_MASK (0xFFFFFC00U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_reserved_0_SHIFT (10U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_SOURCE_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SOURCE_PIF_INTERRUPT_MASK - */ |
| /*! @{ */ |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_wr_done_int_mask_MASK (0x1U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_wr_done_int_mask_SHIFT (0U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_wr_done_int_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_wr_done_int_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_wr_done_int_mask_MASK) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_rd_done_int_mask_MASK (0x2U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_rd_done_int_mask_SHIFT (1U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_rd_done_int_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_rd_done_int_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_host_rd_done_int_mask_MASK) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_nonvalid_type_requested_int_mask_MASK (0x4U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_nonvalid_type_requested_int_mask_SHIFT (2U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_nonvalid_type_requested_int_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_nonvalid_type_requested_int_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_nonvalid_type_requested_int_mask_MASK) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_pslverr_mask_MASK (0x8U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_pslverr_mask_SHIFT (3U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_pslverr_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_pslverr_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_pslverr_mask_MASK) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_done_mask_MASK (0x10U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_done_mask_SHIFT (4U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_done_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_done_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_done_mask_MASK) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_error_mask_MASK (0x20U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_error_mask_SHIFT (5U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_error_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_error_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_alloc_wr_error_mask_MASK) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_overflow_mask_MASK (0x40U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_overflow_mask_SHIFT (6U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_overflow_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_overflow_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_overflow_mask_MASK) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_underflow_mask_MASK (0x80U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_underflow_mask_SHIFT (7U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_underflow_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_underflow_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo1_underflow_mask_MASK) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_overflow_mask_MASK (0x100U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_overflow_mask_SHIFT (8U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_overflow_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_overflow_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_overflow_mask_MASK) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_underflow_mask_MASK (0x200U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_underflow_mask_SHIFT (9U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_underflow_mask(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_underflow_mask_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_fifo2_underflow_mask_MASK) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_reserved_0_MASK (0xFFFFFC00U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_reserved_0_SHIFT (10U) |
| #define HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_INTERRUPT_MASK_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SOURCE_PIF_PKT_ALLOC_REG - */ |
| /*! @{ */ |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_pkt_alloc_address_MASK (0xFU) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_pkt_alloc_address_SHIFT (0U) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_pkt_alloc_address(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_pkt_alloc_address_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_pkt_alloc_address_MASK) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_0_MASK (0xF0U) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_0_SHIFT (4U) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_0_MASK) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_packet_type_MASK (0xFF00U) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_packet_type_SHIFT (8U) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_packet_type(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_packet_type_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_packet_type_MASK) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_type_valid_MASK (0x10000U) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_type_valid_SHIFT (16U) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_type_valid(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_type_valid_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_type_valid_MASK) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_active_idle_type_MASK (0x20000U) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_active_idle_type_SHIFT (17U) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_active_idle_type(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_active_idle_type_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_active_idle_type_MASK) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_1_MASK (0xFFFC0000U) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_1_SHIFT (18U) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_1(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_1_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_REG_reserved_1_MASK) |
| /*! @} */ |
| |
| /*! @name SOURCE_PIF_PKT_ALLOC_WR_EN - */ |
| /*! @{ */ |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_pkt_alloc_wr_en_MASK (0x1U) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_pkt_alloc_wr_en_SHIFT (0U) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_pkt_alloc_wr_en(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_pkt_alloc_wr_en_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_pkt_alloc_wr_en_MASK) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_reserved_0_MASK (0xFFFFFFFEU) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_reserved_0_SHIFT (1U) |
| #define HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_PKT_ALLOC_WR_EN_reserved_0_MASK) |
| /*! @} */ |
| |
| /*! @name SOURCE_PIF_SW_RESET - */ |
| /*! @{ */ |
| #define HDMI_TX_SOURCE_PIF_SW_RESET_sw_rst_MASK (0x1U) |
| #define HDMI_TX_SOURCE_PIF_SW_RESET_sw_rst_SHIFT (0U) |
| #define HDMI_TX_SOURCE_PIF_SW_RESET_sw_rst(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_SW_RESET_sw_rst_SHIFT)) & HDMI_TX_SOURCE_PIF_SW_RESET_sw_rst_MASK) |
| #define HDMI_TX_SOURCE_PIF_SW_RESET_reserved_0_MASK (0xFFFFFFFEU) |
| #define HDMI_TX_SOURCE_PIF_SW_RESET_reserved_0_SHIFT (1U) |
| #define HDMI_TX_SOURCE_PIF_SW_RESET_reserved_0(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_SOURCE_PIF_SW_RESET_reserved_0_SHIFT)) & HDMI_TX_SOURCE_PIF_SW_RESET_reserved_0_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group HDMI_TX_Register_Masks */ |
| |
| |
| /* HDMI_TX - Peripheral instance base addresses */ |
| /** Peripheral HDMI_TX base address */ |
| #define HDMI_TX_BASE (0x32C00000u) |
| /** Peripheral HDMI_TX base pointer */ |
| #define HDMI_TX ((HDMI_TX_Type *)HDMI_TX_BASE) |
| /** Array initializer of HDMI_TX peripheral base addresses */ |
| #define HDMI_TX_BASE_ADDRS { HDMI_TX_BASE } |
| /** Array initializer of HDMI_TX peripheral base pointers */ |
| #define HDMI_TX_BASE_PTRS { HDMI_TX } |
| |
| /*! |
| * @} |
| */ /* end of group HDMI_TX_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- I2C Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** I2C - Register Layout Typedef */ |
| typedef struct { |
| __IO uint16_t IADR; /**< I2C Address Register, offset: 0x0 */ |
| uint8_t RESERVED_0[2]; |
| __IO uint16_t IFDR; /**< I2C Frequency Divider Register, offset: 0x4 */ |
| uint8_t RESERVED_1[2]; |
| __IO uint16_t I2CR; /**< I2C Control Register, offset: 0x8 */ |
| uint8_t RESERVED_2[2]; |
| __IO uint16_t I2SR; /**< I2C Status Register, offset: 0xC */ |
| uint8_t RESERVED_3[2]; |
| __IO uint16_t I2DR; /**< I2C Data I/O Register, offset: 0x10 */ |
| } I2C_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- I2C Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup I2C_Register_Masks I2C Register Masks |
| * @{ |
| */ |
| |
| /*! @name IADR - I2C Address Register */ |
| /*! @{ */ |
| #define I2C_IADR_ADR_MASK (0xFEU) |
| #define I2C_IADR_ADR_SHIFT (1U) |
| #define I2C_IADR_ADR(x) (((uint16_t)(((uint16_t)(x)) << I2C_IADR_ADR_SHIFT)) & I2C_IADR_ADR_MASK) |
| /*! @} */ |
| |
| /*! @name IFDR - I2C Frequency Divider Register */ |
| /*! @{ */ |
| #define I2C_IFDR_IC_MASK (0x3FU) |
| #define I2C_IFDR_IC_SHIFT (0U) |
| #define I2C_IFDR_IC(x) (((uint16_t)(((uint16_t)(x)) << I2C_IFDR_IC_SHIFT)) & I2C_IFDR_IC_MASK) |
| /*! @} */ |
| |
| /*! @name I2CR - I2C Control Register */ |
| /*! @{ */ |
| #define I2C_I2CR_RSTA_MASK (0x4U) |
| #define I2C_I2CR_RSTA_SHIFT (2U) |
| /*! RSTA |
| * 0b0..No repeat start |
| * 0b1..Generates a Repeated Start condition |
| */ |
| #define I2C_I2CR_RSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_RSTA_SHIFT)) & I2C_I2CR_RSTA_MASK) |
| #define I2C_I2CR_TXAK_MASK (0x8U) |
| #define I2C_I2CR_TXAK_SHIFT (3U) |
| /*! TXAK |
| * 0b0..An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data. |
| * 0b1..No acknowledge signal response is sent (that is, the acknowledge bit = 1). |
| */ |
| #define I2C_I2CR_TXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_TXAK_SHIFT)) & I2C_I2CR_TXAK_MASK) |
| #define I2C_I2CR_MTX_MASK (0x10U) |
| #define I2C_I2CR_MTX_SHIFT (4U) |
| /*! MTX |
| * 0b0..Receive.When a slave is addressed, the software should set MTX according to the slave read/write bit in the I2C status register (I2C_I2SR[SRW]). |
| * 0b1..Transmit.In Master mode, MTX should be set according to the type of transfer required. Therefore, for address cycles, MTX is always 1. |
| */ |
| #define I2C_I2CR_MTX(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MTX_SHIFT)) & I2C_I2CR_MTX_MASK) |
| #define I2C_I2CR_MSTA_MASK (0x20U) |
| #define I2C_I2CR_MSTA_SHIFT (5U) |
| /*! MSTA |
| * 0b0..Slave mode. Changing MSTA from 1 to 0 generates a Stop and selects Slave mode. |
| * 0b1..Master mode. Changing MSTA from 0 to 1 signals a Start on the bus and selects Master mode. |
| */ |
| #define I2C_I2CR_MSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MSTA_SHIFT)) & I2C_I2CR_MSTA_MASK) |
| #define I2C_I2CR_IIEN_MASK (0x40U) |
| #define I2C_I2CR_IIEN_SHIFT (6U) |
| /*! IIEN |
| * 0b0..I2C interrupts are disabled, but the status flag I2C_I2SR[IIF] continues to be set when an Interrupt condition occurs. |
| * 0b1..I2C interrupts are enabled. An I2C interrupt occurs if I2C_I2SR[IIF] is also set. |
| */ |
| #define I2C_I2CR_IIEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IIEN_SHIFT)) & I2C_I2CR_IIEN_MASK) |
| #define I2C_I2CR_IEN_MASK (0x80U) |
| #define I2C_I2CR_IEN_SHIFT (7U) |
| /*! IEN |
| * 0b0..The block is disabled, but registers can still be accessed. |
| * 0b1..The I2C is enabled. This bit must be set before any other I2C_I2CR bits have an effect. |
| */ |
| #define I2C_I2CR_IEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IEN_SHIFT)) & I2C_I2CR_IEN_MASK) |
| /*! @} */ |
| |
| /*! @name I2SR - I2C Status Register */ |
| /*! @{ */ |
| #define I2C_I2SR_RXAK_MASK (0x1U) |
| #define I2C_I2SR_RXAK_SHIFT (0U) |
| /*! RXAK |
| * 0b0..An "acknowledge" signal was received after the completion of an 8-bit data transmission on the bus. |
| * 0b1..A "No acknowledge" signal was detected at the ninth clock. |
| */ |
| #define I2C_I2SR_RXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_RXAK_SHIFT)) & I2C_I2SR_RXAK_MASK) |
| #define I2C_I2SR_IIF_MASK (0x2U) |
| #define I2C_I2SR_IIF_SHIFT (1U) |
| /*! IIF |
| * 0b0..No I2C interrupt pending. |
| * 0b1..An interrupt is pending.This causes a processor interrupt request (if the interrupt enable is asserted [IIEN = 1]). The interrupt is set when one of the following occurs: One byte transfer is completed (the interrupt is set at the falling edge of the ninth clock). An address is received that matches its own specific address in Slave Receive mode. Arbitration is lost. |
| */ |
| #define I2C_I2SR_IIF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IIF_SHIFT)) & I2C_I2SR_IIF_MASK) |
| #define I2C_I2SR_SRW_MASK (0x4U) |
| #define I2C_I2SR_SRW_SHIFT (2U) |
| /*! SRW |
| * 0b0..Slave receive, master writing to slave |
| * 0b1..Slave transmit, master reading from slave |
| */ |
| #define I2C_I2SR_SRW(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_SRW_SHIFT)) & I2C_I2SR_SRW_MASK) |
| #define I2C_I2SR_IAL_MASK (0x10U) |
| #define I2C_I2SR_IAL_SHIFT (4U) |
| /*! IAL |
| * 0b0..No arbitration lost. |
| * 0b1..Arbitration is lost. |
| */ |
| #define I2C_I2SR_IAL(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAL_SHIFT)) & I2C_I2SR_IAL_MASK) |
| #define I2C_I2SR_IBB_MASK (0x20U) |
| #define I2C_I2SR_IBB_SHIFT (5U) |
| /*! IBB |
| * 0b0..Bus is idle. If a Stop signal is detected, IBB is cleared. |
| * 0b1..Bus is busy. When Start is detected, IBB is set. |
| */ |
| #define I2C_I2SR_IBB(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IBB_SHIFT)) & I2C_I2SR_IBB_MASK) |
| #define I2C_I2SR_IAAS_MASK (0x40U) |
| #define I2C_I2SR_IAAS_SHIFT (6U) |
| /*! IAAS |
| * 0b0..Not addressed |
| * 0b1..Addressed as a slave. Set when its own address (I2C_IADR) matches the calling address. |
| */ |
| #define I2C_I2SR_IAAS(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAAS_SHIFT)) & I2C_I2SR_IAAS_MASK) |
| #define I2C_I2SR_ICF_MASK (0x80U) |
| #define I2C_I2SR_ICF_SHIFT (7U) |
| /*! ICF |
| * 0b0..Transfer is in progress. |
| * 0b1..Transfer is complete. This bit is set by the falling edge of the ninth clock of the last byte transfer. |
| */ |
| #define I2C_I2SR_ICF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_ICF_SHIFT)) & I2C_I2SR_ICF_MASK) |
| /*! @} */ |
| |
| /*! @name I2DR - I2C Data I/O Register */ |
| /*! @{ */ |
| #define I2C_I2DR_DATA_MASK (0xFFU) |
| #define I2C_I2DR_DATA_SHIFT (0U) |
| #define I2C_I2DR_DATA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2DR_DATA_SHIFT)) & I2C_I2DR_DATA_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group I2C_Register_Masks */ |
| |
| |
| /* I2C - Peripheral instance base addresses */ |
| /** Peripheral I2C1 base address */ |
| #define I2C1_BASE (0x30A20000u) |
| /** Peripheral I2C1 base pointer */ |
| #define I2C1 ((I2C_Type *)I2C1_BASE) |
| /** Peripheral I2C2 base address */ |
| #define I2C2_BASE (0x30A30000u) |
| /** Peripheral I2C2 base pointer */ |
| #define I2C2 ((I2C_Type *)I2C2_BASE) |
| /** Peripheral I2C3 base address */ |
| #define I2C3_BASE (0x30A40000u) |
| /** Peripheral I2C3 base pointer */ |
| #define I2C3 ((I2C_Type *)I2C3_BASE) |
| /** Peripheral I2C4 base address */ |
| #define I2C4_BASE (0x30A50000u) |
| /** Peripheral I2C4 base pointer */ |
| #define I2C4 ((I2C_Type *)I2C4_BASE) |
| /** Array initializer of I2C peripheral base addresses */ |
| #define I2C_BASE_ADDRS { 0u, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE } |
| /** Array initializer of I2C peripheral base pointers */ |
| #define I2C_BASE_PTRS { (I2C_Type *)0u, I2C1, I2C2, I2C3, I2C4 } |
| /** Interrupt vectors for the I2C peripheral type */ |
| #define I2C_IRQS { NotAvail_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn, I2C4_IRQn } |
| |
| /*! |
| * @} |
| */ /* end of group I2C_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- I2S Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** I2S - Register Layout Typedef */ |
| typedef struct { |
| __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ |
| __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ |
| __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x8 */ |
| __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0xC */ |
| __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x10 */ |
| __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0x14 */ |
| __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x18 */ |
| __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x1C */ |
| __O uint32_t TDR[8]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ |
| __I uint32_t TFR[8]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ |
| __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ |
| uint8_t RESERVED_0[36]; |
| __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x88 */ |
| __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x8C */ |
| __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x90 */ |
| __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x94 */ |
| __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x98 */ |
| __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x9C */ |
| __I uint32_t RDR[8]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ |
| __I uint32_t RFR[8]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ |
| __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ |
| } I2S_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- I2S Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup I2S_Register_Masks I2S Register Masks |
| * @{ |
| */ |
| |
| /*! @name VERID - Version ID Register */ |
| /*! @{ */ |
| #define I2S_VERID_FEATURE_MASK (0xFFFFU) |
| #define I2S_VERID_FEATURE_SHIFT (0U) |
| /*! FEATURE - Feature Specification Number |
| * 0b0000000000000000..Standard feature set. |
| */ |
| #define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) |
| #define I2S_VERID_MINOR_MASK (0xFF0000U) |
| #define I2S_VERID_MINOR_SHIFT (16U) |
| #define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) |
| #define I2S_VERID_MAJOR_MASK (0xFF000000U) |
| #define I2S_VERID_MAJOR_SHIFT (24U) |
| #define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) |
| /*! @} */ |
| |
| /*! @name PARAM - Parameter Register */ |
| /*! @{ */ |
| #define I2S_PARAM_DATALINE_MASK (0xFU) |
| #define I2S_PARAM_DATALINE_SHIFT (0U) |
| #define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) |
| #define I2S_PARAM_FIFO_MASK (0xF00U) |
| #define I2S_PARAM_FIFO_SHIFT (8U) |
| #define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) |
| #define I2S_PARAM_FRAME_MASK (0xF0000U) |
| #define I2S_PARAM_FRAME_SHIFT (16U) |
| #define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) |
| /*! @} */ |
| |
| /*! @name TCSR - SAI Transmit Control Register */ |
| /*! @{ */ |
| #define I2S_TCSR_FRDE_MASK (0x1U) |
| #define I2S_TCSR_FRDE_SHIFT (0U) |
| /*! FRDE - FIFO Request DMA Enable |
| * 0b0..Disables the DMA request. |
| * 0b1..Enables the DMA request. |
| */ |
| #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) |
| #define I2S_TCSR_FWDE_MASK (0x2U) |
| #define I2S_TCSR_FWDE_SHIFT (1U) |
| /*! FWDE - FIFO Warning DMA Enable |
| * 0b0..Disables the DMA request. |
| * 0b1..Enables the DMA request. |
| */ |
| #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) |
| #define I2S_TCSR_FRIE_MASK (0x100U) |
| #define I2S_TCSR_FRIE_SHIFT (8U) |
| /*! FRIE - FIFO Request Interrupt Enable |
| * 0b0..Disables the interrupt. |
| * 0b1..Enables the interrupt. |
| */ |
| #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) |
| #define I2S_TCSR_FWIE_MASK (0x200U) |
| #define I2S_TCSR_FWIE_SHIFT (9U) |
| /*! FWIE - FIFO Warning Interrupt Enable |
| * 0b0..Disables the interrupt. |
| * 0b1..Enables the interrupt. |
| */ |
| #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) |
| #define I2S_TCSR_FEIE_MASK (0x400U) |
| #define I2S_TCSR_FEIE_SHIFT (10U) |
| /*! FEIE - FIFO Error Interrupt Enable |
| * 0b0..Disables the interrupt. |
| * 0b1..Enables the interrupt. |
| */ |
| #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) |
| #define I2S_TCSR_SEIE_MASK (0x800U) |
| #define I2S_TCSR_SEIE_SHIFT (11U) |
| /*! SEIE - Sync Error Interrupt Enable |
| * 0b0..Disables interrupt. |
| * 0b1..Enables interrupt. |
| */ |
| #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) |
| #define I2S_TCSR_WSIE_MASK (0x1000U) |
| #define I2S_TCSR_WSIE_SHIFT (12U) |
| /*! WSIE - Word Start Interrupt Enable |
| * 0b0..Disables interrupt. |
| * 0b1..Enables interrupt. |
| */ |
| #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) |
| #define I2S_TCSR_FRF_MASK (0x10000U) |
| #define I2S_TCSR_FRF_SHIFT (16U) |
| /*! FRF - FIFO Request Flag |
| * 0b0..Transmit FIFO watermark has not been reached. |
| * 0b1..Transmit FIFO watermark has been reached. |
| */ |
| #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) |
| #define I2S_TCSR_FWF_MASK (0x20000U) |
| #define I2S_TCSR_FWF_SHIFT (17U) |
| /*! FWF - FIFO Warning Flag |
| * 0b0..No enabled transmit FIFO is empty. |
| * 0b1..Enabled transmit FIFO is empty. |
| */ |
| #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) |
| #define I2S_TCSR_FEF_MASK (0x40000U) |
| #define I2S_TCSR_FEF_SHIFT (18U) |
| /*! FEF - FIFO Error Flag |
| * 0b0..Transmit underrun not detected. |
| * 0b1..Transmit underrun detected. |
| */ |
| #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) |
| #define I2S_TCSR_SEF_MASK (0x80000U) |
| #define I2S_TCSR_SEF_SHIFT (19U) |
| /*! SEF - Sync Error Flag |
| * 0b0..Sync error not detected. |
| * 0b1..Frame sync error detected. |
| */ |
| #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) |
| #define I2S_TCSR_WSF_MASK (0x100000U) |
| #define I2S_TCSR_WSF_SHIFT (20U) |
| /*! WSF - Word Start Flag |
| * 0b0..Start of word not detected. |
| * 0b1..Start of word detected. |
| */ |
| #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) |
| #define I2S_TCSR_SR_MASK (0x1000000U) |
| #define I2S_TCSR_SR_SHIFT (24U) |
| /*! SR - Software Reset |
| * 0b0..No effect. |
| * 0b1..Software reset. |
| */ |
| #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) |
| #define I2S_TCSR_FR_MASK (0x2000000U) |
| #define I2S_TCSR_FR_SHIFT (25U) |
| /*! FR - FIFO Reset |
| * 0b0..No effect. |
| * 0b1..FIFO reset. |
| */ |
| #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) |
| #define I2S_TCSR_BCE_MASK (0x10000000U) |
| #define I2S_TCSR_BCE_SHIFT (28U) |
| /*! BCE - Bit Clock Enable |
| * 0b0..Transmit bit clock is disabled. |
| * 0b1..Transmit bit clock is enabled. |
| */ |
| #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) |
| #define I2S_TCSR_DBGE_MASK (0x20000000U) |
| #define I2S_TCSR_DBGE_SHIFT (29U) |
| /*! DBGE - Debug Enable |
| * 0b0..Transmitter is disabled in Debug mode, after completing the current frame. |
| * 0b1..Transmitter is enabled in Debug mode. |
| */ |
| #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) |
| #define I2S_TCSR_TE_MASK (0x80000000U) |
| #define I2S_TCSR_TE_SHIFT (31U) |
| /*! TE - Transmitter Enable |
| * 0b0..Transmitter is disabled. |
| * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. |
| */ |
| #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) |
| /*! @} */ |
| |
| /*! @name TCR1 - SAI Transmit Configuration 1 Register */ |
| /*! @{ */ |
| #define I2S_TCR1_TFW_MASK (0x7FU) |
| #define I2S_TCR1_TFW_SHIFT (0U) |
| #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) |
| /*! @} */ |
| |
| /*! @name TCR2 - SAI Transmit Configuration 2 Register */ |
| /*! @{ */ |
| #define I2S_TCR2_DIV_MASK (0xFFU) |
| #define I2S_TCR2_DIV_SHIFT (0U) |
| #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) |
| #define I2S_TCR2_BCD_MASK (0x1000000U) |
| #define I2S_TCR2_BCD_SHIFT (24U) |
| /*! BCD - Bit Clock Direction |
| * 0b0..Bit clock is generated externally in Slave mode. |
| * 0b1..Bit clock is generated internally in Master mode. |
| */ |
| #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) |
| #define I2S_TCR2_BCP_MASK (0x2000000U) |
| #define I2S_TCR2_BCP_SHIFT (25U) |
| /*! BCP - Bit Clock Polarity |
| * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. |
| * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. |
| */ |
| #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) |
| #define I2S_TCR2_MSEL_MASK (0xC000000U) |
| #define I2S_TCR2_MSEL_SHIFT (26U) |
| /*! MSEL - MCLK Select |
| * 0b00..Bus Clock selected. |
| * 0b01..Master Clock (MCLK) 1 option selected. |
| * 0b10..Master Clock (MCLK) 2 option selected. |
| * 0b11..Master Clock (MCLK) 3 option selected. |
| */ |
| #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) |
| #define I2S_TCR2_BCI_MASK (0x10000000U) |
| #define I2S_TCR2_BCI_SHIFT (28U) |
| /*! BCI - Bit Clock Input |
| * 0b0..No effect. |
| * 0b1..Internal logic is clocked as if bit clock was externally generated. |
| */ |
| #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) |
| #define I2S_TCR2_BCS_MASK (0x20000000U) |
| #define I2S_TCR2_BCS_SHIFT (29U) |
| /*! BCS - Bit Clock Swap |
| * 0b0..Use the normal bit clock source. |
| * 0b1..Swap the bit clock source. |
| */ |
| #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) |
| #define I2S_TCR2_SYNC_MASK (0xC0000000U) |
| #define I2S_TCR2_SYNC_SHIFT (30U) |
| /*! SYNC - Synchronous Mode |
| * 0b00..Asynchronous mode. |
| * 0b01..Synchronous with receiver. |
| * 0b10..Reserved. |
| * 0b11..Reserved. |
| */ |
| #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) |
| /*! @} */ |
| |
| /*! @name TCR3 - SAI Transmit Configuration 3 Register */ |
| /*! @{ */ |
| #define I2S_TCR3_WDFL_MASK (0x1FU) |
| #define I2S_TCR3_WDFL_SHIFT (0U) |
| #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) |
| #define I2S_TCR3_TCE_MASK (0xFF0000U) /* Merged from fields with different position or width, of widths (1, 8), largest definition used */ |
| #define I2S_TCR3_TCE_SHIFT (16U) |
| #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 8), largest definition used */ |
| #define I2S_TCR3_CFR_MASK (0xFF000000U) |
| #define I2S_TCR3_CFR_SHIFT (24U) |
| #define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) |
| /*! @} */ |
| |
| /*! @name TCR4 - SAI Transmit Configuration 4 Register */ |
| /*! @{ */ |
| #define I2S_TCR4_FSD_MASK (0x1U) |
| #define I2S_TCR4_FSD_SHIFT (0U) |
| /*! FSD - Frame Sync Direction |
| * 0b0..Frame sync is generated externally in Slave mode. |
| * 0b1..Frame sync is generated internally in Master mode. |
| */ |
| #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) |
| #define I2S_TCR4_FSP_MASK (0x2U) |
| #define I2S_TCR4_FSP_SHIFT (1U) |
| /*! FSP - Frame Sync Polarity |
| * 0b0..Frame sync is active high. |
| * 0b1..Frame sync is active low. |
| */ |
| #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) |
| #define I2S_TCR4_ONDEM_MASK (0x4U) |
| #define I2S_TCR4_ONDEM_SHIFT (2U) |
| /*! ONDEM - On Demand Mode |
| * 0b0..Internal frame sync is generated continuously. |
| * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. |
| */ |
| #define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) |
| #define I2S_TCR4_FSE_MASK (0x8U) |
| #define I2S_TCR4_FSE_SHIFT (3U) |
| /*! FSE - Frame Sync Early |
| * 0b0..Frame sync asserts with the first bit of the frame. |
| * 0b1..Frame sync asserts one bit before the first bit of the frame. |
| */ |
| #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) |
| #define I2S_TCR4_MF_MASK (0x10U) |
| #define I2S_TCR4_MF_SHIFT (4U) |
| /*! MF - MSB First |
| * 0b0..LSB is transmitted first. |
| * 0b1..MSB is transmitted first. |
| */ |
| #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) |
| #define I2S_TCR4_CHMOD_MASK (0x20U) |
| #define I2S_TCR4_CHMOD_SHIFT (5U) |
| /*! CHMOD - Channel Mode |
| * 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. |
| * 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. |
| */ |
| #define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) |
| #define I2S_TCR4_SYWD_MASK (0x1F00U) |
| #define I2S_TCR4_SYWD_SHIFT (8U) |
| #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) |
| #define I2S_TCR4_FRSZ_MASK (0x1F0000U) |
| #define I2S_TCR4_FRSZ_SHIFT (16U) |
| #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) |
| #define I2S_TCR4_FPACK_MASK (0x3000000U) |
| #define I2S_TCR4_FPACK_SHIFT (24U) |
| /*! FPACK - FIFO Packing Mode |
| * 0b00..FIFO packing is disabled |
| * 0b01..Reserved |
| * 0b10..8-bit FIFO packing is enabled |
| * 0b11..16-bit FIFO packing is enabled |
| */ |
| #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) |
| #define I2S_TCR4_FCOMB_MASK (0xC000000U) |
| #define I2S_TCR4_FCOMB_SHIFT (26U) |
| /*! FCOMB - FIFO Combine Mode |
| * 0b00..FIFO combine mode disabled. |
| * 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers). |
| * 0b10..FIFO combine mode enabled on FIFO writes (by software). |
| * 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). |
| */ |
| #define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) |
| #define I2S_TCR4_FCONT_MASK (0x10000000U) |
| #define I2S_TCR4_FCONT_SHIFT (28U) |
| /*! FCONT - FIFO Continue on Error |
| * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. |
| * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. |
| */ |
| #define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) |
| /*! @} */ |
| |
| /*! @name TCR5 - SAI Transmit Configuration 5 Register */ |
| /*! @{ */ |
| #define I2S_TCR5_FBT_MASK (0x1F00U) |
| #define I2S_TCR5_FBT_SHIFT (8U) |
| #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) |
| #define I2S_TCR5_W0W_MASK (0x1F0000U) |
| #define I2S_TCR5_W0W_SHIFT (16U) |
| #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) |
| #define I2S_TCR5_WNW_MASK (0x1F000000U) |
| #define I2S_TCR5_WNW_SHIFT (24U) |
| #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) |
| /*! @} */ |
| |
| /*! @name TDR - SAI Transmit Data Register */ |
| /*! @{ */ |
| #define I2S_TDR_TDR_MASK (0xFFFFFFFFU) |
| #define I2S_TDR_TDR_SHIFT (0U) |
| #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) |
| /*! @} */ |
| |
| /* The count of I2S_TDR */ |
| #define I2S_TDR_COUNT (8U) |
| |
| /*! @name TFR - SAI Transmit FIFO Register */ |
| /*! @{ */ |
| #define I2S_TFR_RFP_MASK (0xFFU) |
| #define I2S_TFR_RFP_SHIFT (0U) |
| #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) |
| #define I2S_TFR_WFP_MASK (0xFF0000U) |
| #define I2S_TFR_WFP_SHIFT (16U) |
| #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) |
| #define I2S_TFR_WCP_MASK (0x80000000U) |
| #define I2S_TFR_WCP_SHIFT (31U) |
| /*! WCP - Write Channel Pointer |
| * 0b0..No effect. |
| * 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. |
| */ |
| #define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) |
| /*! @} */ |
| |
| /* The count of I2S_TFR */ |
| #define I2S_TFR_COUNT (8U) |
| |
| /*! @name TMR - SAI Transmit Mask Register */ |
| /*! @{ */ |
| #define I2S_TMR_TWM_MASK (0xFFFFFFFFU) |
| #define I2S_TMR_TWM_SHIFT (0U) |
| /*! TWM - Transmit Word Mask |
| * 0b00000000000000000000000000000000..Word N is enabled. |
| * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked. |
| */ |
| #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) |
| /*! @} */ |
| |
| /*! @name RCSR - SAI Receive Control Register */ |
| /*! @{ */ |
| #define I2S_RCSR_FRDE_MASK (0x1U) |
| #define I2S_RCSR_FRDE_SHIFT (0U) |
| /*! FRDE - FIFO Request DMA Enable |
| * 0b0..Disables the DMA request. |
| * 0b1..Enables the DMA request. |
| */ |
| #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) |
| #define I2S_RCSR_FWDE_MASK (0x2U) |
| #define I2S_RCSR_FWDE_SHIFT (1U) |
| /*! FWDE - FIFO Warning DMA Enable |
| * 0b0..Disables the DMA request. |
| * 0b1..Enables the DMA request. |
| */ |
| #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) |
| #define I2S_RCSR_FRIE_MASK (0x100U) |
| #define I2S_RCSR_FRIE_SHIFT (8U) |
| /*! FRIE - FIFO Request Interrupt Enable |
| * 0b0..Disables the interrupt. |
| * 0b1..Enables the interrupt. |
| */ |
| #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) |
| #define I2S_RCSR_FWIE_MASK (0x200U) |
| #define I2S_RCSR_FWIE_SHIFT (9U) |
| /*! FWIE - FIFO Warning Interrupt Enable |
| * 0b0..Disables the interrupt. |
| * 0b1..Enables the interrupt. |
| */ |
| #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) |
| #define I2S_RCSR_FEIE_MASK (0x400U) |
| #define I2S_RCSR_FEIE_SHIFT (10U) |
| /*! FEIE - FIFO Error Interrupt Enable |
| * 0b0..Disables the interrupt. |
| * 0b1..Enables the interrupt. |
| */ |
| #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) |
| #define I2S_RCSR_SEIE_MASK (0x800U) |
| #define I2S_RCSR_SEIE_SHIFT (11U) |
| /*! SEIE - Sync Error Interrupt Enable |
| * 0b0..Disables interrupt. |
| * 0b1..Enables interrupt. |
| */ |
| #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) |
| #define I2S_RCSR_WSIE_MASK (0x1000U) |
| #define I2S_RCSR_WSIE_SHIFT (12U) |
| /*! WSIE - Word Start Interrupt Enable |
| * 0b0..Disables interrupt. |
| * 0b1..Enables interrupt. |
| */ |
| #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) |
| #define I2S_RCSR_FRF_MASK (0x10000U) |
| #define I2S_RCSR_FRF_SHIFT (16U) |
| /*! FRF - FIFO Request Flag |
| * 0b0..Receive FIFO watermark not reached. |
| * 0b1..Receive FIFO watermark has been reached. |
| */ |
| #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) |
| #define I2S_RCSR_FWF_MASK (0x20000U) |
| #define I2S_RCSR_FWF_SHIFT (17U) |
| /*! FWF - FIFO Warning Flag |
| * 0b0..No enabled receive FIFO is full. |
| * 0b1..Enabled receive FIFO is full. |
| */ |
| #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) |
| #define I2S_RCSR_FEF_MASK (0x40000U) |
| #define I2S_RCSR_FEF_SHIFT (18U) |
| /*! FEF - FIFO Error Flag |
| * 0b0..Receive overflow not detected. |
| * 0b1..Receive overflow detected. |
| */ |
| #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) |
| #define I2S_RCSR_SEF_MASK (0x80000U) |
| #define I2S_RCSR_SEF_SHIFT (19U) |
| /*! SEF - Sync Error Flag |
| * 0b0..Sync error not detected. |
| * 0b1..Frame sync error detected. |
| */ |
| #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) |
| #define I2S_RCSR_WSF_MASK (0x100000U) |
| #define I2S_RCSR_WSF_SHIFT (20U) |
| /*! WSF - Word Start Flag |
| * 0b0..Start of word not detected. |
| * 0b1..Start of word detected. |
| */ |
| #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) |
| #define I2S_RCSR_SR_MASK (0x1000000U) |
| #define I2S_RCSR_SR_SHIFT (24U) |
| /*! SR - Software Reset |
| * 0b0..No effect. |
| * 0b1..Software reset. |
| */ |
| #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) |
| #define I2S_RCSR_FR_MASK (0x2000000U) |
| #define I2S_RCSR_FR_SHIFT (25U) |
| /*! FR - FIFO Reset |
| * 0b0..No effect. |
| * 0b1..FIFO reset. |
| */ |
| #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) |
| #define I2S_RCSR_BCE_MASK (0x10000000U) |
| #define I2S_RCSR_BCE_SHIFT (28U) |
| /*! BCE - Bit Clock Enable |
| * 0b0..Receive bit clock is disabled. |
| * 0b1..Receive bit clock is enabled. |
| */ |
| #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) |
| #define I2S_RCSR_DBGE_MASK (0x20000000U) |
| #define I2S_RCSR_DBGE_SHIFT (29U) |
| /*! DBGE - Debug Enable |
| * 0b0..Receiver is disabled in Debug mode, after completing the current frame. |
| * 0b1..Receiver is enabled in Debug mode. |
| */ |
| #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) |
| #define I2S_RCSR_RE_MASK (0x80000000U) |
| #define I2S_RCSR_RE_SHIFT (31U) |
| /*! RE - Receiver Enable |
| * 0b0..Receiver is disabled. |
| * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. |
| */ |
| #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) |
| /*! @} */ |
| |
| /*! @name RCR1 - SAI Receive Configuration 1 Register */ |
| /*! @{ */ |
| #define I2S_RCR1_RFW_MASK (0x7FU) |
| #define I2S_RCR1_RFW_SHIFT (0U) |
| #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) |
| /*! @} */ |
| |
| /*! @name RCR2 - SAI Receive Configuration 2 Register */ |
| /*! @{ */ |
| #define I2S_RCR2_DIV_MASK (0xFFU) |
| #define I2S_RCR2_DIV_SHIFT (0U) |
| #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) |
| #define I2S_RCR2_BCD_MASK (0x1000000U) |
| #define I2S_RCR2_BCD_SHIFT (24U) |
| /*! BCD - Bit Clock Direction |
| * 0b0..Bit clock is generated externally in Slave mode. |
| * 0b1..Bit clock is generated internally in Master mode. |
| */ |
| #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) |
| #define I2S_RCR2_BCP_MASK (0x2000000U) |
| #define I2S_RCR2_BCP_SHIFT (25U) |
| /*! BCP - Bit Clock Polarity |
| * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. |
| * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. |
| */ |
| #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) |
| #define I2S_RCR2_MSEL_MASK (0xC000000U) |
| #define I2S_RCR2_MSEL_SHIFT (26U) |
| /*! MSEL - MCLK Select |
| * 0b00..Bus Clock selected. |
| * 0b01..Master Clock (MCLK) 1 option selected. |
| * 0b10..Master Clock (MCLK) 2 option selected. |
| * 0b11..Master Clock (MCLK) 3 option selected. |
| */ |
| #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) |
| #define I2S_RCR2_BCI_MASK (0x10000000U) |
| #define I2S_RCR2_BCI_SHIFT (28U) |
| /*! BCI - Bit Clock Input |
| * 0b0..No effect. |
| * 0b1..Internal logic is clocked as if bit clock was externally generated. |
| */ |
| #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) |
| #define I2S_RCR2_BCS_MASK (0x20000000U) |
| #define I2S_RCR2_BCS_SHIFT (29U) |
| /*! BCS - Bit Clock Swap |
| * 0b0..Use the normal bit clock source. |
| * 0b1..Swap the bit clock source. |
| */ |
| #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) |
| #define I2S_RCR2_SYNC_MASK (0xC0000000U) |
| #define I2S_RCR2_SYNC_SHIFT (30U) |
| /*! SYNC - Synchronous Mode |
| * 0b00..Asynchronous mode. |
| * 0b01..Synchronous with transmitter. |
| * 0b10..Reserved. |
| * 0b11..Reserved. |
| */ |
| #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) |
| /*! @} */ |
| |
| /*! @name RCR3 - SAI Receive Configuration 3 Register */ |
| /*! @{ */ |
| #define I2S_RCR3_WDFL_MASK (0x1FU) |
| #define I2S_RCR3_WDFL_SHIFT (0U) |
| #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) |
| #define I2S_RCR3_RCE_MASK (0xFF0000U) /* Merged from fields with different position or width, of widths (1, 8), largest definition used */ |
| #define I2S_RCR3_RCE_SHIFT (16U) |
| #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 8), largest definition used */ |
| #define I2S_RCR3_CFR_MASK (0xFF000000U) |
| #define I2S_RCR3_CFR_SHIFT (24U) |
| #define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) |
| /*! @} */ |
| |
| /*! @name RCR4 - SAI Receive Configuration 4 Register */ |
| /*! @{ */ |
| #define I2S_RCR4_FSD_MASK (0x1U) |
| #define I2S_RCR4_FSD_SHIFT (0U) |
| /*! FSD - Frame Sync Direction |
| * 0b0..Frame Sync is generated externally in Slave mode. |
| * 0b1..Frame Sync is generated internally in Master mode. |
| */ |
| #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) |
| #define I2S_RCR4_FSP_MASK (0x2U) |
| #define I2S_RCR4_FSP_SHIFT (1U) |
| /*! FSP - Frame Sync Polarity |
| * 0b0..Frame sync is active high. |
| * 0b1..Frame sync is active low. |
| */ |
| #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) |
| #define I2S_RCR4_ONDEM_MASK (0x4U) |
| #define I2S_RCR4_ONDEM_SHIFT (2U) |
| /*! ONDEM - On Demand Mode |
| * 0b0..Internal frame sync is generated continuously. |
| * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. |
| */ |
| #define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) |
| #define I2S_RCR4_FSE_MASK (0x8U) |
| #define I2S_RCR4_FSE_SHIFT (3U) |
| /*! FSE - Frame Sync Early |
| * 0b0..Frame sync asserts with the first bit of the frame. |
| * 0b1..Frame sync asserts one bit before the first bit of the frame. |
| */ |
| #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) |
| #define I2S_RCR4_MF_MASK (0x10U) |
| #define I2S_RCR4_MF_SHIFT (4U) |
| /*! MF - MSB First |
| * 0b0..LSB is received first. |
| * 0b1..MSB is received first. |
| */ |
| #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) |
| #define I2S_RCR4_SYWD_MASK (0x1F00U) |
| #define I2S_RCR4_SYWD_SHIFT (8U) |
| #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) |
| #define I2S_RCR4_FRSZ_MASK (0x1F0000U) |
| #define I2S_RCR4_FRSZ_SHIFT (16U) |
| #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) |
| #define I2S_RCR4_FPACK_MASK (0x3000000U) |
| #define I2S_RCR4_FPACK_SHIFT (24U) |
| /*! FPACK - FIFO Packing Mode |
| * 0b00..FIFO packing is disabled |
| * 0b01..Reserved. |
| * 0b10..8-bit FIFO packing is enabled |
| * 0b11..16-bit FIFO packing is enabled |
| */ |
| #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) |
| #define I2S_RCR4_FCOMB_MASK (0xC000000U) |
| #define I2S_RCR4_FCOMB_SHIFT (26U) |
| /*! FCOMB - FIFO Combine Mode |
| * 0b00..FIFO combine mode disabled. |
| * 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers). |
| * 0b10..FIFO combine mode enabled on FIFO reads (by software). |
| * 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). |
| */ |
| #define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) |
| #define I2S_RCR4_FCONT_MASK (0x10000000U) |
| #define I2S_RCR4_FCONT_SHIFT (28U) |
| /*! FCONT - FIFO Continue on Error |
| * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. |
| * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. |
| */ |
| #define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) |
| /*! @} */ |
| |
| /*! @name RCR5 - SAI Receive Configuration 5 Register */ |
| /*! @{ */ |
| #define I2S_RCR5_FBT_MASK (0x1F00U) |
| #define I2S_RCR5_FBT_SHIFT (8U) |
| #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) |
| #define I2S_RCR5_W0W_MASK (0x1F0000U) |
| #define I2S_RCR5_W0W_SHIFT (16U) |
| #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) |
| #define I2S_RCR5_WNW_MASK (0x1F000000U) |
| #define I2S_RCR5_WNW_SHIFT (24U) |
| #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) |
| /*! @} */ |
| |
| /*! @name RDR - SAI Receive Data Register */ |
| /*! @{ */ |
| #define I2S_RDR_RDR_MASK (0xFFFFFFFFU) |
| #define I2S_RDR_RDR_SHIFT (0U) |
| #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) |
| /*! @} */ |
| |
| /* The count of I2S_RDR */ |
| #define I2S_RDR_COUNT (8U) |
| |
| /*! @name RFR - SAI Receive FIFO Register */ |
| /*! @{ */ |
| #define I2S_RFR_RFP_MASK (0xFFU) |
| #define I2S_RFR_RFP_SHIFT (0U) |
| #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) |
| #define I2S_RFR_RCP_MASK (0x8000U) |
| #define I2S_RFR_RCP_SHIFT (15U) |
| /*! RCP - Receive Channel Pointer |
| * 0b0..No effect. |
| * 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. |
| */ |
| #define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) |
| #define I2S_RFR_WFP_MASK (0xFF0000U) |
| #define I2S_RFR_WFP_SHIFT (16U) |
| #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) |
| /*! @} */ |
| |
| /* The count of I2S_RFR */ |
| #define I2S_RFR_COUNT (8U) |
| |
| /*! @name RMR - SAI Receive Mask Register */ |
| /*! @{ */ |
| #define I2S_RMR_RWM_MASK (0xFFFFFFFFU) |
| #define I2S_RMR_RWM_SHIFT (0U) |
| /*! RWM - Receive Word Mask |
| * 0b00000000000000000000000000000000..Word N is enabled. |
| * 0b00000000000000000000000000000001..Word N is masked. |
| */ |
| #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group I2S_Register_Masks */ |
| |
| |
| /* I2S - Peripheral instance base addresses */ |
| /** Peripheral I2S1 base address */ |
| #define I2S1_BASE (0x30010000u) |
| /** Peripheral I2S1 base pointer */ |
| #define I2S1 ((I2S_Type *)I2S1_BASE) |
| /** Peripheral I2S2 base address */ |
| #define I2S2_BASE (0x308B0000u) |
| /** Peripheral I2S2 base pointer */ |
| #define I2S2 ((I2S_Type *)I2S2_BASE) |
| /** Peripheral I2S3 base address */ |
| #define I2S3_BASE (0x308C0000u) |
| /** Peripheral I2S3 base pointer */ |
| #define I2S3 ((I2S_Type *)I2S3_BASE) |
| /** Peripheral I2S4 base address */ |
| #define I2S4_BASE (0x30050000u) |
| /** Peripheral I2S4 base pointer */ |
| #define I2S4 ((I2S_Type *)I2S4_BASE) |
| /** Peripheral I2S5 base address */ |
| #define I2S5_BASE (0x30040000u) |
| /** Peripheral I2S5 base pointer */ |
| #define I2S5 ((I2S_Type *)I2S5_BASE) |
| /** Peripheral I2S6 base address */ |
| #define I2S6_BASE (0x30030000u) |
| /** Peripheral I2S6 base pointer */ |
| #define I2S6 ((I2S_Type *)I2S6_BASE) |
| /** Array initializer of I2S peripheral base addresses */ |
| #define I2S_BASE_ADDRS { 0u, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE } |
| /** Array initializer of I2S peripheral base pointers */ |
| #define I2S_BASE_PTRS { (I2S_Type *)0u, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6 } |
| /** Interrupt vectors for the I2S peripheral type */ |
| #define I2S_RX_IRQS { NotAvail_IRQn, I2S1_IRQn, I2S2_IRQn, I2S3_IRQn, I2S4_IRQn, I2S56_IRQn, I2S56_IRQn } |
| #define I2S_TX_IRQS { NotAvail_IRQn, I2S1_IRQn, I2S2_IRQn, I2S3_IRQn, I2S4_IRQn, I2S56_IRQn, I2S56_IRQn } |
| |
| /*! |
| * @} |
| */ /* end of group I2S_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- IOMUXC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** IOMUXC - Register Layout Typedef */ |
| typedef struct { |
| uint8_t RESERVED_0[20]; |
| __IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ; /**< SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register, offset: 0x14 */ |
| __IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ; /**< SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register, offset: 0x18 */ |
| __IO uint32_t SW_MUX_CTL_PAD_ONOFF; /**< SW_MUX_CTL_PAD_ONOFF SW MUX Control Register, offset: 0x1C */ |
| __IO uint32_t SW_MUX_CTL_PAD_POR_B; /**< SW_MUX_CTL_PAD_POR_B SW MUX Control Register, offset: 0x20 */ |
| __IO uint32_t SW_MUX_CTL_PAD_RTC_RESET_B; /**< SW_MUX_CTL_PAD_RTC_RESET_B SW MUX Control Register, offset: 0x24 */ |
| __IO uint32_t SW_MUX_CTL_PAD[139]; /**< SW_MUX_CTL_PAD_GPIO1_IO00 SW MUX Control Register..SW_MUX_CTL_PAD_UART4_TXD SW MUX Control Register, array offset: 0x28, array step: 0x4 */ |
| __IO uint32_t SW_PAD_CTL_PAD[154]; /**< SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register..SW_PAD_CTL_PAD_UART4_TXD SW PAD Control Register, array offset: 0x254, array step: 0x4 */ |
| __IO uint32_t SELECT_INPUT[30]; /**< CCM_PMIC_READY_SELECT_INPUT DAISY Register..SAI6_MCLK_SELECT_INPUT DAISY Register, array offset: 0x4BC, array step: 0x4 */ |
| } IOMUXC_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- IOMUXC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks |
| * @{ |
| */ |
| |
| /*! @name SW_MUX_CTL_PAD_PMIC_STBY_REQ - SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */ |
| /*! @{ */ |
| #define IOMUXC_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x40U) |
| #define IOMUXC_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (6U) |
| /*! SION - Software Input On Field |
| * 0b0..Input Path of pad PMIC_STBY_REQ is determined by functionality |
| * 0b1..Force Input Path of pad PMIC_STBY_REQ |
| */ |
| #define IOMUXC_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK) |
| /*! @} */ |
| |
| /*! @name SW_MUX_CTL_PAD_PMIC_ON_REQ - SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */ |
| /*! @{ */ |
| #define IOMUXC_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x40U) |
| #define IOMUXC_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (6U) |
| /*! SION - Software Input On Field |
| * 0b0..Input Path of pad PMIC_ON_REQ is determined by functionality |
| * 0b1..Force Input Path of pad PMIC_ON_REQ |
| */ |
| #define IOMUXC_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK) |
| /*! @} */ |
| |
| /*! @name SW_MUX_CTL_PAD_ONOFF - SW_MUX_CTL_PAD_ONOFF SW MUX Control Register */ |
| /*! @{ */ |
| #define IOMUXC_SW_MUX_CTL_PAD_ONOFF_SION_MASK (0x40U) |
| #define IOMUXC_SW_MUX_CTL_PAD_ONOFF_SION_SHIFT (6U) |
| /*! SION - Software Input On Field |
| * 0b0..Input Path of pad ONOFF is determined by functionality |
| * 0b1..Force Input Path of pad ONOFF |
| */ |
| #define IOMUXC_SW_MUX_CTL_PAD_ONOFF_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_ONOFF_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_ONOFF_SION_MASK) |
| /*! @} */ |
| |
| /*! @name SW_MUX_CTL_PAD_POR_B - SW_MUX_CTL_PAD_POR_B SW MUX Control Register */ |
| /*! @{ */ |
| #define IOMUXC_SW_MUX_CTL_PAD_POR_B_SION_MASK (0x40U) |
| #define IOMUXC_SW_MUX_CTL_PAD_POR_B_SION_SHIFT (6U) |
| /*! SION - Software Input On Field |
| * 0b0..Input Path of pad POR_B is determined by functionality |
| * 0b1..Force Input Path of pad POR_B |
| */ |
| #define IOMUXC_SW_MUX_CTL_PAD_POR_B_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_POR_B_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_POR_B_SION_MASK) |
| /*! @} */ |
| |
| /*! @name SW_MUX_CTL_PAD_RTC_RESET_B - SW_MUX_CTL_PAD_RTC_RESET_B SW MUX Control Register */ |
| /*! @{ */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RTC_RESET_B_SION_MASK (0x40U) |
| #define IOMUXC_SW_MUX_CTL_PAD_RTC_RESET_B_SION_SHIFT (6U) |
| /*! SION - Software Input On Field |
| * 0b0..Input Path of pad RTC_RESET_B is determined by functionality |
| * 0b1..Force Input Path of pad RTC_RESET_B |
| */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RTC_RESET_B_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_RTC_RESET_B_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_RTC_RESET_B_SION_MASK) |
| /*! @} */ |
| |
| /*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO1_IO00 SW MUX Control Register..SW_MUX_CTL_PAD_UART4_TXD SW MUX Control Register */ |
| /*! @{ */ |
| #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U) |
| #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) |
| /*! MUX_MODE - MUX Mode Select Field |
| * 0b000..Select mux mode: ALT0 mux port: RX_DATA5 of instance: SAI1 |
| * 0b001..Select mux mode: ALT1 mux port: TX_DATA0 of instance: SAI6 |
| * 0b010..Select mux mode: ALT2 mux port: RX_DATA0 of instance: SAI6 |
| * 0b011..Select mux mode: ALT3 mux port: RX_SYNC of instance: SAI1 |
| * 0b100..Select mux mode: ALT4 mux port: TRACE5 of instance: CORESIGHT |
| * 0b101..Select mux mode: ALT5 mux port: IO07 of instance: GPIO4 |
| * 0b110..Select mux mode: ALT6 mux port: BOOT_CFG5 of instance: SRC |
| */ |
| #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) |
| #define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) |
| /*! SION - Software Input On Field |
| * 0b0..Input Path of pad SPDIF_EXT_CLK is determined by functionality |
| * 0b1..Force Input Path of pad SPDIF_EXT_CLK |
| */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) |
| /*! @} */ |
| |
| /* The count of IOMUXC_SW_MUX_CTL_PAD */ |
| #define IOMUXC_SW_MUX_CTL_PAD_COUNT (139U) |
| |
| /*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register..SW_PAD_CTL_PAD_UART4_TXD SW PAD Control Register */ |
| /*! @{ */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x7U) |
| #define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (0U) |
| /*! DSE - Drive Strength Field |
| * 0b000..HI-Z |
| * 0b001..255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V |
| * 0b010..105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V |
| * 0b011..75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V |
| * 0b100..85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V |
| * 0b101..65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V |
| * 0b110..45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V |
| * 0b111..40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V |
| */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x18U) |
| #define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (3U) |
| /*! SRE - Slew Rate Field |
| * 0b00..Slow Frequency Slew Rate (50Mhz) |
| * 0b01..Medium Frequency Slew Rate (100Mhz) |
| * 0b10..Fast Frequency Slew Rate (150Mhz) |
| * 0b11..Max Frequency Slew Rate (200Mhz) |
| */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x20U) |
| #define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (5U) |
| /*! ODE - Open Drain Enable Field |
| * 0b0..Open Drain Disabled |
| * 0b1..Open Drain Enabled |
| */ |
| #define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x40U) |
| #define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (6U) |
| /*! PUE - Pull Up Enable Field |
| * 0b0..Pull Up Resistor Disabled |
| * 0b1..Pull Up Resistor Enabled |
| */ |
| #define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x80U) |
| #define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (7U) |
| /*! HYS - Schmitt trigger Enable Field |
| * 0b0..Schmitt Trigger Disabled |
| * 0b1..Schmitt Trigger Enabled |
| */ |
| #define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LVTTL_MASK (0x100U) |
| #define IOMUXC_SW_PAD_CTL_PAD_LVTTL_SHIFT (8U) |
| /*! LVTTL - Lvttl Enable Field |
| * 0b0..LVTTL Disabled |
| * 0b1..LVTTL Enabled |
| */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LVTTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_LVTTL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_LVTTL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_VSEL_MASK (0x3800U) |
| #define IOMUXC_SW_PAD_CTL_PAD_VSEL_SHIFT (11U) |
| /*! VSEL - Voltage Select Field |
| * 0b000..Auto Detect 3.3/2.5/1.2/1.8 V mode |
| * 0b001..Auto Detect 3.3/2.5/1.2/1.8 V mode |
| * 0b010..Auto Detect 3.3/2.5/1.2/1.8 V mode |
| * 0b011..Auto Detect 3.3/2.5/1.2/1.8 V mode |
| * 0b100..Manually Set 3.3V mode |
| * 0b101..Manually Set 2.5V mode |
| * 0b110..Manually Set 2.5V mode |
| * 0b111..Manually Set 1.2V/1.8V mode |
| */ |
| #define IOMUXC_SW_PAD_CTL_PAD_VSEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_VSEL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_VSEL_MASK) |
| /*! @} */ |
| |
| /* The count of IOMUXC_SW_PAD_CTL_PAD */ |
| #define IOMUXC_SW_PAD_CTL_PAD_COUNT (154U) |
| |
| /*! @name SELECT_INPUT - CCM_PMIC_READY_SELECT_INPUT DAISY Register..SAI6_MCLK_SELECT_INPUT DAISY Register */ |
| /*! @{ */ |
| #define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ |
| #define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U) |
| /*! DAISY - Input Select (DAISY) Field |
| * 0b000..Selecting Pad: SAI5_RXD1 Mode: ALT2 for SAI1_TX_SYNC |
| * 0b001..Selecting Pad: SAI5_RXD2 Mode: ALT2 for SAI1_TX_SYNC |
| * 0b010..Selecting Pad: SAI5_RXD3 Mode: ALT2 for SAI1_TX_SYNC |
| * 0b011..Selecting Pad: SAI1_TXFS Mode: ALT0 for SAI1_TX_SYNC |
| * 0b100..Selecting Pad: SAI1_RXD7 Mode: ALT2 for SAI1_TX_SYNC |
| */ |
| #define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ |
| /*! @} */ |
| |
| /* The count of IOMUXC_SELECT_INPUT */ |
| #define IOMUXC_SELECT_INPUT_COUNT (30U) |
| |
| |
| /*! |
| * @} |
| */ /* end of group IOMUXC_Register_Masks */ |
| |
| |
| /* IOMUXC - Peripheral instance base addresses */ |
| /** Peripheral IOMUXC base address */ |
| #define IOMUXC_BASE (0x30330000u) |
| /** Peripheral IOMUXC base pointer */ |
| #define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE) |
| /** Array initializer of IOMUXC peripheral base addresses */ |
| #define IOMUXC_BASE_ADDRS { IOMUXC_BASE } |
| /** Array initializer of IOMUXC peripheral base pointers */ |
| #define IOMUXC_BASE_PTRS { IOMUXC } |
| |
| /*! |
| * @} |
| */ /* end of group IOMUXC_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- IOMUXC_GPR Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** IOMUXC_GPR - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t GPR[48]; /**< GPR0 General Purpose Register..GPR47 General Purpose Register, array offset: 0x0, array step: 0x4 */ |
| } IOMUXC_GPR_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- IOMUXC_GPR Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks |
| * @{ |
| */ |
| |
| /*! @name GPR - GPR0 General Purpose Register..GPR47 General Purpose Register */ |
| /*! @{ */ |
| #define IOMUXC_GPR_GPR_ARCACHE_USDHC_MASK (0x1U) |
| #define IOMUXC_GPR_GPR_ARCACHE_USDHC_SHIFT (0U) |
| /*! ARCACHE_USDHC |
| * 0b0..Drive USDHC AXI Master ARCACHE[1] to 0 |
| * 0b1..Drive USDHC AXI Master ARCACHE[1] to 1 |
| */ |
| #define IOMUXC_GPR_GPR_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR_ARCACHE_USDHC_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_BYTE_CNT_MASK (0x3FFU) |
| #define IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_BYTE_CNT_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_BYTE_CNT_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_BYTE_CNT_MASK (0x3FFU) |
| #define IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_BYTE_CNT_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_BYTE_CNT_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_BYTE_CNT_MASK (0x3FFU) |
| #define IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_BYTE_CNT_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_BYTE_CNT_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_BYTE_CNT_MASK (0x3FFU) |
| #define IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_BYTE_CNT_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_BYTE_CNT_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_ECC_TWO_BIT_ERROR_MASK (0x1U) |
| #define IOMUXC_GPR_GPR_CSI2_1_ECC_TWO_BIT_ERROR_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_CSI2_1_ECC_TWO_BIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ECC_TWO_BIT_ERROR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ECC_TWO_BIT_ERROR_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_RX_RCAL_MASK (0x3U) |
| #define IOMUXC_GPR_GPR_CSI2_1_RX_RCAL_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_CSI2_1_RX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_RX_RCAL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_RX_RCAL_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_TEST_PATTERN_MASK (0xFFFFFFFFU) |
| #define IOMUXC_GPR_GPR_CSI2_1_TEST_PATTERN_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_CSI2_1_TEST_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_TEST_PATTERN_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_TEST_PATTERN_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_BYTE_CNT_MASK (0x3FFU) |
| #define IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_BYTE_CNT_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_BYTE_CNT_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_BYTE_CNT_MASK (0x3FFU) |
| #define IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_BYTE_CNT_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_BYTE_CNT_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_BYTE_CNT_MASK (0x3FFU) |
| #define IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_BYTE_CNT_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_BYTE_CNT_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_BYTE_CNT_MASK (0x3FFU) |
| #define IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_BYTE_CNT_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_BYTE_CNT_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_ECC_TWO_BIT_ERROR_MASK (0x1U) |
| #define IOMUXC_GPR_GPR_CSI2_2_ECC_TWO_BIT_ERROR_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_CSI2_2_ECC_TWO_BIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ECC_TWO_BIT_ERROR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ECC_TWO_BIT_ERROR_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_RX_RCAL_MASK (0x3U) |
| #define IOMUXC_GPR_GPR_CSI2_2_RX_RCAL_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_CSI2_2_RX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_RX_RCAL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_RX_RCAL_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_TEST_PATTERN_MASK (0xFFFFFFFFU) |
| #define IOMUXC_GPR_GPR_CSI2_2_TEST_PATTERN_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_CSI2_2_TEST_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_TEST_PATTERN_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_TEST_PATTERN_MASK) |
| #define IOMUXC_GPR_GPR_DSI_D0_INT_LB_BYTE_CNT_MASK (0x3FFU) |
| #define IOMUXC_GPR_GPR_DSI_D0_INT_LB_BYTE_CNT_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_DSI_D0_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D0_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D0_INT_LB_BYTE_CNT_MASK) |
| #define IOMUXC_GPR_GPR_DSI_D1_INT_LB_BYTE_CNT_MASK (0x3FFU) |
| #define IOMUXC_GPR_GPR_DSI_D1_INT_LB_BYTE_CNT_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_DSI_D1_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D1_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D1_INT_LB_BYTE_CNT_MASK) |
| #define IOMUXC_GPR_GPR_DSI_D2_INT_LB_BYTE_CNT_MASK (0x3FFU) |
| #define IOMUXC_GPR_GPR_DSI_D2_INT_LB_BYTE_CNT_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_DSI_D2_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D2_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D2_INT_LB_BYTE_CNT_MASK) |
| #define IOMUXC_GPR_GPR_DSI_D3_INT_LB_BYTE_CNT_MASK (0x3FFU) |
| #define IOMUXC_GPR_GPR_DSI_D3_INT_LB_BYTE_CNT_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_DSI_D3_INT_LB_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D3_INT_LB_BYTE_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D3_INT_LB_BYTE_CNT_MASK) |
| #define IOMUXC_GPR_GPR_DSI_RX_RCAL_MASK (0x3U) |
| #define IOMUXC_GPR_GPR_DSI_RX_RCAL_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_DSI_RX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_RX_RCAL_SHIFT)) & IOMUXC_GPR_GPR_DSI_RX_RCAL_MASK) |
| #define IOMUXC_GPR_GPR_DSI_TEST_PATTERN_MASK (0xFFFFFFFFU) |
| #define IOMUXC_GPR_GPR_DSI_TEST_PATTERN_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_DSI_TEST_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_TEST_PATTERN_SHIFT)) & IOMUXC_GPR_GPR_DSI_TEST_PATTERN_MASK) |
| #define IOMUXC_GPR_GPR_DSI_TWO_BIT_ERR_MASK (0x1U) |
| #define IOMUXC_GPR_GPR_DSI_TWO_BIT_ERR_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_DSI_TWO_BIT_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_TWO_BIT_ERR_SHIFT)) & IOMUXC_GPR_GPR_DSI_TWO_BIT_ERR_MASK) |
| #define IOMUXC_GPR_GPR_DSI_UI_STATUS0_RO_MASK (0xFFFFFFFFU) |
| #define IOMUXC_GPR_GPR_DSI_UI_STATUS0_RO_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_DSI_UI_STATUS0_RO(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_UI_STATUS0_RO_SHIFT)) & IOMUXC_GPR_GPR_DSI_UI_STATUS0_RO_MASK) |
| #define IOMUXC_GPR_GPR_DSI_UI_STATUS1_RO_MASK (0xFFFFFFFFU) |
| #define IOMUXC_GPR_GPR_DSI_UI_STATUS1_RO_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_DSI_UI_STATUS1_RO(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_UI_STATUS1_RO_SHIFT)) & IOMUXC_GPR_GPR_DSI_UI_STATUS1_RO_MASK) |
| #define IOMUXC_GPR_GPR_DSI_UI_STATUS2_RO_MASK (0xFFFFFFFFU) |
| #define IOMUXC_GPR_GPR_DSI_UI_STATUS2_RO_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_DSI_UI_STATUS2_RO(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_UI_STATUS2_RO_SHIFT)) & IOMUXC_GPR_GPR_DSI_UI_STATUS2_RO_MASK) |
| #define IOMUXC_GPR_GPR_DSI_UI_STATUS3_RO_MASK (0x3FFFFFFFU) |
| #define IOMUXC_GPR_GPR_DSI_UI_STATUS3_RO_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_DSI_UI_STATUS3_RO(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_UI_STATUS3_RO_SHIFT)) & IOMUXC_GPR_GPR_DSI_UI_STATUS3_RO_MASK) |
| #define IOMUXC_GPR_GPR_GPR_SAI1_EXT_MCLK_EN_MASK (0x1U) |
| #define IOMUXC_GPR_GPR_GPR_SAI1_EXT_MCLK_EN_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_GPR_SAI1_EXT_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_GPR_SAI1_EXT_MCLK_EN_SHIFT)) & IOMUXC_GPR_GPR_GPR_SAI1_EXT_MCLK_EN_MASK) |
| #define IOMUXC_GPR_GPR_HDMI_HPD_PD_MASK (0x1U) |
| #define IOMUXC_GPR_GPR_HDMI_HPD_PD_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_HDMI_HPD_PD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_HDMI_HPD_PD_SHIFT)) & IOMUXC_GPR_GPR_HDMI_HPD_PD_MASK) |
| #define IOMUXC_GPR_GPR_OCRAM_TZ_EN_MASK (0x1U) |
| #define IOMUXC_GPR_GPR_OCRAM_TZ_EN_SHIFT (0U) |
| /*! OCRAM_TZ_EN |
| * 0b0..The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor). |
| * 0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter. |
| */ |
| #define IOMUXC_GPR_GPR_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_TZ_EN_MASK) |
| #define IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_LOW_MASK (0x7FU) |
| #define IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_LOW_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_LOW_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_LOW_MASK) |
| #define IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_LOW_MASK (0x7FU) |
| #define IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_LOW_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_LOW_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_LOW_MASK) |
| #define IOMUXC_GPR_GPR_PCIE_DIAG_STATUS_MASK (0xFFFFFFFFU) |
| #define IOMUXC_GPR_GPR_PCIE_DIAG_STATUS_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_PCIE_DIAG_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE_DIAG_STATUS_SHIFT)) & IOMUXC_GPR_GPR_PCIE_DIAG_STATUS_MASK) |
| #define IOMUXC_GPR_GPR_RDATA_WAIT_EN_MASK (0x1U) |
| #define IOMUXC_GPR_GPR_RDATA_WAIT_EN_SHIFT (0U) |
| /*! RDATA_WAIT_EN |
| * 0b0..read data wait state disabled |
| * 0b1..read data wait state enabled |
| */ |
| #define IOMUXC_GPR_GPR_RDATA_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_RDATA_WAIT_EN_SHIFT)) & IOMUXC_GPR_GPR_RDATA_WAIT_EN_MASK) |
| #define IOMUXC_GPR_GPR_SDMA1_IPG_STOP_MASK (0x1U) |
| #define IOMUXC_GPR_GPR_SDMA1_IPG_STOP_SHIFT (0U) |
| /*! SDMA1_IPG_STOP |
| * 0b0..stop request off |
| * 0b1..stop request on |
| */ |
| #define IOMUXC_GPR_GPR_SDMA1_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SDMA1_IPG_STOP_SHIFT)) & IOMUXC_GPR_GPR_SDMA1_IPG_STOP_MASK) |
| #define IOMUXC_GPR_GPR_TZASC_EN_MASK (0x1U) |
| #define IOMUXC_GPR_GPR_TZASC_EN_SHIFT (0U) |
| #define IOMUXC_GPR_GPR_TZASC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_TZASC_EN_SHIFT)) & IOMUXC_GPR_GPR_TZASC_EN_MASK) |
| #define IOMUXC_GPR_GPR_AWCACHE_USDHC_MASK (0x2U) |
| #define IOMUXC_GPR_GPR_AWCACHE_USDHC_SHIFT (1U) |
| /*! AWCACHE_USDHC |
| * 0b0..Drive USDHC AXI Master AWCACHE[1] to 0 |
| * 0b1..Drive USDHC AXI Master AWCACHE[1] to 1 |
| */ |
| #define IOMUXC_GPR_GPR_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR_AWCACHE_USDHC_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERR_POS_MASK (0x3EU) |
| #define IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERR_POS_SHIFT (1U) |
| #define IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERR_POS_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERR_POS_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERR_POS_MASK (0x3EU) |
| #define IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERR_POS_SHIFT (1U) |
| #define IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERR_POS_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERR_POS_MASK) |
| #define IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_POS_MASK (0x3EU) |
| #define IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_POS_SHIFT (1U) |
| #define IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_POS_SHIFT)) & IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_POS_MASK) |
| #define IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL0_MASK (0x2U) |
| #define IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL0_SHIFT (1U) |
| /*! ENET1_IPD_REQ_TIMER_SEL0 |
| * 0b0..Select ipd_req_mac0_timer2 to SDMA IRQ 45 |
| * 0b1..Select ipd_req_mac0_timer0 to SDMA IRQ 45 |
| */ |
| #define IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL0_SHIFT)) & IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL0_MASK) |
| #define IOMUXC_GPR_GPR_GPR_SAI2_EXT_MCLK_EN_MASK (0x2U) |
| #define IOMUXC_GPR_GPR_GPR_SAI2_EXT_MCLK_EN_SHIFT (1U) |
| #define IOMUXC_GPR_GPR_GPR_SAI2_EXT_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_GPR_SAI2_EXT_MCLK_EN_SHIFT)) & IOMUXC_GPR_GPR_GPR_SAI2_EXT_MCLK_EN_MASK) |
| #define IOMUXC_GPR_GPR_HDMI_DDC_SDA_PD_MASK (0x2U) |
| #define IOMUXC_GPR_GPR_HDMI_DDC_SDA_PD_SHIFT (1U) |
| #define IOMUXC_GPR_GPR_HDMI_DDC_SDA_PD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_HDMI_DDC_SDA_PD_SHIFT)) & IOMUXC_GPR_GPR_HDMI_DDC_SDA_PD_MASK) |
| #define IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_MASK (0x3EU) |
| #define IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_SHIFT (1U) |
| #define IOMUXC_GPR_GPR_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_MASK) |
| #define IOMUXC_GPR_GPR_RADDR_PIPE_EN_MASK (0x2U) |
| #define IOMUXC_GPR_GPR_RADDR_PIPE_EN_SHIFT (1U) |
| /*! RADDR_PIPE_EN |
| * 0b0..read address pipeline is disabled |
| * 0b1..read address pipeline is enabled |
| */ |
| #define IOMUXC_GPR_GPR_RADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_RADDR_PIPE_EN_SHIFT)) & IOMUXC_GPR_GPR_RADDR_PIPE_EN_MASK) |
| #define IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_MASK (0x2U) |
| #define IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_SHIFT (1U) |
| #define IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_SHIFT)) & IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_S_PRG_RXHS_SETTLE_MASK (0xFCU) |
| #define IOMUXC_GPR_GPR_CSI2_1_S_PRG_RXHS_SETTLE_SHIFT (2U) |
| #define IOMUXC_GPR_GPR_CSI2_1_S_PRG_RXHS_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_S_PRG_RXHS_SETTLE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_S_PRG_RXHS_SETTLE_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_S_PRG_RXHS_SETTLE_MASK (0xFCU) |
| #define IOMUXC_GPR_GPR_CSI2_2_S_PRG_RXHS_SETTLE_SHIFT (2U) |
| #define IOMUXC_GPR_GPR_CSI2_2_S_PRG_RXHS_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_S_PRG_RXHS_SETTLE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_S_PRG_RXHS_SETTLE_MASK) |
| #define IOMUXC_GPR_GPR_DSI_RTERM_SEL_MASK (0x4U) |
| #define IOMUXC_GPR_GPR_DSI_RTERM_SEL_SHIFT (2U) |
| #define IOMUXC_GPR_GPR_DSI_RTERM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_RTERM_SEL_SHIFT)) & IOMUXC_GPR_GPR_DSI_RTERM_SEL_MASK) |
| #define IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL1_MASK (0x4U) |
| #define IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL1_SHIFT (2U) |
| /*! ENET1_IPD_REQ_TIMER_SEL1 |
| * 0b0..Select ipd_req_mac0_timer3 to SDMA IRQ 47 |
| * 0b1..Select ipd_req_mac0_timer1 to SDMA IRQ 47 |
| */ |
| #define IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL1_SHIFT)) & IOMUXC_GPR_GPR_ENET1_IPD_REQ_TIMER_SEL1_MASK) |
| #define IOMUXC_GPR_GPR_GPR_SAI3_EXT_MCLK_EN_MASK (0x4U) |
| #define IOMUXC_GPR_GPR_GPR_SAI3_EXT_MCLK_EN_SHIFT (2U) |
| #define IOMUXC_GPR_GPR_GPR_SAI3_EXT_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_GPR_SAI3_EXT_MCLK_EN_SHIFT)) & IOMUXC_GPR_GPR_GPR_SAI3_EXT_MCLK_EN_MASK) |
| #define IOMUXC_GPR_GPR_HDMI_DDC_SCL_PD_MASK (0x4U) |
| #define IOMUXC_GPR_GPR_HDMI_DDC_SCL_PD_SHIFT (2U) |
| #define IOMUXC_GPR_GPR_HDMI_DDC_SCL_PD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_HDMI_DDC_SCL_PD_SHIFT)) & IOMUXC_GPR_GPR_HDMI_DDC_SCL_PD_MASK) |
| #define IOMUXC_GPR_GPR_MIPI_MUX_SEL_MASK (0x4U) |
| #define IOMUXC_GPR_GPR_MIPI_MUX_SEL_SHIFT (2U) |
| #define IOMUXC_GPR_GPR_MIPI_MUX_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_MIPI_MUX_SEL_SHIFT)) & IOMUXC_GPR_GPR_MIPI_MUX_SEL_MASK) |
| #define IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_MASK (0x4U) |
| #define IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_SHIFT (2U) |
| /*! SEC_ERR_RESP_EN |
| * 0b0..OKAY response |
| * 0b1..SLVERR response |
| */ |
| #define IOMUXC_GPR_GPR_SEC_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_SHIFT)) & IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_MASK) |
| #define IOMUXC_GPR_GPR_WDATA_PIPE_EN_MASK (0x4U) |
| #define IOMUXC_GPR_GPR_WDATA_PIPE_EN_SHIFT (2U) |
| /*! WDATA_PIPE_EN |
| * 0b0..write data pipeline is disabled |
| * 0b1..write data pipeline is enabled |
| */ |
| #define IOMUXC_GPR_GPR_WDATA_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_WDATA_PIPE_EN_SHIFT)) & IOMUXC_GPR_GPR_WDATA_PIPE_EN_MASK) |
| #define IOMUXC_GPR_GPR_DSI_RCALT_MASK (0x18U) |
| #define IOMUXC_GPR_GPR_DSI_RCALT_SHIFT (3U) |
| #define IOMUXC_GPR_GPR_DSI_RCALT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_RCALT_SHIFT)) & IOMUXC_GPR_GPR_DSI_RCALT_MASK) |
| #define IOMUXC_GPR_GPR_ENET1_IPG_STOP_MASK (0x8U) |
| #define IOMUXC_GPR_GPR_ENET1_IPG_STOP_SHIFT (3U) |
| /*! ENET1_IPG_STOP |
| * 0b0..stop request off |
| * 0b1..stop request on |
| */ |
| #define IOMUXC_GPR_GPR_ENET1_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ENET1_IPG_STOP_SHIFT)) & IOMUXC_GPR_GPR_ENET1_IPG_STOP_MASK) |
| #define IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_MASK (0x8U) |
| #define IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_SHIFT (3U) |
| /*! EXC_ERR_RESP_EN |
| * 0b0..OK response on the AXI for an exclusive access error |
| * 0b1..ERR response on the AXI for an exclusive access error |
| */ |
| #define IOMUXC_GPR_GPR_EXC_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_SHIFT)) & IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_MASK) |
| #define IOMUXC_GPR_GPR_GPR_SAI4_EXT_MCLK_EN_MASK (0x8U) |
| #define IOMUXC_GPR_GPR_GPR_SAI4_EXT_MCLK_EN_SHIFT (3U) |
| #define IOMUXC_GPR_GPR_GPR_SAI4_EXT_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_GPR_SAI4_EXT_MCLK_EN_SHIFT)) & IOMUXC_GPR_GPR_GPR_SAI4_EXT_MCLK_EN_MASK) |
| #define IOMUXC_GPR_GPR_HDMI_CEC_PD_MASK (0x8U) |
| #define IOMUXC_GPR_GPR_HDMI_CEC_PD_SHIFT (3U) |
| #define IOMUXC_GPR_GPR_HDMI_CEC_PD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_HDMI_CEC_PD_SHIFT)) & IOMUXC_GPR_GPR_HDMI_CEC_PD_MASK) |
| #define IOMUXC_GPR_GPR_MIPI_MUX_INV_MASK (0x8U) |
| #define IOMUXC_GPR_GPR_MIPI_MUX_INV_SHIFT (3U) |
| #define IOMUXC_GPR_GPR_MIPI_MUX_INV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_MIPI_MUX_INV_SHIFT)) & IOMUXC_GPR_GPR_MIPI_MUX_INV_MASK) |
| #define IOMUXC_GPR_GPR_WADDR_PIPE_EN_MASK (0x8U) |
| #define IOMUXC_GPR_GPR_WADDR_PIPE_EN_SHIFT (3U) |
| /*! WADDR_PIPE_EN |
| * 0b0..write address pipeline is disabled |
| * 0b1..write address pipeline is enabled |
| */ |
| #define IOMUXC_GPR_GPR_WADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_WADDR_PIPE_EN_SHIFT)) & IOMUXC_GPR_GPR_WADDR_PIPE_EN_MASK) |
| #define IOMUXC_GPR_GPR_ARCACHE_PCIE1_MASK (0x10U) |
| #define IOMUXC_GPR_GPR_ARCACHE_PCIE1_SHIFT (4U) |
| /*! ARCACHE_PCIE1 |
| * 0b0..Drive PCIe AXI Master Port ARCACHE[1] to 0 |
| * 0b1..Drive PCIe AXI Master Port ARCACHE[1] to 1 |
| */ |
| #define IOMUXC_GPR_GPR_ARCACHE_PCIE1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ARCACHE_PCIE1_SHIFT)) & IOMUXC_GPR_GPR_ARCACHE_PCIE1_MASK) |
| #define IOMUXC_GPR_GPR_GPR_SAI5_EXT_MCLK_EN_MASK (0x10U) |
| #define IOMUXC_GPR_GPR_GPR_SAI5_EXT_MCLK_EN_SHIFT (4U) |
| #define IOMUXC_GPR_GPR_GPR_SAI5_EXT_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_GPR_SAI5_EXT_MCLK_EN_SHIFT)) & IOMUXC_GPR_GPR_GPR_SAI5_EXT_MCLK_EN_MASK) |
| #define IOMUXC_GPR_GPR_SDMA2_IPG_STOP_MASK (0x10U) |
| #define IOMUXC_GPR_GPR_SDMA2_IPG_STOP_SHIFT (4U) |
| /*! SDMA2_IPG_STOP |
| * 0b0..stop request off |
| * 0b1..stop request on |
| */ |
| #define IOMUXC_GPR_GPR_SDMA2_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SDMA2_IPG_STOP_SHIFT)) & IOMUXC_GPR_GPR_SDMA2_IPG_STOP_MASK) |
| #define IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_MASK (0x10U) |
| #define IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_SHIFT (4U) |
| #define IOMUXC_GPR_GPR_S_RDATA_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_SHIFT)) & IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_MASK) |
| #define IOMUXC_GPR_GPR_AWCACHE_PCIE1_MASK (0x20U) |
| #define IOMUXC_GPR_GPR_AWCACHE_PCIE1_SHIFT (5U) |
| /*! AWCACHE_PCIE1 |
| * 0b0..Drive PCIe AXI Master Port AWCACHE[1] to 0 |
| * 0b1..Drive PCIe AXI Master Port AWCACHE[1] to 1 |
| */ |
| #define IOMUXC_GPR_GPR_AWCACHE_PCIE1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_AWCACHE_PCIE1_SHIFT)) & IOMUXC_GPR_GPR_AWCACHE_PCIE1_MASK) |
| #define IOMUXC_GPR_GPR_DSI_NOCAL_MASK (0x20U) |
| #define IOMUXC_GPR_GPR_DSI_NOCAL_SHIFT (5U) |
| #define IOMUXC_GPR_GPR_DSI_NOCAL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_NOCAL_SHIFT)) & IOMUXC_GPR_GPR_DSI_NOCAL_MASK) |
| #define IOMUXC_GPR_GPR_GPR_SAI6_EXT_MCLK_EN_MASK (0x20U) |
| #define IOMUXC_GPR_GPR_GPR_SAI6_EXT_MCLK_EN_SHIFT (5U) |
| #define IOMUXC_GPR_GPR_GPR_SAI6_EXT_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_GPR_SAI6_EXT_MCLK_EN_SHIFT)) & IOMUXC_GPR_GPR_GPR_SAI6_EXT_MCLK_EN_MASK) |
| #define IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_MASK (0x20U) |
| #define IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_SHIFT (5U) |
| #define IOMUXC_GPR_GPR_S_RADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_SHIFT)) & IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_MASK) |
| #define IOMUXC_GPR_GPR_ARCACHE_LCDIF_MASK (0x40U) |
| #define IOMUXC_GPR_GPR_ARCACHE_LCDIF_SHIFT (6U) |
| /*! ARCACHE_LCDIF |
| * 0b0..Drive LCDIF AXI Master Port ARCACHE[1] to 0 |
| * 0b1..Drive LCDIF AXI Master Port ARCACHE[1] to 1 |
| */ |
| #define IOMUXC_GPR_GPR_ARCACHE_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ARCACHE_LCDIF_SHIFT)) & IOMUXC_GPR_GPR_ARCACHE_LCDIF_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERROR_MASK (0x40U) |
| #define IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERROR_SHIFT (6U) |
| #define IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERROR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ECC_ONE_BIT_ERROR_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERROR_MASK (0x40U) |
| #define IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERROR_SHIFT (6U) |
| #define IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERROR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ECC_ONE_BIT_ERROR_MASK) |
| #define IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_MASK (0x40U) |
| #define IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_SHIFT (6U) |
| #define IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_SHIFT)) & IOMUXC_GPR_GPR_DSI_ECC_ONE_BIT_ERR_MASK) |
| #define IOMUXC_GPR_GPR_DSI_HSEL_MASK (0x40U) |
| #define IOMUXC_GPR_GPR_DSI_HSEL_SHIFT (6U) |
| #define IOMUXC_GPR_GPR_DSI_HSEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_HSEL_SHIFT)) & IOMUXC_GPR_GPR_DSI_HSEL_MASK) |
| #define IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_MASK (0x40U) |
| #define IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_SHIFT (6U) |
| #define IOMUXC_GPR_GPR_S_WDATA_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_SHIFT)) & IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_MASK) |
| #define IOMUXC_GPR_GPR_WDOG1_MASK_MASK (0x40U) |
| #define IOMUXC_GPR_GPR_WDOG1_MASK_SHIFT (6U) |
| /*! WDOG1_MASK |
| * 0b0..WDOG1 Timeout behaves normally |
| * 0b1..WDOG1 Timeout is masked |
| */ |
| #define IOMUXC_GPR_GPR_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR_WDOG1_MASK_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_POS_MASK (0x380U) |
| #define IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_POS_SHIFT (7U) |
| #define IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_POS_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_POS_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_POS_MASK (0x380U) |
| #define IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_POS_SHIFT (7U) |
| #define IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_POS_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_POS_MASK) |
| #define IOMUXC_GPR_GPR_DSI_ECC_ERR_POS_MASK (0x380U) |
| #define IOMUXC_GPR_GPR_DSI_ECC_ERR_POS_SHIFT (7U) |
| #define IOMUXC_GPR_GPR_DSI_ECC_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_ECC_ERR_POS_SHIFT)) & IOMUXC_GPR_GPR_DSI_ECC_ERR_POS_MASK) |
| #define IOMUXC_GPR_GPR_DSI_TX_ULPS_ENABLE_MASK (0xF80U) |
| #define IOMUXC_GPR_GPR_DSI_TX_ULPS_ENABLE_SHIFT (7U) |
| #define IOMUXC_GPR_GPR_DSI_TX_ULPS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_TX_ULPS_ENABLE_SHIFT)) & IOMUXC_GPR_GPR_DSI_TX_ULPS_ENABLE_MASK) |
| #define IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_FULL_MASK (0x3F80U) |
| #define IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_FULL_SHIFT (7U) |
| #define IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_FULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_FULL_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PCS_TX_SWING_FULL_MASK) |
| #define IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_FULL_MASK (0x3F80U) |
| #define IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_FULL_SHIFT (7U) |
| #define IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_FULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_FULL_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PCS_TX_SWING_FULL_MASK) |
| #define IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_MASK (0x80U) |
| #define IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_SHIFT (7U) |
| #define IOMUXC_GPR_GPR_S_WADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_SHIFT)) & IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_MASK) |
| #define IOMUXC_GPR_GPR_WDOG2_MASK_MASK (0x80U) |
| #define IOMUXC_GPR_GPR_WDOG2_MASK_SHIFT (7U) |
| /*! WDOG2_MASK |
| * 0b0..WDOG2 Timeout behaves normally |
| * 0b1..WDOG2 Timeout is masked |
| */ |
| #define IOMUXC_GPR_GPR_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR_WDOG2_MASK_MASK) |
| #define IOMUXC_GPR_GPR_ARCACHE_PCIE2_EN_MASK (0x100U) |
| #define IOMUXC_GPR_GPR_ARCACHE_PCIE2_EN_SHIFT (8U) |
| /*! ARCACHE_PCIE2_EN |
| * 0b0..PCIE Primary AXI Master Port ARCACHE[1] driven by PCIE |
| * 0b1..PCIE Primary AXI Master Port ARCACHE[1] driven to constant value specified by the ARCACHE_PCIE2 bit |
| */ |
| #define IOMUXC_GPR_GPR_ARCACHE_PCIE2_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ARCACHE_PCIE2_EN_SHIFT)) & IOMUXC_GPR_GPR_ARCACHE_PCIE2_EN_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_CONT_CLK_MODE_MASK (0x100U) |
| #define IOMUXC_GPR_GPR_CSI2_1_CONT_CLK_MODE_SHIFT (8U) |
| #define IOMUXC_GPR_GPR_CSI2_1_CONT_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_CONT_CLK_MODE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_CONT_CLK_MODE_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_CONT_CLK_MODE_MASK (0x100U) |
| #define IOMUXC_GPR_GPR_CSI2_2_CONT_CLK_MODE_SHIFT (8U) |
| #define IOMUXC_GPR_GPR_CSI2_2_CONT_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_CONT_CLK_MODE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_CONT_CLK_MODE_MASK) |
| #define IOMUXC_GPR_GPR_PCIE1_APP_CLK_PM_EN_MASK (0x100U) |
| #define IOMUXC_GPR_GPR_PCIE1_APP_CLK_PM_EN_SHIFT (8U) |
| #define IOMUXC_GPR_GPR_PCIE1_APP_CLK_PM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_APP_CLK_PM_EN_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_APP_CLK_PM_EN_MASK) |
| #define IOMUXC_GPR_GPR_PCIE2_APP_CLK_PM_EN_MASK (0x100U) |
| #define IOMUXC_GPR_GPR_PCIE2_APP_CLK_PM_EN_SHIFT (8U) |
| #define IOMUXC_GPR_GPR_PCIE2_APP_CLK_PM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_APP_CLK_PM_EN_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_APP_CLK_PM_EN_MASK) |
| #define IOMUXC_GPR_GPR_PCIE2_CTRL_DEVICE_TYPE_MASK (0xF00U) |
| #define IOMUXC_GPR_GPR_PCIE2_CTRL_DEVICE_TYPE_SHIFT (8U) |
| /*! PCIE2_CTRL_DEVICE_TYPE |
| * 0b0000..PCI Express endpoint |
| * 0b0001..Legacy PCI Express endpoint |
| * 0b0100..Root port of PCI Express root complex |
| */ |
| #define IOMUXC_GPR_GPR_PCIE2_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_CTRL_DEVICE_TYPE_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_CTRL_DEVICE_TYPE_MASK) |
| #define IOMUXC_GPR_GPR_AWCACHE_PCIE2_EN_MASK (0x200U) |
| #define IOMUXC_GPR_GPR_AWCACHE_PCIE2_EN_SHIFT (9U) |
| /*! AWCACHE_PCIE2_EN |
| * 0b0..PCIE Primary AXI Master Port AWCACHE[1] driven by PCIE |
| * 0b1..PXP Primary AXI Master Port AWCACHE[1] driven to constant value specified by the AWCACHE_PCIE2 bit |
| */ |
| #define IOMUXC_GPR_GPR_AWCACHE_PCIE2_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_AWCACHE_PCIE2_EN_SHIFT)) & IOMUXC_GPR_GPR_AWCACHE_PCIE2_EN_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_AUTO_PD_EN_MASK (0x200U) |
| #define IOMUXC_GPR_GPR_CSI2_1_AUTO_PD_EN_SHIFT (9U) |
| #define IOMUXC_GPR_GPR_CSI2_1_AUTO_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_AUTO_PD_EN_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_AUTO_PD_EN_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_AUTO_PD_EN_MASK (0x200U) |
| #define IOMUXC_GPR_GPR_CSI2_2_AUTO_PD_EN_SHIFT (9U) |
| #define IOMUXC_GPR_GPR_CSI2_2_AUTO_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_AUTO_PD_EN_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_AUTO_PD_EN_MASK) |
| #define IOMUXC_GPR_GPR_PCIE1_REF_USE_PAD_MASK (0x200U) |
| #define IOMUXC_GPR_GPR_PCIE1_REF_USE_PAD_SHIFT (9U) |
| #define IOMUXC_GPR_GPR_PCIE1_REF_USE_PAD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_REF_USE_PAD_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_REF_USE_PAD_MASK) |
| #define IOMUXC_GPR_GPR_PCIE2_REF_USE_PAD_MASK (0x200U) |
| #define IOMUXC_GPR_GPR_PCIE2_REF_USE_PAD_SHIFT (9U) |
| #define IOMUXC_GPR_GPR_PCIE2_REF_USE_PAD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_REF_USE_PAD_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_REF_USE_PAD_MASK) |
| #define IOMUXC_GPR_GPR_ARCACHE_PCIE1_EN_MASK (0x400U) |
| #define IOMUXC_GPR_GPR_ARCACHE_PCIE1_EN_SHIFT (10U) |
| /*! ARCACHE_PCIE1_EN |
| * 0b0..PCIe AXI Master Port ARCACHE[1] driven by PCIe |
| * 0b1..PCIe AXI Master Port ARCACHE[1] driven to constant value specified by the ARCACHE_PXP1 bit |
| */ |
| #define IOMUXC_GPR_GPR_ARCACHE_PCIE1_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ARCACHE_PCIE1_EN_SHIFT)) & IOMUXC_GPR_GPR_ARCACHE_PCIE1_EN_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_ERR_CNT_MASK (0xFFC00U) |
| #define IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_ERR_CNT_SHIFT (10U) |
| #define IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D0_INT_LB_ERR_CNT_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_ERR_CNT_MASK (0xFFC00U) |
| #define IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_ERR_CNT_SHIFT (10U) |
| #define IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D1_INT_LB_ERR_CNT_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_ERR_CNT_MASK (0xFFC00U) |
| #define IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_ERR_CNT_SHIFT (10U) |
| #define IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D2_INT_LB_ERR_CNT_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_ERR_CNT_MASK (0xFFC00U) |
| #define IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_ERR_CNT_SHIFT (10U) |
| #define IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D3_INT_LB_ERR_CNT_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_MASK (0x400U) |
| #define IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_SHIFT (10U) |
| #define IOMUXC_GPR_GPR_CSI2_1_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ECC_ERR_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_HSEL_MASK (0x400U) |
| #define IOMUXC_GPR_GPR_CSI2_1_HSEL_SHIFT (10U) |
| #define IOMUXC_GPR_GPR_CSI2_1_HSEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_HSEL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_HSEL_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_ERR_CNT_MASK (0xFFC00U) |
| #define IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_ERR_CNT_SHIFT (10U) |
| #define IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D0_INT_LB_ERR_CNT_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_ERR_CNT_MASK (0xFFC00U) |
| #define IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_ERR_CNT_SHIFT (10U) |
| #define IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D1_INT_LB_ERR_CNT_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_ERR_CNT_MASK (0xFFC00U) |
| #define IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_ERR_CNT_SHIFT (10U) |
| #define IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D2_INT_LB_ERR_CNT_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_ERR_CNT_MASK (0xFFC00U) |
| #define IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_ERR_CNT_SHIFT (10U) |
| #define IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D3_INT_LB_ERR_CNT_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_MASK (0x400U) |
| #define IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_SHIFT (10U) |
| #define IOMUXC_GPR_GPR_CSI2_2_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ECC_ERR_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_HSEL_MASK (0x400U) |
| #define IOMUXC_GPR_GPR_CSI2_2_HSEL_SHIFT (10U) |
| #define IOMUXC_GPR_GPR_CSI2_2_HSEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_HSEL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_HSEL_MASK) |
| #define IOMUXC_GPR_GPR_DSI_D0_INT_LB_ERR_CNT_MASK (0xFFC00U) |
| #define IOMUXC_GPR_GPR_DSI_D0_INT_LB_ERR_CNT_SHIFT (10U) |
| #define IOMUXC_GPR_GPR_DSI_D0_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D0_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D0_INT_LB_ERR_CNT_MASK) |
| #define IOMUXC_GPR_GPR_DSI_D1_INT_LB_ERR_CNT_MASK (0xFFC00U) |
| #define IOMUXC_GPR_GPR_DSI_D1_INT_LB_ERR_CNT_SHIFT (10U) |
| #define IOMUXC_GPR_GPR_DSI_D1_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D1_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D1_INT_LB_ERR_CNT_MASK) |
| #define IOMUXC_GPR_GPR_DSI_D2_INT_LB_ERR_CNT_MASK (0xFFC00U) |
| #define IOMUXC_GPR_GPR_DSI_D2_INT_LB_ERR_CNT_SHIFT (10U) |
| #define IOMUXC_GPR_GPR_DSI_D2_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D2_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D2_INT_LB_ERR_CNT_MASK) |
| #define IOMUXC_GPR_GPR_DSI_D3_INT_LB_ERR_CNT_MASK (0xFFC00U) |
| #define IOMUXC_GPR_GPR_DSI_D3_INT_LB_ERR_CNT_SHIFT (10U) |
| #define IOMUXC_GPR_GPR_DSI_D3_INT_LB_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D3_INT_LB_ERR_CNT_SHIFT)) & IOMUXC_GPR_GPR_DSI_D3_INT_LB_ERR_CNT_MASK) |
| #define IOMUXC_GPR_GPR_DSI_ECC_ERR_MASK (0x400U) |
| #define IOMUXC_GPR_GPR_DSI_ECC_ERR_SHIFT (10U) |
| #define IOMUXC_GPR_GPR_DSI_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_ECC_ERR_SHIFT)) & IOMUXC_GPR_GPR_DSI_ECC_ERR_MASK) |
| #define IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_MASK (0x400U) |
| #define IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_SHIFT (10U) |
| /*! OCRAM_S_TZ_EN |
| * 0b0..The TrustZone feature is disabled. Entire State Retention OCRAM space is available for all access types (secure/non-secure/user/supervisor). |
| * 0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter. |
| */ |
| #define IOMUXC_GPR_GPR_OCRAM_S_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_MASK) |
| #define IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_EN_MASK (0x400U) |
| #define IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_EN_SHIFT (10U) |
| #define IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_EN_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_EN_MASK) |
| #define IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_EN_MASK (0x400U) |
| #define IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_EN_SHIFT (10U) |
| #define IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_EN_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_EN_MASK) |
| #define IOMUXC_GPR_GPR_AWCACHE_PCIE1_EN_MASK (0x800U) |
| #define IOMUXC_GPR_GPR_AWCACHE_PCIE1_EN_SHIFT (11U) |
| /*! AWCACHE_PCIE1_EN |
| * 0b0..PCIe AXI Master Port AWCACHE[1] driven by PCIe |
| * 0b1..PCIe AXI Master Port AWCACHE[1] driven to constant value specified by the AWCACHE_PCIE1 bit |
| */ |
| #define IOMUXC_GPR_GPR_AWCACHE_PCIE1_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_AWCACHE_PCIE1_EN_SHIFT)) & IOMUXC_GPR_GPR_AWCACHE_PCIE1_EN_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_PD_RX_MASK (0x800U) |
| #define IOMUXC_GPR_GPR_CSI2_1_PD_RX_SHIFT (11U) |
| #define IOMUXC_GPR_GPR_CSI2_1_PD_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_PD_RX_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_PD_RX_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_ULPS_MARK_ACTIVE_MASK (0xF800U) |
| #define IOMUXC_GPR_GPR_CSI2_1_ULPS_MARK_ACTIVE_SHIFT (11U) |
| #define IOMUXC_GPR_GPR_CSI2_1_ULPS_MARK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ULPS_MARK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ULPS_MARK_ACTIVE_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_PD_RX_MASK (0x800U) |
| #define IOMUXC_GPR_GPR_CSI2_2_PD_RX_SHIFT (11U) |
| #define IOMUXC_GPR_GPR_CSI2_2_PD_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_PD_RX_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_PD_RX_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_ULPS_MARK_ACTIVE_MASK (0xF800U) |
| #define IOMUXC_GPR_GPR_CSI2_2_ULPS_MARK_ACTIVE_SHIFT (11U) |
| #define IOMUXC_GPR_GPR_CSI2_2_ULPS_MARK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ULPS_MARK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ULPS_MARK_ACTIVE_MASK) |
| #define IOMUXC_GPR_GPR_DSI_HOST_UNDERRUN_ERR_MASK (0x800U) |
| #define IOMUXC_GPR_GPR_DSI_HOST_UNDERRUN_ERR_SHIFT (11U) |
| #define IOMUXC_GPR_GPR_DSI_HOST_UNDERRUN_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_HOST_UNDERRUN_ERR_SHIFT)) & IOMUXC_GPR_GPR_DSI_HOST_UNDERRUN_ERR_MASK) |
| #define IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_MASK (0x3800U) |
| #define IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_SHIFT (11U) |
| #define IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_MASK) |
| #define IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_MASK (0x800U) |
| #define IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_SHIFT (11U) |
| #define IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_CLKREQ_B_OVERRIDE_MASK) |
| #define IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_MASK (0x800U) |
| #define IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_SHIFT (11U) |
| #define IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_CLKREQ_B_OVERRIDE_MASK) |
| #define IOMUXC_GPR_GPR_ARCACHE_LCDIF_EN_MASK (0x1000U) |
| #define IOMUXC_GPR_GPR_ARCACHE_LCDIF_EN_SHIFT (12U) |
| /*! ARCACHE_LCDIF_EN |
| * 0b0..LCDIF AXI Master Port ARCACHE[1] driven by LCDIF |
| * 0b1..LCDIF AXI Master Port ARCACHE[1] driven to constant value specified by the ARCACHE_LCDIF bit |
| */ |
| #define IOMUXC_GPR_GPR_ARCACHE_LCDIF_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ARCACHE_LCDIF_EN_SHIFT)) & IOMUXC_GPR_GPR_ARCACHE_LCDIF_EN_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_VID_INTFC_ENB_MASK (0x1000U) |
| #define IOMUXC_GPR_GPR_CSI2_1_VID_INTFC_ENB_SHIFT (12U) |
| #define IOMUXC_GPR_GPR_CSI2_1_VID_INTFC_ENB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_VID_INTFC_ENB_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_VID_INTFC_ENB_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_VID_INTFC_ENB_MASK (0x1000U) |
| #define IOMUXC_GPR_GPR_CSI2_2_VID_INTFC_ENB_SHIFT (12U) |
| #define IOMUXC_GPR_GPR_CSI2_2_VID_INTFC_ENB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_VID_INTFC_ENB_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_VID_INTFC_ENB_MASK) |
| #define IOMUXC_GPR_GPR_DSI_TRIGGER_ACK_MASK (0x1000U) |
| #define IOMUXC_GPR_GPR_DSI_TRIGGER_ACK_SHIFT (12U) |
| #define IOMUXC_GPR_GPR_DSI_TRIGGER_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_TRIGGER_ACK_SHIFT)) & IOMUXC_GPR_GPR_DSI_TRIGGER_ACK_MASK) |
| #define IOMUXC_GPR_GPR_DSI_TRIGGER_SEND_MASK (0x3000U) |
| #define IOMUXC_GPR_GPR_DSI_TRIGGER_SEND_SHIFT (12U) |
| #define IOMUXC_GPR_GPR_DSI_TRIGGER_SEND(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_TRIGGER_SEND_SHIFT)) & IOMUXC_GPR_GPR_DSI_TRIGGER_SEND_MASK) |
| #define IOMUXC_GPR_GPR_IRQ_MASK (0x1000U) |
| #define IOMUXC_GPR_GPR_IRQ_SHIFT (12U) |
| #define IOMUXC_GPR_GPR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_IRQ_SHIFT)) & IOMUXC_GPR_GPR_IRQ_MASK) |
| #define IOMUXC_GPR_GPR_PCIE1_CTRL_DEVICE_TYPE_MASK (0xF000U) |
| #define IOMUXC_GPR_GPR_PCIE1_CTRL_DEVICE_TYPE_SHIFT (12U) |
| /*! PCIE1_CTRL_DEVICE_TYPE |
| * 0b0000..PCI Express endpoint |
| * 0b0001..Legacy PCI Express endpoint |
| * 0b0100..Root port of PCI Express root complex |
| */ |
| #define IOMUXC_GPR_GPR_PCIE1_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_CTRL_DEVICE_TYPE_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_CTRL_DEVICE_TYPE_MASK) |
| #define IOMUXC_GPR_GPR_PCIE1_VREG_BYPASS_MASK (0x1000U) |
| #define IOMUXC_GPR_GPR_PCIE1_VREG_BYPASS_SHIFT (12U) |
| #define IOMUXC_GPR_GPR_PCIE1_VREG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_VREG_BYPASS_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_VREG_BYPASS_MASK) |
| #define IOMUXC_GPR_GPR_PCIE2_VREG_BYPASS_MASK (0x1000U) |
| #define IOMUXC_GPR_GPR_PCIE2_VREG_BYPASS_SHIFT (12U) |
| #define IOMUXC_GPR_GPR_PCIE2_VREG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_VREG_BYPASS_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_VREG_BYPASS_MASK) |
| #define IOMUXC_GPR_GPR_ARCACHE_PCIE2_MASK (0x2000U) |
| #define IOMUXC_GPR_GPR_ARCACHE_PCIE2_SHIFT (13U) |
| /*! ARCACHE_PCIE2 |
| * 0b0..Drive PCIe AXI Master Port ARCACHE[1] to 0 |
| * 0b1..Drive PCIe AXI Master Port ARCACHE[1] to 1 |
| */ |
| #define IOMUXC_GPR_GPR_ARCACHE_PCIE2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ARCACHE_PCIE2_SHIFT)) & IOMUXC_GPR_GPR_ARCACHE_PCIE2_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_RX_ENABLE_MASK (0x2000U) |
| #define IOMUXC_GPR_GPR_CSI2_1_RX_ENABLE_SHIFT (13U) |
| #define IOMUXC_GPR_GPR_CSI2_1_RX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_RX_ENABLE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_RX_ENABLE_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_RX_ENABLE_MASK (0x2000U) |
| #define IOMUXC_GPR_GPR_CSI2_2_RX_ENABLE_SHIFT (13U) |
| #define IOMUXC_GPR_GPR_CSI2_2_RX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_RX_ENABLE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_RX_ENABLE_MASK) |
| #define IOMUXC_GPR_GPR_DSI_LP_RX_TIMEOUT_MASK (0x2000U) |
| #define IOMUXC_GPR_GPR_DSI_LP_RX_TIMEOUT_SHIFT (13U) |
| #define IOMUXC_GPR_GPR_DSI_LP_RX_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_LP_RX_TIMEOUT_SHIFT)) & IOMUXC_GPR_GPR_DSI_LP_RX_TIMEOUT_MASK) |
| #define IOMUXC_GPR_GPR_ENET1_TX_CLK_SEL_MASK (0x2000U) |
| #define IOMUXC_GPR_GPR_ENET1_TX_CLK_SEL_SHIFT (13U) |
| /*! ENET1_TX_CLK_SEL |
| * 0b0..Gets ENET1 TX reference clk. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function. |
| * 0b1..Gets ENET1 TX reference clk from the ENET1_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller |
| */ |
| #define IOMUXC_GPR_GPR_ENET1_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ENET1_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR_ENET1_TX_CLK_SEL_MASK) |
| #define IOMUXC_GPR_GPR_PCIE1_PHY_TX_VBOOST_LVL_MASK (0xE000U) |
| #define IOMUXC_GPR_GPR_PCIE1_PHY_TX_VBOOST_LVL_SHIFT (13U) |
| #define IOMUXC_GPR_GPR_PCIE1_PHY_TX_VBOOST_LVL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PHY_TX_VBOOST_LVL_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PHY_TX_VBOOST_LVL_MASK) |
| #define IOMUXC_GPR_GPR_PCIE2_PHY_TX_VBOOST_LVL_MASK (0xE000U) |
| #define IOMUXC_GPR_GPR_PCIE2_PHY_TX_VBOOST_LVL_SHIFT (13U) |
| #define IOMUXC_GPR_GPR_PCIE2_PHY_TX_VBOOST_LVL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PHY_TX_VBOOST_LVL_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PHY_TX_VBOOST_LVL_MASK) |
| #define IOMUXC_GPR_GPR_AWCACHE_PCIE2_MASK (0x4000U) |
| #define IOMUXC_GPR_GPR_AWCACHE_PCIE2_SHIFT (14U) |
| /*! AWCACHE_PCIE2 |
| * 0b0..Drive PCIe AXI Master Port AWCACHE[1] to 0 |
| * 0b1..Drive PCIe AXI Master Port AWCACHE[1] to 1 |
| */ |
| #define IOMUXC_GPR_GPR_AWCACHE_PCIE2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_AWCACHE_PCIE2_SHIFT)) & IOMUXC_GPR_GPR_AWCACHE_PCIE2_MASK) |
| #define IOMUXC_GPR_GPR_DSI_HS_TX_TIMEOUT_MASK (0x4000U) |
| #define IOMUXC_GPR_GPR_DSI_HS_TX_TIMEOUT_SHIFT (14U) |
| #define IOMUXC_GPR_GPR_DSI_HS_TX_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_HS_TX_TIMEOUT_SHIFT)) & IOMUXC_GPR_GPR_DSI_HS_TX_TIMEOUT_MASK) |
| #define IOMUXC_GPR_GPR_DSI_TRIGGER_REQ_MASK (0x4000U) |
| #define IOMUXC_GPR_GPR_DSI_TRIGGER_REQ_SHIFT (14U) |
| #define IOMUXC_GPR_GPR_DSI_TRIGGER_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_TRIGGER_REQ_SHIFT)) & IOMUXC_GPR_GPR_DSI_TRIGGER_REQ_MASK) |
| #define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_6DB_MASK (0xFC000U) |
| #define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_6DB_SHIFT (14U) |
| #define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_6DB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_6DB_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_6DB_MASK) |
| #define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_6DB_MASK (0xFC000U) |
| #define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_6DB_SHIFT (14U) |
| #define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_6DB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_6DB_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_6DB_MASK) |
| #define IOMUXC_GPR_GPR_DDSI_DPHY_TURNAROUND_MASK (0x8000U) |
| #define IOMUXC_GPR_GPR_DDSI_DPHY_TURNAROUND_SHIFT (15U) |
| #define IOMUXC_GPR_GPR_DDSI_DPHY_TURNAROUND(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DDSI_DPHY_TURNAROUND_SHIFT)) & IOMUXC_GPR_GPR_DDSI_DPHY_TURNAROUND_MASK) |
| #define IOMUXC_GPR_GPR_DSI_HOST_BTA_TIMEOUT_MASK (0x8000U) |
| #define IOMUXC_GPR_GPR_DSI_HOST_BTA_TIMEOUT_SHIFT (15U) |
| #define IOMUXC_GPR_GPR_DSI_HOST_BTA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_HOST_BTA_TIMEOUT_SHIFT)) & IOMUXC_GPR_GPR_DSI_HOST_BTA_TIMEOUT_MASK) |
| #define IOMUXC_GPR_GPR_GPR_ANAMIX_IPT_MODE_MASK (0x8000U) |
| #define IOMUXC_GPR_GPR_GPR_ANAMIX_IPT_MODE_SHIFT (15U) |
| #define IOMUXC_GPR_GPR_GPR_ANAMIX_IPT_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_GPR_ANAMIX_IPT_MODE_SHIFT)) & IOMUXC_GPR_GPR_GPR_ANAMIX_IPT_MODE_MASK) |
| #define IOMUXC_GPR_GPR_CPU_STANDBYWFI_MASK (0xF0000U) |
| #define IOMUXC_GPR_GPR_CPU_STANDBYWFI_SHIFT (16U) |
| #define IOMUXC_GPR_GPR_CPU_STANDBYWFI(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CPU_STANDBYWFI_SHIFT)) & IOMUXC_GPR_GPR_CPU_STANDBYWFI_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_RX_DPHY_RDY_MASK (0x10000U) |
| #define IOMUXC_GPR_GPR_CSI2_1_RX_DPHY_RDY_SHIFT (16U) |
| #define IOMUXC_GPR_GPR_CSI2_1_RX_DPHY_RDY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_RX_DPHY_RDY_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_RX_DPHY_RDY_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_RX_DPHY_RDY_MASK (0x10000U) |
| #define IOMUXC_GPR_GPR_CSI2_2_RX_DPHY_RDY_SHIFT (16U) |
| #define IOMUXC_GPR_GPR_CSI2_2_RX_DPHY_RDY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_RX_DPHY_RDY_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_RX_DPHY_RDY_MASK) |
| #define IOMUXC_GPR_GPR_DSI_DPHY_DIRECTION_MASK (0x10000U) |
| #define IOMUXC_GPR_GPR_DSI_DPHY_DIRECTION_SHIFT (16U) |
| #define IOMUXC_GPR_GPR_DSI_DPHY_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_DPHY_DIRECTION_SHIFT)) & IOMUXC_GPR_GPR_DSI_DPHY_DIRECTION_MASK) |
| #define IOMUXC_GPR_GPR_OCRAM_TZ_EN_LOCK_MASK (0x10000U) |
| #define IOMUXC_GPR_GPR_OCRAM_TZ_EN_LOCK_SHIFT (16U) |
| #define IOMUXC_GPR_GPR_OCRAM_TZ_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_TZ_EN_LOCK_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_TZ_EN_LOCK_MASK) |
| #define IOMUXC_GPR_GPR_PCIE1_PHY_TX0_TERM_OFFSET_MASK (0x1F0000U) |
| #define IOMUXC_GPR_GPR_PCIE1_PHY_TX0_TERM_OFFSET_SHIFT (16U) |
| #define IOMUXC_GPR_GPR_PCIE1_PHY_TX0_TERM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PHY_TX0_TERM_OFFSET_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PHY_TX0_TERM_OFFSET_MASK) |
| #define IOMUXC_GPR_GPR_PCIE2_PHY_TX0_TERM_OFFSET_MASK (0x1F0000U) |
| #define IOMUXC_GPR_GPR_PCIE2_PHY_TX0_TERM_OFFSET_SHIFT (16U) |
| #define IOMUXC_GPR_GPR_PCIE2_PHY_TX0_TERM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PHY_TX0_TERM_OFFSET_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PHY_TX0_TERM_OFFSET_MASK) |
| #define IOMUXC_GPR_GPR_RDATA_WAIT_EN_PDG_MASK (0x10000U) |
| #define IOMUXC_GPR_GPR_RDATA_WAIT_EN_PDG_SHIFT (16U) |
| /*! RDATA_WAIT_EN_PDG |
| * 0b0..read data wait state control configuration valid |
| * 0b1..read data wait state control bit changed |
| */ |
| #define IOMUXC_GPR_GPR_RDATA_WAIT_EN_PDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_RDATA_WAIT_EN_PDG_SHIFT)) & IOMUXC_GPR_GPR_RDATA_WAIT_EN_PDG_MASK) |
| #define IOMUXC_GPR_GPR_SDMA1_IPG_STOP_ACK_MASK (0x10000U) |
| #define IOMUXC_GPR_GPR_SDMA1_IPG_STOP_ACK_SHIFT (16U) |
| /*! SDMA1_IPG_STOP_ACK |
| * 0b0..stop acknowledge is not asserted |
| * 0b1..stop acknowledge is asserted, peripheral is in STOP mode |
| */ |
| #define IOMUXC_GPR_GPR_SDMA1_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SDMA1_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SDMA1_IPG_STOP_ACK_MASK) |
| #define IOMUXC_GPR_GPR_TZASC_EN_LOCK_MASK (0x10000U) |
| #define IOMUXC_GPR_GPR_TZASC_EN_LOCK_SHIFT (16U) |
| #define IOMUXC_GPR_GPR_TZASC_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_TZASC_EN_LOCK_SHIFT)) & IOMUXC_GPR_GPR_TZASC_EN_LOCK_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_CRC_ERR_MASK (0x20000U) |
| #define IOMUXC_GPR_GPR_CSI2_1_CRC_ERR_SHIFT (17U) |
| #define IOMUXC_GPR_GPR_CSI2_1_CRC_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_CRC_ERR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_CRC_ERR_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_CRC_ERR_MASK (0x20000U) |
| #define IOMUXC_GPR_GPR_CSI2_2_CRC_ERR_SHIFT (17U) |
| #define IOMUXC_GPR_GPR_CSI2_2_CRC_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_CRC_ERR_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_CRC_ERR_MASK) |
| #define IOMUXC_GPR_GPR_DSI_CRC_ERR_MASK (0x20000U) |
| #define IOMUXC_GPR_GPR_DSI_CRC_ERR_SHIFT (17U) |
| #define IOMUXC_GPR_GPR_DSI_CRC_ERR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_CRC_ERR_SHIFT)) & IOMUXC_GPR_GPR_DSI_CRC_ERR_MASK) |
| #define IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_LOCK_MASK (0x3E0000U) |
| #define IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_LOCK_SHIFT (17U) |
| #define IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_LOCK_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_TZ_ADDR_LOCK_MASK) |
| #define IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT_MASK (0x1E0000U) |
| #define IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT (17U) |
| #define IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT_MASK) |
| #define IOMUXC_GPR_GPR_RADDR_PIPE_EN_PDG_MASK (0x20000U) |
| #define IOMUXC_GPR_GPR_RADDR_PIPE_EN_PDG_SHIFT (17U) |
| /*! RADDR_PIPE_EN_PDG |
| * 0b0..read address pipeline enable configuration valid |
| * 0b1..read address pipeline enable bit changed |
| */ |
| #define IOMUXC_GPR_GPR_RADDR_PIPE_EN_PDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_RADDR_PIPE_EN_PDG_SHIFT)) & IOMUXC_GPR_GPR_RADDR_PIPE_EN_PDG_MASK) |
| #define IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_LOCK_MASK (0x20000U) |
| #define IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_LOCK_SHIFT (17U) |
| #define IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_LOCK_SHIFT)) & IOMUXC_GPR_GPR_TZASC_ID_SWAP_BYPASS_LOCK_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_ULPS_ACTIVE_MASK (0x7C0000U) |
| #define IOMUXC_GPR_GPR_CSI2_1_ULPS_ACTIVE_SHIFT (18U) |
| #define IOMUXC_GPR_GPR_CSI2_1_ULPS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ULPS_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ULPS_ACTIVE_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_ULPS_ACTIVE_MASK (0x7C0000U) |
| #define IOMUXC_GPR_GPR_CSI2_2_ULPS_ACTIVE_SHIFT (18U) |
| #define IOMUXC_GPR_GPR_CSI2_2_ULPS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ULPS_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ULPS_ACTIVE_MASK) |
| #define IOMUXC_GPR_GPR_DSI_CALOUT_MASK (0xC0000U) |
| #define IOMUXC_GPR_GPR_DSI_CALOUT_SHIFT (18U) |
| #define IOMUXC_GPR_GPR_DSI_CALOUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_CALOUT_SHIFT)) & IOMUXC_GPR_GPR_DSI_CALOUT_MASK) |
| #define IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_LOCK_MASK (0x40000U) |
| #define IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_LOCK_SHIFT (18U) |
| #define IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_LOCK_SHIFT)) & IOMUXC_GPR_GPR_SEC_ERR_RESP_EN_LOCK_MASK) |
| #define IOMUXC_GPR_GPR_WDATA_PIPE_EN_PDG_MASK (0x40000U) |
| #define IOMUXC_GPR_GPR_WDATA_PIPE_EN_PDG_SHIFT (18U) |
| /*! WDATA_PIPE_EN_PDG |
| * 0b0..write data pipeline enable configuration valid |
| * 0b1..write data pipeline enable bit changed |
| */ |
| #define IOMUXC_GPR_GPR_WDATA_PIPE_EN_PDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_WDATA_PIPE_EN_PDG_SHIFT)) & IOMUXC_GPR_GPR_WDATA_PIPE_EN_PDG_MASK) |
| #define IOMUXC_GPR_GPR_ENET1_IPG_STOP_ACK_MASK (0x80000U) |
| #define IOMUXC_GPR_GPR_ENET1_IPG_STOP_ACK_SHIFT (19U) |
| /*! ENET1_IPG_STOP_ACK |
| * 0b0..stop acknowledge is not asserted |
| * 0b1..stop acknowledge is asserted, peripheral is in STOP mode |
| */ |
| #define IOMUXC_GPR_GPR_ENET1_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_ENET1_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_ENET1_IPG_STOP_ACK_MASK) |
| #define IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_LOCK_MASK (0x80000U) |
| #define IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_LOCK_SHIFT (19U) |
| #define IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_LOCK_SHIFT)) & IOMUXC_GPR_GPR_EXC_ERR_RESP_EN_LOCK_MASK) |
| #define IOMUXC_GPR_GPR_WADDR_PIPE_EN_PNDG_MASK (0x80000U) |
| #define IOMUXC_GPR_GPR_WADDR_PIPE_EN_PNDG_SHIFT (19U) |
| /*! WADDR_PIPE_EN_PNDG |
| * 0b0..write address pipeline enable configuration valid |
| * 0b1..write address pipeline enable bit changed |
| */ |
| #define IOMUXC_GPR_GPR_WADDR_PIPE_EN_PNDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_WADDR_PIPE_EN_PNDG_SHIFT)) & IOMUXC_GPR_GPR_WADDR_PIPE_EN_PNDG_MASK) |
| #define IOMUXC_GPR_GPR_CPU_STANDBYWFE_MASK (0xF00000U) |
| #define IOMUXC_GPR_GPR_CPU_STANDBYWFE_SHIFT (20U) |
| #define IOMUXC_GPR_GPR_CPU_STANDBYWFE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CPU_STANDBYWFE_SHIFT)) & IOMUXC_GPR_GPR_CPU_STANDBYWFE_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_D0_LB_ACTIVE_MASK (0x100000U) |
| #define IOMUXC_GPR_GPR_CSI2_1_D0_LB_ACTIVE_SHIFT (20U) |
| #define IOMUXC_GPR_GPR_CSI2_1_D0_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D0_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D0_LB_ACTIVE_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_D1_LB_ACTIVE_MASK (0x100000U) |
| #define IOMUXC_GPR_GPR_CSI2_1_D1_LB_ACTIVE_SHIFT (20U) |
| #define IOMUXC_GPR_GPR_CSI2_1_D1_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D1_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D1_LB_ACTIVE_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_D2_LB_ACTIVE_MASK (0x100000U) |
| #define IOMUXC_GPR_GPR_CSI2_1_D2_LB_ACTIVE_SHIFT (20U) |
| #define IOMUXC_GPR_GPR_CSI2_1_D2_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D2_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D2_LB_ACTIVE_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_D3_LB_ACTIVE_MASK (0x100000U) |
| #define IOMUXC_GPR_GPR_CSI2_1_D3_LB_ACTIVE_SHIFT (20U) |
| #define IOMUXC_GPR_GPR_CSI2_1_D3_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_D3_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_D3_LB_ACTIVE_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_D0_LB_ACTIVE_MASK (0x100000U) |
| #define IOMUXC_GPR_GPR_CSI2_2_D0_LB_ACTIVE_SHIFT (20U) |
| #define IOMUXC_GPR_GPR_CSI2_2_D0_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D0_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D0_LB_ACTIVE_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_D1_LB_ACTIVE_MASK (0x100000U) |
| #define IOMUXC_GPR_GPR_CSI2_2_D1_LB_ACTIVE_SHIFT (20U) |
| #define IOMUXC_GPR_GPR_CSI2_2_D1_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D1_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D1_LB_ACTIVE_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_D2_LB_ACTIVE_MASK (0x100000U) |
| #define IOMUXC_GPR_GPR_CSI2_2_D2_LB_ACTIVE_SHIFT (20U) |
| #define IOMUXC_GPR_GPR_CSI2_2_D2_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D2_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D2_LB_ACTIVE_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_D3_LB_ACTIVE_MASK (0x100000U) |
| #define IOMUXC_GPR_GPR_CSI2_2_D3_LB_ACTIVE_SHIFT (20U) |
| #define IOMUXC_GPR_GPR_CSI2_2_D3_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_D3_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_D3_LB_ACTIVE_MASK) |
| #define IOMUXC_GPR_GPR_DSI_CALCOMPL_MASK (0x100000U) |
| #define IOMUXC_GPR_GPR_DSI_CALCOMPL_SHIFT (20U) |
| #define IOMUXC_GPR_GPR_DSI_CALCOMPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_CALCOMPL_SHIFT)) & IOMUXC_GPR_GPR_DSI_CALCOMPL_MASK) |
| #define IOMUXC_GPR_GPR_DSI_D0_LB_ACTIVE_MASK (0x100000U) |
| #define IOMUXC_GPR_GPR_DSI_D0_LB_ACTIVE_SHIFT (20U) |
| #define IOMUXC_GPR_GPR_DSI_D0_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D0_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_DSI_D0_LB_ACTIVE_MASK) |
| #define IOMUXC_GPR_GPR_DSI_D1_LB_ACTIVE_MASK (0x100000U) |
| #define IOMUXC_GPR_GPR_DSI_D1_LB_ACTIVE_SHIFT (20U) |
| #define IOMUXC_GPR_GPR_DSI_D1_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D1_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_DSI_D1_LB_ACTIVE_MASK) |
| #define IOMUXC_GPR_GPR_DSI_D2_LB_ACTIVE_MASK (0x100000U) |
| #define IOMUXC_GPR_GPR_DSI_D2_LB_ACTIVE_SHIFT (20U) |
| #define IOMUXC_GPR_GPR_DSI_D2_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D2_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_DSI_D2_LB_ACTIVE_MASK) |
| #define IOMUXC_GPR_GPR_DSI_D3_LB_ACTIVE_MASK (0x100000U) |
| #define IOMUXC_GPR_GPR_DSI_D3_LB_ACTIVE_SHIFT (20U) |
| #define IOMUXC_GPR_GPR_DSI_D3_LB_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_D3_LB_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_DSI_D3_LB_ACTIVE_MASK) |
| #define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_3P5DB_MASK (0x3F00000U) |
| #define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_3P5DB_SHIFT (20U) |
| #define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_3P5DB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_3P5DB_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN2_3P5DB_MASK) |
| #define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_3P5DB_MASK (0x3F00000U) |
| #define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_3P5DB_SHIFT (20U) |
| #define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_3P5DB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_3P5DB_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN2_3P5DB_MASK) |
| #define IOMUXC_GPR_GPR_SDMA2_IPG_STOP_ACK_MASK (0x100000U) |
| #define IOMUXC_GPR_GPR_SDMA2_IPG_STOP_ACK_SHIFT (20U) |
| /*! SDMA2_IPG_STOP_ACK |
| * 0b0..stop acknowledge is not asserted |
| * 0b1..stop acknowledge is asserted, peripheral is in STOP mode |
| */ |
| #define IOMUXC_GPR_GPR_SDMA2_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SDMA2_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SDMA2_IPG_STOP_ACK_MASK) |
| #define IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_PNDG_MASK (0x100000U) |
| #define IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_PNDG_SHIFT (20U) |
| /*! S_RDATA_WAIT_EN_PNDG |
| * 0b0..read data wait state control configuration valid |
| * 0b1..read data wait state control bit changed |
| */ |
| #define IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_PNDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_PNDG_SHIFT)) & IOMUXC_GPR_GPR_S_RDATA_WAIT_EN_PNDG_MASK) |
| #define IOMUXC_GPR_GPR_WDOG3_MASK_MASK (0x100000U) |
| #define IOMUXC_GPR_GPR_WDOG3_MASK_SHIFT (20U) |
| /*! WDOG3_MASK |
| * 0b0..WDOG3 Timeout behaves normally |
| * 0b1..WDOG3 Timeout is masked |
| */ |
| #define IOMUXC_GPR_GPR_WDOG3_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_WDOG3_MASK_SHIFT)) & IOMUXC_GPR_GPR_WDOG3_MASK_MASK) |
| #define IOMUXC_GPR_GPR_DSI_ULPS_ACTIVE_MASK (0x3E00000U) |
| #define IOMUXC_GPR_GPR_DSI_ULPS_ACTIVE_SHIFT (21U) |
| #define IOMUXC_GPR_GPR_DSI_ULPS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DSI_ULPS_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR_DSI_ULPS_ACTIVE_MASK) |
| #define IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_CTRL_BUS_MASK (0x600000U) |
| #define IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_CTRL_BUS_SHIFT (21U) |
| #define IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_CTRL_BUS_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_CTRL_DIAG_CTRL_BUS_MASK) |
| #define IOMUXC_GPR_GPR_PCIE1_PHY_RX0_EQ_MASK (0xE00000U) |
| #define IOMUXC_GPR_GPR_PCIE1_PHY_RX0_EQ_SHIFT (21U) |
| #define IOMUXC_GPR_GPR_PCIE1_PHY_RX0_EQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PHY_RX0_EQ_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PHY_RX0_EQ_MASK) |
| #define IOMUXC_GPR_GPR_PCIE2_PHY_RX0_EQ_MASK (0xE00000U) |
| #define IOMUXC_GPR_GPR_PCIE2_PHY_RX0_EQ_SHIFT (21U) |
| #define IOMUXC_GPR_GPR_PCIE2_PHY_RX0_EQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PHY_RX0_EQ_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PHY_RX0_EQ_MASK) |
| #define IOMUXC_GPR_GPR_SAI1_IPG_STOP_ACK_MASK (0x200000U) |
| #define IOMUXC_GPR_GPR_SAI1_IPG_STOP_ACK_SHIFT (21U) |
| /*! SAI1_IPG_STOP_ACK |
| * 0b0..stop acknowledge is not asserted |
| * 0b1..stop acknowledge is asserted, peripheral is in STOP mode |
| */ |
| #define IOMUXC_GPR_GPR_SAI1_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SAI1_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SAI1_IPG_STOP_ACK_MASK) |
| #define IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_PNDG_MASK (0x200000U) |
| #define IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_PNDG_SHIFT (21U) |
| /*! S_RADDR_PIPE_EN_PNDG |
| * 0b0..read address pipeline enable configuration valid |
| * 0b1..read address pipeline enable bit changed |
| */ |
| #define IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_PNDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_PNDG_SHIFT)) & IOMUXC_GPR_GPR_S_RADDR_PIPE_EN_PNDG_MASK) |
| #define IOMUXC_GPR_GPR_SAI2_IPG_STOP_ACK_MASK (0x400000U) |
| #define IOMUXC_GPR_GPR_SAI2_IPG_STOP_ACK_SHIFT (22U) |
| /*! SAI2_IPG_STOP_ACK |
| * 0b0..stop acknowledge is not asserted |
| * 0b1..stop acknowledge is asserted, peripheral is in STOP mode |
| */ |
| #define IOMUXC_GPR_GPR_SAI2_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SAI2_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SAI2_IPG_STOP_ACK_MASK) |
| #define IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_PNDG_MASK (0x400000U) |
| #define IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_PNDG_SHIFT (22U) |
| /*! S_WDATA_PIPE_EN_PNDG |
| * 0b0..write data pipeline enable configuration valid |
| * 0b1..write data pipeline enable bit changed |
| */ |
| #define IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_PNDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_PNDG_SHIFT)) & IOMUXC_GPR_GPR_S_WDATA_PIPE_EN_PNDG_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_ERR_FIFO_WR_OVFL_MASK (0x800000U) |
| #define IOMUXC_GPR_GPR_CSI2_1_ERR_FIFO_WR_OVFL_SHIFT (23U) |
| #define IOMUXC_GPR_GPR_CSI2_1_ERR_FIFO_WR_OVFL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ERR_FIFO_WR_OVFL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ERR_FIFO_WR_OVFL_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_ERR_FIFO_WR_OVFL_MASK (0x800000U) |
| #define IOMUXC_GPR_GPR_CSI2_2_ERR_FIFO_WR_OVFL_SHIFT (23U) |
| #define IOMUXC_GPR_GPR_CSI2_2_ERR_FIFO_WR_OVFL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ERR_FIFO_WR_OVFL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ERR_FIFO_WR_OVFL_MASK) |
| #define IOMUXC_GPR_GPR_SAI3_IPG_STOP_ACK_MASK (0x800000U) |
| #define IOMUXC_GPR_GPR_SAI3_IPG_STOP_ACK_SHIFT (23U) |
| /*! SAI3_IPG_STOP_ACK |
| * 0b0..stop acknowledge is not asserted |
| * 0b1..stop acknowledge is asserted, peripheral is in STOP mode |
| */ |
| #define IOMUXC_GPR_GPR_SAI3_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SAI3_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SAI3_IPG_STOP_ACK_MASK) |
| #define IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_PNDG_MASK (0x800000U) |
| #define IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_PNDG_SHIFT (23U) |
| /*! S_WADDR_PIPE_EN_PNDG |
| * 0b0..write address pipeline enable configuration valid |
| * 0b1..write address pipeline enable bit changed |
| */ |
| #define IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_PNDG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_PNDG_SHIFT)) & IOMUXC_GPR_GPR_S_WADDR_PIPE_EN_PNDG_MASK) |
| #define IOMUXC_GPR_GPR_TZASC1_SECURE_BOOT_LOCK_MASK (0x800000U) |
| #define IOMUXC_GPR_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT (23U) |
| /*! TZASC1_SECURE_BOOT_LOCK |
| * 0b0..Secure boot lock is disabled |
| * 0b1..Secure boot lock is enabled |
| */ |
| #define IOMUXC_GPR_GPR_TZASC1_SECURE_BOOT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT)) & IOMUXC_GPR_GPR_TZASC1_SECURE_BOOT_LOCK_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_1_ERR_SEND_LEVEL_MASK (0x1000000U) |
| #define IOMUXC_GPR_GPR_CSI2_1_ERR_SEND_LEVEL_SHIFT (24U) |
| #define IOMUXC_GPR_GPR_CSI2_1_ERR_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_1_ERR_SEND_LEVEL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_1_ERR_SEND_LEVEL_MASK) |
| #define IOMUXC_GPR_GPR_CSI2_2_ERR_SEND_LEVEL_MASK (0x1000000U) |
| #define IOMUXC_GPR_GPR_CSI2_2_ERR_SEND_LEVEL_SHIFT (24U) |
| #define IOMUXC_GPR_GPR_CSI2_2_ERR_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_CSI2_2_ERR_SEND_LEVEL_SHIFT)) & IOMUXC_GPR_GPR_CSI2_2_ERR_SEND_LEVEL_MASK) |
| #define IOMUXC_GPR_GPR_PCIE1_PHY_LOS_LEVEL_MASK (0x1F000000U) |
| #define IOMUXC_GPR_GPR_PCIE1_PHY_LOS_LEVEL_SHIFT (24U) |
| #define IOMUXC_GPR_GPR_PCIE1_PHY_LOS_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PHY_LOS_LEVEL_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PHY_LOS_LEVEL_MASK) |
| #define IOMUXC_GPR_GPR_PCIE2_PHY_LOS_LEVEL_MASK (0x1F000000U) |
| #define IOMUXC_GPR_GPR_PCIE2_PHY_LOS_LEVEL_SHIFT (24U) |
| #define IOMUXC_GPR_GPR_PCIE2_PHY_LOS_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PHY_LOS_LEVEL_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PHY_LOS_LEVEL_MASK) |
| #define IOMUXC_GPR_GPR_SAI4_IPG_STOP_ACK_MASK (0x1000000U) |
| #define IOMUXC_GPR_GPR_SAI4_IPG_STOP_ACK_SHIFT (24U) |
| /*! SAI4_IPG_STOP_ACK |
| * 0b0..stop acknowledge is not asserted |
| * 0b1..stop acknowledge is asserted, peripheral is in STOP mode |
| */ |
| #define IOMUXC_GPR_GPR_SAI4_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SAI4_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SAI4_IPG_STOP_ACK_MASK) |
| #define IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_STATUS_BUS_SELECT_MASK (0x1E000000U) |
| #define IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT (25U) |
| #define IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_STATUS_BUS_SELECT_MASK) |
| #define IOMUXC_GPR_GPR_SAI5_IPG_STOP_ACK_MASK (0x2000000U) |
| #define IOMUXC_GPR_GPR_SAI5_IPG_STOP_ACK_SHIFT (25U) |
| /*! SAI5_IPG_STOP_ACK |
| * 0b0..stop acknowledge is not asserted |
| * 0b1..stop acknowledge is asserted, peripheral is in STOP mode |
| */ |
| #define IOMUXC_GPR_GPR_SAI5_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SAI5_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SAI5_IPG_STOP_ACK_MASK) |
| #define IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_LOCK_MASK (0x4000000U) |
| #define IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_LOCK_SHIFT (26U) |
| #define IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_LOCK_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_S_TZ_EN_LOCK_MASK) |
| #define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN1_MASK (0xFC000000U) |
| #define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN1_SHIFT (26U) |
| #define IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN1_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PCS_TX_DEEMPH_GEN1_MASK) |
| #define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN1_MASK (0xFC000000U) |
| #define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN1_SHIFT (26U) |
| #define IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN1_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PCS_TX_DEEMPH_GEN1_MASK) |
| #define IOMUXC_GPR_GPR_SAI6_IPG_STOP_ACK_MASK (0x4000000U) |
| #define IOMUXC_GPR_GPR_SAI6_IPG_STOP_ACK_SHIFT (26U) |
| /*! SAI6_IPG_STOP_ACK |
| * 0b0..stop acknowledge is not asserted |
| * 0b1..stop acknowledge is asserted, peripheral is in STOP mode |
| */ |
| #define IOMUXC_GPR_GPR_SAI6_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_SAI6_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR_SAI6_IPG_STOP_ACK_MASK) |
| #define IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_LOCK_MASK (0x38000000U) |
| #define IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_LOCK_SHIFT (27U) |
| #define IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_LOCK_SHIFT)) & IOMUXC_GPR_GPR_OCRAM_S_TZ_ADDR_LOCK_MASK) |
| #define IOMUXC_GPR_GPR_DBG_ACK_MASK (0xF0000000U) |
| #define IOMUXC_GPR_GPR_DBG_ACK_SHIFT (28U) |
| #define IOMUXC_GPR_GPR_DBG_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_DBG_ACK_SHIFT)) & IOMUXC_GPR_GPR_DBG_ACK_MASK) |
| #define IOMUXC_GPR_GPR_PCIE1_PHY_LOS_BIAS_MASK (0xE0000000U) |
| #define IOMUXC_GPR_GPR_PCIE1_PHY_LOS_BIAS_SHIFT (29U) |
| #define IOMUXC_GPR_GPR_PCIE1_PHY_LOS_BIAS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE1_PHY_LOS_BIAS_SHIFT)) & IOMUXC_GPR_GPR_PCIE1_PHY_LOS_BIAS_MASK) |
| #define IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_CTRL_BUS_MASK (0x60000000U) |
| #define IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_CTRL_BUS_SHIFT (29U) |
| #define IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_CTRL_BUS_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_CTRL_DIAG_CTRL_BUS_MASK) |
| #define IOMUXC_GPR_GPR_PCIE2_PHY_LOS_BIAS_MASK (0xE0000000U) |
| #define IOMUXC_GPR_GPR_PCIE2_PHY_LOS_BIAS_SHIFT (29U) |
| #define IOMUXC_GPR_GPR_PCIE2_PHY_LOS_BIAS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE2_PHY_LOS_BIAS_SHIFT)) & IOMUXC_GPR_GPR_PCIE2_PHY_LOS_BIAS_MASK) |
| #define IOMUXC_GPR_GPR_PCIE_DIAG_BUS_SEL_MASK (0x80000000U) |
| #define IOMUXC_GPR_GPR_PCIE_DIAG_BUS_SEL_SHIFT (31U) |
| #define IOMUXC_GPR_GPR_PCIE_DIAG_BUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR_PCIE_DIAG_BUS_SEL_SHIFT)) & IOMUXC_GPR_GPR_PCIE_DIAG_BUS_SEL_MASK) |
| /*! @} */ |
| |
| /* The count of IOMUXC_GPR_GPR */ |
| #define IOMUXC_GPR_GPR_COUNT (48U) |
| |
| |
| /*! |
| * @} |
| */ /* end of group IOMUXC_GPR_Register_Masks */ |
| |
| |
| /* IOMUXC_GPR - Peripheral instance base addresses */ |
| /** Peripheral IOMUXC_GPR base address */ |
| #define IOMUXC_GPR_BASE (0x30340000u) |
| /** Peripheral IOMUXC_GPR base pointer */ |
| #define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE) |
| /** Array initializer of IOMUXC_GPR peripheral base addresses */ |
| #define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE } |
| /** Array initializer of IOMUXC_GPR peripheral base pointers */ |
| #define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR } |
| |
| /*! |
| * @} |
| */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- IRQ_STEER Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup IRQ_STEER_Peripheral_Access_Layer IRQ_STEER Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** IRQ_STEER - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t CHANNCTL; /**< Channel n Control Register, offset: 0x0 */ |
| __IO uint32_t CHN_MASK[16]; /**< Channel n Interrupt Mask Register, array offset: 0x4, array step: 0x4 */ |
| __IO uint32_t CHN_SET[16]; /**< Channel n Interrupt Set Register, array offset: 0x44, array step: 0x4 */ |
| __I uint32_t CHN_STATUS[16]; /**< Channel n Interrupt Status Register, array offset: 0x84, array step: 0x4 */ |
| __IO uint32_t CHN_MINTDIS; /**< Channel n Master Interrupt Disable Register, offset: 0xC4 */ |
| __I uint32_t CHN_MSTRSTAT; /**< Channel n Master Status Register, offset: 0xC8 */ |
| } IRQ_STEER_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- IRQ_STEER Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup IRQ_STEER_Register_Masks IRQ_STEER Register Masks |
| * @{ |
| */ |
| |
| /*! @name CHANNCTL - Channel n Control Register */ |
| /*! @{ */ |
| #define IRQ_STEER_CHANNCTL_CH0_MASK (0x1U) |
| #define IRQ_STEER_CHANNCTL_CH0_SHIFT (0U) |
| /*! CH0 - Channel 0 control |
| * 0b0..Disable channel 0 |
| * 0b1..Enable channel 0 |
| */ |
| #define IRQ_STEER_CHANNCTL_CH0(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHANNCTL_CH0_SHIFT)) & IRQ_STEER_CHANNCTL_CH0_MASK) |
| #define IRQ_STEER_CHANNCTL_CH1_MASK (0x2U) |
| #define IRQ_STEER_CHANNCTL_CH1_SHIFT (1U) |
| /*! CH1 - Channel 1 control |
| * 0b0..Disable channel 1 |
| * 0b1..Enable channel 1 |
| */ |
| #define IRQ_STEER_CHANNCTL_CH1(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHANNCTL_CH1_SHIFT)) & IRQ_STEER_CHANNCTL_CH1_MASK) |
| #define IRQ_STEER_CHANNCTL_CH2_MASK (0x4U) |
| #define IRQ_STEER_CHANNCTL_CH2_SHIFT (2U) |
| /*! CH2 - Channel 2 control |
| * 0b0..Disable channel 2 |
| * 0b1..Enable channel 2 |
| */ |
| #define IRQ_STEER_CHANNCTL_CH2(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHANNCTL_CH2_SHIFT)) & IRQ_STEER_CHANNCTL_CH2_MASK) |
| #define IRQ_STEER_CHANNCTL_CH3_MASK (0x8U) |
| #define IRQ_STEER_CHANNCTL_CH3_SHIFT (3U) |
| /*! CH3 - Channel 3 control |
| * 0b0..Disable channel 3 |
| * 0b1..Enable channel 3 |
| */ |
| #define IRQ_STEER_CHANNCTL_CH3(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHANNCTL_CH3_SHIFT)) & IRQ_STEER_CHANNCTL_CH3_MASK) |
| #define IRQ_STEER_CHANNCTL_CH4_MASK (0x10U) |
| #define IRQ_STEER_CHANNCTL_CH4_SHIFT (4U) |
| /*! CH4 - Channel 4 control |
| * 0b0..Disable channel 4 |
| * 0b1..Enable channel 4 |
| */ |
| #define IRQ_STEER_CHANNCTL_CH4(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHANNCTL_CH4_SHIFT)) & IRQ_STEER_CHANNCTL_CH4_MASK) |
| /*! @} */ |
| |
| /*! @name CHN_MASK - Channel n Interrupt Mask Register */ |
| /*! @{ */ |
| #define IRQ_STEER_CHN_MASK_MASKFLD_MASK (0xFFFFFFFFU) |
| #define IRQ_STEER_CHN_MASK_MASKFLD_SHIFT (0U) |
| /*! MASKFLD - Mask bits |
| * 0b00000000000000000000000000000000..Mask interrupt |
| * 0b00000000000000000000000000000001..Do not mask interrupt |
| */ |
| #define IRQ_STEER_CHN_MASK_MASKFLD(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHN_MASK_MASKFLD_SHIFT)) & IRQ_STEER_CHN_MASK_MASKFLD_MASK) |
| /*! @} */ |
| |
| /* The count of IRQ_STEER_CHN_MASK */ |
| #define IRQ_STEER_CHN_MASK_COUNT (16U) |
| |
| /*! @name CHN_SET - Channel n Interrupt Set Register */ |
| /*! @{ */ |
| #define IRQ_STEER_CHN_SET_FORCEFLD_MASK (0xFFFFFFFFU) |
| #define IRQ_STEER_CHN_SET_FORCEFLD_SHIFT (0U) |
| /*! FORCEFLD - Brief bitfield description. |
| * 0b00000000000000000000000000000000..Normal operation |
| * 0b00000000000000000000000000000001..Force interrupt |
| */ |
| #define IRQ_STEER_CHN_SET_FORCEFLD(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHN_SET_FORCEFLD_SHIFT)) & IRQ_STEER_CHN_SET_FORCEFLD_MASK) |
| /*! @} */ |
| |
| /* The count of IRQ_STEER_CHN_SET */ |
| #define IRQ_STEER_CHN_SET_COUNT (16U) |
| |
| /*! @name CHN_STATUS - Channel n Interrupt Status Register */ |
| /*! @{ */ |
| #define IRQ_STEER_CHN_STATUS_STATUS_MASK (0xFFFFFFFFU) |
| #define IRQ_STEER_CHN_STATUS_STATUS_SHIFT (0U) |
| /*! STATUS - Status of an interrupt |
| * 0b00000000000000000000000000000000..Interrupt is not set. |
| * 0b00000000000000000000000000000001..Interrupt is set. |
| */ |
| #define IRQ_STEER_CHN_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHN_STATUS_STATUS_SHIFT)) & IRQ_STEER_CHN_STATUS_STATUS_MASK) |
| /*! @} */ |
| |
| /* The count of IRQ_STEER_CHN_STATUS */ |
| #define IRQ_STEER_CHN_STATUS_COUNT (16U) |
| |
| /*! @name CHN_MINTDIS - Channel n Master Interrupt Disable Register */ |
| /*! @{ */ |
| #define IRQ_STEER_CHN_MINTDIS_DISABLE_MASK (0xFFU) |
| #define IRQ_STEER_CHN_MINTDIS_DISABLE_SHIFT (0U) |
| /*! DISABLE - Each bit of this field disables the corresponding interrupts in table above. |
| * 0b00000000..Enable interrupts |
| * 0b00000001..Disable interrupts |
| */ |
| #define IRQ_STEER_CHN_MINTDIS_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHN_MINTDIS_DISABLE_SHIFT)) & IRQ_STEER_CHN_MINTDIS_DISABLE_MASK) |
| /*! @} */ |
| |
| /*! @name CHN_MSTRSTAT - Channel n Master Status Register */ |
| /*! @{ */ |
| #define IRQ_STEER_CHN_MSTRSTAT_STATUS_MASK (0x1U) |
| #define IRQ_STEER_CHN_MSTRSTAT_STATUS_SHIFT (0U) |
| /*! STATUS - Status of all interrupts |
| * 0b0..No interrupts are asserted. |
| * 0b1..At least one interrupt is asserted. |
| */ |
| #define IRQ_STEER_CHN_MSTRSTAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IRQ_STEER_CHN_MSTRSTAT_STATUS_SHIFT)) & IRQ_STEER_CHN_MSTRSTAT_STATUS_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group IRQ_STEER_Register_Masks */ |
| |
| |
| /* IRQ_STEER - Peripheral instance base addresses */ |
| /** Peripheral IRQ_STEER base address */ |
| #define IRQ_STEER_BASE (0x32E2D000u) |
| /** Peripheral IRQ_STEER base pointer */ |
| #define IRQ_STEER ((IRQ_STEER_Type *)IRQ_STEER_BASE) |
| /** Array initializer of IRQ_STEER peripheral base addresses */ |
| #define IRQ_STEER_BASE_ADDRS { IRQ_STEER_BASE } |
| /** Array initializer of IRQ_STEER peripheral base pointers */ |
| #define IRQ_STEER_BASE_PTRS { IRQ_STEER } |
| |
| /*! |
| * @} |
| */ /* end of group IRQ_STEER_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- LCDIF Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** LCDIF - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t CTRL; /**< LCDIF General Control Register, offset: 0x0 */ |
| __IO uint32_t CTRL_SET; /**< LCDIF General Control Register, offset: 0x4 */ |
| __IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 */ |
| __IO uint32_t CTRL_TOG; /**< LCDIF General Control Register, offset: 0xC */ |
| __IO uint32_t CTRL1; /**< LCDIF General Control1 Register, offset: 0x10 */ |
| __IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x14 */ |
| __IO uint32_t CTRL1_CLR; /**< LCDIF General Control1 Register, offset: 0x18 */ |
| __IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1C */ |
| __IO uint32_t CTRL2; /**< LCDIF General Control2 Register, offset: 0x20 */ |
| __IO uint32_t CTRL2_SET; /**< LCDIF General Control2 Register, offset: 0x24 */ |
| __IO uint32_t CTRL2_CLR; /**< LCDIF General Control2 Register, offset: 0x28 */ |
| __IO uint32_t CTRL2_TOG; /**< LCDIF General Control2 Register, offset: 0x2C */ |
| __IO uint32_t TRANSFER_COUNT; /**< LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */ |
| uint8_t RESERVED_0[12]; |
| __IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */ |
| uint8_t RESERVED_1[12]; |
| __IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */ |
| uint8_t RESERVED_2[12]; |
| __IO uint32_t TIMING; /**< LCD Interface Timing Register, offset: 0x60 */ |
| uint8_t RESERVED_3[12]; |
| __IO uint32_t VDCTRL0; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */ |
| __IO uint32_t VDCTRL0_SET; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */ |
| __IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */ |
| __IO uint32_t VDCTRL0_TOG; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */ |
| __IO uint32_t VDCTRL1; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */ |
| uint8_t RESERVED_4[12]; |
| __IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */ |
| uint8_t RESERVED_5[12]; |
| __IO uint32_t VDCTRL3; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */ |
| uint8_t RESERVED_6[12]; |
| __IO uint32_t VDCTRL4; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */ |
| uint8_t RESERVED_7[12]; |
| __IO uint32_t DVICTRL0; /**< Digital Video Interface Control0 Register, offset: 0xC0 */ |
| uint8_t RESERVED_8[12]; |
| __IO uint32_t DVICTRL1; /**< Digital Video Interface Control1 Register, offset: 0xD0 */ |
| uint8_t RESERVED_9[12]; |
| __IO uint32_t DVICTRL2; /**< Digital Video Interface Control2 Register, offset: 0xE0 */ |
| uint8_t RESERVED_10[12]; |
| __IO uint32_t DVICTRL3; /**< Digital Video Interface Control3 Register, offset: 0xF0 */ |
| uint8_t RESERVED_11[12]; |
| __IO uint32_t DVICTRL4; /**< Digital Video Interface Control4 Register, offset: 0x100 */ |
| uint8_t RESERVED_12[12]; |
| __IO uint32_t CSC_COEFF0; /**< RGB to YCbCr 4:2:2 CSC Coefficient0 Register, offset: 0x110 */ |
| uint8_t RESERVED_13[12]; |
| __IO uint32_t CSC_COEFF1; /**< RGB to YCbCr 4:2:2 CSC Coefficient1 Register, offset: 0x120 */ |
| uint8_t RESERVED_14[12]; |
| __IO uint32_t CSC_COEFF2; /**< RGB to YCbCr 4:2:2 CSC Coefficent2 Register, offset: 0x130 */ |
| uint8_t RESERVED_15[12]; |
| __IO uint32_t CSC_COEFF3; /**< RGB to YCbCr 4:2:2 CSC Coefficient3 Register, offset: 0x140 */ |
| uint8_t RESERVED_16[12]; |
| __IO uint32_t CSC_COEFF4; /**< RGB to YCbCr 4:2:2 CSC Coefficient4 Register, offset: 0x150 */ |
| uint8_t RESERVED_17[12]; |
| __IO uint32_t CSC_OFFSET; /**< RGB to YCbCr 4:2:2 CSC Offset Register, offset: 0x160 */ |
| uint8_t RESERVED_18[12]; |
| __IO uint32_t CSC_LIMIT; /**< RGB to YCbCr 4:2:2 CSC Limit Register, offset: 0x170 */ |
| uint8_t RESERVED_19[12]; |
| __IO uint32_t DATA; /**< LCD Interface Data Register, offset: 0x180 */ |
| uint8_t RESERVED_20[12]; |
| __IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */ |
| uint8_t RESERVED_21[12]; |
| __IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */ |
| uint8_t RESERVED_22[12]; |
| __I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */ |
| uint8_t RESERVED_23[76]; |
| __IO uint32_t THRES; /**< LCDIF Threshold Register, offset: 0x200 */ |
| uint8_t RESERVED_24[12]; |
| __IO uint32_t AS_CTRL; /**< LCDIF AS Buffer Control Register, offset: 0x210 */ |
| uint8_t RESERVED_25[12]; |
| __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x220 */ |
| uint8_t RESERVED_26[12]; |
| __IO uint32_t AS_NEXT_BUF; /**< , offset: 0x230 */ |
| uint8_t RESERVED_27[12]; |
| __IO uint32_t AS_CLRKEYLOW; /**< LCDIF Overlay Color Key Low, offset: 0x240 */ |
| uint8_t RESERVED_28[12]; |
| __IO uint32_t AS_CLRKEYHIGH; /**< LCDIF Overlay Color Key High, offset: 0x250 */ |
| uint8_t RESERVED_29[12]; |
| __IO uint32_t SYNC_DELAY; /**< LCD working insync mode with CSI for VSYNC delay, offset: 0x260 */ |
| } LCDIF_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- LCDIF Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup LCDIF_Register_Masks LCDIF Register Masks |
| * @{ |
| */ |
| |
| /*! @name CTRL - LCDIF General Control Register */ |
| /*! @{ */ |
| #define LCDIF_CTRL_RUN_MASK (0x1U) |
| #define LCDIF_CTRL_RUN_SHIFT (0U) |
| #define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK) |
| #define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U) |
| #define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U) |
| /*! DATA_FORMAT_24_BIT |
| * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. |
| * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. |
| */ |
| #define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK) |
| #define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U) |
| #define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U) |
| /*! DATA_FORMAT_18_BIT |
| * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. |
| * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. |
| */ |
| #define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK) |
| #define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U) |
| #define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U) |
| #define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK) |
| #define LCDIF_CTRL_RSRVD0_MASK (0x10U) |
| #define LCDIF_CTRL_RSRVD0_SHIFT (4U) |
| #define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK) |
| #define LCDIF_CTRL_MASTER_MASK (0x20U) |
| #define LCDIF_CTRL_MASTER_SHIFT (5U) |
| #define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK) |
| #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U) |
| #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U) |
| #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK) |
| #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK (0x80U) |
| #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT (7U) |
| #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK) |
| #define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U) |
| #define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U) |
| /*! WORD_LENGTH |
| * 0b00..Input data is 16 bits per pixel. |
| * 0b01..Input data is 8 bits wide. |
| * 0b10..Input data is 18 bits per pixel. |
| * 0b11..Input data is 24 bits per pixel. |
| */ |
| #define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK) |
| #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U) |
| #define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U) |
| /*! LCD_DATABUS_WIDTH |
| * 0b00..16-bit data bus mode. |
| * 0b01..8-bit data bus mode. |
| * 0b10..18-bit data bus mode. |
| * 0b11..24-bit data bus mode. |
| */ |
| #define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK) |
| #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U) |
| #define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U) |
| /*! CSC_DATA_SWIZZLE |
| * 0b00..No byte swapping.(Little endian) |
| * 0b00..Little Endian byte ordering (same as NO_SWAP). |
| * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). |
| * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). |
| * 0b10..Swap half-words. |
| * 0b11..Swap bytes within each half-word. |
| */ |
| #define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK) |
| #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U) |
| #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U) |
| /*! INPUT_DATA_SWIZZLE |
| * 0b00..No byte swapping.(Little endian) |
| * 0b00..Little Endian byte ordering (same as NO_SWAP). |
| * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). |
| * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). |
| * 0b10..Swap half-words. |
| * 0b11..Swap bytes within each half-word. |
| */ |
| #define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK) |
| #define LCDIF_CTRL_DATA_SELECT_MASK (0x10000U) |
| #define LCDIF_CTRL_DATA_SELECT_SHIFT (16U) |
| /*! DATA_SELECT |
| * 0b0..Command Mode. LCD_RS signal is Low. |
| * 0b1..Data Mode. LCD_RS signal is High. |
| */ |
| #define LCDIF_CTRL_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SELECT_SHIFT)) & LCDIF_CTRL_DATA_SELECT_MASK) |
| #define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U) |
| #define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U) |
| #define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK) |
| #define LCDIF_CTRL_VSYNC_MODE_MASK (0x40000U) |
| #define LCDIF_CTRL_VSYNC_MODE_SHIFT (18U) |
| #define LCDIF_CTRL_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_VSYNC_MODE_MASK) |
| #define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U) |
| #define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U) |
| #define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK) |
| #define LCDIF_CTRL_DVI_MODE_MASK (0x100000U) |
| #define LCDIF_CTRL_DVI_MODE_SHIFT (20U) |
| #define LCDIF_CTRL_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DVI_MODE_SHIFT)) & LCDIF_CTRL_DVI_MODE_MASK) |
| #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U) |
| #define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U) |
| #define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK) |
| #define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U) |
| #define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U) |
| /*! DATA_SHIFT_DIR |
| * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. |
| * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. |
| */ |
| #define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK) |
| #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) |
| #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) |
| #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK) |
| #define LCDIF_CTRL_READ_WRITEB_MASK (0x10000000U) |
| #define LCDIF_CTRL_READ_WRITEB_SHIFT (28U) |
| #define LCDIF_CTRL_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_READ_WRITEB_SHIFT)) & LCDIF_CTRL_READ_WRITEB_MASK) |
| #define LCDIF_CTRL_YCBCR422_INPUT_MASK (0x20000000U) |
| #define LCDIF_CTRL_YCBCR422_INPUT_SHIFT (29U) |
| #define LCDIF_CTRL_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_YCBCR422_INPUT_MASK) |
| #define LCDIF_CTRL_CLKGATE_MASK (0x40000000U) |
| #define LCDIF_CTRL_CLKGATE_SHIFT (30U) |
| #define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK) |
| #define LCDIF_CTRL_SFTRST_MASK (0x80000000U) |
| #define LCDIF_CTRL_SFTRST_SHIFT (31U) |
| #define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL_SET - LCDIF General Control Register */ |
| /*! @{ */ |
| #define LCDIF_CTRL_SET_RUN_MASK (0x1U) |
| #define LCDIF_CTRL_SET_RUN_SHIFT (0U) |
| #define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK) |
| #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U) |
| #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U) |
| /*! DATA_FORMAT_24_BIT |
| * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. |
| * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. |
| */ |
| #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK) |
| #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U) |
| #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U) |
| /*! DATA_FORMAT_18_BIT |
| * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. |
| * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. |
| */ |
| #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK) |
| #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U) |
| #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U) |
| #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK) |
| #define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U) |
| #define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U) |
| #define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK) |
| #define LCDIF_CTRL_SET_MASTER_MASK (0x20U) |
| #define LCDIF_CTRL_SET_MASTER_SHIFT (5U) |
| #define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK) |
| #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U) |
| #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U) |
| #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK) |
| #define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK (0x80U) |
| #define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT (7U) |
| #define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK) |
| #define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U) |
| #define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U) |
| /*! WORD_LENGTH |
| * 0b00..Input data is 16 bits per pixel. |
| * 0b01..Input data is 8 bits wide. |
| * 0b10..Input data is 18 bits per pixel. |
| * 0b11..Input data is 24 bits per pixel. |
| */ |
| #define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK) |
| #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U) |
| #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U) |
| /*! LCD_DATABUS_WIDTH |
| * 0b00..16-bit data bus mode. |
| * 0b01..8-bit data bus mode. |
| * 0b10..18-bit data bus mode. |
| * 0b11..24-bit data bus mode. |
| */ |
| #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK) |
| #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U) |
| #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U) |
| /*! CSC_DATA_SWIZZLE |
| * 0b00..No byte swapping.(Little endian) |
| * 0b00..Little Endian byte ordering (same as NO_SWAP). |
| * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). |
| * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). |
| * 0b10..Swap half-words. |
| * 0b11..Swap bytes within each half-word. |
| */ |
| #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK) |
| #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U) |
| #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U) |
| /*! INPUT_DATA_SWIZZLE |
| * 0b00..No byte swapping.(Little endian) |
| * 0b00..Little Endian byte ordering (same as NO_SWAP). |
| * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). |
| * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). |
| * 0b10..Swap half-words. |
| * 0b11..Swap bytes within each half-word. |
| */ |
| #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK) |
| #define LCDIF_CTRL_SET_DATA_SELECT_MASK (0x10000U) |
| #define LCDIF_CTRL_SET_DATA_SELECT_SHIFT (16U) |
| /*! DATA_SELECT |
| * 0b0..Command Mode. LCD_RS signal is Low. |
| * 0b1..Data Mode. LCD_RS signal is High. |
| */ |
| #define LCDIF_CTRL_SET_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SELECT_SHIFT)) & LCDIF_CTRL_SET_DATA_SELECT_MASK) |
| #define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U) |
| #define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U) |
| #define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK) |
| #define LCDIF_CTRL_SET_VSYNC_MODE_MASK (0x40000U) |
| #define LCDIF_CTRL_SET_VSYNC_MODE_SHIFT (18U) |
| #define LCDIF_CTRL_SET_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_SET_VSYNC_MODE_MASK) |
| #define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U) |
| #define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U) |
| #define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK) |
| #define LCDIF_CTRL_SET_DVI_MODE_MASK (0x100000U) |
| #define LCDIF_CTRL_SET_DVI_MODE_SHIFT (20U) |
| #define LCDIF_CTRL_SET_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DVI_MODE_SHIFT)) & LCDIF_CTRL_SET_DVI_MODE_MASK) |
| #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U) |
| #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U) |
| #define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK) |
| #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U) |
| #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U) |
| /*! DATA_SHIFT_DIR |
| * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. |
| * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. |
| */ |
| #define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK) |
| #define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) |
| #define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) |
| #define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK) |
| #define LCDIF_CTRL_SET_READ_WRITEB_MASK (0x10000000U) |
| #define LCDIF_CTRL_SET_READ_WRITEB_SHIFT (28U) |
| #define LCDIF_CTRL_SET_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_READ_WRITEB_SHIFT)) & LCDIF_CTRL_SET_READ_WRITEB_MASK) |
| #define LCDIF_CTRL_SET_YCBCR422_INPUT_MASK (0x20000000U) |
| #define LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT (29U) |
| #define LCDIF_CTRL_SET_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_SET_YCBCR422_INPUT_MASK) |
| #define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U) |
| #define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U) |
| #define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK) |
| #define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U) |
| #define LCDIF_CTRL_SET_SFTRST_SHIFT (31U) |
| #define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL_CLR - LCDIF General Control Register */ |
| /*! @{ */ |
| #define LCDIF_CTRL_CLR_RUN_MASK (0x1U) |
| #define LCDIF_CTRL_CLR_RUN_SHIFT (0U) |
| #define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK) |
| #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U) |
| #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U) |
| /*! DATA_FORMAT_24_BIT |
| * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. |
| * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. |
| */ |
| #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK) |
| #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U) |
| #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U) |
| /*! DATA_FORMAT_18_BIT |
| * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. |
| * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. |
| */ |
| #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK) |
| #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U) |
| #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U) |
| #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK) |
| #define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U) |
| #define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U) |
| #define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK) |
| #define LCDIF_CTRL_CLR_MASTER_MASK (0x20U) |
| #define LCDIF_CTRL_CLR_MASTER_SHIFT (5U) |
| #define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK) |
| #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U) |
| #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U) |
| #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK) |
| #define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK (0x80U) |
| #define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT (7U) |
| #define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK) |
| #define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U) |
| #define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U) |
| /*! WORD_LENGTH |
| * 0b00..Input data is 16 bits per pixel. |
| * 0b01..Input data is 8 bits wide. |
| * 0b10..Input data is 18 bits per pixel. |
| * 0b11..Input data is 24 bits per pixel. |
| */ |
| #define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK) |
| #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U) |
| #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U) |
| /*! LCD_DATABUS_WIDTH |
| * 0b00..16-bit data bus mode. |
| * 0b01..8-bit data bus mode. |
| * 0b10..18-bit data bus mode. |
| * 0b11..24-bit data bus mode. |
| */ |
| #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK) |
| #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U) |
| #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U) |
| /*! CSC_DATA_SWIZZLE |
| * 0b00..No byte swapping.(Little endian) |
| * 0b00..Little Endian byte ordering (same as NO_SWAP). |
| * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). |
| * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). |
| * 0b10..Swap half-words. |
| * 0b11..Swap bytes within each half-word. |
| */ |
| #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK) |
| #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U) |
| #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U) |
| /*! INPUT_DATA_SWIZZLE |
| * 0b00..No byte swapping.(Little endian) |
| * 0b00..Little Endian byte ordering (same as NO_SWAP). |
| * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). |
| * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). |
| * 0b10..Swap half-words. |
| * 0b11..Swap bytes within each half-word. |
| */ |
| #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK) |
| #define LCDIF_CTRL_CLR_DATA_SELECT_MASK (0x10000U) |
| #define LCDIF_CTRL_CLR_DATA_SELECT_SHIFT (16U) |
| /*! DATA_SELECT |
| * 0b0..Command Mode. LCD_RS signal is Low. |
| * 0b1..Data Mode. LCD_RS signal is High. |
| */ |
| #define LCDIF_CTRL_CLR_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SELECT_SHIFT)) & LCDIF_CTRL_CLR_DATA_SELECT_MASK) |
| #define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U) |
| #define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U) |
| #define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK) |
| #define LCDIF_CTRL_CLR_VSYNC_MODE_MASK (0x40000U) |
| #define LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT (18U) |
| #define LCDIF_CTRL_CLR_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_CLR_VSYNC_MODE_MASK) |
| #define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U) |
| #define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U) |
| #define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK) |
| #define LCDIF_CTRL_CLR_DVI_MODE_MASK (0x100000U) |
| #define LCDIF_CTRL_CLR_DVI_MODE_SHIFT (20U) |
| #define LCDIF_CTRL_CLR_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DVI_MODE_SHIFT)) & LCDIF_CTRL_CLR_DVI_MODE_MASK) |
| #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U) |
| #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U) |
| #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK) |
| #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U) |
| #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U) |
| /*! DATA_SHIFT_DIR |
| * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. |
| * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. |
| */ |
| #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK) |
| #define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) |
| #define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) |
| #define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK) |
| #define LCDIF_CTRL_CLR_READ_WRITEB_MASK (0x10000000U) |
| #define LCDIF_CTRL_CLR_READ_WRITEB_SHIFT (28U) |
| #define LCDIF_CTRL_CLR_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_READ_WRITEB_SHIFT)) & LCDIF_CTRL_CLR_READ_WRITEB_MASK) |
| #define LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK (0x20000000U) |
| #define LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT (29U) |
| #define LCDIF_CTRL_CLR_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK) |
| #define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U) |
| #define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U) |
| #define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK) |
| #define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U) |
| #define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U) |
| #define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL_TOG - LCDIF General Control Register */ |
| /*! @{ */ |
| #define LCDIF_CTRL_TOG_RUN_MASK (0x1U) |
| #define LCDIF_CTRL_TOG_RUN_SHIFT (0U) |
| #define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK) |
| #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U) |
| #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U) |
| /*! DATA_FORMAT_24_BIT |
| * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. |
| * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. |
| */ |
| #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK) |
| #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U) |
| #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U) |
| /*! DATA_FORMAT_18_BIT |
| * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. |
| * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. |
| */ |
| #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK) |
| #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U) |
| #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U) |
| #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK) |
| #define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U) |
| #define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U) |
| #define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK) |
| #define LCDIF_CTRL_TOG_MASTER_MASK (0x20U) |
| #define LCDIF_CTRL_TOG_MASTER_SHIFT (5U) |
| #define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK) |
| #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U) |
| #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U) |
| #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK) |
| #define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK (0x80U) |
| #define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT (7U) |
| #define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK) |
| #define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U) |
| #define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U) |
| /*! WORD_LENGTH |
| * 0b00..Input data is 16 bits per pixel. |
| * 0b01..Input data is 8 bits wide. |
| * 0b10..Input data is 18 bits per pixel. |
| * 0b11..Input data is 24 bits per pixel. |
| */ |
| #define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK) |
| #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U) |
| #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U) |
| /*! LCD_DATABUS_WIDTH |
| * 0b00..16-bit data bus mode. |
| * 0b01..8-bit data bus mode. |
| * 0b10..18-bit data bus mode. |
| * 0b11..24-bit data bus mode. |
| */ |
| #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK) |
| #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U) |
| #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U) |
| /*! CSC_DATA_SWIZZLE |
| * 0b00..No byte swapping.(Little endian) |
| * 0b00..Little Endian byte ordering (same as NO_SWAP). |
| * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). |
| * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). |
| * 0b10..Swap half-words. |
| * 0b11..Swap bytes within each half-word. |
| */ |
| #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK) |
| #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U) |
| #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U) |
| /*! INPUT_DATA_SWIZZLE |
| * 0b00..No byte swapping.(Little endian) |
| * 0b00..Little Endian byte ordering (same as NO_SWAP). |
| * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). |
| * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). |
| * 0b10..Swap half-words. |
| * 0b11..Swap bytes within each half-word. |
| */ |
| #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK) |
| #define LCDIF_CTRL_TOG_DATA_SELECT_MASK (0x10000U) |
| #define LCDIF_CTRL_TOG_DATA_SELECT_SHIFT (16U) |
| /*! DATA_SELECT |
| * 0b0..Command Mode. LCD_RS signal is Low. |
| * 0b1..Data Mode. LCD_RS signal is High. |
| */ |
| #define LCDIF_CTRL_TOG_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SELECT_SHIFT)) & LCDIF_CTRL_TOG_DATA_SELECT_MASK) |
| #define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U) |
| #define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U) |
| #define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK) |
| #define LCDIF_CTRL_TOG_VSYNC_MODE_MASK (0x40000U) |
| #define LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT (18U) |
| #define LCDIF_CTRL_TOG_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_TOG_VSYNC_MODE_MASK) |
| #define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U) |
| #define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U) |
| #define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK) |
| #define LCDIF_CTRL_TOG_DVI_MODE_MASK (0x100000U) |
| #define LCDIF_CTRL_TOG_DVI_MODE_SHIFT (20U) |
| #define LCDIF_CTRL_TOG_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DVI_MODE_SHIFT)) & LCDIF_CTRL_TOG_DVI_MODE_MASK) |
| #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U) |
| #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U) |
| #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK) |
| #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U) |
| #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U) |
| /*! DATA_SHIFT_DIR |
| * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. |
| * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. |
| */ |
| #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK) |
| #define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) |
| #define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) |
| #define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK) |
| #define LCDIF_CTRL_TOG_READ_WRITEB_MASK (0x10000000U) |
| #define LCDIF_CTRL_TOG_READ_WRITEB_SHIFT (28U) |
| #define LCDIF_CTRL_TOG_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_READ_WRITEB_SHIFT)) & LCDIF_CTRL_TOG_READ_WRITEB_MASK) |
| #define LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK (0x20000000U) |
| #define LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT (29U) |
| #define LCDIF_CTRL_TOG_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK) |
| #define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U) |
| #define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U) |
| #define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK) |
| #define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U) |
| #define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U) |
| #define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL1 - LCDIF General Control1 Register */ |
| /*! @{ */ |
| #define LCDIF_CTRL1_RESET_MASK (0x1U) |
| #define LCDIF_CTRL1_RESET_SHIFT (0U) |
| /*! RESET |
| * 0b0..LCD_RESET output signal is low. |
| * 0b1..LCD_RESET output signal is high. |
| */ |
| #define LCDIF_CTRL1_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RESET_SHIFT)) & LCDIF_CTRL1_RESET_MASK) |
| #define LCDIF_CTRL1_MODE86_MASK (0x2U) |
| #define LCDIF_CTRL1_MODE86_SHIFT (1U) |
| /*! MODE86 |
| * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. |
| * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. |
| */ |
| #define LCDIF_CTRL1_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_MODE86_SHIFT)) & LCDIF_CTRL1_MODE86_MASK) |
| #define LCDIF_CTRL1_BUSY_ENABLE_MASK (0x4U) |
| #define LCDIF_CTRL1_BUSY_ENABLE_SHIFT (2U) |
| /*! BUSY_ENABLE |
| * 0b0..The busy signal from the LCD controller will be ignored. |
| * 0b1..Enable the use of the busy signal from the LCD controller. |
| */ |
| #define LCDIF_CTRL1_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_BUSY_ENABLE_MASK) |
| #define LCDIF_CTRL1_RSRVD0_MASK (0xF8U) |
| #define LCDIF_CTRL1_RSRVD0_SHIFT (3U) |
| #define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK) |
| #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U) |
| #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U) |
| /*! VSYNC_EDGE_IRQ |
| * 0b0..No Interrupt Request Pending. |
| * 0b1..Interrupt Request Pending. |
| */ |
| #define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) |
| #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U) |
| #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U) |
| /*! CUR_FRAME_DONE_IRQ |
| * 0b0..No Interrupt Request Pending. |
| * 0b1..Interrupt Request Pending. |
| */ |
| #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK) |
| #define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U) |
| #define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U) |
| /*! UNDERFLOW_IRQ |
| * 0b0..No Interrupt Request Pending. |
| * 0b1..Interrupt Request Pending. |
| */ |
| #define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK) |
| #define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U) |
| #define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U) |
| /*! OVERFLOW_IRQ |
| * 0b0..No Interrupt Request Pending. |
| * 0b1..Interrupt Request Pending. |
| */ |
| #define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK) |
| #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) |
| #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U) |
| #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK) |
| #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) |
| #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) |
| #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK) |
| #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U) |
| #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U) |
| #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK) |
| #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U) |
| #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U) |
| #define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK) |
| #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U) |
| #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U) |
| #define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK) |
| #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) |
| #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) |
| #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK) |
| #define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U) |
| #define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U) |
| #define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK) |
| #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) |
| #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) |
| #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK) |
| #define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U) |
| #define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U) |
| #define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK) |
| #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) |
| #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U) |
| #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK) |
| #define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U) |
| #define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U) |
| /*! BM_ERROR_IRQ |
| * 0b0..No Interrupt Request Pending. |
| * 0b1..Interrupt Request Pending. |
| */ |
| #define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK) |
| #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U) |
| #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U) |
| #define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK) |
| #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK (0x8000000U) |
| #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT (27U) |
| #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL1_SET - LCDIF General Control1 Register */ |
| /*! @{ */ |
| #define LCDIF_CTRL1_SET_RESET_MASK (0x1U) |
| #define LCDIF_CTRL1_SET_RESET_SHIFT (0U) |
| /*! RESET |
| * 0b0..LCD_RESET output signal is low. |
| * 0b1..LCD_RESET output signal is high. |
| */ |
| #define LCDIF_CTRL1_SET_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RESET_SHIFT)) & LCDIF_CTRL1_SET_RESET_MASK) |
| #define LCDIF_CTRL1_SET_MODE86_MASK (0x2U) |
| #define LCDIF_CTRL1_SET_MODE86_SHIFT (1U) |
| /*! MODE86 |
| * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. |
| * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. |
| */ |
| #define LCDIF_CTRL1_SET_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_MODE86_SHIFT)) & LCDIF_CTRL1_SET_MODE86_MASK) |
| #define LCDIF_CTRL1_SET_BUSY_ENABLE_MASK (0x4U) |
| #define LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT (2U) |
| /*! BUSY_ENABLE |
| * 0b0..The busy signal from the LCD controller will be ignored. |
| * 0b1..Enable the use of the busy signal from the LCD controller. |
| */ |
| #define LCDIF_CTRL1_SET_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_SET_BUSY_ENABLE_MASK) |
| #define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U) |
| #define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U) |
| #define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK) |
| #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U) |
| #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U) |
| /*! VSYNC_EDGE_IRQ |
| * 0b0..No Interrupt Request Pending. |
| * 0b1..Interrupt Request Pending. |
| */ |
| #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK) |
| #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U) |
| #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U) |
| /*! CUR_FRAME_DONE_IRQ |
| * 0b0..No Interrupt Request Pending. |
| * 0b1..Interrupt Request Pending. |
| */ |
| #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK) |
| #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U) |
| #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U) |
| /*! UNDERFLOW_IRQ |
| * 0b0..No Interrupt Request Pending. |
| * 0b1..Interrupt Request Pending. |
| */ |
| #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK) |
| #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U) |
| #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U) |
| /*! OVERFLOW_IRQ |
| * 0b0..No Interrupt Request Pending. |
| * 0b1..Interrupt Request Pending. |
| */ |
| #define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK) |
| #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) |
| #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U) |
| #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK) |
| #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) |
| #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) |
| #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK) |
| #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U) |
| #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U) |
| #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK) |
| #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U) |
| #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U) |
| #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK) |
| #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U) |
| #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U) |
| #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK) |
| #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) |
| #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) |
| #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK) |
| #define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U) |
| #define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U) |
| #define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK) |
| #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) |
| #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) |
| #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK) |
| #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U) |
| #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U) |
| #define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK) |
| #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) |
| #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U) |
| #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK) |
| #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U) |
| #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U) |
| /*! BM_ERROR_IRQ |
| * 0b0..No Interrupt Request Pending. |
| * 0b1..Interrupt Request Pending. |
| */ |
| #define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK) |
| #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U) |
| #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U) |
| #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK) |
| #define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK (0x8000000U) |
| #define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT (27U) |
| #define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL1_CLR - LCDIF General Control1 Register */ |
| /*! @{ */ |
| #define LCDIF_CTRL1_CLR_RESET_MASK (0x1U) |
| #define LCDIF_CTRL1_CLR_RESET_SHIFT (0U) |
| /*! RESET |
| * 0b0..LCD_RESET output signal is low. |
| * 0b1..LCD_RESET output signal is high. |
| */ |
| #define LCDIF_CTRL1_CLR_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RESET_SHIFT)) & LCDIF_CTRL1_CLR_RESET_MASK) |
| #define LCDIF_CTRL1_CLR_MODE86_MASK (0x2U) |
| #define LCDIF_CTRL1_CLR_MODE86_SHIFT (1U) |
| /*! MODE86 |
| * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. |
| * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. |
| */ |
| #define LCDIF_CTRL1_CLR_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_MODE86_SHIFT)) & LCDIF_CTRL1_CLR_MODE86_MASK) |
| #define LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK (0x4U) |
| #define LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT (2U) |
| /*! BUSY_ENABLE |
| * 0b0..The busy signal from the LCD controller will be ignored. |
| * 0b1..Enable the use of the busy signal from the LCD controller. |
| */ |
| #define LCDIF_CTRL1_CLR_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK) |
| #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) |
| #define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U) |
| #define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK) |
| #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U) |
| #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U) |
| /*! VSYNC_EDGE_IRQ |
| * 0b0..No Interrupt Request Pending. |
| * 0b1..Interrupt Request Pending. |
| */ |
| #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK) |
| #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U) |
| #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U) |
| /*! CUR_FRAME_DONE_IRQ |
| * 0b0..No Interrupt Request Pending. |
| * 0b1..Interrupt Request Pending. |
| */ |
| #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK) |
| #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U) |
| #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U) |
| /*! UNDERFLOW_IRQ |
| * 0b0..No Interrupt Request Pending. |
| * 0b1..Interrupt Request Pending. |
| */ |
| #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK) |
| #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U) |
| #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U) |
| /*! OVERFLOW_IRQ |
| * 0b0..No Interrupt Request Pending. |
| * 0b1..Interrupt Request Pending. |
| */ |
| #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK) |
| #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) |
| #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U) |
| #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK) |
| #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) |
| #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) |
| #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK) |
| #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U) |
| #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U) |
| #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK) |
| #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U) |
| #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U) |
| #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK) |
| #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U) |
| #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U) |
| #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK) |
| #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) |
| #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) |
| #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK) |
| #define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U) |
| #define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U) |
| #define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK) |
| #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) |
| #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) |
| #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK) |
| #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U) |
| #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U) |
| #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK) |
| #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) |
| #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U) |
| #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK) |
| #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U) |
| #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U) |
| /*! BM_ERROR_IRQ |
| * 0b0..No Interrupt Request Pending. |
| * 0b1..Interrupt Request Pending. |
| */ |
| #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK) |
| #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U) |
| #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U) |
| #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK) |
| #define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK (0x8000000U) |
| #define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT (27U) |
| #define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL1_TOG - LCDIF General Control1 Register */ |
| /*! @{ */ |
| #define LCDIF_CTRL1_TOG_RESET_MASK (0x1U) |
| #define LCDIF_CTRL1_TOG_RESET_SHIFT (0U) |
| /*! RESET |
| * 0b0..LCD_RESET output signal is low. |
| * 0b1..LCD_RESET output signal is high. |
| */ |
| #define LCDIF_CTRL1_TOG_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RESET_SHIFT)) & LCDIF_CTRL1_TOG_RESET_MASK) |
| #define LCDIF_CTRL1_TOG_MODE86_MASK (0x2U) |
| #define LCDIF_CTRL1_TOG_MODE86_SHIFT (1U) |
| /*! MODE86 |
| * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. |
| * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. |
| */ |
| #define LCDIF_CTRL1_TOG_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_MODE86_SHIFT)) & LCDIF_CTRL1_TOG_MODE86_MASK) |
| #define LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK (0x4U) |
| #define LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT (2U) |
| /*! BUSY_ENABLE |
| * 0b0..The busy signal from the LCD controller will be ignored. |
| * 0b1..Enable the use of the busy signal from the LCD controller. |
| */ |
| #define LCDIF_CTRL1_TOG_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK) |
| #define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U) |
| #define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U) |
| #define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK) |
| #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U) |
| #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U) |
| /*! VSYNC_EDGE_IRQ |
| * 0b0..No Interrupt Request Pending. |
| * 0b1..Interrupt Request Pending. |
| */ |
| #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK) |
| #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U) |
| #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U) |
| /*! CUR_FRAME_DONE_IRQ |
| * 0b0..No Interrupt Request Pending. |
| * 0b1..Interrupt Request Pending. |
| */ |
| #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK) |
| #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U) |
| #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U) |
| /*! UNDERFLOW_IRQ |
| * 0b0..No Interrupt Request Pending. |
| * 0b1..Interrupt Request Pending. |
| */ |
| #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK) |
| #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U) |
| #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U) |
| /*! OVERFLOW_IRQ |
| * 0b0..No Interrupt Request Pending. |
| * 0b1..Interrupt Request Pending. |
| */ |
| #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK) |
| #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) |
| #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U) |
| #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK) |
| #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) |
| #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) |
| #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK) |
| #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U) |
| #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U) |
| #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK) |
| #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U) |
| #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U) |
| #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK) |
| #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U) |
| #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U) |
| #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK) |
| #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) |
| #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) |
| #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK) |
| #define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U) |
| #define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U) |
| #define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK) |
| #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) |
| #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) |
| #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK) |
| #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U) |
| #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U) |
| #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK) |
| #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) |
| #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U) |
| #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK) |
| #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U) |
| #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U) |
| /*! BM_ERROR_IRQ |
| * 0b0..No Interrupt Request Pending. |
| * 0b1..Interrupt Request Pending. |
| */ |
| #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK) |
| #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U) |
| #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U) |
| #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK) |
| #define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK (0x8000000U) |
| #define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT (27U) |
| #define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL2 - LCDIF General Control2 Register */ |
| /*! @{ */ |
| #define LCDIF_CTRL2_RSRVD0_MASK (0x1U) |
| #define LCDIF_CTRL2_RSRVD0_SHIFT (0U) |
| #define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK) |
| #define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0xEU) |
| #define LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT (1U) |
| #define LCDIF_CTRL2_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK) |
| #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) |
| #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) |
| #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK) |
| #define LCDIF_CTRL2_RSRVD1_MASK (0x80U) |
| #define LCDIF_CTRL2_RSRVD1_SHIFT (7U) |
| #define LCDIF_CTRL2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD1_SHIFT)) & LCDIF_CTRL2_RSRVD1_MASK) |
| #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK (0x100U) |
| #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT (8U) |
| #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK) |
| #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) |
| #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) |
| #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) |
| #define LCDIF_CTRL2_READ_PACK_DIR_MASK (0x400U) |
| #define LCDIF_CTRL2_READ_PACK_DIR_SHIFT (10U) |
| #define LCDIF_CTRL2_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_READ_PACK_DIR_MASK) |
| #define LCDIF_CTRL2_RSRVD2_MASK (0x800U) |
| #define LCDIF_CTRL2_RSRVD2_SHIFT (11U) |
| #define LCDIF_CTRL2_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD2_SHIFT)) & LCDIF_CTRL2_RSRVD2_MASK) |
| #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U) |
| #define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U) |
| /*! EVEN_LINE_PATTERN |
| * 0b000..RGB |
| * 0b001..RBG |
| * 0b010..GBR |
| * 0b011..GRB |
| * 0b100..BRG |
| * 0b101..BGR |
| */ |
| #define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK) |
| #define LCDIF_CTRL2_RSRVD3_MASK (0x8000U) |
| #define LCDIF_CTRL2_RSRVD3_SHIFT (15U) |
| #define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK) |
| #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U) |
| #define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U) |
| /*! ODD_LINE_PATTERN |
| * 0b000..RGB |
| * 0b001..RBG |
| * 0b010..GBR |
| * 0b011..GRB |
| * 0b100..BRG |
| * 0b101..BGR |
| */ |
| #define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK) |
| #define LCDIF_CTRL2_RSRVD4_MASK (0x80000U) |
| #define LCDIF_CTRL2_RSRVD4_SHIFT (19U) |
| #define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK) |
| #define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U) |
| #define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U) |
| #define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK) |
| #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U) |
| #define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U) |
| /*! OUTSTANDING_REQS |
| * 0b000..REQ_1 |
| * 0b001..REQ_2 |
| * 0b010..REQ_4 |
| * 0b011..REQ_8 |
| * 0b100..REQ_16 |
| */ |
| #define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK) |
| #define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U) |
| #define LCDIF_CTRL2_RSRVD5_SHIFT (24U) |
| #define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL2_SET - LCDIF General Control2 Register */ |
| /*! @{ */ |
| #define LCDIF_CTRL2_SET_RSRVD0_MASK (0x1U) |
| #define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U) |
| #define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK) |
| #define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK (0xEU) |
| #define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT (1U) |
| #define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK) |
| #define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) |
| #define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) |
| #define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK) |
| #define LCDIF_CTRL2_SET_RSRVD1_MASK (0x80U) |
| #define LCDIF_CTRL2_SET_RSRVD1_SHIFT (7U) |
| #define LCDIF_CTRL2_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD1_SHIFT)) & LCDIF_CTRL2_SET_RSRVD1_MASK) |
| #define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK (0x100U) |
| #define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT (8U) |
| #define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK) |
| #define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) |
| #define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) |
| #define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) |
| #define LCDIF_CTRL2_SET_READ_PACK_DIR_MASK (0x400U) |
| #define LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT (10U) |
| #define LCDIF_CTRL2_SET_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_SET_READ_PACK_DIR_MASK) |
| #define LCDIF_CTRL2_SET_RSRVD2_MASK (0x800U) |
| #define LCDIF_CTRL2_SET_RSRVD2_SHIFT (11U) |
| #define LCDIF_CTRL2_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD2_SHIFT)) & LCDIF_CTRL2_SET_RSRVD2_MASK) |
| #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U) |
| #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U) |
| /*! EVEN_LINE_PATTERN |
| * 0b000..RGB |
| * 0b001..RBG |
| * 0b010..GBR |
| * 0b011..GRB |
| * 0b100..BRG |
| * 0b101..BGR |
| */ |
| #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK) |
| #define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U) |
| #define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U) |
| #define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK) |
| #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U) |
| #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U) |
| /*! ODD_LINE_PATTERN |
| * 0b000..RGB |
| * 0b001..RBG |
| * 0b010..GBR |
| * 0b011..GRB |
| * 0b100..BRG |
| * 0b101..BGR |
| */ |
| #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK) |
| #define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U) |
| #define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U) |
| #define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK) |
| #define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U) |
| #define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U) |
| #define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK) |
| #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U) |
| #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U) |
| /*! OUTSTANDING_REQS |
| * 0b000..REQ_1 |
| * 0b001..REQ_2 |
| * 0b010..REQ_4 |
| * 0b011..REQ_8 |
| * 0b100..REQ_16 |
| */ |
| #define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK) |
| #define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U) |
| #define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U) |
| #define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL2_CLR - LCDIF General Control2 Register */ |
| /*! @{ */ |
| #define LCDIF_CTRL2_CLR_RSRVD0_MASK (0x1U) |
| #define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U) |
| #define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK) |
| #define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK (0xEU) |
| #define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT (1U) |
| #define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK) |
| #define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) |
| #define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) |
| #define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK) |
| #define LCDIF_CTRL2_CLR_RSRVD1_MASK (0x80U) |
| #define LCDIF_CTRL2_CLR_RSRVD1_SHIFT (7U) |
| #define LCDIF_CTRL2_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD1_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD1_MASK) |
| #define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK (0x100U) |
| #define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT (8U) |
| #define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK) |
| #define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) |
| #define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) |
| #define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) |
| #define LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK (0x400U) |
| #define LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT (10U) |
| #define LCDIF_CTRL2_CLR_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK) |
| #define LCDIF_CTRL2_CLR_RSRVD2_MASK (0x800U) |
| #define LCDIF_CTRL2_CLR_RSRVD2_SHIFT (11U) |
| #define LCDIF_CTRL2_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD2_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD2_MASK) |
| #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U) |
| #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U) |
| /*! EVEN_LINE_PATTERN |
| * 0b000..RGB |
| * 0b001..RBG |
| * 0b010..GBR |
| * 0b011..GRB |
| * 0b100..BRG |
| * 0b101..BGR |
| */ |
| #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK) |
| #define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U) |
| #define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U) |
| #define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK) |
| #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U) |
| #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U) |
| /*! ODD_LINE_PATTERN |
| * 0b000..RGB |
| * 0b001..RBG |
| * 0b010..GBR |
| * 0b011..GRB |
| * 0b100..BRG |
| * 0b101..BGR |
| */ |
| #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK) |
| #define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U) |
| #define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U) |
| #define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK) |
| #define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U) |
| #define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U) |
| #define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK) |
| #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U) |
| #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U) |
| /*! OUTSTANDING_REQS |
| * 0b000..REQ_1 |
| * 0b001..REQ_2 |
| * 0b010..REQ_4 |
| * 0b011..REQ_8 |
| * 0b100..REQ_16 |
| */ |
| #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK) |
| #define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U) |
| #define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U) |
| #define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL2_TOG - LCDIF General Control2 Register */ |
| /*! @{ */ |
| #define LCDIF_CTRL2_TOG_RSRVD0_MASK (0x1U) |
| #define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U) |
| #define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK) |
| #define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK (0xEU) |
| #define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT (1U) |
| #define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK) |
| #define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) |
| #define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) |
| #define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK) |
| #define LCDIF_CTRL2_TOG_RSRVD1_MASK (0x80U) |
| #define LCDIF_CTRL2_TOG_RSRVD1_SHIFT (7U) |
| #define LCDIF_CTRL2_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD1_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD1_MASK) |
| #define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK (0x100U) |
| #define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT (8U) |
| #define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK) |
| #define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) |
| #define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) |
| #define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) |
| #define LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK (0x400U) |
| #define LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT (10U) |
| #define LCDIF_CTRL2_TOG_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK) |
| #define LCDIF_CTRL2_TOG_RSRVD2_MASK (0x800U) |
| #define LCDIF_CTRL2_TOG_RSRVD2_SHIFT (11U) |
| #define LCDIF_CTRL2_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD2_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD2_MASK) |
| #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U) |
| #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U) |
| /*! EVEN_LINE_PATTERN |
| * 0b000..RGB |
| * 0b001..RBG |
| * 0b010..GBR |
| * 0b011..GRB |
| * 0b100..BRG |
| * 0b101..BGR |
| */ |
| #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK) |
| #define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U) |
| #define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U) |
| #define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK) |
| #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U) |
| #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U) |
| /*! ODD_LINE_PATTERN |
| * 0b000..RGB |
| * 0b001..RBG |
| * 0b010..GBR |
| * 0b011..GRB |
| * 0b100..BRG |
| * 0b101..BGR |
| */ |
| #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK) |
| #define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U) |
| #define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U) |
| #define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK) |
| #define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U) |
| #define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U) |
| #define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK) |
| #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U) |
| #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U) |
| /*! OUTSTANDING_REQS |
| * 0b000..REQ_1 |
| * 0b001..REQ_2 |
| * 0b010..REQ_4 |
| * 0b011..REQ_8 |
| * 0b100..REQ_16 |
| */ |
| #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK) |
| #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) |
| #define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U) |
| #define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK) |
| /*! @} */ |
| |
| /*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */ |
| /*! @{ */ |
| #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU) |
| #define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U) |
| #define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK) |
| #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U) |
| #define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U) |
| #define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK) |
| /*! @} */ |
| |
| /*! @name CUR_BUF - LCD Interface Current Buffer Address Register */ |
| /*! @{ */ |
| #define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU) |
| #define LCDIF_CUR_BUF_ADDR_SHIFT (0U) |
| #define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */ |
| /*! @{ */ |
| #define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) |
| #define LCDIF_NEXT_BUF_ADDR_SHIFT (0U) |
| #define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name TIMING - LCD Interface Timing Register */ |
| /*! @{ */ |
| #define LCDIF_TIMING_DATA_SETUP_MASK (0xFFU) |
| #define LCDIF_TIMING_DATA_SETUP_SHIFT (0U) |
| #define LCDIF_TIMING_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_SETUP_SHIFT)) & LCDIF_TIMING_DATA_SETUP_MASK) |
| #define LCDIF_TIMING_DATA_HOLD_MASK (0xFF00U) |
| #define LCDIF_TIMING_DATA_HOLD_SHIFT (8U) |
| #define LCDIF_TIMING_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_HOLD_SHIFT)) & LCDIF_TIMING_DATA_HOLD_MASK) |
| #define LCDIF_TIMING_CMD_SETUP_MASK (0xFF0000U) |
| #define LCDIF_TIMING_CMD_SETUP_SHIFT (16U) |
| #define LCDIF_TIMING_CMD_SETUP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_SETUP_SHIFT)) & LCDIF_TIMING_CMD_SETUP_MASK) |
| #define LCDIF_TIMING_CMD_HOLD_MASK (0xFF000000U) |
| #define LCDIF_TIMING_CMD_HOLD_SHIFT (24U) |
| #define LCDIF_TIMING_CMD_HOLD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_HOLD_SHIFT)) & LCDIF_TIMING_CMD_HOLD_MASK) |
| /*! @} */ |
| |
| /*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ |
| /*! @{ */ |
| #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) |
| #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U) |
| #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) |
| #define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U) |
| #define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U) |
| #define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK) |
| #define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U) |
| #define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U) |
| #define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK) |
| #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) |
| #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) |
| #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK) |
| #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U) |
| #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U) |
| #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK) |
| #define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U) |
| #define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U) |
| #define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK) |
| #define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U) |
| #define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U) |
| #define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK) |
| #define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U) |
| #define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U) |
| #define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK) |
| #define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U) |
| #define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U) |
| #define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK) |
| #define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U) |
| #define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U) |
| #define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK) |
| #define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U) |
| #define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U) |
| #define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK) |
| #define LCDIF_VDCTRL0_VSYNC_OEB_MASK (0x20000000U) |
| #define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT (29U) |
| /*! VSYNC_OEB |
| * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. |
| * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. |
| */ |
| #define LCDIF_VDCTRL0_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK) |
| #define LCDIF_VDCTRL0_RSRVD2_MASK (0xC0000000U) |
| #define LCDIF_VDCTRL0_RSRVD2_SHIFT (30U) |
| #define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK) |
| /*! @} */ |
| |
| /*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ |
| /*! @{ */ |
| #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) |
| #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U) |
| #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK) |
| #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U) |
| #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U) |
| #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK) |
| #define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U) |
| #define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U) |
| #define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK) |
| #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) |
| #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) |
| #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK) |
| #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U) |
| #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U) |
| #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK) |
| #define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U) |
| #define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U) |
| #define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK) |
| #define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U) |
| #define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U) |
| #define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK) |
| #define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U) |
| #define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U) |
| #define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK) |
| #define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U) |
| #define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U) |
| #define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK) |
| #define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U) |
| #define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U) |
| #define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK) |
| #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U) |
| #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U) |
| #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK) |
| #define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK (0x20000000U) |
| #define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT (29U) |
| /*! VSYNC_OEB |
| * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. |
| * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. |
| */ |
| #define LCDIF_VDCTRL0_SET_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK) |
| #define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xC0000000U) |
| #define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (30U) |
| #define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK) |
| /*! @} */ |
| |
| /*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ |
| /*! @{ */ |
| #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) |
| #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U) |
| #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK) |
| #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U) |
| #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U) |
| #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK) |
| #define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U) |
| #define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U) |
| #define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK) |
| #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) |
| #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) |
| #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK) |
| #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U) |
| #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U) |
| #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK) |
| #define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U) |
| #define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U) |
| #define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK) |
| #define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U) |
| #define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U) |
| #define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK) |
| #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U) |
| #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U) |
| #define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK) |
| #define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U) |
| #define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U) |
| #define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK) |
| #define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U) |
| #define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U) |
| #define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK) |
| #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U) |
| #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U) |
| #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK) |
| #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK (0x20000000U) |
| #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT (29U) |
| /*! VSYNC_OEB |
| * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. |
| * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. |
| */ |
| #define LCDIF_VDCTRL0_CLR_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK) |
| #define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xC0000000U) |
| #define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (30U) |
| #define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK) |
| /*! @} */ |
| |
| /*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ |
| /*! @{ */ |
| #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) |
| #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U) |
| #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK) |
| #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U) |
| #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U) |
| #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK) |
| #define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U) |
| #define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U) |
| #define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK) |
| #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) |
| #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) |
| #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK) |
| #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U) |
| #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U) |
| #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK) |
| #define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U) |
| #define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U) |
| #define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK) |
| #define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U) |
| #define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U) |
| #define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK) |
| #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U) |
| #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U) |
| #define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK) |
| #define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U) |
| #define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U) |
| #define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK) |
| #define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U) |
| #define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U) |
| #define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK) |
| #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U) |
| #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U) |
| #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK) |
| #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK (0x20000000U) |
| #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT (29U) |
| /*! VSYNC_OEB |
| * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. |
| * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. |
| */ |
| #define LCDIF_VDCTRL0_TOG_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK) |
| #define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xC0000000U) |
| #define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (30U) |
| #define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK) |
| /*! @} */ |
| |
| /*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */ |
| /*! @{ */ |
| #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU) |
| #define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U) |
| #define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) |
| /*! @} */ |
| |
| /*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */ |
| /*! @{ */ |
| #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU) |
| #define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U) |
| #define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) |
| #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U) |
| #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U) |
| #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) |
| /*! @} */ |
| |
| /*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */ |
| /*! @{ */ |
| #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU) |
| #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U) |
| #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) |
| #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U) |
| #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U) |
| #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK) |
| #define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U) |
| #define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U) |
| #define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK) |
| #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U) |
| #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U) |
| #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK) |
| #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) |
| #define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U) |
| #define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK) |
| /*! @} */ |
| |
| /*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */ |
| /*! @{ */ |
| #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU) |
| #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U) |
| #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) |
| #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U) |
| #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U) |
| #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK) |
| #define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U) |
| #define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U) |
| #define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK) |
| #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U) |
| #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U) |
| #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name DVICTRL0 - Digital Video Interface Control0 Register */ |
| /*! @{ */ |
| #define LCDIF_DVICTRL0_H_BLANKING_CNT_MASK (0xFFFU) |
| #define LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT (0U) |
| #define LCDIF_DVICTRL0_H_BLANKING_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT)) & LCDIF_DVICTRL0_H_BLANKING_CNT_MASK) |
| #define LCDIF_DVICTRL0_RSRVD0_MASK (0xF000U) |
| #define LCDIF_DVICTRL0_RSRVD0_SHIFT (12U) |
| #define LCDIF_DVICTRL0_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD0_SHIFT)) & LCDIF_DVICTRL0_RSRVD0_MASK) |
| #define LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK (0xFFF0000U) |
| #define LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT (16U) |
| #define LCDIF_DVICTRL0_H_ACTIVE_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT)) & LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK) |
| #define LCDIF_DVICTRL0_RSRVD1_MASK (0xF0000000U) |
| #define LCDIF_DVICTRL0_RSRVD1_SHIFT (28U) |
| #define LCDIF_DVICTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD1_SHIFT)) & LCDIF_DVICTRL0_RSRVD1_MASK) |
| /*! @} */ |
| |
| /*! @name DVICTRL1 - Digital Video Interface Control1 Register */ |
| /*! @{ */ |
| #define LCDIF_DVICTRL1_F2_START_LINE_MASK (0x3FFU) |
| #define LCDIF_DVICTRL1_F2_START_LINE_SHIFT (0U) |
| #define LCDIF_DVICTRL1_F2_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F2_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F2_START_LINE_MASK) |
| #define LCDIF_DVICTRL1_F1_END_LINE_MASK (0xFFC00U) |
| #define LCDIF_DVICTRL1_F1_END_LINE_SHIFT (10U) |
| #define LCDIF_DVICTRL1_F1_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_END_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_END_LINE_MASK) |
| #define LCDIF_DVICTRL1_F1_START_LINE_MASK (0x3FF00000U) |
| #define LCDIF_DVICTRL1_F1_START_LINE_SHIFT (20U) |
| #define LCDIF_DVICTRL1_F1_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_START_LINE_MASK) |
| #define LCDIF_DVICTRL1_RSRVD0_MASK (0xC0000000U) |
| #define LCDIF_DVICTRL1_RSRVD0_SHIFT (30U) |
| #define LCDIF_DVICTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_RSRVD0_SHIFT)) & LCDIF_DVICTRL1_RSRVD0_MASK) |
| /*! @} */ |
| |
| /*! @name DVICTRL2 - Digital Video Interface Control2 Register */ |
| /*! @{ */ |
| #define LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK (0x3FFU) |
| #define LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT (0U) |
| #define LCDIF_DVICTRL2_V1_BLANK_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK) |
| #define LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK (0xFFC00U) |
| #define LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT (10U) |
| #define LCDIF_DVICTRL2_V1_BLANK_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT)) & LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK) |
| #define LCDIF_DVICTRL2_F2_END_LINE_MASK (0x3FF00000U) |
| #define LCDIF_DVICTRL2_F2_END_LINE_SHIFT (20U) |
| #define LCDIF_DVICTRL2_F2_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_F2_END_LINE_SHIFT)) & LCDIF_DVICTRL2_F2_END_LINE_MASK) |
| #define LCDIF_DVICTRL2_RSRVD0_MASK (0xC0000000U) |
| #define LCDIF_DVICTRL2_RSRVD0_SHIFT (30U) |
| #define LCDIF_DVICTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_RSRVD0_SHIFT)) & LCDIF_DVICTRL2_RSRVD0_MASK) |
| /*! @} */ |
| |
| /*! @name DVICTRL3 - Digital Video Interface Control3 Register */ |
| /*! @{ */ |
| #define LCDIF_DVICTRL3_V_LINES_CNT_MASK (0x3FFU) |
| #define LCDIF_DVICTRL3_V_LINES_CNT_SHIFT (0U) |
| #define LCDIF_DVICTRL3_V_LINES_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V_LINES_CNT_SHIFT)) & LCDIF_DVICTRL3_V_LINES_CNT_MASK) |
| #define LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK (0xFFC00U) |
| #define LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT (10U) |
| #define LCDIF_DVICTRL3_V2_BLANK_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK) |
| #define LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK (0x3FF00000U) |
| #define LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT (20U) |
| #define LCDIF_DVICTRL3_V2_BLANK_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT)) & LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK) |
| #define LCDIF_DVICTRL3_RSRVD0_MASK (0xC0000000U) |
| #define LCDIF_DVICTRL3_RSRVD0_SHIFT (30U) |
| #define LCDIF_DVICTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_RSRVD0_SHIFT)) & LCDIF_DVICTRL3_RSRVD0_MASK) |
| /*! @} */ |
| |
| /*! @name DVICTRL4 - Digital Video Interface Control4 Register */ |
| /*! @{ */ |
| #define LCDIF_DVICTRL4_H_FILL_CNT_MASK (0xFFU) |
| #define LCDIF_DVICTRL4_H_FILL_CNT_SHIFT (0U) |
| #define LCDIF_DVICTRL4_H_FILL_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_H_FILL_CNT_SHIFT)) & LCDIF_DVICTRL4_H_FILL_CNT_MASK) |
| #define LCDIF_DVICTRL4_CR_FILL_VALUE_MASK (0xFF00U) |
| #define LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT (8U) |
| #define LCDIF_DVICTRL4_CR_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CR_FILL_VALUE_MASK) |
| #define LCDIF_DVICTRL4_CB_FILL_VALUE_MASK (0xFF0000U) |
| #define LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT (16U) |
| #define LCDIF_DVICTRL4_CB_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CB_FILL_VALUE_MASK) |
| #define LCDIF_DVICTRL4_Y_FILL_VALUE_MASK (0xFF000000U) |
| #define LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT (24U) |
| #define LCDIF_DVICTRL4_Y_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_Y_FILL_VALUE_MASK) |
| /*! @} */ |
| |
| /*! @name CSC_COEFF0 - RGB to YCbCr 4:2:2 CSC Coefficient0 Register */ |
| /*! @{ */ |
| #define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK (0x3U) |
| #define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT (0U) |
| /*! CSC_SUBSAMPLE_FILTER |
| * 0b00..No filtering, simply keep every chroma value for samples numbered 2n and discard chroma values associated with all samples numbered 2n+1. |
| * 0b01..Reserved |
| * 0b10..Chroma samples numbered 2n and 2n+1 are averaged (weights 1/2, 1/2) and that chroma value replaces the two chroma values at 2n and 2n+1. This chroma now exists horizontally halfway between the two luma samples. |
| * 0b11..Chroma samples numbered 2n-1, 2n, and 2n+1 are averaged (weights 1/4, 1/2, 1/4) and that chroma value exists at the same site as the luma sample numbered 2n and the chroma samples at 2n+1 are discarded. |
| */ |
| #define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT)) & LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK) |
| #define LCDIF_CSC_COEFF0_RSRVD0_MASK (0xFFFCU) |
| #define LCDIF_CSC_COEFF0_RSRVD0_SHIFT (2U) |
| #define LCDIF_CSC_COEFF0_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD0_MASK) |
| #define LCDIF_CSC_COEFF0_C0_MASK (0x3FF0000U) |
| #define LCDIF_CSC_COEFF0_C0_SHIFT (16U) |
| #define LCDIF_CSC_COEFF0_C0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_C0_SHIFT)) & LCDIF_CSC_COEFF0_C0_MASK) |
| #define LCDIF_CSC_COEFF0_RSRVD1_MASK (0xFC000000U) |
| #define LCDIF_CSC_COEFF0_RSRVD1_SHIFT (26U) |
| #define LCDIF_CSC_COEFF0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD1_MASK) |
| /*! @} */ |
| |
| /*! @name CSC_COEFF1 - RGB to YCbCr 4:2:2 CSC Coefficient1 Register */ |
| /*! @{ */ |
| #define LCDIF_CSC_COEFF1_C1_MASK (0x3FFU) |
| #define LCDIF_CSC_COEFF1_C1_SHIFT (0U) |
| #define LCDIF_CSC_COEFF1_C1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C1_SHIFT)) & LCDIF_CSC_COEFF1_C1_MASK) |
| #define LCDIF_CSC_COEFF1_RSRVD0_MASK (0xFC00U) |
| #define LCDIF_CSC_COEFF1_RSRVD0_SHIFT (10U) |
| #define LCDIF_CSC_COEFF1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD0_MASK) |
| #define LCDIF_CSC_COEFF1_C2_MASK (0x3FF0000U) |
| #define LCDIF_CSC_COEFF1_C2_SHIFT (16U) |
| #define LCDIF_CSC_COEFF1_C2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C2_SHIFT)) & LCDIF_CSC_COEFF1_C2_MASK) |
| #define LCDIF_CSC_COEFF1_RSRVD1_MASK (0xFC000000U) |
| #define LCDIF_CSC_COEFF1_RSRVD1_SHIFT (26U) |
| #define LCDIF_CSC_COEFF1_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD1_MASK) |
| /*! @} */ |
| |
| /*! @name CSC_COEFF2 - RGB to YCbCr 4:2:2 CSC Coefficent2 Register */ |
| /*! @{ */ |
| #define LCDIF_CSC_COEFF2_C3_MASK (0x3FFU) |
| #define LCDIF_CSC_COEFF2_C3_SHIFT (0U) |
| #define LCDIF_CSC_COEFF2_C3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C3_SHIFT)) & LCDIF_CSC_COEFF2_C3_MASK) |
| #define LCDIF_CSC_COEFF2_RSRVD0_MASK (0xFC00U) |
| #define LCDIF_CSC_COEFF2_RSRVD0_SHIFT (10U) |
| #define LCDIF_CSC_COEFF2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD0_MASK) |
| #define LCDIF_CSC_COEFF2_C4_MASK (0x3FF0000U) |
| #define LCDIF_CSC_COEFF2_C4_SHIFT (16U) |
| #define LCDIF_CSC_COEFF2_C4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C4_SHIFT)) & LCDIF_CSC_COEFF2_C4_MASK) |
| #define LCDIF_CSC_COEFF2_RSRVD1_MASK (0xFC000000U) |
| #define LCDIF_CSC_COEFF2_RSRVD1_SHIFT (26U) |
| #define LCDIF_CSC_COEFF2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD1_MASK) |
| /*! @} */ |
| |
| /*! @name CSC_COEFF3 - RGB to YCbCr 4:2:2 CSC Coefficient3 Register */ |
| /*! @{ */ |
| #define LCDIF_CSC_COEFF3_C5_MASK (0x3FFU) |
| #define LCDIF_CSC_COEFF3_C5_SHIFT (0U) |
| #define LCDIF_CSC_COEFF3_C5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C5_SHIFT)) & LCDIF_CSC_COEFF3_C5_MASK) |
| #define LCDIF_CSC_COEFF3_RSRVD0_MASK (0xFC00U) |
| #define LCDIF_CSC_COEFF3_RSRVD0_SHIFT (10U) |
| #define LCDIF_CSC_COEFF3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD0_MASK) |
| #define LCDIF_CSC_COEFF3_C6_MASK (0x3FF0000U) |
| #define LCDIF_CSC_COEFF3_C6_SHIFT (16U) |
| #define LCDIF_CSC_COEFF3_C6(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C6_SHIFT)) & LCDIF_CSC_COEFF3_C6_MASK) |
| #define LCDIF_CSC_COEFF3_RSRVD1_MASK (0xFC000000U) |
| #define LCDIF_CSC_COEFF3_RSRVD1_SHIFT (26U) |
| #define LCDIF_CSC_COEFF3_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD1_MASK) |
| /*! @} */ |
| |
| /*! @name CSC_COEFF4 - RGB to YCbCr 4:2:2 CSC Coefficient4 Register */ |
| /*! @{ */ |
| #define LCDIF_CSC_COEFF4_C7_MASK (0x3FFU) |
| #define LCDIF_CSC_COEFF4_C7_SHIFT (0U) |
| #define LCDIF_CSC_COEFF4_C7(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C7_SHIFT)) & LCDIF_CSC_COEFF4_C7_MASK) |
| #define LCDIF_CSC_COEFF4_RSRVD0_MASK (0xFC00U) |
| #define LCDIF_CSC_COEFF4_RSRVD0_SHIFT (10U) |
| #define LCDIF_CSC_COEFF4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD0_MASK) |
| #define LCDIF_CSC_COEFF4_C8_MASK (0x3FF0000U) |
| #define LCDIF_CSC_COEFF4_C8_SHIFT (16U) |
| #define LCDIF_CSC_COEFF4_C8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C8_SHIFT)) & LCDIF_CSC_COEFF4_C8_MASK) |
| #define LCDIF_CSC_COEFF4_RSRVD1_MASK (0xFC000000U) |
| #define LCDIF_CSC_COEFF4_RSRVD1_SHIFT (26U) |
| #define LCDIF_CSC_COEFF4_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD1_MASK) |
| /*! @} */ |
| |
| /*! @name CSC_OFFSET - RGB to YCbCr 4:2:2 CSC Offset Register */ |
| /*! @{ */ |
| #define LCDIF_CSC_OFFSET_Y_OFFSET_MASK (0x1FFU) |
| #define LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT (0U) |
| #define LCDIF_CSC_OFFSET_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_Y_OFFSET_MASK) |
| #define LCDIF_CSC_OFFSET_RSRVD0_MASK (0xFE00U) |
| #define LCDIF_CSC_OFFSET_RSRVD0_SHIFT (9U) |
| #define LCDIF_CSC_OFFSET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD0_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD0_MASK) |
| #define LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK (0x1FF0000U) |
| #define LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT (16U) |
| #define LCDIF_CSC_OFFSET_CBCR_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK) |
| #define LCDIF_CSC_OFFSET_RSRVD1_MASK (0xFE000000U) |
| #define LCDIF_CSC_OFFSET_RSRVD1_SHIFT (25U) |
| #define LCDIF_CSC_OFFSET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD1_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD1_MASK) |
| /*! @} */ |
| |
| /*! @name CSC_LIMIT - RGB to YCbCr 4:2:2 CSC Limit Register */ |
| /*! @{ */ |
| #define LCDIF_CSC_LIMIT_Y_MAX_MASK (0xFFU) |
| #define LCDIF_CSC_LIMIT_Y_MAX_SHIFT (0U) |
| #define LCDIF_CSC_LIMIT_Y_MAX(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MAX_SHIFT)) & LCDIF_CSC_LIMIT_Y_MAX_MASK) |
| #define LCDIF_CSC_LIMIT_Y_MIN_MASK (0xFF00U) |
| #define LCDIF_CSC_LIMIT_Y_MIN_SHIFT (8U) |
| #define LCDIF_CSC_LIMIT_Y_MIN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MIN_SHIFT)) & LCDIF_CSC_LIMIT_Y_MIN_MASK) |
| #define LCDIF_CSC_LIMIT_CBCR_MAX_MASK (0xFF0000U) |
| #define LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT (16U) |
| #define LCDIF_CSC_LIMIT_CBCR_MAX(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MAX_MASK) |
| #define LCDIF_CSC_LIMIT_CBCR_MIN_MASK (0xFF000000U) |
| #define LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT (24U) |
| #define LCDIF_CSC_LIMIT_CBCR_MIN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name DATA - LCD Interface Data Register */ |
| /*! @{ */ |
| #define LCDIF_DATA_DATA_ZERO_MASK (0xFFU) |
| #define LCDIF_DATA_DATA_ZERO_SHIFT (0U) |
| #define LCDIF_DATA_DATA_ZERO(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ZERO_SHIFT)) & LCDIF_DATA_DATA_ZERO_MASK) |
| #define LCDIF_DATA_DATA_ONE_MASK (0xFF00U) |
| #define LCDIF_DATA_DATA_ONE_SHIFT (8U) |
| #define LCDIF_DATA_DATA_ONE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ONE_SHIFT)) & LCDIF_DATA_DATA_ONE_MASK) |
| #define LCDIF_DATA_DATA_TWO_MASK (0xFF0000U) |
| #define LCDIF_DATA_DATA_TWO_SHIFT (16U) |
| #define LCDIF_DATA_DATA_TWO(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_TWO_SHIFT)) & LCDIF_DATA_DATA_TWO_MASK) |
| #define LCDIF_DATA_DATA_THREE_MASK (0xFF000000U) |
| #define LCDIF_DATA_DATA_THREE_SHIFT (24U) |
| #define LCDIF_DATA_DATA_THREE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_THREE_SHIFT)) & LCDIF_DATA_DATA_THREE_MASK) |
| /*! @} */ |
| |
| /*! @name BM_ERROR_STAT - Bus Master Error Status Register */ |
| /*! @{ */ |
| #define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU) |
| #define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U) |
| #define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CRC_STAT - CRC Status Register */ |
| /*! @{ */ |
| #define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU) |
| #define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U) |
| #define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK) |
| /*! @} */ |
| |
| /*! @name STAT - LCD Interface Status Register */ |
| /*! @{ */ |
| #define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU) |
| #define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U) |
| #define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK) |
| #define LCDIF_STAT_RSRVD0_MASK (0xFFFE00U) |
| #define LCDIF_STAT_RSRVD0_SHIFT (9U) |
| #define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK) |
| #define LCDIF_STAT_DVI_CURRENT_FIELD_MASK (0x1000000U) |
| #define LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT (24U) |
| #define LCDIF_STAT_DVI_CURRENT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT)) & LCDIF_STAT_DVI_CURRENT_FIELD_MASK) |
| #define LCDIF_STAT_BUSY_MASK (0x2000000U) |
| #define LCDIF_STAT_BUSY_SHIFT (25U) |
| #define LCDIF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_BUSY_SHIFT)) & LCDIF_STAT_BUSY_MASK) |
| #define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U) |
| #define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U) |
| #define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK) |
| #define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U) |
| #define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U) |
| #define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK) |
| #define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U) |
| #define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U) |
| #define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK) |
| #define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U) |
| #define LCDIF_STAT_LFIFO_FULL_SHIFT (29U) |
| #define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK) |
| #define LCDIF_STAT_PRESENT_MASK (0x80000000U) |
| #define LCDIF_STAT_PRESENT_SHIFT (31U) |
| #define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK) |
| /*! @} */ |
| |
| /*! @name THRES - LCDIF Threshold Register */ |
| /*! @{ */ |
| #define LCDIF_THRES_PANIC_MASK (0x1FFU) |
| #define LCDIF_THRES_PANIC_SHIFT (0U) |
| #define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK) |
| #define LCDIF_THRES_RSRVD1_MASK (0xFE00U) |
| #define LCDIF_THRES_RSRVD1_SHIFT (9U) |
| #define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK) |
| #define LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U) |
| #define LCDIF_THRES_FASTCLOCK_SHIFT (16U) |
| #define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK) |
| #define LCDIF_THRES_RSRVD2_MASK (0xFE000000U) |
| #define LCDIF_THRES_RSRVD2_SHIFT (25U) |
| #define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK) |
| /*! @} */ |
| |
| /*! @name AS_CTRL - LCDIF AS Buffer Control Register */ |
| /*! @{ */ |
| #define LCDIF_AS_CTRL_AS_ENABLE_MASK (0x1U) |
| #define LCDIF_AS_CTRL_AS_ENABLE_SHIFT (0U) |
| #define LCDIF_AS_CTRL_AS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_AS_ENABLE_SHIFT)) & LCDIF_AS_CTRL_AS_ENABLE_MASK) |
| #define LCDIF_AS_CTRL_ALPHA_CTRL_MASK (0x6U) |
| #define LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT (1U) |
| #define LCDIF_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT)) & LCDIF_AS_CTRL_ALPHA_CTRL_MASK) |
| #define LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U) |
| #define LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U) |
| #define LCDIF_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK) |
| #define LCDIF_AS_CTRL_FORMAT_MASK (0xF0U) |
| #define LCDIF_AS_CTRL_FORMAT_SHIFT (4U) |
| #define LCDIF_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_FORMAT_SHIFT)) & LCDIF_AS_CTRL_FORMAT_MASK) |
| #define LCDIF_AS_CTRL_ALPHA_MASK (0xFF00U) |
| #define LCDIF_AS_CTRL_ALPHA_SHIFT (8U) |
| #define LCDIF_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_SHIFT)) & LCDIF_AS_CTRL_ALPHA_MASK) |
| #define LCDIF_AS_CTRL_ROP_MASK (0xF0000U) |
| #define LCDIF_AS_CTRL_ROP_SHIFT (16U) |
| #define LCDIF_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ROP_SHIFT)) & LCDIF_AS_CTRL_ROP_MASK) |
| #define LCDIF_AS_CTRL_ALPHA_INVERT_MASK (0x100000U) |
| #define LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT (20U) |
| #define LCDIF_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT)) & LCDIF_AS_CTRL_ALPHA_INVERT_MASK) |
| #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK (0x600000U) |
| #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT (21U) |
| #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK) |
| #define LCDIF_AS_CTRL_PS_DISABLE_MASK (0x800000U) |
| #define LCDIF_AS_CTRL_PS_DISABLE_SHIFT (23U) |
| #define LCDIF_AS_CTRL_PS_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_PS_DISABLE_SHIFT)) & LCDIF_AS_CTRL_PS_DISABLE_MASK) |
| #define LCDIF_AS_CTRL_RVDS1_MASK (0x7000000U) |
| #define LCDIF_AS_CTRL_RVDS1_SHIFT (24U) |
| #define LCDIF_AS_CTRL_RVDS1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_RVDS1_SHIFT)) & LCDIF_AS_CTRL_RVDS1_MASK) |
| #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK (0x8000000U) |
| #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT (27U) |
| #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK) |
| #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK (0x10000000U) |
| #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT (28U) |
| #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK) |
| #define LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK (0x20000000U) |
| #define LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT (29U) |
| #define LCDIF_AS_CTRL_CSI_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK) |
| #define LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK (0x40000000U) |
| #define LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT (30U) |
| #define LCDIF_AS_CTRL_CSI_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK) |
| #define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK (0x80000000U) |
| #define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT (31U) |
| #define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK) |
| /*! @} */ |
| |
| /*! @name AS_BUF - Alpha Surface Buffer Pointer */ |
| /*! @{ */ |
| #define LCDIF_AS_BUF_ADDR_MASK (0xFFFFFFFFU) |
| #define LCDIF_AS_BUF_ADDR_SHIFT (0U) |
| #define LCDIF_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_BUF_ADDR_SHIFT)) & LCDIF_AS_BUF_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name AS_NEXT_BUF - */ |
| /*! @{ */ |
| #define LCDIF_AS_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) |
| #define LCDIF_AS_NEXT_BUF_ADDR_SHIFT (0U) |
| #define LCDIF_AS_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_NEXT_BUF_ADDR_SHIFT)) & LCDIF_AS_NEXT_BUF_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name AS_CLRKEYLOW - LCDIF Overlay Color Key Low */ |
| /*! @{ */ |
| #define LCDIF_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) |
| #define LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT (0U) |
| #define LCDIF_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYLOW_PIXEL_MASK) |
| #define LCDIF_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) |
| #define LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT (24U) |
| #define LCDIF_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYLOW_RSVD1_MASK) |
| /*! @} */ |
| |
| /*! @name AS_CLRKEYHIGH - LCDIF Overlay Color Key High */ |
| /*! @{ */ |
| #define LCDIF_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) |
| #define LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT (0U) |
| #define LCDIF_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYHIGH_PIXEL_MASK) |
| #define LCDIF_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) |
| #define LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT (24U) |
| #define LCDIF_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYHIGH_RSVD1_MASK) |
| /*! @} */ |
| |
| /*! @name SYNC_DELAY - LCD working insync mode with CSI for VSYNC delay */ |
| /*! @{ */ |
| #define LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK (0xFFFFU) |
| #define LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT (0U) |
| #define LCDIF_SYNC_DELAY_H_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK) |
| #define LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK (0xFFFF0000U) |
| #define LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT (16U) |
| #define LCDIF_SYNC_DELAY_V_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group LCDIF_Register_Masks */ |
| |
| |
| /* LCDIF - Peripheral instance base addresses */ |
| /** Peripheral LCDIF base address */ |
| #define LCDIF_BASE (0x30320000u) |
| /** Peripheral LCDIF base pointer */ |
| #define LCDIF ((LCDIF_Type *)LCDIF_BASE) |
| /** Array initializer of LCDIF peripheral base addresses */ |
| #define LCDIF_BASE_ADDRS { LCDIF_BASE } |
| /** Array initializer of LCDIF peripheral base pointers */ |
| #define LCDIF_BASE_PTRS { LCDIF } |
| |
| /*! |
| * @} |
| */ /* end of group LCDIF_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- LMEM Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** LMEM - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t PCCCR; /**< Cache control register, offset: 0x0 */ |
| __IO uint32_t PCCLCR; /**< Cache line control register, offset: 0x4 */ |
| __IO uint32_t PCCSAR; /**< Cache search address register, offset: 0x8 */ |
| __IO uint32_t PCCCVR; /**< Cache read/write value register, offset: 0xC */ |
| uint8_t RESERVED_0[2032]; |
| __IO uint32_t PSCCR; /**< Cache control register, offset: 0x800 */ |
| __IO uint32_t PSCLCR; /**< Cache line control register, offset: 0x804 */ |
| __IO uint32_t PSCSAR; /**< Cache search address register, offset: 0x808 */ |
| __IO uint32_t PSCCVR; /**< Cache read/write value register, offset: 0x80C */ |
| } LMEM_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- LMEM Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup LMEM_Register_Masks LMEM Register Masks |
| * @{ |
| */ |
| |
| /*! @name PCCCR - Cache control register */ |
| /*! @{ */ |
| #define LMEM_PCCCR_ENCACHE_MASK (0x1U) |
| #define LMEM_PCCCR_ENCACHE_SHIFT (0U) |
| /*! ENCACHE - Cache enable |
| * 0b0..Cache disabled |
| * 0b1..Cache enabled |
| */ |
| #define LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK) |
| #define LMEM_PCCCR_ENWRBUF_MASK (0x2U) |
| #define LMEM_PCCCR_ENWRBUF_SHIFT (1U) |
| /*! ENWRBUF - Enable Write Buffer |
| * 0b0..Write buffer disabled |
| * 0b1..Write buffer enabled |
| */ |
| #define LMEM_PCCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK) |
| #define LMEM_PCCCR_PCCR2_MASK (0x4U) |
| #define LMEM_PCCCR_PCCR2_SHIFT (2U) |
| #define LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK) |
| #define LMEM_PCCCR_PCCR3_MASK (0x8U) |
| #define LMEM_PCCCR_PCCR3_SHIFT (3U) |
| #define LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK) |
| #define LMEM_PCCCR_INVW0_MASK (0x1000000U) |
| #define LMEM_PCCCR_INVW0_SHIFT (24U) |
| /*! INVW0 - Invalidate Way 0 |
| * 0b0..No operation |
| * 0b1..When setting the GO bit, invalidate all lines in way 0. |
| */ |
| #define LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK) |
| #define LMEM_PCCCR_PUSHW0_MASK (0x2000000U) |
| #define LMEM_PCCCR_PUSHW0_SHIFT (25U) |
| /*! PUSHW0 - Push Way 0 |
| * 0b0..No operation |
| * 0b1..When setting the GO bit, push all modified lines in way 0 |
| */ |
| #define LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK) |
| #define LMEM_PCCCR_INVW1_MASK (0x4000000U) |
| #define LMEM_PCCCR_INVW1_SHIFT (26U) |
| /*! INVW1 - Invalidate Way 1 |
| * 0b0..No operation |
| * 0b1..When setting the GO bit, invalidate all lines in way 1 |
| */ |
| #define LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK) |
| #define LMEM_PCCCR_PUSHW1_MASK (0x8000000U) |
| #define LMEM_PCCCR_PUSHW1_SHIFT (27U) |
| /*! PUSHW1 - Push Way 1 |
| * 0b0..No operation |
| * 0b1..When setting the GO bit, push all modified lines in way 1 |
| */ |
| #define LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK) |
| #define LMEM_PCCCR_GO_MASK (0x80000000U) |
| #define LMEM_PCCCR_GO_SHIFT (31U) |
| /*! GO - Initiate Cache Command |
| * 0b0..Write: no effect. Read: no cache command active. |
| * 0b1..Write: initiate command indicated by bits 27-24. Read: cache command active. |
| */ |
| #define LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK) |
| /*! @} */ |
| |
| /*! @name PCCLCR - Cache line control register */ |
| /*! @{ */ |
| #define LMEM_PCCLCR_LGO_MASK (0x1U) |
| #define LMEM_PCCLCR_LGO_SHIFT (0U) |
| /*! LGO - Initiate Cache Line Command |
| * 0b0..Write: no effect. Read: no line command active. |
| * 0b1..Write: initiate line command indicated by bits 27-24. Read: line command active. |
| */ |
| #define LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK) |
| #define LMEM_PCCLCR_CACHEADDR_MASK (0x1FFCU) |
| #define LMEM_PCCLCR_CACHEADDR_SHIFT (2U) |
| #define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK) |
| #define LMEM_PCCLCR_WSEL_MASK (0x4000U) |
| #define LMEM_PCCLCR_WSEL_SHIFT (14U) |
| /*! WSEL - Way select |
| * 0b0..Way 0 |
| * 0b1..Way 1 |
| */ |
| #define LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK) |
| #define LMEM_PCCLCR_TDSEL_MASK (0x10000U) |
| #define LMEM_PCCLCR_TDSEL_SHIFT (16U) |
| /*! TDSEL - Tag/Data Select |
| * 0b0..Data |
| * 0b1..Tag |
| */ |
| #define LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK) |
| #define LMEM_PCCLCR_LCIVB_MASK (0x100000U) |
| #define LMEM_PCCLCR_LCIVB_SHIFT (20U) |
| #define LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK) |
| #define LMEM_PCCLCR_LCIMB_MASK (0x200000U) |
| #define LMEM_PCCLCR_LCIMB_SHIFT (21U) |
| #define LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK) |
| #define LMEM_PCCLCR_LCWAY_MASK (0x400000U) |
| #define LMEM_PCCLCR_LCWAY_SHIFT (22U) |
| #define LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK) |
| #define LMEM_PCCLCR_LCMD_MASK (0x3000000U) |
| #define LMEM_PCCLCR_LCMD_SHIFT (24U) |
| /*! LCMD - Line Command |
| * 0b00..Search and read or write |
| * 0b01..Invalidate |
| * 0b10..Push |
| * 0b11..Clear |
| */ |
| #define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK) |
| #define LMEM_PCCLCR_LADSEL_MASK (0x4000000U) |
| #define LMEM_PCCLCR_LADSEL_SHIFT (26U) |
| /*! LADSEL - Line Address Select |
| * 0b0..Cache address |
| * 0b1..Physical address |
| */ |
| #define LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK) |
| #define LMEM_PCCLCR_LACC_MASK (0x8000000U) |
| #define LMEM_PCCLCR_LACC_SHIFT (27U) |
| /*! LACC - Line access type |
| * 0b0..Read |
| * 0b1..Write |
| */ |
| #define LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK) |
| /*! @} */ |
| |
| /*! @name PCCSAR - Cache search address register */ |
| /*! @{ */ |
| #define LMEM_PCCSAR_LGO_MASK (0x1U) |
| #define LMEM_PCCSAR_LGO_SHIFT (0U) |
| /*! LGO - Initiate Cache Line Command |
| * 0b0..Write: no effect. Read: no line command active. |
| * 0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active. |
| */ |
| #define LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK) |
| #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) |
| #define LMEM_PCCSAR_PHYADDR_SHIFT (2U) |
| #define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK) |
| /*! @} */ |
| |
| /*! @name PCCCVR - Cache read/write value register */ |
| /*! @{ */ |
| #define LMEM_PCCCVR_DATA_MASK (0xFFFFFFFFU) |
| #define LMEM_PCCCVR_DATA_SHIFT (0U) |
| #define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK) |
| /*! @} */ |
| |
| /*! @name PSCCR - Cache control register */ |
| /*! @{ */ |
| #define LMEM_PSCCR_ENCACHE_MASK (0x1U) |
| #define LMEM_PSCCR_ENCACHE_SHIFT (0U) |
| /*! ENCACHE - Cache enable |
| * 0b0..Cache disabled |
| * 0b1..Cache enabled |
| */ |
| #define LMEM_PSCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENCACHE_SHIFT)) & LMEM_PSCCR_ENCACHE_MASK) |
| #define LMEM_PSCCR_ENWRBUF_MASK (0x2U) |
| #define LMEM_PSCCR_ENWRBUF_SHIFT (1U) |
| /*! ENWRBUF - Enable Write Buffer |
| * 0b0..Write buffer disabled |
| * 0b1..Write buffer enabled |
| */ |
| #define LMEM_PSCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENWRBUF_SHIFT)) & LMEM_PSCCR_ENWRBUF_MASK) |
| #define LMEM_PSCCR_INVW0_MASK (0x1000000U) |
| #define LMEM_PSCCR_INVW0_SHIFT (24U) |
| /*! INVW0 - Invalidate Way 0 |
| * 0b0..No operation |
| * 0b1..When setting the GO bit, invalidate all lines in way 0. |
| */ |
| #define LMEM_PSCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW0_SHIFT)) & LMEM_PSCCR_INVW0_MASK) |
| #define LMEM_PSCCR_PUSHW0_MASK (0x2000000U) |
| #define LMEM_PSCCR_PUSHW0_SHIFT (25U) |
| /*! PUSHW0 - Push Way 0 |
| * 0b0..No operation |
| * 0b1..When setting the GO bit, push all modified lines in way 0 |
| */ |
| #define LMEM_PSCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW0_SHIFT)) & LMEM_PSCCR_PUSHW0_MASK) |
| #define LMEM_PSCCR_INVW1_MASK (0x4000000U) |
| #define LMEM_PSCCR_INVW1_SHIFT (26U) |
| /*! INVW1 - Invalidate Way 1 |
| * 0b0..No operation |
| * 0b1..When setting the GO bit, invalidate all lines in way 1 |
| */ |
| #define LMEM_PSCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW1_SHIFT)) & LMEM_PSCCR_INVW1_MASK) |
| #define LMEM_PSCCR_PUSHW1_MASK (0x8000000U) |
| #define LMEM_PSCCR_PUSHW1_SHIFT (27U) |
| /*! PUSHW1 - Push Way 1 |
| * 0b0..No operation |
| * 0b1..When setting the GO bit, push all modified lines in way 1 |
| */ |
| #define LMEM_PSCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW1_SHIFT)) & LMEM_PSCCR_PUSHW1_MASK) |
| #define LMEM_PSCCR_GO_MASK (0x80000000U) |
| #define LMEM_PSCCR_GO_SHIFT (31U) |
| /*! GO - Initiate Cache Command |
| * 0b0..Write: no effect. Read: no cache command active. |
| * 0b1..Write: initiate command indicated by bits 27-24. Read: cache command active. |
| */ |
| #define LMEM_PSCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_GO_SHIFT)) & LMEM_PSCCR_GO_MASK) |
| /*! @} */ |
| |
| /*! @name PSCLCR - Cache line control register */ |
| /*! @{ */ |
| #define LMEM_PSCLCR_LGO_MASK (0x1U) |
| #define LMEM_PSCLCR_LGO_SHIFT (0U) |
| /*! LGO - Initiate Cache Line Command |
| * 0b0..Write: no effect. Read: no line command active. |
| * 0b1..Write: initiate line command indicated by bits 27-24. Read: line command active. |
| */ |
| #define LMEM_PSCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LGO_SHIFT)) & LMEM_PSCLCR_LGO_MASK) |
| #define LMEM_PSCLCR_CACHEADDR_MASK (0x1FFCU) |
| #define LMEM_PSCLCR_CACHEADDR_SHIFT (2U) |
| #define LMEM_PSCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_CACHEADDR_SHIFT)) & LMEM_PSCLCR_CACHEADDR_MASK) |
| #define LMEM_PSCLCR_WSEL_MASK (0x4000U) |
| #define LMEM_PSCLCR_WSEL_SHIFT (14U) |
| /*! WSEL - Way select |
| * 0b0..Way 0 |
| * 0b1..Way 1 |
| */ |
| #define LMEM_PSCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_WSEL_SHIFT)) & LMEM_PSCLCR_WSEL_MASK) |
| #define LMEM_PSCLCR_TDSEL_MASK (0x10000U) |
| #define LMEM_PSCLCR_TDSEL_SHIFT (16U) |
| /*! TDSEL - Tag/Data Select |
| * 0b0..Data |
| * 0b1..Tag |
| */ |
| #define LMEM_PSCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_TDSEL_SHIFT)) & LMEM_PSCLCR_TDSEL_MASK) |
| #define LMEM_PSCLCR_LCIVB_MASK (0x100000U) |
| #define LMEM_PSCLCR_LCIVB_SHIFT (20U) |
| #define LMEM_PSCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIVB_SHIFT)) & LMEM_PSCLCR_LCIVB_MASK) |
| #define LMEM_PSCLCR_LCIMB_MASK (0x200000U) |
| #define LMEM_PSCLCR_LCIMB_SHIFT (21U) |
| #define LMEM_PSCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIMB_SHIFT)) & LMEM_PSCLCR_LCIMB_MASK) |
| #define LMEM_PSCLCR_LCWAY_MASK (0x400000U) |
| #define LMEM_PSCLCR_LCWAY_SHIFT (22U) |
| #define LMEM_PSCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCWAY_SHIFT)) & LMEM_PSCLCR_LCWAY_MASK) |
| #define LMEM_PSCLCR_LCMD_MASK (0x3000000U) |
| #define LMEM_PSCLCR_LCMD_SHIFT (24U) |
| /*! LCMD - Line Command |
| * 0b00..Search and read or write |
| * 0b01..Invalidate |
| * 0b10..Push |
| * 0b11..Clear |
| */ |
| #define LMEM_PSCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCMD_SHIFT)) & LMEM_PSCLCR_LCMD_MASK) |
| #define LMEM_PSCLCR_LADSEL_MASK (0x4000000U) |
| #define LMEM_PSCLCR_LADSEL_SHIFT (26U) |
| /*! LADSEL - Line Address Select |
| * 0b0..Cache address |
| * 0b1..Physical address |
| */ |
| #define LMEM_PSCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LADSEL_SHIFT)) & LMEM_PSCLCR_LADSEL_MASK) |
| #define LMEM_PSCLCR_LACC_MASK (0x8000000U) |
| #define LMEM_PSCLCR_LACC_SHIFT (27U) |
| /*! LACC - Line access type |
| * 0b0..Read |
| * 0b1..Write |
| */ |
| #define LMEM_PSCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LACC_SHIFT)) & LMEM_PSCLCR_LACC_MASK) |
| /*! @} */ |
| |
| /*! @name PSCSAR - Cache search address register */ |
| /*! @{ */ |
| #define LMEM_PSCSAR_LGO_MASK (0x1U) |
| #define LMEM_PSCSAR_LGO_SHIFT (0U) |
| /*! LGO - Initiate Cache Line Command |
| * 0b0..Write: no effect. Read: no line command active. |
| * 0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active. |
| */ |
| #define LMEM_PSCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_LGO_SHIFT)) & LMEM_PSCSAR_LGO_MASK) |
| #define LMEM_PSCSAR_PHYADDR_MASK (0xFFFFFFFCU) |
| #define LMEM_PSCSAR_PHYADDR_SHIFT (2U) |
| #define LMEM_PSCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_PHYADDR_SHIFT)) & LMEM_PSCSAR_PHYADDR_MASK) |
| /*! @} */ |
| |
| /*! @name PSCCVR - Cache read/write value register */ |
| /*! @{ */ |
| #define LMEM_PSCCVR_DATA_MASK (0xFFFFFFFFU) |
| #define LMEM_PSCCVR_DATA_SHIFT (0U) |
| #define LMEM_PSCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCVR_DATA_SHIFT)) & LMEM_PSCCVR_DATA_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group LMEM_Register_Masks */ |
| |
| |
| /* LMEM - Peripheral instance base addresses */ |
| /** Peripheral LMEM base address */ |
| #define LMEM_BASE (0xE0082000u) |
| /** Peripheral LMEM base pointer */ |
| #define LMEM ((LMEM_Type *)LMEM_BASE) |
| /** Array initializer of LMEM peripheral base addresses */ |
| #define LMEM_BASE_ADDRS { LMEM_BASE } |
| /** Array initializer of LMEM peripheral base pointers */ |
| #define LMEM_BASE_PTRS { LMEM } |
| |
| /*! |
| * @} |
| */ /* end of group LMEM_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- LUT_LD Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup LUT_LD_Peripheral_Access_Layer LUT_LD Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** LUT_LD - Register Layout Typedef */ |
| typedef struct { |
| struct { /* offset: 0x0 */ |
| __IO uint32_t RW; /**< Control/Status register for LUT Loader., offset: 0x0 */ |
| __IO uint32_t SET; /**< Control/Status register for LUT Loader., offset: 0x4 */ |
| __IO uint32_t CLR; /**< Control/Status register for LUT Loader., offset: 0x8 */ |
| __IO uint32_t TOG; /**< Control/Status register for LUT Loader., offset: 0xC */ |
| } CTRL_STATUS; |
| __IO uint32_t BASE_ADDR; /**< Address for data fetch., offset: 0x10 */ |
| } LUT_LD_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- LUT_LD Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup LUT_LD_Register_Masks LUT_LD Register Masks |
| * @{ |
| */ |
| |
| /*! @name CTRL_STATUS - Control/Status register for LUT Loader. */ |
| /*! @{ */ |
| #define LUT_LD_CTRL_STATUS_ENABLE_MASK (0x1U) |
| #define LUT_LD_CTRL_STATUS_ENABLE_SHIFT (0U) |
| #define LUT_LD_CTRL_STATUS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LUT_LD_CTRL_STATUS_ENABLE_SHIFT)) & LUT_LD_CTRL_STATUS_ENABLE_MASK) |
| #define LUT_LD_CTRL_STATUS_BYTES_PER_REQ_MASK (0x2U) |
| #define LUT_LD_CTRL_STATUS_BYTES_PER_REQ_SHIFT (1U) |
| #define LUT_LD_CTRL_STATUS_BYTES_PER_REQ(x) (((uint32_t)(((uint32_t)(x)) << LUT_LD_CTRL_STATUS_BYTES_PER_REQ_SHIFT)) & LUT_LD_CTRL_STATUS_BYTES_PER_REQ_MASK) |
| #define LUT_LD_CTRL_STATUS_RD_ERR_EN_MASK (0x100U) |
| #define LUT_LD_CTRL_STATUS_RD_ERR_EN_SHIFT (8U) |
| #define LUT_LD_CTRL_STATUS_RD_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << LUT_LD_CTRL_STATUS_RD_ERR_EN_SHIFT)) & LUT_LD_CTRL_STATUS_RD_ERR_EN_MASK) |
| #define LUT_LD_CTRL_STATUS_RD_ERR_MASK (0x10000U) |
| #define LUT_LD_CTRL_STATUS_RD_ERR_SHIFT (16U) |
| #define LUT_LD_CTRL_STATUS_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << LUT_LD_CTRL_STATUS_RD_ERR_SHIFT)) & LUT_LD_CTRL_STATUS_RD_ERR_MASK) |
| /*! @} */ |
| |
| /*! @name BASE_ADDR - Address for data fetch. */ |
| /*! @{ */ |
| #define LUT_LD_BASE_ADDR_BASE_ADDR_MASK (0xFFFFFFFFU) |
| #define LUT_LD_BASE_ADDR_BASE_ADDR_SHIFT (0U) |
| #define LUT_LD_BASE_ADDR_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LUT_LD_BASE_ADDR_BASE_ADDR_SHIFT)) & LUT_LD_BASE_ADDR_BASE_ADDR_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group LUT_LD_Register_Masks */ |
| |
| |
| /* LUT_LD - Peripheral instance base addresses */ |
| /** Peripheral DCSS__LUT_LD base address */ |
| #define DCSS__LUT_LD_BASE (0x32E24000u) |
| /** Peripheral DCSS__LUT_LD base pointer */ |
| #define DCSS__LUT_LD ((LUT_LD_Type *)DCSS__LUT_LD_BASE) |
| /** Array initializer of LUT_LD peripheral base addresses */ |
| #define LUT_LD_BASE_ADDRS { DCSS__LUT_LD_BASE } |
| /** Array initializer of LUT_LD peripheral base pointers */ |
| #define LUT_LD_BASE_PTRS { DCSS__LUT_LD } |
| |
| /*! |
| * @} |
| */ /* end of group LUT_LD_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- MCM Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** MCM - Register Layout Typedef */ |
| typedef struct { |
| uint8_t RESERVED_0[8]; |
| __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ |
| __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ |
| uint32_t PLACR; /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */ |
| uint8_t RESERVED_1[16]; |
| __I uint32_t FADR; /**< Fault address register, offset: 0x20 */ |
| __I uint32_t FATR; /**< Fault attributes register, offset: 0x24 */ |
| __I uint32_t FDR; /**< Fault data register, offset: 0x28 */ |
| } MCM_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- MCM Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MCM_Register_Masks MCM Register Masks |
| * @{ |
| */ |
| |
| /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ |
| /*! @{ */ |
| #define MCM_PLASC_ASC_MASK (0xFFU) |
| #define MCM_PLASC_ASC_SHIFT (0U) |
| /*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. |
| * 0b00000000..A bus slave connection to AXBS input port n is absent |
| * 0b00000001..A bus slave connection to AXBS input port n is present |
| */ |
| #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) |
| /*! @} */ |
| |
| /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ |
| /*! @{ */ |
| #define MCM_PLAMC_AMC_MASK (0xFFU) |
| #define MCM_PLAMC_AMC_SHIFT (0U) |
| /*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. |
| * 0b00000000..A bus master connection to AXBS input port n is absent |
| * 0b00000001..A bus master connection to AXBS input port n is present |
| */ |
| #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) |
| /*! @} */ |
| |
| /*! @name FADR - Fault address register */ |
| /*! @{ */ |
| #define MCM_FADR_ADDRESS_MASK (0xFFFFFFFFU) |
| #define MCM_FADR_ADDRESS_SHIFT (0U) |
| #define MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK) |
| /*! @} */ |
| |
| /*! @name FATR - Fault attributes register */ |
| /*! @{ */ |
| #define MCM_FATR_BEDA_MASK (0x1U) |
| #define MCM_FATR_BEDA_SHIFT (0U) |
| /*! BEDA - Bus error access type |
| * 0b0..Instruction |
| * 0b1..Data |
| */ |
| #define MCM_FATR_BEDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK) |
| #define MCM_FATR_BEMD_MASK (0x2U) |
| #define MCM_FATR_BEMD_SHIFT (1U) |
| /*! BEMD - Bus error privilege level |
| * 0b0..User mode |
| * 0b1..Supervisor/privileged mode |
| */ |
| #define MCM_FATR_BEMD(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK) |
| #define MCM_FATR_BESZ_MASK (0x30U) |
| #define MCM_FATR_BESZ_SHIFT (4U) |
| /*! BESZ - Bus error size |
| * 0b00..8-bit access |
| * 0b01..16-bit access |
| * 0b10..32-bit access |
| * 0b11..Reserved |
| */ |
| #define MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK) |
| #define MCM_FATR_BEWT_MASK (0x80U) |
| #define MCM_FATR_BEWT_SHIFT (7U) |
| /*! BEWT - Bus error write |
| * 0b0..Read access |
| * 0b1..Write access |
| */ |
| #define MCM_FATR_BEWT(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK) |
| #define MCM_FATR_BEMN_MASK (0xF00U) |
| #define MCM_FATR_BEMN_SHIFT (8U) |
| #define MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK) |
| #define MCM_FATR_BEOVR_MASK (0x80000000U) |
| #define MCM_FATR_BEOVR_SHIFT (31U) |
| /*! BEOVR - Bus error overrun |
| * 0b0..No bus error overrun |
| * 0b1..Bus error overrun occurred. The FADR and FDR registers and the other FATR bits are not updated to reflect this new bus error. |
| */ |
| #define MCM_FATR_BEOVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK) |
| /*! @} */ |
| |
| /*! @name FDR - Fault data register */ |
| /*! @{ */ |
| #define MCM_FDR_DATA_MASK (0xFFFFFFFFU) |
| #define MCM_FDR_DATA_SHIFT (0U) |
| #define MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group MCM_Register_Masks */ |
| |
| |
| /* MCM - Peripheral instance base addresses */ |
| /** Peripheral MCM base address */ |
| #define MCM_BASE (0xE0080000u) |
| /** Peripheral MCM base pointer */ |
| #define MCM ((MCM_Type *)MCM_BASE) |
| /** Array initializer of MCM peripheral base addresses */ |
| #define MCM_BASE_ADDRS { MCM_BASE } |
| /** Array initializer of MCM peripheral base pointers */ |
| #define MCM_BASE_PTRS { MCM } |
| |
| /*! |
| * @} |
| */ /* end of group MCM_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- MED_DC_SCALER Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MED_DC_SCALER_Peripheral_Access_Layer MED_DC_SCALER Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** MED_DC_SCALER - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t SCALE_CTRL; /**< Scale Control Register, offset: 0x0 */ |
| __IO uint32_t SCALE_OFIFO_CTRL; /**< Scale Output FIFO Control Register, offset: 0x4 */ |
| __IO uint32_t SCALE_SRC_DATA_CTRL; /**< Scale Source Data Control Register, offset: 0x8 */ |
| __IO uint32_t SCALE_BIT_DEPTH; /**< Scale Bit Depth Control Register, offset: 0xC */ |
| __IO uint32_t SCALE_SRC_FORMAT; /**< Scale Source Format Control Register, offset: 0x10 */ |
| __IO uint32_t SCALE_DST_FORMAT; /**< Scale Destination Format Control Register, offset: 0x14 */ |
| __IO uint32_t SCALE_SRC_LUMA_RES; /**< Scale Source Luma Resolution Register, offset: 0x18 */ |
| __IO uint32_t SCALE_SRC_CHROMA_RES; /**< Scale Source Chroma Resolution Register, offset: 0x1C */ |
| __IO uint32_t SCALE_DST_LUMA_RES; /**< Scale Destination Luma Resolution Register, offset: 0x20 */ |
| __IO uint32_t SCALE_DST_CHROMA_RES; /**< Scale Destination Chroma Resolution Register, offset: 0x24 */ |
| uint8_t RESERVED_0[32]; |
| __IO uint32_t SCALE_V_LUMA_START; /**< Scale Vertical Luma Start Register, offset: 0x48 */ |
| __IO uint32_t SCALE_V_LUMA_INC; /**< Scale Vertical Luma Increment Register, offset: 0x4C */ |
| __IO uint32_t SCALE_H_LUMA_START; /**< Scale Horizontal Luma Start Register, offset: 0x50 */ |
| __IO uint32_t SCALE_H_LUMA_INC; /**< Scale Horizontal Luma Increment Register, offset: 0x54 */ |
| __IO uint32_t SCALE_V_CHROMA_START; /**< Scale Vertical Chroma Start Register, offset: 0x58 */ |
| __IO uint32_t SCALE_V_CHROMA_INC; /**< Scale Vertical Chroma Increment Register, offset: 0x5C */ |
| __IO uint32_t SCALE_H_CHROMA_START; /**< Scale Horizontal Chroma Start Register, offset: 0x60 */ |
| __IO uint32_t SCALE_H_CHROMA_INC; /**< Scale Horizontal Chroma Increment Register, offset: 0x64 */ |
| uint8_t RESERVED_1[24]; |
| __IO uint32_t SCALE_COEF_ARRAY; /**< Scale Coefficient Memory Array, offset: 0x80 */ |
| } MED_DC_SCALER_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- MED_DC_SCALER Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MED_DC_SCALER_Register_Masks MED_DC_SCALER Register Masks |
| * @{ |
| */ |
| |
| /*! @name SCALE_CTRL - Scale Control Register */ |
| /*! @{ */ |
| #define MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALER_MASK (0x1U) |
| #define MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALER_SHIFT (0U) |
| #define MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALER(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALER_SHIFT)) & MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALER_MASK) |
| #define MED_DC_SCALER_SCALE_CTRL_ENABLE_REPEAT_MASK (0x10U) |
| #define MED_DC_SCALER_SCALE_CTRL_ENABLE_REPEAT_SHIFT (4U) |
| #define MED_DC_SCALER_SCALE_CTRL_ENABLE_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_CTRL_ENABLE_REPEAT_SHIFT)) & MED_DC_SCALER_SCALE_CTRL_ENABLE_REPEAT_MASK) |
| #define MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALE2MEM_MASK (0x100U) |
| #define MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALE2MEM_SHIFT (8U) |
| #define MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALE2MEM(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALE2MEM_SHIFT)) & MED_DC_SCALER_SCALE_CTRL_ENABLE_SCALE2MEM_MASK) |
| #define MED_DC_SCALER_SCALE_CTRL_ENABLE_MEM2OFIFO_MASK (0x1000U) |
| #define MED_DC_SCALER_SCALE_CTRL_ENABLE_MEM2OFIFO_SHIFT (12U) |
| #define MED_DC_SCALER_SCALE_CTRL_ENABLE_MEM2OFIFO(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_CTRL_ENABLE_MEM2OFIFO_SHIFT)) & MED_DC_SCALER_SCALE_CTRL_ENABLE_MEM2OFIFO_MASK) |
| /*! @} */ |
| |
| /*! @name SCALE_OFIFO_CTRL - Scale Output FIFO Control Register */ |
| /*! @{ */ |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_LOW_THRESH_MASK (0x3FFU) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_LOW_THRESH_SHIFT (0U) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_LOW_THRESH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_LOW_THRESH_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_LOW_THRESH_MASK) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_HIGH_THRESH_MASK (0x3FF0000U) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_HIGH_THRESH_SHIFT (16U) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_HIGH_THRESH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_HIGH_THRESH_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_OFIFO_HIGH_THRESH_MASK) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_UNDERRUN_DETECT_MASK (0x4000000U) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_UNDERRUN_DETECT_SHIFT (26U) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_UNDERRUN_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_UNDERRUN_DETECT_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_UNDERRUN_DETECT_MASK) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_LOW_THRESH_DETECT_MASK (0x8000000U) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_LOW_THRESH_DETECT_SHIFT (27U) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_LOW_THRESH_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_LOW_THRESH_DETECT_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_LOW_THRESH_DETECT_MASK) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_HIGH_THRESH_DETECT_MASK (0x10000000U) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_HIGH_THRESH_DETECT_SHIFT (28U) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_HIGH_THRESH_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_HIGH_THRESH_DETECT_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_CLEAR_HIGH_THRESH_DETECT_MASK) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_UNDERRUN_DETECT_MASK (0x20000000U) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_UNDERRUN_DETECT_SHIFT (29U) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_UNDERRUN_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_UNDERRUN_DETECT_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_UNDERRUN_DETECT_MASK) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_LOW_THRESH_DETECT_MASK (0x40000000U) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_LOW_THRESH_DETECT_SHIFT (30U) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_LOW_THRESH_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_LOW_THRESH_DETECT_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_LOW_THRESH_DETECT_MASK) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_HIGH_THRESH_DETECT_MASK (0x80000000U) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_HIGH_THRESH_DETECT_SHIFT (31U) |
| #define MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_HIGH_THRESH_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_HIGH_THRESH_DETECT_SHIFT)) & MED_DC_SCALER_SCALE_OFIFO_CTRL_ENABLE_HIGH_THRESH_DETECT_MASK) |
| /*! @} */ |
| |
| /*! @name SCALE_SRC_DATA_CTRL - Scale Source Data Control Register */ |
| /*! @{ */ |
| #define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_SRC_SELECT_MASK (0x1U) |
| #define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_SRC_SELECT_SHIFT (0U) |
| #define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_SRC_SELECT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_DATA_CTRL_SRC_SELECT_SHIFT)) & MED_DC_SCALER_SCALE_SRC_DATA_CTRL_SRC_SELECT_MASK) |
| #define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_RTRAM_LINES_PER_BANK_MASK (0x2U) |
| #define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_RTRAM_LINES_PER_BANK_SHIFT (1U) |
| #define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_RTRAM_LINES_PER_BANK(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_DATA_CTRL_RTRAM_LINES_PER_BANK_SHIFT)) & MED_DC_SCALER_SCALE_SRC_DATA_CTRL_RTRAM_LINES_PER_BANK_MASK) |
| #define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_Y_UV_BYTE_SWAP_MASK (0x10U) |
| #define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_Y_UV_BYTE_SWAP_SHIFT (4U) |
| #define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_Y_UV_BYTE_SWAP(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_DATA_CTRL_Y_UV_BYTE_SWAP_SHIFT)) & MED_DC_SCALER_SCALE_SRC_DATA_CTRL_Y_UV_BYTE_SWAP_MASK) |
| #define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_A2R10G10B10_FORMAT_MASK (0xF00U) |
| #define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_A2R10G10B10_FORMAT_SHIFT (8U) |
| #define MED_DC_SCALER_SCALE_SRC_DATA_CTRL_A2R10G10B10_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_DATA_CTRL_A2R10G10B10_FORMAT_SHIFT)) & MED_DC_SCALER_SCALE_SRC_DATA_CTRL_A2R10G10B10_FORMAT_MASK) |
| /*! @} */ |
| |
| /*! @name SCALE_BIT_DEPTH - Scale Bit Depth Control Register */ |
| /*! @{ */ |
| #define MED_DC_SCALER_SCALE_BIT_DEPTH_LUMA_BIT_DEPTH_MASK (0x3U) |
| #define MED_DC_SCALER_SCALE_BIT_DEPTH_LUMA_BIT_DEPTH_SHIFT (0U) |
| #define MED_DC_SCALER_SCALE_BIT_DEPTH_LUMA_BIT_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_BIT_DEPTH_LUMA_BIT_DEPTH_SHIFT)) & MED_DC_SCALER_SCALE_BIT_DEPTH_LUMA_BIT_DEPTH_MASK) |
| #define MED_DC_SCALER_SCALE_BIT_DEPTH_CHROMA_BIT_DEPTH_MASK (0x30U) |
| #define MED_DC_SCALER_SCALE_BIT_DEPTH_CHROMA_BIT_DEPTH_SHIFT (4U) |
| #define MED_DC_SCALER_SCALE_BIT_DEPTH_CHROMA_BIT_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_BIT_DEPTH_CHROMA_BIT_DEPTH_SHIFT)) & MED_DC_SCALER_SCALE_BIT_DEPTH_CHROMA_BIT_DEPTH_MASK) |
| /*! @} */ |
| |
| /*! @name SCALE_SRC_FORMAT - Scale Source Format Control Register */ |
| /*! @{ */ |
| #define MED_DC_SCALER_SCALE_SRC_FORMAT_SRC_FORMAT_MASK (0x3U) |
| #define MED_DC_SCALER_SCALE_SRC_FORMAT_SRC_FORMAT_SHIFT (0U) |
| #define MED_DC_SCALER_SCALE_SRC_FORMAT_SRC_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_FORMAT_SRC_FORMAT_SHIFT)) & MED_DC_SCALER_SCALE_SRC_FORMAT_SRC_FORMAT_MASK) |
| /*! @} */ |
| |
| /*! @name SCALE_DST_FORMAT - Scale Destination Format Control Register */ |
| /*! @{ */ |
| #define MED_DC_SCALER_SCALE_DST_FORMAT_DST_FORMAT_MASK (0x3U) |
| #define MED_DC_SCALER_SCALE_DST_FORMAT_DST_FORMAT_SHIFT (0U) |
| #define MED_DC_SCALER_SCALE_DST_FORMAT_DST_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_DST_FORMAT_DST_FORMAT_SHIFT)) & MED_DC_SCALER_SCALE_DST_FORMAT_DST_FORMAT_MASK) |
| /*! @} */ |
| |
| /*! @name SCALE_SRC_LUMA_RES - Scale Source Luma Resolution Register */ |
| /*! @{ */ |
| #define MED_DC_SCALER_SCALE_SRC_LUMA_RES_WIDTH_MASK (0xFFFU) |
| #define MED_DC_SCALER_SCALE_SRC_LUMA_RES_WIDTH_SHIFT (0U) |
| #define MED_DC_SCALER_SCALE_SRC_LUMA_RES_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_LUMA_RES_WIDTH_SHIFT)) & MED_DC_SCALER_SCALE_SRC_LUMA_RES_WIDTH_MASK) |
| #define MED_DC_SCALER_SCALE_SRC_LUMA_RES_HEIGHT_MASK (0xFFF0000U) |
| #define MED_DC_SCALER_SCALE_SRC_LUMA_RES_HEIGHT_SHIFT (16U) |
| #define MED_DC_SCALER_SCALE_SRC_LUMA_RES_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_LUMA_RES_HEIGHT_SHIFT)) & MED_DC_SCALER_SCALE_SRC_LUMA_RES_HEIGHT_MASK) |
| /*! @} */ |
| |
| /*! @name SCALE_SRC_CHROMA_RES - Scale Source Chroma Resolution Register */ |
| /*! @{ */ |
| #define MED_DC_SCALER_SCALE_SRC_CHROMA_RES_WIDTH_MASK (0xFFFU) |
| #define MED_DC_SCALER_SCALE_SRC_CHROMA_RES_WIDTH_SHIFT (0U) |
| #define MED_DC_SCALER_SCALE_SRC_CHROMA_RES_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_CHROMA_RES_WIDTH_SHIFT)) & MED_DC_SCALER_SCALE_SRC_CHROMA_RES_WIDTH_MASK) |
| #define MED_DC_SCALER_SCALE_SRC_CHROMA_RES_HEIGHT_MASK (0xFFF0000U) |
| #define MED_DC_SCALER_SCALE_SRC_CHROMA_RES_HEIGHT_SHIFT (16U) |
| #define MED_DC_SCALER_SCALE_SRC_CHROMA_RES_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_SRC_CHROMA_RES_HEIGHT_SHIFT)) & MED_DC_SCALER_SCALE_SRC_CHROMA_RES_HEIGHT_MASK) |
| /*! @} */ |
| |
| /*! @name SCALE_DST_LUMA_RES - Scale Destination Luma Resolution Register */ |
| /*! @{ */ |
| #define MED_DC_SCALER_SCALE_DST_LUMA_RES_WIDTH_MASK (0xFFFU) |
| #define MED_DC_SCALER_SCALE_DST_LUMA_RES_WIDTH_SHIFT (0U) |
| #define MED_DC_SCALER_SCALE_DST_LUMA_RES_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_DST_LUMA_RES_WIDTH_SHIFT)) & MED_DC_SCALER_SCALE_DST_LUMA_RES_WIDTH_MASK) |
| #define MED_DC_SCALER_SCALE_DST_LUMA_RES_HEIGHT_MASK (0xFFF0000U) |
| #define MED_DC_SCALER_SCALE_DST_LUMA_RES_HEIGHT_SHIFT (16U) |
| #define MED_DC_SCALER_SCALE_DST_LUMA_RES_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_DST_LUMA_RES_HEIGHT_SHIFT)) & MED_DC_SCALER_SCALE_DST_LUMA_RES_HEIGHT_MASK) |
| /*! @} */ |
| |
| /*! @name SCALE_DST_CHROMA_RES - Scale Destination Chroma Resolution Register */ |
| /*! @{ */ |
| #define MED_DC_SCALER_SCALE_DST_CHROMA_RES_WIDTH_MASK (0xFFFU) |
| #define MED_DC_SCALER_SCALE_DST_CHROMA_RES_WIDTH_SHIFT (0U) |
| #define MED_DC_SCALER_SCALE_DST_CHROMA_RES_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_DST_CHROMA_RES_WIDTH_SHIFT)) & MED_DC_SCALER_SCALE_DST_CHROMA_RES_WIDTH_MASK) |
| /*! @} */ |
| |
| /*! @name SCALE_V_LUMA_START - Scale Vertical Luma Start Register */ |
| /*! @{ */ |
| #define MED_DC_SCALER_SCALE_V_LUMA_START_V_START_MASK (0x3FFFFFFU) |
| #define MED_DC_SCALER_SCALE_V_LUMA_START_V_START_SHIFT (0U) |
| #define MED_DC_SCALER_SCALE_V_LUMA_START_V_START(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_V_LUMA_START_V_START_SHIFT)) & MED_DC_SCALER_SCALE_V_LUMA_START_V_START_MASK) |
| /*! @} */ |
| |
| /*! @name SCALE_V_LUMA_INC - Scale Vertical Luma Increment Register */ |
| /*! @{ */ |
| #define MED_DC_SCALER_SCALE_V_LUMA_INC_V_INC_MASK (0xFFFFFU) |
| #define MED_DC_SCALER_SCALE_V_LUMA_INC_V_INC_SHIFT (0U) |
| #define MED_DC_SCALER_SCALE_V_LUMA_INC_V_INC(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_V_LUMA_INC_V_INC_SHIFT)) & MED_DC_SCALER_SCALE_V_LUMA_INC_V_INC_MASK) |
| /*! @} */ |
| |
| /*! @name SCALE_H_LUMA_START - Scale Horizontal Luma Start Register */ |
| /*! @{ */ |
| #define MED_DC_SCALER_SCALE_H_LUMA_START_H_START_MASK (0x3FFFFFFU) |
| #define MED_DC_SCALER_SCALE_H_LUMA_START_H_START_SHIFT (0U) |
| #define MED_DC_SCALER_SCALE_H_LUMA_START_H_START(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_H_LUMA_START_H_START_SHIFT)) & MED_DC_SCALER_SCALE_H_LUMA_START_H_START_MASK) |
| /*! @} */ |
| |
| /*! @name SCALE_H_LUMA_INC - Scale Horizontal Luma Increment Register */ |
| /*! @{ */ |
| #define MED_DC_SCALER_SCALE_H_LUMA_INC_H_INC_MASK (0xFFFFFU) |
| #define MED_DC_SCALER_SCALE_H_LUMA_INC_H_INC_SHIFT (0U) |
| #define MED_DC_SCALER_SCALE_H_LUMA_INC_H_INC(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_H_LUMA_INC_H_INC_SHIFT)) & MED_DC_SCALER_SCALE_H_LUMA_INC_H_INC_MASK) |
| /*! @} */ |
| |
| /*! @name SCALE_V_CHROMA_START - Scale Vertical Chroma Start Register */ |
| /*! @{ */ |
| #define MED_DC_SCALER_SCALE_V_CHROMA_START_V_START_MASK (0x3FFFFFFU) |
| #define MED_DC_SCALER_SCALE_V_CHROMA_START_V_START_SHIFT (0U) |
| #define MED_DC_SCALER_SCALE_V_CHROMA_START_V_START(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_V_CHROMA_START_V_START_SHIFT)) & MED_DC_SCALER_SCALE_V_CHROMA_START_V_START_MASK) |
| /*! @} */ |
| |
| /*! @name SCALE_V_CHROMA_INC - Scale Vertical Chroma Increment Register */ |
| /*! @{ */ |
| #define MED_DC_SCALER_SCALE_V_CHROMA_INC_V_INC_MASK (0xFFFFFU) |
| #define MED_DC_SCALER_SCALE_V_CHROMA_INC_V_INC_SHIFT (0U) |
| #define MED_DC_SCALER_SCALE_V_CHROMA_INC_V_INC(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_V_CHROMA_INC_V_INC_SHIFT)) & MED_DC_SCALER_SCALE_V_CHROMA_INC_V_INC_MASK) |
| /*! @} */ |
| |
| /*! @name SCALE_H_CHROMA_START - Scale Horizontal Chroma Start Register */ |
| /*! @{ */ |
| #define MED_DC_SCALER_SCALE_H_CHROMA_START_H_START_MASK (0x3FFFFFFU) |
| #define MED_DC_SCALER_SCALE_H_CHROMA_START_H_START_SHIFT (0U) |
| #define MED_DC_SCALER_SCALE_H_CHROMA_START_H_START(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_H_CHROMA_START_H_START_SHIFT)) & MED_DC_SCALER_SCALE_H_CHROMA_START_H_START_MASK) |
| /*! @} */ |
| |
| /*! @name SCALE_H_CHROMA_INC - Scale Horizontal Chroma Increment Register */ |
| /*! @{ */ |
| #define MED_DC_SCALER_SCALE_H_CHROMA_INC_H_INC_MASK (0xFFFFFU) |
| #define MED_DC_SCALER_SCALE_H_CHROMA_INC_H_INC_SHIFT (0U) |
| #define MED_DC_SCALER_SCALE_H_CHROMA_INC_H_INC(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_H_CHROMA_INC_H_INC_SHIFT)) & MED_DC_SCALER_SCALE_H_CHROMA_INC_H_INC_MASK) |
| /*! @} */ |
| |
| /*! @name SCALE_COEF_ARRAY - Scale Coefficient Memory Array */ |
| /*! @{ */ |
| #define MED_DC_SCALER_SCALE_COEF_ARRAY_COEF_MASK (0xFFFU) |
| #define MED_DC_SCALER_SCALE_COEF_ARRAY_COEF_SHIFT (0U) |
| #define MED_DC_SCALER_SCALE_COEF_ARRAY_COEF(x) (((uint32_t)(((uint32_t)(x)) << MED_DC_SCALER_SCALE_COEF_ARRAY_COEF_SHIFT)) & MED_DC_SCALER_SCALE_COEF_ARRAY_COEF_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group MED_DC_SCALER_Register_Masks */ |
| |
| |
| /* MED_DC_SCALER - Peripheral instance base addresses */ |
| /** Peripheral DCSS__MED_DC_SCALER base address */ |
| #define DCSS__MED_DC_SCALER_BASE (0x32E1C000u) |
| /** Peripheral DCSS__MED_DC_SCALER base pointer */ |
| #define DCSS__MED_DC_SCALER ((MED_DC_SCALER_Type *)DCSS__MED_DC_SCALER_BASE) |
| /** Array initializer of MED_DC_SCALER peripheral base addresses */ |
| #define MED_DC_SCALER_BASE_ADDRS { DCSS__MED_DC_SCALER_BASE } |
| /** Array initializer of MED_DC_SCALER peripheral base pointers */ |
| #define MED_DC_SCALER_BASE_PTRS { DCSS__MED_DC_SCALER } |
| |
| /*! |
| * @} |
| */ /* end of group MED_DC_SCALER_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- MED_HDR10 Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MED_HDR10_Peripheral_Access_Layer MED_HDR10 Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** MED_HDR10 - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t PIPE1_A0_LUT; /**< A0 component Look-Up-Table. (LUT), offset: 0x0 */ |
| uint8_t RESERVED_0[4092]; |
| __IO uint32_t PIPE1_A1_LUT; /**< A1 component Look-Up-Table. (LUT), offset: 0x1000 */ |
| uint8_t RESERVED_1[4092]; |
| __IO uint32_t PIPE1_A2_LUT; /**< A2 component Look-Up-Table. (LUT), offset: 0x2000 */ |
| uint8_t RESERVED_2[4092]; |
| __IO uint32_t HDR_PIPE1_CSCA_CONTROL_REG; /**< Pipe1 Colorspace Converter A control., offset: 0x3000 */ |
| __IO uint32_t HDR_PIPE1_CSCA_H00; /**< Pipe1 Colorspace Converter A (CSCA) h(0,0) matrix coefficient, offset: 0x3004 */ |
| __IO uint32_t HDR_PIPE1_CSCA_H10; /**< Pipe1 Colorspace Converter A (CSCA) h(1,0) matrix coefficient, offset: 0x3008 */ |
| __IO uint32_t HDR_PIPE1_CSCA_H20; /**< Pipe1 Colorspace Converter A (CSCA) h(2,0) matrix coefficient, offset: 0x300C */ |
| __IO uint32_t HDR_PIPE1_CSCA_H01; /**< Pipe1 Colorspace Converter A (CSCA) h(0,1) matrix coefficient, offset: 0x3010 */ |
| __IO uint32_t HDR_PIPE1_CSCA_H11; /**< Pipe1 Colorspace Converter A (CSCA) h(1,1) matrix coefficient, offset: 0x3014 */ |
| __IO uint32_t HDR_PIPE1_CSCA_H21; /**< Pipe1 Colorspace Converter A (CSCA) h(2,1) matrix coefficient, offset: 0x3018 */ |
| __IO uint32_t HDR_PIPE1_CSCA_H02; /**< Pipe1 Colorspace Converter A (CSCA) h(0,2) matrix coefficient, offset: 0x301C */ |
| __IO uint32_t HDR_PIPE1_CSCA_H12; /**< Pipe1 Colorspace Converter A (CSCA) h(1,2) matrix coefficient, offset: 0x3020 */ |
| __IO uint32_t HDR_PIPE1_CSCA_H22; /**< Pipe1 Colorspace Converter A (CSCA) h(2,2) matrix coefficient, offset: 0x3024 */ |
| __IO uint32_t HDR_PIPE1_CSCA_IO_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 pre-offset, offset: 0x3028 */ |
| __IO uint32_t HDR_PIPE1_CSCA_IO_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 pre-offset, offset: 0x302C */ |
| __IO uint32_t HDR_PIPE1_CSCA_IO_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 pre-offset, offset: 0x3030 */ |
| __IO uint32_t HDR_PIPE1_CSCA_IO_MIN_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 clip min., offset: 0x3034 */ |
| __IO uint32_t HDR_PIPE1_CSCA_IO_MIN_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 clip min., offset: 0x3038 */ |
| __IO uint32_t HDR_PIPE1_CSCA_IO_MIN_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 clip min., offset: 0x303C */ |
| __IO uint32_t HDR_PIPE1_CSCA_IO_MAX_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 clip max value., offset: 0x3040 */ |
| __IO uint32_t HDR_PIPE1_CSCA_IO_MAX_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 clip max value., offset: 0x3044 */ |
| __IO uint32_t HDR_PIPE1_CSCA_IO_MAX_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 clip max value., offset: 0x3048 */ |
| __IO uint32_t HDR_PIPE1_CSCA_NORM; /**< Pipe1 Colorspace Converter A (CSCA) normalization factor, offset: 0x304C */ |
| __IO uint32_t HDR_PIPE1_CSCA_OO_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 0, offset: 0x3050 */ |
| __IO uint32_t HDR_PIPE1_CSCA_OO_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 1, offset: 0x3054 */ |
| __IO uint32_t HDR_PIPE1_CSCA_OO_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 2, offset: 0x3058 */ |
| __IO uint32_t HDR_PIPE1_CSCA_OMIN_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 0, offset: 0x305C */ |
| __IO uint32_t HDR_PIPE1_CSCA_OMIN_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 1, offset: 0x3060 */ |
| __IO uint32_t HDR_PIPE1_CSCA_OMIN_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 2, offset: 0x3064 */ |
| __IO uint32_t HDR_PIPE1_CSCA_OMAX_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 0, offset: 0x3068 */ |
| __IO uint32_t HDR_PIPE1_CSCA_OMAX_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 1, offset: 0x306C */ |
| __IO uint32_t HDR_PIPE1_CSCA_OMAX_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 2, offset: 0x3070 */ |
| uint32_t HDR_PIPE1_ENTRY_29; /**< PIPE1: NOT USED, offset: 0x3074 */ |
| uint8_t RESERVED_3[8]; |
| __IO uint32_t HDR_PIPE1_LUT_CONTROL_REG; /**< Pipe1 LUT control register, offset: 0x3080 */ |
| uint8_t RESERVED_4[1916]; |
| __IO uint32_t HDR_PIPE1_CSCB_CONTROL_REG; /**< Pipe1 Colorspace Converter B control., offset: 0x3800 */ |
| __IO uint32_t HDR_PIPE1_CSCB_H00; /**< Pipe1 Colorspace Converter A (CSCB) h(0,0) matrix coefficient, offset: 0x3804 */ |
| __IO uint32_t HDR_PIPE1_CSCB_H10; /**< Pipe1 Colorspace Converter B (CSCB) h(1,0) matrix coefficient, offset: 0x3808 */ |
| __IO uint32_t HDR_PIPE1_CSCB_H20; /**< Pipe1 Colorspace Converter B (CSCB) h(2,0) matrix coefficient, offset: 0x380C */ |
| __IO uint32_t HDR_PIPE1_CSCB_H01; /**< Pipe1 Colorspace Converter B (CSCB) h(0,1) matrix coefficient, offset: 0x3810 */ |
| __IO uint32_t HDR_PIPE1_CSCB_H11; /**< Pipe1 Colorspace Converter B (CSCB) h(1,1) matrix coefficient, offset: 0x3814 */ |
| __IO uint32_t HDR_PIPE1_CSCB_H21; /**< Pipe1 Colorspace Converter B (CSCB) h(2,1) matrix coefficient, offset: 0x3818 */ |
| __IO uint32_t HDR_PIPE1_CSCB_H02; /**< Pipe1 Colorspace Converter B (CSCB) h(0,2) matrix coefficient, offset: 0x381C */ |
| __IO uint32_t HDR_PIPE1_CSCB_H12; /**< Pipe1 Colorspace Converter B (CSCB) h(1,2) matrix coefficient, offset: 0x3820 */ |
| __IO uint32_t HDR_PIPE1_CSCB_H22; /**< Pipe1 Colorspace Converter B (CSCB) h(2,2) matrix coefficient, offset: 0x3824 */ |
| __IO uint32_t HDR_PIPE1_CSCB_IO_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 pre-offset, offset: 0x3828 */ |
| __IO uint32_t HDR_PIPE1_CSCB_IO_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 pre-offset, offset: 0x382C */ |
| __IO uint32_t HDR_PIPE1_CSCB_IO_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 pre-offset, offset: 0x3830 */ |
| __IO uint32_t HDR_PIPE1_CSCB_IO_MIN_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 clip min., offset: 0x3834 */ |
| __IO uint32_t HDR_PIPE1_CSCB_IO_MIN_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 clip min., offset: 0x3838 */ |
| __IO uint32_t HDR_PIPE1_CSCB_IO_MIN_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 clip min., offset: 0x383C */ |
| __IO uint32_t HDR_PIPE1_CSCB_IO_MAX_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 clip max value., offset: 0x3840 */ |
| __IO uint32_t HDR_PIPE1_CSCB_IO_MAX_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 clip max value., offset: 0x3844 */ |
| __IO uint32_t HDR_PIPE1_CSCB_IO_MAX_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 clip max value., offset: 0x3848 */ |
| __IO uint32_t HDR_PIPE1_CSCB_NORM; /**< Pipe1 Colorspace Converter B (CSCB) normalization factor, offset: 0x384C */ |
| __IO uint32_t HDR_PIPE1_CSCB_OO_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 0, offset: 0x3850 */ |
| __IO uint32_t HDR_PIPE1_CSCB_OO_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 1, offset: 0x3854 */ |
| __IO uint32_t HDR_PIPE1_CSCB_OO_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 2, offset: 0x3858 */ |
| __IO uint32_t HDR_PIPE1_CSCB_OMIN_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 0, offset: 0x385C */ |
| __IO uint32_t HDR_PIPE1_CSCB_OMIN_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 1, offset: 0x3860 */ |
| __IO uint32_t HDR_PIPE1_CSCB_OMIN_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 2, offset: 0x3864 */ |
| __IO uint32_t HDR_PIPE1_CSCB_OMAX_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 0, offset: 0x3868 */ |
| __IO uint32_t HDR_PIPE1_CSCB_OMAX_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 1, offset: 0x386C */ |
| __IO uint32_t HDR_PIPE1_CSCB_OMAX_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 2, offset: 0x3870 */ |
| __IO uint32_t HDR_PIPE1_FL2FX; /**< Pipe1 floating point to fixed point control, offset: 0x3874 */ |
| uint32_t HDR_PIPE1_ENTRY_30; /**< PIPE1: NOT USED, offset: 0x3878 */ |
| uint8_t RESERVED_5[1924]; |
| __IO uint32_t PIPE2_A0_LUT; /**< A0 component Look-Up-Table. (LUT), offset: 0x4000 */ |
| uint8_t RESERVED_6[4092]; |
| __IO uint32_t PIPE2_A1_LUT; /**< A1 component Look-Up-Table. (LUT), offset: 0x5000 */ |
| uint8_t RESERVED_7[4092]; |
| __IO uint32_t PIPE2_A2_LUT; /**< A2 component Look-Up-Table. (LUT), offset: 0x6000 */ |
| uint8_t RESERVED_8[4092]; |
| __IO uint32_t HDR_PIPE2_CSCA_CONTROL_REG; /**< Pipe1 Colorspace Converter A control., offset: 0x7000 */ |
| __IO uint32_t HDR_PIPE2_CSCA_H00; /**< Pipe1 Colorspace Converter A (CSCA) h(0,0) matrix coefficient, offset: 0x7004 */ |
| __IO uint32_t HDR_PIPE2_CSCA_H10; /**< Pipe1 Colorspace Converter A (CSCA) h(1,0) matrix coefficient, offset: 0x7008 */ |
| __IO uint32_t HDR_PIPE2_CSCA_H20; /**< Pipe1 Colorspace Converter A (CSCA) h(2,0) matrix coefficient, offset: 0x700C */ |
| __IO uint32_t HDR_PIPE2_CSCA_H01; /**< Pipe1 Colorspace Converter A (CSCA) h(0,1) matrix coefficient, offset: 0x7010 */ |
| __IO uint32_t HDR_PIPE2_CSCA_H11; /**< Pipe1 Colorspace Converter A (CSCA) h(1,1) matrix coefficient, offset: 0x7014 */ |
| __IO uint32_t HDR_PIPE2_CSCA_H21; /**< Pipe1 Colorspace Converter A (CSCA) h(2,1) matrix coefficient, offset: 0x7018 */ |
| __IO uint32_t HDR_PIPE2_CSCA_H02; /**< Pipe1 Colorspace Converter A (CSCA) h(0,2) matrix coefficient, offset: 0x701C */ |
| __IO uint32_t HDR_PIPE2_CSCA_H12; /**< Pipe1 Colorspace Converter A (CSCA) h(1,2) matrix coefficient, offset: 0x7020 */ |
| __IO uint32_t HDR_PIPE2_CSCA_H22; /**< Pipe1 Colorspace Converter A (CSCA) h(2,2) matrix coefficient, offset: 0x7024 */ |
| __IO uint32_t HDR_PIPE2_CSCA_IO_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 pre-offset, offset: 0x7028 */ |
| __IO uint32_t HDR_PIPE2_CSCA_IO_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 pre-offset, offset: 0x702C */ |
| __IO uint32_t HDR_PIPE2_CSCA_IO_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 pre-offset, offset: 0x7030 */ |
| __IO uint32_t HDR_PIPE2_CSCA_IO_MIN_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 clip min., offset: 0x7034 */ |
| __IO uint32_t HDR_PIPE2_CSCA_IO_MIN_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 clip min., offset: 0x7038 */ |
| __IO uint32_t HDR_PIPE2_CSCA_IO_MIN_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 clip min., offset: 0x703C */ |
| __IO uint32_t HDR_PIPE2_CSCA_IO_MAX_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 clip max value., offset: 0x7040 */ |
| __IO uint32_t HDR_PIPE2_CSCA_IO_MAX_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 clip max value., offset: 0x7044 */ |
| __IO uint32_t HDR_PIPE2_CSCA_IO_MAX_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 clip max value., offset: 0x7048 */ |
| __IO uint32_t HDR_PIPE2_CSCA_NORM; /**< Pipe1 Colorspace Converter A (CSCA) normalization factor, offset: 0x704C */ |
| __IO uint32_t HDR_PIPE2_CSCA_OO_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 0, offset: 0x7050 */ |
| __IO uint32_t HDR_PIPE2_CSCA_OO_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 1, offset: 0x7054 */ |
| __IO uint32_t HDR_PIPE2_CSCA_OO_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 2, offset: 0x7058 */ |
| __IO uint32_t HDR_PIPE2_CSCA_OMIN_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 0, offset: 0x705C */ |
| __IO uint32_t HDR_PIPE2_CSCA_OMIN_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 1, offset: 0x7060 */ |
| __IO uint32_t HDR_PIPE2_CSCA_OMIN_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 2, offset: 0x7064 */ |
| __IO uint32_t HDR_PIPE2_CSCA_OMAX_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 0, offset: 0x7068 */ |
| __IO uint32_t HDR_PIPE2_CSCA_OMAX_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 1, offset: 0x706C */ |
| __IO uint32_t HDR_PIPE2_CSCA_OMAX_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 2, offset: 0x7070 */ |
| uint32_t HDR_PIPE2_ENTRY_29; /**< PIPE2: NOT USED, offset: 0x7074 */ |
| uint8_t RESERVED_9[8]; |
| __IO uint32_t HDR_PIPE2_LUT_CONTROL_REG; /**< Pipe1 LUT control register, offset: 0x7080 */ |
| uint8_t RESERVED_10[1916]; |
| __IO uint32_t HDR_PIPE2_CSCB_CONTROL_REG; /**< Pipe1 Colorspace Converter B control., offset: 0x7800 */ |
| __IO uint32_t HDR_PIPE2_CSCB_H00; /**< Pipe1 Colorspace Converter A (CSCB) h(0,0) matrix coefficient, offset: 0x7804 */ |
| __IO uint32_t HDR_PIPE2_CSCB_H10; /**< Pipe1 Colorspace Converter B (CSCB) h(1,0) matrix coefficient, offset: 0x7808 */ |
| __IO uint32_t HDR_PIPE2_CSCB_H20; /**< Pipe1 Colorspace Converter B (CSCB) h(2,0) matrix coefficient, offset: 0x780C */ |
| __IO uint32_t HDR_PIPE2_CSCB_H01; /**< Pipe1 Colorspace Converter B (CSCB) h(0,1) matrix coefficient, offset: 0x7810 */ |
| __IO uint32_t HDR_PIPE2_CSCB_H11; /**< Pipe1 Colorspace Converter B (CSCB) h(1,1) matrix coefficient, offset: 0x7814 */ |
| __IO uint32_t HDR_PIPE2_CSCB_H21; /**< Pipe1 Colorspace Converter B (CSCB) h(2,1) matrix coefficient, offset: 0x7818 */ |
| __IO uint32_t HDR_PIPE2_CSCB_H02; /**< Pipe1 Colorspace Converter B (CSCB) h(0,2) matrix coefficient, offset: 0x781C */ |
| __IO uint32_t HDR_PIPE2_CSCB_H12; /**< Pipe1 Colorspace Converter B (CSCB) h(1,2) matrix coefficient, offset: 0x7820 */ |
| __IO uint32_t HDR_PIPE2_CSCB_H22; /**< Pipe1 Colorspace Converter B (CSCB) h(2,2) matrix coefficient, offset: 0x7824 */ |
| __IO uint32_t HDR_PIPE2_CSCB_IO_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 pre-offset, offset: 0x7828 */ |
| __IO uint32_t HDR_PIPE2_CSCB_IO_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 pre-offset, offset: 0x782C */ |
| __IO uint32_t HDR_PIPE2_CSCB_IO_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 pre-offset, offset: 0x7830 */ |
| __IO uint32_t HDR_PIPE2_CSCB_IO_MIN_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 clip min., offset: 0x7834 */ |
| __IO uint32_t HDR_PIPE2_CSCB_IO_MIN_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 clip min., offset: 0x7838 */ |
| __IO uint32_t HDR_PIPE2_CSCB_IO_MIN_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 clip min., offset: 0x783C */ |
| __IO uint32_t HDR_PIPE2_CSCB_IO_MAX_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 clip max value., offset: 0x7840 */ |
| __IO uint32_t HDR_PIPE2_CSCB_IO_MAX_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 clip max value., offset: 0x7844 */ |
| __IO uint32_t HDR_PIPE2_CSCB_IO_MAX_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 clip max value., offset: 0x7848 */ |
| __IO uint32_t HDR_PIPE2_CSCB_NORM; /**< Pipe1 Colorspace Converter B (CSCB) normalization factor, offset: 0x784C */ |
| __IO uint32_t HDR_PIPE2_CSCB_OO_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 0, offset: 0x7850 */ |
| __IO uint32_t HDR_PIPE2_CSCB_OO_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 1, offset: 0x7854 */ |
| __IO uint32_t HDR_PIPE2_CSCB_OO_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 2, offset: 0x7858 */ |
| __IO uint32_t HDR_PIPE2_CSCB_OMIN_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 0, offset: 0x785C */ |
| __IO uint32_t HDR_PIPE2_CSCB_OMIN_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 1, offset: 0x7860 */ |
| __IO uint32_t HDR_PIPE2_CSCB_OMIN_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 2, offset: 0x7864 */ |
| __IO uint32_t HDR_PIPE2_CSCB_OMAX_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 0, offset: 0x7868 */ |
| __IO uint32_t HDR_PIPE2_CSCB_OMAX_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 1, offset: 0x786C */ |
| __IO uint32_t HDR_PIPE2_CSCB_OMAX_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 2, offset: 0x7870 */ |
| __IO uint32_t HDR_PIPE2_FL2FX; /**< Pipe1 floating point to fixed point control, offset: 0x7874 */ |
| uint32_t HDR_PIPE2_ENTRY_30; /**< PIPE2: NOT USED, offset: 0x7878 */ |
| uint8_t RESERVED_11[1924]; |
| __IO uint32_t PIPE3_A0_LUT; /**< A0 component Look-Up-Table. (LUT), offset: 0x8000 */ |
| uint8_t RESERVED_12[4092]; |
| __IO uint32_t PIPE3_A1_LUT; /**< A1 component Look-Up-Table. (LUT), offset: 0x9000 */ |
| uint8_t RESERVED_13[4092]; |
| __IO uint32_t PIPE3_A2_LUT; /**< A2 component Look-Up-Table. (LUT), offset: 0xA000 */ |
| uint8_t RESERVED_14[4092]; |
| __IO uint32_t HDR_PIPE3_CSCA_CONTROL_REG; /**< Pipe1 Colorspace Converter A control., offset: 0xB000 */ |
| __IO uint32_t HDR_PIPE3_CSCA_H00; /**< Pipe1 Colorspace Converter A (CSCA) h(0,0) matrix coefficient, offset: 0xB004 */ |
| __IO uint32_t HDR_PIPE3_CSCA_H10; /**< Pipe1 Colorspace Converter A (CSCA) h(1,0) matrix coefficient, offset: 0xB008 */ |
| __IO uint32_t HDR_PIPE3_CSCA_H20; /**< Pipe1 Colorspace Converter A (CSCA) h(2,0) matrix coefficient, offset: 0xB00C */ |
| __IO uint32_t HDR_PIPE3_CSCA_H01; /**< Pipe1 Colorspace Converter A (CSCA) h(0,1) matrix coefficient, offset: 0xB010 */ |
| __IO uint32_t HDR_PIPE3_CSCA_H11; /**< Pipe1 Colorspace Converter A (CSCA) h(1,1) matrix coefficient, offset: 0xB014 */ |
| __IO uint32_t HDR_PIPE3_CSCA_H21; /**< Pipe1 Colorspace Converter A (CSCA) h(2,1) matrix coefficient, offset: 0xB018 */ |
| __IO uint32_t HDR_PIPE3_CSCA_H02; /**< Pipe1 Colorspace Converter A (CSCA) h(0,2) matrix coefficient, offset: 0xB01C */ |
| __IO uint32_t HDR_PIPE3_CSCA_H12; /**< Pipe1 Colorspace Converter A (CSCA) h(1,2) matrix coefficient, offset: 0xB020 */ |
| __IO uint32_t HDR_PIPE3_CSCA_H22; /**< Pipe1 Colorspace Converter A (CSCA) h(2,2) matrix coefficient, offset: 0xB024 */ |
| __IO uint32_t HDR_PIPE3_CSCA_IO_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 pre-offset, offset: 0xB028 */ |
| __IO uint32_t HDR_PIPE3_CSCA_IO_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 pre-offset, offset: 0xB02C */ |
| __IO uint32_t HDR_PIPE3_CSCA_IO_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 pre-offset, offset: 0xB030 */ |
| __IO uint32_t HDR_PIPE3_CSCA_IO_MIN_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 clip min., offset: 0xB034 */ |
| __IO uint32_t HDR_PIPE3_CSCA_IO_MIN_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 clip min., offset: 0xB038 */ |
| __IO uint32_t HDR_PIPE3_CSCA_IO_MIN_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 clip min., offset: 0xB03C */ |
| __IO uint32_t HDR_PIPE3_CSCA_IO_MAX_0; /**< Pipe1 Colorspace Converter A (CSCA) component 0 clip max value., offset: 0xB040 */ |
| __IO uint32_t HDR_PIPE3_CSCA_IO_MAX_1; /**< Pipe1 Colorspace Converter A (CSCA) component 1 clip max value., offset: 0xB044 */ |
| __IO uint32_t HDR_PIPE3_CSCA_IO_MAX_2; /**< Pipe1 Colorspace Converter A (CSCA) component 2 clip max value., offset: 0xB048 */ |
| __IO uint32_t HDR_PIPE3_CSCA_NORM; /**< Pipe1 Colorspace Converter A (CSCA) normalization factor, offset: 0xB04C */ |
| __IO uint32_t HDR_PIPE3_CSCA_OO_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 0, offset: 0xB050 */ |
| __IO uint32_t HDR_PIPE3_CSCA_OO_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 1, offset: 0xB054 */ |
| __IO uint32_t HDR_PIPE3_CSCA_OO_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset component 2, offset: 0xB058 */ |
| __IO uint32_t HDR_PIPE3_CSCA_OMIN_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 0, offset: 0xB05C */ |
| __IO uint32_t HDR_PIPE3_CSCA_OMIN_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 1, offset: 0xB060 */ |
| __IO uint32_t HDR_PIPE3_CSCA_OMIN_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 2, offset: 0xB064 */ |
| __IO uint32_t HDR_PIPE3_CSCA_OMAX_0; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 0, offset: 0xB068 */ |
| __IO uint32_t HDR_PIPE3_CSCA_OMAX_1; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 1, offset: 0xB06C */ |
| __IO uint32_t HDR_PIPE3_CSCA_OMAX_2; /**< Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 2, offset: 0xB070 */ |
| uint32_t HDR_PIPE3_ENTRY_29; /**< PIPE3: NOT USED, offset: 0xB074 */ |
| uint8_t RESERVED_15[8]; |
| __IO uint32_t HDR_PIPE3_LUT_CONTROL_REG; /**< Pipe1 LUT control register, offset: 0xB080 */ |
| uint8_t RESERVED_16[1916]; |
| __IO uint32_t HDR_PIPE3_CSCB_CONTROL_REG; /**< Pipe1 Colorspace Converter B control., offset: 0xB800 */ |
| __IO uint32_t HDR_PIPE3_CSCB_H00; /**< Pipe1 Colorspace Converter A (CSCB) h(0,0) matrix coefficient, offset: 0xB804 */ |
| __IO uint32_t HDR_PIPE3_CSCB_H10; /**< Pipe1 Colorspace Converter B (CSCB) h(1,0) matrix coefficient, offset: 0xB808 */ |
| __IO uint32_t HDR_PIPE3_CSCB_H20; /**< Pipe1 Colorspace Converter B (CSCB) h(2,0) matrix coefficient, offset: 0xB80C */ |
| __IO uint32_t HDR_PIPE3_CSCB_H01; /**< Pipe1 Colorspace Converter B (CSCB) h(0,1) matrix coefficient, offset: 0xB810 */ |
| __IO uint32_t HDR_PIPE3_CSCB_H11; /**< Pipe1 Colorspace Converter B (CSCB) h(1,1) matrix coefficient, offset: 0xB814 */ |
| __IO uint32_t HDR_PIPE3_CSCB_H21; /**< Pipe1 Colorspace Converter B (CSCB) h(2,1) matrix coefficient, offset: 0xB818 */ |
| __IO uint32_t HDR_PIPE3_CSCB_H02; /**< Pipe1 Colorspace Converter B (CSCB) h(0,2) matrix coefficient, offset: 0xB81C */ |
| __IO uint32_t HDR_PIPE3_CSCB_H12; /**< Pipe1 Colorspace Converter B (CSCB) h(1,2) matrix coefficient, offset: 0xB820 */ |
| __IO uint32_t HDR_PIPE3_CSCB_H22; /**< Pipe1 Colorspace Converter B (CSCB) h(2,2) matrix coefficient, offset: 0xB824 */ |
| __IO uint32_t HDR_PIPE3_CSCB_IO_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 pre-offset, offset: 0xB828 */ |
| __IO uint32_t HDR_PIPE3_CSCB_IO_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 pre-offset, offset: 0xB82C */ |
| __IO uint32_t HDR_PIPE3_CSCB_IO_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 pre-offset, offset: 0xB830 */ |
| __IO uint32_t HDR_PIPE3_CSCB_IO_MIN_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 clip min., offset: 0xB834 */ |
| __IO uint32_t HDR_PIPE3_CSCB_IO_MIN_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 clip min., offset: 0xB838 */ |
| __IO uint32_t HDR_PIPE3_CSCB_IO_MIN_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 clip min., offset: 0xB83C */ |
| __IO uint32_t HDR_PIPE3_CSCB_IO_MAX_0; /**< Pipe1 Colorspace Converter B (CSCB) component 0 clip max value., offset: 0xB840 */ |
| __IO uint32_t HDR_PIPE3_CSCB_IO_MAX_1; /**< Pipe1 Colorspace Converter B (CSCB) component 1 clip max value., offset: 0xB844 */ |
| __IO uint32_t HDR_PIPE3_CSCB_IO_MAX_2; /**< Pipe1 Colorspace Converter B (CSCB) component 2 clip max value., offset: 0xB848 */ |
| __IO uint32_t HDR_PIPE3_CSCB_NORM; /**< Pipe1 Colorspace Converter B (CSCB) normalization factor, offset: 0xB84C */ |
| __IO uint32_t HDR_PIPE3_CSCB_OO_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 0, offset: 0xB850 */ |
| __IO uint32_t HDR_PIPE3_CSCB_OO_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 1, offset: 0xB854 */ |
| __IO uint32_t HDR_PIPE3_CSCB_OO_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset component 2, offset: 0xB858 */ |
| __IO uint32_t HDR_PIPE3_CSCB_OMIN_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 0, offset: 0xB85C */ |
| __IO uint32_t HDR_PIPE3_CSCB_OMIN_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 1, offset: 0xB860 */ |
| __IO uint32_t HDR_PIPE3_CSCB_OMIN_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 2, offset: 0xB864 */ |
| __IO uint32_t HDR_PIPE3_CSCB_OMAX_0; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 0, offset: 0xB868 */ |
| __IO uint32_t HDR_PIPE3_CSCB_OMAX_1; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 1, offset: 0xB86C */ |
| __IO uint32_t HDR_PIPE3_CSCB_OMAX_2; /**< Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 2, offset: 0xB870 */ |
| __IO uint32_t HDR_PIPE3_FL2FX; /**< Pipe1 floating point to fixed point control, offset: 0xB874 */ |
| uint32_t HDR_PIPE3_ENTRY_30; /**< PIPE3: NOT USED, offset: 0xB878 */ |
| uint8_t RESERVED_17[1924]; |
| __IO uint32_t OPIPE_A0_TABLE; /**< A0 component Linear-to-Non-linear conversion table, offset: 0xC000 */ |
| uint8_t RESERVED_18[4092]; |
| __IO uint32_t OPIPE_A1_TABLE; /**< A1 component Linear-to-Non-linear conversion table, offset: 0xD000 */ |
| uint8_t RESERVED_19[4092]; |
| __IO uint32_t OPIPE_A2_TABLE; /**< A2 component Linear-to-Non-linear conversion table, offset: 0xE000 */ |
| uint8_t RESERVED_20[4092]; |
| __IO uint32_t HDR_OPIPE_CSC_CONTROL_REG; /**< HDR output stage Colorspace Converter (CSCO) control., offset: 0xF000 */ |
| __IO uint32_t HDR_OPIPE_CSC_H00; /**< Pipe1 Colorspace Converter (CSC) h(0,0) matrix coefficient, offset: 0xF004 */ |
| __IO uint32_t HDR_OPIPE_CSC_H10; /**< Pipe1 Colorspace Converter (CSC) h(1,0) matrix coefficient, offset: 0xF008 */ |
| __IO uint32_t HDR_OPIPE_CSC_H20; /**< HDR OUTPUT Colorspace Converter (CSCO) h(2,0) matrix coefficient, offset: 0xF00C */ |
| __IO uint32_t HDR_OPIPE_CSC_H01; /**< HDR OUTPUT pipe Colorspace Converter (CSCO) h(0,1) matrix coefficient, offset: 0xF010 */ |
| __IO uint32_t HDR_OPIPE_CSC_H11; /**< HDR OUTPUT pipe Colorspace Converter (CSCO) h(1,1) matrix coefficient, offset: 0xF014 */ |
| __IO uint32_t HDR_OPIPE_CSC_H21; /**< HDR_output pipe Colorspace Converter (CSCO) h(2,1) matrix coefficient, offset: 0xF018 */ |
| __IO uint32_t HDR_OPIPE_CSC_H02; /**< HDR OUTPUT pipe Colorspace Converter (CSCO) h(0,2) matrix coefficient, offset: 0xF01C */ |
| __IO uint32_t HDR_OPIPE_CSC_H12; /**< HDR OUPUT pipe Colorspace Converter (CSCO) h(1,2) matrix coefficient, offset: 0xF020 */ |
| __IO uint32_t HDR_; /**< HDR OUPUT pipe Colorspace Converter (CSCO) h(2,2) matrix coefficient, offset: 0xF024 */ |
| __IO uint32_t HDR_OPIPE_CSC_IO_0; /**< HDR OUTPUT pipe Colorspace Converter (CSCO) component 0 pre-offset, offset: 0xF028 */ |
| __IO uint32_t HDR_OPIPE_CSC_IO_1; /**< HDR OUPTUT pipe Colorspace Converter (CSCO) component 1 pre-offset, offset: 0xF02C */ |
| __IO uint32_t HDR_OPIPE_CSC_IO_2; /**< HDR OUPUT pipe: Colorspace Converter (CSCO) component 2 pre-offset, offset: 0xF030 */ |
| __IO uint32_t HDR_OPIPE_CSC_MIN_0; /**< HDR OUPTU pipe Colorspace Converter (CSCO) component 0 clip min., offset: 0xF034 */ |
| __IO uint32_t HDR_OPIPE_CSC_MIN_1; /**< HDR OUPUT pipe Colorspace Converter (CSCO) component 1 clip min., offset: 0xF038 */ |
| __IO uint32_t HDR_OPIPE_CSC_MIN_2; /**< HDR OUPTU pipe Colorspace Converter (CSCO) component 2 clip min., offset: 0xF03C */ |
| __IO uint32_t HDR_OPIPE_CSC_MAX_0; /**< HDR OUPTUT pipe Colorspace Converter O (CSC) component 0 clip max value., offset: 0xF040 */ |
| __IO uint32_t HDR_OPIPE_CSC_MAX_1; /**< HDR OUTPUT pipe Colorspace Converter (CSCO) component 1 clip max value., offset: 0xF044 */ |
| __IO uint32_t HDR_OPIPE_CSC_MAX_2; /**< HDR OUTPUT pipe Colorspace Converter (CSCO) component 2 clip max value., offset: 0xF048 */ |
| __IO uint32_t HDR_OPIPE_CSC_NORM; /**< HDR OUPUT pipe Colorspace Converter (CSCO) normalization factor, offset: 0xF04C */ |
| __IO uint32_t HDR_OPIPE_CSC_OO_0; /**< HDR OUPTUT pipe Colorspace Converter (CSC): Post offset component 0, offset: 0xF050 */ |
| __IO uint32_t HDR_OPIPE_CSC_OO_1; /**< HDR OUTPUT pipe Colorspace Converter (CSC): Post offset component 1, offset: 0xF054 */ |
| __IO uint32_t HDR_OPIPE_CSC_OO_2; /**< HDR OUPTUT pipe Colorspace Converter (CSC): Post offset component 2, offset: 0xF058 */ |
| __IO uint32_t HDR_OPIPE_CSC_OMIN_0; /**< HDR OUTPUT pipe Colorspace Converter (CSC): Post offset min clip value for component 0, offset: 0xF05C */ |
| __IO uint32_t HDR_OPIPE_CSC_OMIN_1; /**< HDR OUTPUT pipe Colorspace Converter (CSC): Post offset min clip value for component 1, offset: 0xF060 */ |
| __IO uint32_t HDR_OPIPE_CSC_OMIN_2; /**< HDR OUTPUT pipe Colorspace Converter (CSC): Post offset min clip value for component 2, offset: 0xF064 */ |
| __IO uint32_t HDR_OPIPE_CSC_OMAX_0; /**< HDR OUPTUT pipe Colorspace Converter (CSC): Post offset max clip value for component 0, offset: 0xF068 */ |
| __IO uint32_t HDR_OPIPE_CSC_OMAX_1; /**< HDR OUTPUT pipe Colorspace Converter (CSC): Post offset max clip value for component 1, offset: 0xF06C */ |
| __IO uint32_t HDR_OPIPE_CSC_OMAX_2; /**< HDR OUTPUT pipe Colorspace Converter (CSC): Post offset max clip value for component 2, offset: 0xF070 */ |
| uint8_t RESERVED_21[2048]; |
| __IO uint32_t HDR_OPIPE_2NL_CONTROL_REG; /**< HDR OUTPUT -TO NON LINEAR pipeline control, offset: 0xF874 */ |
| } MED_HDR10_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- MED_HDR10 Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MED_HDR10_Register_Masks MED_HDR10 Register Masks |
| * @{ |
| */ |
| |
| /*! @name PIPE1_A0_LUT - A0 component Look-Up-Table. (LUT) */ |
| /*! @{ */ |
| #define MED_HDR10_PIPE1_A0_LUT_PIPE1_A0_LUT_MASK (0x3FFFU) |
| #define MED_HDR10_PIPE1_A0_LUT_PIPE1_A0_LUT_SHIFT (0U) |
| #define MED_HDR10_PIPE1_A0_LUT_PIPE1_A0_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE1_A0_LUT_PIPE1_A0_LUT_SHIFT)) & MED_HDR10_PIPE1_A0_LUT_PIPE1_A0_LUT_MASK) |
| /*! @} */ |
| |
| /*! @name PIPE1_A1_LUT - A1 component Look-Up-Table. (LUT) */ |
| /*! @{ */ |
| #define MED_HDR10_PIPE1_A1_LUT_PIPE1_A1_LUT_MASK (0x3FFFU) |
| #define MED_HDR10_PIPE1_A1_LUT_PIPE1_A1_LUT_SHIFT (0U) |
| #define MED_HDR10_PIPE1_A1_LUT_PIPE1_A1_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE1_A1_LUT_PIPE1_A1_LUT_SHIFT)) & MED_HDR10_PIPE1_A1_LUT_PIPE1_A1_LUT_MASK) |
| /*! @} */ |
| |
| /*! @name PIPE1_A2_LUT - A2 component Look-Up-Table. (LUT) */ |
| /*! @{ */ |
| #define MED_HDR10_PIPE1_A2_LUT_PIPE1_A2_LUT_MASK (0x3FFFU) |
| #define MED_HDR10_PIPE1_A2_LUT_PIPE1_A2_LUT_SHIFT (0U) |
| #define MED_HDR10_PIPE1_A2_LUT_PIPE1_A2_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE1_A2_LUT_PIPE1_A2_LUT_SHIFT)) & MED_HDR10_PIPE1_A2_LUT_PIPE1_A2_LUT_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_CONTROL_REG - Pipe1 Colorspace Converter A control. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_MASK (0x1U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_MASK) |
| #define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK) |
| #define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_BYPASS_MASK (0x8000U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_BYPASS_SHIFT (15U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_CONTROL_REG_BYPASS_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_H00 - Pipe1 Colorspace Converter A (CSCA) h(0,0) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_H00_H00_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_H00_H00_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_H00_H00(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H00_H00_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H00_H00_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_H10 - Pipe1 Colorspace Converter A (CSCA) h(1,0) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_H10_H10_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_H10_H10_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_H10_H10(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H10_H10_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H10_H10_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_H20 - Pipe1 Colorspace Converter A (CSCA) h(2,0) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_H20_H20_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_H20_H20_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_H20_H20(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H20_H20_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H20_H20_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_H01 - Pipe1 Colorspace Converter A (CSCA) h(0,1) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_H01_H01_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_H01_H01_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_H01_H01(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H01_H01_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H01_H01_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_H11 - Pipe1 Colorspace Converter A (CSCA) h(1,1) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_H11_H11_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_H11_H11_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_H11_H11(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H11_H11_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H11_H11_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_H21 - Pipe1 Colorspace Converter A (CSCA) h(2,1) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_H21_H21_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_H21_H21_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_H21_H21(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H21_H21_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H21_H21_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_H02 - Pipe1 Colorspace Converter A (CSCA) h(0,2) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_H02_H02_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_H02_H02_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_H02_H02(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H02_H02_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H02_H02_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_H12 - Pipe1 Colorspace Converter A (CSCA) h(1,2) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_H12_H12_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_H12_H12_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_H12_H12(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H12_H12_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H12_H12_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_H22 - Pipe1 Colorspace Converter A (CSCA) h(2,2) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_H22_H22_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_H22_H22_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_H22_H22(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_H22_H22_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_H22_H22_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_IO_0 - Pipe1 Colorspace Converter A (CSCA) component 0 pre-offset */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_0_COMPO_PRE_OFFSET_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_0_COMPO_PRE_OFFSET_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_0_COMPO_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_0_COMPO_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_0_COMPO_PRE_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_IO_1 - Pipe1 Colorspace Converter A (CSCA) component 1 pre-offset */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_1_COMP1_PRE_OFFSET_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_1_COMP1_PRE_OFFSET_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_1_COMP1_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_1_COMP1_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_1_COMP1_PRE_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_IO_2 - Pipe1 Colorspace Converter A (CSCA) component 2 pre-offset */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_2_COMP2_PRE_OFFSET_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_2_COMP2_PRE_OFFSET_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_2_COMP2_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_2_COMP2_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_2_COMP2_PRE_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_IO_MIN_0 - Pipe1 Colorspace Converter A (CSCA) component 0 clip min. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_0_COMP0_CLIP_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_0_COMP0_CLIP_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_0_COMP0_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_0_COMP0_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_0_COMP0_CLIP_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_IO_MIN_1 - Pipe1 Colorspace Converter A (CSCA) component 1 clip min. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_1_COMP1_CLIP_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_1_COMP1_CLIP_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_1_COMP1_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_1_COMP1_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_1_COMP1_CLIP_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_IO_MIN_2 - Pipe1 Colorspace Converter A (CSCA) component 2 clip min. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_2_COMP2_CLIP_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_2_COMP2_CLIP_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_2_COMP2_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_2_COMP2_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_MIN_2_COMP2_CLIP_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_IO_MAX_0 - Pipe1 Colorspace Converter A (CSCA) component 0 clip max value. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_0_COMP0_CLIP_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_0_COMP0_CLIP_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_0_COMP0_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_0_COMP0_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_0_COMP0_CLIP_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_IO_MAX_1 - Pipe1 Colorspace Converter A (CSCA) component 1 clip max value. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_1_COMP1_CLIP_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_1_COMP1_CLIP_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_1_COMP1_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_1_COMP1_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_1_COMP1_CLIP_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_IO_MAX_2 - Pipe1 Colorspace Converter A (CSCA) component 2 clip max value. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_2_COMP2_CLIP_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_2_COMP2_CLIP_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_2_COMP2_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_2_COMP2_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_IO_MAX_2_COMP2_CLIP_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_NORM - Pipe1 Colorspace Converter A (CSCA) normalization factor */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_NORM_CSCA_NORM_MASK (0x1FU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_NORM_CSCA_NORM_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_NORM_CSCA_NORM(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_NORM_CSCA_NORM_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_NORM_CSCA_NORM_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_OO_0 - Pipe1 Colorspace Converter A (CSCA): Post offset component 0 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_OO_0_CSCA_OO_0_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_OO_0_CSCA_OO_0_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_OO_0_CSCA_OO_0(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OO_0_CSCA_OO_0_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OO_0_CSCA_OO_0_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_OO_1 - Pipe1 Colorspace Converter A (CSCA): Post offset component 1 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_OO_1_CSCA_OO_1_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_OO_1_CSCA_OO_1_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_OO_1_CSCA_OO_1(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OO_1_CSCA_OO_1_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OO_1_CSCA_OO_1_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_OO_2 - Pipe1 Colorspace Converter A (CSCA): Post offset component 2 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_OO_2_CSCA_OO_2_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_OO_2_CSCA_OO_2_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_OO_2_CSCA_OO_2(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OO_2_CSCA_OO_2_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OO_2_CSCA_OO_2_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_OMIN_0 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 0 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_OMIN_0_POST_OFF_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_OMIN_0_POST_OFF_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_OMIN_0_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OMIN_0_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OMIN_0_POST_OFF_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_OMIN_1 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 1 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_OMIN_1_POST_OFF_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_OMIN_1_POST_OFF_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_OMIN_1_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OMIN_1_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OMIN_1_POST_OFF_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_OMIN_2 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 2 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_OMIN_2_POST_OFF_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_OMIN_2_POST_OFF_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_OMIN_2_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OMIN_2_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OMIN_2_POST_OFF_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_OMAX_0 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 0 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_OMAX_0_POST_OFF_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_OMAX_0_POST_OFF_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_OMAX_0_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OMAX_0_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OMAX_0_POST_OFF_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_OMAX_1 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 1 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_OMAX_1_POST_OFF_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_OMAX_1_POST_OFF_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_OMAX_1_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OMAX_1_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OMAX_1_POST_OFF_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCA_OMAX_2 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 2 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCA_OMAX_2_POST_OFF_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE1_CSCA_OMAX_2_POST_OFF_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCA_OMAX_2_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCA_OMAX_2_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCA_OMAX_2_POST_OFF_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_LUT_CONTROL_REG - Pipe1 LUT control register */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_MASK (0x1U) |
| #define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_MASK) |
| #define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U) |
| #define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U) |
| #define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK) |
| #define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_BYPASS_MASK (0x8000U) |
| #define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_BYPASS_SHIFT (15U) |
| #define MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE1_LUT_CONTROL_REG_BYPASS_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_CONTROL_REG - Pipe1 Colorspace Converter B control. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_MASK (0x1U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_MASK) |
| #define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK) |
| #define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_BYPASS_MASK (0x8000U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_BYPASS_SHIFT (15U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_CONTROL_REG_BYPASS_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_H00 - Pipe1 Colorspace Converter A (CSCB) h(0,0) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_H00_H00_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_H00_H00_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_H00_H00(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H00_H00_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H00_H00_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_H10 - Pipe1 Colorspace Converter B (CSCB) h(1,0) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_H10_H10_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_H10_H10_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_H10_H10(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H10_H10_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H10_H10_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_H20 - Pipe1 Colorspace Converter B (CSCB) h(2,0) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_H20_H20_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_H20_H20_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_H20_H20(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H20_H20_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H20_H20_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_H01 - Pipe1 Colorspace Converter B (CSCB) h(0,1) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_H01_H01_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_H01_H01_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_H01_H01(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H01_H01_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H01_H01_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_H11 - Pipe1 Colorspace Converter B (CSCB) h(1,1) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_H11_H11_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_H11_H11_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_H11_H11(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H11_H11_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H11_H11_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_H21 - Pipe1 Colorspace Converter B (CSCB) h(2,1) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_H21_H21_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_H21_H21_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_H21_H21(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H21_H21_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H21_H21_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_H02 - Pipe1 Colorspace Converter B (CSCB) h(0,2) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_H02_H02_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_H02_H02_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_H02_H02(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H02_H02_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H02_H02_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_H12 - Pipe1 Colorspace Converter B (CSCB) h(1,2) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_H12_H12_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_H12_H12_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_H12_H12(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H12_H12_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H12_H12_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_H22 - Pipe1 Colorspace Converter B (CSCB) h(2,2) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_H22_H22_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_H22_H22_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_H22_H22(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_H22_H22_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_H22_H22_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_IO_0 - Pipe1 Colorspace Converter B (CSCB) component 0 pre-offset */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_0_COMPO_PRE_OFFSET_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_0_COMPO_PRE_OFFSET_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_0_COMPO_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_0_COMPO_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_0_COMPO_PRE_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_IO_1 - Pipe1 Colorspace Converter B (CSCB) component 1 pre-offset */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_1_COMP1_PRE_OFFSET_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_1_COMP1_PRE_OFFSET_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_1_COMP1_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_1_COMP1_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_1_COMP1_PRE_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_IO_2 - Pipe1 Colorspace Converter B (CSCB) component 2 pre-offset */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_2_COMP2_PRE_OFFSET_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_2_COMP2_PRE_OFFSET_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_2_COMP2_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_2_COMP2_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_2_COMP2_PRE_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_IO_MIN_0 - Pipe1 Colorspace Converter B (CSCB) component 0 clip min. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_0_COMP0_CLIP_MIN_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_0_COMP0_CLIP_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_0_COMP0_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_0_COMP0_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_0_COMP0_CLIP_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_IO_MIN_1 - Pipe1 Colorspace Converter B (CSCB) component 1 clip min. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_1_COMP1_CLIP_MIN_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_1_COMP1_CLIP_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_1_COMP1_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_1_COMP1_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_1_COMP1_CLIP_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_IO_MIN_2 - Pipe1 Colorspace Converter B (CSCB) component 2 clip min. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_2_COMP2_CLIP_MIN_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_2_COMP2_CLIP_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_2_COMP2_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_2_COMP2_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_MIN_2_COMP2_CLIP_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_IO_MAX_0 - Pipe1 Colorspace Converter B (CSCB) component 0 clip max value. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_0_COMP0_CLIP_MAX_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_0_COMP0_CLIP_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_0_COMP0_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_0_COMP0_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_0_COMP0_CLIP_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_IO_MAX_1 - Pipe1 Colorspace Converter B (CSCB) component 1 clip max value. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_1_COMP1_CLIP_MAX_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_1_COMP1_CLIP_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_1_COMP1_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_1_COMP1_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_1_COMP1_CLIP_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_IO_MAX_2 - Pipe1 Colorspace Converter B (CSCB) component 2 clip max value. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_2_COMP2_CLIP_MAX_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_2_COMP2_CLIP_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_2_COMP2_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_2_COMP2_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_IO_MAX_2_COMP2_CLIP_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_NORM - Pipe1 Colorspace Converter B (CSCB) normalization factor */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_NORM_CSCB_NORM_MASK (0x1FU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_NORM_CSCB_NORM_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_NORM_CSCB_NORM(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_NORM_CSCB_NORM_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_NORM_CSCB_NORM_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_OO_0 - Pipe1 Colorspace Converter B (CSCB): Post offset component 0 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_OO_0_CSCB_OO_0_MASK (0x1FFFFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_OO_0_CSCB_OO_0_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_OO_0_CSCB_OO_0(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OO_0_CSCB_OO_0_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OO_0_CSCB_OO_0_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_OO_1 - Pipe1 Colorspace Converter B (CSCB): Post offset component 1 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_OO_1_CSCB_OO_1_MASK (0x1FFFFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_OO_1_CSCB_OO_1_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_OO_1_CSCB_OO_1(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OO_1_CSCB_OO_1_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OO_1_CSCB_OO_1_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_OO_2 - Pipe1 Colorspace Converter B (CSCB): Post offset component 2 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_OO_2_CSCB_OO_2_MASK (0x1FFFFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_OO_2_CSCB_OO_2_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_OO_2_CSCB_OO_2(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OO_2_CSCB_OO_2_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OO_2_CSCB_OO_2_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_OMIN_0 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 0 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_OMIN_0_POST_OFF_MIN_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_OMIN_0_POST_OFF_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_OMIN_0_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OMIN_0_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OMIN_0_POST_OFF_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_OMIN_1 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 1 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_OMIN_1_POST_OFF_MIN_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_OMIN_1_POST_OFF_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_OMIN_1_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OMIN_1_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OMIN_1_POST_OFF_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_OMIN_2 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 2 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_OMIN_2_POST_OFF_MIN_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_OMIN_2_POST_OFF_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_OMIN_2_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OMIN_2_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OMIN_2_POST_OFF_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_OMAX_0 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 0 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_OMAX_0_POST_OFF_MAX_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_OMAX_0_POST_OFF_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_OMAX_0_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OMAX_0_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OMAX_0_POST_OFF_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_OMAX_1 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 1 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_OMAX_1_POST_OFF_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_OMAX_1_POST_OFF_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_OMAX_1_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OMAX_1_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OMAX_1_POST_OFF_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_CSCB_OMAX_2 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 2 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_CSCB_OMAX_2_POST_OFF_MAX_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE1_CSCB_OMAX_2_POST_OFF_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_CSCB_OMAX_2_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_CSCB_OMAX_2_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE1_CSCB_OMAX_2_POST_OFF_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE1_FL2FX - Pipe1 floating point to fixed point control */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_MASK (0x1U) |
| #define MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE1_FL2FX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_MASK) |
| #define MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_FOR_ALL_PELS_MASK (0x2U) |
| #define MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_FOR_ALL_PELS_SHIFT (1U) |
| #define MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE1_FL2FX_ENABLE_FOR_ALL_PELS_MASK) |
| /*! @} */ |
| |
| /*! @name PIPE2_A0_LUT - A0 component Look-Up-Table. (LUT) */ |
| /*! @{ */ |
| #define MED_HDR10_PIPE2_A0_LUT_PIPE2_A0_LUT_MASK (0x3FFFU) |
| #define MED_HDR10_PIPE2_A0_LUT_PIPE2_A0_LUT_SHIFT (0U) |
| #define MED_HDR10_PIPE2_A0_LUT_PIPE2_A0_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE2_A0_LUT_PIPE2_A0_LUT_SHIFT)) & MED_HDR10_PIPE2_A0_LUT_PIPE2_A0_LUT_MASK) |
| /*! @} */ |
| |
| /*! @name PIPE2_A1_LUT - A1 component Look-Up-Table. (LUT) */ |
| /*! @{ */ |
| #define MED_HDR10_PIPE2_A1_LUT_PIPE2_A1_LUT_MASK (0x3FFFU) |
| #define MED_HDR10_PIPE2_A1_LUT_PIPE2_A1_LUT_SHIFT (0U) |
| #define MED_HDR10_PIPE2_A1_LUT_PIPE2_A1_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE2_A1_LUT_PIPE2_A1_LUT_SHIFT)) & MED_HDR10_PIPE2_A1_LUT_PIPE2_A1_LUT_MASK) |
| /*! @} */ |
| |
| /*! @name PIPE2_A2_LUT - A2 component Look-Up-Table. (LUT) */ |
| /*! @{ */ |
| #define MED_HDR10_PIPE2_A2_LUT_PIPE2_A2_LUT_MASK (0x3FFFU) |
| #define MED_HDR10_PIPE2_A2_LUT_PIPE2_A2_LUT_SHIFT (0U) |
| #define MED_HDR10_PIPE2_A2_LUT_PIPE2_A2_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE2_A2_LUT_PIPE2_A2_LUT_SHIFT)) & MED_HDR10_PIPE2_A2_LUT_PIPE2_A2_LUT_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_CONTROL_REG - Pipe1 Colorspace Converter A control. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_MASK (0x1U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_MASK) |
| #define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK) |
| #define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_BYPASS_MASK (0x8000U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_BYPASS_SHIFT (15U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_CONTROL_REG_BYPASS_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_H00 - Pipe1 Colorspace Converter A (CSCA) h(0,0) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_H00_H00_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_H00_H00_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_H00_H00(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H00_H00_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H00_H00_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_H10 - Pipe1 Colorspace Converter A (CSCA) h(1,0) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_H10_H10_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_H10_H10_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_H10_H10(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H10_H10_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H10_H10_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_H20 - Pipe1 Colorspace Converter A (CSCA) h(2,0) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_H20_H20_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_H20_H20_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_H20_H20(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H20_H20_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H20_H20_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_H01 - Pipe1 Colorspace Converter A (CSCA) h(0,1) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_H01_H01_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_H01_H01_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_H01_H01(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H01_H01_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H01_H01_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_H11 - Pipe1 Colorspace Converter A (CSCA) h(1,1) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_H11_H11_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_H11_H11_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_H11_H11(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H11_H11_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H11_H11_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_H21 - Pipe1 Colorspace Converter A (CSCA) h(2,1) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_H21_H21_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_H21_H21_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_H21_H21(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H21_H21_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H21_H21_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_H02 - Pipe1 Colorspace Converter A (CSCA) h(0,2) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_H02_H02_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_H02_H02_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_H02_H02(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H02_H02_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H02_H02_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_H12 - Pipe1 Colorspace Converter A (CSCA) h(1,2) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_H12_H12_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_H12_H12_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_H12_H12(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H12_H12_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H12_H12_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_H22 - Pipe1 Colorspace Converter A (CSCA) h(2,2) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_H22_H22_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_H22_H22_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_H22_H22(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_H22_H22_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_H22_H22_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_IO_0 - Pipe1 Colorspace Converter A (CSCA) component 0 pre-offset */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_0_COMPO_PRE_OFFSET_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_0_COMPO_PRE_OFFSET_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_0_COMPO_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_0_COMPO_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_0_COMPO_PRE_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_IO_1 - Pipe1 Colorspace Converter A (CSCA) component 1 pre-offset */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_1_COMP1_PRE_OFFSET_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_1_COMP1_PRE_OFFSET_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_1_COMP1_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_1_COMP1_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_1_COMP1_PRE_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_IO_2 - Pipe1 Colorspace Converter A (CSCA) component 2 pre-offset */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_2_COMP2_PRE_OFFSET_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_2_COMP2_PRE_OFFSET_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_2_COMP2_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_2_COMP2_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_2_COMP2_PRE_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_IO_MIN_0 - Pipe1 Colorspace Converter A (CSCA) component 0 clip min. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_0_COMP0_CLIP_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_0_COMP0_CLIP_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_0_COMP0_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_0_COMP0_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_0_COMP0_CLIP_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_IO_MIN_1 - Pipe1 Colorspace Converter A (CSCA) component 1 clip min. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_1_COMP1_CLIP_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_1_COMP1_CLIP_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_1_COMP1_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_1_COMP1_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_1_COMP1_CLIP_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_IO_MIN_2 - Pipe1 Colorspace Converter A (CSCA) component 2 clip min. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_2_COMP2_CLIP_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_2_COMP2_CLIP_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_2_COMP2_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_2_COMP2_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_MIN_2_COMP2_CLIP_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_IO_MAX_0 - Pipe1 Colorspace Converter A (CSCA) component 0 clip max value. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_0_COMP0_CLIP_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_0_COMP0_CLIP_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_0_COMP0_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_0_COMP0_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_0_COMP0_CLIP_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_IO_MAX_1 - Pipe1 Colorspace Converter A (CSCA) component 1 clip max value. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_1_COMP1_CLIP_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_1_COMP1_CLIP_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_1_COMP1_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_1_COMP1_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_1_COMP1_CLIP_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_IO_MAX_2 - Pipe1 Colorspace Converter A (CSCA) component 2 clip max value. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_2_COMP2_CLIP_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_2_COMP2_CLIP_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_2_COMP2_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_2_COMP2_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_IO_MAX_2_COMP2_CLIP_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_NORM - Pipe1 Colorspace Converter A (CSCA) normalization factor */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_NORM_CSCA_NORM_MASK (0x1FU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_NORM_CSCA_NORM_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_NORM_CSCA_NORM(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_NORM_CSCA_NORM_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_NORM_CSCA_NORM_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_OO_0 - Pipe1 Colorspace Converter A (CSCA): Post offset component 0 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_OO_0_CSCA_OO_0_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_OO_0_CSCA_OO_0_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_OO_0_CSCA_OO_0(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OO_0_CSCA_OO_0_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OO_0_CSCA_OO_0_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_OO_1 - Pipe1 Colorspace Converter A (CSCA): Post offset component 1 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_OO_1_CSCA_OO_1_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_OO_1_CSCA_OO_1_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_OO_1_CSCA_OO_1(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OO_1_CSCA_OO_1_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OO_1_CSCA_OO_1_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_OO_2 - Pipe1 Colorspace Converter A (CSCA): Post offset component 2 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_OO_2_CSCA_OO_2_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_OO_2_CSCA_OO_2_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_OO_2_CSCA_OO_2(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OO_2_CSCA_OO_2_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OO_2_CSCA_OO_2_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_OMIN_0 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 0 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_OMIN_0_POST_OFF_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_OMIN_0_POST_OFF_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_OMIN_0_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OMIN_0_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OMIN_0_POST_OFF_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_OMIN_1 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 1 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_OMIN_1_POST_OFF_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_OMIN_1_POST_OFF_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_OMIN_1_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OMIN_1_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OMIN_1_POST_OFF_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_OMIN_2 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 2 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_OMIN_2_POST_OFF_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_OMIN_2_POST_OFF_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_OMIN_2_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OMIN_2_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OMIN_2_POST_OFF_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_OMAX_0 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 0 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_OMAX_0_POST_OFF_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_OMAX_0_POST_OFF_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_OMAX_0_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OMAX_0_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OMAX_0_POST_OFF_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_OMAX_1 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 1 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_OMAX_1_POST_OFF_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_OMAX_1_POST_OFF_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_OMAX_1_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OMAX_1_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OMAX_1_POST_OFF_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCA_OMAX_2 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 2 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCA_OMAX_2_POST_OFF_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE2_CSCA_OMAX_2_POST_OFF_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCA_OMAX_2_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCA_OMAX_2_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCA_OMAX_2_POST_OFF_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_LUT_CONTROL_REG - Pipe1 LUT control register */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_MASK (0x1U) |
| #define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_MASK) |
| #define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U) |
| #define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U) |
| #define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK) |
| #define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_BYPASS_MASK (0x8000U) |
| #define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_BYPASS_SHIFT (15U) |
| #define MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE2_LUT_CONTROL_REG_BYPASS_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_CONTROL_REG - Pipe1 Colorspace Converter B control. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_MASK (0x1U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_MASK) |
| #define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK) |
| #define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_BYPASS_MASK (0x8000U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_BYPASS_SHIFT (15U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_CONTROL_REG_BYPASS_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_H00 - Pipe1 Colorspace Converter A (CSCB) h(0,0) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_H00_H00_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_H00_H00_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_H00_H00(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H00_H00_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H00_H00_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_H10 - Pipe1 Colorspace Converter B (CSCB) h(1,0) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_H10_H10_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_H10_H10_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_H10_H10(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H10_H10_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H10_H10_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_H20 - Pipe1 Colorspace Converter B (CSCB) h(2,0) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_H20_H20_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_H20_H20_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_H20_H20(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H20_H20_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H20_H20_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_H01 - Pipe1 Colorspace Converter B (CSCB) h(0,1) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_H01_H01_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_H01_H01_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_H01_H01(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H01_H01_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H01_H01_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_H11 - Pipe1 Colorspace Converter B (CSCB) h(1,1) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_H11_H11_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_H11_H11_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_H11_H11(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H11_H11_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H11_H11_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_H21 - Pipe1 Colorspace Converter B (CSCB) h(2,1) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_H21_H21_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_H21_H21_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_H21_H21(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H21_H21_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H21_H21_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_H02 - Pipe1 Colorspace Converter B (CSCB) h(0,2) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_H02_H02_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_H02_H02_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_H02_H02(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H02_H02_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H02_H02_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_H12 - Pipe1 Colorspace Converter B (CSCB) h(1,2) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_H12_H12_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_H12_H12_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_H12_H12(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H12_H12_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H12_H12_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_H22 - Pipe1 Colorspace Converter B (CSCB) h(2,2) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_H22_H22_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_H22_H22_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_H22_H22(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_H22_H22_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_H22_H22_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_IO_0 - Pipe1 Colorspace Converter B (CSCB) component 0 pre-offset */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_0_COMPO_PRE_OFFSET_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_0_COMPO_PRE_OFFSET_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_0_COMPO_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_0_COMPO_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_0_COMPO_PRE_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_IO_1 - Pipe1 Colorspace Converter B (CSCB) component 1 pre-offset */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_1_COMP1_PRE_OFFSET_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_1_COMP1_PRE_OFFSET_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_1_COMP1_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_1_COMP1_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_1_COMP1_PRE_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_IO_2 - Pipe1 Colorspace Converter B (CSCB) component 2 pre-offset */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_2_COMP2_PRE_OFFSET_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_2_COMP2_PRE_OFFSET_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_2_COMP2_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_2_COMP2_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_2_COMP2_PRE_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_IO_MIN_0 - Pipe1 Colorspace Converter B (CSCB) component 0 clip min. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_0_COMP0_CLIP_MIN_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_0_COMP0_CLIP_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_0_COMP0_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_0_COMP0_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_0_COMP0_CLIP_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_IO_MIN_1 - Pipe1 Colorspace Converter B (CSCB) component 1 clip min. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_1_COMP1_CLIP_MIN_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_1_COMP1_CLIP_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_1_COMP1_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_1_COMP1_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_1_COMP1_CLIP_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_IO_MIN_2 - Pipe1 Colorspace Converter B (CSCB) component 2 clip min. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_2_COMP2_CLIP_MIN_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_2_COMP2_CLIP_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_2_COMP2_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_2_COMP2_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_MIN_2_COMP2_CLIP_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_IO_MAX_0 - Pipe1 Colorspace Converter B (CSCB) component 0 clip max value. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_0_COMP0_CLIP_MAX_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_0_COMP0_CLIP_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_0_COMP0_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_0_COMP0_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_0_COMP0_CLIP_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_IO_MAX_1 - Pipe1 Colorspace Converter B (CSCB) component 1 clip max value. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_1_COMP1_CLIP_MAX_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_1_COMP1_CLIP_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_1_COMP1_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_1_COMP1_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_1_COMP1_CLIP_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_IO_MAX_2 - Pipe1 Colorspace Converter B (CSCB) component 2 clip max value. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_2_COMP2_CLIP_MAX_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_2_COMP2_CLIP_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_2_COMP2_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_2_COMP2_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_IO_MAX_2_COMP2_CLIP_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_NORM - Pipe1 Colorspace Converter B (CSCB) normalization factor */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_NORM_CSCB_NORM_MASK (0x1FU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_NORM_CSCB_NORM_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_NORM_CSCB_NORM(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_NORM_CSCB_NORM_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_NORM_CSCB_NORM_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_OO_0 - Pipe1 Colorspace Converter B (CSCB): Post offset component 0 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_OO_0_CSCB_OO_0_MASK (0x1FFFFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_OO_0_CSCB_OO_0_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_OO_0_CSCB_OO_0(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OO_0_CSCB_OO_0_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OO_0_CSCB_OO_0_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_OO_1 - Pipe1 Colorspace Converter B (CSCB): Post offset component 1 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_OO_1_CSCB_OO_1_MASK (0x1FFFFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_OO_1_CSCB_OO_1_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_OO_1_CSCB_OO_1(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OO_1_CSCB_OO_1_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OO_1_CSCB_OO_1_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_OO_2 - Pipe1 Colorspace Converter B (CSCB): Post offset component 2 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_OO_2_CSCB_OO_2_MASK (0x1FFFFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_OO_2_CSCB_OO_2_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_OO_2_CSCB_OO_2(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OO_2_CSCB_OO_2_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OO_2_CSCB_OO_2_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_OMIN_0 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 0 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_OMIN_0_POST_OFF_MIN_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_OMIN_0_POST_OFF_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_OMIN_0_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OMIN_0_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OMIN_0_POST_OFF_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_OMIN_1 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 1 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_OMIN_1_POST_OFF_MIN_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_OMIN_1_POST_OFF_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_OMIN_1_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OMIN_1_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OMIN_1_POST_OFF_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_OMIN_2 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 2 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_OMIN_2_POST_OFF_MIN_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_OMIN_2_POST_OFF_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_OMIN_2_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OMIN_2_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OMIN_2_POST_OFF_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_OMAX_0 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 0 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_OMAX_0_POST_OFF_MAX_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_OMAX_0_POST_OFF_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_OMAX_0_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OMAX_0_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OMAX_0_POST_OFF_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_OMAX_1 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 1 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_OMAX_1_POST_OFF_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_OMAX_1_POST_OFF_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_OMAX_1_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OMAX_1_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OMAX_1_POST_OFF_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_CSCB_OMAX_2 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 2 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_CSCB_OMAX_2_POST_OFF_MAX_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE2_CSCB_OMAX_2_POST_OFF_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_CSCB_OMAX_2_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_CSCB_OMAX_2_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE2_CSCB_OMAX_2_POST_OFF_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE2_FL2FX - Pipe1 floating point to fixed point control */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_MASK (0x1U) |
| #define MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE2_FL2FX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_MASK) |
| #define MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_FOR_ALL_PELS_MASK (0x2U) |
| #define MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_FOR_ALL_PELS_SHIFT (1U) |
| #define MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE2_FL2FX_ENABLE_FOR_ALL_PELS_MASK) |
| /*! @} */ |
| |
| /*! @name PIPE3_A0_LUT - A0 component Look-Up-Table. (LUT) */ |
| /*! @{ */ |
| #define MED_HDR10_PIPE3_A0_LUT_PIPE3_A0_LUT_MASK (0x3FFFU) |
| #define MED_HDR10_PIPE3_A0_LUT_PIPE3_A0_LUT_SHIFT (0U) |
| #define MED_HDR10_PIPE3_A0_LUT_PIPE3_A0_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE3_A0_LUT_PIPE3_A0_LUT_SHIFT)) & MED_HDR10_PIPE3_A0_LUT_PIPE3_A0_LUT_MASK) |
| /*! @} */ |
| |
| /*! @name PIPE3_A1_LUT - A1 component Look-Up-Table. (LUT) */ |
| /*! @{ */ |
| #define MED_HDR10_PIPE3_A1_LUT_PIPE3_A1_LUT_MASK (0x3FFFU) |
| #define MED_HDR10_PIPE3_A1_LUT_PIPE3_A1_LUT_SHIFT (0U) |
| #define MED_HDR10_PIPE3_A1_LUT_PIPE3_A1_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE3_A1_LUT_PIPE3_A1_LUT_SHIFT)) & MED_HDR10_PIPE3_A1_LUT_PIPE3_A1_LUT_MASK) |
| /*! @} */ |
| |
| /*! @name PIPE3_A2_LUT - A2 component Look-Up-Table. (LUT) */ |
| /*! @{ */ |
| #define MED_HDR10_PIPE3_A2_LUT_PIPE3_A2_LUT_MASK (0x3FFFU) |
| #define MED_HDR10_PIPE3_A2_LUT_PIPE3_A2_LUT_SHIFT (0U) |
| #define MED_HDR10_PIPE3_A2_LUT_PIPE3_A2_LUT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_PIPE3_A2_LUT_PIPE3_A2_LUT_SHIFT)) & MED_HDR10_PIPE3_A2_LUT_PIPE3_A2_LUT_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_CONTROL_REG - Pipe1 Colorspace Converter A control. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_MASK (0x1U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_MASK) |
| #define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK) |
| #define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_BYPASS_MASK (0x8000U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_BYPASS_SHIFT (15U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_CONTROL_REG_BYPASS_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_H00 - Pipe1 Colorspace Converter A (CSCA) h(0,0) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_H00_H00_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_H00_H00_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_H00_H00(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H00_H00_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H00_H00_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_H10 - Pipe1 Colorspace Converter A (CSCA) h(1,0) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_H10_H10_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_H10_H10_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_H10_H10(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H10_H10_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H10_H10_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_H20 - Pipe1 Colorspace Converter A (CSCA) h(2,0) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_H20_H20_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_H20_H20_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_H20_H20(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H20_H20_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H20_H20_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_H01 - Pipe1 Colorspace Converter A (CSCA) h(0,1) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_H01_H01_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_H01_H01_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_H01_H01(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H01_H01_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H01_H01_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_H11 - Pipe1 Colorspace Converter A (CSCA) h(1,1) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_H11_H11_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_H11_H11_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_H11_H11(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H11_H11_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H11_H11_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_H21 - Pipe1 Colorspace Converter A (CSCA) h(2,1) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_H21_H21_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_H21_H21_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_H21_H21(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H21_H21_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H21_H21_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_H02 - Pipe1 Colorspace Converter A (CSCA) h(0,2) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_H02_H02_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_H02_H02_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_H02_H02(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H02_H02_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H02_H02_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_H12 - Pipe1 Colorspace Converter A (CSCA) h(1,2) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_H12_H12_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_H12_H12_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_H12_H12(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H12_H12_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H12_H12_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_H22 - Pipe1 Colorspace Converter A (CSCA) h(2,2) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_H22_H22_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_H22_H22_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_H22_H22(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_H22_H22_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_H22_H22_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_IO_0 - Pipe1 Colorspace Converter A (CSCA) component 0 pre-offset */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_0_COMPO_PRE_OFFSET_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_0_COMPO_PRE_OFFSET_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_0_COMPO_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_0_COMPO_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_0_COMPO_PRE_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_IO_1 - Pipe1 Colorspace Converter A (CSCA) component 1 pre-offset */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_1_COMP1_PRE_OFFSET_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_1_COMP1_PRE_OFFSET_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_1_COMP1_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_1_COMP1_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_1_COMP1_PRE_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_IO_2 - Pipe1 Colorspace Converter A (CSCA) component 2 pre-offset */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_2_COMP2_PRE_OFFSET_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_2_COMP2_PRE_OFFSET_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_2_COMP2_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_2_COMP2_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_2_COMP2_PRE_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_IO_MIN_0 - Pipe1 Colorspace Converter A (CSCA) component 0 clip min. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_0_COMP0_CLIP_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_0_COMP0_CLIP_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_0_COMP0_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_0_COMP0_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_0_COMP0_CLIP_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_IO_MIN_1 - Pipe1 Colorspace Converter A (CSCA) component 1 clip min. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_1_COMP1_CLIP_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_1_COMP1_CLIP_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_1_COMP1_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_1_COMP1_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_1_COMP1_CLIP_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_IO_MIN_2 - Pipe1 Colorspace Converter A (CSCA) component 2 clip min. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_2_COMP2_CLIP_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_2_COMP2_CLIP_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_2_COMP2_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_2_COMP2_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_MIN_2_COMP2_CLIP_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_IO_MAX_0 - Pipe1 Colorspace Converter A (CSCA) component 0 clip max value. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_0_COMP0_CLIP_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_0_COMP0_CLIP_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_0_COMP0_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_0_COMP0_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_0_COMP0_CLIP_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_IO_MAX_1 - Pipe1 Colorspace Converter A (CSCA) component 1 clip max value. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_1_COMP1_CLIP_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_1_COMP1_CLIP_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_1_COMP1_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_1_COMP1_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_1_COMP1_CLIP_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_IO_MAX_2 - Pipe1 Colorspace Converter A (CSCA) component 2 clip max value. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_2_COMP2_CLIP_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_2_COMP2_CLIP_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_2_COMP2_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_2_COMP2_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_IO_MAX_2_COMP2_CLIP_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_NORM - Pipe1 Colorspace Converter A (CSCA) normalization factor */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_NORM_CSCA_NORM_MASK (0x1FU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_NORM_CSCA_NORM_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_NORM_CSCA_NORM(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_NORM_CSCA_NORM_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_NORM_CSCA_NORM_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_OO_0 - Pipe1 Colorspace Converter A (CSCA): Post offset component 0 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_OO_0_CSCA_OO_0_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_OO_0_CSCA_OO_0_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_OO_0_CSCA_OO_0(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OO_0_CSCA_OO_0_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OO_0_CSCA_OO_0_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_OO_1 - Pipe1 Colorspace Converter A (CSCA): Post offset component 1 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_OO_1_CSCA_OO_1_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_OO_1_CSCA_OO_1_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_OO_1_CSCA_OO_1(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OO_1_CSCA_OO_1_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OO_1_CSCA_OO_1_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_OO_2 - Pipe1 Colorspace Converter A (CSCA): Post offset component 2 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_OO_2_CSCA_OO_2_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_OO_2_CSCA_OO_2_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_OO_2_CSCA_OO_2(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OO_2_CSCA_OO_2_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OO_2_CSCA_OO_2_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_OMIN_0 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 0 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_OMIN_0_POST_OFF_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_OMIN_0_POST_OFF_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_OMIN_0_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OMIN_0_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OMIN_0_POST_OFF_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_OMIN_1 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 1 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_OMIN_1_POST_OFF_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_OMIN_1_POST_OFF_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_OMIN_1_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OMIN_1_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OMIN_1_POST_OFF_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_OMIN_2 - Pipe1 Colorspace Converter A (CSCA): Post offset min clip value for component 2 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_OMIN_2_POST_OFF_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_OMIN_2_POST_OFF_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_OMIN_2_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OMIN_2_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OMIN_2_POST_OFF_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_OMAX_0 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 0 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_OMAX_0_POST_OFF_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_OMAX_0_POST_OFF_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_OMAX_0_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OMAX_0_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OMAX_0_POST_OFF_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_OMAX_1 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 1 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_OMAX_1_POST_OFF_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_OMAX_1_POST_OFF_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_OMAX_1_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OMAX_1_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OMAX_1_POST_OFF_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCA_OMAX_2 - Pipe1 Colorspace Converter A (CSCA): Post offset max clip value for component 2 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCA_OMAX_2_POST_OFF_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE3_CSCA_OMAX_2_POST_OFF_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCA_OMAX_2_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCA_OMAX_2_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCA_OMAX_2_POST_OFF_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_LUT_CONTROL_REG - Pipe1 LUT control register */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_MASK (0x1U) |
| #define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_MASK) |
| #define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U) |
| #define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U) |
| #define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK) |
| #define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_BYPASS_MASK (0x8000U) |
| #define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_BYPASS_SHIFT (15U) |
| #define MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE3_LUT_CONTROL_REG_BYPASS_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_CONTROL_REG - Pipe1 Colorspace Converter B control. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_MASK (0x1U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_MASK) |
| #define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK) |
| #define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_BYPASS_MASK (0x8000U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_BYPASS_SHIFT (15U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_CONTROL_REG_BYPASS_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_H00 - Pipe1 Colorspace Converter A (CSCB) h(0,0) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_H00_H00_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_H00_H00_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_H00_H00(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H00_H00_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H00_H00_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_H10 - Pipe1 Colorspace Converter B (CSCB) h(1,0) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_H10_H10_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_H10_H10_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_H10_H10(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H10_H10_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H10_H10_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_H20 - Pipe1 Colorspace Converter B (CSCB) h(2,0) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_H20_H20_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_H20_H20_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_H20_H20(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H20_H20_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H20_H20_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_H01 - Pipe1 Colorspace Converter B (CSCB) h(0,1) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_H01_H01_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_H01_H01_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_H01_H01(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H01_H01_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H01_H01_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_H11 - Pipe1 Colorspace Converter B (CSCB) h(1,1) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_H11_H11_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_H11_H11_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_H11_H11(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H11_H11_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H11_H11_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_H21 - Pipe1 Colorspace Converter B (CSCB) h(2,1) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_H21_H21_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_H21_H21_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_H21_H21(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H21_H21_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H21_H21_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_H02 - Pipe1 Colorspace Converter B (CSCB) h(0,2) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_H02_H02_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_H02_H02_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_H02_H02(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H02_H02_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H02_H02_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_H12 - Pipe1 Colorspace Converter B (CSCB) h(1,2) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_H12_H12_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_H12_H12_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_H12_H12(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H12_H12_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H12_H12_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_H22 - Pipe1 Colorspace Converter B (CSCB) h(2,2) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_H22_H22_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_H22_H22_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_H22_H22(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_H22_H22_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_H22_H22_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_IO_0 - Pipe1 Colorspace Converter B (CSCB) component 0 pre-offset */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_0_COMPO_PRE_OFFSET_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_0_COMPO_PRE_OFFSET_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_0_COMPO_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_0_COMPO_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_0_COMPO_PRE_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_IO_1 - Pipe1 Colorspace Converter B (CSCB) component 1 pre-offset */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_1_COMP1_PRE_OFFSET_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_1_COMP1_PRE_OFFSET_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_1_COMP1_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_1_COMP1_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_1_COMP1_PRE_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_IO_2 - Pipe1 Colorspace Converter B (CSCB) component 2 pre-offset */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_2_COMP2_PRE_OFFSET_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_2_COMP2_PRE_OFFSET_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_2_COMP2_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_2_COMP2_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_2_COMP2_PRE_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_IO_MIN_0 - Pipe1 Colorspace Converter B (CSCB) component 0 clip min. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_0_COMP0_CLIP_MIN_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_0_COMP0_CLIP_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_0_COMP0_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_0_COMP0_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_0_COMP0_CLIP_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_IO_MIN_1 - Pipe1 Colorspace Converter B (CSCB) component 1 clip min. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_1_COMP1_CLIP_MIN_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_1_COMP1_CLIP_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_1_COMP1_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_1_COMP1_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_1_COMP1_CLIP_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_IO_MIN_2 - Pipe1 Colorspace Converter B (CSCB) component 2 clip min. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_2_COMP2_CLIP_MIN_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_2_COMP2_CLIP_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_2_COMP2_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_2_COMP2_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_MIN_2_COMP2_CLIP_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_IO_MAX_0 - Pipe1 Colorspace Converter B (CSCB) component 0 clip max value. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_0_COMP0_CLIP_MAX_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_0_COMP0_CLIP_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_0_COMP0_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_0_COMP0_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_0_COMP0_CLIP_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_IO_MAX_1 - Pipe1 Colorspace Converter B (CSCB) component 1 clip max value. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_1_COMP1_CLIP_MAX_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_1_COMP1_CLIP_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_1_COMP1_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_1_COMP1_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_1_COMP1_CLIP_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_IO_MAX_2 - Pipe1 Colorspace Converter B (CSCB) component 2 clip max value. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_2_COMP2_CLIP_MAX_MASK (0x3FFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_2_COMP2_CLIP_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_2_COMP2_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_2_COMP2_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_IO_MAX_2_COMP2_CLIP_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_NORM - Pipe1 Colorspace Converter B (CSCB) normalization factor */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_NORM_CSCB_NORM_MASK (0x1FU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_NORM_CSCB_NORM_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_NORM_CSCB_NORM(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_NORM_CSCB_NORM_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_NORM_CSCB_NORM_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_OO_0 - Pipe1 Colorspace Converter B (CSCB): Post offset component 0 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_OO_0_CSCB_OO_0_MASK (0x1FFFFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_OO_0_CSCB_OO_0_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_OO_0_CSCB_OO_0(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OO_0_CSCB_OO_0_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OO_0_CSCB_OO_0_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_OO_1 - Pipe1 Colorspace Converter B (CSCB): Post offset component 1 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_OO_1_CSCB_OO_1_MASK (0x1FFFFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_OO_1_CSCB_OO_1_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_OO_1_CSCB_OO_1(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OO_1_CSCB_OO_1_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OO_1_CSCB_OO_1_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_OO_2 - Pipe1 Colorspace Converter B (CSCB): Post offset component 2 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_OO_2_CSCB_OO_2_MASK (0x1FFFFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_OO_2_CSCB_OO_2_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_OO_2_CSCB_OO_2(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OO_2_CSCB_OO_2_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OO_2_CSCB_OO_2_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_OMIN_0 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 0 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_OMIN_0_POST_OFF_MIN_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_OMIN_0_POST_OFF_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_OMIN_0_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OMIN_0_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OMIN_0_POST_OFF_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_OMIN_1 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 1 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_OMIN_1_POST_OFF_MIN_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_OMIN_1_POST_OFF_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_OMIN_1_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OMIN_1_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OMIN_1_POST_OFF_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_OMIN_2 - Pipe1 Colorspace Converter B (CSCB): Post offset min clip value for component 2 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_OMIN_2_POST_OFF_MIN_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_OMIN_2_POST_OFF_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_OMIN_2_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OMIN_2_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OMIN_2_POST_OFF_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_OMAX_0 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 0 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_OMAX_0_POST_OFF_MAX_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_OMAX_0_POST_OFF_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_OMAX_0_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OMAX_0_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OMAX_0_POST_OFF_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_OMAX_1 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 1 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_OMAX_1_POST_OFF_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_OMAX_1_POST_OFF_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_OMAX_1_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OMAX_1_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OMAX_1_POST_OFF_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_CSCB_OMAX_2 - Pipe1 Colorspace Converter B (CSCB): Post offset max clip value for component 2 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_CSCB_OMAX_2_POST_OFF_MAX_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_PIPE3_CSCB_OMAX_2_POST_OFF_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_CSCB_OMAX_2_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_CSCB_OMAX_2_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_PIPE3_CSCB_OMAX_2_POST_OFF_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_PIPE3_FL2FX - Pipe1 floating point to fixed point control */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_MASK (0x1U) |
| #define MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_SHIFT (0U) |
| #define MED_HDR10_HDR_PIPE3_FL2FX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_SHIFT)) & MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_MASK) |
| #define MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_FOR_ALL_PELS_MASK (0x2U) |
| #define MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_FOR_ALL_PELS_SHIFT (1U) |
| #define MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_PIPE3_FL2FX_ENABLE_FOR_ALL_PELS_MASK) |
| /*! @} */ |
| |
| /*! @name OPIPE_A0_TABLE - A0 component Linear-to-Non-linear conversion table */ |
| /*! @{ */ |
| #define MED_HDR10_OPIPE_A0_TABLE_OPIPE_A0_TABLE_MASK (0x3FFFU) |
| #define MED_HDR10_OPIPE_A0_TABLE_OPIPE_A0_TABLE_SHIFT (0U) |
| #define MED_HDR10_OPIPE_A0_TABLE_OPIPE_A0_TABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_OPIPE_A0_TABLE_OPIPE_A0_TABLE_SHIFT)) & MED_HDR10_OPIPE_A0_TABLE_OPIPE_A0_TABLE_MASK) |
| /*! @} */ |
| |
| /*! @name OPIPE_A1_TABLE - A1 component Linear-to-Non-linear conversion table */ |
| /*! @{ */ |
| #define MED_HDR10_OPIPE_A1_TABLE_OPIPE_A1_TABLE_MASK (0x3FFFU) |
| #define MED_HDR10_OPIPE_A1_TABLE_OPIPE_A1_TABLE_SHIFT (0U) |
| #define MED_HDR10_OPIPE_A1_TABLE_OPIPE_A1_TABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_OPIPE_A1_TABLE_OPIPE_A1_TABLE_SHIFT)) & MED_HDR10_OPIPE_A1_TABLE_OPIPE_A1_TABLE_MASK) |
| /*! @} */ |
| |
| /*! @name OPIPE_A2_TABLE - A2 component Linear-to-Non-linear conversion table */ |
| /*! @{ */ |
| #define MED_HDR10_OPIPE_A2_TABLE_OPIPE_A2_TABLE_MASK (0x3FFFU) |
| #define MED_HDR10_OPIPE_A2_TABLE_OPIPE_A2_TABLE_SHIFT (0U) |
| #define MED_HDR10_OPIPE_A2_TABLE_OPIPE_A2_TABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_OPIPE_A2_TABLE_OPIPE_A2_TABLE_SHIFT)) & MED_HDR10_OPIPE_A2_TABLE_OPIPE_A2_TABLE_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_CONTROL_REG - HDR output stage Colorspace Converter (CSCO) control. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_MASK (0x1U) |
| #define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_MASK) |
| #define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK (0x2U) |
| #define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT (1U) |
| #define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_ENABLE_FOR_ALL_PELS_MASK) |
| #define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_BYPASS_MASK (0x8000U) |
| #define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_BYPASS_SHIFT (15U) |
| #define MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_BYPASS_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_CONTROL_REG_BYPASS_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_H00 - Pipe1 Colorspace Converter (CSC) h(0,0) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_H00_H00_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_H00_H00_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_H00_H00(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H00_H00_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H00_H00_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_H10 - Pipe1 Colorspace Converter (CSC) h(1,0) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_H10_H10_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_H10_H10_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_H10_H10(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H10_H10_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H10_H10_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_H20 - HDR OUTPUT Colorspace Converter (CSCO) h(2,0) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_H20_H20_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_H20_H20_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_H20_H20(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H20_H20_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H20_H20_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_H01 - HDR OUTPUT pipe Colorspace Converter (CSCO) h(0,1) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_H01_H01_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_H01_H01_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_H01_H01(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H01_H01_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H01_H01_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_H11 - HDR OUTPUT pipe Colorspace Converter (CSCO) h(1,1) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_H11_H11_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_H11_H11_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_H11_H11(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H11_H11_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H11_H11_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_H21 - HDR_output pipe Colorspace Converter (CSCO) h(2,1) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_H21_H21_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_H21_H21_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_H21_H21(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H21_H21_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H21_H21_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_H02 - HDR OUTPUT pipe Colorspace Converter (CSCO) h(0,2) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_H02_H02_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_H02_H02_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_H02_H02(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H02_H02_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H02_H02_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_H12 - HDR OUPUT pipe Colorspace Converter (CSCO) h(1,2) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_H12_H12_MASK (0xFFFFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_H12_H12_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_H12_H12(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_H12_H12_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_H12_H12_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_ - HDR OUPUT pipe Colorspace Converter (CSCO) h(2,2) matrix coefficient */ |
| /*! @{ */ |
| #define MED_HDR10_HDR__H22_MASK (0xFFFFU) |
| #define MED_HDR10_HDR__H22_SHIFT (0U) |
| #define MED_HDR10_HDR__H22(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR__H22_SHIFT)) & MED_HDR10_HDR__H22_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_IO_0 - HDR OUTPUT pipe Colorspace Converter (CSCO) component 0 pre-offset */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_IO_0_COMPO_PRE_OFFSET_MASK (0x3FFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_IO_0_COMPO_PRE_OFFSET_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_IO_0_COMPO_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_IO_0_COMPO_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_IO_0_COMPO_PRE_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_IO_1 - HDR OUPTUT pipe Colorspace Converter (CSCO) component 1 pre-offset */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_IO_1_COMP1_PRE_OFFSET_MASK (0x3FFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_IO_1_COMP1_PRE_OFFSET_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_IO_1_COMP1_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_IO_1_COMP1_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_IO_1_COMP1_PRE_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_IO_2 - HDR OUPUT pipe: Colorspace Converter (CSCO) component 2 pre-offset */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_IO_2_COMP2_PRE_OFFSET_MASK (0x3FFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_IO_2_COMP2_PRE_OFFSET_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_IO_2_COMP2_PRE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_IO_2_COMP2_PRE_OFFSET_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_IO_2_COMP2_PRE_OFFSET_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_MIN_0 - HDR OUPTU pipe Colorspace Converter (CSCO) component 0 clip min. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_MIN_0_COMP0_CLIP_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_MIN_0_COMP0_CLIP_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_MIN_0_COMP0_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_MIN_0_COMP0_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_MIN_0_COMP0_CLIP_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_MIN_1 - HDR OUPUT pipe Colorspace Converter (CSCO) component 1 clip min. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_MIN_1_COMP1_CLIP_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_MIN_1_COMP1_CLIP_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_MIN_1_COMP1_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_MIN_1_COMP1_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_MIN_1_COMP1_CLIP_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_MIN_2 - HDR OUPTU pipe Colorspace Converter (CSCO) component 2 clip min. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_MIN_2_COMP2_CLIP_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_MIN_2_COMP2_CLIP_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_MIN_2_COMP2_CLIP_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_MIN_2_COMP2_CLIP_MIN_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_MIN_2_COMP2_CLIP_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_MAX_0 - HDR OUPTUT pipe Colorspace Converter O (CSC) component 0 clip max value. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_MAX_0_COMP0_CLIP_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_MAX_0_COMP0_CLIP_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_MAX_0_COMP0_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_MAX_0_COMP0_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_MAX_0_COMP0_CLIP_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_MAX_1 - HDR OUTPUT pipe Colorspace Converter (CSCO) component 1 clip max value. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_MAX_1_COMP1_CLIP_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_MAX_1_COMP1_CLIP_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_MAX_1_COMP1_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_MAX_1_COMP1_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_MAX_1_COMP1_CLIP_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_MAX_2 - HDR OUTPUT pipe Colorspace Converter (CSCO) component 2 clip max value. */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_MAX_2_COMP2_CLIP_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_MAX_2_COMP2_CLIP_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_MAX_2_COMP2_CLIP_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_MAX_2_COMP2_CLIP_MAX_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_MAX_2_COMP2_CLIP_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_NORM - HDR OUPUT pipe Colorspace Converter (CSCO) normalization factor */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_NORM_CSC_NORM_MASK (0x1FU) |
| #define MED_HDR10_HDR_OPIPE_CSC_NORM_CSC_NORM_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_NORM_CSC_NORM(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_NORM_CSC_NORM_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_NORM_CSC_NORM_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_OO_0 - HDR OUPTUT pipe Colorspace Converter (CSC): Post offset component 0 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_OO_0_CSC_OO_0_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_OO_0_CSC_OO_0_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_OO_0_CSC_OO_0(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OO_0_CSC_OO_0_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OO_0_CSC_OO_0_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_OO_1 - HDR OUTPUT pipe Colorspace Converter (CSC): Post offset component 1 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_OO_1_CSC_OO_1_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_OO_1_CSC_OO_1_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_OO_1_CSC_OO_1(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OO_1_CSC_OO_1_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OO_1_CSC_OO_1_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_OO_2 - HDR OUPTUT pipe Colorspace Converter (CSC): Post offset component 2 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_OO_2_CSC_OO_2_MASK (0xFFFFFFFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_OO_2_CSC_OO_2_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_OO_2_CSC_OO_2(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OO_2_CSC_OO_2_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OO_2_CSC_OO_2_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_OMIN_0 - HDR OUTPUT pipe Colorspace Converter (CSC): Post offset min clip value for component 0 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_OMIN_0_POST_OFF_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_OMIN_0_POST_OFF_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_OMIN_0_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OMIN_0_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OMIN_0_POST_OFF_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_OMIN_1 - HDR OUTPUT pipe Colorspace Converter (CSC): Post offset min clip value for component 1 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_OMIN_1_POST_OFF_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_OMIN_1_POST_OFF_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_OMIN_1_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OMIN_1_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OMIN_1_POST_OFF_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_OMIN_2 - HDR OUTPUT pipe Colorspace Converter (CSC): Post offset min clip value for component 2 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_OMIN_2_POST_OFF_MIN_MASK (0x3FFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_OMIN_2_POST_OFF_MIN_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_OMIN_2_POST_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OMIN_2_POST_OFF_MIN_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OMIN_2_POST_OFF_MIN_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_OMAX_0 - HDR OUPTUT pipe Colorspace Converter (CSC): Post offset max clip value for component 0 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_OMAX_0_POST_OFF_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_OMAX_0_POST_OFF_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_OMAX_0_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OMAX_0_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OMAX_0_POST_OFF_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_OMAX_1 - HDR OUTPUT pipe Colorspace Converter (CSC): Post offset max clip value for component 1 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_OMAX_1_POST_OFF_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_OMAX_1_POST_OFF_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_OMAX_1_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OMAX_1_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OMAX_1_POST_OFF_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_CSC_OMAX_2 - HDR OUTPUT pipe Colorspace Converter (CSC): Post offset max clip value for component 2 */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_CSC_OMAX_2_POST_OFF_MAX_MASK (0x3FFU) |
| #define MED_HDR10_HDR_OPIPE_CSC_OMAX_2_POST_OFF_MAX_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_CSC_OMAX_2_POST_OFF_MAX(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_CSC_OMAX_2_POST_OFF_MAX_SHIFT)) & MED_HDR10_HDR_OPIPE_CSC_OMAX_2_POST_OFF_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name HDR_OPIPE_2NL_CONTROL_REG - HDR OUTPUT -TO NON LINEAR pipeline control */ |
| /*! @{ */ |
| #define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_PASS_THRU_MASK (0x1U) |
| #define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_PASS_THRU_SHIFT (0U) |
| #define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_PASS_THRU(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_PASS_THRU_SHIFT)) & MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_PASS_THRU_MASK) |
| #define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_DISABLE_FIXED_TO_FLOAT_MASK (0x2U) |
| #define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_DISABLE_FIXED_TO_FLOAT_SHIFT (1U) |
| #define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_DISABLE_FIXED_TO_FLOAT(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_DISABLE_FIXED_TO_FLOAT_SHIFT)) & MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_DISABLE_FIXED_TO_FLOAT_MASK) |
| #define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_LTNL_ENABLE_FOR_ALL_PELS_MASK (0x4U) |
| #define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_LTNL_ENABLE_FOR_ALL_PELS_SHIFT (2U) |
| #define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_LTNL_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_LTNL_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_LTNL_ENABLE_FOR_ALL_PELS_MASK) |
| #define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_FIX2FLT_ENABLE_FOR_ALL_PELS_MASK (0x8U) |
| #define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_FIX2FLT_ENABLE_FOR_ALL_PELS_SHIFT (3U) |
| #define MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_FIX2FLT_ENABLE_FOR_ALL_PELS(x) (((uint32_t)(((uint32_t)(x)) << MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_FIX2FLT_ENABLE_FOR_ALL_PELS_SHIFT)) & MED_HDR10_HDR_OPIPE_2NL_CONTROL_REG_FIX2FLT_ENABLE_FOR_ALL_PELS_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group MED_HDR10_Register_Masks */ |
| |
| |
| /* MED_HDR10 - Peripheral instance base addresses */ |
| /** Peripheral DCSS__MED_HDR10 base address */ |
| #define DCSS__MED_HDR10_BASE (0x32E0C000u) |
| /** Peripheral DCSS__MED_HDR10 base pointer */ |
| #define DCSS__MED_HDR10 ((MED_HDR10_Type *)DCSS__MED_HDR10_BASE) |
| /** Array initializer of MED_HDR10 peripheral base addresses */ |
| #define MED_HDR10_BASE_ADDRS { DCSS__MED_HDR10_BASE } |
| /** Array initializer of MED_HDR10 peripheral base pointers */ |
| #define MED_HDR10_BASE_PTRS { DCSS__MED_HDR10 } |
| |
| /*! |
| * @} |
| */ /* end of group MED_HDR10_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- MIPI_CSI2RX Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MIPI_CSI2RX_Peripheral_Access_Layer MIPI_CSI2RX Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** MIPI_CSI2RX - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t CSI2RX_CFG_NUM_LANES; /**< , offset: 0x0 */ |
| __IO uint32_t CSI2RX_CFG_DISABLE_DATA_LANES; /**< , offset: 0x4 */ |
| __I uint32_t CSI2RX_BIT_ERR; /**< , offset: 0x8 */ |
| __I uint32_t CSI2RX_IRQ_STATUS; /**< , offset: 0xC */ |
| __IO uint32_t CSI2RX_IRQ_MASK; /**< , offset: 0x10 */ |
| __I uint32_t CSI2RX_ULPS_STATUS; /**< , offset: 0x14 */ |
| __I uint32_t CSI2RX_PPI_ERRSOT_HS; /**< , offset: 0x18 */ |
| __I uint32_t CSI2RX_PPI_ERRSOTSYNC_HS; /**< , offset: 0x1C */ |
| __I uint32_t CSI2RX_PPI_ERRESC; /**< , offset: 0x20 */ |
| __I uint32_t CSI2RX_PPI_ERRSYNCESC; /**< , offset: 0x24 */ |
| __I uint32_t CSI2RX_PPI_ERRCONTROL; /**< , offset: 0x28 */ |
| __IO uint32_t CSI2RX_CFG_DISABLE_PAYLOAD_0; /**< , offset: 0x2C */ |
| __IO uint32_t CSI2RX_CFG_DISABLE_PAYLOAD_1; /**< , offset: 0x30 */ |
| } MIPI_CSI2RX_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- MIPI_CSI2RX Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MIPI_CSI2RX_Register_Masks MIPI_CSI2RX Register Masks |
| * @{ |
| */ |
| |
| /*! @name CSI2RX_CFG_NUM_LANES - */ |
| /*! @{ */ |
| #define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_MASK (0x3U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_SHIFT (0U) |
| /*! csi2rx_cfg_num_lanes - Sets the number of active lanes that are to be used for receiving data. |
| * 0b00..1 Lane |
| * 0b01..2 Lane |
| * 0b10..3 Lane |
| * 0b11..4 Lane |
| */ |
| #define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_MASK) |
| /*! @} */ |
| |
| /*! @name CSI2RX_CFG_DISABLE_DATA_LANES - */ |
| /*! @{ */ |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_MASK (0xFU) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_SHIFT (0U) |
| /*! csi2rx_cfg_disable_data_lanes - Setting bits to a '1' value causes the DPHY Enable signal to deassert. |
| * 0b0001..Data Lane 0 |
| * 0b0010..Data Lane 1 |
| * 0b0100..Data Lane 2 |
| * 0b1000..Data Lane 3 |
| */ |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_MASK) |
| /*! @} */ |
| |
| /*! @name CSI2RX_BIT_ERR - */ |
| /*! @{ */ |
| #define MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_MASK (0x3FFU) |
| #define MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_SHIFT (0U) |
| #define MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_SHIFT)) & MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_MASK) |
| /*! @} */ |
| |
| /*! @name CSI2RX_IRQ_STATUS - */ |
| /*! @{ */ |
| #define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_MASK (0x1FFU) |
| #define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_SHIFT (0U) |
| #define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_SHIFT)) & MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_MASK) |
| /*! @} */ |
| |
| /*! @name CSI2RX_IRQ_MASK - */ |
| /*! @{ */ |
| #define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_MASK (0x1FFU) |
| #define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_SHIFT (0U) |
| #define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_SHIFT)) & MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_MASK) |
| /*! @} */ |
| |
| /*! @name CSI2RX_ULPS_STATUS - */ |
| /*! @{ */ |
| #define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_MASK (0x3FFU) |
| #define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_SHIFT (0U) |
| #define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_SHIFT)) & MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_MASK) |
| /*! @} */ |
| |
| /*! @name CSI2RX_PPI_ERRSOT_HS - */ |
| /*! @{ */ |
| #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_MASK (0xFU) |
| #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_SHIFT (0U) |
| #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_MASK) |
| /*! @} */ |
| |
| /*! @name CSI2RX_PPI_ERRSOTSYNC_HS - */ |
| /*! @{ */ |
| #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_MASK (0xFU) |
| #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_SHIFT (0U) |
| #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_MASK) |
| /*! @} */ |
| |
| /*! @name CSI2RX_PPI_ERRESC - */ |
| /*! @{ */ |
| #define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_MASK (0xFU) |
| #define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_SHIFT (0U) |
| #define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_MASK) |
| /*! @} */ |
| |
| /*! @name CSI2RX_PPI_ERRSYNCESC - */ |
| /*! @{ */ |
| #define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_MASK (0xFU) |
| #define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_SHIFT (0U) |
| #define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_MASK) |
| /*! @} */ |
| |
| /*! @name CSI2RX_PPI_ERRCONTROL - */ |
| /*! @{ */ |
| #define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_MASK (0xFU) |
| #define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_SHIFT (0U) |
| #define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_MASK) |
| /*! @} */ |
| |
| /*! @name CSI2RX_CFG_DISABLE_PAYLOAD_0 - */ |
| /*! @{ */ |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_null_MASK (0x1U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_null_SHIFT (0U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_null(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_null_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_null_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_blank_MASK (0x2U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_blank_SHIFT (1U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_blank(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_blank_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_blank_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_embedded_MASK (0x4U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_embedded_SHIFT (2U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_embedded(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_embedded_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_embedded_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_legacy_yuv_8_MASK (0x400U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_legacy_yuv_8_SHIFT (10U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_legacy_yuv_8(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_legacy_yuv_8_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_legacy_yuv_8_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_8_MASK (0x4000U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_8_SHIFT (14U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_8(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_8_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_8_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_10_MASK (0x8000U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_10_SHIFT (15U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_10_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_yuv_10_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb444_MASK (0x10000U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb444_SHIFT (16U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb444(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb444_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb444_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb555_MASK (0x20000U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb555_SHIFT (17U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb555(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb555_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb555_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb565_MASK (0x40000U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb565_SHIFT (18U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb565(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb565_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb565_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb666_MASK (0x80000U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb666_SHIFT (19U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb666(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb666_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb666_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb888_MASK (0x100000U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb888_SHIFT (20U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb888(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb888_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_rgb888_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw6_MASK (0x1000000U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw6_SHIFT (24U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw6(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw6_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw6_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw7_MASK (0x2000000U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw7_SHIFT (25U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw7(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw7_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw7_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw8_MASK (0x4000000U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw8_SHIFT (26U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw8(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw8_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw8_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw10_MASK (0x8000000U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw10_SHIFT (27U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw10_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw10_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw12_MASK (0x10000000U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw12_SHIFT (28U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw12(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw12_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw12_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw14_MASK (0x20000000U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw14_SHIFT (29U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw14(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw14_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_raw14_MASK) |
| /*! @} */ |
| |
| /*! @name CSI2RX_CFG_DISABLE_PAYLOAD_1 - */ |
| /*! @{ */ |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_30_MASK (0x1U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_30_SHIFT (0U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_30(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_30_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_30_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_31_MASK (0x2U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_31_SHIFT (1U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_31_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_31_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_32_MASK (0x4U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_32_SHIFT (2U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_32(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_32_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_32_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_33_MASK (0x8U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_33_SHIFT (3U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_33(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_33_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_33_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_34_MASK (0x10U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_34_SHIFT (4U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_34(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_34_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_34_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_35_MASK (0x20U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_35_SHIFT (5U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_35(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_35_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_35_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_36_MASK (0x40U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_36_SHIFT (6U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_36(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_36_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_36_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_37_MASK (0x80U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_37_SHIFT (7U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_37(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_37_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_udef_37_MASK) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_unsupported_MASK (0x10000U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_unsupported_SHIFT (16U) |
| #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_unsupported(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_unsupported_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_unsupported_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group MIPI_CSI2RX_Register_Masks */ |
| |
| |
| /* MIPI_CSI2RX - Peripheral instance base addresses */ |
| /** Peripheral MIPI_CSI2RX1 base address */ |
| #define MIPI_CSI2RX1_BASE (0x30A70000u) |
| /** Peripheral MIPI_CSI2RX1 base pointer */ |
| #define MIPI_CSI2RX1 ((MIPI_CSI2RX_Type *)MIPI_CSI2RX1_BASE) |
| /** Peripheral MIPI_CSI2RX2 base address */ |
| #define MIPI_CSI2RX2_BASE (0x30B60000u) |
| /** Peripheral MIPI_CSI2RX2 base pointer */ |
| #define MIPI_CSI2RX2 ((MIPI_CSI2RX_Type *)MIPI_CSI2RX2_BASE) |
| /** Array initializer of MIPI_CSI2RX peripheral base addresses */ |
| #define MIPI_CSI2RX_BASE_ADDRS { 0u, MIPI_CSI2RX1_BASE, MIPI_CSI2RX2_BASE } |
| /** Array initializer of MIPI_CSI2RX peripheral base pointers */ |
| #define MIPI_CSI2RX_BASE_PTRS { (MIPI_CSI2RX_Type *)0u, MIPI_CSI2RX1, MIPI_CSI2RX2 } |
| |
| /*! |
| * @} |
| */ /* end of group MIPI_CSI2RX_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- MIPI_DSI_HOST Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MIPI_DSI_HOST_Peripheral_Access_Layer MIPI_DSI_HOST Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** MIPI_DSI_HOST - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t DSI_HOST_CFG_NUM_LANES; /**< , offset: 0x0 */ |
| __IO uint32_t DSI_HOST_CFG_NONCONTINUOUS_CLK; /**< , offset: 0x4 */ |
| __IO uint32_t DSI_HOST_CFG_T_PRE; /**< , offset: 0x8 */ |
| __IO uint32_t DSI_HOST_CFG_T_POST; /**< , offset: 0xC */ |
| __IO uint32_t DSI_HOST_CFG_TX_GAP; /**< , offset: 0x10 */ |
| __IO uint32_t DSI_HOST_CFG_AUTOINSERT_EOTP; /**< , offset: 0x14 */ |
| __IO uint32_t DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP; /**< , offset: 0x18 */ |
| __IO uint32_t DSI_HOST_CFG_HTX_TO_COUNT; /**< , offset: 0x1C */ |
| __IO uint32_t DSI_HOST_CFG_LRX_H_TO_COUNT; /**< , offset: 0x20 */ |
| __IO uint32_t DSI_HOST_CFG_BTA_H_TO_COUNT; /**< , offset: 0x24 */ |
| __IO uint32_t DSI_HOST_CFG_TWAKEUP; /**< , offset: 0x28 */ |
| __I uint32_t DSI_HOST_CFG_STATUS_OUT; /**< , offset: 0x2C */ |
| __I uint32_t DSI_HOST_RX_ERROR_STATUS; /**< , offset: 0x30 */ |
| } MIPI_DSI_HOST_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- MIPI_DSI_HOST Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MIPI_DSI_HOST_Register_Masks MIPI_DSI_HOST Register Masks |
| * @{ |
| */ |
| |
| /*! @name DSI_HOST_CFG_NUM_LANES - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_MASK (0x3U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_SHIFT (0U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_NONCONTINUOUS_CLK - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_MASK (0x1U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_SHIFT (0U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_T_PRE - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_MASK (0x7FU) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_SHIFT (0U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_T_POST - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_MASK (0x7FU) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_SHIFT (0U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_TX_GAP - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_MASK (0x7FU) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_SHIFT (0U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_AUTOINSERT_EOTP - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_MASK (0x1U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_SHIFT (0U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_MASK (0xFFU) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_SHIFT (0U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_HTX_TO_COUNT - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_MASK (0xFFFFFFU) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_SHIFT (0U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_LRX_H_TO_COUNT - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_MASK (0xFFFFFFU) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_SHIFT (0U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_BTA_H_TO_COUNT - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_MASK (0xFFFFFFU) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_SHIFT (0U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_TWAKEUP - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_MASK (0x7FFFFU) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_SHIFT (0U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_STATUS_OUT - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_ERROR_MASK (0x1U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_ERROR_SHIFT (0U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_ERROR_MASK) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_SYNC_ERROR_MASK (0x2U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_SYNC_ERROR_SHIFT (1U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_SYNC_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_SYNC_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_SOT_SYNC_ERROR_MASK) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_EOT_SYNC_ERROR_MASK (0x4U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_EOT_SYNC_ERROR_SHIFT (2U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_EOT_SYNC_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_EOT_SYNC_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_EOT_SYNC_ERROR_MASK) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ESCAPE_MODE_ENTRY_CMD_ERROR_MASK (0x8U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ESCAPE_MODE_ENTRY_CMD_ERROR_SHIFT (3U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ESCAPE_MODE_ENTRY_CMD_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ESCAPE_MODE_ENTRY_CMD_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ESCAPE_MODE_ENTRY_CMD_ERROR_MASK) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_LP_TX_SYNC_ERROR_MASK (0x10U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_LP_TX_SYNC_ERROR_SHIFT (4U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_LP_TX_SYNC_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_LP_TX_SYNC_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_LP_TX_SYNC_ERROR_MASK) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_PERIPH_TIMEOUT_ERROR_MASK (0x20U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_PERIPH_TIMEOUT_ERROR_SHIFT (5U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_PERIPH_TIMEOUT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_PERIPH_TIMEOUT_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_PERIPH_TIMEOUT_ERROR_MASK) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_FALSE_CONTROL_ERROR_MASK (0x40U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_FALSE_CONTROL_ERROR_SHIFT (6U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_FALSE_CONTROL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_FALSE_CONTROL_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_FALSE_CONTROL_ERROR_MASK) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CONTENTION_DETECT_MASK (0x80U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CONTENTION_DETECT_SHIFT (7U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CONTENTION_DETECT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CONTENTION_DETECT_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CONTENTION_DETECT_MASK) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_SINGLE_BIT_MASK (0x100U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_SINGLE_BIT_SHIFT (8U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_SINGLE_BIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_SINGLE_BIT_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_SINGLE_BIT_MASK) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_MULTI_BIT_MASK (0x200U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_MULTI_BIT_SHIFT (9U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_MULTI_BIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_MULTI_BIT_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_ECC_ERROR_MULTI_BIT_MASK) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CHECKSUM_ERROR_MASK (0x400U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CHECKSUM_ERROR_SHIFT (10U) |
| #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CHECKSUM_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CHECKSUM_ERROR_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_CHECKSUM_ERROR_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_RX_ERROR_STATUS - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_MASK (0x7FFU) |
| #define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_SHIFT (0U) |
| #define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group MIPI_DSI_HOST_Register_Masks */ |
| |
| |
| /* MIPI_DSI_HOST - Peripheral instance base addresses */ |
| /** Peripheral MIPI_DSI_HOST base address */ |
| #define MIPI_DSI_HOST_BASE (0x30A10000u) |
| /** Peripheral MIPI_DSI_HOST base pointer */ |
| #define MIPI_DSI_HOST ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST_BASE) |
| /** Array initializer of MIPI_DSI_HOST peripheral base addresses */ |
| #define MIPI_DSI_HOST_BASE_ADDRS { MIPI_DSI_HOST_BASE } |
| /** Array initializer of MIPI_DSI_HOST peripheral base pointers */ |
| #define MIPI_DSI_HOST_BASE_PTRS { MIPI_DSI_HOST } |
| |
| /*! |
| * @} |
| */ /* end of group MIPI_DSI_HOST_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- MIPI_DSI_HOST_APB_PKT_IF Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MIPI_DSI_HOST_APB_PKT_IF_Peripheral_Access_Layer MIPI_DSI_HOST_APB_PKT_IF Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** MIPI_DSI_HOST_APB_PKT_IF - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t DSI_HOST_TX_PAYLOAD; /**< , offset: 0x0 */ |
| __IO uint32_t DSI_HOST_PKT_CONTROL; /**< , offset: 0x4 */ |
| __IO uint32_t DSI_HOST_SEND_PACKET; /**< , offset: 0x8 */ |
| __I uint32_t DSI_HOST_PKT_STATUS; /**< , offset: 0xC */ |
| __I uint32_t DSI_HOST_PKT_FIFO_WR_LEVEL; /**< , offset: 0x10 */ |
| __I uint32_t DSI_HOST_PKT_FIFO_RD_LEVEL; /**< , offset: 0x14 */ |
| __I uint32_t DSI_HOST_PKT_RX_PAYLOAD; /**< , offset: 0x18 */ |
| __I uint32_t DSI_HOST_PKT_RX_PKT_HEADER; /**< , offset: 0x1C */ |
| __I uint32_t DSI_HOST_IRQ_STATUS; /**< , offset: 0x20 */ |
| __I uint32_t DSI_HOST_IRQ_STATUS2; /**< , offset: 0x24 */ |
| __IO uint32_t DSI_HOST_IRQ_MASK; /**< , offset: 0x28 */ |
| __IO uint32_t DSI_HOST_IRQ_MASK2; /**< , offset: 0x2C */ |
| } MIPI_DSI_HOST_APB_PKT_IF_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- MIPI_DSI_HOST_APB_PKT_IF Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MIPI_DSI_HOST_APB_PKT_IF_Register_Masks MIPI_DSI_HOST_APB_PKT_IF Register Masks |
| * @{ |
| */ |
| |
| /*! @name DSI_HOST_TX_PAYLOAD - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_MASK (0xFFFFFFFFU) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_SHIFT (0U) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_PKT_CONTROL - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_MASK (0x7FFFFFFU) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_SHIFT (0U) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_SEND_PACKET - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_SEND_PACKET_dsi_host_send_packet_MASK (0x1U) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_SEND_PACKET_dsi_host_send_packet_SHIFT (0U) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_SEND_PACKET_dsi_host_send_packet(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_SEND_PACKET_dsi_host_send_packet_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_SEND_PACKET_dsi_host_send_packet_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_PKT_STATUS - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_MASK (0x1FFU) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_SHIFT (0U) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_STATUS_dsi_host_pkt_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_PKT_FIFO_WR_LEVEL - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_MASK (0xFFFFU) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_SHIFT (0U) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_PKT_FIFO_RD_LEVEL - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_MASK (0xFFFFU) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_SHIFT (0U) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_PKT_RX_PAYLOAD - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_MASK (0xFFFFFFFFU) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_SHIFT (0U) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_PKT_RX_PKT_HEADER - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_MASK (0xFFFFFFU) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_SHIFT (0U) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_IRQ_STATUS - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_MASK (0xFFFFFFFFU) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_SHIFT (0U) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS_dsi_host_irq_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_IRQ_STATUS2 - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_MASK (0x7U) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_SHIFT (0U) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_IRQ_MASK - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_MASK (0xFFFFFFFFU) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_SHIFT (0U) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK_dsi_host_irq_mask(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_IRQ_MASK2 - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_MASK (0x7U) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_SHIFT (0U) |
| #define MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_SHIFT)) & MIPI_DSI_HOST_APB_PKT_IF_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group MIPI_DSI_HOST_APB_PKT_IF_Register_Masks */ |
| |
| |
| /* MIPI_DSI_HOST_APB_PKT_IF - Peripheral instance base addresses */ |
| /** Peripheral MIPI_DSI_HOST_APB_PKT_IF base address */ |
| #define MIPI_DSI_HOST_APB_PKT_IF_BASE (0x30A10280u) |
| /** Peripheral MIPI_DSI_HOST_APB_PKT_IF base pointer */ |
| #define MIPI_DSI_HOST_APB_PKT_IF ((MIPI_DSI_HOST_APB_PKT_IF_Type *)MIPI_DSI_HOST_APB_PKT_IF_BASE) |
| /** Array initializer of MIPI_DSI_HOST_APB_PKT_IF peripheral base addresses */ |
| #define MIPI_DSI_HOST_APB_PKT_IF_BASE_ADDRS { MIPI_DSI_HOST_APB_PKT_IF_BASE } |
| /** Array initializer of MIPI_DSI_HOST_APB_PKT_IF peripheral base pointers */ |
| #define MIPI_DSI_HOST_APB_PKT_IF_BASE_PTRS { MIPI_DSI_HOST_APB_PKT_IF } |
| |
| /*! |
| * @} |
| */ /* end of group MIPI_DSI_HOST_APB_PKT_IF_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- MIPI_DSI_HOST_DPI_INTFC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MIPI_DSI_HOST_DPI_INTFC_Peripheral_Access_Layer MIPI_DSI_HOST_DPI_INTFC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** MIPI_DSI_HOST_DPI_INTFC - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE; /**< , offset: 0x0 */ |
| __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL; /**< , offset: 0x4 */ |
| __IO uint32_t DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING; /**< , offset: 0x8 */ |
| __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_FORMAT; /**< , offset: 0xC */ |
| __IO uint32_t DSI_HOST_CFG_DPI_VSYNC_POLARITY; /**< , offset: 0x10 */ |
| __IO uint32_t DSI_HOST_CFG_DPI_HSYNC_POLARITY; /**< , offset: 0x14 */ |
| __IO uint32_t DSI_HOST_CFG_DPI_VIDEO_MODE; /**< , offset: 0x18 */ |
| __IO uint32_t DSI_HOST_CFG_DPI_HFP; /**< , offset: 0x1C */ |
| __IO uint32_t DSI_HOST_CFG_DPI_HBP; /**< , offset: 0x20 */ |
| __IO uint32_t DSI_HOST_CFG_DPI_HSA; /**< , offset: 0x24 */ |
| __IO uint32_t DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS; /**< , offset: 0x28 */ |
| __IO uint32_t DSI_HOST_CFG_DPI_VBP; /**< , offset: 0x2C */ |
| __IO uint32_t DSI_HOST_CFG_DPI_VFP; /**< , offset: 0x30 */ |
| __IO uint32_t DSI_HOST_CFG_DPI_BLLP_MODE; /**< , offset: 0x34 */ |
| __IO uint32_t DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP; /**< , offset: 0x38 */ |
| __IO uint32_t DSI_HOST_CFG_DPI_VACTIVE; /**< , offset: 0x3C */ |
| __IO uint32_t DSI_HOST_CFG_DPI_VC; /**< , offset: 0x40 */ |
| } MIPI_DSI_HOST_DPI_INTFC_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- MIPI_DSI_HOST_DPI_INTFC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MIPI_DSI_HOST_DPI_INTFC_Register_Masks MIPI_DSI_HOST_DPI_INTFC Register Masks |
| * @{ |
| */ |
| |
| /*! @name DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_MASK (0xFFFFU) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_SHIFT (0U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_MASK (0xFFFFU) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_SHIFT (0U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_MASK (0x7U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_SHIFT (0U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_DPI_PIXEL_FORMAT - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_MASK (0x3U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_SHIFT (0U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_DPI_VSYNC_POLARITY - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_MASK (0x1U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_SHIFT (0U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_DPI_HSYNC_POLARITY - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_MASK (0x1U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_SHIFT (0U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_DPI_VIDEO_MODE - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_MASK (0x3U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_SHIFT (0U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_DPI_HFP - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_MASK (0xFFFFU) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_SHIFT (0U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_DPI_HBP - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_MASK (0xFFFFU) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_SHIFT (0U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_DPI_HSA - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_MASK (0xFFFFU) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_SHIFT (0U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_MASK (0x1U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_SHIFT (0U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_DPI_VBP - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_MASK (0xFFU) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_SHIFT (0U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_DPI_VFP - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_MASK (0xFFU) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_SHIFT (0U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_DPI_BLLP_MODE - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_MASK (0x1U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_SHIFT (0U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_MASK (0x1U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_SHIFT (0U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_DPI_VACTIVE - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_MASK (0x3FFFU) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_SHIFT (0U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_MASK) |
| /*! @} */ |
| |
| /*! @name DSI_HOST_CFG_DPI_VC - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_MASK (0x3U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_SHIFT (0U) |
| #define MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_SHIFT)) & MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group MIPI_DSI_HOST_DPI_INTFC_Register_Masks */ |
| |
| |
| /* MIPI_DSI_HOST_DPI_INTFC - Peripheral instance base addresses */ |
| /** Peripheral MIPI_DSI_HOST_DPI_INTFC base address */ |
| #define MIPI_DSI_HOST_DPI_INTFC_BASE (0x30A10200u) |
| /** Peripheral MIPI_DSI_HOST_DPI_INTFC base pointer */ |
| #define MIPI_DSI_HOST_DPI_INTFC ((MIPI_DSI_HOST_DPI_INTFC_Type *)MIPI_DSI_HOST_DPI_INTFC_BASE) |
| /** Array initializer of MIPI_DSI_HOST_DPI_INTFC peripheral base addresses */ |
| #define MIPI_DSI_HOST_DPI_INTFC_BASE_ADDRS { MIPI_DSI_HOST_DPI_INTFC_BASE } |
| /** Array initializer of MIPI_DSI_HOST_DPI_INTFC peripheral base pointers */ |
| #define MIPI_DSI_HOST_DPI_INTFC_BASE_PTRS { MIPI_DSI_HOST_DPI_INTFC } |
| |
| /*! |
| * @} |
| */ /* end of group MIPI_DSI_HOST_DPI_INTFC_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Peripheral_Access_Layer MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t DPHY_PD_DPHY; /**< , offset: 0x0 */ |
| __IO uint32_t DPHY_M_PRG_HS_PREPARE; /**< , offset: 0x4 */ |
| __IO uint32_t DPHY_MC_PRG_HS_PREPARE; /**< , offset: 0x8 */ |
| __IO uint32_t DPHY_M_PRG_HS_ZERO; /**< , offset: 0xC */ |
| __IO uint32_t DPHY_MC_PRG_HS_ZERO; /**< , offset: 0x10 */ |
| __IO uint32_t DPHY_M_PRG_HS_TRAIL; /**< , offset: 0x14 */ |
| __IO uint32_t DPHY_MC_PRG_HS_TRAIL; /**< , offset: 0x18 */ |
| __IO uint32_t DPHY_PD_PLL; /**< , offset: 0x1C */ |
| __IO uint32_t DPHY_TST; /**< , offset: 0x20 */ |
| __IO uint32_t DPHY_CN; /**< , offset: 0x24 */ |
| __IO uint32_t DPHY_CM; /**< , offset: 0x28 */ |
| __IO uint32_t DPHY_CO; /**< , offset: 0x2C */ |
| __I uint32_t DPHY_LOCK; /**< , offset: 0x30 */ |
| __IO uint32_t DPHY_LOCK_BYP; /**< , offset: 0x34 */ |
| __IO uint32_t DPHY_RTERM_SEL; /**< , offset: 0x38 */ |
| __IO uint32_t DPHY_AUTO_PD_EN; /**< , offset: 0x3C */ |
| __IO uint32_t DPHY_RXLPRP; /**< , offset: 0x40 */ |
| __IO uint32_t DPHY_RXCDRP; /**< , offset: 0x44 */ |
| } MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Register_Masks MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC Register Masks |
| * @{ |
| */ |
| |
| /*! @name DPHY_PD_DPHY - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_DPHY_dphy_pd_dphy_MASK (0x1U) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_DPHY_dphy_pd_dphy_SHIFT (0U) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_DPHY_dphy_pd_dphy(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_DPHY_dphy_pd_dphy_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_DPHY_dphy_pd_dphy_MASK) |
| /*! @} */ |
| |
| /*! @name DPHY_M_PRG_HS_PREPARE - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_MASK (0x3U) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_SHIFT (0U) |
| /*! dphy_m_prg_hs_prepare - DPHY m_PRG_HS_PREPARE input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. |
| * 0b00..1 |
| * 0b01..1.5 |
| * 0b10..2 |
| * 0b11..2.5 |
| */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_MASK) |
| /*! @} */ |
| |
| /*! @name DPHY_MC_PRG_HS_PREPARE - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_MASK (0x1U) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_SHIFT (0U) |
| /*! dphy_mc_prg_hs_prepare - DPHY mc_PRG_HS_PREPARE input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. |
| * 0b0..1 |
| * 0b1..1.5 |
| */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_MASK) |
| /*! @} */ |
| |
| /*! @name DPHY_M_PRG_HS_ZERO - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_MASK (0x1FU) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_SHIFT (0U) |
| /*! dphy_m_prg_hs_zero - DPHY m_PRG_HS_ZERO input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. |
| * 0b00000..0 |
| * 0b00001..1 |
| * 0b00010..2 |
| * 0b00011..3 |
| * 0b00100..4 |
| * 0b00101..5 |
| * 0b00110..6 |
| * 0b00111..7 |
| * 0b01000..8 |
| * 0b01001..9 |
| * 0b01010..10 |
| * 0b01011..11 |
| * 0b01100..12 |
| * 0b01101..13 |
| * 0b01110..14 |
| * 0b01111..15 |
| * 0b10000..16 |
| * 0b10001..17 |
| * 0b10010..18 |
| * 0b10011..19 |
| * 0b10100..20 |
| * 0b10101..21 |
| * 0b10110..22 |
| * 0b10111..23 |
| * 0b11000..24 |
| * 0b11001..25 |
| * 0b11010..26 |
| * 0b11011..27 |
| * 0b11100..28 |
| * 0b11101..29 |
| * 0b11110..30 |
| * 0b11111..31 |
| */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_MASK) |
| /*! @} */ |
| |
| /*! @name DPHY_MC_PRG_HS_ZERO - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_MASK (0x3FU) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_SHIFT (0U) |
| /*! dphy_mc_prg_hs_zero - DPHY mc_PRG_HS_ZERO input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. |
| * 0b100000..32 |
| * 0b100001..33 |
| * 0b100010..34 |
| * 0b100011..35 |
| * 0b100100..36 |
| * 0b100101..37 |
| * 0b100110..38 |
| * 0b100111..39 |
| * 0b101000..40 |
| * 0b101001..41 |
| * 0b101010..42 |
| * 0b101011..43 |
| * 0b101100..44 |
| * 0b101101..45 |
| * 0b101110..46 |
| * 0b101111..47 |
| * 0b110000..48 |
| * 0b110001..49 |
| * 0b110010..50 |
| * 0b110011..51 |
| * 0b110100..52 |
| * 0b110101..53 |
| * 0b110110..54 |
| * 0b110111..55 |
| * 0b111000..56 |
| * 0b111001..57 |
| * 0b111010..58 |
| * 0b111011..59 |
| * 0b111100..60 |
| * 0b111101..61 |
| * 0b111110..62 |
| * 0b111111..63 |
| */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_MASK) |
| /*! @} */ |
| |
| /*! @name DPHY_M_PRG_HS_TRAIL - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_MASK (0xFU) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_SHIFT (0U) |
| /*! dphy_m_prg_hs_trail - DPHY m_PRG_HS_TRAIL input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. |
| * 0b0000..0 |
| * 0b0001..1 |
| * 0b0010..2 |
| * 0b0011..3 |
| * 0b0100..4 |
| * 0b0101..5 |
| * 0b0110..6 |
| * 0b0111..7 |
| * 0b1000..8 |
| * 0b1001..9 |
| * 0b1010..10 |
| * 0b1011..11 |
| * 0b1100..12 |
| * 0b1101..13 |
| * 0b1110..14 |
| * 0b1111..15 |
| */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_MASK) |
| /*! @} */ |
| |
| /*! @name DPHY_MC_PRG_HS_TRAIL - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_MASK (0xFU) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_SHIFT (0U) |
| /*! dphy_mc_prg_hs_trail - DPHY mc_PRG_HS_TRAIL input. Detailed information about this parameter programming is available in the MIPI-DSI DPHY section. |
| * 0b0000..0 |
| * 0b0001..1 |
| * 0b0010..2 |
| * 0b0011..3 |
| * 0b0100..4 |
| * 0b0101..5 |
| * 0b0110..6 |
| * 0b0111..7 |
| * 0b1000..8 |
| * 0b1001..9 |
| * 0b1010..10 |
| * 0b1011..11 |
| * 0b1100..12 |
| * 0b1101..13 |
| * 0b1110..14 |
| * 0b1111..15 |
| */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_MASK) |
| /*! @} */ |
| |
| /*! @name DPHY_PD_PLL - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_PLL_PD_MASK (0x1U) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_PLL_PD_SHIFT (0U) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_PLL_PD(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_PLL_PD_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_PD_PLL_PD_MASK) |
| /*! @} */ |
| |
| /*! @name DPHY_TST - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_TST_TST_MASK (0x3FU) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_TST_TST_SHIFT (0U) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_TST_TST(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_TST_TST_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_TST_TST_MASK) |
| /*! @} */ |
| |
| /*! @name DPHY_CN - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN_CN_MASK (0x1FU) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN_CN_SHIFT (0U) |
| /*! CN |
| * 0b11111..Divide by 1 |
| * 0b00000..Divide by 2 |
| * 0b10000..Divide by 3 |
| * 0b11000..Divide by 4 |
| * 0b11100..Divide by 5 |
| * 0b01110..Divide by 6 |
| * 0b00111..Divide by 7 |
| * 0b10011..Divide by 8 |
| * 0b01001..Divide by 9 |
| * 0b00100..Divide by 10 |
| * 0b00010..Divide by 11 |
| * 0b10001..Divide by 12 |
| * 0b01000..Divide by 13 |
| * 0b10100..Divide by 14 |
| * 0b01010..Divide by 15 |
| * 0b10101..Divide by 16 |
| * 0b11010..Divide by 17 |
| * 0b11101..Divide by 18 |
| * 0b11110..Divide by 19 |
| * 0b01111..Divide by 20 |
| * 0b10111..Divide by 21 |
| * 0b11011..Divide by 22 |
| * 0b01101..Divide by 23 |
| * 0b10110..Divide by 24 |
| * 0b01011..Divide by 25 |
| * 0b00101..Divide by 26 |
| * 0b10010..Divide by 27 |
| * 0b11001..Divide by 28 |
| * 0b01100..Divide by 29 |
| * 0b00110..Divide by 30 |
| * 0b00011..Divide by 31 |
| * 0b00001..Divide by 32 |
| */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN_CN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN_CN_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN_CN_MASK) |
| /*! @} */ |
| |
| /*! @name DPHY_CM - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM_CM_MASK (0xFFU) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM_CM_SHIFT (0U) |
| /*! CM |
| * 0b111x0000..Divide by 16 |
| * 0b111x1111..Divide by 31 |
| * 0b11000000..Divide by 32 |
| * 0b11011111..Divide by 63 |
| * 0b10000000..Divide by 64 |
| * 0b10111111..Divide by 127 |
| * 0b00000000..Divide by 128 |
| * 0b01111111..Divide by 255 |
| */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM_CM(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM_CM_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM_CM_MASK) |
| /*! @} */ |
| |
| /*! @name DPHY_CO - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO_CO_MASK (0x3U) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO_CO_SHIFT (0U) |
| /*! CO |
| * 0b00..Divide by 1 |
| * 0b01..Divide by 2 |
| * 0b10..Divide by 4 |
| * 0b11..Divide by 8 |
| */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO_CO(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO_CO_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO_CO_MASK) |
| /*! @} */ |
| |
| /*! @name DPHY_LOCK - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_LOCK_MASK (0x1U) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_LOCK_SHIFT (0U) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_LOCK_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_LOCK_MASK) |
| /*! @} */ |
| |
| /*! @name DPHY_LOCK_BYP - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_BYP_dphy_lock_byp_MASK (0x1U) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_BYP_dphy_lock_byp_SHIFT (0U) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_BYP_dphy_lock_byp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_BYP_dphy_lock_byp_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_LOCK_BYP_dphy_lock_byp_MASK) |
| /*! @} */ |
| |
| /*! @name DPHY_RTERM_SEL - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RTERM_SEL_dphy_rterm_sel_MASK (0x1U) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RTERM_SEL_dphy_rterm_sel_SHIFT (0U) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RTERM_SEL_dphy_rterm_sel(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RTERM_SEL_dphy_rterm_sel_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RTERM_SEL_dphy_rterm_sel_MASK) |
| /*! @} */ |
| |
| /*! @name DPHY_AUTO_PD_EN - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_AUTO_PD_EN_dphy_auto_pd_en_MASK (0x1U) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_AUTO_PD_EN_dphy_auto_pd_en_SHIFT (0U) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_AUTO_PD_EN_dphy_auto_pd_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_AUTO_PD_EN_dphy_auto_pd_en_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_AUTO_PD_EN_dphy_auto_pd_en_MASK) |
| /*! @} */ |
| |
| /*! @name DPHY_RXLPRP - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXLPRP_dphy_rxlprp_MASK (0x3U) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXLPRP_dphy_rxlprp_SHIFT (0U) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXLPRP_dphy_rxlprp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXLPRP_dphy_rxlprp_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXLPRP_dphy_rxlprp_MASK) |
| /*! @} */ |
| |
| /*! @name DPHY_RXCDRP - */ |
| /*! @{ */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXCDRP_dphy_rxcdrp_MASK (0x3U) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXCDRP_dphy_rxcdrp_SHIFT (0U) |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXCDRP_dphy_rxcdrp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXCDRP_dphy_rxcdrp_SHIFT)) & MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_RXCDRP_dphy_rxcdrp_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Register_Masks */ |
| |
| |
| /* MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC - Peripheral instance base addresses */ |
| /** Peripheral MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC base address */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_BASE (0x30A10300u) |
| /** Peripheral MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC base pointer */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC ((MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Type *)MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_BASE) |
| /** Array initializer of MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC peripheral base |
| * addresses */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_BASE_ADDRS { MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_BASE } |
| /** Array initializer of MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC peripheral base |
| * pointers */ |
| #define MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_BASE_PTRS { MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC } |
| |
| /*! |
| * @} |
| */ /* end of group MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_Peripheral_Access_Layer */ |
| |
| /*! |
| * @brief Power mode on the other side definition. |
| */ |
| typedef enum _mu_power_mode |
| { |
| kMU_PowerModeRun = 0x00U, /*!< Run mode. */ |
| kMU_PowerModeWait = 0x01U, /*!< WAIT mode. */ |
| kMU_PowerModeStop = 0x03U, /*!< STOP mode. */ |
| } mu_power_mode_t; |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- MU Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** MU - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t TR[4]; /**< Processor B Transmit Register 0..Processor B Transmit Register 3, array offset: 0x0, array step: 0x4 */ |
| __I uint32_t RR[4]; /**< Processor B Receive Register 0..Processor B Receive Register 3, array offset: 0x10, array step: 0x4 */ |
| __IO uint32_t SR; /**< Processor B Status Register, offset: 0x20 */ |
| __IO uint32_t CR; /**< Processor B Control Register, offset: 0x24 */ |
| } MU_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- MU Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MU_Register_Masks MU Register Masks |
| * @{ |
| */ |
| |
| /*! @name TR - Processor B Transmit Register 0..Processor B Transmit Register 3 */ |
| /*! @{ */ |
| #define MU_TR_BTR0_MASK (0xFFFFFFFFU) |
| #define MU_TR_BTR0_SHIFT (0U) |
| #define MU_TR_BTR0(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR0_SHIFT)) & MU_TR_BTR0_MASK) |
| #define MU_TR_BTR1_MASK (0xFFFFFFFFU) |
| #define MU_TR_BTR1_SHIFT (0U) |
| #define MU_TR_BTR1(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR1_SHIFT)) & MU_TR_BTR1_MASK) |
| #define MU_TR_BTR2_MASK (0xFFFFFFFFU) |
| #define MU_TR_BTR2_SHIFT (0U) |
| #define MU_TR_BTR2(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK) |
| #define MU_TR_BTR3_MASK (0xFFFFFFFFU) |
| #define MU_TR_BTR3_SHIFT (0U) |
| #define MU_TR_BTR3(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR3_SHIFT)) & MU_TR_BTR3_MASK) |
| /*! @} */ |
| |
| /* The count of MU_TR */ |
| #define MU_TR_COUNT (4U) |
| |
| /*! @name RR - Processor B Receive Register 0..Processor B Receive Register 3 */ |
| /*! @{ */ |
| #define MU_RR_BRR0_MASK (0xFFFFFFFFU) |
| #define MU_RR_BRR0_SHIFT (0U) |
| #define MU_RR_BRR0(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR0_SHIFT)) & MU_RR_BRR0_MASK) |
| #define MU_RR_BRR1_MASK (0xFFFFFFFFU) |
| #define MU_RR_BRR1_SHIFT (0U) |
| #define MU_RR_BRR1(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR1_SHIFT)) & MU_RR_BRR1_MASK) |
| #define MU_RR_BRR2_MASK (0xFFFFFFFFU) |
| #define MU_RR_BRR2_SHIFT (0U) |
| #define MU_RR_BRR2(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR2_SHIFT)) & MU_RR_BRR2_MASK) |
| #define MU_RR_BRR3_MASK (0xFFFFFFFFU) |
| #define MU_RR_BRR3_SHIFT (0U) |
| #define MU_RR_BRR3(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR3_SHIFT)) & MU_RR_BRR3_MASK) |
| /*! @} */ |
| |
| /* The count of MU_RR */ |
| #define MU_RR_COUNT (4U) |
| |
| /*! @name SR - Processor B Status Register */ |
| /*! @{ */ |
| #define MU_SR_Fn_MASK (0x7U) |
| #define MU_SR_Fn_SHIFT (0U) |
| /*! Fn |
| * 0b000..ABFn bit in ACR register is written 0 (default). |
| * 0b001..ABFn bit in ACR register is written 1. |
| */ |
| #define MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK) |
| #define MU_SR_EP_MASK (0x10U) |
| #define MU_SR_EP_SHIFT (4U) |
| /*! EP |
| * 0b0..The Processor B-side event is not pending (default). |
| * 0b1..The Processor B-side event is pending. |
| */ |
| #define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK) |
| #define MU_SR_APM_MASK (0x60U) |
| #define MU_SR_APM_SHIFT (5U) |
| /*! APM |
| * 0b00..The System is in Run Mode. |
| * 0b01..The System is in WAIT Mode. |
| * 0b10..Reserved. |
| * 0b11..The System is in STOP Mode. |
| */ |
| #define MU_SR_APM(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_APM_SHIFT)) & MU_SR_APM_MASK) |
| #define MU_SR_ARS_MASK (0x80U) |
| #define MU_SR_ARS_SHIFT (7U) |
| /*! ARS |
| * 0b0..The Processor A or the Processor A-side of the MU is not in reset. |
| * 0b1..The Processor A or the Processor A-side of the MU is in reset. |
| */ |
| #define MU_SR_ARS(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_ARS_SHIFT)) & MU_SR_ARS_MASK) |
| #define MU_SR_FUP_MASK (0x100U) |
| #define MU_SR_FUP_SHIFT (8U) |
| /*! FUP |
| * 0b0..No flags updated, initiated by the Processor B, in progress (default) |
| * 0b1..Processor B initiated flags update, processing |
| */ |
| #define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK) |
| #define MU_SR_TEn_MASK (0xF00000U) |
| #define MU_SR_TEn_SHIFT (20U) |
| /*! TEn |
| * 0b0000..BTRn register is not empty. |
| * 0b0001..BTRn register is empty (default). |
| */ |
| #define MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK) |
| #define MU_SR_RFn_MASK (0xF000000U) |
| #define MU_SR_RFn_SHIFT (24U) |
| /*! RFn |
| * 0b0000..BRRn register is not full (default). |
| * 0b0001..BRRn register has received data from ATRn register and is ready to be read by the Processor B. |
| */ |
| #define MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK) |
| #define MU_SR_GIPn_MASK (0xF0000000U) |
| #define MU_SR_GIPn_SHIFT (28U) |
| /*! GIPn |
| * 0b0000..Processor B general purpose interrupt n is not pending. (default) |
| * 0b0001..Processor B general purpose interrupt n is pending. |
| */ |
| #define MU_SR_GIPn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK) |
| /*! @} */ |
| |
| /*! @name CR - Processor B Control Register */ |
| /*! @{ */ |
| #define MU_CR_BAFn_MASK (0x7U) |
| #define MU_CR_BAFn_SHIFT (0U) |
| /*! BAFn |
| * 0b000..Clears the Fn bit in the ASR register. |
| * 0b001..Sets the Fn bit in the ASR register. |
| */ |
| #define MU_CR_BAFn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_BAFn_SHIFT)) & MU_CR_BAFn_MASK) |
| #define MU_CR_HRM_MASK (0x10U) |
| #define MU_CR_HRM_SHIFT (4U) |
| /*! HRM |
| * 0b0..BHR bit in ACR is not masked, enables the hardware reset to the Processor B (default after hardware reset). |
| * 0b1..BHR bit in ACR is masked, disables the hardware reset request to the Processor B. |
| */ |
| #define MU_CR_HRM(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_HRM_SHIFT)) & MU_CR_HRM_MASK) |
| #define MU_CR_GIRn_MASK (0xF0000U) |
| #define MU_CR_GIRn_SHIFT (16U) |
| /*! GIRn |
| * 0b0000..Processor B General Interrupt n is not requested to the Processor A (default). |
| * 0b0001..Processor B General Interrupt n is requested to the Processor A. |
| */ |
| #define MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK) |
| #define MU_CR_TIEn_MASK (0xF00000U) |
| #define MU_CR_TIEn_SHIFT (20U) |
| /*! TIEn |
| * 0b0000..Disables Processor B Transmit Interrupt n. (default) |
| * 0b0001..Enables Processor B Transmit Interrupt n. |
| */ |
| #define MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK) |
| #define MU_CR_RIEn_MASK (0xF000000U) |
| #define MU_CR_RIEn_SHIFT (24U) |
| /*! RIEn |
| * 0b0000..Disables Processor B Receive Interrupt n. (default) |
| * 0b0001..Enables Processor B Receive Interrupt n. |
| */ |
| #define MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK) |
| #define MU_CR_GIEn_MASK (0xF0000000U) |
| #define MU_CR_GIEn_SHIFT (28U) |
| /*! GIEn |
| * 0b0000..Disables Processor B General Interrupt n. (default) |
| * 0b0001..Enables Processor B General Interrupt n. |
| */ |
| #define MU_CR_GIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group MU_Register_Masks */ |
| |
| |
| /* MU - Peripheral instance base addresses */ |
| /** Peripheral MUB base address */ |
| #define MUB_BASE (0x30AB0000u) |
| /** Peripheral MUB base pointer */ |
| #define MUB ((MU_Type *)MUB_BASE) |
| /** Array initializer of MU peripheral base addresses */ |
| #define MU_BASE_ADDRS { MUB_BASE } |
| /** Array initializer of MU peripheral base pointers */ |
| #define MU_BASE_PTRS { MUB } |
| /** Interrupt vectors for the MU peripheral type */ |
| #define MU_IRQS { MU_M4_IRQn } |
| /* Backward compatibility */ |
| #define MU_SR_PM_MASK MU_SR_APM_MASK |
| #define MU_SR_PM_SHIFT MU_SR_APM_SHIFT |
| #define MU_SR_PM(x) MU_SR_APM(x) |
| #define MU_SR_RS_MASK MU_SR_ARS_MASK |
| #define MU_SR_RS_SHIFT MU_SR_ARS_SHIFT |
| #define MU_SR_RS(x) MU_SR_ARS(x) |
| #define MU_CR_Fn_MASK MU_CR_BAFn_MASK |
| #define MU_CR_Fn_SHIFT MU_CR_BAFn_SHIFT |
| #define MU_CR_Fn(x) MU_CR_BAFn(x) |
| |
| |
| /*! |
| * @} |
| */ /* end of group MU_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- OCOTP Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** OCOTP - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t CTRL; /**< OTP Controller Control Register, offset: 0x0 */ |
| __IO uint32_t CTRL_SET; /**< OTP Controller Control Register, offset: 0x4 */ |
| __IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8 */ |
| __IO uint32_t CTRL_TOG; /**< OTP Controller Control Register, offset: 0xC */ |
| __IO uint32_t TIMING; /**< OTP Controller Timing Register, offset: 0x10 */ |
| uint8_t RESERVED_0[12]; |
| __IO uint32_t DATA; /**< OTP Controller Write Data Register, offset: 0x20 */ |
| uint8_t RESERVED_1[12]; |
| __IO uint32_t READ_CTRL; /**< OTP Controller Write Data Register, offset: 0x30 */ |
| uint8_t RESERVED_2[12]; |
| __IO uint32_t READ_FUSE_DATA; /**< OTP Controller Read Data Register, offset: 0x40 */ |
| uint8_t RESERVED_3[12]; |
| __IO uint32_t SW_STICKY; /**< Sticky bit Register, offset: 0x50 */ |
| uint8_t RESERVED_4[12]; |
| __IO uint32_t SCS; /**< Software Controllable Signals Register, offset: 0x60 */ |
| __IO uint32_t SCS_SET; /**< Software Controllable Signals Register, offset: 0x64 */ |
| __IO uint32_t SCS_CLR; /**< Software Controllable Signals Register, offset: 0x68 */ |
| __IO uint32_t SCS_TOG; /**< Software Controllable Signals Register, offset: 0x6C */ |
| uint8_t RESERVED_5[32]; |
| __I uint32_t VERSION; /**< OTP Controller Version Register, offset: 0x90 */ |
| uint8_t RESERVED_6[876]; |
| __I uint32_t LOCK; /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */ |
| uint8_t RESERVED_7[12]; |
| __IO uint32_t TESTER0; /**< Value of OTP Bank0 Word1 (Tester Info.), offset: 0x410 */ |
| uint8_t RESERVED_8[12]; |
| __IO uint32_t TESTER1; /**< Value of OTP Bank0 Word2 (tester Info.), offset: 0x420 */ |
| uint8_t RESERVED_9[12]; |
| __IO uint32_t TESTER2; /**< Value of OTP Bank0 Word3 (Tester Info.), offset: 0x430 */ |
| uint8_t RESERVED_10[12]; |
| __IO uint32_t TESTER3; /**< Value of OTP Bank1 Word0 (Tester Info.), offset: 0x440 */ |
| uint8_t RESERVED_11[12]; |
| __IO uint32_t TESTER4; /**< Value of OTP Bank1 Word1 (Tester Info.), offset: 0x450 */ |
| uint8_t RESERVED_12[12]; |
| __IO uint32_t TESTER5; /**< Value of OTP Bank1 Word2 (Tester Info.), offset: 0x460 */ |
| uint8_t RESERVED_13[12]; |
| __IO uint32_t BOOT_CFG0; /**< Value of OTP Bank1 Word3 (Boot Configuration Info.), offset: 0x470 */ |
| uint8_t RESERVED_14[12]; |
| __IO uint32_t BOOT_CFG1; /**< Value of OTP Bank2 Word0 (Boot Configuration Info.), offset: 0x480 */ |
| uint8_t RESERVED_15[12]; |
| __IO uint32_t BOOT_CFG2; /**< Value of OTP Bank2 Word1 (Boot Configuration Info.), offset: 0x490 */ |
| uint8_t RESERVED_16[12]; |
| __IO uint32_t BOOT_CFG3; /**< Value of OTP Bank2 Word2 (Boot Configuration Info.), offset: 0x4A0 */ |
| uint8_t RESERVED_17[12]; |
| __IO uint32_t BOOT_CFG4; /**< Value of OTP Bank2 Word3 (BOOT Configuration Info.), offset: 0x4B0 */ |
| uint8_t RESERVED_18[12]; |
| __IO uint32_t MEM_TRIM0; /**< Value of OTP Bank3 Word0 (Memory Related Info.), offset: 0x4C0 */ |
| uint8_t RESERVED_19[12]; |
| __IO uint32_t MEM_TRIM1; /**< Value of OTP Bank3 Word1 (Memory Related Info.), offset: 0x4D0 */ |
| uint8_t RESERVED_20[12]; |
| __IO uint32_t ANA0; /**< Value of OTP Bank3 Word2 (Analog Info.), offset: 0x4E0 */ |
| uint8_t RESERVED_21[12]; |
| __IO uint32_t ANA1; /**< Value of OTP Bank3 Word3 (Analog Info.), offset: 0x4F0 */ |
| uint8_t RESERVED_22[140]; |
| __IO uint32_t SRK0; /**< Shadow Register for OTP Bank6 Word0 (SRK Hash), offset: 0x580 */ |
| uint8_t RESERVED_23[12]; |
| __IO uint32_t SRK1; /**< Shadow Register for OTP Bank6 Word1 (SRK Hash), offset: 0x590 */ |
| uint8_t RESERVED_24[12]; |
| __IO uint32_t SRK2; /**< Shadow Register for OTP Bank6 Word2 (SRK Hash), offset: 0x5A0 */ |
| uint8_t RESERVED_25[12]; |
| __IO uint32_t SRK3; /**< Shadow Register for OTP Bank6 Word3 (SRK Hash), offset: 0x5B0 */ |
| uint8_t RESERVED_26[12]; |
| __IO uint32_t SRK4; /**< Shadow Register for OTP Bank7 Word0 (SRK Hash), offset: 0x5C0 */ |
| uint8_t RESERVED_27[12]; |
| __IO uint32_t SRK5; /**< Shadow Register for OTP Bank7 Word1 (SRK Hash), offset: 0x5D0 */ |
| uint8_t RESERVED_28[12]; |
| __IO uint32_t SRK6; /**< Shadow Register for OTP Bank7 Word2 (SRK Hash), offset: 0x5E0 */ |
| uint8_t RESERVED_29[12]; |
| __IO uint32_t SRK7; /**< Shadow Register for OTP Bank7 Word3 (SRK Hash), offset: 0x5F0 */ |
| uint8_t RESERVED_30[12]; |
| __IO uint32_t SJC_RESP0; /**< Value of OTP Bank8 Word0 (Secure JTAG Response Field), offset: 0x600 */ |
| uint8_t RESERVED_31[12]; |
| __IO uint32_t SJC_RESP1; /**< Value of OTP Bank8 Word1 (Secure JTAG Response Field), offset: 0x610 */ |
| uint8_t RESERVED_32[12]; |
| __IO uint32_t USB_ID; /**< Value of OTP Bank8 Word2 (USB ID info), offset: 0x620 */ |
| uint8_t RESERVED_33[12]; |
| __IO uint32_t FIELD_RETURN; /**< Value of OTP Bank5 Word6 (Field Return), offset: 0x630 */ |
| uint8_t RESERVED_34[12]; |
| __IO uint32_t MAC_ADDR0; /**< Value of OTP Bank9 Word0 (MAC Address), offset: 0x640 */ |
| uint8_t RESERVED_35[12]; |
| __IO uint32_t MAC_ADDR1; /**< Value of OTP Bank9 Word1 (MAC Address), offset: 0x650 */ |
| uint8_t RESERVED_36[12]; |
| __IO uint32_t MAC_ADDR2; /**< Value of OTP Bank9 Word2 (MAC Address), offset: 0x660 */ |
| uint8_t RESERVED_37[12]; |
| __IO uint32_t SRK_REVOKE; /**< Value of OTP Bank9 Word3 (SRK Revoke), offset: 0x670 */ |
| uint8_t RESERVED_38[12]; |
| __IO uint32_t MAU_KEY0; /**< Shadow Register for OTP Bank10 Word0 (MAU Key), offset: 0x680 */ |
| uint8_t RESERVED_39[12]; |
| __IO uint32_t MAU_KEY1; /**< Shadow Register for OTP Bank10 Word1 (MAU Key), offset: 0x690 */ |
| uint8_t RESERVED_40[12]; |
| __IO uint32_t MAU_KEY2; /**< Shadow Register for OTP Bank10 Word2 (MAU Key), offset: 0x6A0 */ |
| uint8_t RESERVED_41[12]; |
| __IO uint32_t MAU_KEY3; /**< Shadow Register for OTP Bank10 Word3 (MAU Key), offset: 0x6B0 */ |
| uint8_t RESERVED_42[12]; |
| __IO uint32_t MAU_KEY4; /**< Shadow Register for OTP Bank11 Word0 (MAU Key), offset: 0x6C0 */ |
| uint8_t RESERVED_43[12]; |
| __IO uint32_t MAU_KEY5; /**< Shadow Register for OTP Bank11 Word1 (MAU Key), offset: 0x6D0 */ |
| uint8_t RESERVED_44[12]; |
| __IO uint32_t MAU_KEY6; /**< Shadow Register for OTP Bank11 Word2 (MAU Key), offset: 0x6E0 */ |
| uint8_t RESERVED_45[12]; |
| __IO uint32_t MAU_KEY7; /**< Shadow Register for OTP Bank11 Word3 (MAU Key), offset: 0x6F0 */ |
| uint8_t RESERVED_46[140]; |
| __IO uint32_t GP10; /**< Value of OTP Bank14 Word0 (), offset: 0x780 */ |
| uint8_t RESERVED_47[12]; |
| __IO uint32_t GP11; /**< Value of OTP Bank14 Word1 (), offset: 0x790 */ |
| uint8_t RESERVED_48[12]; |
| __IO uint32_t GP20; /**< Value of OTP Bank14 Word2 (), offset: 0x7A0 */ |
| uint8_t RESERVED_49[12]; |
| __IO uint32_t GP21; /**< Value of OTP Bank14 Word3 (), offset: 0x7B0 */ |
| uint8_t RESERVED_50[12]; |
| __IO uint32_t GP_CRC0; /**< Value of OTP Bank15 Word0 (CRC Key), offset: 0x7C0 */ |
| uint8_t RESERVED_51[12]; |
| __IO uint32_t GP_CRC1; /**< Value of OTP Bank15 Word1 (CRC Key), offset: 0x7D0 */ |
| uint8_t RESERVED_52[12]; |
| __IO uint32_t GP_CRC2; /**< Value of OTP Bank15 Word2 (CRC Key), offset: 0x7E0 */ |
| uint8_t RESERVED_53[12]; |
| __IO uint32_t GROUP_MASK; /**< Value of OTP Bank15 Word3 (CRC Key), offset: 0x7F0 */ |
| uint8_t RESERVED_54[12]; |
| __IO uint32_t HDMI_FW_SRK0; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x800 */ |
| uint8_t RESERVED_55[12]; |
| __IO uint32_t HDMI_FW_SRK1; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0x810 */ |
| uint8_t RESERVED_56[12]; |
| __IO uint32_t HDMI_FW_SRK2; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x820 */ |
| uint8_t RESERVED_57[12]; |
| __IO uint32_t HDMI_FW_SRK3; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x830 */ |
| uint8_t RESERVED_58[12]; |
| __IO uint32_t HDMI_FW_SRK4; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x840 */ |
| uint8_t RESERVED_59[12]; |
| __IO uint32_t HDMI_FW_SRK5; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x850 */ |
| uint8_t RESERVED_60[12]; |
| __IO uint32_t HDMI_FW_SRK6; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x860 */ |
| uint8_t RESERVED_61[12]; |
| __IO uint32_t HDMI_FW_SRK7; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x870 */ |
| uint8_t RESERVED_62[12]; |
| __IO uint32_t HDMI_KMEK0; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x880 */ |
| uint8_t RESERVED_63[12]; |
| __IO uint32_t HDMI_KMEK1; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x890 */ |
| uint8_t RESERVED_64[12]; |
| __IO uint32_t HDMI_KMEK2; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x8A0 */ |
| uint8_t RESERVED_65[12]; |
| __IO uint32_t HDMI_KMEK3; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x8B0 */ |
| uint8_t RESERVED_66[76]; |
| __IO uint32_t HDCP_TX_CONS0; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x900 */ |
| uint8_t RESERVED_67[12]; |
| __IO uint32_t HDCP_TX_CONS1; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0x910 */ |
| uint8_t RESERVED_68[12]; |
| __IO uint32_t HDCP_TX_CONS2; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x920 */ |
| uint8_t RESERVED_69[12]; |
| __IO uint32_t HDCP_TX_CONS3; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x930 */ |
| uint8_t RESERVED_70[12]; |
| __IO uint32_t HDCP_TX_CERT0; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x940 */ |
| uint8_t RESERVED_71[12]; |
| __IO uint32_t HDCP_TX_CERT1; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x950 */ |
| uint8_t RESERVED_72[12]; |
| __IO uint32_t HDCP_TX_CERT2; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x960 */ |
| uint8_t RESERVED_73[12]; |
| __IO uint32_t HDCP_TX_CERT3; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x970 */ |
| uint8_t RESERVED_74[12]; |
| __IO uint32_t HDCP_TX_CERT4; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x980 */ |
| uint8_t RESERVED_75[12]; |
| __IO uint32_t HDCP_TX_CERT5; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x990 */ |
| uint8_t RESERVED_76[12]; |
| __IO uint32_t HDCP_TX_CERT6; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x9A0 */ |
| uint8_t RESERVED_77[12]; |
| __IO uint32_t HDCP_TX_CERT7; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x9B0 */ |
| uint8_t RESERVED_78[12]; |
| __IO uint32_t HDCP_TX_CERT8; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x9C0 */ |
| uint8_t RESERVED_79[12]; |
| __IO uint32_t HDCP_TX_CERT9; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x9D0 */ |
| uint8_t RESERVED_80[12]; |
| __IO uint32_t HDCP_TX_CERT10; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x9E0 */ |
| uint8_t RESERVED_81[12]; |
| __IO uint32_t HDCP_TX_CERT11; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x9F0 */ |
| uint8_t RESERVED_82[12]; |
| __IO uint32_t HDCP_TX_CERT12; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xA00 */ |
| uint8_t RESERVED_83[12]; |
| __IO uint32_t HDCP_TX_CERT13; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0xA10 */ |
| uint8_t RESERVED_84[12]; |
| __IO uint32_t HDCP_TX_CERT14; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xA20 */ |
| uint8_t RESERVED_85[12]; |
| __IO uint32_t HDCP_TX_CERT15; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xA30 */ |
| uint8_t RESERVED_86[12]; |
| __IO uint32_t HDCP_TX_CERT16; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xA40 */ |
| uint8_t RESERVED_87[12]; |
| __IO uint32_t HDCP_TX_CERT17; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xA50 */ |
| uint8_t RESERVED_88[12]; |
| __IO uint32_t HDCP_TX_CERT18; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xA60 */ |
| uint8_t RESERVED_89[12]; |
| __IO uint32_t HDCP_TX_CERT19; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xA70 */ |
| uint8_t RESERVED_90[12]; |
| __IO uint32_t HDCP_TX_CERT20; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xA80 */ |
| uint8_t RESERVED_91[12]; |
| __IO uint32_t HDCP_TX_CERT21; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xA90 */ |
| uint8_t RESERVED_92[12]; |
| __IO uint32_t HDCP_TX_CERT22; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xAA0 */ |
| uint8_t RESERVED_93[12]; |
| __IO uint32_t HDCP_TX_CERT23; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xAB0 */ |
| uint8_t RESERVED_94[12]; |
| __IO uint32_t HDCP_TX_CERT24; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xAC0 */ |
| uint8_t RESERVED_95[12]; |
| __IO uint32_t HDCP_TX_CERT25; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xAD0 */ |
| uint8_t RESERVED_96[12]; |
| __IO uint32_t HDCP_TX_CERT26; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xAE0 */ |
| uint8_t RESERVED_97[12]; |
| __IO uint32_t HDCP_TX_CERT27; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xAF0 */ |
| uint8_t RESERVED_98[12]; |
| __IO uint32_t HDCP_TX_CERT28; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xB00 */ |
| uint8_t RESERVED_99[12]; |
| __IO uint32_t HDCP_TX_CERT29; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0xB10 */ |
| uint8_t RESERVED_100[12]; |
| __IO uint32_t HDCP_TX_CERT30; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xB20 */ |
| uint8_t RESERVED_101[12]; |
| __IO uint32_t HDCP_TX_CERT31; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xB30 */ |
| uint8_t RESERVED_102[12]; |
| __IO uint32_t HDCP_TX_CERT32; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xB40 */ |
| uint8_t RESERVED_103[12]; |
| __IO uint32_t HDCP_TX_CERT33; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xB50 */ |
| uint8_t RESERVED_104[12]; |
| __IO uint32_t HDCP_TX_CERT34; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xB60 */ |
| uint8_t RESERVED_105[12]; |
| __IO uint32_t HDCP_TX_CERT35; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xB70 */ |
| uint8_t RESERVED_106[12]; |
| __IO uint32_t HDCP_TX_CERT36; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xB80 */ |
| uint8_t RESERVED_107[12]; |
| __IO uint32_t HDCP_TX_CERT37; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xB90 */ |
| uint8_t RESERVED_108[12]; |
| __IO uint32_t HDCP_TX_CERT38; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xBA0 */ |
| uint8_t RESERVED_109[12]; |
| __IO uint32_t HDCP_TX_CERT39; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xBB0 */ |
| uint8_t RESERVED_110[12]; |
| __IO uint32_t HDCP_TX_CERT40; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xBC0 */ |
| uint8_t RESERVED_111[12]; |
| __IO uint32_t HDCP_TX_CERT41; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xBD0 */ |
| uint8_t RESERVED_112[12]; |
| __IO uint32_t HDCP_TX_CERT42; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xBE0 */ |
| uint8_t RESERVED_113[12]; |
| __IO uint32_t HDCP_TX_CERT43; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xBF0 */ |
| uint8_t RESERVED_114[12]; |
| __IO uint32_t HDCP_TX_CERT44; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xC00 */ |
| uint8_t RESERVED_115[12]; |
| __IO uint32_t HDCP_TX_CERT45; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0xC10 */ |
| uint8_t RESERVED_116[12]; |
| __IO uint32_t HDCP_TX_CERT46; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xC20 */ |
| uint8_t RESERVED_117[12]; |
| __IO uint32_t HDCP_TX_CERT47; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xC30 */ |
| uint8_t RESERVED_118[12]; |
| __IO uint32_t HDCP_TX_CERT48; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xC40 */ |
| uint8_t RESERVED_119[12]; |
| __IO uint32_t HDCP_TX_CERT49; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xC50 */ |
| uint8_t RESERVED_120[12]; |
| __IO uint32_t HDCP_TX_CERT50; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xC60 */ |
| uint8_t RESERVED_121[12]; |
| __IO uint32_t HDCP_TX_CERT51; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xC70 */ |
| uint8_t RESERVED_122[12]; |
| __IO uint32_t HDCP_TX_CERT52; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xC80 */ |
| uint8_t RESERVED_123[12]; |
| __IO uint32_t HDCP_TX_CERT53; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xC90 */ |
| uint8_t RESERVED_124[12]; |
| __IO uint32_t HDCP_TX_CERT54; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xCA0 */ |
| uint8_t RESERVED_125[12]; |
| __IO uint32_t HDCP_TX_CERT55; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xCB0 */ |
| uint8_t RESERVED_126[12]; |
| __IO uint32_t HDCP_TX_CERT56; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xCC0 */ |
| uint8_t RESERVED_127[12]; |
| __IO uint32_t HDCP_TX_CERT57; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xCD0 */ |
| uint8_t RESERVED_128[12]; |
| __IO uint32_t HDCP_TX_CERT58; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xCE0 */ |
| uint8_t RESERVED_129[12]; |
| __IO uint32_t HDCP_TX_CERT59; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xCF0 */ |
| uint8_t RESERVED_130[12]; |
| __IO uint32_t HDCP_TX_CERT60; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xD00 */ |
| uint8_t RESERVED_131[12]; |
| __IO uint32_t HDCP_TX_CERT61; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0xD10 */ |
| uint8_t RESERVED_132[12]; |
| __IO uint32_t HDCP_TX_CERT62; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xD20 */ |
| uint8_t RESERVED_133[12]; |
| __IO uint32_t HDCP_TX_CERT63; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xD30 */ |
| uint8_t RESERVED_134[12]; |
| __IO uint32_t HDCP_TX_CERT64; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xD40 */ |
| uint8_t RESERVED_135[12]; |
| __IO uint32_t HDCP_TX_CERT65; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xD50 */ |
| uint8_t RESERVED_136[12]; |
| __IO uint32_t HDCP_TX_CERT66; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xD60 */ |
| uint8_t RESERVED_137[12]; |
| __IO uint32_t HDCP_TX_CERT67; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xD70 */ |
| uint8_t RESERVED_138[12]; |
| __IO uint32_t HDCP_TX_CERT68; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xD80 */ |
| uint8_t RESERVED_139[12]; |
| __IO uint32_t HDCP_TX_CERT69; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xD90 */ |
| uint8_t RESERVED_140[12]; |
| __IO uint32_t HDCP_TX_CERT70; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xDA0 */ |
| uint8_t RESERVED_141[12]; |
| __IO uint32_t HDCP_TX_CERT71; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xDB0 */ |
| uint8_t RESERVED_142[12]; |
| __IO uint32_t HDCP_TX_CERT72; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xDC0 */ |
| uint8_t RESERVED_143[12]; |
| __IO uint32_t HDCP_TX_CERT73; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xDD0 */ |
| uint8_t RESERVED_144[12]; |
| __IO uint32_t HDCP_TX_CERT74; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xDE0 */ |
| uint8_t RESERVED_145[12]; |
| __IO uint32_t HDCP_TX_CERT75; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xDF0 */ |
| uint8_t RESERVED_146[12]; |
| __IO uint32_t HDCP_TX_CERT76; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xE00 */ |
| uint8_t RESERVED_147[12]; |
| __IO uint32_t HDCP_TX_CERT77; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0xE10 */ |
| uint8_t RESERVED_148[12]; |
| __IO uint32_t HDCP_TX_CERT78; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xE20 */ |
| uint8_t RESERVED_149[12]; |
| __IO uint32_t HDCP_TX_CERT79; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xE30 */ |
| uint8_t RESERVED_150[12]; |
| __IO uint32_t HDCP_TX_CERT80; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xE40 */ |
| uint8_t RESERVED_151[12]; |
| __IO uint32_t HDCP_TX_CERT81; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xE50 */ |
| uint8_t RESERVED_152[12]; |
| __IO uint32_t HDCP_TX_CERT82; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xE60 */ |
| uint8_t RESERVED_153[12]; |
| __IO uint32_t HDCP_TX_CERT83; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xE70 */ |
| uint8_t RESERVED_154[12]; |
| __IO uint32_t HDCP_TX_CERT84; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xE80 */ |
| uint8_t RESERVED_155[12]; |
| __IO uint32_t HDCP_TX_CERT85; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xE90 */ |
| uint8_t RESERVED_156[12]; |
| __IO uint32_t HDCP_TX_CERT86; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xEA0 */ |
| uint8_t RESERVED_157[12]; |
| __IO uint32_t HDCP_TX_CERT87; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xEB0 */ |
| uint8_t RESERVED_158[12]; |
| __IO uint32_t HDCP_TX_CERT88; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xEC0 */ |
| uint8_t RESERVED_159[12]; |
| __IO uint32_t HDCP_TX_CERT89; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xED0 */ |
| uint8_t RESERVED_160[12]; |
| __IO uint32_t HDCP_TX_CERT90; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xEE0 */ |
| uint8_t RESERVED_161[12]; |
| __IO uint32_t HDCP_TX_CERT91; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xEF0 */ |
| uint8_t RESERVED_162[12]; |
| __IO uint32_t HDCP_TX_CERT92; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xF00 */ |
| uint8_t RESERVED_163[12]; |
| __IO uint32_t HDCP_TX_CERT93; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0xF10 */ |
| uint8_t RESERVED_164[12]; |
| __IO uint32_t HDCP_TX_CERT94; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xF20 */ |
| uint8_t RESERVED_165[12]; |
| __IO uint32_t HDCP_TX_CERT95; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xF30 */ |
| uint8_t RESERVED_166[12]; |
| __IO uint32_t HDCP_KEY0; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xF40 */ |
| uint8_t RESERVED_167[12]; |
| __IO uint32_t HDCP_KEY1; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xF50 */ |
| uint8_t RESERVED_168[12]; |
| __IO uint32_t HDCP_KEY2; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xF60 */ |
| uint8_t RESERVED_169[12]; |
| __IO uint32_t HDCP_KEY3; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xF70 */ |
| uint8_t RESERVED_170[12]; |
| __IO uint32_t HDCP_KEY4; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xF80 */ |
| uint8_t RESERVED_171[12]; |
| __IO uint32_t HDCP_KEY5; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xF90 */ |
| uint8_t RESERVED_172[12]; |
| __IO uint32_t HDCP_KEY6; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xFA0 */ |
| uint8_t RESERVED_173[12]; |
| __IO uint32_t HDCP_KEY7; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xFB0 */ |
| uint8_t RESERVED_174[12]; |
| __IO uint32_t HDCP_KEY8; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0xFC0 */ |
| uint8_t RESERVED_175[12]; |
| __IO uint32_t HDCP_KEY9; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0xFD0 */ |
| uint8_t RESERVED_176[12]; |
| __IO uint32_t HDCP_KEY10; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xFE0 */ |
| uint8_t RESERVED_177[12]; |
| __IO uint32_t HDCP_KEY11; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0xFF0 */ |
| uint8_t RESERVED_178[12]; |
| __IO uint32_t HDCP_KEY12; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1000 */ |
| uint8_t RESERVED_179[12]; |
| __IO uint32_t HDCP_KEY13; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0x1010 */ |
| uint8_t RESERVED_180[12]; |
| __IO uint32_t HDCP_KEY14; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1020 */ |
| uint8_t RESERVED_181[12]; |
| __IO uint32_t HDCP_KEY15; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1030 */ |
| uint8_t RESERVED_182[12]; |
| __IO uint32_t HDCP_KEY16; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x1040 */ |
| uint8_t RESERVED_183[12]; |
| __IO uint32_t HDCP_KEY17; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x1050 */ |
| uint8_t RESERVED_184[12]; |
| __IO uint32_t HDCP_KEY18; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1060 */ |
| uint8_t RESERVED_185[12]; |
| __IO uint32_t HDCP_KEY19; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1070 */ |
| uint8_t RESERVED_186[12]; |
| __IO uint32_t HDCP_KEY20; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1080 */ |
| uint8_t RESERVED_187[12]; |
| __IO uint32_t HDCP_KEY21; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1090 */ |
| uint8_t RESERVED_188[12]; |
| __IO uint32_t HDCP_KEY22; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x10A0 */ |
| uint8_t RESERVED_189[12]; |
| __IO uint32_t HDCP_KEY23; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x10B0 */ |
| uint8_t RESERVED_190[12]; |
| __IO uint32_t HDCP_KEY24; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x10C0 */ |
| uint8_t RESERVED_191[12]; |
| __IO uint32_t HDCP_KEY25; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x10D0 */ |
| uint8_t RESERVED_192[12]; |
| __IO uint32_t HDCP_KEY26; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x10E0 */ |
| uint8_t RESERVED_193[12]; |
| __IO uint32_t HDCP_KEY27; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x10F0 */ |
| uint8_t RESERVED_194[12]; |
| __IO uint32_t HDCP_KEY28; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1100 */ |
| uint8_t RESERVED_195[12]; |
| __IO uint32_t HDCP_KEY29; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0x1110 */ |
| uint8_t RESERVED_196[12]; |
| __IO uint32_t HDCP_KEY30; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1120 */ |
| uint8_t RESERVED_197[12]; |
| __IO uint32_t HDCP_KEY31; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1130 */ |
| uint8_t RESERVED_198[12]; |
| __IO uint32_t HDCP_KEY32; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x1140 */ |
| uint8_t RESERVED_199[12]; |
| __IO uint32_t HDCP_KEY33; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x1150 */ |
| uint8_t RESERVED_200[12]; |
| __IO uint32_t HDCP_KEY34; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1160 */ |
| uint8_t RESERVED_201[12]; |
| __IO uint32_t HDCP_KEY35; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1170 */ |
| uint8_t RESERVED_202[12]; |
| __IO uint32_t HDCP_KEY36; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1180 */ |
| uint8_t RESERVED_203[12]; |
| __IO uint32_t HDCP_KEY37; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1190 */ |
| uint8_t RESERVED_204[12]; |
| __IO uint32_t HDCP_KEY38; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x11A0 */ |
| uint8_t RESERVED_205[12]; |
| __IO uint32_t HDCP_KEY39; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x11B0 */ |
| uint8_t RESERVED_206[12]; |
| __IO uint32_t HDCP_KEY40; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x11C0 */ |
| uint8_t RESERVED_207[12]; |
| __IO uint32_t HDCP_KEY41; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x11D0 */ |
| uint8_t RESERVED_208[12]; |
| __IO uint32_t HDCP_KEY42; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x11E0 */ |
| uint8_t RESERVED_209[12]; |
| __IO uint32_t HDCP_KEY43; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x11F0 */ |
| uint8_t RESERVED_210[12]; |
| __IO uint32_t HDCP_KEY44; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1200 */ |
| uint8_t RESERVED_211[12]; |
| __IO uint32_t HDCP_KEY45; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0x1210 */ |
| uint8_t RESERVED_212[12]; |
| __IO uint32_t HDCP_KEY46; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1220 */ |
| uint8_t RESERVED_213[12]; |
| __IO uint32_t HDCP_KEY47; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1230 */ |
| uint8_t RESERVED_214[12]; |
| __IO uint32_t HDCP_KEY48; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x1240 */ |
| uint8_t RESERVED_215[12]; |
| __IO uint32_t HDCP_KEY49; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x1250 */ |
| uint8_t RESERVED_216[12]; |
| __IO uint32_t HDCP_KEY50; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1260 */ |
| uint8_t RESERVED_217[12]; |
| __IO uint32_t HDCP_KEY51; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1270 */ |
| uint8_t RESERVED_218[12]; |
| __IO uint32_t HDCP_KEY52; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1280 */ |
| uint8_t RESERVED_219[12]; |
| __IO uint32_t HDCP_KEY53; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1290 */ |
| uint8_t RESERVED_220[12]; |
| __IO uint32_t HDCP_KEY54; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x12A0 */ |
| uint8_t RESERVED_221[12]; |
| __IO uint32_t HDCP_KEY55; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x12B0 */ |
| uint8_t RESERVED_222[12]; |
| __IO uint32_t HDCP_KEY56; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x12C0 */ |
| uint8_t RESERVED_223[12]; |
| __IO uint32_t HDCP_KEY57; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x12D0 */ |
| uint8_t RESERVED_224[12]; |
| __IO uint32_t HDCP_KEY58; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x12E0 */ |
| uint8_t RESERVED_225[12]; |
| __IO uint32_t HDCP_KEY59; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x12F0 */ |
| uint8_t RESERVED_226[12]; |
| __IO uint32_t HDCP_KEY60; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1300 */ |
| uint8_t RESERVED_227[12]; |
| __IO uint32_t HDCP_KEY61; /**< Value of OTP Bank16 Word1 (HDCP Key), offset: 0x1310 */ |
| uint8_t RESERVED_228[12]; |
| __IO uint32_t HDCP_KEY62; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1320 */ |
| uint8_t RESERVED_229[12]; |
| __IO uint32_t HDCP_KEY63; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1330 */ |
| uint8_t RESERVED_230[12]; |
| __IO uint32_t HDCP_KEY64; /**< Value of OTP Bank17 Word0 (HDCP Key), offset: 0x1340 */ |
| uint8_t RESERVED_231[12]; |
| __IO uint32_t HDCP_KEY65; /**< Value of OTP Bank17 Word1 (HDCP Key), offset: 0x1350 */ |
| uint8_t RESERVED_232[12]; |
| __IO uint32_t HDCP_KEY66; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1360 */ |
| uint8_t RESERVED_233[12]; |
| __IO uint32_t HDCP_KEY67; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1370 */ |
| uint8_t RESERVED_234[12]; |
| __IO uint32_t HDCP_KEY68; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1380 */ |
| uint8_t RESERVED_235[12]; |
| __IO uint32_t HDCP_KEY69; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x1390 */ |
| uint8_t RESERVED_236[12]; |
| __IO uint32_t HDCP_KEY70; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x13A0 */ |
| uint8_t RESERVED_237[12]; |
| __IO uint32_t HDCP_KEY71; /**< Value of OTP Bank16 Word0 (HDCP Key), offset: 0x13B0 */ |
| } OCOTP_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- OCOTP Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup OCOTP_Register_Masks OCOTP Register Masks |
| * @{ |
| */ |
| |
| /*! @name CTRL - OTP Controller Control Register */ |
| /*! @{ */ |
| #define OCOTP_CTRL_ADDR_MASK (0xFFU) |
| #define OCOTP_CTRL_ADDR_SHIFT (0U) |
| #define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK) |
| #define OCOTP_CTRL_BUSY_MASK (0x100U) |
| #define OCOTP_CTRL_BUSY_SHIFT (8U) |
| #define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK) |
| #define OCOTP_CTRL_ERROR_MASK (0x200U) |
| #define OCOTP_CTRL_ERROR_SHIFT (9U) |
| #define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK) |
| #define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U) |
| #define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U) |
| #define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK) |
| #define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U) |
| #define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U) |
| #define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL_SET - OTP Controller Control Register */ |
| /*! @{ */ |
| #define OCOTP_CTRL_SET_ADDR_MASK (0xFFU) |
| #define OCOTP_CTRL_SET_ADDR_SHIFT (0U) |
| #define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK) |
| #define OCOTP_CTRL_SET_BUSY_MASK (0x100U) |
| #define OCOTP_CTRL_SET_BUSY_SHIFT (8U) |
| #define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK) |
| #define OCOTP_CTRL_SET_ERROR_MASK (0x200U) |
| #define OCOTP_CTRL_SET_ERROR_SHIFT (9U) |
| #define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK) |
| #define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U) |
| #define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U) |
| #define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK) |
| #define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U) |
| #define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U) |
| #define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL_CLR - OTP Controller Control Register */ |
| /*! @{ */ |
| #define OCOTP_CTRL_CLR_ADDR_MASK (0xFFU) |
| #define OCOTP_CTRL_CLR_ADDR_SHIFT (0U) |
| #define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK) |
| #define OCOTP_CTRL_CLR_BUSY_MASK (0x100U) |
| #define OCOTP_CTRL_CLR_BUSY_SHIFT (8U) |
| #define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK) |
| #define OCOTP_CTRL_CLR_ERROR_MASK (0x200U) |
| #define OCOTP_CTRL_CLR_ERROR_SHIFT (9U) |
| #define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK) |
| #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U) |
| #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U) |
| #define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK) |
| #define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U) |
| #define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U) |
| #define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK) |
| /*! @} */ |
| |
| /*! @name CTRL_TOG - OTP Controller Control Register */ |
| /*! @{ */ |
| #define OCOTP_CTRL_TOG_ADDR_MASK (0xFFU) |
| #define OCOTP_CTRL_TOG_ADDR_SHIFT (0U) |
| #define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK) |
| #define OCOTP_CTRL_TOG_BUSY_MASK (0x100U) |
| #define OCOTP_CTRL_TOG_BUSY_SHIFT (8U) |
| #define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK) |
| #define OCOTP_CTRL_TOG_ERROR_MASK (0x200U) |
| #define OCOTP_CTRL_TOG_ERROR_SHIFT (9U) |
| #define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK) |
| #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U) |
| #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U) |
| #define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK) |
| #define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U) |
| #define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U) |
| #define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK) |
| /*! @} */ |
| |
| /*! @name TIMING - OTP Controller Timing Register */ |
| /*! @{ */ |
| #define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU) |
| #define OCOTP_TIMING_STROBE_PROG_SHIFT (0U) |
| #define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK) |
| #define OCOTP_TIMING_RELAX_MASK (0xF000U) |
| #define OCOTP_TIMING_RELAX_SHIFT (12U) |
| #define OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK) |
| #define OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U) |
| #define OCOTP_TIMING_STROBE_READ_SHIFT (16U) |
| #define OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK) |
| #define OCOTP_TIMING_WAIT_MASK (0xFC00000U) |
| #define OCOTP_TIMING_WAIT_SHIFT (22U) |
| #define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK) |
| #define OCOTP_TIMING_RSRVD0_MASK (0xF0000000U) |
| #define OCOTP_TIMING_RSRVD0_SHIFT (28U) |
| #define OCOTP_TIMING_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RSRVD0_SHIFT)) & OCOTP_TIMING_RSRVD0_MASK) |
| /*! @} */ |
| |
| /*! @name DATA - OTP Controller Write Data Register */ |
| /*! @{ */ |
| #define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU) |
| #define OCOTP_DATA_DATA_SHIFT (0U) |
| #define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK) |
| /*! @} */ |
| |
| /*! @name READ_CTRL - OTP Controller Write Data Register */ |
| /*! @{ */ |
| #define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U) |
| #define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U) |
| #define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK) |
| #define OCOTP_READ_CTRL_RSVD0_MASK (0xFFFFFFFEU) |
| #define OCOTP_READ_CTRL_RSVD0_SHIFT (1U) |
| #define OCOTP_READ_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_RSVD0_SHIFT)) & OCOTP_READ_CTRL_RSVD0_MASK) |
| /*! @} */ |
| |
| /*! @name READ_FUSE_DATA - OTP Controller Read Data Register */ |
| /*! @{ */ |
| #define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU) |
| #define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U) |
| #define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK) |
| /*! @} */ |
| |
| /*! @name SW_STICKY - Sticky bit Register */ |
| /*! @{ */ |
| #define OCOTP_SW_STICKY_RSVD0_MASK (0x1U) |
| #define OCOTP_SW_STICKY_RSVD0_SHIFT (0U) |
| #define OCOTP_SW_STICKY_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_RSVD0_SHIFT)) & OCOTP_SW_STICKY_RSVD0_MASK) |
| #define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U) |
| #define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U) |
| #define OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK) |
| #define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U) |
| #define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U) |
| #define OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK) |
| #define OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK (0x8U) |
| #define OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT (3U) |
| #define OCOTP_SW_STICKY_BLOCK_ROM_PART(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT)) & OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK) |
| #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U) |
| #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U) |
| #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK) |
| #define OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK_MASK (0x20U) |
| #define OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK_SHIFT (5U) |
| #define OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK_SHIFT)) & OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK_MASK) |
| #define OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK_MASK (0x40U) |
| #define OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK_SHIFT (6U) |
| #define OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK_SHIFT)) & OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK_MASK) |
| #define OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK_MASK (0x80U) |
| #define OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK_SHIFT (7U) |
| #define OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK_SHIFT)) & OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK_MASK) |
| #define OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT_MASK (0x100U) |
| #define OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT_SHIFT (8U) |
| #define OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT_SHIFT)) & OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT_MASK) |
| #define OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT_MASK (0x200U) |
| #define OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT_SHIFT (9U) |
| #define OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT_SHIFT)) & OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT_MASK) |
| #define OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY_MASK (0x400U) |
| #define OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY_SHIFT (10U) |
| #define OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY_SHIFT)) & OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY_MASK) |
| #define OCOTP_SW_STICKY_RSVD1_MASK (0xFFFFF800U) |
| #define OCOTP_SW_STICKY_RSVD1_SHIFT (11U) |
| #define OCOTP_SW_STICKY_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_RSVD1_SHIFT)) & OCOTP_SW_STICKY_RSVD1_MASK) |
| /*! @} */ |
| |
| /*! @name SCS - Software Controllable Signals Register */ |
| /*! @{ */ |
| #define OCOTP_SCS_HAB_JDE_MASK (0x1U) |
| #define OCOTP_SCS_HAB_JDE_SHIFT (0U) |
| #define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK) |
| #define OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU) |
| #define OCOTP_SCS_SPARE_SHIFT (1U) |
| #define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK) |
| #define OCOTP_SCS_LOCK_MASK (0x80000000U) |
| #define OCOTP_SCS_LOCK_SHIFT (31U) |
| #define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK) |
| /*! @} */ |
| |
| /*! @name SCS_SET - Software Controllable Signals Register */ |
| /*! @{ */ |
| #define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U) |
| #define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U) |
| #define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK) |
| #define OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU) |
| #define OCOTP_SCS_SET_SPARE_SHIFT (1U) |
| #define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK) |
| #define OCOTP_SCS_SET_LOCK_MASK (0x80000000U) |
| #define OCOTP_SCS_SET_LOCK_SHIFT (31U) |
| #define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK) |
| /*! @} */ |
| |
| /*! @name SCS_CLR - Software Controllable Signals Register */ |
| /*! @{ */ |
| #define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U) |
| #define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U) |
| #define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK) |
| #define OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU) |
| #define OCOTP_SCS_CLR_SPARE_SHIFT (1U) |
| #define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK) |
| #define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U) |
| #define OCOTP_SCS_CLR_LOCK_SHIFT (31U) |
| #define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK) |
| /*! @} */ |
| |
| /*! @name SCS_TOG - Software Controllable Signals Register */ |
| /*! @{ */ |
| #define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U) |
| #define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U) |
| #define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK) |
| #define OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU) |
| #define OCOTP_SCS_TOG_SPARE_SHIFT (1U) |
| #define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK) |
| #define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U) |
| #define OCOTP_SCS_TOG_LOCK_SHIFT (31U) |
| #define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK) |
| /*! @} */ |
| |
| /*! @name VERSION - OTP Controller Version Register */ |
| /*! @{ */ |
| #define OCOTP_VERSION_STEP_MASK (0xFFFFU) |
| #define OCOTP_VERSION_STEP_SHIFT (0U) |
| #define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK) |
| #define OCOTP_VERSION_MINOR_MASK (0xFF0000U) |
| #define OCOTP_VERSION_MINOR_SHIFT (16U) |
| #define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK) |
| #define OCOTP_VERSION_MAJOR_MASK (0xFF000000U) |
| #define OCOTP_VERSION_MAJOR_SHIFT (24U) |
| #define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK) |
| /*! @} */ |
| |
| /*! @name LOCK - Value of OTP Bank0 Word0 (Lock controls) */ |
| /*! @{ */ |
| #define OCOTP_LOCK_TESTER_MASK (0x3U) |
| #define OCOTP_LOCK_TESTER_SHIFT (0U) |
| #define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK) |
| #define OCOTP_LOCK_BOOT_CFG_MASK (0xCU) |
| #define OCOTP_LOCK_BOOT_CFG_SHIFT (2U) |
| #define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK) |
| #define OCOTP_LOCK_MEM_TRIM_MASK (0x30U) |
| #define OCOTP_LOCK_MEM_TRIM_SHIFT (4U) |
| #define OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK) |
| #define OCOTP_LOCK_ANALOG_MASK (0xC0U) |
| #define OCOTP_LOCK_ANALOG_SHIFT (6U) |
| #define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK) |
| #define OCOTP_LOCK_OTPMK_MASK (0x100U) |
| #define OCOTP_LOCK_OTPMK_SHIFT (8U) |
| #define OCOTP_LOCK_OTPMK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_SHIFT)) & OCOTP_LOCK_OTPMK_MASK) |
| #define OCOTP_LOCK_SRK_MASK (0x200U) |
| #define OCOTP_LOCK_SRK_SHIFT (9U) |
| #define OCOTP_LOCK_SRK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SRK_SHIFT)) & OCOTP_LOCK_SRK_MASK) |
| #define OCOTP_LOCK_SJC_RESP_MASK (0x400U) |
| #define OCOTP_LOCK_SJC_RESP_SHIFT (10U) |
| #define OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK) |
| #define OCOTP_LOCK_GROUP_MASK_MASK (0x800U) |
| #define OCOTP_LOCK_GROUP_MASK_SHIFT (11U) |
| #define OCOTP_LOCK_GROUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GROUP_MASK_SHIFT)) & OCOTP_LOCK_GROUP_MASK_MASK) |
| #define OCOTP_LOCK_USB_ID_MASK (0x3000U) |
| #define OCOTP_LOCK_USB_ID_SHIFT (12U) |
| #define OCOTP_LOCK_USB_ID(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_USB_ID_SHIFT)) & OCOTP_LOCK_USB_ID_MASK) |
| #define OCOTP_LOCK_MAC_ADDR_MASK (0xC000U) |
| #define OCOTP_LOCK_MAC_ADDR_SHIFT (14U) |
| #define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK) |
| #define OCOTP_LOCK_MAU_KEY_MASK (0x10000U) |
| #define OCOTP_LOCK_MAU_KEY_SHIFT (16U) |
| #define OCOTP_LOCK_MAU_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAU_KEY_SHIFT)) & OCOTP_LOCK_MAU_KEY_MASK) |
| #define OCOTP_LOCK_ROM_PATCH_MASK (0x20000U) |
| #define OCOTP_LOCK_ROM_PATCH_SHIFT (17U) |
| #define OCOTP_LOCK_ROM_PATCH(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ROM_PATCH_SHIFT)) & OCOTP_LOCK_ROM_PATCH_MASK) |
| #define OCOTP_LOCK_GP_CRC_MASK (0xC0000U) |
| #define OCOTP_LOCK_GP_CRC_SHIFT (18U) |
| #define OCOTP_LOCK_GP_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP_CRC_SHIFT)) & OCOTP_LOCK_GP_CRC_MASK) |
| #define OCOTP_LOCK_GP1_MASK (0x300000U) |
| #define OCOTP_LOCK_GP1_SHIFT (20U) |
| #define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK) |
| #define OCOTP_LOCK_GP2_MASK (0xC00000U) |
| #define OCOTP_LOCK_GP2_SHIFT (22U) |
| #define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK) |
| #define OCOTP_LOCK_HDMI_KEY_MASK (0x3000000U) |
| #define OCOTP_LOCK_HDMI_KEY_SHIFT (24U) |
| #define OCOTP_LOCK_HDMI_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_HDMI_KEY_SHIFT)) & OCOTP_LOCK_HDMI_KEY_MASK) |
| #define OCOTP_LOCK_HDMI_CRC_MASK (0xC000000U) |
| #define OCOTP_LOCK_HDMI_CRC_SHIFT (26U) |
| #define OCOTP_LOCK_HDMI_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_HDMI_CRC_SHIFT)) & OCOTP_LOCK_HDMI_CRC_MASK) |
| #define OCOTP_LOCK_HDCP_KEY_MASK (0x30000000U) |
| #define OCOTP_LOCK_HDCP_KEY_SHIFT (28U) |
| #define OCOTP_LOCK_HDCP_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_HDCP_KEY_SHIFT)) & OCOTP_LOCK_HDCP_KEY_MASK) |
| #define OCOTP_LOCK_HDCP_CRC_MASK (0xC0000000U) |
| #define OCOTP_LOCK_HDCP_CRC_SHIFT (30U) |
| #define OCOTP_LOCK_HDCP_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_HDCP_CRC_SHIFT)) & OCOTP_LOCK_HDCP_CRC_MASK) |
| /*! @} */ |
| |
| /*! @name TESTER0 - Value of OTP Bank0 Word1 (Tester Info.) */ |
| /*! @{ */ |
| #define OCOTP_TESTER0_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_TESTER0_BITS_SHIFT (0U) |
| #define OCOTP_TESTER0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TESTER0_BITS_SHIFT)) & OCOTP_TESTER0_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name TESTER1 - Value of OTP Bank0 Word2 (tester Info.) */ |
| /*! @{ */ |
| #define OCOTP_TESTER1_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_TESTER1_BITS_SHIFT (0U) |
| #define OCOTP_TESTER1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TESTER1_BITS_SHIFT)) & OCOTP_TESTER1_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name TESTER2 - Value of OTP Bank0 Word3 (Tester Info.) */ |
| /*! @{ */ |
| #define OCOTP_TESTER2_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_TESTER2_BITS_SHIFT (0U) |
| #define OCOTP_TESTER2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TESTER2_BITS_SHIFT)) & OCOTP_TESTER2_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name TESTER3 - Value of OTP Bank1 Word0 (Tester Info.) */ |
| /*! @{ */ |
| #define OCOTP_TESTER3_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_TESTER3_BITS_SHIFT (0U) |
| #define OCOTP_TESTER3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TESTER3_BITS_SHIFT)) & OCOTP_TESTER3_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name TESTER4 - Value of OTP Bank1 Word1 (Tester Info.) */ |
| /*! @{ */ |
| #define OCOTP_TESTER4_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_TESTER4_BITS_SHIFT (0U) |
| #define OCOTP_TESTER4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TESTER4_BITS_SHIFT)) & OCOTP_TESTER4_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name TESTER5 - Value of OTP Bank1 Word2 (Tester Info.) */ |
| /*! @{ */ |
| #define OCOTP_TESTER5_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_TESTER5_BITS_SHIFT (0U) |
| #define OCOTP_TESTER5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TESTER5_BITS_SHIFT)) & OCOTP_TESTER5_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name BOOT_CFG0 - Value of OTP Bank1 Word3 (Boot Configuration Info.) */ |
| /*! @{ */ |
| #define OCOTP_BOOT_CFG0_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_BOOT_CFG0_BITS_SHIFT (0U) |
| #define OCOTP_BOOT_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_BOOT_CFG0_BITS_SHIFT)) & OCOTP_BOOT_CFG0_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name BOOT_CFG1 - Value of OTP Bank2 Word0 (Boot Configuration Info.) */ |
| /*! @{ */ |
| #define OCOTP_BOOT_CFG1_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_BOOT_CFG1_BITS_SHIFT (0U) |
| #define OCOTP_BOOT_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_BOOT_CFG1_BITS_SHIFT)) & OCOTP_BOOT_CFG1_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name BOOT_CFG2 - Value of OTP Bank2 Word1 (Boot Configuration Info.) */ |
| /*! @{ */ |
| #define OCOTP_BOOT_CFG2_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_BOOT_CFG2_BITS_SHIFT (0U) |
| #define OCOTP_BOOT_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_BOOT_CFG2_BITS_SHIFT)) & OCOTP_BOOT_CFG2_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name BOOT_CFG3 - Value of OTP Bank2 Word2 (Boot Configuration Info.) */ |
| /*! @{ */ |
| #define OCOTP_BOOT_CFG3_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_BOOT_CFG3_BITS_SHIFT (0U) |
| #define OCOTP_BOOT_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_BOOT_CFG3_BITS_SHIFT)) & OCOTP_BOOT_CFG3_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name BOOT_CFG4 - Value of OTP Bank2 Word3 (BOOT Configuration Info.) */ |
| /*! @{ */ |
| #define OCOTP_BOOT_CFG4_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_BOOT_CFG4_BITS_SHIFT (0U) |
| #define OCOTP_BOOT_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_BOOT_CFG4_BITS_SHIFT)) & OCOTP_BOOT_CFG4_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name MEM_TRIM0 - Value of OTP Bank3 Word0 (Memory Related Info.) */ |
| /*! @{ */ |
| #define OCOTP_MEM_TRIM0_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_MEM_TRIM0_BITS_SHIFT (0U) |
| #define OCOTP_MEM_TRIM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM_TRIM0_BITS_SHIFT)) & OCOTP_MEM_TRIM0_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name MEM_TRIM1 - Value of OTP Bank3 Word1 (Memory Related Info.) */ |
| /*! @{ */ |
| #define OCOTP_MEM_TRIM1_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_MEM_TRIM1_BITS_SHIFT (0U) |
| #define OCOTP_MEM_TRIM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM_TRIM1_BITS_SHIFT)) & OCOTP_MEM_TRIM1_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name ANA0 - Value of OTP Bank3 Word2 (Analog Info.) */ |
| /*! @{ */ |
| #define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_ANA0_BITS_SHIFT (0U) |
| #define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name ANA1 - Value of OTP Bank3 Word3 (Analog Info.) */ |
| /*! @{ */ |
| #define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_ANA1_BITS_SHIFT (0U) |
| #define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name SRK0 - Shadow Register for OTP Bank6 Word0 (SRK Hash) */ |
| /*! @{ */ |
| #define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_SRK0_BITS_SHIFT (0U) |
| #define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name SRK1 - Shadow Register for OTP Bank6 Word1 (SRK Hash) */ |
| /*! @{ */ |
| #define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_SRK1_BITS_SHIFT (0U) |
| #define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name SRK2 - Shadow Register for OTP Bank6 Word2 (SRK Hash) */ |
| /*! @{ */ |
| #define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_SRK2_BITS_SHIFT (0U) |
| #define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name SRK3 - Shadow Register for OTP Bank6 Word3 (SRK Hash) */ |
| /*! @{ */ |
| #define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_SRK3_BITS_SHIFT (0U) |
| #define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name SRK4 - Shadow Register for OTP Bank7 Word0 (SRK Hash) */ |
| /*! @{ */ |
| #define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_SRK4_BITS_SHIFT (0U) |
| #define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name SRK5 - Shadow Register for OTP Bank7 Word1 (SRK Hash) */ |
| /*! @{ */ |
| #define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_SRK5_BITS_SHIFT (0U) |
| #define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name SRK6 - Shadow Register for OTP Bank7 Word2 (SRK Hash) */ |
| /*! @{ */ |
| #define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_SRK6_BITS_SHIFT (0U) |
| #define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name SRK7 - Shadow Register for OTP Bank7 Word3 (SRK Hash) */ |
| /*! @{ */ |
| #define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_SRK7_BITS_SHIFT (0U) |
| #define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name SJC_RESP0 - Value of OTP Bank8 Word0 (Secure JTAG Response Field) */ |
| /*! @{ */ |
| #define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_SJC_RESP0_BITS_SHIFT (0U) |
| #define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name SJC_RESP1 - Value of OTP Bank8 Word1 (Secure JTAG Response Field) */ |
| /*! @{ */ |
| #define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_SJC_RESP1_BITS_SHIFT (0U) |
| #define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name USB_ID - Value of OTP Bank8 Word2 (USB ID info) */ |
| /*! @{ */ |
| #define OCOTP_USB_ID_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_USB_ID_BITS_SHIFT (0U) |
| #define OCOTP_USB_ID_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_USB_ID_BITS_SHIFT)) & OCOTP_USB_ID_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name FIELD_RETURN - Value of OTP Bank5 Word6 (Field Return) */ |
| /*! @{ */ |
| #define OCOTP_FIELD_RETURN_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_FIELD_RETURN_BITS_SHIFT (0U) |
| #define OCOTP_FIELD_RETURN_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FIELD_RETURN_BITS_SHIFT)) & OCOTP_FIELD_RETURN_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name MAC_ADDR0 - Value of OTP Bank9 Word0 (MAC Address) */ |
| /*! @{ */ |
| #define OCOTP_MAC_ADDR0_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_MAC_ADDR0_BITS_SHIFT (0U) |
| #define OCOTP_MAC_ADDR0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC_ADDR0_BITS_SHIFT)) & OCOTP_MAC_ADDR0_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name MAC_ADDR1 - Value of OTP Bank9 Word1 (MAC Address) */ |
| /*! @{ */ |
| #define OCOTP_MAC_ADDR1_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_MAC_ADDR1_BITS_SHIFT (0U) |
| #define OCOTP_MAC_ADDR1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC_ADDR1_BITS_SHIFT)) & OCOTP_MAC_ADDR1_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name MAC_ADDR2 - Value of OTP Bank9 Word2 (MAC Address) */ |
| /*! @{ */ |
| #define OCOTP_MAC_ADDR2_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_MAC_ADDR2_BITS_SHIFT (0U) |
| #define OCOTP_MAC_ADDR2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC_ADDR2_BITS_SHIFT)) & OCOTP_MAC_ADDR2_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name SRK_REVOKE - Value of OTP Bank9 Word3 (SRK Revoke) */ |
| /*! @{ */ |
| #define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_SRK_REVOKE_BITS_SHIFT (0U) |
| #define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name MAU_KEY0 - Shadow Register for OTP Bank10 Word0 (MAU Key) */ |
| /*! @{ */ |
| #define OCOTP_MAU_KEY0_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_MAU_KEY0_BITS_SHIFT (0U) |
| #define OCOTP_MAU_KEY0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY0_BITS_SHIFT)) & OCOTP_MAU_KEY0_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name MAU_KEY1 - Shadow Register for OTP Bank10 Word1 (MAU Key) */ |
| /*! @{ */ |
| #define OCOTP_MAU_KEY1_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_MAU_KEY1_BITS_SHIFT (0U) |
| #define OCOTP_MAU_KEY1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY1_BITS_SHIFT)) & OCOTP_MAU_KEY1_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name MAU_KEY2 - Shadow Register for OTP Bank10 Word2 (MAU Key) */ |
| /*! @{ */ |
| #define OCOTP_MAU_KEY2_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_MAU_KEY2_BITS_SHIFT (0U) |
| #define OCOTP_MAU_KEY2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY2_BITS_SHIFT)) & OCOTP_MAU_KEY2_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name MAU_KEY3 - Shadow Register for OTP Bank10 Word3 (MAU Key) */ |
| /*! @{ */ |
| #define OCOTP_MAU_KEY3_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_MAU_KEY3_BITS_SHIFT (0U) |
| #define OCOTP_MAU_KEY3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY3_BITS_SHIFT)) & OCOTP_MAU_KEY3_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name MAU_KEY4 - Shadow Register for OTP Bank11 Word0 (MAU Key) */ |
| /*! @{ */ |
| #define OCOTP_MAU_KEY4_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_MAU_KEY4_BITS_SHIFT (0U) |
| #define OCOTP_MAU_KEY4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY4_BITS_SHIFT)) & OCOTP_MAU_KEY4_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name MAU_KEY5 - Shadow Register for OTP Bank11 Word1 (MAU Key) */ |
| /*! @{ */ |
| #define OCOTP_MAU_KEY5_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_MAU_KEY5_BITS_SHIFT (0U) |
| #define OCOTP_MAU_KEY5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY5_BITS_SHIFT)) & OCOTP_MAU_KEY5_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name MAU_KEY6 - Shadow Register for OTP Bank11 Word2 (MAU Key) */ |
| /*! @{ */ |
| #define OCOTP_MAU_KEY6_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_MAU_KEY6_BITS_SHIFT (0U) |
| #define OCOTP_MAU_KEY6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY6_BITS_SHIFT)) & OCOTP_MAU_KEY6_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name MAU_KEY7 - Shadow Register for OTP Bank11 Word3 (MAU Key) */ |
| /*! @{ */ |
| #define OCOTP_MAU_KEY7_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_MAU_KEY7_BITS_SHIFT (0U) |
| #define OCOTP_MAU_KEY7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAU_KEY7_BITS_SHIFT)) & OCOTP_MAU_KEY7_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name GP10 - Value of OTP Bank14 Word0 () */ |
| /*! @{ */ |
| #define OCOTP_GP10_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_GP10_BITS_SHIFT (0U) |
| #define OCOTP_GP10_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP10_BITS_SHIFT)) & OCOTP_GP10_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name GP11 - Value of OTP Bank14 Word1 () */ |
| /*! @{ */ |
| #define OCOTP_GP11_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_GP11_BITS_SHIFT (0U) |
| #define OCOTP_GP11_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP11_BITS_SHIFT)) & OCOTP_GP11_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name GP20 - Value of OTP Bank14 Word2 () */ |
| /*! @{ */ |
| #define OCOTP_GP20_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_GP20_BITS_SHIFT (0U) |
| #define OCOTP_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP20_BITS_SHIFT)) & OCOTP_GP20_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name GP21 - Value of OTP Bank14 Word3 () */ |
| /*! @{ */ |
| #define OCOTP_GP21_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_GP21_BITS_SHIFT (0U) |
| #define OCOTP_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP21_BITS_SHIFT)) & OCOTP_GP21_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name GP_CRC0 - Value of OTP Bank15 Word0 (CRC Key) */ |
| /*! @{ */ |
| #define OCOTP_GP_CRC0_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_GP_CRC0_BITS_SHIFT (0U) |
| #define OCOTP_GP_CRC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP_CRC0_BITS_SHIFT)) & OCOTP_GP_CRC0_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name GP_CRC1 - Value of OTP Bank15 Word1 (CRC Key) */ |
| /*! @{ */ |
| #define OCOTP_GP_CRC1_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_GP_CRC1_BITS_SHIFT (0U) |
| #define OCOTP_GP_CRC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP_CRC1_BITS_SHIFT)) & OCOTP_GP_CRC1_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name GP_CRC2 - Value of OTP Bank15 Word2 (CRC Key) */ |
| /*! @{ */ |
| #define OCOTP_GP_CRC2_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_GP_CRC2_BITS_SHIFT (0U) |
| #define OCOTP_GP_CRC2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP_CRC2_BITS_SHIFT)) & OCOTP_GP_CRC2_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name GROUP_MASK - Value of OTP Bank15 Word3 (CRC Key) */ |
| /*! @{ */ |
| #define OCOTP_GROUP_MASK_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_GROUP_MASK_BITS_SHIFT (0U) |
| #define OCOTP_GROUP_MASK_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GROUP_MASK_BITS_SHIFT)) & OCOTP_GROUP_MASK_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDMI_FW_SRK0 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDMI_FW_SRK0_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDMI_FW_SRK0_BITS_SHIFT (0U) |
| #define OCOTP_HDMI_FW_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK0_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK0_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDMI_FW_SRK1 - Value of OTP Bank16 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDMI_FW_SRK1_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDMI_FW_SRK1_BITS_SHIFT (0U) |
| #define OCOTP_HDMI_FW_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK1_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK1_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDMI_FW_SRK2 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDMI_FW_SRK2_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDMI_FW_SRK2_BITS_SHIFT (0U) |
| #define OCOTP_HDMI_FW_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK2_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK2_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDMI_FW_SRK3 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDMI_FW_SRK3_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDMI_FW_SRK3_BITS_SHIFT (0U) |
| #define OCOTP_HDMI_FW_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK3_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK3_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDMI_FW_SRK4 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDMI_FW_SRK4_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDMI_FW_SRK4_BITS_SHIFT (0U) |
| #define OCOTP_HDMI_FW_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK4_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK4_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDMI_FW_SRK5 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDMI_FW_SRK5_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDMI_FW_SRK5_BITS_SHIFT (0U) |
| #define OCOTP_HDMI_FW_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK5_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK5_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDMI_FW_SRK6 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDMI_FW_SRK6_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDMI_FW_SRK6_BITS_SHIFT (0U) |
| #define OCOTP_HDMI_FW_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK6_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK6_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDMI_FW_SRK7 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDMI_FW_SRK7_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDMI_FW_SRK7_BITS_SHIFT (0U) |
| #define OCOTP_HDMI_FW_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_FW_SRK7_BITS_SHIFT)) & OCOTP_HDMI_FW_SRK7_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDMI_KMEK0 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDMI_KMEK0_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDMI_KMEK0_BITS_SHIFT (0U) |
| #define OCOTP_HDMI_KMEK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_KMEK0_BITS_SHIFT)) & OCOTP_HDMI_KMEK0_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDMI_KMEK1 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDMI_KMEK1_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDMI_KMEK1_BITS_SHIFT (0U) |
| #define OCOTP_HDMI_KMEK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_KMEK1_BITS_SHIFT)) & OCOTP_HDMI_KMEK1_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDMI_KMEK2 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDMI_KMEK2_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDMI_KMEK2_BITS_SHIFT (0U) |
| #define OCOTP_HDMI_KMEK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_KMEK2_BITS_SHIFT)) & OCOTP_HDMI_KMEK2_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDMI_KMEK3 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDMI_KMEK3_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDMI_KMEK3_BITS_SHIFT (0U) |
| #define OCOTP_HDMI_KMEK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDMI_KMEK3_BITS_SHIFT)) & OCOTP_HDMI_KMEK3_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CONS0 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CONS0_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CONS0_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CONS0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CONS0_BITS_SHIFT)) & OCOTP_HDCP_TX_CONS0_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CONS1 - Value of OTP Bank16 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CONS1_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CONS1_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CONS1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CONS1_BITS_SHIFT)) & OCOTP_HDCP_TX_CONS1_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CONS2 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CONS2_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CONS2_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CONS2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CONS2_BITS_SHIFT)) & OCOTP_HDCP_TX_CONS2_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CONS3 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CONS3_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CONS3_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CONS3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CONS3_BITS_SHIFT)) & OCOTP_HDCP_TX_CONS3_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT0 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT0_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT0_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT0_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT0_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT1 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT1_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT1_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT1_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT1_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT2 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT2_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT2_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT2_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT2_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT3 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT3_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT3_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT3_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT3_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT4 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT4_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT4_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT4_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT4_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT5 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT5_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT5_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT5_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT5_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT6 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT6_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT6_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT6_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT6_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT7 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT7_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT7_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT7_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT7_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT8 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT8_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT8_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT8_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT8_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT8_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT9 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT9_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT9_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT9_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT9_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT9_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT10 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT10_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT10_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT10_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT10_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT10_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT11 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT11_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT11_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT11_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT11_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT11_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT12 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT12_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT12_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT12_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT12_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT12_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT13 - Value of OTP Bank16 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT13_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT13_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT13_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT13_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT13_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT14 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT14_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT14_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT14_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT14_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT14_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT15 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT15_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT15_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT15_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT15_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT15_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT16 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT16_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT16_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT16_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT16_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT16_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT17 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT17_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT17_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT17_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT17_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT17_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT18 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT18_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT18_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT18_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT18_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT18_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT19 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT19_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT19_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT19_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT19_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT19_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT20 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT20_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT20_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT20_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT20_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT21 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT21_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT21_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT21_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT21_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT22 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT22_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT22_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT22_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT22_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT23 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT23_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT23_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT23_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT23_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT24 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT24_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT24_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT24_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT24_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT24_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT25 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT25_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT25_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT25_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT25_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT25_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT26 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT26_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT26_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT26_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT26_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT26_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT27 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT27_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT27_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT27_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT27_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT27_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT28 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT28_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT28_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT28_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT28_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT28_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT29 - Value of OTP Bank16 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT29_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT29_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT29_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT29_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT29_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT30 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT30_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT30_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT30_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT30_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT30_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT31 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT31_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT31_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT31_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT31_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT31_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT32 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT32_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT32_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT32_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT32_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT32_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT33 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT33_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT33_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT33_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT33_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT33_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT34 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT34_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT34_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT34_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT34_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT34_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT35 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT35_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT35_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT35_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT35_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT35_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT36 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT36_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT36_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT36_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT36_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT36_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT37 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT37_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT37_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT37_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT37_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT37_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT38 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT38_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT38_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT38_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT38_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT38_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT39 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT39_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT39_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT39_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT39_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT39_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT40 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT40_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT40_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT40_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT40_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT40_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT41 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT41_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT41_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT41_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT41_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT41_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT42 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT42_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT42_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT42_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT42_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT42_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT43 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT43_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT43_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT43_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT43_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT43_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT44 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT44_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT44_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT44_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT44_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT44_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT45 - Value of OTP Bank16 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT45_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT45_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT45_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT45_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT45_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT46 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT46_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT46_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT46_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT46_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT46_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT47 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT47_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT47_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT47_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT47_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT47_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT48 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT48_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT48_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT48_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT48_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT48_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT49 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT49_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT49_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT49_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT49_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT49_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT50 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT50_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT50_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT50_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT50_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT50_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT51 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT51_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT51_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT51_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT51_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT51_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT52 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT52_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT52_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT52_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT52_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT52_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT53 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT53_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT53_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT53_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT53_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT53_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT54 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT54_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT54_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT54_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT54_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT54_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT55 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT55_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT55_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT55_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT55_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT55_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT56 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT56_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT56_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT56_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT56_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT56_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT57 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT57_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT57_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT57_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT57_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT57_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT58 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT58_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT58_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT58_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT58_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT58_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT59 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT59_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT59_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT59_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT59_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT59_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT60 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT60_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT60_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT60_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT60_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT60_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT61 - Value of OTP Bank16 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT61_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT61_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT61_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT61_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT61_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT62 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT62_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT62_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT62_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT62_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT62_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT63 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT63_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT63_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT63_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT63_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT63_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT64 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT64_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT64_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT64_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT64_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT64_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT65 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT65_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT65_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT65_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT65_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT65_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT66 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT66_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT66_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT66_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT66_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT66_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT67 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT67_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT67_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT67_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT67_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT67_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT68 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT68_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT68_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT68_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT68_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT68_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT69 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT69_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT69_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT69_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT69_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT69_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT70 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT70_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT70_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT70_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT70_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT70_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT71 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT71_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT71_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT71_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT71_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT71_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT72 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT72_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT72_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT72_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT72_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT72_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT73 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT73_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT73_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT73_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT73_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT73_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT74 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT74_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT74_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT74_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT74_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT74_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT75 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT75_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT75_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT75_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT75_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT75_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT76 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT76_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT76_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT76_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT76_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT76_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT77 - Value of OTP Bank16 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT77_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT77_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT77_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT77_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT77_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT78 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT78_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT78_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT78_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT78_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT78_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT79 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT79_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT79_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT79_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT79_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT79_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT80 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT80_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT80_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT80_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT80_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT80_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT81 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT81_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT81_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT81_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT81_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT81_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT82 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT82_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT82_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT82_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT82_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT82_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT83 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT83_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT83_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT83_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT83_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT83_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT84 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT84_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT84_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT84_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT84_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT84_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT85 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT85_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT85_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT85_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT85_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT85_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT86 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT86_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT86_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT86_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT86_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT86_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT87 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT87_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT87_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT87_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT87_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT87_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT88 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT88_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT88_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT88_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT88_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT88_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT89 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT89_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT89_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT89_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT89_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT89_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT90 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT90_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT90_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT90_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT90_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT90_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT91 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT91_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT91_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT91_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT91_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT91_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT92 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT92_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT92_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT92_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT92_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT92_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT93 - Value of OTP Bank16 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT93_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT93_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT93_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT93_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT93_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT94 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT94_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT94_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT94_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT94_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT94_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_TX_CERT95 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_TX_CERT95_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_TX_CERT95_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_TX_CERT95_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_TX_CERT95_BITS_SHIFT)) & OCOTP_HDCP_TX_CERT95_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY0 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY0_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY0_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY0_BITS_SHIFT)) & OCOTP_HDCP_KEY0_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY1 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY1_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY1_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY1_BITS_SHIFT)) & OCOTP_HDCP_KEY1_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY2 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY2_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY2_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY2_BITS_SHIFT)) & OCOTP_HDCP_KEY2_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY3 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY3_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY3_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY3_BITS_SHIFT)) & OCOTP_HDCP_KEY3_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY4 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY4_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY4_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY4_BITS_SHIFT)) & OCOTP_HDCP_KEY4_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY5 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY5_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY5_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY5_BITS_SHIFT)) & OCOTP_HDCP_KEY5_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY6 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY6_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY6_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY6_BITS_SHIFT)) & OCOTP_HDCP_KEY6_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY7 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY7_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY7_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY7_BITS_SHIFT)) & OCOTP_HDCP_KEY7_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY8 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY8_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY8_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY8_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY8_BITS_SHIFT)) & OCOTP_HDCP_KEY8_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY9 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY9_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY9_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY9_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY9_BITS_SHIFT)) & OCOTP_HDCP_KEY9_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY10 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY10_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY10_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY10_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY10_BITS_SHIFT)) & OCOTP_HDCP_KEY10_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY11 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY11_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY11_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY11_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY11_BITS_SHIFT)) & OCOTP_HDCP_KEY11_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY12 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY12_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY12_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY12_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY12_BITS_SHIFT)) & OCOTP_HDCP_KEY12_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY13 - Value of OTP Bank16 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY13_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY13_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY13_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY13_BITS_SHIFT)) & OCOTP_HDCP_KEY13_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY14 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY14_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY14_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY14_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY14_BITS_SHIFT)) & OCOTP_HDCP_KEY14_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY15 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY15_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY15_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY15_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY15_BITS_SHIFT)) & OCOTP_HDCP_KEY15_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY16 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY16_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY16_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY16_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY16_BITS_SHIFT)) & OCOTP_HDCP_KEY16_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY17 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY17_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY17_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY17_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY17_BITS_SHIFT)) & OCOTP_HDCP_KEY17_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY18 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY18_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY18_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY18_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY18_BITS_SHIFT)) & OCOTP_HDCP_KEY18_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY19 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY19_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY19_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY19_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY19_BITS_SHIFT)) & OCOTP_HDCP_KEY19_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY20 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY20_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY20_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY20_BITS_SHIFT)) & OCOTP_HDCP_KEY20_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY21 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY21_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY21_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY21_BITS_SHIFT)) & OCOTP_HDCP_KEY21_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY22 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY22_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY22_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY22_BITS_SHIFT)) & OCOTP_HDCP_KEY22_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY23 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY23_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY23_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY23_BITS_SHIFT)) & OCOTP_HDCP_KEY23_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY24 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY24_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY24_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY24_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY24_BITS_SHIFT)) & OCOTP_HDCP_KEY24_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY25 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY25_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY25_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY25_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY25_BITS_SHIFT)) & OCOTP_HDCP_KEY25_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY26 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY26_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY26_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY26_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY26_BITS_SHIFT)) & OCOTP_HDCP_KEY26_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY27 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY27_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY27_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY27_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY27_BITS_SHIFT)) & OCOTP_HDCP_KEY27_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY28 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY28_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY28_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY28_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY28_BITS_SHIFT)) & OCOTP_HDCP_KEY28_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY29 - Value of OTP Bank16 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY29_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY29_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY29_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY29_BITS_SHIFT)) & OCOTP_HDCP_KEY29_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY30 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY30_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY30_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY30_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY30_BITS_SHIFT)) & OCOTP_HDCP_KEY30_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY31 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY31_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY31_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY31_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY31_BITS_SHIFT)) & OCOTP_HDCP_KEY31_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY32 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY32_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY32_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY32_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY32_BITS_SHIFT)) & OCOTP_HDCP_KEY32_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY33 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY33_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY33_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY33_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY33_BITS_SHIFT)) & OCOTP_HDCP_KEY33_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY34 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY34_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY34_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY34_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY34_BITS_SHIFT)) & OCOTP_HDCP_KEY34_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY35 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY35_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY35_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY35_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY35_BITS_SHIFT)) & OCOTP_HDCP_KEY35_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY36 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY36_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY36_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY36_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY36_BITS_SHIFT)) & OCOTP_HDCP_KEY36_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY37 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY37_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY37_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY37_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY37_BITS_SHIFT)) & OCOTP_HDCP_KEY37_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY38 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY38_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY38_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY38_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY38_BITS_SHIFT)) & OCOTP_HDCP_KEY38_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY39 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY39_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY39_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY39_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY39_BITS_SHIFT)) & OCOTP_HDCP_KEY39_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY40 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY40_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY40_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY40_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY40_BITS_SHIFT)) & OCOTP_HDCP_KEY40_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY41 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY41_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY41_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY41_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY41_BITS_SHIFT)) & OCOTP_HDCP_KEY41_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY42 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY42_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY42_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY42_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY42_BITS_SHIFT)) & OCOTP_HDCP_KEY42_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY43 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY43_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY43_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY43_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY43_BITS_SHIFT)) & OCOTP_HDCP_KEY43_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY44 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY44_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY44_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY44_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY44_BITS_SHIFT)) & OCOTP_HDCP_KEY44_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY45 - Value of OTP Bank16 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY45_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY45_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY45_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY45_BITS_SHIFT)) & OCOTP_HDCP_KEY45_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY46 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY46_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY46_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY46_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY46_BITS_SHIFT)) & OCOTP_HDCP_KEY46_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY47 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY47_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY47_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY47_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY47_BITS_SHIFT)) & OCOTP_HDCP_KEY47_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY48 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY48_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY48_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY48_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY48_BITS_SHIFT)) & OCOTP_HDCP_KEY48_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY49 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY49_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY49_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY49_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY49_BITS_SHIFT)) & OCOTP_HDCP_KEY49_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY50 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY50_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY50_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY50_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY50_BITS_SHIFT)) & OCOTP_HDCP_KEY50_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY51 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY51_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY51_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY51_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY51_BITS_SHIFT)) & OCOTP_HDCP_KEY51_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY52 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY52_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY52_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY52_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY52_BITS_SHIFT)) & OCOTP_HDCP_KEY52_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY53 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY53_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY53_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY53_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY53_BITS_SHIFT)) & OCOTP_HDCP_KEY53_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY54 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY54_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY54_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY54_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY54_BITS_SHIFT)) & OCOTP_HDCP_KEY54_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY55 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY55_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY55_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY55_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY55_BITS_SHIFT)) & OCOTP_HDCP_KEY55_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY56 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY56_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY56_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY56_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY56_BITS_SHIFT)) & OCOTP_HDCP_KEY56_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY57 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY57_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY57_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY57_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY57_BITS_SHIFT)) & OCOTP_HDCP_KEY57_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY58 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY58_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY58_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY58_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY58_BITS_SHIFT)) & OCOTP_HDCP_KEY58_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY59 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY59_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY59_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY59_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY59_BITS_SHIFT)) & OCOTP_HDCP_KEY59_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY60 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY60_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY60_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY60_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY60_BITS_SHIFT)) & OCOTP_HDCP_KEY60_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY61 - Value of OTP Bank16 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY61_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY61_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY61_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY61_BITS_SHIFT)) & OCOTP_HDCP_KEY61_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY62 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY62_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY62_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY62_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY62_BITS_SHIFT)) & OCOTP_HDCP_KEY62_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY63 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY63_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY63_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY63_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY63_BITS_SHIFT)) & OCOTP_HDCP_KEY63_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY64 - Value of OTP Bank17 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY64_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY64_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY64_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY64_BITS_SHIFT)) & OCOTP_HDCP_KEY64_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY65 - Value of OTP Bank17 Word1 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY65_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY65_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY65_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY65_BITS_SHIFT)) & OCOTP_HDCP_KEY65_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY66 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY66_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY66_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY66_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY66_BITS_SHIFT)) & OCOTP_HDCP_KEY66_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY67 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY67_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY67_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY67_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY67_BITS_SHIFT)) & OCOTP_HDCP_KEY67_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY68 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY68_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY68_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY68_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY68_BITS_SHIFT)) & OCOTP_HDCP_KEY68_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY69 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY69_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY69_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY69_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY69_BITS_SHIFT)) & OCOTP_HDCP_KEY69_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY70 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY70_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY70_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY70_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY70_BITS_SHIFT)) & OCOTP_HDCP_KEY70_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name HDCP_KEY71 - Value of OTP Bank16 Word0 (HDCP Key) */ |
| /*! @{ */ |
| #define OCOTP_HDCP_KEY71_BITS_MASK (0xFFFFFFFFU) |
| #define OCOTP_HDCP_KEY71_BITS_SHIFT (0U) |
| #define OCOTP_HDCP_KEY71_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HDCP_KEY71_BITS_SHIFT)) & OCOTP_HDCP_KEY71_BITS_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group OCOTP_Register_Masks */ |
| |
| |
| /* OCOTP - Peripheral instance base addresses */ |
| /** Peripheral OCOTP base address */ |
| #define OCOTP_BASE (0x30350000u) |
| /** Peripheral OCOTP base pointer */ |
| #define OCOTP ((OCOTP_Type *)OCOTP_BASE) |
| /** Array initializer of OCOTP peripheral base addresses */ |
| #define OCOTP_BASE_ADDRS { OCOTP_BASE } |
| /** Array initializer of OCOTP peripheral base pointers */ |
| #define OCOTP_BASE_PTRS { OCOTP } |
| |
| /*! |
| * @} |
| */ /* end of group OCOTP_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- PWM Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** PWM - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t PWMCR; /**< PWM Control Register, offset: 0x0 */ |
| __IO uint32_t PWMSR; /**< PWM Status Register, offset: 0x4 */ |
| __IO uint32_t PWMIR; /**< PWM Interrupt Register, offset: 0x8 */ |
| __IO uint32_t PWMSAR; /**< PWM Sample Register, offset: 0xC */ |
| __IO uint32_t PWMPR; /**< PWM Period Register, offset: 0x10 */ |
| __I uint32_t PWMCNR; /**< PWM Counter Register, offset: 0x14 */ |
| } PWM_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- PWM Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup PWM_Register_Masks PWM Register Masks |
| * @{ |
| */ |
| |
| /*! @name PWMCR - PWM Control Register */ |
| /*! @{ */ |
| #define PWM_PWMCR_EN_MASK (0x1U) |
| #define PWM_PWMCR_EN_SHIFT (0U) |
| /*! EN |
| * 0b0..PWM disabled |
| * 0b1..PWM enabled |
| */ |
| #define PWM_PWMCR_EN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_EN_SHIFT)) & PWM_PWMCR_EN_MASK) |
| #define PWM_PWMCR_REPEAT_MASK (0x6U) |
| #define PWM_PWMCR_REPEAT_SHIFT (1U) |
| /*! REPEAT |
| * 0b00..Use each sample once |
| * 0b01..Use each sample twice |
| * 0b10..Use each sample four times |
| * 0b11..Use each sample eight times |
| */ |
| #define PWM_PWMCR_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_REPEAT_SHIFT)) & PWM_PWMCR_REPEAT_MASK) |
| #define PWM_PWMCR_SWR_MASK (0x8U) |
| #define PWM_PWMCR_SWR_SHIFT (3U) |
| /*! SWR |
| * 0b0..PWM is out of reset |
| * 0b1..PWM is undergoing reset |
| */ |
| #define PWM_PWMCR_SWR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_SWR_SHIFT)) & PWM_PWMCR_SWR_MASK) |
| #define PWM_PWMCR_PRESCALER_MASK (0xFFF0U) |
| #define PWM_PWMCR_PRESCALER_SHIFT (4U) |
| /*! PRESCALER |
| * 0b000000000000..Divide by 1 |
| * 0b000000000001..Divide by 2 |
| * 0b111111111111..Divide by 4096 |
| */ |
| #define PWM_PWMCR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_PRESCALER_SHIFT)) & PWM_PWMCR_PRESCALER_MASK) |
| #define PWM_PWMCR_CLKSRC_MASK (0x30000U) |
| #define PWM_PWMCR_CLKSRC_SHIFT (16U) |
| /*! CLKSRC |
| * 0b00..Clock is off |
| * 0b01..ipg_clk |
| * 0b10..ipg_clk_highfreq |
| * 0b11..ipg_clk_32k |
| */ |
| #define PWM_PWMCR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_CLKSRC_SHIFT)) & PWM_PWMCR_CLKSRC_MASK) |
| #define PWM_PWMCR_POUTC_MASK (0xC0000U) |
| #define PWM_PWMCR_POUTC_SHIFT (18U) |
| /*! POUTC |
| * 0b00..Output pin is set at rollover and cleared at comparison |
| * 0b01..Output pin is cleared at rollover and set at comparison |
| * 0b10..PWM output is disconnected |
| * 0b11..PWM output is disconnected |
| */ |
| #define PWM_PWMCR_POUTC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_POUTC_SHIFT)) & PWM_PWMCR_POUTC_MASK) |
| #define PWM_PWMCR_HCTR_MASK (0x100000U) |
| #define PWM_PWMCR_HCTR_SHIFT (20U) |
| /*! HCTR |
| * 0b0..Half word swapping does not take place |
| * 0b1..Half words from write data bus are swapped |
| */ |
| #define PWM_PWMCR_HCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_HCTR_SHIFT)) & PWM_PWMCR_HCTR_MASK) |
| #define PWM_PWMCR_BCTR_MASK (0x200000U) |
| #define PWM_PWMCR_BCTR_SHIFT (21U) |
| /*! BCTR |
| * 0b0..byte ordering remains the same |
| * 0b1..byte ordering is reversed |
| */ |
| #define PWM_PWMCR_BCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_BCTR_SHIFT)) & PWM_PWMCR_BCTR_MASK) |
| #define PWM_PWMCR_DBGEN_MASK (0x400000U) |
| #define PWM_PWMCR_DBGEN_SHIFT (22U) |
| /*! DBGEN |
| * 0b0..Inactive in debug mode |
| * 0b1..Active in debug mode |
| */ |
| #define PWM_PWMCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DBGEN_SHIFT)) & PWM_PWMCR_DBGEN_MASK) |
| #define PWM_PWMCR_WAITEN_MASK (0x800000U) |
| #define PWM_PWMCR_WAITEN_SHIFT (23U) |
| /*! WAITEN |
| * 0b0..Inactive in wait mode |
| * 0b1..Active in wait mode |
| */ |
| #define PWM_PWMCR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_WAITEN_SHIFT)) & PWM_PWMCR_WAITEN_MASK) |
| #define PWM_PWMCR_DOZEN_MASK (0x1000000U) |
| #define PWM_PWMCR_DOZEN_SHIFT (24U) |
| /*! DOZEN |
| * 0b0..Inactive in doze mode |
| * 0b1..Active in doze mode |
| */ |
| #define PWM_PWMCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DOZEN_SHIFT)) & PWM_PWMCR_DOZEN_MASK) |
| #define PWM_PWMCR_STOPEN_MASK (0x2000000U) |
| #define PWM_PWMCR_STOPEN_SHIFT (25U) |
| /*! STOPEN |
| * 0b0..Inactive in stop mode |
| * 0b1..Active in stop mode |
| */ |
| #define PWM_PWMCR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_STOPEN_SHIFT)) & PWM_PWMCR_STOPEN_MASK) |
| #define PWM_PWMCR_FWM_MASK (0xC000000U) |
| #define PWM_PWMCR_FWM_SHIFT (26U) |
| /*! FWM |
| * 0b00..FIFO empty flag is set when there are more than or equal to 1 empty slots in FIFO |
| * 0b01..FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO |
| * 0b10..FIFO empty flag is set when there are more than or equal to 3 empty slots in FIFO |
| * 0b11..FIFO empty flag is set when there are more than or equal to 4 empty slots in FIFO |
| */ |
| #define PWM_PWMCR_FWM(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_FWM_SHIFT)) & PWM_PWMCR_FWM_MASK) |
| /*! @} */ |
| |
| /*! @name PWMSR - PWM Status Register */ |
| /*! @{ */ |
| #define PWM_PWMSR_FIFOAV_MASK (0x7U) |
| #define PWM_PWMSR_FIFOAV_SHIFT (0U) |
| /*! FIFOAV |
| * 0b000..No data available |
| * 0b001..1 word of data in FIFO |
| * 0b010..2 words of data in FIFO |
| * 0b011..3 words of data in FIFO |
| * 0b100..4 words of data in FIFO |
| * 0b101..unused |
| * 0b110..unused |
| * 0b111..unused |
| */ |
| #define PWM_PWMSR_FIFOAV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FIFOAV_SHIFT)) & PWM_PWMSR_FIFOAV_MASK) |
| #define PWM_PWMSR_FE_MASK (0x8U) |
| #define PWM_PWMSR_FE_SHIFT (3U) |
| /*! FE |
| * 0b0..Data level is above water mark |
| * 0b1..When the data level falls below the mark set by FWM field |
| */ |
| #define PWM_PWMSR_FE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FE_SHIFT)) & PWM_PWMSR_FE_MASK) |
| #define PWM_PWMSR_ROV_MASK (0x10U) |
| #define PWM_PWMSR_ROV_SHIFT (4U) |
| /*! ROV |
| * 0b0..Roll-over event not occurred |
| * 0b1..Roll-over event occurred |
| */ |
| #define PWM_PWMSR_ROV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_ROV_SHIFT)) & PWM_PWMSR_ROV_MASK) |
| #define PWM_PWMSR_CMP_MASK (0x20U) |
| #define PWM_PWMSR_CMP_SHIFT (5U) |
| /*! CMP |
| * 0b0..Compare event not occurred |
| * 0b1..Compare event occurred |
| */ |
| #define PWM_PWMSR_CMP(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_CMP_SHIFT)) & PWM_PWMSR_CMP_MASK) |
| #define PWM_PWMSR_FWE_MASK (0x40U) |
| #define PWM_PWMSR_FWE_SHIFT (6U) |
| /*! FWE |
| * 0b0..FIFO write error not occurred |
| * 0b1..FIFO write error occurred |
| */ |
| #define PWM_PWMSR_FWE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FWE_SHIFT)) & PWM_PWMSR_FWE_MASK) |
| /*! @} */ |
| |
| /*! @name PWMIR - PWM Interrupt Register */ |
| /*! @{ */ |
| #define PWM_PWMIR_FIE_MASK (0x1U) |
| #define PWM_PWMIR_FIE_SHIFT (0U) |
| /*! FIE |
| * 0b0..FIFO Empty interrupt disabled |
| * 0b1..FIFO Empty interrupt enabled |
| */ |
| #define PWM_PWMIR_FIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_FIE_SHIFT)) & PWM_PWMIR_FIE_MASK) |
| #define PWM_PWMIR_RIE_MASK (0x2U) |
| #define PWM_PWMIR_RIE_SHIFT (1U) |
| /*! RIE |
| * 0b0..Roll-over interrupt not enabled |
| * 0b1..Roll-over Interrupt enabled |
| */ |
| #define PWM_PWMIR_RIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_RIE_SHIFT)) & PWM_PWMIR_RIE_MASK) |
| #define PWM_PWMIR_CIE_MASK (0x4U) |
| #define PWM_PWMIR_CIE_SHIFT (2U) |
| /*! CIE |
| * 0b0..Compare Interrupt not enabled |
| * 0b1..Compare Interrupt enabled |
| */ |
| #define PWM_PWMIR_CIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_CIE_SHIFT)) & PWM_PWMIR_CIE_MASK) |
| /*! @} */ |
| |
| /*! @name PWMSAR - PWM Sample Register */ |
| /*! @{ */ |
| #define PWM_PWMSAR_SAMPLE_MASK (0xFFFFU) |
| #define PWM_PWMSAR_SAMPLE_SHIFT (0U) |
| #define PWM_PWMSAR_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSAR_SAMPLE_SHIFT)) & PWM_PWMSAR_SAMPLE_MASK) |
| /*! @} */ |
| |
| /*! @name PWMPR - PWM Period Register */ |
| /*! @{ */ |
| #define PWM_PWMPR_PERIOD_MASK (0xFFFFU) |
| #define PWM_PWMPR_PERIOD_SHIFT (0U) |
| #define PWM_PWMPR_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMPR_PERIOD_SHIFT)) & PWM_PWMPR_PERIOD_MASK) |
| /*! @} */ |
| |
| /*! @name PWMCNR - PWM Counter Register */ |
| /*! @{ */ |
| #define PWM_PWMCNR_COUNT_MASK (0xFFFFU) |
| #define PWM_PWMCNR_COUNT_SHIFT (0U) |
| #define PWM_PWMCNR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCNR_COUNT_SHIFT)) & PWM_PWMCNR_COUNT_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group PWM_Register_Masks */ |
| |
| |
| /* PWM - Peripheral instance base addresses */ |
| /** Peripheral PWM1 base address */ |
| #define PWM1_BASE (0x30660000u) |
| /** Peripheral PWM1 base pointer */ |
| #define PWM1 ((PWM_Type *)PWM1_BASE) |
| /** Peripheral PWM2 base address */ |
| #define PWM2_BASE (0x30670000u) |
| /** Peripheral PWM2 base pointer */ |
| #define PWM2 ((PWM_Type *)PWM2_BASE) |
| /** Peripheral PWM3 base address */ |
| #define PWM3_BASE (0x30680000u) |
| /** Peripheral PWM3 base pointer */ |
| #define PWM3 ((PWM_Type *)PWM3_BASE) |
| /** Peripheral PWM4 base address */ |
| #define PWM4_BASE (0x30690000u) |
| /** Peripheral PWM4 base pointer */ |
| #define PWM4 ((PWM_Type *)PWM4_BASE) |
| /** Array initializer of PWM peripheral base addresses */ |
| #define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE } |
| /** Array initializer of PWM peripheral base pointers */ |
| #define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 } |
| /** Interrupt vectors for the PWM peripheral type */ |
| #define PWM_IRQS { NotAvail_IRQn, PWM1_IRQn, PWM2_IRQn, PWM3_IRQn, PWM4_IRQn } |
| |
| /*! |
| * @} |
| */ /* end of group PWM_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- QuadSPI Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** QuadSPI - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ |
| uint8_t RESERVED_0[4]; |
| __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ |
| __IO uint32_t FLSHCR; /**< Flash Configuration Register, offset: 0xC */ |
| __IO uint32_t BUF0CR; /**< Buffer0 Configuration Register, offset: 0x10 */ |
| __IO uint32_t BUF1CR; /**< Buffer1 Configuration Register, offset: 0x14 */ |
| __IO uint32_t BUF2CR; /**< Buffer2 Configuration Register, offset: 0x18 */ |
| __IO uint32_t BUF3CR; /**< Buffer3 Configuration Register, offset: 0x1C */ |
| __IO uint32_t BFGENCR; /**< Buffer Generic Configuration Register, offset: 0x20 */ |
| uint8_t RESERVED_1[12]; |
| __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ |
| __IO uint32_t BUF1IND; /**< Buffer1 Top Index Register, offset: 0x34 */ |
| __IO uint32_t BUF2IND; /**< Buffer2 Top Index Register, offset: 0x38 */ |
| uint8_t RESERVED_2[196]; |
| __IO uint32_t SFAR; /**< Serial Flash Address Register, offset: 0x100 */ |
| uint8_t RESERVED_3[4]; |
| __IO uint32_t SMPR; /**< Sampling Register, offset: 0x108 */ |
| __I uint32_t RBSR; /**< RX Buffer Status Register, offset: 0x10C */ |
| __IO uint32_t RBCT; /**< RX Buffer Control Register, offset: 0x110 */ |
| uint8_t RESERVED_4[60]; |
| __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ |
| __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ |
| uint8_t RESERVED_5[4]; |
| __I uint32_t SR; /**< Status Register, offset: 0x15C */ |
| __IO uint32_t FR; /**< Flag Register, offset: 0x160 */ |
| __IO uint32_t RSER; /**< Interrupt and DMA Request Select and Enable Register, offset: 0x164 */ |
| __I uint32_t SPNDST; /**< Sequence Suspend Status Register, offset: 0x168 */ |
| __IO uint32_t SPTRCLR; /**< Sequence Pointer Clear Register, offset: 0x16C */ |
| uint8_t RESERVED_6[16]; |
| __IO uint32_t SFA1AD; /**< Serial Flash A1 Top Address, offset: 0x180 */ |
| __IO uint32_t SFA2AD; /**< Serial Flash A2 Top Address, offset: 0x184 */ |
| __IO uint32_t SFB1AD; /**< Serial Flash B1Top Address, offset: 0x188 */ |
| __IO uint32_t SFB2AD; /**< Serial Flash B2Top Address, offset: 0x18C */ |
| uint8_t RESERVED_7[112]; |
| __IO uint32_t RBDR[32]; /**< RX Buffer Data Register, array offset: 0x200, array step: 0x4 */ |
| uint8_t RESERVED_8[128]; |
| __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x300 */ |
| __IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x304 */ |
| uint8_t RESERVED_9[8]; |
| __IO uint32_t LUT[64]; /**< Look-up Table register, array offset: 0x310, array step: 0x4 */ |
| } QuadSPI_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- QuadSPI Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks |
| * @{ |
| */ |
| |
| /*! @name MCR - Module Configuration Register */ |
| /*! @{ */ |
| #define QuadSPI_MCR_SWRSTSD_MASK (0x1U) |
| #define QuadSPI_MCR_SWRSTSD_SHIFT (0U) |
| /*! SWRSTSD |
| * 0b0..No action |
| * 0b1..Serial Flash domain flops are reset. Does not reset configuration registers. It is advisable to reset both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects. |
| */ |
| #define QuadSPI_MCR_SWRSTSD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTSD_SHIFT)) & QuadSPI_MCR_SWRSTSD_MASK) |
| #define QuadSPI_MCR_SWRSTHD_MASK (0x2U) |
| #define QuadSPI_MCR_SWRSTHD_SHIFT (1U) |
| /*! SWRSTHD |
| * 0b0..No action |
| * 0b1..AHB domain flops are reset. Does not reset configuration registers. It is advisable to reset both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects. |
| */ |
| #define QuadSPI_MCR_SWRSTHD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK) |
| #define QuadSPI_MCR_END_CFG_MASK (0xCU) |
| #define QuadSPI_MCR_END_CFG_SHIFT (2U) |
| #define QuadSPI_MCR_END_CFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_END_CFG_SHIFT)) & QuadSPI_MCR_END_CFG_MASK) |
| #define QuadSPI_MCR_DQS_EN_MASK (0x40U) |
| #define QuadSPI_MCR_DQS_EN_SHIFT (6U) |
| /*! DQS_EN |
| * 0b0..DQS disabled. |
| * 0b1..DQS enabled- When enabled, the incoming data is sampled on both the edges of DQS input when QSPI_MCR[DDR_EN] is set, else, on only one edge when QSPI_MCR[DDR_EN] is 0. The QSPI_SMPR[DDR_SMP] values are ignored. |
| */ |
| #define QuadSPI_MCR_DQS_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_EN_SHIFT)) & QuadSPI_MCR_DQS_EN_MASK) |
| #define QuadSPI_MCR_DDR_EN_MASK (0x80U) |
| #define QuadSPI_MCR_DDR_EN_SHIFT (7U) |
| /*! DDR_EN |
| * 0b0..2x and 4x clocks are disabled for SDR instructions only |
| * 0b1..2x and 4x clocks are enabled supports both SDR and DDR instruction. |
| */ |
| #define QuadSPI_MCR_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DDR_EN_SHIFT)) & QuadSPI_MCR_DDR_EN_MASK) |
| #define QuadSPI_MCR_CLR_RXF_MASK (0x400U) |
| #define QuadSPI_MCR_CLR_RXF_SHIFT (10U) |
| /*! CLR_RXF |
| * 0b0..No action. |
| * 0b1..Read and write pointers of the RX Buffer are reset to 0. QSPI_RBSR[RDBFL] is reset to 0. |
| */ |
| #define QuadSPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_RXF_SHIFT)) & QuadSPI_MCR_CLR_RXF_MASK) |
| #define QuadSPI_MCR_CLR_TXF_MASK (0x800U) |
| #define QuadSPI_MCR_CLR_TXF_SHIFT (11U) |
| /*! CLR_TXF |
| * 0b0..No action. |
| * 0b1..Read and write pointers of the TX Buffer are reset to 0. QSPI_TBSR[TRCTR] is reset to 0. |
| */ |
| #define QuadSPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_TXF_SHIFT)) & QuadSPI_MCR_CLR_TXF_MASK) |
| #define QuadSPI_MCR_MDIS_MASK (0x4000U) |
| #define QuadSPI_MCR_MDIS_SHIFT (14U) |
| /*! MDIS |
| * 0b0..Enable QuadSPI clocks. |
| * 0b1..Allow external logic to disable QuadSPI clocks. |
| */ |
| #define QuadSPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_MDIS_SHIFT)) & QuadSPI_MCR_MDIS_MASK) |
| #define QuadSPI_MCR_DQS_LOOPBACK_FROM_PAD_MASK (0x1000000U) |
| #define QuadSPI_MCR_DQS_LOOPBACK_FROM_PAD_SHIFT (24U) |
| #define QuadSPI_MCR_DQS_LOOPBACK_FROM_PAD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_LOOPBACK_FROM_PAD_SHIFT)) & QuadSPI_MCR_DQS_LOOPBACK_FROM_PAD_MASK) |
| #define QuadSPI_MCR_DQS_LOOPBACK_EN_MASK (0x2000000U) |
| #define QuadSPI_MCR_DQS_LOOPBACK_EN_SHIFT (25U) |
| #define QuadSPI_MCR_DQS_LOOPBACK_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_LOOPBACK_EN_SHIFT)) & QuadSPI_MCR_DQS_LOOPBACK_EN_MASK) |
| #define QuadSPI_MCR_DQS_PHASE_EN_MASK (0x4000000U) |
| #define QuadSPI_MCR_DQS_PHASE_EN_SHIFT (26U) |
| #define QuadSPI_MCR_DQS_PHASE_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_PHASE_EN_SHIFT)) & QuadSPI_MCR_DQS_PHASE_EN_MASK) |
| /*! @} */ |
| |
| /*! @name IPCR - IP Configuration Register */ |
| /*! @{ */ |
| #define QuadSPI_IPCR_IDATSZ_MASK (0xFFFFU) |
| #define QuadSPI_IPCR_IDATSZ_SHIFT (0U) |
| #define QuadSPI_IPCR_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_IDATSZ_SHIFT)) & QuadSPI_IPCR_IDATSZ_MASK) |
| #define QuadSPI_IPCR_PAR_EN_MASK (0x10000U) |
| #define QuadSPI_IPCR_PAR_EN_SHIFT (16U) |
| #define QuadSPI_IPCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_PAR_EN_SHIFT)) & QuadSPI_IPCR_PAR_EN_MASK) |
| #define QuadSPI_IPCR_SEQID_MASK (0xF000000U) |
| #define QuadSPI_IPCR_SEQID_SHIFT (24U) |
| #define QuadSPI_IPCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK) |
| /*! @} */ |
| |
| /*! @name FLSHCR - Flash Configuration Register */ |
| /*! @{ */ |
| #define QuadSPI_FLSHCR_TCSS_MASK (0xFU) |
| #define QuadSPI_FLSHCR_TCSS_SHIFT (0U) |
| #define QuadSPI_FLSHCR_TCSS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSS_SHIFT)) & QuadSPI_FLSHCR_TCSS_MASK) |
| #define QuadSPI_FLSHCR_TCSH_MASK (0xF00U) |
| #define QuadSPI_FLSHCR_TCSH_SHIFT (8U) |
| #define QuadSPI_FLSHCR_TCSH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSH_SHIFT)) & QuadSPI_FLSHCR_TCSH_MASK) |
| #define QuadSPI_FLSHCR_TDH_MASK (0x30000U) |
| #define QuadSPI_FLSHCR_TDH_SHIFT (16U) |
| /*! TDH |
| * 0b00..Data aligned with the posedge of Internal reference clock of QuadSPI |
| * 0b01..Data aligned with 2x serial flash half clock |
| * 0b10..Reserved |
| * 0b11..Reserved |
| */ |
| #define QuadSPI_FLSHCR_TDH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK) |
| /*! @} */ |
| |
| /*! @name BUF0CR - Buffer0 Configuration Register */ |
| /*! @{ */ |
| #define QuadSPI_BUF0CR_MSTRID_MASK (0xFU) |
| #define QuadSPI_BUF0CR_MSTRID_SHIFT (0U) |
| #define QuadSPI_BUF0CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_MSTRID_SHIFT)) & QuadSPI_BUF0CR_MSTRID_MASK) |
| #define QuadSPI_BUF0CR_ADATSZ_MASK (0xFF00U) |
| #define QuadSPI_BUF0CR_ADATSZ_SHIFT (8U) |
| #define QuadSPI_BUF0CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_ADATSZ_SHIFT)) & QuadSPI_BUF0CR_ADATSZ_MASK) |
| #define QuadSPI_BUF0CR_HP_EN_MASK (0x80000000U) |
| #define QuadSPI_BUF0CR_HP_EN_SHIFT (31U) |
| #define QuadSPI_BUF0CR_HP_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_HP_EN_SHIFT)) & QuadSPI_BUF0CR_HP_EN_MASK) |
| /*! @} */ |
| |
| /*! @name BUF1CR - Buffer1 Configuration Register */ |
| /*! @{ */ |
| #define QuadSPI_BUF1CR_MSTRID_MASK (0xFU) |
| #define QuadSPI_BUF1CR_MSTRID_SHIFT (0U) |
| #define QuadSPI_BUF1CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_MSTRID_SHIFT)) & QuadSPI_BUF1CR_MSTRID_MASK) |
| #define QuadSPI_BUF1CR_ADATSZ_MASK (0xFF00U) |
| #define QuadSPI_BUF1CR_ADATSZ_SHIFT (8U) |
| #define QuadSPI_BUF1CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_ADATSZ_SHIFT)) & QuadSPI_BUF1CR_ADATSZ_MASK) |
| /*! @} */ |
| |
| /*! @name BUF2CR - Buffer2 Configuration Register */ |
| /*! @{ */ |
| #define QuadSPI_BUF2CR_MSTRID_MASK (0xFU) |
| #define QuadSPI_BUF2CR_MSTRID_SHIFT (0U) |
| #define QuadSPI_BUF2CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_MSTRID_SHIFT)) & QuadSPI_BUF2CR_MSTRID_MASK) |
| #define QuadSPI_BUF2CR_ADATSZ_MASK (0xFF00U) |
| #define QuadSPI_BUF2CR_ADATSZ_SHIFT (8U) |
| #define QuadSPI_BUF2CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_ADATSZ_SHIFT)) & QuadSPI_BUF2CR_ADATSZ_MASK) |
| /*! @} */ |
| |
| /*! @name BUF3CR - Buffer3 Configuration Register */ |
| /*! @{ */ |
| #define QuadSPI_BUF3CR_MSTRID_MASK (0xFU) |
| #define QuadSPI_BUF3CR_MSTRID_SHIFT (0U) |
| #define QuadSPI_BUF3CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_MSTRID_SHIFT)) & QuadSPI_BUF3CR_MSTRID_MASK) |
| #define QuadSPI_BUF3CR_ADATSZ_MASK (0xFF00U) |
| #define QuadSPI_BUF3CR_ADATSZ_SHIFT (8U) |
| #define QuadSPI_BUF3CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ADATSZ_SHIFT)) & QuadSPI_BUF3CR_ADATSZ_MASK) |
| #define QuadSPI_BUF3CR_ALLMST_MASK (0x80000000U) |
| #define QuadSPI_BUF3CR_ALLMST_SHIFT (31U) |
| #define QuadSPI_BUF3CR_ALLMST(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ALLMST_SHIFT)) & QuadSPI_BUF3CR_ALLMST_MASK) |
| /*! @} */ |
| |
| /*! @name BFGENCR - Buffer Generic Configuration Register */ |
| /*! @{ */ |
| #define QuadSPI_BFGENCR_SEQID_MASK (0xF000U) |
| #define QuadSPI_BFGENCR_SEQID_SHIFT (12U) |
| #define QuadSPI_BFGENCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_SEQID_SHIFT)) & QuadSPI_BFGENCR_SEQID_MASK) |
| #define QuadSPI_BFGENCR_PAR_EN_MASK (0x10000U) |
| #define QuadSPI_BFGENCR_PAR_EN_SHIFT (16U) |
| #define QuadSPI_BFGENCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_PAR_EN_SHIFT)) & QuadSPI_BFGENCR_PAR_EN_MASK) |
| /*! @} */ |
| |
| /*! @name BUF0IND - Buffer0 Top Index Register */ |
| /*! @{ */ |
| #define QuadSPI_BUF0IND_TPINDX0_MASK (0xFFFFFFF8U) |
| #define QuadSPI_BUF0IND_TPINDX0_SHIFT (3U) |
| #define QuadSPI_BUF0IND_TPINDX0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0IND_TPINDX0_SHIFT)) & QuadSPI_BUF0IND_TPINDX0_MASK) |
| /*! @} */ |
| |
| /*! @name BUF1IND - Buffer1 Top Index Register */ |
| /*! @{ */ |
| #define QuadSPI_BUF1IND_TPINDX1_MASK (0xFFFFFFF8U) |
| #define QuadSPI_BUF1IND_TPINDX1_SHIFT (3U) |
| #define QuadSPI_BUF1IND_TPINDX1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1IND_TPINDX1_SHIFT)) & QuadSPI_BUF1IND_TPINDX1_MASK) |
| /*! @} */ |
| |
| /*! @name BUF2IND - Buffer2 Top Index Register */ |
| /*! @{ */ |
| #define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) |
| #define QuadSPI_BUF2IND_TPINDX2_SHIFT (3U) |
| #define QuadSPI_BUF2IND_TPINDX2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK) |
| /*! @} */ |
| |
| /*! @name SFAR - Serial Flash Address Register */ |
| /*! @{ */ |
| #define QuadSPI_SFAR_SFADR_MASK (0xFFFFFFFFU) |
| #define QuadSPI_SFAR_SFADR_SHIFT (0U) |
| #define QuadSPI_SFAR_SFADR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFAR_SFADR_SHIFT)) & QuadSPI_SFAR_SFADR_MASK) |
| /*! @} */ |
| |
| /*! @name SMPR - Sampling Register */ |
| /*! @{ */ |
| #define QuadSPI_SMPR_SDRSMP_MASK (0x60U) |
| #define QuadSPI_SMPR_SDRSMP_SHIFT (5U) |
| #define QuadSPI_SMPR_SDRSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_SDRSMP_SHIFT)) & QuadSPI_SMPR_SDRSMP_MASK) |
| #define QuadSPI_SMPR_DDRSMP_MASK (0x70000U) |
| #define QuadSPI_SMPR_DDRSMP_SHIFT (16U) |
| #define QuadSPI_SMPR_DDRSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_DDRSMP_SHIFT)) & QuadSPI_SMPR_DDRSMP_MASK) |
| /*! @} */ |
| |
| /*! @name RBSR - RX Buffer Status Register */ |
| /*! @{ */ |
| #define QuadSPI_RBSR_RDBFL_MASK (0x3F00U) |
| #define QuadSPI_RBSR_RDBFL_SHIFT (8U) |
| #define QuadSPI_RBSR_RDBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDBFL_SHIFT)) & QuadSPI_RBSR_RDBFL_MASK) |
| #define QuadSPI_RBSR_RDCTR_MASK (0xFFFF0000U) |
| #define QuadSPI_RBSR_RDCTR_SHIFT (16U) |
| #define QuadSPI_RBSR_RDCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDCTR_SHIFT)) & QuadSPI_RBSR_RDCTR_MASK) |
| /*! @} */ |
| |
| /*! @name RBCT - RX Buffer Control Register */ |
| /*! @{ */ |
| #define QuadSPI_RBCT_WMRK_MASK (0x1FU) |
| #define QuadSPI_RBCT_WMRK_SHIFT (0U) |
| #define QuadSPI_RBCT_WMRK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_WMRK_SHIFT)) & QuadSPI_RBCT_WMRK_MASK) |
| #define QuadSPI_RBCT_RXBRD_MASK (0x100U) |
| #define QuadSPI_RBCT_RXBRD_SHIFT (8U) |
| /*! RXBRD |
| * 0b0..RX Buffer content is read using the AHB Bus registers QSPI_ARDB0 to QSPI_ARDB31. For details, refer to Exclusive Access to Serial Flash for AHB Commands. |
| * 0b1..RX Buffer content is read using the IP Bus registers QSPI_RBDR0 to QSPI_RBDR31. |
| */ |
| #define QuadSPI_RBCT_RXBRD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_RXBRD_SHIFT)) & QuadSPI_RBCT_RXBRD_MASK) |
| /*! @} */ |
| |
| /*! @name TBSR - TX Buffer Status Register */ |
| /*! @{ */ |
| #define QuadSPI_TBSR_TRBFL_MASK (0x1F00U) |
| #define QuadSPI_TBSR_TRBFL_SHIFT (8U) |
| #define QuadSPI_TBSR_TRBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRBFL_SHIFT)) & QuadSPI_TBSR_TRBFL_MASK) |
| #define QuadSPI_TBSR_TRCTR_MASK (0xFFFF0000U) |
| #define QuadSPI_TBSR_TRCTR_SHIFT (16U) |
| #define QuadSPI_TBSR_TRCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRCTR_SHIFT)) & QuadSPI_TBSR_TRCTR_MASK) |
| /*! @} */ |
| |
| /*! @name TBDR - TX Buffer Data Register */ |
| /*! @{ */ |
| #define QuadSPI_TBDR_TXDATA_MASK (0xFFFFFFFFU) |
| #define QuadSPI_TBDR_TXDATA_SHIFT (0U) |
| #define QuadSPI_TBDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBDR_TXDATA_SHIFT)) & QuadSPI_TBDR_TXDATA_MASK) |
| /*! @} */ |
| |
| /*! @name SR - Status Register */ |
| /*! @{ */ |
| #define QuadSPI_SR_BUSY_MASK (0x1U) |
| #define QuadSPI_SR_BUSY_SHIFT (0U) |
| #define QuadSPI_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_BUSY_SHIFT)) & QuadSPI_SR_BUSY_MASK) |
| #define QuadSPI_SR_IP_ACC_MASK (0x2U) |
| #define QuadSPI_SR_IP_ACC_SHIFT (1U) |
| #define QuadSPI_SR_IP_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_IP_ACC_SHIFT)) & QuadSPI_SR_IP_ACC_MASK) |
| #define QuadSPI_SR_AHB_ACC_MASK (0x4U) |
| #define QuadSPI_SR_AHB_ACC_SHIFT (2U) |
| #define QuadSPI_SR_AHB_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB_ACC_SHIFT)) & QuadSPI_SR_AHB_ACC_MASK) |
| #define QuadSPI_SR_AHBGNT_MASK (0x20U) |
| #define QuadSPI_SR_AHBGNT_SHIFT (5U) |
| #define QuadSPI_SR_AHBGNT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBGNT_SHIFT)) & QuadSPI_SR_AHBGNT_MASK) |
| #define QuadSPI_SR_AHBTRN_MASK (0x40U) |
| #define QuadSPI_SR_AHBTRN_SHIFT (6U) |
| #define QuadSPI_SR_AHBTRN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBTRN_SHIFT)) & QuadSPI_SR_AHBTRN_MASK) |
| #define QuadSPI_SR_AHB0NE_MASK (0x80U) |
| #define QuadSPI_SR_AHB0NE_SHIFT (7U) |
| #define QuadSPI_SR_AHB0NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK) |
| #define QuadSPI_SR_AHB1NE_MASK (0x100U) |
| #define QuadSPI_SR_AHB1NE_SHIFT (8U) |
| #define QuadSPI_SR_AHB1NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1NE_SHIFT)) & QuadSPI_SR_AHB1NE_MASK) |
| #define QuadSPI_SR_AHB2NE_MASK (0x200U) |
| #define QuadSPI_SR_AHB2NE_SHIFT (9U) |
| #define QuadSPI_SR_AHB2NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2NE_SHIFT)) & QuadSPI_SR_AHB2NE_MASK) |
| #define QuadSPI_SR_AHB3NE_MASK (0x400U) |
| #define QuadSPI_SR_AHB3NE_SHIFT (10U) |
| #define QuadSPI_SR_AHB3NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3NE_SHIFT)) & QuadSPI_SR_AHB3NE_MASK) |
| #define QuadSPI_SR_AHB0FUL_MASK (0x800U) |
| #define QuadSPI_SR_AHB0FUL_SHIFT (11U) |
| #define QuadSPI_SR_AHB0FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK) |
| #define QuadSPI_SR_AHB1FUL_MASK (0x1000U) |
| #define QuadSPI_SR_AHB1FUL_SHIFT (12U) |
| #define QuadSPI_SR_AHB1FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1FUL_SHIFT)) & QuadSPI_SR_AHB1FUL_MASK) |
| #define QuadSPI_SR_AHB2FUL_MASK (0x2000U) |
| #define QuadSPI_SR_AHB2FUL_SHIFT (13U) |
| #define QuadSPI_SR_AHB2FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2FUL_SHIFT)) & QuadSPI_SR_AHB2FUL_MASK) |
| #define QuadSPI_SR_AHB3FUL_MASK (0x4000U) |
| #define QuadSPI_SR_AHB3FUL_SHIFT (14U) |
| #define QuadSPI_SR_AHB3FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3FUL_SHIFT)) & QuadSPI_SR_AHB3FUL_MASK) |
| #define QuadSPI_SR_RXWE_MASK (0x10000U) |
| #define QuadSPI_SR_RXWE_SHIFT (16U) |
| #define QuadSPI_SR_RXWE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK) |
| #define QuadSPI_SR_RXFULL_MASK (0x80000U) |
| #define QuadSPI_SR_RXFULL_SHIFT (19U) |
| #define QuadSPI_SR_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK) |
| #define QuadSPI_SR_RXDMA_MASK (0x800000U) |
| #define QuadSPI_SR_RXDMA_SHIFT (23U) |
| #define QuadSPI_SR_RXDMA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXDMA_SHIFT)) & QuadSPI_SR_RXDMA_MASK) |
| #define QuadSPI_SR_TXEDA_MASK (0x1000000U) |
| #define QuadSPI_SR_TXEDA_SHIFT (24U) |
| #define QuadSPI_SR_TXEDA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXEDA_SHIFT)) & QuadSPI_SR_TXEDA_MASK) |
| #define QuadSPI_SR_TXFULL_MASK (0x8000000U) |
| #define QuadSPI_SR_TXFULL_SHIFT (27U) |
| #define QuadSPI_SR_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK) |
| #define QuadSPI_SR_DLPSMP_MASK (0xE0000000U) |
| #define QuadSPI_SR_DLPSMP_SHIFT (29U) |
| #define QuadSPI_SR_DLPSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK) |
| /*! @} */ |
| |
| /*! @name FR - Flag Register */ |
| /*! @{ */ |
| #define QuadSPI_FR_TFF_MASK (0x1U) |
| #define QuadSPI_FR_TFF_SHIFT (0U) |
| #define QuadSPI_FR_TFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TFF_SHIFT)) & QuadSPI_FR_TFF_MASK) |
| #define QuadSPI_FR_IPGEF_MASK (0x10U) |
| #define QuadSPI_FR_IPGEF_SHIFT (4U) |
| #define QuadSPI_FR_IPGEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPGEF_SHIFT)) & QuadSPI_FR_IPGEF_MASK) |
| #define QuadSPI_FR_IPIEF_MASK (0x40U) |
| #define QuadSPI_FR_IPIEF_SHIFT (6U) |
| #define QuadSPI_FR_IPIEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPIEF_SHIFT)) & QuadSPI_FR_IPIEF_MASK) |
| #define QuadSPI_FR_IPAEF_MASK (0x80U) |
| #define QuadSPI_FR_IPAEF_SHIFT (7U) |
| #define QuadSPI_FR_IPAEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPAEF_SHIFT)) & QuadSPI_FR_IPAEF_MASK) |
| #define QuadSPI_FR_IUEF_MASK (0x800U) |
| #define QuadSPI_FR_IUEF_SHIFT (11U) |
| #define QuadSPI_FR_IUEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IUEF_SHIFT)) & QuadSPI_FR_IUEF_MASK) |
| #define QuadSPI_FR_ABOF_MASK (0x1000U) |
| #define QuadSPI_FR_ABOF_SHIFT (12U) |
| #define QuadSPI_FR_ABOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABOF_SHIFT)) & QuadSPI_FR_ABOF_MASK) |
| #define QuadSPI_FR_ABSEF_MASK (0x8000U) |
| #define QuadSPI_FR_ABSEF_SHIFT (15U) |
| #define QuadSPI_FR_ABSEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK) |
| #define QuadSPI_FR_RBDF_MASK (0x10000U) |
| #define QuadSPI_FR_RBDF_SHIFT (16U) |
| #define QuadSPI_FR_RBDF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBDF_SHIFT)) & QuadSPI_FR_RBDF_MASK) |
| #define QuadSPI_FR_RBOF_MASK (0x20000U) |
| #define QuadSPI_FR_RBOF_SHIFT (17U) |
| #define QuadSPI_FR_RBOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBOF_SHIFT)) & QuadSPI_FR_RBOF_MASK) |
| #define QuadSPI_FR_ILLINE_MASK (0x800000U) |
| #define QuadSPI_FR_ILLINE_SHIFT (23U) |
| #define QuadSPI_FR_ILLINE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK) |
| #define QuadSPI_FR_TBUF_MASK (0x4000000U) |
| #define QuadSPI_FR_TBUF_SHIFT (26U) |
| #define QuadSPI_FR_TBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBUF_SHIFT)) & QuadSPI_FR_TBUF_MASK) |
| #define QuadSPI_FR_TBFF_MASK (0x8000000U) |
| #define QuadSPI_FR_TBFF_SHIFT (27U) |
| #define QuadSPI_FR_TBFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBFF_SHIFT)) & QuadSPI_FR_TBFF_MASK) |
| #define QuadSPI_FR_DLPFF_MASK (0x80000000U) |
| #define QuadSPI_FR_DLPFF_SHIFT (31U) |
| #define QuadSPI_FR_DLPFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_DLPFF_SHIFT)) & QuadSPI_FR_DLPFF_MASK) |
| /*! @} */ |
| |
| /*! @name RSER - Interrupt and DMA Request Select and Enable Register */ |
| /*! @{ */ |
| #define QuadSPI_RSER_TFIE_MASK (0x1U) |
| #define QuadSPI_RSER_TFIE_SHIFT (0U) |
| /*! TFIE |
| * 0b0..No TFF interrupt will be generated |
| * 0b1..TFF interrupt will be generated |
| */ |
| #define QuadSPI_RSER_TFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TFIE_SHIFT)) & QuadSPI_RSER_TFIE_MASK) |
| #define QuadSPI_RSER_IPGEIE_MASK (0x10U) |
| #define QuadSPI_RSER_IPGEIE_SHIFT (4U) |
| /*! IPGEIE |
| * 0b0..No IPGEF interrupt will be generated |
| * 0b1..IPGEF interrupt will be generated |
| */ |
| #define QuadSPI_RSER_IPGEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPGEIE_SHIFT)) & QuadSPI_RSER_IPGEIE_MASK) |
| #define QuadSPI_RSER_IPIEIE_MASK (0x40U) |
| #define QuadSPI_RSER_IPIEIE_SHIFT (6U) |
| /*! IPIEIE |
| * 0b0..No IPIEF interrupt will be generated |
| * 0b0..IPIEF interrupt will be generated |
| */ |
| #define QuadSPI_RSER_IPIEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPIEIE_SHIFT)) & QuadSPI_RSER_IPIEIE_MASK) |
| #define QuadSPI_RSER_IPAEIE_MASK (0x80U) |
| #define QuadSPI_RSER_IPAEIE_SHIFT (7U) |
| /*! IPAEIE |
| * 0b0..No IPAEF interrupt will be generated |
| * 0b1..IPAEF interrupt will be generated |
| */ |
| #define QuadSPI_RSER_IPAEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPAEIE_SHIFT)) & QuadSPI_RSER_IPAEIE_MASK) |
| #define QuadSPI_RSER_IUEIE_MASK (0x800U) |
| #define QuadSPI_RSER_IUEIE_SHIFT (11U) |
| /*! IUEIE |
| * 0b0..No IUEF interrupt will be generated |
| * 0b1..IUEF interrupt will be generated |
| */ |
| #define QuadSPI_RSER_IUEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IUEIE_SHIFT)) & QuadSPI_RSER_IUEIE_MASK) |
| #define QuadSPI_RSER_ABOIE_MASK (0x1000U) |
| #define QuadSPI_RSER_ABOIE_SHIFT (12U) |
| /*! ABOIE |
| * 0b0..No ABOF interrupt will be generated |
| * 0b1..ABOF interrupt will be generated |
| */ |
| #define QuadSPI_RSER_ABOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABOIE_SHIFT)) & QuadSPI_RSER_ABOIE_MASK) |
| #define QuadSPI_RSER_ABSEIE_MASK (0x8000U) |
| #define QuadSPI_RSER_ABSEIE_SHIFT (15U) |
| /*! ABSEIE |
| * 0b0..No ABSEF interrupt will be generated |
| * 0b1..ABSEF interrupt will be generated |
| */ |
| #define QuadSPI_RSER_ABSEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABSEIE_SHIFT)) & QuadSPI_RSER_ABSEIE_MASK) |
| #define QuadSPI_RSER_RBDIE_MASK (0x10000U) |
| #define QuadSPI_RSER_RBDIE_SHIFT (16U) |
| /*! RBDIE |
| * 0b0..No RBDF interrupt will be generated |
| * 0b1..RBDF Interrupt will be generated |
| */ |
| #define QuadSPI_RSER_RBDIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDIE_SHIFT)) & QuadSPI_RSER_RBDIE_MASK) |
| #define QuadSPI_RSER_RBOIE_MASK (0x20000U) |
| #define QuadSPI_RSER_RBOIE_SHIFT (17U) |
| /*! RBOIE |
| * 0b0..No RBOF interrupt will be generated |
| * 0b1..RBOF interrupt will be generated |
| */ |
| #define QuadSPI_RSER_RBOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBOIE_SHIFT)) & QuadSPI_RSER_RBOIE_MASK) |
| #define QuadSPI_RSER_RBDDE_MASK (0x200000U) |
| #define QuadSPI_RSER_RBDDE_SHIFT (21U) |
| /*! RBDDE |
| * 0b0..No DMA request will be generated |
| * 0b1..DMA request will be generated |
| */ |
| #define QuadSPI_RSER_RBDDE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDDE_SHIFT)) & QuadSPI_RSER_RBDDE_MASK) |
| #define QuadSPI_RSER_ILLINIE_MASK (0x800000U) |
| #define QuadSPI_RSER_ILLINIE_SHIFT (23U) |
| /*! ILLINIE |
| * 0b0..No ILLINE interrupt will be generated |
| * 0b1..ILLINE interrupt will be generated |
| */ |
| #define QuadSPI_RSER_ILLINIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ILLINIE_SHIFT)) & QuadSPI_RSER_ILLINIE_MASK) |
| #define QuadSPI_RSER_TBUIE_MASK (0x4000000U) |
| #define QuadSPI_RSER_TBUIE_SHIFT (26U) |
| /*! TBUIE |
| * 0b0..No TBUF interrupt will be generated |
| * 0b1..TBUF interrupt will be generated |
| */ |
| #define QuadSPI_RSER_TBUIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBUIE_SHIFT)) & QuadSPI_RSER_TBUIE_MASK) |
| #define QuadSPI_RSER_TBFIE_MASK (0x8000000U) |
| #define QuadSPI_RSER_TBFIE_SHIFT (27U) |
| /*! TBFIE |
| * 0b0..No TBFF interrupt will be generated |
| * 0b1..TBFF interrupt will be generated |
| */ |
| #define QuadSPI_RSER_TBFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFIE_SHIFT)) & QuadSPI_RSER_TBFIE_MASK) |
| #define QuadSPI_RSER_DLPFIE_MASK (0x80000000U) |
| #define QuadSPI_RSER_DLPFIE_SHIFT (31U) |
| /*! DLPFIE |
| * 0b0..No DLPFF interrupt will be generated |
| * 0b1..DLPFF interrupt will be generated |
| */ |
| #define QuadSPI_RSER_DLPFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_DLPFIE_SHIFT)) & QuadSPI_RSER_DLPFIE_MASK) |
| /*! @} */ |
| |
| /*! @name SPNDST - Sequence Suspend Status Register */ |
| /*! @{ */ |
| #define QuadSPI_SPNDST_SUSPND_MASK (0x1U) |
| #define QuadSPI_SPNDST_SUSPND_SHIFT (0U) |
| #define QuadSPI_SPNDST_SUSPND(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SUSPND_SHIFT)) & QuadSPI_SPNDST_SUSPND_MASK) |
| #define QuadSPI_SPNDST_SPDBUF_MASK (0xC0U) |
| #define QuadSPI_SPNDST_SPDBUF_SHIFT (6U) |
| #define QuadSPI_SPNDST_SPDBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SPDBUF_SHIFT)) & QuadSPI_SPNDST_SPDBUF_MASK) |
| #define QuadSPI_SPNDST_DATLFT_MASK (0xFE00U) |
| #define QuadSPI_SPNDST_DATLFT_SHIFT (9U) |
| #define QuadSPI_SPNDST_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_DATLFT_SHIFT)) & QuadSPI_SPNDST_DATLFT_MASK) |
| /*! @} */ |
| |
| /*! @name SPTRCLR - Sequence Pointer Clear Register */ |
| /*! @{ */ |
| #define QuadSPI_SPTRCLR_BFPTRC_MASK (0x1U) |
| #define QuadSPI_SPTRCLR_BFPTRC_SHIFT (0U) |
| #define QuadSPI_SPTRCLR_BFPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_BFPTRC_SHIFT)) & QuadSPI_SPTRCLR_BFPTRC_MASK) |
| #define QuadSPI_SPTRCLR_IPPTRC_MASK (0x100U) |
| #define QuadSPI_SPTRCLR_IPPTRC_SHIFT (8U) |
| #define QuadSPI_SPTRCLR_IPPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_IPPTRC_SHIFT)) & QuadSPI_SPTRCLR_IPPTRC_MASK) |
| /*! @} */ |
| |
| /*! @name SFA1AD - Serial Flash A1 Top Address */ |
| /*! @{ */ |
| #define QuadSPI_SFA1AD_TPADA1_MASK (0xFFFFFC00U) |
| #define QuadSPI_SFA1AD_TPADA1_SHIFT (10U) |
| #define QuadSPI_SFA1AD_TPADA1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA1AD_TPADA1_SHIFT)) & QuadSPI_SFA1AD_TPADA1_MASK) |
| /*! @} */ |
| |
| /*! @name SFA2AD - Serial Flash A2 Top Address */ |
| /*! @{ */ |
| #define QuadSPI_SFA2AD_TPADA2_MASK (0xFFFFFC00U) |
| #define QuadSPI_SFA2AD_TPADA2_SHIFT (10U) |
| #define QuadSPI_SFA2AD_TPADA2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA2AD_TPADA2_SHIFT)) & QuadSPI_SFA2AD_TPADA2_MASK) |
| /*! @} */ |
| |
| /*! @name SFB1AD - Serial Flash B1Top Address */ |
| /*! @{ */ |
| #define QuadSPI_SFB1AD_TPADB1_MASK (0xFFFFFC00U) |
| #define QuadSPI_SFB1AD_TPADB1_SHIFT (10U) |
| #define QuadSPI_SFB1AD_TPADB1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB1AD_TPADB1_SHIFT)) & QuadSPI_SFB1AD_TPADB1_MASK) |
| /*! @} */ |
| |
| /*! @name SFB2AD - Serial Flash B2Top Address */ |
| /*! @{ */ |
| #define QuadSPI_SFB2AD_TPADB2_MASK (0xFFFFFC00U) |
| #define QuadSPI_SFB2AD_TPADB2_SHIFT (10U) |
| #define QuadSPI_SFB2AD_TPADB2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB2AD_TPADB2_SHIFT)) & QuadSPI_SFB2AD_TPADB2_MASK) |
| /*! @} */ |
| |
| /*! @name RBDR - RX Buffer Data Register */ |
| /*! @{ */ |
| #define QuadSPI_RBDR_RXDATA_MASK (0xFFFFFFFFU) |
| #define QuadSPI_RBDR_RXDATA_SHIFT (0U) |
| #define QuadSPI_RBDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBDR_RXDATA_SHIFT)) & QuadSPI_RBDR_RXDATA_MASK) |
| /*! @} */ |
| |
| /* The count of QuadSPI_RBDR */ |
| #define QuadSPI_RBDR_COUNT (32U) |
| |
| /*! @name LUTKEY - LUT Key Register */ |
| /*! @{ */ |
| #define QuadSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) |
| #define QuadSPI_LUTKEY_KEY_SHIFT (0U) |
| #define QuadSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUTKEY_KEY_SHIFT)) & QuadSPI_LUTKEY_KEY_MASK) |
| /*! @} */ |
| |
| /*! @name LCKCR - LUT Lock Configuration Register */ |
| /*! @{ */ |
| #define QuadSPI_LCKCR_LOCK_MASK (0x1U) |
| #define QuadSPI_LCKCR_LOCK_SHIFT (0U) |
| #define QuadSPI_LCKCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK) |
| #define QuadSPI_LCKCR_UNLOCK_MASK (0x2U) |
| #define QuadSPI_LCKCR_UNLOCK_SHIFT (1U) |
| #define QuadSPI_LCKCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_UNLOCK_SHIFT)) & QuadSPI_LCKCR_UNLOCK_MASK) |
| /*! @} */ |
| |
| /*! @name LUT - Look-up Table register */ |
| /*! @{ */ |
| #define QuadSPI_LUT_OPRND0_MASK (0xFFU) |
| #define QuadSPI_LUT_OPRND0_SHIFT (0U) |
| #define QuadSPI_LUT_OPRND0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND0_SHIFT)) & QuadSPI_LUT_OPRND0_MASK) |
| #define QuadSPI_LUT_PAD0_MASK (0x300U) |
| #define QuadSPI_LUT_PAD0_SHIFT (8U) |
| /*! PAD0 - Pad information for INSTR0. |
| * 0b00..1 Pad |
| * 0b01..2 Pads |
| * 0b10..4 Pads |
| * 0b11..NA |
| */ |
| #define QuadSPI_LUT_PAD0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD0_SHIFT)) & QuadSPI_LUT_PAD0_MASK) |
| #define QuadSPI_LUT_INSTR0_MASK (0xFC00U) |
| #define QuadSPI_LUT_INSTR0_SHIFT (10U) |
| #define QuadSPI_LUT_INSTR0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR0_SHIFT)) & QuadSPI_LUT_INSTR0_MASK) |
| #define QuadSPI_LUT_OPRND1_MASK (0xFF0000U) |
| #define QuadSPI_LUT_OPRND1_SHIFT (16U) |
| #define QuadSPI_LUT_OPRND1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND1_SHIFT)) & QuadSPI_LUT_OPRND1_MASK) |
| #define QuadSPI_LUT_PAD1_MASK (0x3000000U) |
| #define QuadSPI_LUT_PAD1_SHIFT (24U) |
| /*! PAD1 - Pad information for INSTR1. |
| * 0b00..1 Pad |
| * 0b01..2 Pads |
| * 0b10..4 Pads |
| * 0b11..NA |
| */ |
| #define QuadSPI_LUT_PAD1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD1_SHIFT)) & QuadSPI_LUT_PAD1_MASK) |
| #define QuadSPI_LUT_INSTR1_MASK (0xFC000000U) |
| #define QuadSPI_LUT_INSTR1_SHIFT (26U) |
| #define QuadSPI_LUT_INSTR1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR1_SHIFT)) & QuadSPI_LUT_INSTR1_MASK) |
| /*! @} */ |
| |
| /* The count of QuadSPI_LUT */ |
| #define QuadSPI_LUT_COUNT (64U) |
| |
| |
| /*! |
| * @} |
| */ /* end of group QuadSPI_Register_Masks */ |
| |
| |
| /* QuadSPI - Peripheral instance base addresses */ |
| /** Peripheral QuadSPI base address */ |
| #define QuadSPI_BASE (0x30BB0000u) |
| /** Peripheral QuadSPI base pointer */ |
| #define QuadSPI ((QuadSPI_Type *)QuadSPI_BASE) |
| /** Array initializer of QuadSPI peripheral base addresses */ |
| #define QuadSPI_BASE_ADDRS { QuadSPI_BASE } |
| /** Array initializer of QuadSPI peripheral base pointers */ |
| #define QuadSPI_BASE_PTRS { QuadSPI } |
| /** Interrupt vectors for the QuadSPI peripheral type */ |
| #define QuadSPI_IRQS { QSPI_IRQn } |
| |
| /*! |
| * @} |
| */ /* end of group QuadSPI_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- RDC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup RDC_Peripheral_Access_Layer RDC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** RDC - Register Layout Typedef */ |
| typedef struct { |
| __I uint32_t VIR; /**< Version Information, offset: 0x0 */ |
| uint8_t RESERVED_0[32]; |
| __IO uint32_t STAT; /**< Status, offset: 0x24 */ |
| __IO uint32_t INTCTRL; /**< Interrupt and Control, offset: 0x28 */ |
| __IO uint32_t INTSTAT; /**< Interrupt Status, offset: 0x2C */ |
| uint8_t RESERVED_1[464]; |
| __IO uint32_t MDA[27]; /**< Master Domain Assignment, array offset: 0x200, array step: 0x4 */ |
| uint8_t RESERVED_2[404]; |
| __IO uint32_t PDAP[118]; /**< Peripheral Domain Access Permissions, array offset: 0x400, array step: 0x4 */ |
| uint8_t RESERVED_3[552]; |
| struct { /* offset: 0x800, array step: 0x10 */ |
| __IO uint32_t MRSA; /**< Memory Region Start Address, array offset: 0x800, array step: 0x10 */ |
| __IO uint32_t MREA; /**< Memory Region End Address, array offset: 0x804, array step: 0x10 */ |
| __IO uint32_t MRC; /**< Memory Region Control, array offset: 0x808, array step: 0x10 */ |
| __IO uint32_t MRVS; /**< Memory Region Violation Status, array offset: 0x80C, array step: 0x10 */ |
| } MR[52]; |
| } RDC_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- RDC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup RDC_Register_Masks RDC Register Masks |
| * @{ |
| */ |
| |
| /*! @name VIR - Version Information */ |
| /*! @{ */ |
| #define RDC_VIR_NDID_MASK (0xFU) |
| #define RDC_VIR_NDID_SHIFT (0U) |
| #define RDC_VIR_NDID(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NDID_SHIFT)) & RDC_VIR_NDID_MASK) |
| #define RDC_VIR_NMSTR_MASK (0xFF0U) |
| #define RDC_VIR_NMSTR_SHIFT (4U) |
| #define RDC_VIR_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NMSTR_SHIFT)) & RDC_VIR_NMSTR_MASK) |
| #define RDC_VIR_NPER_MASK (0xFF000U) |
| #define RDC_VIR_NPER_SHIFT (12U) |
| #define RDC_VIR_NPER(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NPER_SHIFT)) & RDC_VIR_NPER_MASK) |
| #define RDC_VIR_NRGN_MASK (0xFF00000U) |
| #define RDC_VIR_NRGN_SHIFT (20U) |
| #define RDC_VIR_NRGN(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NRGN_SHIFT)) & RDC_VIR_NRGN_MASK) |
| /*! @} */ |
| |
| /*! @name STAT - Status */ |
| /*! @{ */ |
| #define RDC_STAT_DID_MASK (0xFU) |
| #define RDC_STAT_DID_SHIFT (0U) |
| #define RDC_STAT_DID(x) (((uint32_t)(((uint32_t)(x)) << RDC_STAT_DID_SHIFT)) & RDC_STAT_DID_MASK) |
| #define RDC_STAT_PDS_MASK (0x100U) |
| #define RDC_STAT_PDS_SHIFT (8U) |
| /*! PDS - Power Domain Status |
| * 0b0..Power Down Domain is OFF |
| * 0b1..Power Down Domain is ON |
| */ |
| #define RDC_STAT_PDS(x) (((uint32_t)(((uint32_t)(x)) << RDC_STAT_PDS_SHIFT)) & RDC_STAT_PDS_MASK) |
| /*! @} */ |
| |
| /*! @name INTCTRL - Interrupt and Control */ |
| /*! @{ */ |
| #define RDC_INTCTRL_RCI_EN_MASK (0x1U) |
| #define RDC_INTCTRL_RCI_EN_SHIFT (0U) |
| /*! RCI_EN - Restoration Complete Interrupt |
| * 0b0..Interrupt Disabled |
| * 0b1..Interrupt Enabled |
| */ |
| #define RDC_INTCTRL_RCI_EN(x) (((uint32_t)(((uint32_t)(x)) << RDC_INTCTRL_RCI_EN_SHIFT)) & RDC_INTCTRL_RCI_EN_MASK) |
| /*! @} */ |
| |
| /*! @name INTSTAT - Interrupt Status */ |
| /*! @{ */ |
| #define RDC_INTSTAT_INT_MASK (0x1U) |
| #define RDC_INTSTAT_INT_SHIFT (0U) |
| /*! INT - Interrupt Status |
| * 0b0..No Interrupt Pending |
| * 0b1..Interrupt Pending |
| */ |
| #define RDC_INTSTAT_INT(x) (((uint32_t)(((uint32_t)(x)) << RDC_INTSTAT_INT_SHIFT)) & RDC_INTSTAT_INT_MASK) |
| /*! @} */ |
| |
| /*! @name MDA - Master Domain Assignment */ |
| /*! @{ */ |
| #define RDC_MDA_DID_MASK (0x3U) |
| #define RDC_MDA_DID_SHIFT (0U) |
| /*! DID - Domain ID |
| * 0b00..Master assigned to Processing Domain 0 |
| * 0b01..Master assigned to Processing Domain 1 |
| * 0b10..Master assigned to Processing Domain 2 |
| * 0b11..Master assigned to Processing Domain 3 |
| */ |
| #define RDC_MDA_DID(x) (((uint32_t)(((uint32_t)(x)) << RDC_MDA_DID_SHIFT)) & RDC_MDA_DID_MASK) |
| #define RDC_MDA_LCK_MASK (0x80000000U) |
| #define RDC_MDA_LCK_SHIFT (31U) |
| /*! LCK |
| * 0b0..Not Locked |
| * 0b1..Locked |
| */ |
| #define RDC_MDA_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_MDA_LCK_SHIFT)) & RDC_MDA_LCK_MASK) |
| /*! @} */ |
| |
| /* The count of RDC_MDA */ |
| #define RDC_MDA_COUNT (27U) |
| |
| /*! @name PDAP - Peripheral Domain Access Permissions */ |
| /*! @{ */ |
| #define RDC_PDAP_D0W_MASK (0x1U) |
| #define RDC_PDAP_D0W_SHIFT (0U) |
| /*! D0W - Domain 0 Write Access |
| * 0b0..No Write Access |
| * 0b1..Write Access Allowed |
| */ |
| #define RDC_PDAP_D0W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0W_SHIFT)) & RDC_PDAP_D0W_MASK) |
| #define RDC_PDAP_D0R_MASK (0x2U) |
| #define RDC_PDAP_D0R_SHIFT (1U) |
| /*! D0R - Domain 0 Read Access |
| * 0b0..No Read Access |
| * 0b1..Read Access Allowed |
| */ |
| #define RDC_PDAP_D0R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0R_SHIFT)) & RDC_PDAP_D0R_MASK) |
| #define RDC_PDAP_D1W_MASK (0x4U) |
| #define RDC_PDAP_D1W_SHIFT (2U) |
| /*! D1W - Domain 1 Write Access |
| * 0b0..No Write Access |
| * 0b1..Write Access Allowed |
| */ |
| #define RDC_PDAP_D1W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1W_SHIFT)) & RDC_PDAP_D1W_MASK) |
| #define RDC_PDAP_D1R_MASK (0x8U) |
| #define RDC_PDAP_D1R_SHIFT (3U) |
| /*! D1R - Domain 1 Read Access |
| * 0b0..No Read Access |
| * 0b1..Read Access Allowed |
| */ |
| #define RDC_PDAP_D1R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1R_SHIFT)) & RDC_PDAP_D1R_MASK) |
| #define RDC_PDAP_D2W_MASK (0x10U) |
| #define RDC_PDAP_D2W_SHIFT (4U) |
| /*! D2W - Domain 2 Write Access |
| * 0b0..No Write Access |
| * 0b1..Write Access Allowed |
| */ |
| #define RDC_PDAP_D2W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D2W_SHIFT)) & RDC_PDAP_D2W_MASK) |
| #define RDC_PDAP_D2R_MASK (0x20U) |
| #define RDC_PDAP_D2R_SHIFT (5U) |
| /*! D2R - Domain 2 Read Access |
| * 0b0..No Read Access |
| * 0b1..Read Access Allowed |
| */ |
| #define RDC_PDAP_D2R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D2R_SHIFT)) & RDC_PDAP_D2R_MASK) |
| #define RDC_PDAP_D3W_MASK (0x40U) |
| #define RDC_PDAP_D3W_SHIFT (6U) |
| /*! D3W - Domain 3 Write Access |
| * 0b0..No Write Access |
| * 0b1..Write Access Allowed |
| */ |
| #define RDC_PDAP_D3W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D3W_SHIFT)) & RDC_PDAP_D3W_MASK) |
| #define RDC_PDAP_D3R_MASK (0x80U) |
| #define RDC_PDAP_D3R_SHIFT (7U) |
| /*! D3R - Domain 3 Read Access |
| * 0b0..No Read Access |
| * 0b1..Read Access Allowed |
| */ |
| #define RDC_PDAP_D3R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D3R_SHIFT)) & RDC_PDAP_D3R_MASK) |
| #define RDC_PDAP_SREQ_MASK (0x40000000U) |
| #define RDC_PDAP_SREQ_SHIFT (30U) |
| /*! SREQ - Semaphore Required |
| * 0b0..Semaphores have no effect |
| * 0b1..Semaphores are enforced |
| */ |
| #define RDC_PDAP_SREQ(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_SREQ_SHIFT)) & RDC_PDAP_SREQ_MASK) |
| #define RDC_PDAP_LCK_MASK (0x80000000U) |
| #define RDC_PDAP_LCK_SHIFT (31U) |
| /*! LCK - Peripheral Permissions Lock |
| * 0b0..Not Locked |
| * 0b1..Locked |
| */ |
| #define RDC_PDAP_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_LCK_SHIFT)) & RDC_PDAP_LCK_MASK) |
| /*! @} */ |
| |
| /* The count of RDC_PDAP */ |
| #define RDC_PDAP_COUNT (118U) |
| |
| /*! @name MRSA - Memory Region Start Address */ |
| /*! @{ */ |
| #define RDC_MRSA_SADR_MASK (0xFFFFFF80U) |
| #define RDC_MRSA_SADR_SHIFT (7U) |
| #define RDC_MRSA_SADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRSA_SADR_SHIFT)) & RDC_MRSA_SADR_MASK) |
| /*! @} */ |
| |
| /* The count of RDC_MRSA */ |
| #define RDC_MRSA_COUNT (52U) |
| |
| /*! @name MREA - Memory Region End Address */ |
| /*! @{ */ |
| #define RDC_MREA_EADR_MASK (0xFFFFFF80U) |
| #define RDC_MREA_EADR_SHIFT (7U) |
| #define RDC_MREA_EADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MREA_EADR_SHIFT)) & RDC_MREA_EADR_MASK) |
| /*! @} */ |
| |
| /* The count of RDC_MREA */ |
| #define RDC_MREA_COUNT (52U) |
| |
| /*! @name MRC - Memory Region Control */ |
| /*! @{ */ |
| #define RDC_MRC_D0W_MASK (0x1U) |
| #define RDC_MRC_D0W_SHIFT (0U) |
| /*! D0W - Domain 0 Write Access to Region |
| * 0b0..Processing Domain 0 does not have Write access to the memory region |
| * 0b1..Processing Domain 0 has Write access to the memory region |
| */ |
| #define RDC_MRC_D0W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0W_SHIFT)) & RDC_MRC_D0W_MASK) |
| #define RDC_MRC_D0R_MASK (0x2U) |
| #define RDC_MRC_D0R_SHIFT (1U) |
| /*! D0R - Domain 0 Read Access to Region |
| * 0b0..Processing Domain 0 does not have Read access to the memory region |
| * 0b1..Processing Domain 0 has Read access to the memory region |
| */ |
| #define RDC_MRC_D0R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0R_SHIFT)) & RDC_MRC_D0R_MASK) |
| #define RDC_MRC_D1W_MASK (0x4U) |
| #define RDC_MRC_D1W_SHIFT (2U) |
| /*! D1W - Domain 1 Write Access to Region |
| * 0b0..Processing Domain 1 does not have Write access to the memory region |
| * 0b1..Processing Domain 1 has Write access to the memory region |
| */ |
| #define RDC_MRC_D1W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1W_SHIFT)) & RDC_MRC_D1W_MASK) |
| #define RDC_MRC_D1R_MASK (0x8U) |
| #define RDC_MRC_D1R_SHIFT (3U) |
| /*! D1R - Domain 1 Read Access to Region |
| * 0b0..Processing Domain 1 does not have Read access to the memory region |
| * 0b1..Processing Domain 1 has Read access to the memory region |
| */ |
| #define RDC_MRC_D1R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1R_SHIFT)) & RDC_MRC_D1R_MASK) |
| #define RDC_MRC_D2W_MASK (0x10U) |
| #define RDC_MRC_D2W_SHIFT (4U) |
| /*! D2W - Domain 2 Write Access to Region |
| * 0b0..Processing Domain 2 does not have Write access to the memory region |
| * 0b1..Processing Domain 2 has Write access to the memory region |
| */ |
| #define RDC_MRC_D2W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D2W_SHIFT)) & RDC_MRC_D2W_MASK) |
| #define RDC_MRC_D2R_MASK (0x20U) |
| #define RDC_MRC_D2R_SHIFT (5U) |
| /*! D2R - Domain 2 Read Access to Region |
| * 0b0..Processing Domain 2 does not have Read access to the memory region |
| * 0b1..Processing Domain 2 has Read access to the memory region |
| */ |
| #define RDC_MRC_D2R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D2R_SHIFT)) & RDC_MRC_D2R_MASK) |
| #define RDC_MRC_D3W_MASK (0x40U) |
| #define RDC_MRC_D3W_SHIFT (6U) |
| /*! D3W - Domain 3 Write Access to Region |
| * 0b0..Processing Domain 3 does not have Write access to the memory region |
| * 0b1..Processing Domain 3 has Read access to the memory region |
| */ |
| #define RDC_MRC_D3W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D3W_SHIFT)) & RDC_MRC_D3W_MASK) |
| #define RDC_MRC_D3R_MASK (0x80U) |
| #define RDC_MRC_D3R_SHIFT (7U) |
| /*! D3R - Domain 3 Read Access to Region |
| * 0b0..Processing Domain 3 does not have Read access to the memory region |
| * 0b1..Processing Domain 3 has Read access to the memory region |
| */ |
| #define RDC_MRC_D3R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D3R_SHIFT)) & RDC_MRC_D3R_MASK) |
| #define RDC_MRC_ENA_MASK (0x40000000U) |
| #define RDC_MRC_ENA_SHIFT (30U) |
| /*! ENA - Region Enable |
| * 0b0..Memory region is not defined or restricted. |
| * 0b1..Memory boundaries, domain permissions and controls are in effect. |
| */ |
| #define RDC_MRC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_ENA_SHIFT)) & RDC_MRC_ENA_MASK) |
| #define RDC_MRC_LCK_MASK (0x80000000U) |
| #define RDC_MRC_LCK_SHIFT (31U) |
| /*! LCK - Region Lock |
| * 0b0..No Lock. All fields in this register may be modified. |
| * 0b1..Locked. No fields in this register may be modified except ENA, which may be set but not cleared. |
| */ |
| #define RDC_MRC_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_LCK_SHIFT)) & RDC_MRC_LCK_MASK) |
| /*! @} */ |
| |
| /* The count of RDC_MRC */ |
| #define RDC_MRC_COUNT (52U) |
| |
| /*! @name MRVS - Memory Region Violation Status */ |
| /*! @{ */ |
| #define RDC_MRVS_VDID_MASK (0x3U) |
| #define RDC_MRVS_VDID_SHIFT (0U) |
| /*! VDID - Violating Domain ID |
| * 0b00..Processing Domain 0 |
| * 0b01..Processing Domain 1 |
| * 0b10..Processing Domain 2 |
| * 0b11..Processing Domain 3 |
| */ |
| #define RDC_MRVS_VDID(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VDID_SHIFT)) & RDC_MRVS_VDID_MASK) |
| #define RDC_MRVS_AD_MASK (0x10U) |
| #define RDC_MRVS_AD_SHIFT (4U) |
| #define RDC_MRVS_AD(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_AD_SHIFT)) & RDC_MRVS_AD_MASK) |
| #define RDC_MRVS_VADR_MASK (0xFFFFFFE0U) |
| #define RDC_MRVS_VADR_SHIFT (5U) |
| #define RDC_MRVS_VADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VADR_SHIFT)) & RDC_MRVS_VADR_MASK) |
| /*! @} */ |
| |
| /* The count of RDC_MRVS */ |
| #define RDC_MRVS_COUNT (52U) |
| |
| |
| /*! |
| * @} |
| */ /* end of group RDC_Register_Masks */ |
| |
| |
| /* RDC - Peripheral instance base addresses */ |
| /** Peripheral RDC base address */ |
| #define RDC_BASE (0x303D0000u) |
| /** Peripheral RDC base pointer */ |
| #define RDC ((RDC_Type *)RDC_BASE) |
| /** Array initializer of RDC peripheral base addresses */ |
| #define RDC_BASE_ADDRS { RDC_BASE } |
| /** Array initializer of RDC peripheral base pointers */ |
| #define RDC_BASE_PTRS { RDC } |
| /** Interrupt vectors for the RDC peripheral type */ |
| #define RDC_IRQS { RDC_IRQn } |
| |
| /*! |
| * @} |
| */ /* end of group RDC_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- RDC_SEMAPHORE Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup RDC_SEMAPHORE_Peripheral_Access_Layer RDC_SEMAPHORE Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** RDC_SEMAPHORE - Register Layout Typedef */ |
| typedef struct { |
| __IO uint8_t GATE0; /**< Gate Register, offset: 0x0 */ |
| __IO uint8_t GATE1; /**< Gate Register, offset: 0x1 */ |
| __IO uint8_t GATE2; /**< Gate Register, offset: 0x2 */ |
| __IO uint8_t GATE3; /**< Gate Register, offset: 0x3 */ |
| __IO uint8_t GATE4; /**< Gate Register, offset: 0x4 */ |
| __IO uint8_t GATE5; /**< Gate Register, offset: 0x5 */ |
| __IO uint8_t GATE6; /**< Gate Register, offset: 0x6 */ |
| __IO uint8_t GATE7; /**< Gate Register, offset: 0x7 */ |
| __IO uint8_t GATE8; /**< Gate Register, offset: 0x8 */ |
| __IO uint8_t GATE9; /**< Gate Register, offset: 0x9 */ |
| __IO uint8_t GATE10; /**< Gate Register, offset: 0xA */ |
| __IO uint8_t GATE11; /**< Gate Register, offset: 0xB */ |
| __IO uint8_t GATE12; /**< Gate Register, offset: 0xC */ |
| __IO uint8_t GATE13; /**< Gate Register, offset: 0xD */ |
| __IO uint8_t GATE14; /**< Gate Register, offset: 0xE */ |
| __IO uint8_t GATE15; /**< Gate Register, offset: 0xF */ |
| __IO uint8_t GATE16; /**< Gate Register, offset: 0x10 */ |
| __IO uint8_t GATE17; /**< Gate Register, offset: 0x11 */ |
| __IO uint8_t GATE18; /**< Gate Register, offset: 0x12 */ |
| __IO uint8_t GATE19; /**< Gate Register, offset: 0x13 */ |
| __IO uint8_t GATE20; /**< Gate Register, offset: 0x14 */ |
| __IO uint8_t GATE21; /**< Gate Register, offset: 0x15 */ |
| __IO uint8_t GATE22; /**< Gate Register, offset: 0x16 */ |
| __IO uint8_t GATE23; /**< Gate Register, offset: 0x17 */ |
| __IO uint8_t GATE24; /**< Gate Register, offset: 0x18 */ |
| __IO uint8_t GATE25; /**< Gate Register, offset: 0x19 */ |
| __IO uint8_t GATE26; /**< Gate Register, offset: 0x1A */ |
| __IO uint8_t GATE27; /**< Gate Register, offset: 0x1B */ |
| __IO uint8_t GATE28; /**< Gate Register, offset: 0x1C */ |
| __IO uint8_t GATE29; /**< Gate Register, offset: 0x1D */ |
| __IO uint8_t GATE30; /**< Gate Register, offset: 0x1E */ |
| __IO uint8_t GATE31; /**< Gate Register, offset: 0x1F */ |
| __IO uint8_t GATE32; /**< Gate Register, offset: 0x20 */ |
| __IO uint8_t GATE33; /**< Gate Register, offset: 0x21 */ |
| __IO uint8_t GATE34; /**< Gate Register, offset: 0x22 */ |
| __IO uint8_t GATE35; /**< Gate Register, offset: 0x23 */ |
| __IO uint8_t GATE36; /**< Gate Register, offset: 0x24 */ |
| __IO uint8_t GATE37; /**< Gate Register, offset: 0x25 */ |
| __IO uint8_t GATE38; /**< Gate Register, offset: 0x26 */ |
| __IO uint8_t GATE39; /**< Gate Register, offset: 0x27 */ |
| __IO uint8_t GATE40; /**< Gate Register, offset: 0x28 */ |
| __IO uint8_t GATE41; /**< Gate Register, offset: 0x29 */ |
| __IO uint8_t GATE42; /**< Gate Register, offset: 0x2A */ |
| __IO uint8_t GATE43; /**< Gate Register, offset: 0x2B */ |
| __IO uint8_t GATE44; /**< Gate Register, offset: 0x2C */ |
| __IO uint8_t GATE45; /**< Gate Register, offset: 0x2D */ |
| __IO uint8_t GATE46; /**< Gate Register, offset: 0x2E */ |
| __IO uint8_t GATE47; /**< Gate Register, offset: 0x2F */ |
| __IO uint8_t GATE48; /**< Gate Register, offset: 0x30 */ |
| __IO uint8_t GATE49; /**< Gate Register, offset: 0x31 */ |
| __IO uint8_t GATE50; /**< Gate Register, offset: 0x32 */ |
| __IO uint8_t GATE51; /**< Gate Register, offset: 0x33 */ |
| __IO uint8_t GATE52; /**< Gate Register, offset: 0x34 */ |
| __IO uint8_t GATE53; /**< Gate Register, offset: 0x35 */ |
| __IO uint8_t GATE54; /**< Gate Register, offset: 0x36 */ |
| __IO uint8_t GATE55; /**< Gate Register, offset: 0x37 */ |
| __IO uint8_t GATE56; /**< Gate Register, offset: 0x38 */ |
| __IO uint8_t GATE57; /**< Gate Register, offset: 0x39 */ |
| __IO uint8_t GATE58; /**< Gate Register, offset: 0x3A */ |
| __IO uint8_t GATE59; /**< Gate Register, offset: 0x3B */ |
| __IO uint8_t GATE60; /**< Gate Register, offset: 0x3C */ |
| __IO uint8_t GATE61; /**< Gate Register, offset: 0x3D */ |
| __IO uint8_t GATE62; /**< Gate Register, offset: 0x3E */ |
| __IO uint8_t GATE63; /**< Gate Register, offset: 0x3F */ |
| union { /* offset: 0x40 */ |
| __IO uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x40 */ |
| __IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x40 */ |
| }; |
| } RDC_SEMAPHORE_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- RDC_SEMAPHORE Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup RDC_SEMAPHORE_Register_Masks RDC_SEMAPHORE Register Masks |
| * @{ |
| */ |
| |
| /*! @name GATE0 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE0_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE0_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE0_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE0_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE0_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE0_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE0_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE0_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE0_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE0_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE1 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE1_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE1_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE1_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE1_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE1_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE1_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE1_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE1_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE1_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE1_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE2 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE2_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE2_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE2_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE2_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE2_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE2_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE2_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE2_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE2_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE2_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE3 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE3_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE3_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE3_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE3_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE3_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE3_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE3_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE3_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE3_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE3_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE4 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE4_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE4_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE4_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE4_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE4_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE4_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE4_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE4_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE4_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE4_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE5 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE5_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE5_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE5_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE5_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE5_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE5_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE5_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE5_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE5_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE5_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE6 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE6_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE6_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE6_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE6_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE6_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE6_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE6_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE6_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE6_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE6_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE7 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE7_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE7_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE7_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE7_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE7_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE7_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE7_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE7_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE7_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE7_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE8 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE8_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE8_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE8_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE8_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE8_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE8_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE8_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE8_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE8_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE8_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE9 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE9_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE9_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE9_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE9_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE9_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE9_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE9_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE9_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE9_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE9_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE10 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE10_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE10_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE10_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE10_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE10_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE10_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE10_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE10_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE10_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE10_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE11 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE11_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE11_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE11_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE11_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE11_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE11_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE11_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE11_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE11_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE11_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE12 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE12_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE12_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE12_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE12_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE12_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE12_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE12_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE12_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE12_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE13 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE13_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE13_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE13_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE13_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE13_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE13_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE13_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE13_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE13_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE13_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE14 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE14_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE14_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE14_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE14_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE14_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE14_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE14_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE14_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE14_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE14_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE15 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE15_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE15_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE15_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE15_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE15_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE15_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE15_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE15_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE15_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE15_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE16 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE16_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE16_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE16_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE16_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE16_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE16_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE16_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE16_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE16_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE16_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE17 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE17_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE17_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE17_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE17_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE17_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE17_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE17_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE17_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE17_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE17_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE18 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE18_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE18_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE18_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE18_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE18_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE18_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE18_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE18_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE18_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE18_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE19 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE19_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE19_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE19_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE19_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE19_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE19_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE19_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE19_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE19_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE19_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE20 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE20_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE20_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE20_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE20_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE20_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE20_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE20_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE20_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE20_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE20_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE21 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE21_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE21_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE21_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE21_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE21_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE21_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE21_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE21_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE21_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE21_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE22 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE22_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE22_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE22_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE22_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE22_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE22_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE22_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE22_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE22_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE22_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE23 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE23_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE23_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE23_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE23_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE23_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE23_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE23_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE23_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE23_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE23_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE24 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE24_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE24_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE24_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE24_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE24_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE24_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE24_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE24_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE24_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE24_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE25 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE25_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE25_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE25_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE25_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE25_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE25_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE25_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE25_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE25_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE25_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE26 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE26_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE26_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE26_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE26_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE26_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE26_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE26_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE26_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE26_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE26_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE27 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE27_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE27_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE27_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE27_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE27_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE27_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE27_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE27_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE27_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE27_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE28 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE28_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE28_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE28_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE28_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE28_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE28_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE28_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE28_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE28_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE28_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE29 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE29_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE29_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE29_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE29_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE29_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE29_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE29_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE29_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE29_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE29_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE30 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE30_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE30_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE30_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE30_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE30_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE30_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE30_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE30_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE30_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE30_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE31 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE31_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE31_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE31_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE31_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE31_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE31_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE31_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE31_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE31_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE31_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE32 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE32_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE32_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE32_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE32_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE32_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE32_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE32_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE32_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE32_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE32_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE33 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE33_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE33_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE33_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE33_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE33_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE33_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE33_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE33_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE33_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE33_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE34 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE34_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE34_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE34_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE34_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE34_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE34_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE34_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE34_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE34_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE34_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE35 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE35_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE35_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE35_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE35_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE35_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE35_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE35_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE35_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE35_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE35_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE36 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE36_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE36_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE36_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE36_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE36_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE36_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE36_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE36_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE36_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE36_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE37 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE37_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE37_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE37_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE37_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE37_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE37_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE37_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE37_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE37_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE37_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE38 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE38_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE38_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE38_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE38_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE38_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE38_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE38_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE38_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE38_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE38_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE39 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE39_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE39_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE39_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE39_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE39_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE39_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE39_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE39_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE39_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE39_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE40 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE40_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE40_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE40_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE40_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE40_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE40_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE40_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE40_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE40_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE40_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE41 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE41_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE41_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE41_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE41_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE41_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE41_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE41_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE41_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE41_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE41_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE42 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE42_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE42_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE42_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE42_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE42_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE42_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE42_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE42_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE42_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE42_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE43 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE43_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE43_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE43_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE43_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE43_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE43_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE43_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE43_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE43_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE43_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE44 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE44_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE44_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE44_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE44_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE44_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE44_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE44_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE44_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE44_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE44_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE45 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE45_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE45_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE45_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE45_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE45_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE45_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE45_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE45_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE45_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE45_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE46 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE46_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE46_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE46_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE46_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE46_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE46_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE46_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE46_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE46_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE46_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE47 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE47_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE47_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE47_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE47_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE47_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE47_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE47_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE47_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE47_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE47_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE48 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE48_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE48_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE48_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE48_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE48_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE48_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE48_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE48_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE48_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE48_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE49 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE49_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE49_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE49_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE49_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE49_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE49_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE49_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE49_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE49_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE49_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE50 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE50_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE50_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE50_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE50_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE50_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE50_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE50_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE50_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE50_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE50_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE51 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE51_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE51_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE51_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE51_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE51_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE51_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE51_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE51_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE51_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE51_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE52 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE52_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE52_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE52_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE52_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE52_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE52_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE52_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE52_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE52_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE52_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE53 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE53_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE53_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE53_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE53_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE53_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE53_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE53_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE53_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE53_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE53_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE54 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE54_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE54_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE54_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE54_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE54_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE54_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE54_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE54_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE54_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE54_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE55 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE55_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE55_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE55_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE55_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE55_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE55_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE55_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE55_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE55_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE55_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE56 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE56_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE56_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE56_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE56_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE56_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE56_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE56_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE56_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE56_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE56_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE57 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE57_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE57_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE57_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE57_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE57_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE57_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE57_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE57_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE57_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE57_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE58 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE58_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE58_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE58_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE58_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE58_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE58_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE58_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE58_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE58_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE58_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE59 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE59_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE59_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE59_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE59_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE59_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE59_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE59_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE59_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE59_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE59_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE60 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE60_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE60_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE60_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE60_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE60_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE60_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE60_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE60_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE60_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE60_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE61 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE61_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE61_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE61_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE61_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE61_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE61_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE61_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE61_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE61_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE61_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE62 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE62_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE62_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE62_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE62_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE62_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE62_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE62_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE62_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE62_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE62_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name GATE63 - Gate Register */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_GATE63_GTFSM_MASK (0xFU) |
| #define RDC_SEMAPHORE_GATE63_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b0000..The gate is unlocked (free). |
| * 0b0001..The gate has been locked by processor with master_index = 0. |
| * 0b0010..The gate has been locked by processor with master_index = 1. |
| * 0b0011..The gate has been locked by processor with master_index = 2. |
| * 0b0100..The gate has been locked by processor with master_index = 3. |
| * 0b0101..The gate has been locked by processor with master_index = 4. |
| * 0b0110..The gate has been locked by processor with master_index = 5. |
| * 0b0111..The gate has been locked by processor with master_index = 6. |
| * 0b1000..The gate has been locked by processor with master_index = 7. |
| * 0b1001..The gate has been locked by processor with master_index = 8. |
| * 0b1010..The gate has been locked by processor with master_index = 9. |
| * 0b1011..The gate has been locked by processor with master_index = 10. |
| * 0b1100..The gate has been locked by processor with master_index = 11. |
| * 0b1101..The gate has been locked by processor with master_index = 12. |
| * 0b1110..The gate has been locked by processor with master_index = 13. |
| * 0b1111..The gate has been locked by processor with master_index = 14. |
| */ |
| #define RDC_SEMAPHORE_GATE63_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE63_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE63_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE63_LDOM_MASK (0x30U) |
| #define RDC_SEMAPHORE_GATE63_LDOM_SHIFT (4U) |
| /*! LDOM |
| * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) |
| * 0b01..The gate has been locked by domain 1. |
| * 0b10..The gate has been locked by domain 2. |
| * 0b11..The gate has been locked by domain 3. |
| */ |
| #define RDC_SEMAPHORE_GATE63_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE63_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE63_LDOM_MASK) |
| /*! @} */ |
| |
| /*! @name RSTGT_R - Reset Gate Read */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK (0xFU) |
| #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT (0U) |
| #define RDC_SEMAPHORE_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK) |
| #define RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK (0x30U) |
| #define RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT (4U) |
| /*! RSTGSM |
| * 0b00..Idle, waiting for the first data pattern write. |
| * 0b01..Waiting for the second data pattern write. |
| * 0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, this machine returns to the idle (waiting for first data pattern write) state. The "01" state persists for only one clock cycle. Software will never be able to observe this state. |
| * 0b11..This state encoding is never used and therefore reserved. |
| */ |
| #define RDC_SEMAPHORE_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK) |
| #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK (0xFF00U) |
| #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT (8U) |
| #define RDC_SEMAPHORE_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK) |
| /*! @} */ |
| |
| /*! @name RSTGT_W - Reset Gate Write */ |
| /*! @{ */ |
| #define RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK (0xFFU) |
| #define RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT (0U) |
| #define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK) |
| #define RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK (0xFF00U) |
| #define RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT (8U) |
| #define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group RDC_SEMAPHORE_Register_Masks */ |
| |
| |
| /* RDC_SEMAPHORE - Peripheral instance base addresses */ |
| /** Peripheral RDC_SEMAPHORE1 base address */ |
| #define RDC_SEMAPHORE1_BASE (0x303B0000u) |
| /** Peripheral RDC_SEMAPHORE1 base pointer */ |
| #define RDC_SEMAPHORE1 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE1_BASE) |
| /** Peripheral RDC_SEMAPHORE2 base address */ |
| #define RDC_SEMAPHORE2_BASE (0x303C0000u) |
| /** Peripheral RDC_SEMAPHORE2 base pointer */ |
| #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE) |
| /** Array initializer of RDC_SEMAPHORE peripheral base addresses */ |
| #define RDC_SEMAPHORE_BASE_ADDRS { 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE } |
| /** Array initializer of RDC_SEMAPHORE peripheral base pointers */ |
| #define RDC_SEMAPHORE_BASE_PTRS { (RDC_SEMAPHORE_Type *)0u, RDC_SEMAPHORE1, RDC_SEMAPHORE2 } |
| |
| /*! |
| * @} |
| */ /* end of group RDC_SEMAPHORE_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- RD_SRC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup RD_SRC_Peripheral_Access_Layer RD_SRC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** RD_SRC - Register Layout Typedef */ |
| typedef struct { |
| struct { /* offset: 0x0 */ |
| __IO uint32_t RW; /**< Control register for Read surface., offset: 0x0 */ |
| __IO uint32_t SET; /**< Control register for Read surface., offset: 0x4 */ |
| __IO uint32_t CLR; /**< Control register for Read surface., offset: 0x8 */ |
| __IO uint32_t TOG; /**< Control register for Read surface., offset: 0xC */ |
| } CTRL_STATUS; |
| __IO uint32_t BASE_ADDR; /**< Read Surface Base address, offset: 0x10 */ |
| __IO uint32_t PITCH; /**< Read surface vertical pitch, offset: 0x14 */ |
| __IO uint32_t WIDTH; /**< Source frame buffer width, offset: 0x18 */ |
| __IO uint32_t HEIGHT; /**< Height of frame to be read, offset: 0x1C */ |
| } RD_SRC_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- RD_SRC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup RD_SRC_Register_Masks RD_SRC Register Masks |
| * @{ |
| */ |
| |
| /*! @name CTRL_STATUS - Control register for Read surface. */ |
| /*! @{ */ |
| #define RD_SRC_CTRL_STATUS_ENABLE_MASK (0x1U) |
| #define RD_SRC_CTRL_STATUS_ENABLE_SHIFT (0U) |
| #define RD_SRC_CTRL_STATUS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_ENABLE_SHIFT)) & RD_SRC_CTRL_STATUS_ENABLE_MASK) |
| #define RD_SRC_CTRL_STATUS_BPP_MASK (0x1CU) |
| #define RD_SRC_CTRL_STATUS_BPP_SHIFT (2U) |
| #define RD_SRC_CTRL_STATUS_BPP(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_BPP_SHIFT)) & RD_SRC_CTRL_STATUS_BPP_MASK) |
| #define RD_SRC_CTRL_STATUS_T_SIZE_MASK (0x60U) |
| #define RD_SRC_CTRL_STATUS_T_SIZE_SHIFT (5U) |
| #define RD_SRC_CTRL_STATUS_T_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_T_SIZE_SHIFT)) & RD_SRC_CTRL_STATUS_T_SIZE_MASK) |
| #define RD_SRC_CTRL_STATUS_P_SIZE_MASK (0x380U) |
| #define RD_SRC_CTRL_STATUS_P_SIZE_SHIFT (7U) |
| #define RD_SRC_CTRL_STATUS_P_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_P_SIZE_SHIFT)) & RD_SRC_CTRL_STATUS_P_SIZE_MASK) |
| #define RD_SRC_CTRL_STATUS_FRAME_COMP_EN_MASK (0x4000U) |
| #define RD_SRC_CTRL_STATUS_FRAME_COMP_EN_SHIFT (14U) |
| #define RD_SRC_CTRL_STATUS_FRAME_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_FRAME_COMP_EN_SHIFT)) & RD_SRC_CTRL_STATUS_FRAME_COMP_EN_MASK) |
| #define RD_SRC_CTRL_STATUS_RD_ERR_EN_MASK (0x8000U) |
| #define RD_SRC_CTRL_STATUS_RD_ERR_EN_SHIFT (15U) |
| #define RD_SRC_CTRL_STATUS_RD_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_RD_ERR_EN_SHIFT)) & RD_SRC_CTRL_STATUS_RD_ERR_EN_MASK) |
| #define RD_SRC_CTRL_STATUS_FIFO_SIZE_MASK (0x7F0000U) |
| #define RD_SRC_CTRL_STATUS_FIFO_SIZE_SHIFT (16U) |
| #define RD_SRC_CTRL_STATUS_FIFO_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_FIFO_SIZE_SHIFT)) & RD_SRC_CTRL_STATUS_FIFO_SIZE_MASK) |
| #define RD_SRC_CTRL_STATUS_FRAME_COMP_MASK (0x40000000U) |
| #define RD_SRC_CTRL_STATUS_FRAME_COMP_SHIFT (30U) |
| #define RD_SRC_CTRL_STATUS_FRAME_COMP(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_FRAME_COMP_SHIFT)) & RD_SRC_CTRL_STATUS_FRAME_COMP_MASK) |
| #define RD_SRC_CTRL_STATUS_RD_ERR_MASK (0x80000000U) |
| #define RD_SRC_CTRL_STATUS_RD_ERR_SHIFT (31U) |
| #define RD_SRC_CTRL_STATUS_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_CTRL_STATUS_RD_ERR_SHIFT)) & RD_SRC_CTRL_STATUS_RD_ERR_MASK) |
| /*! @} */ |
| |
| /*! @name BASE_ADDR - Read Surface Base address */ |
| /*! @{ */ |
| #define RD_SRC_BASE_ADDR_BASE_ADDR_MASK (0xFFFFFFFFU) |
| #define RD_SRC_BASE_ADDR_BASE_ADDR_SHIFT (0U) |
| #define RD_SRC_BASE_ADDR_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_BASE_ADDR_BASE_ADDR_SHIFT)) & RD_SRC_BASE_ADDR_BASE_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name PITCH - Read surface vertical pitch */ |
| /*! @{ */ |
| #define RD_SRC_PITCH_PITCH_MASK (0xFFFFU) |
| #define RD_SRC_PITCH_PITCH_SHIFT (0U) |
| #define RD_SRC_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_PITCH_PITCH_SHIFT)) & RD_SRC_PITCH_PITCH_MASK) |
| /*! @} */ |
| |
| /*! @name WIDTH - Source frame buffer width */ |
| /*! @{ */ |
| #define RD_SRC_WIDTH_WIDTH_MASK (0xFFFFU) |
| #define RD_SRC_WIDTH_WIDTH_SHIFT (0U) |
| #define RD_SRC_WIDTH_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_WIDTH_WIDTH_SHIFT)) & RD_SRC_WIDTH_WIDTH_MASK) |
| /*! @} */ |
| |
| /*! @name HEIGHT - Height of frame to be read */ |
| /*! @{ */ |
| #define RD_SRC_HEIGHT_HEIGHT_MASK (0xFFFFU) |
| #define RD_SRC_HEIGHT_HEIGHT_SHIFT (0U) |
| #define RD_SRC_HEIGHT_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << RD_SRC_HEIGHT_HEIGHT_SHIFT)) & RD_SRC_HEIGHT_HEIGHT_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group RD_SRC_Register_Masks */ |
| |
| |
| /* RD_SRC - Peripheral instance base addresses */ |
| /** Peripheral DCSS__RD_SRC base address */ |
| #define DCSS__RD_SRC_BASE (0x32E22000u) |
| /** Peripheral DCSS__RD_SRC base pointer */ |
| #define DCSS__RD_SRC ((RD_SRC_Type *)DCSS__RD_SRC_BASE) |
| /** Array initializer of RD_SRC peripheral base addresses */ |
| #define RD_SRC_BASE_ADDRS { DCSS__RD_SRC_BASE } |
| /** Array initializer of RD_SRC peripheral base pointers */ |
| #define RD_SRC_BASE_PTRS { DCSS__RD_SRC } |
| |
| /*! |
| * @} |
| */ /* end of group RD_SRC_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- ROMC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** ROMC - Register Layout Typedef */ |
| typedef struct { |
| uint8_t RESERVED_0[212]; |
| __IO uint32_t ROMPATCHD[8]; /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */ |
| __IO uint32_t ROMPATCHCNTL; /**< ROMC Control Register, offset: 0xF4 */ |
| uint32_t ROMPATCHENH; /**< ROMC Enable Register High, offset: 0xF8 */ |
| __IO uint32_t ROMPATCHENL; /**< ROMC Enable Register Low, offset: 0xFC */ |
| __IO uint32_t ROMPATCHA[16]; /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */ |
| uint8_t RESERVED_1[200]; |
| __IO uint32_t ROMPATCHSR; /**< ROMC Status Register, offset: 0x208 */ |
| } ROMC_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- ROMC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ROMC_Register_Masks ROMC Register Masks |
| * @{ |
| */ |
| |
| /*! @name ROMPATCHD - ROMC Data Registers */ |
| /*! @{ */ |
| #define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU) |
| #define ROMC_ROMPATCHD_DATAX_SHIFT (0U) |
| #define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK) |
| /*! @} */ |
| |
| /* The count of ROMC_ROMPATCHD */ |
| #define ROMC_ROMPATCHD_COUNT (8U) |
| |
| /*! @name ROMPATCHCNTL - ROMC Control Register */ |
| /*! @{ */ |
| #define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU) |
| #define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U) |
| /*! DATAFIX |
| * 0b00000000..Address comparator triggers a opcode patch |
| * 0b00000001..Address comparator triggers a data fix |
| */ |
| #define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK) |
| #define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U) |
| #define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U) |
| /*! DIS |
| * 0b0..Does not affect any ROMC functions (default) |
| * 0b1..Disable all ROMC functions: data fixing, and opcode patching |
| */ |
| #define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK) |
| /*! @} */ |
| |
| /*! @name ROMPATCHENL - ROMC Enable Register Low */ |
| /*! @{ */ |
| #define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU) |
| #define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U) |
| /*! ENABLE |
| * 0b0000000000000000..Address comparator disabled |
| * 0b0000000000000001..Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address |
| */ |
| #define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK) |
| /*! @} */ |
| |
| /*! @name ROMPATCHA - ROMC Address Registers */ |
| /*! @{ */ |
| #define ROMC_ROMPATCHA_THUMBX_MASK (0x1U) |
| #define ROMC_ROMPATCHA_THUMBX_SHIFT (0U) |
| /*! THUMBX |
| * 0b0..Arm patch |
| * 0b1..THUMB patch (ignore if data fix) |
| */ |
| #define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK) |
| #define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU) |
| #define ROMC_ROMPATCHA_ADDRX_SHIFT (1U) |
| #define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK) |
| /*! @} */ |
| |
| /* The count of ROMC_ROMPATCHA */ |
| #define ROMC_ROMPATCHA_COUNT (16U) |
| |
| /*! @name ROMPATCHSR - ROMC Status Register */ |
| /*! @{ */ |
| #define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU) |
| #define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U) |
| /*! SOURCE |
| * 0b000000..Address Comparator 0 matched |
| * 0b000001..Address Comparator 1 matched |
| * 0b001111..Address Comparator 15 matched |
| */ |
| #define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK) |
| #define ROMC_ROMPATCHSR_SW_MASK (0x20000U) |
| #define ROMC_ROMPATCHSR_SW_SHIFT (17U) |
| /*! SW |
| * 0b0..no event or comparator collisions |
| * 0b1..a collision has occurred |
| */ |
| #define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group ROMC_Register_Masks */ |
| |
| |
| /* ROMC - Peripheral instance base addresses */ |
| /** Peripheral ROMC base address */ |
| #define ROMC_BASE (0x30310000u) |
| /** Peripheral ROMC base pointer */ |
| #define ROMC ((ROMC_Type *)ROMC_BASE) |
| /** Array initializer of ROMC peripheral base addresses */ |
| #define ROMC_BASE_ADDRS { ROMC_BASE } |
| /** Array initializer of ROMC peripheral base pointers */ |
| #define ROMC_BASE_PTRS { ROMC } |
| |
| /*! |
| * @} |
| */ /* end of group ROMC_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- SDMAARM Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SDMAARM_Peripheral_Access_Layer SDMAARM Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** SDMAARM - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t MC0PTR; /**< Arm platform Channel 0 Pointer, offset: 0x0 */ |
| __IO uint32_t INTR; /**< Channel Interrupts, offset: 0x4 */ |
| __IO uint32_t STOP_STAT; /**< Channel Stop/Channel Status, offset: 0x8 */ |
| __IO uint32_t HSTART; /**< Channel Start, offset: 0xC */ |
| __IO uint32_t EVTOVR; /**< Channel Event Override, offset: 0x10 */ |
| __IO uint32_t DSPOVR; /**< Channel BP Override, offset: 0x14 */ |
| __IO uint32_t HOSTOVR; /**< Channel Arm platform Override, offset: 0x18 */ |
| __IO uint32_t EVTPEND; /**< Channel Event Pending, offset: 0x1C */ |
| uint8_t RESERVED_0[4]; |
| __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ |
| __I uint32_t EVTERR; /**< DMA Request Error Register, offset: 0x28 */ |
| __IO uint32_t INTRMASK; /**< Channel Arm platform Interrupt Mask, offset: 0x2C */ |
| __I uint32_t PSW; /**< Schedule Status, offset: 0x30 */ |
| __I uint32_t EVTERRDBG; /**< DMA Request Error Register, offset: 0x34 */ |
| __IO uint32_t CONFIG; /**< Configuration Register, offset: 0x38 */ |
| __IO uint32_t SDMA_LOCK; /**< SDMA LOCK, offset: 0x3C */ |
| __IO uint32_t ONCE_ENB; /**< OnCE Enable, offset: 0x40 */ |
| __IO uint32_t ONCE_DATA; /**< OnCE Data Register, offset: 0x44 */ |
| __IO uint32_t ONCE_INSTR; /**< OnCE Instruction Register, offset: 0x48 */ |
| __I uint32_t ONCE_STAT; /**< OnCE Status Register, offset: 0x4C */ |
| __IO uint32_t ONCE_CMD; /**< OnCE Command Register, offset: 0x50 */ |
| uint8_t RESERVED_1[4]; |
| __IO uint32_t ILLINSTADDR; /**< Illegal Instruction Trap Address, offset: 0x58 */ |
| __IO uint32_t CHN0ADDR; /**< Channel 0 Boot Address, offset: 0x5C */ |
| __I uint32_t EVT_MIRROR; /**< DMA Requests, offset: 0x60 */ |
| __I uint32_t EVT_MIRROR2; /**< DMA Requests 2, offset: 0x64 */ |
| uint8_t RESERVED_2[8]; |
| __IO uint32_t XTRIG_CONF1; /**< Cross-Trigger Events Configuration Register 1, offset: 0x70 */ |
| __IO uint32_t XTRIG_CONF2; /**< Cross-Trigger Events Configuration Register 2, offset: 0x74 */ |
| uint8_t RESERVED_3[136]; |
| __IO uint32_t SDMA_CHNPRI[32]; /**< Channel Priority Registers, array offset: 0x100, array step: 0x4 */ |
| uint8_t RESERVED_4[128]; |
| __IO uint32_t CHNENBL[48]; /**< Channel Enable RAM, array offset: 0x200, array step: 0x4 */ |
| } SDMAARM_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- SDMAARM Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SDMAARM_Register_Masks SDMAARM Register Masks |
| * @{ |
| */ |
| |
| /*! @name MC0PTR - Arm platform Channel 0 Pointer */ |
| /*! @{ */ |
| #define SDMAARM_MC0PTR_MC0PTR_MASK (0xFFFFFFFFU) |
| #define SDMAARM_MC0PTR_MC0PTR_SHIFT (0U) |
| #define SDMAARM_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_MC0PTR_MC0PTR_SHIFT)) & SDMAARM_MC0PTR_MC0PTR_MASK) |
| /*! @} */ |
| |
| /*! @name INTR - Channel Interrupts */ |
| /*! @{ */ |
| #define SDMAARM_INTR_HI_MASK (0xFFFFFFFFU) |
| #define SDMAARM_INTR_HI_SHIFT (0U) |
| #define SDMAARM_INTR_HI(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTR_HI_SHIFT)) & SDMAARM_INTR_HI_MASK) |
| /*! @} */ |
| |
| /*! @name STOP_STAT - Channel Stop/Channel Status */ |
| /*! @{ */ |
| #define SDMAARM_STOP_STAT_HE_MASK (0xFFFFFFFFU) |
| #define SDMAARM_STOP_STAT_HE_SHIFT (0U) |
| #define SDMAARM_STOP_STAT_HE(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_STOP_STAT_HE_SHIFT)) & SDMAARM_STOP_STAT_HE_MASK) |
| /*! @} */ |
| |
| /*! @name HSTART - Channel Start */ |
| /*! @{ */ |
| #define SDMAARM_HSTART_HSTART_HE_MASK (0xFFFFFFFFU) |
| #define SDMAARM_HSTART_HSTART_HE_SHIFT (0U) |
| #define SDMAARM_HSTART_HSTART_HE(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_HSTART_HSTART_HE_SHIFT)) & SDMAARM_HSTART_HSTART_HE_MASK) |
| /*! @} */ |
| |
| /*! @name EVTOVR - Channel Event Override */ |
| /*! @{ */ |
| #define SDMAARM_EVTOVR_EO_MASK (0xFFFFFFFFU) |
| #define SDMAARM_EVTOVR_EO_SHIFT (0U) |
| #define SDMAARM_EVTOVR_EO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTOVR_EO_SHIFT)) & SDMAARM_EVTOVR_EO_MASK) |
| /*! @} */ |
| |
| /*! @name DSPOVR - Channel BP Override */ |
| /*! @{ */ |
| #define SDMAARM_DSPOVR_DO_MASK (0xFFFFFFFFU) |
| #define SDMAARM_DSPOVR_DO_SHIFT (0U) |
| /*! DO |
| * 0b00000000000000000000000000000000..- Reserved |
| * 0b00000000000000000000000000000001..- Reset value. |
| */ |
| #define SDMAARM_DSPOVR_DO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DSPOVR_DO_SHIFT)) & SDMAARM_DSPOVR_DO_MASK) |
| /*! @} */ |
| |
| /*! @name HOSTOVR - Channel Arm platform Override */ |
| /*! @{ */ |
| #define SDMAARM_HOSTOVR_HO_MASK (0xFFFFFFFFU) |
| #define SDMAARM_HOSTOVR_HO_SHIFT (0U) |
| #define SDMAARM_HOSTOVR_HO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_HOSTOVR_HO_SHIFT)) & SDMAARM_HOSTOVR_HO_MASK) |
| /*! @} */ |
| |
| /*! @name EVTPEND - Channel Event Pending */ |
| /*! @{ */ |
| #define SDMAARM_EVTPEND_EP_MASK (0xFFFFFFFFU) |
| #define SDMAARM_EVTPEND_EP_SHIFT (0U) |
| #define SDMAARM_EVTPEND_EP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTPEND_EP_SHIFT)) & SDMAARM_EVTPEND_EP_MASK) |
| /*! @} */ |
| |
| /*! @name RESET - Reset Register */ |
| /*! @{ */ |
| #define SDMAARM_RESET_RESET_MASK (0x1U) |
| #define SDMAARM_RESET_RESET_SHIFT (0U) |
| #define SDMAARM_RESET_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESET_SHIFT)) & SDMAARM_RESET_RESET_MASK) |
| #define SDMAARM_RESET_RESCHED_MASK (0x2U) |
| #define SDMAARM_RESET_RESCHED_SHIFT (1U) |
| #define SDMAARM_RESET_RESCHED(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESCHED_SHIFT)) & SDMAARM_RESET_RESCHED_MASK) |
| /*! @} */ |
| |
| /*! @name EVTERR - DMA Request Error Register */ |
| /*! @{ */ |
| #define SDMAARM_EVTERR_CHNERR_MASK (0xFFFFFFFFU) |
| #define SDMAARM_EVTERR_CHNERR_SHIFT (0U) |
| #define SDMAARM_EVTERR_CHNERR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERR_CHNERR_SHIFT)) & SDMAARM_EVTERR_CHNERR_MASK) |
| /*! @} */ |
| |
| /*! @name INTRMASK - Channel Arm platform Interrupt Mask */ |
| /*! @{ */ |
| #define SDMAARM_INTRMASK_HIMASK_MASK (0xFFFFFFFFU) |
| #define SDMAARM_INTRMASK_HIMASK_SHIFT (0U) |
| #define SDMAARM_INTRMASK_HIMASK(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTRMASK_HIMASK_SHIFT)) & SDMAARM_INTRMASK_HIMASK_MASK) |
| /*! @} */ |
| |
| /*! @name PSW - Schedule Status */ |
| /*! @{ */ |
| #define SDMAARM_PSW_CCR_MASK (0xFU) |
| #define SDMAARM_PSW_CCR_SHIFT (0U) |
| #define SDMAARM_PSW_CCR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCR_SHIFT)) & SDMAARM_PSW_CCR_MASK) |
| #define SDMAARM_PSW_CCP_MASK (0xF0U) |
| #define SDMAARM_PSW_CCP_SHIFT (4U) |
| /*! CCP |
| * 0b0000..No running channel |
| * 0b0001..Active channel priority |
| */ |
| #define SDMAARM_PSW_CCP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCP_SHIFT)) & SDMAARM_PSW_CCP_MASK) |
| #define SDMAARM_PSW_NCR_MASK (0x1F00U) |
| #define SDMAARM_PSW_NCR_SHIFT (8U) |
| #define SDMAARM_PSW_NCR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCR_SHIFT)) & SDMAARM_PSW_NCR_MASK) |
| #define SDMAARM_PSW_NCP_MASK (0xE000U) |
| #define SDMAARM_PSW_NCP_SHIFT (13U) |
| /*! NCP |
| * 0b000..No running channel |
| * 0b001..Active channel priority |
| */ |
| #define SDMAARM_PSW_NCP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCP_SHIFT)) & SDMAARM_PSW_NCP_MASK) |
| /*! @} */ |
| |
| /*! @name EVTERRDBG - DMA Request Error Register */ |
| /*! @{ */ |
| #define SDMAARM_EVTERRDBG_CHNERR_MASK (0xFFFFFFFFU) |
| #define SDMAARM_EVTERRDBG_CHNERR_SHIFT (0U) |
| #define SDMAARM_EVTERRDBG_CHNERR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERRDBG_CHNERR_SHIFT)) & SDMAARM_EVTERRDBG_CHNERR_MASK) |
| /*! @} */ |
| |
| /*! @name CONFIG - Configuration Register */ |
| /*! @{ */ |
| #define SDMAARM_CONFIG_CSM_MASK (0x3U) |
| #define SDMAARM_CONFIG_CSM_SHIFT (0U) |
| /*! CSM |
| * 0b00..static |
| * 0b01..dynamic low power |
| * 0b10..dynamic with no loop |
| * 0b11..dynamic |
| */ |
| #define SDMAARM_CONFIG_CSM(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_CSM_SHIFT)) & SDMAARM_CONFIG_CSM_MASK) |
| #define SDMAARM_CONFIG_ACR_MASK (0x10U) |
| #define SDMAARM_CONFIG_ACR_SHIFT (4U) |
| /*! ACR |
| * 0b0..Arm platform DMA interface frequency equals twice core frequency |
| * 0b1..Arm platform DMA interface frequency equals core frequency |
| */ |
| #define SDMAARM_CONFIG_ACR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_ACR_SHIFT)) & SDMAARM_CONFIG_ACR_MASK) |
| #define SDMAARM_CONFIG_RTDOBS_MASK (0x800U) |
| #define SDMAARM_CONFIG_RTDOBS_SHIFT (11U) |
| /*! RTDOBS |
| * 0b0..RTD pins disabled |
| * 0b1..RTD pins enabled |
| */ |
| #define SDMAARM_CONFIG_RTDOBS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_RTDOBS_SHIFT)) & SDMAARM_CONFIG_RTDOBS_MASK) |
| #define SDMAARM_CONFIG_DSPDMA_MASK (0x1000U) |
| #define SDMAARM_CONFIG_DSPDMA_SHIFT (12U) |
| /*! DSPDMA |
| * 0b0..- Reset Value |
| * 0b1..- Reserved |
| */ |
| #define SDMAARM_CONFIG_DSPDMA(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_DSPDMA_SHIFT)) & SDMAARM_CONFIG_DSPDMA_MASK) |
| /*! @} */ |
| |
| /*! @name SDMA_LOCK - SDMA LOCK */ |
| /*! @{ */ |
| #define SDMAARM_SDMA_LOCK_LOCK_MASK (0x1U) |
| #define SDMAARM_SDMA_LOCK_LOCK_SHIFT (0U) |
| /*! LOCK |
| * 0b0..LOCK disengaged. |
| * 0b1..LOCK enabled. |
| */ |
| #define SDMAARM_SDMA_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_LOCK_SHIFT)) & SDMAARM_SDMA_LOCK_LOCK_MASK) |
| #define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK (0x2U) |
| #define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT (1U) |
| /*! SRESET_LOCK_CLR |
| * 0b0..Software Reset does not clear the LOCK bit. |
| * 0b1..Software Reset clears the LOCK bit. |
| */ |
| #define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT)) & SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK) |
| /*! @} */ |
| |
| /*! @name ONCE_ENB - OnCE Enable */ |
| /*! @{ */ |
| #define SDMAARM_ONCE_ENB_ENB_MASK (0x1U) |
| #define SDMAARM_ONCE_ENB_ENB_SHIFT (0U) |
| #define SDMAARM_ONCE_ENB_ENB(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_ENB_ENB_SHIFT)) & SDMAARM_ONCE_ENB_ENB_MASK) |
| /*! @} */ |
| |
| /*! @name ONCE_DATA - OnCE Data Register */ |
| /*! @{ */ |
| #define SDMAARM_ONCE_DATA_DATA_MASK (0xFFFFFFFFU) |
| #define SDMAARM_ONCE_DATA_DATA_SHIFT (0U) |
| #define SDMAARM_ONCE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_DATA_DATA_SHIFT)) & SDMAARM_ONCE_DATA_DATA_MASK) |
| /*! @} */ |
| |
| /*! @name ONCE_INSTR - OnCE Instruction Register */ |
| /*! @{ */ |
| #define SDMAARM_ONCE_INSTR_INSTR_MASK (0xFFFFU) |
| #define SDMAARM_ONCE_INSTR_INSTR_SHIFT (0U) |
| #define SDMAARM_ONCE_INSTR_INSTR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_INSTR_INSTR_SHIFT)) & SDMAARM_ONCE_INSTR_INSTR_MASK) |
| /*! @} */ |
| |
| /*! @name ONCE_STAT - OnCE Status Register */ |
| /*! @{ */ |
| #define SDMAARM_ONCE_STAT_ECDR_MASK (0x7U) |
| #define SDMAARM_ONCE_STAT_ECDR_SHIFT (0U) |
| /*! ECDR |
| * 0b000..1 matched addra_cond |
| * 0b001..1 matched addrb_cond |
| * 0b010..1 matched data_cond |
| */ |
| #define SDMAARM_ONCE_STAT_ECDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ECDR_SHIFT)) & SDMAARM_ONCE_STAT_ECDR_MASK) |
| #define SDMAARM_ONCE_STAT_MST_MASK (0x80U) |
| #define SDMAARM_ONCE_STAT_MST_SHIFT (7U) |
| /*! MST |
| * 0b0..The JTAG interface controls the OnCE. |
| * 0b1..The Arm platform peripheral interface controls the OnCE. |
| */ |
| #define SDMAARM_ONCE_STAT_MST(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_MST_SHIFT)) & SDMAARM_ONCE_STAT_MST_MASK) |
| #define SDMAARM_ONCE_STAT_SWB_MASK (0x100U) |
| #define SDMAARM_ONCE_STAT_SWB_SHIFT (8U) |
| #define SDMAARM_ONCE_STAT_SWB(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_SWB_SHIFT)) & SDMAARM_ONCE_STAT_SWB_MASK) |
| #define SDMAARM_ONCE_STAT_ODR_MASK (0x200U) |
| #define SDMAARM_ONCE_STAT_ODR_SHIFT (9U) |
| #define SDMAARM_ONCE_STAT_ODR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ODR_SHIFT)) & SDMAARM_ONCE_STAT_ODR_MASK) |
| #define SDMAARM_ONCE_STAT_EDR_MASK (0x400U) |
| #define SDMAARM_ONCE_STAT_EDR_SHIFT (10U) |
| #define SDMAARM_ONCE_STAT_EDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_EDR_SHIFT)) & SDMAARM_ONCE_STAT_EDR_MASK) |
| #define SDMAARM_ONCE_STAT_RCV_MASK (0x800U) |
| #define SDMAARM_ONCE_STAT_RCV_SHIFT (11U) |
| #define SDMAARM_ONCE_STAT_RCV(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_RCV_SHIFT)) & SDMAARM_ONCE_STAT_RCV_MASK) |
| #define SDMAARM_ONCE_STAT_PST_MASK (0xF000U) |
| #define SDMAARM_ONCE_STAT_PST_SHIFT (12U) |
| /*! PST |
| * 0b0000..Program |
| * 0b0001..Data |
| * 0b0010..Change of Flow |
| * 0b0011..Change of Flow in Loop |
| * 0b0100..Debug |
| * 0b0101..Functional Unit |
| * 0b0110..Sleep |
| * 0b0111..Save |
| * 0b1000..Program in Sleep |
| * 0b1001..Data in Sleep |
| * 0b0010..Change of Flow in Sleep |
| * 0b0011..Change Flow in Loop in Sleep |
| * 0b1100..Debug in Sleep |
| * 0b1101..Functional Unit in Sleep |
| * 0b1110..Sleep after Reset |
| * 0b1111..Restore |
| */ |
| #define SDMAARM_ONCE_STAT_PST(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_PST_SHIFT)) & SDMAARM_ONCE_STAT_PST_MASK) |
| /*! @} */ |
| |
| /*! @name ONCE_CMD - OnCE Command Register */ |
| /*! @{ */ |
| #define SDMAARM_ONCE_CMD_CMD_MASK (0xFU) |
| #define SDMAARM_ONCE_CMD_CMD_SHIFT (0U) |
| /*! CMD |
| * 0b0000..rstatus |
| * 0b0001..dmov |
| * 0b0010..exec_once |
| * 0b0011..run_core |
| * 0b0100..exec_core |
| * 0b0101..debug_rqst |
| * 0b0110..rbuffer |
| */ |
| #define SDMAARM_ONCE_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_CMD_CMD_SHIFT)) & SDMAARM_ONCE_CMD_CMD_MASK) |
| /*! @} */ |
| |
| /*! @name ILLINSTADDR - Illegal Instruction Trap Address */ |
| /*! @{ */ |
| #define SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK (0x3FFFU) |
| #define SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT (0U) |
| #define SDMAARM_ILLINSTADDR_ILLINSTADDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT)) & SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK) |
| /*! @} */ |
| |
| /*! @name CHN0ADDR - Channel 0 Boot Address */ |
| /*! @{ */ |
| #define SDMAARM_CHN0ADDR_CHN0ADDR_MASK (0x3FFFU) |
| #define SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT (0U) |
| #define SDMAARM_CHN0ADDR_CHN0ADDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT)) & SDMAARM_CHN0ADDR_CHN0ADDR_MASK) |
| #define SDMAARM_CHN0ADDR_SMSZ_MASK (0x4000U) |
| #define SDMAARM_CHN0ADDR_SMSZ_SHIFT (14U) |
| /*! SMSZ |
| * 0b0..24 words per context |
| * 0b1..32 words per context |
| */ |
| #define SDMAARM_CHN0ADDR_SMSZ(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_SMSZ_SHIFT)) & SDMAARM_CHN0ADDR_SMSZ_MASK) |
| /*! @} */ |
| |
| /*! @name EVT_MIRROR - DMA Requests */ |
| /*! @{ */ |
| #define SDMAARM_EVT_MIRROR_EVENTS_MASK (0xFFFFFFFFU) |
| #define SDMAARM_EVT_MIRROR_EVENTS_SHIFT (0U) |
| /*! EVENTS |
| * 0b00000000000000000000000000000000..DMA request event not pending |
| * 0b00000000000000000000000000000001..DMA request event pending |
| */ |
| #define SDMAARM_EVT_MIRROR_EVENTS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR_EVENTS_MASK) |
| /*! @} */ |
| |
| /*! @name EVT_MIRROR2 - DMA Requests 2 */ |
| /*! @{ */ |
| #define SDMAARM_EVT_MIRROR2_EVENTS_MASK (0xFFFFU) |
| #define SDMAARM_EVT_MIRROR2_EVENTS_SHIFT (0U) |
| /*! EVENTS |
| * 0b0000000000000000..- DMA request event not pending |
| */ |
| #define SDMAARM_EVT_MIRROR2_EVENTS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR2_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR2_EVENTS_MASK) |
| /*! @} */ |
| |
| /*! @name XTRIG_CONF1 - Cross-Trigger Events Configuration Register 1 */ |
| /*! @{ */ |
| #define SDMAARM_XTRIG_CONF1_NUM0_MASK (0x3FU) |
| #define SDMAARM_XTRIG_CONF1_NUM0_SHIFT (0U) |
| #define SDMAARM_XTRIG_CONF1_NUM0(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM0_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM0_MASK) |
| #define SDMAARM_XTRIG_CONF1_CNF0_MASK (0x40U) |
| #define SDMAARM_XTRIG_CONF1_CNF0_SHIFT (6U) |
| /*! CNF0 |
| * 0b0..channel |
| * 0b1..DMA request |
| */ |
| #define SDMAARM_XTRIG_CONF1_CNF0(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF0_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF0_MASK) |
| #define SDMAARM_XTRIG_CONF1_NUM1_MASK (0x3F00U) |
| #define SDMAARM_XTRIG_CONF1_NUM1_SHIFT (8U) |
| #define SDMAARM_XTRIG_CONF1_NUM1(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM1_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM1_MASK) |
| #define SDMAARM_XTRIG_CONF1_CNF1_MASK (0x4000U) |
| #define SDMAARM_XTRIG_CONF1_CNF1_SHIFT (14U) |
| /*! CNF1 |
| * 0b0..channel |
| * 0b1..DMA request |
| */ |
| #define SDMAARM_XTRIG_CONF1_CNF1(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF1_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF1_MASK) |
| #define SDMAARM_XTRIG_CONF1_NUM2_MASK (0x3F0000U) |
| #define SDMAARM_XTRIG_CONF1_NUM2_SHIFT (16U) |
| #define SDMAARM_XTRIG_CONF1_NUM2(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM2_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM2_MASK) |
| #define SDMAARM_XTRIG_CONF1_CNF2_MASK (0x400000U) |
| #define SDMAARM_XTRIG_CONF1_CNF2_SHIFT (22U) |
| /*! CNF2 |
| * 0b0..channel |
| * 0b1..DMA request |
| */ |
| #define SDMAARM_XTRIG_CONF1_CNF2(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF2_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF2_MASK) |
| #define SDMAARM_XTRIG_CONF1_NUM3_MASK (0x3F000000U) |
| #define SDMAARM_XTRIG_CONF1_NUM3_SHIFT (24U) |
| #define SDMAARM_XTRIG_CONF1_NUM3(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM3_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM3_MASK) |
| #define SDMAARM_XTRIG_CONF1_CNF3_MASK (0x40000000U) |
| #define SDMAARM_XTRIG_CONF1_CNF3_SHIFT (30U) |
| /*! CNF3 |
| * 0b0..channel |
| * 0b1..DMA request |
| */ |
| #define SDMAARM_XTRIG_CONF1_CNF3(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF3_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF3_MASK) |
| /*! @} */ |
| |
| /*! @name XTRIG_CONF2 - Cross-Trigger Events Configuration Register 2 */ |
| /*! @{ */ |
| #define SDMAARM_XTRIG_CONF2_NUM4_MASK (0x3FU) |
| #define SDMAARM_XTRIG_CONF2_NUM4_SHIFT (0U) |
| #define SDMAARM_XTRIG_CONF2_NUM4(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM4_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM4_MASK) |
| #define SDMAARM_XTRIG_CONF2_CNF4_MASK (0x40U) |
| #define SDMAARM_XTRIG_CONF2_CNF4_SHIFT (6U) |
| /*! CNF4 |
| * 0b0..channel |
| * 0b1..DMA request |
| */ |
| #define SDMAARM_XTRIG_CONF2_CNF4(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF4_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF4_MASK) |
| #define SDMAARM_XTRIG_CONF2_NUM5_MASK (0x3F00U) |
| #define SDMAARM_XTRIG_CONF2_NUM5_SHIFT (8U) |
| #define SDMAARM_XTRIG_CONF2_NUM5(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM5_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM5_MASK) |
| #define SDMAARM_XTRIG_CONF2_CNF5_MASK (0x4000U) |
| #define SDMAARM_XTRIG_CONF2_CNF5_SHIFT (14U) |
| /*! CNF5 |
| * 0b0..channel |
| * 0b1..DMA request |
| */ |
| #define SDMAARM_XTRIG_CONF2_CNF5(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF5_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF5_MASK) |
| #define SDMAARM_XTRIG_CONF2_NUM6_MASK (0x3F0000U) |
| #define SDMAARM_XTRIG_CONF2_NUM6_SHIFT (16U) |
| #define SDMAARM_XTRIG_CONF2_NUM6(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM6_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM6_MASK) |
| #define SDMAARM_XTRIG_CONF2_CNF6_MASK (0x400000U) |
| #define SDMAARM_XTRIG_CONF2_CNF6_SHIFT (22U) |
| /*! CNF6 |
| * 0b0..channel |
| * 0b1..DMA request |
| */ |
| #define SDMAARM_XTRIG_CONF2_CNF6(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF6_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF6_MASK) |
| #define SDMAARM_XTRIG_CONF2_NUM7_MASK (0x3F000000U) |
| #define SDMAARM_XTRIG_CONF2_NUM7_SHIFT (24U) |
| #define SDMAARM_XTRIG_CONF2_NUM7(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM7_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM7_MASK) |
| #define SDMAARM_XTRIG_CONF2_CNF7_MASK (0x40000000U) |
| #define SDMAARM_XTRIG_CONF2_CNF7_SHIFT (30U) |
| /*! CNF7 |
| * 0b0..channel |
| * 0b1..DMA request |
| */ |
| #define SDMAARM_XTRIG_CONF2_CNF7(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF7_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF7_MASK) |
| /*! @} */ |
| |
| /*! @name SDMA_CHNPRI - Channel Priority Registers */ |
| /*! @{ */ |
| #define SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK (0x7U) |
| #define SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT (0U) |
| #define SDMAARM_SDMA_CHNPRI_CHNPRIn(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT)) & SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK) |
| /*! @} */ |
| |
| /* The count of SDMAARM_SDMA_CHNPRI */ |
| #define SDMAARM_SDMA_CHNPRI_COUNT (32U) |
| |
| /*! @name CHNENBL - Channel Enable RAM */ |
| /*! @{ */ |
| #define SDMAARM_CHNENBL_ENBLn_MASK (0xFFFFFFFFU) |
| #define SDMAARM_CHNENBL_ENBLn_SHIFT (0U) |
| #define SDMAARM_CHNENBL_ENBLn(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHNENBL_ENBLn_SHIFT)) & SDMAARM_CHNENBL_ENBLn_MASK) |
| /*! @} */ |
| |
| /* The count of SDMAARM_CHNENBL */ |
| #define SDMAARM_CHNENBL_COUNT (48U) |
| |
| |
| /*! |
| * @} |
| */ /* end of group SDMAARM_Register_Masks */ |
| |
| |
| /* SDMAARM - Peripheral instance base addresses */ |
| /** Peripheral SDMAARM1 base address */ |
| #define SDMAARM1_BASE (0x30BD0000u) |
| /** Peripheral SDMAARM1 base pointer */ |
| #define SDMAARM1 ((SDMAARM_Type *)SDMAARM1_BASE) |
| /** Peripheral SDMAARM2 base address */ |
| #define SDMAARM2_BASE (0x302C0000u) |
| /** Peripheral SDMAARM2 base pointer */ |
| #define SDMAARM2 ((SDMAARM_Type *)SDMAARM2_BASE) |
| /** Array initializer of SDMAARM peripheral base addresses */ |
| #define SDMAARM_BASE_ADDRS { 0u, SDMAARM1_BASE, SDMAARM2_BASE } |
| /** Array initializer of SDMAARM peripheral base pointers */ |
| #define SDMAARM_BASE_PTRS { (SDMAARM_Type *)0u, SDMAARM1, SDMAARM2 } |
| /** Interrupt vectors for the SDMAARM peripheral type */ |
| #define SDMAARM_IRQS { NotAvail_IRQn, SDMA1_IRQn, SDMA2_IRQn } |
| |
| /*! |
| * @} |
| */ /* end of group SDMAARM_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- SEMA4 Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SEMA4_Peripheral_Access_Layer SEMA4 Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** SEMA4 - Register Layout Typedef */ |
| typedef struct { |
| __IO uint8_t Gate00; /**< Semaphores Gate 0 Register, offset: 0x0 */ |
| __IO uint8_t Gate01; /**< Semaphores Gate 1 Register, offset: 0x1 */ |
| __IO uint8_t Gate02; /**< Semaphores Gate 2 Register, offset: 0x2 */ |
| __IO uint8_t Gate03; /**< Semaphores Gate 3 Register, offset: 0x3 */ |
| __IO uint8_t Gate04; /**< Semaphores Gate 4 Register, offset: 0x4 */ |
| __IO uint8_t Gate05; /**< Semaphores Gate 5 Register, offset: 0x5 */ |
| __IO uint8_t Gate06; /**< Semaphores Gate 6 Register, offset: 0x6 */ |
| __IO uint8_t Gate07; /**< Semaphores Gate 7 Register, offset: 0x7 */ |
| __IO uint8_t Gate08; /**< Semaphores Gate 8 Register, offset: 0x8 */ |
| __IO uint8_t Gate09; /**< Semaphores Gate 9 Register, offset: 0x9 */ |
| __IO uint8_t Gate10; /**< Semaphores Gate 10 Register, offset: 0xA */ |
| __IO uint8_t Gate11; /**< Semaphores Gate 11 Register, offset: 0xB */ |
| __IO uint8_t Gate12; /**< Semaphores Gate 12 Register, offset: 0xC */ |
| __IO uint8_t Gate13; /**< Semaphores Gate 13 Register, offset: 0xD */ |
| __IO uint8_t Gate14; /**< Semaphores Gate 14 Register, offset: 0xE */ |
| __IO uint8_t Gate15; /**< Semaphores Gate 15 Register, offset: 0xF */ |
| uint8_t RESERVED_0[48]; |
| struct { /* offset: 0x40, array step: 0x8 */ |
| __IO uint16_t CPINE; /**< Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8 */ |
| uint8_t RESERVED_0[6]; |
| } CPINE[2]; |
| uint8_t RESERVED_1[48]; |
| struct { /* offset: 0x80, array step: 0x8 */ |
| __I uint16_t CPNTF; /**< Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8 */ |
| uint8_t RESERVED_0[6]; |
| } CPNTF[2]; |
| uint8_t RESERVED_2[112]; |
| __IO uint16_t RSTGT; /**< Semaphores (Secure) Reset Gate n, offset: 0x100 */ |
| uint8_t RESERVED_3[2]; |
| __IO uint16_t RSTNTF; /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */ |
| } SEMA4_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- SEMA4 Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SEMA4_Register_Masks SEMA4 Register Masks |
| * @{ |
| */ |
| |
| /*! @name Gate00 - Semaphores Gate 0 Register */ |
| /*! @{ */ |
| #define SEMA4_Gate00_GTFSM_MASK (0x3U) |
| #define SEMA4_Gate00_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b00..The gate is unlocked (free). |
| * 0b01..The gate has been locked by processor 0. |
| * 0b10..The gate has been locked by processor 1. |
| * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. |
| */ |
| #define SEMA4_Gate00_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate00_GTFSM_SHIFT)) & SEMA4_Gate00_GTFSM_MASK) |
| /*! @} */ |
| |
| /*! @name Gate01 - Semaphores Gate 1 Register */ |
| /*! @{ */ |
| #define SEMA4_Gate01_GTFSM_MASK (0x3U) |
| #define SEMA4_Gate01_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b00..The gate is unlocked (free). |
| * 0b01..The gate has been locked by processor 0. |
| * 0b10..The gate has been locked by processor 1. |
| * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. |
| */ |
| #define SEMA4_Gate01_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate01_GTFSM_SHIFT)) & SEMA4_Gate01_GTFSM_MASK) |
| /*! @} */ |
| |
| /*! @name Gate02 - Semaphores Gate 2 Register */ |
| /*! @{ */ |
| #define SEMA4_Gate02_GTFSM_MASK (0x3U) |
| #define SEMA4_Gate02_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b00..The gate is unlocked (free). |
| * 0b01..The gate has been locked by processor 0. |
| * 0b10..The gate has been locked by processor 1. |
| * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. |
| */ |
| #define SEMA4_Gate02_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate02_GTFSM_SHIFT)) & SEMA4_Gate02_GTFSM_MASK) |
| /*! @} */ |
| |
| /*! @name Gate03 - Semaphores Gate 3 Register */ |
| /*! @{ */ |
| #define SEMA4_Gate03_GTFSM_MASK (0x3U) |
| #define SEMA4_Gate03_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b00..The gate is unlocked (free). |
| * 0b01..The gate has been locked by processor 0. |
| * 0b10..The gate has been locked by processor 1. |
| * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. |
| */ |
| #define SEMA4_Gate03_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate03_GTFSM_SHIFT)) & SEMA4_Gate03_GTFSM_MASK) |
| /*! @} */ |
| |
| /*! @name Gate04 - Semaphores Gate 4 Register */ |
| /*! @{ */ |
| #define SEMA4_Gate04_GTFSM_MASK (0x3U) |
| #define SEMA4_Gate04_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b00..The gate is unlocked (free). |
| * 0b01..The gate has been locked by processor 0. |
| * 0b10..The gate has been locked by processor 1. |
| * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. |
| */ |
| #define SEMA4_Gate04_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate04_GTFSM_SHIFT)) & SEMA4_Gate04_GTFSM_MASK) |
| /*! @} */ |
| |
| /*! @name Gate05 - Semaphores Gate 5 Register */ |
| /*! @{ */ |
| #define SEMA4_Gate05_GTFSM_MASK (0x3U) |
| #define SEMA4_Gate05_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b00..The gate is unlocked (free). |
| * 0b01..The gate has been locked by processor 0. |
| * 0b10..The gate has been locked by processor 1. |
| * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. |
| */ |
| #define SEMA4_Gate05_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate05_GTFSM_SHIFT)) & SEMA4_Gate05_GTFSM_MASK) |
| /*! @} */ |
| |
| /*! @name Gate06 - Semaphores Gate 6 Register */ |
| /*! @{ */ |
| #define SEMA4_Gate06_GTFSM_MASK (0x3U) |
| #define SEMA4_Gate06_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b00..The gate is unlocked (free). |
| * 0b01..The gate has been locked by processor 0. |
| * 0b10..The gate has been locked by processor 1. |
| * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. |
| */ |
| #define SEMA4_Gate06_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate06_GTFSM_SHIFT)) & SEMA4_Gate06_GTFSM_MASK) |
| /*! @} */ |
| |
| /*! @name Gate07 - Semaphores Gate 7 Register */ |
| /*! @{ */ |
| #define SEMA4_Gate07_GTFSM_MASK (0x3U) |
| #define SEMA4_Gate07_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b00..The gate is unlocked (free). |
| * 0b01..The gate has been locked by processor 0. |
| * 0b10..The gate has been locked by processor 1. |
| * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. |
| */ |
| #define SEMA4_Gate07_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate07_GTFSM_SHIFT)) & SEMA4_Gate07_GTFSM_MASK) |
| /*! @} */ |
| |
| /*! @name Gate08 - Semaphores Gate 8 Register */ |
| /*! @{ */ |
| #define SEMA4_Gate08_GTFSM_MASK (0x3U) |
| #define SEMA4_Gate08_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b00..The gate is unlocked (free). |
| * 0b01..The gate has been locked by processor 0. |
| * 0b10..The gate has been locked by processor 1. |
| * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. |
| */ |
| #define SEMA4_Gate08_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate08_GTFSM_SHIFT)) & SEMA4_Gate08_GTFSM_MASK) |
| /*! @} */ |
| |
| /*! @name Gate09 - Semaphores Gate 9 Register */ |
| /*! @{ */ |
| #define SEMA4_Gate09_GTFSM_MASK (0x3U) |
| #define SEMA4_Gate09_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b00..The gate is unlocked (free). |
| * 0b01..The gate has been locked by processor 0. |
| * 0b10..The gate has been locked by processor 1. |
| * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. |
| */ |
| #define SEMA4_Gate09_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate09_GTFSM_SHIFT)) & SEMA4_Gate09_GTFSM_MASK) |
| /*! @} */ |
| |
| /*! @name Gate10 - Semaphores Gate 10 Register */ |
| /*! @{ */ |
| #define SEMA4_Gate10_GTFSM_MASK (0x3U) |
| #define SEMA4_Gate10_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b00..The gate is unlocked (free). |
| * 0b01..The gate has been locked by processor 0. |
| * 0b10..The gate has been locked by processor 1. |
| * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. |
| */ |
| #define SEMA4_Gate10_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate10_GTFSM_SHIFT)) & SEMA4_Gate10_GTFSM_MASK) |
| /*! @} */ |
| |
| /*! @name Gate11 - Semaphores Gate 11 Register */ |
| /*! @{ */ |
| #define SEMA4_Gate11_GTFSM_MASK (0x3U) |
| #define SEMA4_Gate11_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b00..The gate is unlocked (free). |
| * 0b01..The gate has been locked by processor 0. |
| * 0b10..The gate has been locked by processor 1. |
| * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. |
| */ |
| #define SEMA4_Gate11_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate11_GTFSM_SHIFT)) & SEMA4_Gate11_GTFSM_MASK) |
| /*! @} */ |
| |
| /*! @name Gate12 - Semaphores Gate 12 Register */ |
| /*! @{ */ |
| #define SEMA4_Gate12_GTFSM_MASK (0x3U) |
| #define SEMA4_Gate12_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b00..The gate is unlocked (free). |
| * 0b01..The gate has been locked by processor 0. |
| * 0b10..The gate has been locked by processor 1. |
| * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. |
| */ |
| #define SEMA4_Gate12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate12_GTFSM_SHIFT)) & SEMA4_Gate12_GTFSM_MASK) |
| /*! @} */ |
| |
| /*! @name Gate13 - Semaphores Gate 13 Register */ |
| /*! @{ */ |
| #define SEMA4_Gate13_GTFSM_MASK (0x3U) |
| #define SEMA4_Gate13_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b00..The gate is unlocked (free). |
| * 0b01..The gate has been locked by processor 0. |
| * 0b10..The gate has been locked by processor 1. |
| * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. |
| */ |
| #define SEMA4_Gate13_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate13_GTFSM_SHIFT)) & SEMA4_Gate13_GTFSM_MASK) |
| /*! @} */ |
| |
| /*! @name Gate14 - Semaphores Gate 14 Register */ |
| /*! @{ */ |
| #define SEMA4_Gate14_GTFSM_MASK (0x3U) |
| #define SEMA4_Gate14_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b00..The gate is unlocked (free). |
| * 0b01..The gate has been locked by processor 0. |
| * 0b10..The gate has been locked by processor 1. |
| * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. |
| */ |
| #define SEMA4_Gate14_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate14_GTFSM_SHIFT)) & SEMA4_Gate14_GTFSM_MASK) |
| /*! @} */ |
| |
| /*! @name Gate15 - Semaphores Gate 15 Register */ |
| /*! @{ */ |
| #define SEMA4_Gate15_GTFSM_MASK (0x3U) |
| #define SEMA4_Gate15_GTFSM_SHIFT (0U) |
| /*! GTFSM - Gate Finite State Machine. |
| * 0b00..The gate is unlocked (free). |
| * 0b01..The gate has been locked by processor 0. |
| * 0b10..The gate has been locked by processor 1. |
| * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine. |
| */ |
| #define SEMA4_Gate15_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate15_GTFSM_SHIFT)) & SEMA4_Gate15_GTFSM_MASK) |
| /*! @} */ |
| |
| /*! @name CPINE - Semaphores Processor n IRQ Notification Enable */ |
| /*! @{ */ |
| #define SEMA4_CPINE_INE7_MASK (0x1U) |
| #define SEMA4_CPINE_INE7_SHIFT (0U) |
| /*! INE7 - Interrupt Request Notification Enable 7. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 7. |
| * 0b0..The generation of the notification interrupt is disabled. |
| * 0b1..The generation of the notification interrupt is enabled. |
| */ |
| #define SEMA4_CPINE_INE7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE7_SHIFT)) & SEMA4_CPINE_INE7_MASK) |
| #define SEMA4_CPINE_INE6_MASK (0x2U) |
| #define SEMA4_CPINE_INE6_SHIFT (1U) |
| /*! INE6 - Interrupt Request Notification Enable 6. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 6. |
| * 0b0..The generation of the notification interrupt is disabled. |
| * 0b1..The generation of the notification interrupt is enabled. |
| */ |
| #define SEMA4_CPINE_INE6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE6_SHIFT)) & SEMA4_CPINE_INE6_MASK) |
| #define SEMA4_CPINE_INE5_MASK (0x4U) |
| #define SEMA4_CPINE_INE5_SHIFT (2U) |
| /*! INE5 - Interrupt Request Notification Enable 5. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 5. |
| * 0b0..The generation of the notification interrupt is disabled. |
| * 0b1..The generation of the notification interrupt is enabled. |
| */ |
| #define SEMA4_CPINE_INE5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE5_SHIFT)) & SEMA4_CPINE_INE5_MASK) |
| #define SEMA4_CPINE_INE4_MASK (0x8U) |
| #define SEMA4_CPINE_INE4_SHIFT (3U) |
| /*! INE4 - Interrupt Request Notification Enable 4. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 4. |
| * 0b0..The generation of the notification interrupt is disabled. |
| * 0b1..The generation of the notification interrupt is enabled. |
| */ |
| #define SEMA4_CPINE_INE4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE4_SHIFT)) & SEMA4_CPINE_INE4_MASK) |
| #define SEMA4_CPINE_INE3_MASK (0x10U) |
| #define SEMA4_CPINE_INE3_SHIFT (4U) |
| /*! INE3 |
| * 0b0..The generation of the notification interrupt is disabled. |
| * 0b1..The generation of the notification interrupt is enabled. |
| */ |
| #define SEMA4_CPINE_INE3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE3_SHIFT)) & SEMA4_CPINE_INE3_MASK) |
| #define SEMA4_CPINE_INE2_MASK (0x20U) |
| #define SEMA4_CPINE_INE2_SHIFT (5U) |
| /*! INE2 |
| * 0b0..The generation of the notification interrupt is disabled. |
| * 0b1..The generation of the notification interrupt is enabled. |
| */ |
| #define SEMA4_CPINE_INE2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE2_SHIFT)) & SEMA4_CPINE_INE2_MASK) |
| #define SEMA4_CPINE_INE1_MASK (0x40U) |
| #define SEMA4_CPINE_INE1_SHIFT (6U) |
| /*! INE1 |
| * 0b0..The generation of the notification interrupt is disabled. |
| * 0b1..The generation of the notification interrupt is enabled. |
| */ |
| #define SEMA4_CPINE_INE1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE1_SHIFT)) & SEMA4_CPINE_INE1_MASK) |
| #define SEMA4_CPINE_INE0_MASK (0x80U) |
| #define SEMA4_CPINE_INE0_SHIFT (7U) |
| /*! INE0 |
| * 0b0..The generation of the notification interrupt is disabled. |
| * 0b1..The generation of the notification interrupt is enabled. |
| */ |
| #define SEMA4_CPINE_INE0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE0_SHIFT)) & SEMA4_CPINE_INE0_MASK) |
| #define SEMA4_CPINE_INE15_MASK (0x100U) |
| #define SEMA4_CPINE_INE15_SHIFT (8U) |
| /*! INE15 - Interrupt Request Notification Enable 15. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 15. |
| * 0b0..The generation of the notification interrupt is disabled. |
| * 0b1..The generation of the notification interrupt is enabled. |
| */ |
| #define SEMA4_CPINE_INE15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE15_SHIFT)) & SEMA4_CPINE_INE15_MASK) |
| #define SEMA4_CPINE_INE14_MASK (0x200U) |
| #define SEMA4_CPINE_INE14_SHIFT (9U) |
| /*! INE14 - Interrupt Request Notification Enable 14. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 14. |
| * 0b0..The generation of the notification interrupt is disabled. |
| * 0b1..The generation of the notification interrupt is enabled. |
| */ |
| #define SEMA4_CPINE_INE14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE14_SHIFT)) & SEMA4_CPINE_INE14_MASK) |
| #define SEMA4_CPINE_INE13_MASK (0x400U) |
| #define SEMA4_CPINE_INE13_SHIFT (10U) |
| /*! INE13 - Interrupt Request Notification Enable 13. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 13. |
| * 0b0..The generation of the notification interrupt is disabled. |
| * 0b1..The generation of the notification interrupt is enabled. |
| */ |
| #define SEMA4_CPINE_INE13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE13_SHIFT)) & SEMA4_CPINE_INE13_MASK) |
| #define SEMA4_CPINE_INE12_MASK (0x800U) |
| #define SEMA4_CPINE_INE12_SHIFT (11U) |
| /*! INE12 - Interrupt Request Notification Enable 12. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 12. |
| * 0b0..The generation of the notification interrupt is disabled. |
| * 0b1..The generation of the notification interrupt is enabled. |
| */ |
| #define SEMA4_CPINE_INE12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE12_SHIFT)) & SEMA4_CPINE_INE12_MASK) |
| #define SEMA4_CPINE_INE11_MASK (0x1000U) |
| #define SEMA4_CPINE_INE11_SHIFT (12U) |
| /*! INE11 - Interrupt Request Notification Enable 11. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 11. |
| * 0b0..The generation of the notification interrupt is disabled. |
| * 0b1..The generation of the notification interrupt is enabled. |
| */ |
| #define SEMA4_CPINE_INE11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE11_SHIFT)) & SEMA4_CPINE_INE11_MASK) |
| #define SEMA4_CPINE_INE10_MASK (0x2000U) |
| #define SEMA4_CPINE_INE10_SHIFT (13U) |
| /*! INE10 - Interrupt Request Notification Enable 10. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 10. |
| * 0b0..The generation of the notification interrupt is disabled. |
| * 0b1..The generation of the notification interrupt is enabled. |
| */ |
| #define SEMA4_CPINE_INE10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE10_SHIFT)) & SEMA4_CPINE_INE10_MASK) |
| #define SEMA4_CPINE_INE9_MASK (0x4000U) |
| #define SEMA4_CPINE_INE9_SHIFT (14U) |
| /*! INE9 - Interrupt Request Notification Enable 9. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 9. |
| * 0b0..The generation of the notification interrupt is disabled. |
| * 0b1..The generation of the notification interrupt is enabled. |
| */ |
| #define SEMA4_CPINE_INE9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE9_SHIFT)) & SEMA4_CPINE_INE9_MASK) |
| #define SEMA4_CPINE_INE8_MASK (0x8000U) |
| #define SEMA4_CPINE_INE8_SHIFT (15U) |
| /*! INE8 - Interrupt Request Notification Enable 8. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 8. |
| * 0b0..The generation of the notification interrupt is disabled. |
| * 0b1..The generation of the notification interrupt is enabled. |
| */ |
| #define SEMA4_CPINE_INE8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE8_SHIFT)) & SEMA4_CPINE_INE8_MASK) |
| /*! @} */ |
| |
| /* The count of SEMA4_CPINE */ |
| #define SEMA4_CPINE_COUNT (2U) |
| |
| /*! @name CPNTF - Semaphores Processor n IRQ Notification */ |
| /*! @{ */ |
| #define SEMA4_CPNTF_GN7_MASK (0x1U) |
| #define SEMA4_CPNTF_GN7_SHIFT (0U) |
| #define SEMA4_CPNTF_GN7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN7_SHIFT)) & SEMA4_CPNTF_GN7_MASK) |
| #define SEMA4_CPNTF_GN6_MASK (0x2U) |
| #define SEMA4_CPNTF_GN6_SHIFT (1U) |
| #define SEMA4_CPNTF_GN6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN6_SHIFT)) & SEMA4_CPNTF_GN6_MASK) |
| #define SEMA4_CPNTF_GN5_MASK (0x4U) |
| #define SEMA4_CPNTF_GN5_SHIFT (2U) |
| #define SEMA4_CPNTF_GN5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN5_SHIFT)) & SEMA4_CPNTF_GN5_MASK) |
| #define SEMA4_CPNTF_GN4_MASK (0x8U) |
| #define SEMA4_CPNTF_GN4_SHIFT (3U) |
| #define SEMA4_CPNTF_GN4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN4_SHIFT)) & SEMA4_CPNTF_GN4_MASK) |
| #define SEMA4_CPNTF_GN3_MASK (0x10U) |
| #define SEMA4_CPNTF_GN3_SHIFT (4U) |
| #define SEMA4_CPNTF_GN3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN3_SHIFT)) & SEMA4_CPNTF_GN3_MASK) |
| #define SEMA4_CPNTF_GN2_MASK (0x20U) |
| #define SEMA4_CPNTF_GN2_SHIFT (5U) |
| #define SEMA4_CPNTF_GN2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN2_SHIFT)) & SEMA4_CPNTF_GN2_MASK) |
| #define SEMA4_CPNTF_GN1_MASK (0x40U) |
| #define SEMA4_CPNTF_GN1_SHIFT (6U) |
| #define SEMA4_CPNTF_GN1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN1_SHIFT)) & SEMA4_CPNTF_GN1_MASK) |
| #define SEMA4_CPNTF_GN0_MASK (0x80U) |
| #define SEMA4_CPNTF_GN0_SHIFT (7U) |
| #define SEMA4_CPNTF_GN0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN0_SHIFT)) & SEMA4_CPNTF_GN0_MASK) |
| #define SEMA4_CPNTF_GN15_MASK (0x100U) |
| #define SEMA4_CPNTF_GN15_SHIFT (8U) |
| #define SEMA4_CPNTF_GN15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN15_SHIFT)) & SEMA4_CPNTF_GN15_MASK) |
| #define SEMA4_CPNTF_GN14_MASK (0x200U) |
| #define SEMA4_CPNTF_GN14_SHIFT (9U) |
| #define SEMA4_CPNTF_GN14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN14_SHIFT)) & SEMA4_CPNTF_GN14_MASK) |
| #define SEMA4_CPNTF_GN13_MASK (0x400U) |
| #define SEMA4_CPNTF_GN13_SHIFT (10U) |
| #define SEMA4_CPNTF_GN13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN13_SHIFT)) & SEMA4_CPNTF_GN13_MASK) |
| #define SEMA4_CPNTF_GN12_MASK (0x800U) |
| #define SEMA4_CPNTF_GN12_SHIFT (11U) |
| #define SEMA4_CPNTF_GN12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN12_SHIFT)) & SEMA4_CPNTF_GN12_MASK) |
| #define SEMA4_CPNTF_GN11_MASK (0x1000U) |
| #define SEMA4_CPNTF_GN11_SHIFT (12U) |
| #define SEMA4_CPNTF_GN11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN11_SHIFT)) & SEMA4_CPNTF_GN11_MASK) |
| #define SEMA4_CPNTF_GN10_MASK (0x2000U) |
| #define SEMA4_CPNTF_GN10_SHIFT (13U) |
| #define SEMA4_CPNTF_GN10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN10_SHIFT)) & SEMA4_CPNTF_GN10_MASK) |
| #define SEMA4_CPNTF_GN9_MASK (0x4000U) |
| #define SEMA4_CPNTF_GN9_SHIFT (14U) |
| #define SEMA4_CPNTF_GN9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN9_SHIFT)) & SEMA4_CPNTF_GN9_MASK) |
| #define SEMA4_CPNTF_GN8_MASK (0x8000U) |
| #define SEMA4_CPNTF_GN8_SHIFT (15U) |
| #define SEMA4_CPNTF_GN8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN8_SHIFT)) & SEMA4_CPNTF_GN8_MASK) |
| /*! @} */ |
| |
| /* The count of SEMA4_CPNTF */ |
| #define SEMA4_CPNTF_COUNT (2U) |
| |
| /*! @name RSTGT - Semaphores (Secure) Reset Gate n */ |
| /*! @{ */ |
| #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK (0xFFU) |
| #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT (0U) |
| #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT)) & SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK) |
| #define SEMA4_RSTGT_RSTGTN_MASK (0xFF00U) |
| #define SEMA4_RSTGT_RSTGTN_SHIFT (8U) |
| #define SEMA4_RSTGT_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGTN_SHIFT)) & SEMA4_RSTGT_RSTGTN_MASK) |
| /*! @} */ |
| |
| /*! @name RSTNTF - Semaphores (Secure) Reset IRQ Notification */ |
| /*! @{ */ |
| #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK (0xFFU) |
| #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT (0U) |
| #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT)) & SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK) |
| #define SEMA4_RSTNTF_RSTNTN_MASK (0xFF00U) |
| #define SEMA4_RSTNTF_RSTNTN_SHIFT (8U) |
| #define SEMA4_RSTNTF_RSTNTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNTN_SHIFT)) & SEMA4_RSTNTF_RSTNTN_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group SEMA4_Register_Masks */ |
| |
| |
| /* SEMA4 - Peripheral instance base addresses */ |
| /** Peripheral SEMA4 base address */ |
| #define SEMA4_BASE (0x30AC0000u) |
| /** Peripheral SEMA4 base pointer */ |
| #define SEMA4 ((SEMA4_Type *)SEMA4_BASE) |
| /** Array initializer of SEMA4 peripheral base addresses */ |
| #define SEMA4_BASE_ADDRS { SEMA4_BASE } |
| /** Array initializer of SEMA4 peripheral base pointers */ |
| #define SEMA4_BASE_PTRS { SEMA4 } |
| |
| /*! |
| * @} |
| */ /* end of group SEMA4_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- SNVS Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** SNVS - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ |
| __IO uint32_t HPCOMR; /**< SNVS_HP Command Register, offset: 0x4 */ |
| __IO uint32_t HPCR; /**< SNVS_HP Control Register, offset: 0x8 */ |
| __IO uint32_t HPSICR; /**< SNVS_HP Security Interrupt Control Register, offset: 0xC */ |
| __IO uint32_t HPSVCR; /**< SNVS_HP Security Violation Control Register, offset: 0x10 */ |
| __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ |
| __IO uint32_t HPSVSR; /**< SNVS_HP Security Violation Status Register, offset: 0x18 */ |
| __IO uint32_t HPHACIVR; /**< SNVS_HP High Assurance Counter IV Register, offset: 0x1C */ |
| __I uint32_t HPHACR; /**< SNVS_HP High Assurance Counter Register, offset: 0x20 */ |
| __IO uint32_t HPRTCMR; /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */ |
| __IO uint32_t HPRTCLR; /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */ |
| __IO uint32_t HPTAMR; /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */ |
| __IO uint32_t HPTALR; /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */ |
| __IO uint32_t LPLR; /**< SNVS_LP Lock Register, offset: 0x34 */ |
| __IO uint32_t LPCR; /**< SNVS_LP Control Register, offset: 0x38 */ |
| __IO uint32_t LPMKCR; /**< SNVS_LP Master Key Control Register, offset: 0x3C */ |
| __IO uint32_t LPSVCR; /**< SNVS_LP Security Violation Control Register, offset: 0x40 */ |
| uint8_t RESERVED_0[4]; |
| __IO uint32_t LPSECR; /**< SNVS_LP Security Events Configuration Register, offset: 0x48 */ |
| __IO uint32_t LPSR; /**< SNVS_LP Status Register, offset: 0x4C */ |
| __IO uint32_t LPSRTCMR; /**< SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50 */ |
| __IO uint32_t LPSRTCLR; /**< SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54 */ |
| __IO uint32_t LPTAR; /**< SNVS_LP Time Alarm Register, offset: 0x58 */ |
| __I uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */ |
| __I uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */ |
| __IO uint32_t LPPGDR; /**< SNVS_LP Power Glitch Detector Register, offset: 0x64 */ |
| __IO uint32_t LPGPR0_LEGACY_ALIAS; /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */ |
| __IO uint32_t LPZMKR[8]; /**< SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4 */ |
| uint8_t RESERVED_1[4]; |
| __IO uint32_t LPGPR_ALIAS[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */ |
| uint8_t RESERVED_2[96]; |
| __IO uint32_t LPGPR[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x100, array step: 0x4 */ |
| uint8_t RESERVED_3[2792]; |
| __I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */ |
| __I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */ |
| } SNVS_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- SNVS Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SNVS_Register_Masks SNVS Register Masks |
| * @{ |
| */ |
| |
| /*! @name HPLR - SNVS_HP Lock Register */ |
| /*! @{ */ |
| #define SNVS_HPLR_ZMK_WSL_MASK (0x1U) |
| #define SNVS_HPLR_ZMK_WSL_SHIFT (0U) |
| /*! ZMK_WSL |
| * 0b0..Write access is allowed |
| * 0b1..Write access is not allowed |
| */ |
| #define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK) |
| #define SNVS_HPLR_ZMK_RSL_MASK (0x2U) |
| #define SNVS_HPLR_ZMK_RSL_SHIFT (1U) |
| /*! ZMK_RSL |
| * 0b0..Read access is allowed (only in software Programming mode) |
| * 0b1..Read access is not allowed |
| */ |
| #define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK) |
| #define SNVS_HPLR_SRTC_SL_MASK (0x4U) |
| #define SNVS_HPLR_SRTC_SL_SHIFT (2U) |
| /*! SRTC_SL |
| * 0b0..Write access is allowed |
| * 0b1..Write access is not allowed |
| */ |
| #define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK) |
| #define SNVS_HPLR_LPCALB_SL_MASK (0x8U) |
| #define SNVS_HPLR_LPCALB_SL_SHIFT (3U) |
| /*! LPCALB_SL |
| * 0b0..Write access is allowed |
| * 0b1..Write access is not allowed |
| */ |
| #define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK) |
| #define SNVS_HPLR_MC_SL_MASK (0x10U) |
| #define SNVS_HPLR_MC_SL_SHIFT (4U) |
| /*! MC_SL |
| * 0b0..Write access (increment) is allowed |
| * 0b1..Write access (increment) is not allowed |
| */ |
| #define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK) |
| #define SNVS_HPLR_GPR_SL_MASK (0x20U) |
| #define SNVS_HPLR_GPR_SL_SHIFT (5U) |
| /*! GPR_SL |
| * 0b0..Write access is allowed |
| * 0b1..Write access is not allowed |
| */ |
| #define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK) |
| #define SNVS_HPLR_LPSVCR_SL_MASK (0x40U) |
| #define SNVS_HPLR_LPSVCR_SL_SHIFT (6U) |
| /*! LPSVCR_SL |
| * 0b0..Write access is allowed |
| * 0b1..Write access is not allowed |
| */ |
| #define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK) |
| #define SNVS_HPLR_LPSECR_SL_MASK (0x100U) |
| #define SNVS_HPLR_LPSECR_SL_SHIFT (8U) |
| /*! LPSECR_SL |
| * 0b0..Write access is allowed |
| * 0b1..Write access is not allowed |
| */ |
| #define SNVS_HPLR_LPSECR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSECR_SL_SHIFT)) & SNVS_HPLR_LPSECR_SL_MASK) |
| #define SNVS_HPLR_MKS_SL_MASK (0x200U) |
| #define SNVS_HPLR_MKS_SL_SHIFT (9U) |
| /*! MKS_SL |
| * 0b0..Write access is allowed |
| * 0b1..Write access is not allowed |
| */ |
| #define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK) |
| #define SNVS_HPLR_HPSVCR_L_MASK (0x10000U) |
| #define SNVS_HPLR_HPSVCR_L_SHIFT (16U) |
| /*! HPSVCR_L |
| * 0b0..Write access is allowed |
| * 0b1..Write access is not allowed |
| */ |
| #define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK) |
| #define SNVS_HPLR_HPSICR_L_MASK (0x20000U) |
| #define SNVS_HPLR_HPSICR_L_SHIFT (17U) |
| /*! HPSICR_L |
| * 0b0..Write access is allowed |
| * 0b1..Write access is not allowed |
| */ |
| #define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK) |
| #define SNVS_HPLR_HAC_L_MASK (0x40000U) |
| #define SNVS_HPLR_HAC_L_SHIFT (18U) |
| /*! HAC_L |
| * 0b0..Write access is allowed |
| * 0b1..Write access is not allowed |
| */ |
| #define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK) |
| /*! @} */ |
| |
| /*! @name HPCOMR - SNVS_HP Command Register */ |
| /*! @{ */ |
| #define SNVS_HPCOMR_SSM_ST_MASK (0x1U) |
| #define SNVS_HPCOMR_SSM_ST_SHIFT (0U) |
| #define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK) |
| #define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U) |
| #define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U) |
| /*! SSM_ST_DIS |
| * 0b0..Secure to Trusted State transition is enabled |
| * 0b1..Secure to Trusted State transition is disabled |
| */ |
| #define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK) |
| #define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U) |
| #define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U) |
| /*! SSM_SFNS_DIS |
| * 0b0..Soft Fail to Non-Secure State transition is enabled |
| * 0b1..Soft Fail to Non-Secure State transition is disabled |
| */ |
| #define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK) |
| #define SNVS_HPCOMR_LP_SWR_MASK (0x10U) |
| #define SNVS_HPCOMR_LP_SWR_SHIFT (4U) |
| /*! LP_SWR |
| * 0b0..No Action |
| * 0b1..Reset LP section |
| */ |
| #define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK) |
| #define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U) |
| #define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U) |
| /*! LP_SWR_DIS |
| * 0b0..LP software reset is enabled |
| * 0b1..LP software reset is disabled |
| */ |
| #define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK) |
| #define SNVS_HPCOMR_SW_SV_MASK (0x100U) |
| #define SNVS_HPCOMR_SW_SV_SHIFT (8U) |
| #define SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK) |
| #define SNVS_HPCOMR_SW_FSV_MASK (0x200U) |
| #define SNVS_HPCOMR_SW_FSV_SHIFT (9U) |
| #define SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK) |
| #define SNVS_HPCOMR_SW_LPSV_MASK (0x400U) |
| #define SNVS_HPCOMR_SW_LPSV_SHIFT (10U) |
| #define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK) |
| #define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U) |
| #define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U) |
| /*! PROG_ZMK |
| * 0b0..No Action |
| * 0b1..Activate hardware key programming mechanism |
| */ |
| #define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK) |
| #define SNVS_HPCOMR_MKS_EN_MASK (0x2000U) |
| #define SNVS_HPCOMR_MKS_EN_SHIFT (13U) |
| #define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK) |
| #define SNVS_HPCOMR_HAC_EN_MASK (0x10000U) |
| #define SNVS_HPCOMR_HAC_EN_SHIFT (16U) |
| /*! HAC_EN |
| * 0b0..High Assurance Counter is disabled |
| * 0b1..High Assurance Counter is enabled |
| */ |
| #define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK) |
| #define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U) |
| #define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U) |
| /*! HAC_LOAD |
| * 0b0..No Action |
| * 0b1..Load the HAC |
| */ |
| #define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK) |
| #define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U) |
| #define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U) |
| /*! HAC_CLEAR |
| * 0b0..No Action |
| * 0b1..Clear the HAC |
| */ |
| #define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK) |
| #define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U) |
| #define SNVS_HPCOMR_HAC_STOP_SHIFT (19U) |
| #define SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK) |
| #define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U) |
| #define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U) |
| #define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK) |
| /*! @} */ |
| |
| /*! @name HPCR - SNVS_HP Control Register */ |
| /*! @{ */ |
| #define SNVS_HPCR_RTC_EN_MASK (0x1U) |
| #define SNVS_HPCR_RTC_EN_SHIFT (0U) |
| /*! RTC_EN |
| * 0b0..RTC is disabled |
| * 0b1..RTC is enabled |
| */ |
| #define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK) |
| #define SNVS_HPCR_HPTA_EN_MASK (0x2U) |
| #define SNVS_HPCR_HPTA_EN_SHIFT (1U) |
| /*! HPTA_EN |
| * 0b0..HP Time Alarm Interrupt is disabled |
| * 0b1..HP Time Alarm Interrupt is enabled |
| */ |
| #define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK) |
| #define SNVS_HPCR_DIS_PI_MASK (0x4U) |
| #define SNVS_HPCR_DIS_PI_SHIFT (2U) |
| /*! DIS_PI |
| * 0b0..Periodic interrupt will trigger a functional interrupt |
| * 0b1..Disable periodic interrupt in the function interrupt |
| */ |
| #define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK) |
| #define SNVS_HPCR_PI_EN_MASK (0x8U) |
| #define SNVS_HPCR_PI_EN_SHIFT (3U) |
| /*! PI_EN |
| * 0b0..HP Periodic Interrupt is disabled |
| * 0b1..HP Periodic Interrupt is enabled |
| */ |
| #define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK) |
| #define SNVS_HPCR_PI_FREQ_MASK (0xF0U) |
| #define SNVS_HPCR_PI_FREQ_SHIFT (4U) |
| /*! PI_FREQ |
| * 0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt |
| * 0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt |
| * 0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt |
| * 0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt |
| * 0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt |
| * 0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt |
| * 0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt |
| * 0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt |
| * 0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt |
| * 0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt |
| * 0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt |
| * 0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt |
| * 0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt |
| * 0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt |
| * 0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt |
| * 0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt |
| */ |
| #define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK) |
| #define SNVS_HPCR_HPCALB_EN_MASK (0x100U) |
| #define SNVS_HPCR_HPCALB_EN_SHIFT (8U) |
| /*! HPCALB_EN |
| * 0b0..HP Timer calibration disabled |
| * 0b1..HP Timer calibration enabled |
| */ |
| #define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK) |
| #define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U) |
| #define SNVS_HPCR_HPCALB_VAL_SHIFT (10U) |
| /*! HPCALB_VAL |
| * 0b00000..+0 counts per each 32768 ticks of the counter |
| * 0b00001..+1 counts per each 32768 ticks of the counter |
| * 0b00010..+2 counts per each 32768 ticks of the counter |
| * 0b01111..+15 counts per each 32768 ticks of the counter |
| * 0b10000..-16 counts per each 32768 ticks of the counter |
| * 0b10001..-15 counts per each 32768 ticks of the counter |
| * 0b11110..-2 counts per each 32768 ticks of the counter |
| * 0b11111..-1 counts per each 32768 ticks of the counter |
| */ |
| #define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK) |
| #define SNVS_HPCR_HP_TS_MASK (0x10000U) |
| #define SNVS_HPCR_HP_TS_SHIFT (16U) |
| /*! HP_TS |
| * 0b0..No Action |
| * 0b1..Synchronize the HP Time Counter to the LP Time Counter |
| */ |
| #define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK) |
| #define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U) |
| #define SNVS_HPCR_BTN_CONFIG_SHIFT (24U) |
| #define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK) |
| #define SNVS_HPCR_BTN_MASK_MASK (0x8000000U) |
| #define SNVS_HPCR_BTN_MASK_SHIFT (27U) |
| #define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK) |
| /*! @} */ |
| |
| /*! @name HPSICR - SNVS_HP Security Interrupt Control Register */ |
| /*! @{ */ |
| #define SNVS_HPSICR_SV0_EN_MASK (0x1U) |
| #define SNVS_HPSICR_SV0_EN_SHIFT (0U) |
| /*! SV0_EN |
| * 0b0..Security Violation 0 Interrupt is Disabled |
| * 0b1..Security Violation 0 Interrupt is Enabled |
| */ |
| #define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK) |
| #define SNVS_HPSICR_SV1_EN_MASK (0x2U) |
| #define SNVS_HPSICR_SV1_EN_SHIFT (1U) |
| /*! SV1_EN |
| * 0b0..Security Violation 1 Interrupt is Disabled |
| * 0b1..Security Violation 1 Interrupt is Enabled |
| */ |
| #define SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK) |
| #define SNVS_HPSICR_SV2_EN_MASK (0x4U) |
| #define SNVS_HPSICR_SV2_EN_SHIFT (2U) |
| /*! SV2_EN |
| * 0b0..Security Violation 2 Interrupt is Disabled |
| * 0b1..Security Violation 2 Interrupt is Enabled |
| */ |
| #define SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK) |
| #define SNVS_HPSICR_SV3_EN_MASK (0x8U) |
| #define SNVS_HPSICR_SV3_EN_SHIFT (3U) |
| /*! SV3_EN |
| * 0b0..Security Violation 3 Interrupt is Disabled |
| * 0b1..Security Violation 3 Interrupt is Enabled |
| */ |
| #define SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK) |
| #define SNVS_HPSICR_SV4_EN_MASK (0x10U) |
| #define SNVS_HPSICR_SV4_EN_SHIFT (4U) |
| /*! SV4_EN |
| * 0b0..Security Violation 4 Interrupt is Disabled |
| * 0b1..Security Violation 4 Interrupt is Enabled |
| */ |
| #define SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK) |
| #define SNVS_HPSICR_SV5_EN_MASK (0x20U) |
| #define SNVS_HPSICR_SV5_EN_SHIFT (5U) |
| /*! SV5_EN |
| * 0b0..Security Violation 5 Interrupt is Disabled |
| * 0b1..Security Violation 5 Interrupt is Enabled |
| */ |
| #define SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK) |
| #define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U) |
| #define SNVS_HPSICR_LPSVI_EN_SHIFT (31U) |
| /*! LPSVI_EN |
| * 0b0..LP Security Violation Interrupt is Disabled |
| * 0b1..LP Security Violation Interrupt is Enabled |
| */ |
| #define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK) |
| /*! @} */ |
| |
| /*! @name HPSVCR - SNVS_HP Security Violation Control Register */ |
| /*! @{ */ |
| #define SNVS_HPSVCR_SV0_CFG_MASK (0x1U) |
| #define SNVS_HPSVCR_SV0_CFG_SHIFT (0U) |
| /*! SV0_CFG |
| * 0b0..Security Violation 0 is a non-fatal violation |
| * 0b1..Security Violation 0 is a fatal violation |
| */ |
| #define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK) |
| #define SNVS_HPSVCR_SV1_CFG_MASK (0x2U) |
| #define SNVS_HPSVCR_SV1_CFG_SHIFT (1U) |
| /*! SV1_CFG |
| * 0b0..Security Violation 1 is a non-fatal violation |
| * 0b1..Security Violation 1 is a fatal violation |
| */ |
| #define SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK) |
| #define SNVS_HPSVCR_SV2_CFG_MASK (0x4U) |
| #define SNVS_HPSVCR_SV2_CFG_SHIFT (2U) |
| /*! SV2_CFG |
| * 0b0..Security Violation 2 is a non-fatal violation |
| * 0b1..Security Violation 2 is a fatal violation |
| */ |
| #define SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK) |
| #define SNVS_HPSVCR_SV3_CFG_MASK (0x8U) |
| #define SNVS_HPSVCR_SV3_CFG_SHIFT (3U) |
| /*! SV3_CFG |
| * 0b0..Security Violation 3 is a non-fatal violation |
| * 0b1..Security Violation 3 is a fatal violation |
| */ |
| #define SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK) |
| #define SNVS_HPSVCR_SV4_CFG_MASK (0x10U) |
| #define SNVS_HPSVCR_SV4_CFG_SHIFT (4U) |
| /*! SV4_CFG |
| * 0b0..Security Violation 4 is a non-fatal violation |
| * 0b1..Security Violation 4 is a fatal violation |
| */ |
| #define SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK) |
| #define SNVS_HPSVCR_SV5_CFG_MASK (0x60U) |
| #define SNVS_HPSVCR_SV5_CFG_SHIFT (5U) |
| /*! SV5_CFG |
| * 0b00..Security Violation 5 is disabled |
| * 0b01..Security Violation 5 is a non-fatal violation |
| * 0b1x..Security Violation 5 is a fatal violation |
| */ |
| #define SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK) |
| #define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U) |
| #define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U) |
| /*! LPSV_CFG |
| * 0b00..LP security violation is disabled |
| * 0b01..LP security violation is a non-fatal violation |
| * 0b1x..LP security violation is a fatal violation |
| */ |
| #define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK) |
| /*! @} */ |
| |
| /*! @name HPSR - SNVS_HP Status Register */ |
| /*! @{ */ |
| #define SNVS_HPSR_HPTA_MASK (0x1U) |
| #define SNVS_HPSR_HPTA_SHIFT (0U) |
| /*! HPTA |
| * 0b0..No time alarm interrupt occurred. |
| * 0b1..A time alarm interrupt occurred. |
| */ |
| #define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK) |
| #define SNVS_HPSR_PI_MASK (0x2U) |
| #define SNVS_HPSR_PI_SHIFT (1U) |
| /*! PI |
| * 0b0..No periodic interrupt occurred. |
| * 0b1..A periodic interrupt occurred. |
| */ |
| #define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK) |
| #define SNVS_HPSR_LPDIS_MASK (0x10U) |
| #define SNVS_HPSR_LPDIS_SHIFT (4U) |
| #define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK) |
| #define SNVS_HPSR_BTN_MASK (0x40U) |
| #define SNVS_HPSR_BTN_SHIFT (6U) |
| #define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK) |
| #define SNVS_HPSR_BI_MASK (0x80U) |
| #define SNVS_HPSR_BI_SHIFT (7U) |
| #define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK) |
| #define SNVS_HPSR_SSM_STATE_MASK (0xF00U) |
| #define SNVS_HPSR_SSM_STATE_SHIFT (8U) |
| /*! SSM_STATE |
| * 0b0000..Init |
| * 0b0001..Hard Fail |
| * 0b0011..Soft Fail |
| * 0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle) |
| * 0b1001..Check |
| * 0b1011..Non-Secure |
| * 0b1101..Trusted |
| * 0b1111..Secure |
| */ |
| #define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK) |
| #define SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U) |
| #define SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U) |
| /*! SECURITY_CONFIG |
| * 0b0000, 0b1000..FAB configuration |
| * 0b0001, 0b0010, 0b0011..OPEN configuration |
| * 0b1010, 0b1001, 0b1011..CLOSED configuration |
| * 0bx1xx..FIELD RETURN configuration |
| */ |
| #define SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK) |
| #define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U) |
| #define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U) |
| #define SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK) |
| #define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U) |
| #define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U) |
| /*! OTPMK_ZERO |
| * 0b0..The OTPMK is not zero. |
| * 0b1..The OTPMK is zero. |
| */ |
| #define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK) |
| #define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U) |
| #define SNVS_HPSR_ZMK_ZERO_SHIFT (31U) |
| /*! ZMK_ZERO |
| * 0b0..The ZMK is not zero. |
| * 0b1..The ZMK is zero. |
| */ |
| #define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK) |
| /*! @} */ |
| |
| /*! @name HPSVSR - SNVS_HP Security Violation Status Register */ |
| /*! @{ */ |
| #define SNVS_HPSVSR_SV0_MASK (0x1U) |
| #define SNVS_HPSVSR_SV0_SHIFT (0U) |
| /*! SV0 |
| * 0b0..No Security Violation 0 security violation was detected. |
| * 0b1..Security Violation 0 security violation was detected. |
| */ |
| #define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK) |
| #define SNVS_HPSVSR_SV1_MASK (0x2U) |
| #define SNVS_HPSVSR_SV1_SHIFT (1U) |
| /*! SV1 |
| * 0b0..No Security Violation 1 security violation was detected. |
| * 0b1..Security Violation 1 security violation was detected. |
| */ |
| #define SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK) |
| #define SNVS_HPSVSR_SV2_MASK (0x4U) |
| #define SNVS_HPSVSR_SV2_SHIFT (2U) |
| /*! SV2 |
| * 0b0..No Security Violation 2 security violation was detected. |
| * 0b1..Security Violation 2 security violation was detected. |
| */ |
| #define SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK) |
| #define SNVS_HPSVSR_SV3_MASK (0x8U) |
| #define SNVS_HPSVSR_SV3_SHIFT (3U) |
| /*! SV3 |
| * 0b0..No Security Violation 3 security violation was detected. |
| * 0b1..Security Violation 3 security violation was detected. |
| */ |
| #define SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK) |
| #define SNVS_HPSVSR_SV4_MASK (0x10U) |
| #define SNVS_HPSVSR_SV4_SHIFT (4U) |
| /*! SV4 |
| * 0b0..No Security Violation 4 security violation was detected. |
| * 0b1..Security Violation 4 security violation was detected. |
| */ |
| #define SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK) |
| #define SNVS_HPSVSR_SV5_MASK (0x20U) |
| #define SNVS_HPSVSR_SV5_SHIFT (5U) |
| /*! SV5 |
| * 0b0..No Security Violation 5 security violation was detected. |
| * 0b1..Security Violation 5 security violation was detected. |
| */ |
| #define SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK) |
| #define SNVS_HPSVSR_SW_SV_MASK (0x2000U) |
| #define SNVS_HPSVSR_SW_SV_SHIFT (13U) |
| #define SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK) |
| #define SNVS_HPSVSR_SW_FSV_MASK (0x4000U) |
| #define SNVS_HPSVSR_SW_FSV_SHIFT (14U) |
| #define SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK) |
| #define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U) |
| #define SNVS_HPSVSR_SW_LPSV_SHIFT (15U) |
| #define SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK) |
| #define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U) |
| #define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U) |
| #define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK) |
| #define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U) |
| #define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U) |
| /*! ZMK_ECC_FAIL |
| * 0b0..ZMK ECC Failure was not detected. |
| * 0b1..ZMK ECC Failure was detected. |
| */ |
| #define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK) |
| #define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U) |
| #define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U) |
| #define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK) |
| /*! @} */ |
| |
| /*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */ |
| /*! @{ */ |
| #define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU) |
| #define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U) |
| #define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK) |
| /*! @} */ |
| |
| /*! @name HPHACR - SNVS_HP High Assurance Counter Register */ |
| /*! @{ */ |
| #define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU) |
| #define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U) |
| #define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK) |
| /*! @} */ |
| |
| /*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */ |
| /*! @{ */ |
| #define SNVS_HPRTCMR_RTC_MASK (0x7FFFU) |
| #define SNVS_HPRTCMR_RTC_SHIFT (0U) |
| #define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK) |
| /*! @} */ |
| |
| /*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */ |
| /*! @{ */ |
| #define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU) |
| #define SNVS_HPRTCLR_RTC_SHIFT (0U) |
| #define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK) |
| /*! @} */ |
| |
| /*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */ |
| /*! @{ */ |
| #define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU) |
| #define SNVS_HPTAMR_HPTA_MS_SHIFT (0U) |
| #define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK) |
| /*! @} */ |
| |
| /*! @name HPTALR - SNVS_HP Time Alarm LSB Register */ |
| /*! @{ */ |
| #define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU) |
| #define SNVS_HPTALR_HPTA_LS_SHIFT (0U) |
| #define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK) |
| /*! @} */ |
| |
| /*! @name LPLR - SNVS_LP Lock Register */ |
| /*! @{ */ |
| #define SNVS_LPLR_ZMK_WHL_MASK (0x1U) |
| #define SNVS_LPLR_ZMK_WHL_SHIFT (0U) |
| /*! ZMK_WHL |
| * 0b0..Write access is allowed. |
| * 0b1..Write access is not allowed. |
| */ |
| #define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK) |
| #define SNVS_LPLR_ZMK_RHL_MASK (0x2U) |
| #define SNVS_LPLR_ZMK_RHL_SHIFT (1U) |
| /*! ZMK_RHL |
| * 0b0..Read access is allowed (only in software programming mode). |
| * 0b1..Read access is not allowed. |
| */ |
| #define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK) |
| #define SNVS_LPLR_SRTC_HL_MASK (0x4U) |
| #define SNVS_LPLR_SRTC_HL_SHIFT (2U) |
| /*! SRTC_HL |
| * 0b0..Write access is allowed. |
| * 0b1..Write access is not allowed. |
| */ |
| #define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK) |
| #define SNVS_LPLR_LPCALB_HL_MASK (0x8U) |
| #define SNVS_LPLR_LPCALB_HL_SHIFT (3U) |
| /*! LPCALB_HL |
| * 0b0..Write access is allowed. |
| * 0b1..Write access is not allowed. |
| */ |
| #define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK) |
| #define SNVS_LPLR_MC_HL_MASK (0x10U) |
| #define SNVS_LPLR_MC_HL_SHIFT (4U) |
| /*! MC_HL |
| * 0b0..Write access (increment) is allowed. |
| * 0b1..Write access (increment) is not allowed. |
| */ |
| #define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK) |
| #define SNVS_LPLR_GPR_HL_MASK (0x20U) |
| #define SNVS_LPLR_GPR_HL_SHIFT (5U) |
| /*! GPR_HL |
| * 0b0..Write access is allowed. |
| * 0b1..Write access is not allowed. |
| */ |
| #define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK) |
| #define SNVS_LPLR_LPSVCR_HL_MASK (0x40U) |
| #define SNVS_LPLR_LPSVCR_HL_SHIFT (6U) |
| /*! LPSVCR_HL |
| * 0b0..Write access is allowed. |
| * 0b1..Write access is not allowed. |
| */ |
| #define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK) |
| #define SNVS_LPLR_LPSECR_HL_MASK (0x100U) |
| #define SNVS_LPLR_LPSECR_HL_SHIFT (8U) |
| /*! LPSECR_HL |
| * 0b0..Write access is allowed. |
| * 0b1..Write access is not allowed. |
| */ |
| #define SNVS_LPLR_LPSECR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSECR_HL_SHIFT)) & SNVS_LPLR_LPSECR_HL_MASK) |
| #define SNVS_LPLR_MKS_HL_MASK (0x200U) |
| #define SNVS_LPLR_MKS_HL_SHIFT (9U) |
| /*! MKS_HL |
| * 0b0..Write access is allowed. |
| * 0b1..Write access is not allowed. |
| */ |
| #define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK) |
| /*! @} */ |
| |
| /*! @name LPCR - SNVS_LP Control Register */ |
| /*! @{ */ |
| #define SNVS_LPCR_SRTC_ENV_MASK (0x1U) |
| #define SNVS_LPCR_SRTC_ENV_SHIFT (0U) |
| /*! SRTC_ENV |
| * 0b0..SRTC is disabled or invalid. |
| * 0b1..SRTC is enabled and valid. |
| */ |
| #define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK) |
| #define SNVS_LPCR_LPTA_EN_MASK (0x2U) |
| #define SNVS_LPCR_LPTA_EN_SHIFT (1U) |
| /*! LPTA_EN |
| * 0b0..LP time alarm interrupt is disabled. |
| * 0b1..LP time alarm interrupt is enabled. |
| */ |
| #define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK) |
| #define SNVS_LPCR_MC_ENV_MASK (0x4U) |
| #define SNVS_LPCR_MC_ENV_SHIFT (2U) |
| /*! MC_ENV |
| * 0b0..MC is disabled or invalid. |
| * 0b1..MC is enabled and valid. |
| */ |
| #define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK) |
| #define SNVS_LPCR_LPWUI_EN_MASK (0x8U) |
| #define SNVS_LPCR_LPWUI_EN_SHIFT (3U) |
| #define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK) |
| #define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U) |
| #define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U) |
| /*! SRTC_INV_EN |
| * 0b0..SRTC stays valid in the case of security violation. |
| * 0b1..SRTC is invalidated in the case of security violation. |
| */ |
| #define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK) |
| #define SNVS_LPCR_DP_EN_MASK (0x20U) |
| #define SNVS_LPCR_DP_EN_SHIFT (5U) |
| /*! DP_EN |
| * 0b0..Smart PMIC enabled. |
| * 0b1..Dumb PMIC enabled. |
| */ |
| #define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK) |
| #define SNVS_LPCR_TOP_MASK (0x40U) |
| #define SNVS_LPCR_TOP_SHIFT (6U) |
| /*! TOP |
| * 0b0..Leave system power on. |
| * 0b1..Turn off system power. |
| */ |
| #define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK) |
| #define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U) |
| #define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U) |
| #define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK) |
| #define SNVS_LPCR_LPCALB_EN_MASK (0x100U) |
| #define SNVS_LPCR_LPCALB_EN_SHIFT (8U) |
| /*! LPCALB_EN |
| * 0b0..SRTC Time calibration is disabled. |
| * 0b1..SRTC Time calibration is enabled. |
| */ |
| #define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK) |
| #define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U) |
| #define SNVS_LPCR_LPCALB_VAL_SHIFT (10U) |
| /*! LPCALB_VAL |
| * 0b00000..+0 counts per each 32768 ticks of the counter clock |
| * 0b00001..+1 counts per each 32768 ticks of the counter clock |
| * 0b00010..+2 counts per each 32768 ticks of the counter clock |
| * 0b01111..+15 counts per each 32768 ticks of the counter clock |
| * 0b10000..-16 counts per each 32768 ticks of the counter clock |
| * 0b10001..-15 counts per each 32768 ticks of the counter clock |
| * 0b11110..-2 counts per each 32768 ticks of the counter clock |
| * 0b11111..-1 counts per each 32768 ticks of the counter clock |
| */ |
| #define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK) |
| #define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U) |
| #define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U) |
| #define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK) |
| #define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U) |
| #define SNVS_LPCR_DEBOUNCE_SHIFT (18U) |
| #define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK) |
| #define SNVS_LPCR_ON_TIME_MASK (0x300000U) |
| #define SNVS_LPCR_ON_TIME_SHIFT (20U) |
| #define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK) |
| #define SNVS_LPCR_PK_EN_MASK (0x400000U) |
| #define SNVS_LPCR_PK_EN_SHIFT (22U) |
| #define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK) |
| #define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U) |
| #define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U) |
| #define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK) |
| #define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U) |
| #define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U) |
| #define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK) |
| /*! @} */ |
| |
| /*! @name LPMKCR - SNVS_LP Master Key Control Register */ |
| /*! @{ */ |
| #define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U) |
| #define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U) |
| /*! MASTER_KEY_SEL |
| * 0b0x..Select one time programmable master key. |
| */ |
| #define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK) |
| #define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U) |
| #define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U) |
| /*! ZMK_HWP |
| * 0b0..ZMK is in the software programming mode. |
| * 0b1..ZMK is in the hardware programming mode. |
| */ |
| #define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK) |
| #define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U) |
| #define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U) |
| /*! ZMK_VAL |
| * 0b0..ZMK is not valid. |
| * 0b1..ZMK is valid. |
| */ |
| #define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK) |
| #define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U) |
| #define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U) |
| /*! ZMK_ECC_EN |
| * 0b0..ZMK ECC check is disabled. |
| * 0b1..ZMK ECC check is enabled. |
| */ |
| #define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK) |
| #define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U) |
| #define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U) |
| #define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK) |
| /*! @} */ |
| |
| /*! @name LPSVCR - SNVS_LP Security Violation Control Register */ |
| /*! @{ */ |
| #define SNVS_LPSVCR_SV0_EN_MASK (0x1U) |
| #define SNVS_LPSVCR_SV0_EN_SHIFT (0U) |
| /*! SV0_EN |
| * 0b0..Security Violation 0 is disabled in the LP domain. |
| * 0b1..Security Violation 0 is enabled in the LP domain. |
| */ |
| #define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK) |
| #define SNVS_LPSVCR_SV1_EN_MASK (0x2U) |
| #define SNVS_LPSVCR_SV1_EN_SHIFT (1U) |
| /*! SV1_EN |
| * 0b0..Security Violation 1 is disabled in the LP domain. |
| * 0b1..Security Violation 1 is enabled in the LP domain. |
| */ |
| #define SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK) |
| #define SNVS_LPSVCR_SV2_EN_MASK (0x4U) |
| #define SNVS_LPSVCR_SV2_EN_SHIFT (2U) |
| /*! SV2_EN |
| * 0b0..Security Violation 2 is disabled in the LP domain. |
| * 0b1..Security Violation 2 is enabled in the LP domain. |
| */ |
| #define SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK) |
| #define SNVS_LPSVCR_SV3_EN_MASK (0x8U) |
| #define SNVS_LPSVCR_SV3_EN_SHIFT (3U) |
| /*! SV3_EN |
| * 0b0..Security Violation 3 is disabled in the LP domain. |
| * 0b1..Security Violation 3 is enabled in the LP domain. |
| */ |
| #define SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK) |
| #define SNVS_LPSVCR_SV4_EN_MASK (0x10U) |
| #define SNVS_LPSVCR_SV4_EN_SHIFT (4U) |
| /*! SV4_EN |
| * 0b0..Security Violation 4 is disabled in the LP domain. |
| * 0b1..Security Violation 4 is enabled in the LP domain. |
| */ |
| #define SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK) |
| #define SNVS_LPSVCR_SV5_EN_MASK (0x20U) |
| #define SNVS_LPSVCR_SV5_EN_SHIFT (5U) |
| /*! SV5_EN |
| * 0b0..Security Violation 5 is disabled in the LP domain. |
| * 0b1..Security Violation 5 is enabled in the LP domain. |
| */ |
| #define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK) |
| /*! @} */ |
| |
| /*! @name LPSECR - SNVS_LP Security Events Configuration Register */ |
| /*! @{ */ |
| #define SNVS_LPSECR_SRTCR_EN_MASK (0x2U) |
| #define SNVS_LPSECR_SRTCR_EN_SHIFT (1U) |
| /*! SRTCR_EN |
| * 0b0..SRTC rollover is disabled. |
| * 0b1..SRTC rollover is enabled. |
| */ |
| #define SNVS_LPSECR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_SRTCR_EN_SHIFT)) & SNVS_LPSECR_SRTCR_EN_MASK) |
| #define SNVS_LPSECR_MCR_EN_MASK (0x4U) |
| #define SNVS_LPSECR_MCR_EN_SHIFT (2U) |
| /*! MCR_EN |
| * 0b0..MC rollover is disabled. |
| * 0b1..MC rollover is enabled. |
| */ |
| #define SNVS_LPSECR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_MCR_EN_SHIFT)) & SNVS_LPSECR_MCR_EN_MASK) |
| #define SNVS_LPSECR_PFD_OBSERV_MASK (0x4000U) |
| #define SNVS_LPSECR_PFD_OBSERV_SHIFT (14U) |
| #define SNVS_LPSECR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_PFD_OBSERV_SHIFT)) & SNVS_LPSECR_PFD_OBSERV_MASK) |
| #define SNVS_LPSECR_POR_OBSERV_MASK (0x8000U) |
| #define SNVS_LPSECR_POR_OBSERV_SHIFT (15U) |
| #define SNVS_LPSECR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_POR_OBSERV_SHIFT)) & SNVS_LPSECR_POR_OBSERV_MASK) |
| #define SNVS_LPSECR_LTDC_MASK (0x70000U) |
| #define SNVS_LPSECR_LTDC_SHIFT (16U) |
| #define SNVS_LPSECR_LTDC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_LTDC_SHIFT)) & SNVS_LPSECR_LTDC_MASK) |
| #define SNVS_LPSECR_HTDC_MASK (0x700000U) |
| #define SNVS_LPSECR_HTDC_SHIFT (20U) |
| #define SNVS_LPSECR_HTDC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_HTDC_SHIFT)) & SNVS_LPSECR_HTDC_MASK) |
| #define SNVS_LPSECR_VRC_MASK (0x7000000U) |
| #define SNVS_LPSECR_VRC_SHIFT (24U) |
| #define SNVS_LPSECR_VRC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_VRC_SHIFT)) & SNVS_LPSECR_VRC_MASK) |
| #define SNVS_LPSECR_OSCB_MASK (0x10000000U) |
| #define SNVS_LPSECR_OSCB_SHIFT (28U) |
| /*! OSCB |
| * 0b0..Normal SRTC clock oscillator not bypassed. |
| * 0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source. |
| */ |
| #define SNVS_LPSECR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_OSCB_SHIFT)) & SNVS_LPSECR_OSCB_MASK) |
| /*! @} */ |
| |
| /*! @name LPSR - SNVS_LP Status Register */ |
| /*! @{ */ |
| #define SNVS_LPSR_LPTA_MASK (0x1U) |
| #define SNVS_LPSR_LPTA_SHIFT (0U) |
| /*! LPTA |
| * 0b0..No time alarm interrupt occurred. |
| * 0b1..A time alarm interrupt occurred. |
| */ |
| #define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK) |
| #define SNVS_LPSR_SRTCR_MASK (0x2U) |
| #define SNVS_LPSR_SRTCR_SHIFT (1U) |
| /*! SRTCR |
| * 0b0..SRTC has not reached its maximum value. |
| * 0b1..SRTC has reached its maximum value. |
| */ |
| #define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK) |
| #define SNVS_LPSR_MCR_MASK (0x4U) |
| #define SNVS_LPSR_MCR_SHIFT (2U) |
| /*! MCR |
| * 0b0..MC has not reached its maximum value. |
| * 0b1..MC has reached its maximum value. |
| */ |
| #define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK) |
| #define SNVS_LPSR_PGD_MASK (0x8U) |
| #define SNVS_LPSR_PGD_SHIFT (3U) |
| #define SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK) |
| #define SNVS_LPSR_ESVD_MASK (0x10000U) |
| #define SNVS_LPSR_ESVD_SHIFT (16U) |
| /*! ESVD |
| * 0b0..No external security violation. |
| * 0b1..External security violation is detected. |
| */ |
| #define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK) |
| #define SNVS_LPSR_EO_MASK (0x20000U) |
| #define SNVS_LPSR_EO_SHIFT (17U) |
| /*! EO |
| * 0b0..Emergency off was not detected. |
| * 0b1..Emergency off was detected. |
| */ |
| #define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK) |
| #define SNVS_LPSR_SPO_MASK (0x40000U) |
| #define SNVS_LPSR_SPO_SHIFT (18U) |
| /*! SPO |
| * 0b0..Set Power Off was not detected. |
| * 0b1..Set Power Off was detected. |
| */ |
| #define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK) |
| #define SNVS_LPSR_LPNS_MASK (0x40000000U) |
| #define SNVS_LPSR_LPNS_SHIFT (30U) |
| /*! LPNS |
| * 0b0..LP section was not programmed in the non-secure state. |
| * 0b1..LP section was programmed in the non-secure state. |
| */ |
| #define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK) |
| #define SNVS_LPSR_LPS_MASK (0x80000000U) |
| #define SNVS_LPSR_LPS_SHIFT (31U) |
| /*! LPS |
| * 0b0..LP section was not programmed in secure or trusted state. |
| * 0b1..LP section was programmed in secure or trusted state. |
| */ |
| #define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK) |
| /*! @} */ |
| |
| /*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */ |
| /*! @{ */ |
| #define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU) |
| #define SNVS_LPSRTCMR_SRTC_SHIFT (0U) |
| #define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK) |
| /*! @} */ |
| |
| /*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */ |
| /*! @{ */ |
| #define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU) |
| #define SNVS_LPSRTCLR_SRTC_SHIFT (0U) |
| #define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK) |
| /*! @} */ |
| |
| /*! @name LPTAR - SNVS_LP Time Alarm Register */ |
| /*! @{ */ |
| #define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU) |
| #define SNVS_LPTAR_LPTA_SHIFT (0U) |
| #define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK) |
| /*! @} */ |
| |
| /*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */ |
| /*! @{ */ |
| #define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU) |
| #define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U) |
| #define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK) |
| #define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U) |
| #define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U) |
| #define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK) |
| /*! @} */ |
| |
| /*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */ |
| /*! @{ */ |
| #define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU) |
| #define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U) |
| #define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK) |
| /*! @} */ |
| |
| /*! @name LPPGDR - SNVS_LP Power Glitch Detector Register */ |
| /*! @{ */ |
| #define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU) |
| #define SNVS_LPPGDR_PGD_SHIFT (0U) |
| #define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK) |
| /*! @} */ |
| |
| /*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */ |
| /*! @{ */ |
| #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU) |
| #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U) |
| #define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK) |
| /*! @} */ |
| |
| /*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */ |
| /*! @{ */ |
| #define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU) |
| #define SNVS_LPZMKR_ZMK_SHIFT (0U) |
| #define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK) |
| /*! @} */ |
| |
| /* The count of SNVS_LPZMKR */ |
| #define SNVS_LPZMKR_COUNT (8U) |
| |
| /*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */ |
| /*! @{ */ |
| #define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU) |
| #define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U) |
| #define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK) |
| /*! @} */ |
| |
| /* The count of SNVS_LPGPR_ALIAS */ |
| #define SNVS_LPGPR_ALIAS_COUNT (4U) |
| |
| /*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 3 */ |
| /*! @{ */ |
| #define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU) |
| #define SNVS_LPGPR_GPR_SHIFT (0U) |
| #define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK) |
| /*! @} */ |
| |
| /* The count of SNVS_LPGPR */ |
| #define SNVS_LPGPR_COUNT (4U) |
| |
| /*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */ |
| /*! @{ */ |
| #define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU) |
| #define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U) |
| #define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK) |
| #define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U) |
| #define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U) |
| #define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK) |
| #define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U) |
| #define SNVS_HPVIDR1_IP_ID_SHIFT (16U) |
| #define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK) |
| /*! @} */ |
| |
| /*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */ |
| /*! @{ */ |
| #define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU) |
| #define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U) |
| #define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK) |
| #define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U) |
| #define SNVS_HPVIDR2_ECO_REV_SHIFT (8U) |
| #define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK) |
| #define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U) |
| #define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U) |
| #define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK) |
| #define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U) |
| #define SNVS_HPVIDR2_IP_ERA_SHIFT (24U) |
| #define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group SNVS_Register_Masks */ |
| |
| |
| /* SNVS - Peripheral instance base addresses */ |
| /** Peripheral SNVS base address */ |
| #define SNVS_BASE (0x30370000u) |
| /** Peripheral SNVS base pointer */ |
| #define SNVS ((SNVS_Type *)SNVS_BASE) |
| /** Array initializer of SNVS peripheral base addresses */ |
| #define SNVS_BASE_ADDRS { SNVS_BASE } |
| /** Array initializer of SNVS peripheral base pointers */ |
| #define SNVS_BASE_PTRS { SNVS } |
| /** Interrupt vectors for the SNVS peripheral type */ |
| #define SNVS_IRQS { SNVS_IRQn } |
| #define SNVS_CONSOLIDATED_IRQS { SNVS_Consolidated_IRQn } |
| #define SNVS_SECURITY_IRQS { SNVS_Security_IRQn } |
| |
| /*! |
| * @} |
| */ /* end of group SNVS_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- SPBA Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SPBA_Peripheral_Access_Layer SPBA Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** SPBA - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t PRR[32]; /**< Peripheral Rights Register, array offset: 0x0, array step: 0x4 */ |
| } SPBA_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- SPBA Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SPBA_Register_Masks SPBA Register Masks |
| * @{ |
| */ |
| |
| /*! @name PRR - Peripheral Rights Register */ |
| /*! @{ */ |
| #define SPBA_PRR_RARA_MASK (0x1U) |
| #define SPBA_PRR_RARA_SHIFT (0U) |
| /*! RARA |
| * 0b0..Access to peripheral is not allowed. |
| * 0b1..Access to peripheral is granted. |
| */ |
| #define SPBA_PRR_RARA(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARA_SHIFT)) & SPBA_PRR_RARA_MASK) |
| #define SPBA_PRR_RARB_MASK (0x2U) |
| #define SPBA_PRR_RARB_SHIFT (1U) |
| /*! RARB |
| * 0b0..Access to peripheral is not allowed. |
| * 0b1..Access to peripheral is granted. |
| */ |
| #define SPBA_PRR_RARB(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARB_SHIFT)) & SPBA_PRR_RARB_MASK) |
| #define SPBA_PRR_RARC_MASK (0x4U) |
| #define SPBA_PRR_RARC_SHIFT (2U) |
| /*! RARC |
| * 0b0..Access to peripheral is not allowed. |
| * 0b1..Access to peripheral is granted. |
| */ |
| #define SPBA_PRR_RARC(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARC_SHIFT)) & SPBA_PRR_RARC_MASK) |
| #define SPBA_PRR_ROI_MASK (0x30000U) |
| #define SPBA_PRR_ROI_SHIFT (16U) |
| /*! ROI |
| * 0b00..Unowned resource. |
| * 0b01..The resource is owned by master A port. |
| * 0b10..The resource is owned by master B port. |
| * 0b11..The resource is owned by master C port. |
| */ |
| #define SPBA_PRR_ROI(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_ROI_SHIFT)) & SPBA_PRR_ROI_MASK) |
| #define SPBA_PRR_RMO_MASK (0xC0000000U) |
| #define SPBA_PRR_RMO_SHIFT (30U) |
| /*! RMO |
| * 0b00..The resource is unowned. |
| * 0b01..Reserved. |
| * 0b10..The resource is owned by another master. |
| * 0b11..The resource is owned by the requesting master. |
| */ |
| #define SPBA_PRR_RMO(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RMO_SHIFT)) & SPBA_PRR_RMO_MASK) |
| /*! @} */ |
| |
| /* The count of SPBA_PRR */ |
| #define SPBA_PRR_COUNT (32U) |
| |
| |
| /*! |
| * @} |
| */ /* end of group SPBA_Register_Masks */ |
| |
| |
| /* SPBA - Peripheral instance base addresses */ |
| /** Peripheral SPBA1 base address */ |
| #define SPBA1_BASE (0x308F0000u) |
| /** Peripheral SPBA1 base pointer */ |
| #define SPBA1 ((SPBA_Type *)SPBA1_BASE) |
| /** Peripheral SPBA2 base address */ |
| #define SPBA2_BASE (0x300F0000u) |
| /** Peripheral SPBA2 base pointer */ |
| #define SPBA2 ((SPBA_Type *)SPBA2_BASE) |
| /** Array initializer of SPBA peripheral base addresses */ |
| #define SPBA_BASE_ADDRS { 0u, SPBA1_BASE, SPBA2_BASE } |
| /** Array initializer of SPBA peripheral base pointers */ |
| #define SPBA_BASE_PTRS { (SPBA_Type *)0u, SPBA1, SPBA2 } |
| |
| /*! |
| * @} |
| */ /* end of group SPBA_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- SPDIF Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** SPDIF - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ |
| __IO uint32_t SRCD; /**< CDText Control Register, offset: 0x4 */ |
| __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ |
| __IO uint32_t SIE; /**< InterruptEn Register, offset: 0xC */ |
| union { /* offset: 0x10 */ |
| __O uint32_t SIC; /**< InterruptClear Register, offset: 0x10 */ |
| __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ |
| }; |
| __I uint32_t SRL; /**< SPDIFRxLeft Register, offset: 0x14 */ |
| __I uint32_t SRR; /**< SPDIFRxRight Register, offset: 0x18 */ |
| __I uint32_t SRCSH; /**< SPDIFRxCChannel_h Register, offset: 0x1C */ |
| __I uint32_t SRCSL; /**< SPDIFRxCChannel_l Register, offset: 0x20 */ |
| __I uint32_t SRU; /**< UchannelRx Register, offset: 0x24 */ |
| __I uint32_t SRQ; /**< QchannelRx Register, offset: 0x28 */ |
| __O uint32_t STL; /**< SPDIFTxLeft Register, offset: 0x2C */ |
| __O uint32_t STR; /**< SPDIFTxRight Register, offset: 0x30 */ |
| __IO uint32_t STCSCH; /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */ |
| __IO uint32_t STCSCL; /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */ |
| uint8_t RESERVED_0[8]; |
| __I uint32_t SRFM; /**< FreqMeas Register, offset: 0x44 */ |
| uint8_t RESERVED_1[8]; |
| __IO uint32_t STC; /**< SPDIFTxClk Register, offset: 0x50 */ |
| } SPDIF_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- SPDIF Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SPDIF_Register_Masks SPDIF Register Masks |
| * @{ |
| */ |
| |
| /*! @name SCR - SPDIF Configuration Register */ |
| /*! @{ */ |
| #define SPDIF_SCR_USRC_SEL_MASK (0x3U) |
| #define SPDIF_SCR_USRC_SEL_SHIFT (0U) |
| /*! USrc_Sel |
| * 0b00..No embedded U channel |
| * 0b01..U channel from SPDIF receive block (CD mode) |
| * 0b10..Reserved |
| * 0b11..U channel from on chip transmitter |
| */ |
| #define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK) |
| #define SPDIF_SCR_TXSEL_MASK (0x1CU) |
| #define SPDIF_SCR_TXSEL_SHIFT (2U) |
| /*! TxSel |
| * 0b000..Off and output 0 |
| * 0b001..Feed-through SPDIFIN |
| * 0b101..Tx Normal operation |
| */ |
| #define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK) |
| #define SPDIF_SCR_VALCTRL_MASK (0x20U) |
| #define SPDIF_SCR_VALCTRL_SHIFT (5U) |
| /*! ValCtrl |
| * 0b0..Outgoing Validity always set |
| * 0b1..Outgoing Validity always clear |
| */ |
| #define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK) |
| #define SPDIF_SCR_DMA_TX_EN_MASK (0x100U) |
| #define SPDIF_SCR_DMA_TX_EN_SHIFT (8U) |
| #define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK) |
| #define SPDIF_SCR_DMA_RX_EN_MASK (0x200U) |
| #define SPDIF_SCR_DMA_RX_EN_SHIFT (9U) |
| #define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK) |
| #define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U) |
| #define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U) |
| /*! TxFIFO_Ctrl |
| * 0b00..Send out digital zero on SPDIF Tx |
| * 0b01..Tx Normal operation |
| * 0b10..Reset to 1 sample remaining |
| * 0b11..Reserved |
| */ |
| #define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK) |
| #define SPDIF_SCR_SOFT_RESET_MASK (0x1000U) |
| #define SPDIF_SCR_SOFT_RESET_SHIFT (12U) |
| #define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK) |
| #define SPDIF_SCR_LOW_POWER_MASK (0x2000U) |
| #define SPDIF_SCR_LOW_POWER_SHIFT (13U) |
| #define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK) |
| #define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U) |
| #define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U) |
| /*! TxFIFOEmpty_Sel |
| * 0b00..Empty interrupt if 0 sample in Tx left and right FIFOs |
| * 0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs |
| * 0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs |
| * 0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs |
| */ |
| #define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) |
| #define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U) |
| #define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U) |
| /*! TxAutoSync |
| * 0b0..Tx FIFO auto sync off |
| * 0b1..Tx FIFO auto sync on |
| */ |
| #define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK) |
| #define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U) |
| #define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U) |
| /*! RxAutoSync |
| * 0b0..Rx FIFO auto sync off |
| * 0b1..RxFIFO auto sync on |
| */ |
| #define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK) |
| #define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U) |
| #define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U) |
| /*! RxFIFOFull_Sel |
| * 0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs |
| * 0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs |
| * 0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs |
| * 0b11..Full interrupt if at least 16 sample in Rx left and right FIFO |
| */ |
| #define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK) |
| #define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U) |
| #define SPDIF_SCR_RXFIFO_RST_SHIFT (21U) |
| /*! RxFIFO_Rst |
| * 0b0..Normal operation |
| * 0b1..Reset register to 1 sample remaining |
| */ |
| #define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK) |
| #define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U) |
| #define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U) |
| /*! RxFIFO_Off_On |
| * 0b0..SPDIF Rx FIFO is on |
| * 0b1..SPDIF Rx FIFO is off. Does not accept data from interface |
| */ |
| #define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK) |
| #define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U) |
| #define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U) |
| /*! RxFIFO_Ctrl |
| * 0b0..Normal operation |
| * 0b1..Always read zero from Rx data register |
| */ |
| #define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK) |
| /*! @} */ |
| |
| /*! @name SRCD - CDText Control Register */ |
| /*! @{ */ |
| #define SPDIF_SRCD_USYNCMODE_MASK (0x2U) |
| #define SPDIF_SRCD_USYNCMODE_SHIFT (1U) |
| /*! USyncMode |
| * 0b0..Non-CD data |
| * 0b1..CD user channel subcode |
| */ |
| #define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK) |
| /*! @} */ |
| |
| /*! @name SRPC - PhaseConfig Register */ |
| /*! @{ */ |
| #define SPDIF_SRPC_GAINSEL_MASK (0x38U) |
| #define SPDIF_SRPC_GAINSEL_SHIFT (3U) |
| /*! GainSel |
| * 0b000..24*(2**10) |
| * 0b001..16*(2**10) |
| * 0b010..12*(2**10) |
| * 0b011..8*(2**10) |
| * 0b100..6*(2**10) |
| * 0b101..4*(2**10) |
| * 0b110..3*(2**10) |
| */ |
| #define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK) |
| #define SPDIF_SRPC_LOCK_MASK (0x40U) |
| #define SPDIF_SRPC_LOCK_SHIFT (6U) |
| #define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK) |
| #define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U) |
| #define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U) |
| /*! ClkSrc_Sel |
| * 0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC) |
| * 0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT) |
| * 0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK |
| * 0b0101..REF_CLK_32K (XTALOSC) |
| * 0b0110..tx_clk (SPDIF0_CLK_ROOT) |
| * 0b1000..SPDIF_EXT_CLK |
| */ |
| #define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name SIE - InterruptEn Register */ |
| /*! @{ */ |
| #define SPDIF_SIE_RXFIFOFUL_MASK (0x1U) |
| #define SPDIF_SIE_RXFIFOFUL_SHIFT (0U) |
| #define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK) |
| #define SPDIF_SIE_TXEM_MASK (0x2U) |
| #define SPDIF_SIE_TXEM_SHIFT (1U) |
| #define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK) |
| #define SPDIF_SIE_LOCKLOSS_MASK (0x4U) |
| #define SPDIF_SIE_LOCKLOSS_SHIFT (2U) |
| #define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK) |
| #define SPDIF_SIE_RXFIFORESYN_MASK (0x8U) |
| #define SPDIF_SIE_RXFIFORESYN_SHIFT (3U) |
| #define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK) |
| #define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U) |
| #define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U) |
| #define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK) |
| #define SPDIF_SIE_UQERR_MASK (0x20U) |
| #define SPDIF_SIE_UQERR_SHIFT (5U) |
| #define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK) |
| #define SPDIF_SIE_UQSYNC_MASK (0x40U) |
| #define SPDIF_SIE_UQSYNC_SHIFT (6U) |
| #define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK) |
| #define SPDIF_SIE_QRXOV_MASK (0x80U) |
| #define SPDIF_SIE_QRXOV_SHIFT (7U) |
| #define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK) |
| #define SPDIF_SIE_QRXFUL_MASK (0x100U) |
| #define SPDIF_SIE_QRXFUL_SHIFT (8U) |
| #define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK) |
| #define SPDIF_SIE_URXOV_MASK (0x200U) |
| #define SPDIF_SIE_URXOV_SHIFT (9U) |
| #define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK) |
| #define SPDIF_SIE_URXFUL_MASK (0x400U) |
| #define SPDIF_SIE_URXFUL_SHIFT (10U) |
| #define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK) |
| #define SPDIF_SIE_BITERR_MASK (0x4000U) |
| #define SPDIF_SIE_BITERR_SHIFT (14U) |
| #define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK) |
| #define SPDIF_SIE_SYMERR_MASK (0x8000U) |
| #define SPDIF_SIE_SYMERR_SHIFT (15U) |
| #define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK) |
| #define SPDIF_SIE_VALNOGOOD_MASK (0x10000U) |
| #define SPDIF_SIE_VALNOGOOD_SHIFT (16U) |
| #define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK) |
| #define SPDIF_SIE_CNEW_MASK (0x20000U) |
| #define SPDIF_SIE_CNEW_SHIFT (17U) |
| #define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK) |
| #define SPDIF_SIE_TXRESYN_MASK (0x40000U) |
| #define SPDIF_SIE_TXRESYN_SHIFT (18U) |
| #define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK) |
| #define SPDIF_SIE_TXUNOV_MASK (0x80000U) |
| #define SPDIF_SIE_TXUNOV_SHIFT (19U) |
| #define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK) |
| #define SPDIF_SIE_LOCK_MASK (0x100000U) |
| #define SPDIF_SIE_LOCK_SHIFT (20U) |
| #define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK) |
| /*! @} */ |
| |
| /*! @name SIC - InterruptClear Register */ |
| /*! @{ */ |
| #define SPDIF_SIC_LOCKLOSS_MASK (0x4U) |
| #define SPDIF_SIC_LOCKLOSS_SHIFT (2U) |
| #define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK) |
| #define SPDIF_SIC_RXFIFORESYN_MASK (0x8U) |
| #define SPDIF_SIC_RXFIFORESYN_SHIFT (3U) |
| #define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK) |
| #define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U) |
| #define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U) |
| #define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK) |
| #define SPDIF_SIC_UQERR_MASK (0x20U) |
| #define SPDIF_SIC_UQERR_SHIFT (5U) |
| #define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK) |
| #define SPDIF_SIC_UQSYNC_MASK (0x40U) |
| #define SPDIF_SIC_UQSYNC_SHIFT (6U) |
| #define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK) |
| #define SPDIF_SIC_QRXOV_MASK (0x80U) |
| #define SPDIF_SIC_QRXOV_SHIFT (7U) |
| #define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK) |
| #define SPDIF_SIC_URXOV_MASK (0x200U) |
| #define SPDIF_SIC_URXOV_SHIFT (9U) |
| #define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK) |
| #define SPDIF_SIC_BITERR_MASK (0x4000U) |
| #define SPDIF_SIC_BITERR_SHIFT (14U) |
| #define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK) |
| #define SPDIF_SIC_SYMERR_MASK (0x8000U) |
| #define SPDIF_SIC_SYMERR_SHIFT (15U) |
| #define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK) |
| #define SPDIF_SIC_VALNOGOOD_MASK (0x10000U) |
| #define SPDIF_SIC_VALNOGOOD_SHIFT (16U) |
| #define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK) |
| #define SPDIF_SIC_CNEW_MASK (0x20000U) |
| #define SPDIF_SIC_CNEW_SHIFT (17U) |
| #define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK) |
| #define SPDIF_SIC_TXRESYN_MASK (0x40000U) |
| #define SPDIF_SIC_TXRESYN_SHIFT (18U) |
| #define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK) |
| #define SPDIF_SIC_TXUNOV_MASK (0x80000U) |
| #define SPDIF_SIC_TXUNOV_SHIFT (19U) |
| #define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK) |
| #define SPDIF_SIC_LOCK_MASK (0x100000U) |
| #define SPDIF_SIC_LOCK_SHIFT (20U) |
| #define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK) |
| /*! @} */ |
| |
| /*! @name SIS - InterruptStat Register */ |
| /*! @{ */ |
| #define SPDIF_SIS_RXFIFOFUL_MASK (0x1U) |
| #define SPDIF_SIS_RXFIFOFUL_SHIFT (0U) |
| #define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK) |
| #define SPDIF_SIS_TXEM_MASK (0x2U) |
| #define SPDIF_SIS_TXEM_SHIFT (1U) |
| #define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK) |
| #define SPDIF_SIS_LOCKLOSS_MASK (0x4U) |
| #define SPDIF_SIS_LOCKLOSS_SHIFT (2U) |
| #define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK) |
| #define SPDIF_SIS_RXFIFORESYN_MASK (0x8U) |
| #define SPDIF_SIS_RXFIFORESYN_SHIFT (3U) |
| #define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK) |
| #define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U) |
| #define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U) |
| #define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK) |
| #define SPDIF_SIS_UQERR_MASK (0x20U) |
| #define SPDIF_SIS_UQERR_SHIFT (5U) |
| #define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK) |
| #define SPDIF_SIS_UQSYNC_MASK (0x40U) |
| #define SPDIF_SIS_UQSYNC_SHIFT (6U) |
| #define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK) |
| #define SPDIF_SIS_QRXOV_MASK (0x80U) |
| #define SPDIF_SIS_QRXOV_SHIFT (7U) |
| #define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK) |
| #define SPDIF_SIS_QRXFUL_MASK (0x100U) |
| #define SPDIF_SIS_QRXFUL_SHIFT (8U) |
| #define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK) |
| #define SPDIF_SIS_URXOV_MASK (0x200U) |
| #define SPDIF_SIS_URXOV_SHIFT (9U) |
| #define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK) |
| #define SPDIF_SIS_URXFUL_MASK (0x400U) |
| #define SPDIF_SIS_URXFUL_SHIFT (10U) |
| #define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK) |
| #define SPDIF_SIS_BITERR_MASK (0x4000U) |
| #define SPDIF_SIS_BITERR_SHIFT (14U) |
| #define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK) |
| #define SPDIF_SIS_SYMERR_MASK (0x8000U) |
| #define SPDIF_SIS_SYMERR_SHIFT (15U) |
| #define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK) |
| #define SPDIF_SIS_VALNOGOOD_MASK (0x10000U) |
| #define SPDIF_SIS_VALNOGOOD_SHIFT (16U) |
| #define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK) |
| #define SPDIF_SIS_CNEW_MASK (0x20000U) |
| #define SPDIF_SIS_CNEW_SHIFT (17U) |
| #define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK) |
| #define SPDIF_SIS_TXRESYN_MASK (0x40000U) |
| #define SPDIF_SIS_TXRESYN_SHIFT (18U) |
| #define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK) |
| #define SPDIF_SIS_TXUNOV_MASK (0x80000U) |
| #define SPDIF_SIS_TXUNOV_SHIFT (19U) |
| #define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK) |
| #define SPDIF_SIS_LOCK_MASK (0x100000U) |
| #define SPDIF_SIS_LOCK_SHIFT (20U) |
| #define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK) |
| /*! @} */ |
| |
| /*! @name SRL - SPDIFRxLeft Register */ |
| /*! @{ */ |
| #define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU) |
| #define SPDIF_SRL_RXDATALEFT_SHIFT (0U) |
| #define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK) |
| /*! @} */ |
| |
| /*! @name SRR - SPDIFRxRight Register */ |
| /*! @{ */ |
| #define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU) |
| #define SPDIF_SRR_RXDATARIGHT_SHIFT (0U) |
| #define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK) |
| /*! @} */ |
| |
| /*! @name SRCSH - SPDIFRxCChannel_h Register */ |
| /*! @{ */ |
| #define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU) |
| #define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U) |
| #define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK) |
| /*! @} */ |
| |
| /*! @name SRCSL - SPDIFRxCChannel_l Register */ |
| /*! @{ */ |
| #define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU) |
| #define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U) |
| #define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK) |
| /*! @} */ |
| |
| /*! @name SRU - UchannelRx Register */ |
| /*! @{ */ |
| #define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU) |
| #define SPDIF_SRU_RXUCHANNEL_SHIFT (0U) |
| #define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK) |
| /*! @} */ |
| |
| /*! @name SRQ - QchannelRx Register */ |
| /*! @{ */ |
| #define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU) |
| #define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U) |
| #define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK) |
| /*! @} */ |
| |
| /*! @name STL - SPDIFTxLeft Register */ |
| /*! @{ */ |
| #define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU) |
| #define SPDIF_STL_TXDATALEFT_SHIFT (0U) |
| #define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK) |
| /*! @} */ |
| |
| /*! @name STR - SPDIFTxRight Register */ |
| /*! @{ */ |
| #define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU) |
| #define SPDIF_STR_TXDATARIGHT_SHIFT (0U) |
| #define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK) |
| /*! @} */ |
| |
| /*! @name STCSCH - SPDIFTxCChannelCons_h Register */ |
| /*! @{ */ |
| #define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU) |
| #define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U) |
| #define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK) |
| /*! @} */ |
| |
| /*! @name STCSCL - SPDIFTxCChannelCons_l Register */ |
| /*! @{ */ |
| #define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU) |
| #define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U) |
| #define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK) |
| /*! @} */ |
| |
| /*! @name SRFM - FreqMeas Register */ |
| /*! @{ */ |
| #define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU) |
| #define SPDIF_SRFM_FREQMEAS_SHIFT (0U) |
| #define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK) |
| /*! @} */ |
| |
| /*! @name STC - SPDIFTxClk Register */ |
| /*! @{ */ |
| #define SPDIF_STC_TXCLK_DF_MASK (0x7FU) |
| #define SPDIF_STC_TXCLK_DF_SHIFT (0U) |
| /*! TxClk_DF |
| * 0b0000000..divider factor is 1 |
| * 0b0000001..divider factor is 2 |
| * 0b1111111..divider factor is 128 |
| */ |
| #define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK) |
| #define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U) |
| #define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U) |
| /*! tx_all_clk_en |
| * 0b0..disable transfer clock. |
| * 0b1..enable transfer clock. |
| */ |
| #define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK) |
| #define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U) |
| #define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U) |
| /*! TxClk_Source |
| * 0b000..REF_CLK_32K input (XTALOSC 32 kHz clock) |
| * 0b001..tx_clk input (from SPDIF0_CLK_ROOT. See CCM.) |
| * 0b011..SPDIF_EXT_CLK, from pads |
| * 0b101..ipg_clk input (frequency divided) |
| */ |
| #define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK) |
| #define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U) |
| #define SPDIF_STC_SYSCLK_DF_SHIFT (11U) |
| /*! SYSCLK_DF |
| * 0b000000000..no clock signal |
| * 0b000000001..divider factor is 2 |
| * 0b111111111..divider factor is 512 |
| */ |
| #define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group SPDIF_Register_Masks */ |
| |
| |
| /* SPDIF - Peripheral instance base addresses */ |
| /** Peripheral SPDIF1 base address */ |
| #define SPDIF1_BASE (0x30810000u) |
| /** Peripheral SPDIF1 base pointer */ |
| #define SPDIF1 ((SPDIF_Type *)SPDIF1_BASE) |
| /** Peripheral SPDIF2 base address */ |
| #define SPDIF2_BASE (0x308A0000u) |
| /** Peripheral SPDIF2 base pointer */ |
| #define SPDIF2 ((SPDIF_Type *)SPDIF2_BASE) |
| /** Array initializer of SPDIF peripheral base addresses */ |
| #define SPDIF_BASE_ADDRS { 0u, SPDIF1_BASE, SPDIF2_BASE } |
| /** Array initializer of SPDIF peripheral base pointers */ |
| #define SPDIF_BASE_PTRS { (SPDIF_Type *)0u, SPDIF1, SPDIF2 } |
| /** Interrupt vectors for the SPDIF peripheral type */ |
| #define SPDIF_IRQS { NotAvail_IRQn, SPDIF1_IRQn, SPDIF2_IRQn } |
| |
| /*! |
| * @} |
| */ /* end of group SPDIF_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- SRC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** SRC - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t SCR; /**< SRC Reset Control Register, offset: 0x0 */ |
| __IO uint32_t A53RCR0; /**< A53 Reset Control Register, offset: 0x4 */ |
| __IO uint32_t A53RCR1; /**< A53 Reset Control Register, offset: 0x8 */ |
| __IO uint32_t M4RCR; /**< M4 Reset Control Register, offset: 0xC */ |
| uint8_t RESERVED_0[16]; |
| __IO uint32_t USBOPHY1_RCR; /**< USB OTG PHY1 Reset Control Register, offset: 0x20 */ |
| __IO uint32_t USBOPHY2_RCR; /**< USB OTG PHY2 Reset Control Register, offset: 0x24 */ |
| __IO uint32_t MIPIPHY_RCR; /**< MIPI PHY Reset Control Register, offset: 0x28 */ |
| __IO uint32_t PCIEPHY_RCR; /**< PCIE PHY Reset Control Register, offset: 0x2C */ |
| __IO uint32_t HDMI_RCR; /**< HDMI Reset Control Register, offset: 0x30 */ |
| __IO uint32_t DISP_RCR; /**< DISP Reset Control Register, offset: 0x34 */ |
| uint8_t RESERVED_1[8]; |
| __IO uint32_t GPU_RCR; /**< GPU Reset Control Register, offset: 0x40 */ |
| __IO uint32_t VPU_RCR; /**< VPU Reset Control Register, offset: 0x44 */ |
| __IO uint32_t PCIE2_RCR; /**< PCIE2 Reset Control Register, offset: 0x48 */ |
| __IO uint32_t MIPIPHY1_RCR; /**< MIPI CSI1 PHY Reset Control Register, offset: 0x4C */ |
| __IO uint32_t MIPIPHY2_RCR; /**< MIPI CSI2 PHY Reset Control Register, offset: 0x50 */ |
| uint8_t RESERVED_2[4]; |
| __I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x58 */ |
| __IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x5C */ |
| uint8_t RESERVED_3[8]; |
| __I uint32_t SISR; /**< SRC Interrupt Status Register, offset: 0x68 */ |
| __IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0x6C */ |
| __IO uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x70 */ |
| __IO uint32_t GPR[10]; /**< SRC General Purpose Register 1..SRC General Purpose Register 10, array offset: 0x74, array step: 0x4 */ |
| uint8_t RESERVED_4[3940]; |
| __IO uint32_t DDRC_RCR; /**< SRC DDR Controller Reset Control Register, offset: 0x1000 */ |
| __IO uint32_t DDRC2_RCR; /**< SRC DDRC2 Controller Reset Control Register, offset: 0x1004 */ |
| } SRC_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- SRC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SRC_Register_Masks SRC Register Masks |
| * @{ |
| */ |
| |
| /*! @name SCR - SRC Reset Control Register */ |
| /*! @{ */ |
| #define SRC_SCR_MASK_TEMPSENSE_RESET_MASK (0xF0U) |
| #define SRC_SCR_MASK_TEMPSENSE_RESET_SHIFT (4U) |
| /*! MASK_TEMPSENSE_RESET |
| * 0b0101..tempsense_reset is masked |
| * 0b1010..tempsense_reset is not masked |
| */ |
| #define SRC_SCR_MASK_TEMPSENSE_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_TEMPSENSE_RESET_SHIFT)) & SRC_SCR_MASK_TEMPSENSE_RESET_MASK) |
| #define SRC_SCR_DOMAIN0_MASK (0x1000000U) |
| #define SRC_SCR_DOMAIN0_SHIFT (24U) |
| /*! DOMAIN0 |
| * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain0. The master from domain3 can write to this register |
| */ |
| #define SRC_SCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN0_SHIFT)) & SRC_SCR_DOMAIN0_MASK) |
| #define SRC_SCR_DOMAIN1_MASK (0x2000000U) |
| #define SRC_SCR_DOMAIN1_SHIFT (25U) |
| /*! DOMAIN1 |
| * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain1. The master from domain3 can write to this register |
| */ |
| #define SRC_SCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN1_SHIFT)) & SRC_SCR_DOMAIN1_MASK) |
| #define SRC_SCR_DOMAIN2_MASK (0x4000000U) |
| #define SRC_SCR_DOMAIN2_SHIFT (26U) |
| /*! DOMAIN2 |
| * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain2. The master from domain3 can write to this register |
| */ |
| #define SRC_SCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN2_SHIFT)) & SRC_SCR_DOMAIN2_MASK) |
| #define SRC_SCR_DOMAIN3_MASK (0x8000000U) |
| #define SRC_SCR_DOMAIN3_SHIFT (27U) |
| /*! DOMAIN3 |
| * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain3. The master from domain3 can write to this register |
| */ |
| #define SRC_SCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN3_SHIFT)) & SRC_SCR_DOMAIN3_MASK) |
| #define SRC_SCR_LOCK_MASK (0x40000000U) |
| #define SRC_SCR_LOCK_SHIFT (30U) |
| /*! LOCK |
| * 0b0..[31] and [27:24] bits can be modified |
| * 0b1..[31] and [27:24] bits cannot be modified |
| */ |
| #define SRC_SCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_LOCK_SHIFT)) & SRC_SCR_LOCK_MASK) |
| #define SRC_SCR_DOM_EN_MASK (0x80000000U) |
| #define SRC_SCR_DOM_EN_SHIFT (31U) |
| /*! DOM_EN |
| * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters |
| * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. |
| */ |
| #define SRC_SCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOM_EN_SHIFT)) & SRC_SCR_DOM_EN_MASK) |
| /*! @} */ |
| |
| /*! @name A53RCR0 - A53 Reset Control Register */ |
| /*! @{ */ |
| #define SRC_A53RCR0_A53_CORE_POR_RESET0_MASK (0x1U) |
| #define SRC_A53RCR0_A53_CORE_POR_RESET0_SHIFT (0U) |
| /*! A53_CORE_POR_RESET0 |
| * 0b0..do not assert core0 reset |
| * 0b1..assert core0 reset |
| */ |
| #define SRC_A53RCR0_A53_CORE_POR_RESET0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET0_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET0_MASK) |
| #define SRC_A53RCR0_A53_CORE_POR_RESET1_MASK (0x2U) |
| #define SRC_A53RCR0_A53_CORE_POR_RESET1_SHIFT (1U) |
| /*! A53_CORE_POR_RESET1 |
| * 0b0..do not assert core1 reset |
| * 0b1..assert core1 reset |
| */ |
| #define SRC_A53RCR0_A53_CORE_POR_RESET1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET1_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET1_MASK) |
| #define SRC_A53RCR0_A53_CORE_POR_RESET2_MASK (0x4U) |
| #define SRC_A53RCR0_A53_CORE_POR_RESET2_SHIFT (2U) |
| /*! A53_CORE_POR_RESET2 |
| * 0b0..do not assert core2 reset |
| * 0b1..assert core2 reset |
| */ |
| #define SRC_A53RCR0_A53_CORE_POR_RESET2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET2_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET2_MASK) |
| #define SRC_A53RCR0_A53_CORE_POR_RESET3_MASK (0x8U) |
| #define SRC_A53RCR0_A53_CORE_POR_RESET3_SHIFT (3U) |
| /*! A53_CORE_POR_RESET3 |
| * 0b0..do not assert core3 reset |
| * 0b1..assert core3 reset |
| */ |
| #define SRC_A53RCR0_A53_CORE_POR_RESET3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET3_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET3_MASK) |
| #define SRC_A53RCR0_A53_CORE_RESET0_MASK (0x10U) |
| #define SRC_A53RCR0_A53_CORE_RESET0_SHIFT (4U) |
| /*! A53_CORE_RESET0 |
| * 0b0..do not assert core0 reset |
| * 0b1..assert core0 reset |
| */ |
| #define SRC_A53RCR0_A53_CORE_RESET0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET0_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET0_MASK) |
| #define SRC_A53RCR0_A53_CORE_RESET1_MASK (0x20U) |
| #define SRC_A53RCR0_A53_CORE_RESET1_SHIFT (5U) |
| /*! A53_CORE_RESET1 |
| * 0b0..do not assert core1 reset |
| * 0b1..assert core1 reset |
| */ |
| #define SRC_A53RCR0_A53_CORE_RESET1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET1_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET1_MASK) |
| #define SRC_A53RCR0_A53_CORE_RESET2_MASK (0x40U) |
| #define SRC_A53RCR0_A53_CORE_RESET2_SHIFT (6U) |
| /*! A53_CORE_RESET2 |
| * 0b0..do not assert core2 reset |
| * 0b1..assert core2 reset |
| */ |
| #define SRC_A53RCR0_A53_CORE_RESET2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET2_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET2_MASK) |
| #define SRC_A53RCR0_A53_CORE_RESET3_MASK (0x80U) |
| #define SRC_A53RCR0_A53_CORE_RESET3_SHIFT (7U) |
| /*! A53_CORE_RESET3 |
| * 0b0..do not assert core3 reset |
| * 0b1..assert core3 reset |
| */ |
| #define SRC_A53RCR0_A53_CORE_RESET3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET3_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET3_MASK) |
| #define SRC_A53RCR0_A53_DBG_RESET0_MASK (0x100U) |
| #define SRC_A53RCR0_A53_DBG_RESET0_SHIFT (8U) |
| /*! A53_DBG_RESET0 |
| * 0b0..do not assert core0 debug reset |
| * 0b1..assert core0 debug reset |
| */ |
| #define SRC_A53RCR0_A53_DBG_RESET0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET0_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET0_MASK) |
| #define SRC_A53RCR0_A53_DBG_RESET1_MASK (0x200U) |
| #define SRC_A53RCR0_A53_DBG_RESET1_SHIFT (9U) |
| /*! A53_DBG_RESET1 |
| * 0b0..do not assert core1 debug reset |
| * 0b1..assert core1 debug reset |
| */ |
| #define SRC_A53RCR0_A53_DBG_RESET1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET1_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET1_MASK) |
| #define SRC_A53RCR0_A53_DBG_RESET2_MASK (0x400U) |
| #define SRC_A53RCR0_A53_DBG_RESET2_SHIFT (10U) |
| /*! A53_DBG_RESET2 |
| * 0b0..do not assert core2 debug reset |
| * 0b1..assert core2 debug reset |
| */ |
| #define SRC_A53RCR0_A53_DBG_RESET2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET2_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET2_MASK) |
| #define SRC_A53RCR0_A53_DBG_RESET3_MASK (0x800U) |
| #define SRC_A53RCR0_A53_DBG_RESET3_SHIFT (11U) |
| /*! A53_DBG_RESET3 |
| * 0b0..do not assert core3 debug reset |
| * 0b1..assert core3 debug reset |
| */ |
| #define SRC_A53RCR0_A53_DBG_RESET3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET3_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET3_MASK) |
| #define SRC_A53RCR0_A53_ETM_RESET0_MASK (0x1000U) |
| #define SRC_A53RCR0_A53_ETM_RESET0_SHIFT (12U) |
| /*! A53_ETM_RESET0 |
| * 0b0..do not assert core0 ETM reset |
| * 0b1..assert core0 ETM reset |
| */ |
| #define SRC_A53RCR0_A53_ETM_RESET0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET0_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET0_MASK) |
| #define SRC_A53RCR0_A53_ETM_RESET1_MASK (0x2000U) |
| #define SRC_A53RCR0_A53_ETM_RESET1_SHIFT (13U) |
| /*! A53_ETM_RESET1 |
| * 0b0..do not assert core1 ETM reset |
| * 0b1..assert core1 ETM reset |
| */ |
| #define SRC_A53RCR0_A53_ETM_RESET1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET1_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET1_MASK) |
| #define SRC_A53RCR0_A53_ETM_RESET2_MASK (0x4000U) |
| #define SRC_A53RCR0_A53_ETM_RESET2_SHIFT (14U) |
| /*! A53_ETM_RESET2 |
| * 0b0..do not assert core2 ETM reset |
| * 0b1..assert core2 ETM reset |
| */ |
| #define SRC_A53RCR0_A53_ETM_RESET2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET2_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET2_MASK) |
| #define SRC_A53RCR0_A53_ETM_RESET3_MASK (0x8000U) |
| #define SRC_A53RCR0_A53_ETM_RESET3_SHIFT (15U) |
| /*! A53_ETM_RESET3 |
| * 0b0..do not assert core3 ETM reset |
| * 0b1..assert core3 ETM reset |
| */ |
| #define SRC_A53RCR0_A53_ETM_RESET3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET3_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET3_MASK) |
| #define SRC_A53RCR0_MASK_WDOG1_RST_MASK (0xF0000U) |
| #define SRC_A53RCR0_MASK_WDOG1_RST_SHIFT (16U) |
| /*! MASK_WDOG1_RST |
| * 0b0101..wdog1_rst_b is masked |
| * 0b1010..wdog1_rst_b is not masked |
| */ |
| #define SRC_A53RCR0_MASK_WDOG1_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_MASK_WDOG1_RST_SHIFT)) & SRC_A53RCR0_MASK_WDOG1_RST_MASK) |
| #define SRC_A53RCR0_A53_SOC_DBG_RESET_MASK (0x100000U) |
| #define SRC_A53RCR0_A53_SOC_DBG_RESET_SHIFT (20U) |
| /*! A53_SOC_DBG_RESET |
| * 0b0..do not assert system level debug reset |
| * 0b1..assert system level debug reset |
| */ |
| #define SRC_A53RCR0_A53_SOC_DBG_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_SOC_DBG_RESET_SHIFT)) & SRC_A53RCR0_A53_SOC_DBG_RESET_MASK) |
| #define SRC_A53RCR0_A53_L2RESET_MASK (0x200000U) |
| #define SRC_A53RCR0_A53_L2RESET_SHIFT (21U) |
| /*! A53_L2RESET |
| * 0b0..do not assert SCU reset |
| * 0b1..assert SCU reset |
| */ |
| #define SRC_A53RCR0_A53_L2RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_L2RESET_SHIFT)) & SRC_A53RCR0_A53_L2RESET_MASK) |
| #define SRC_A53RCR0_DOMAIN0_MASK (0x1000000U) |
| #define SRC_A53RCR0_DOMAIN0_SHIFT (24U) |
| /*! DOMAIN0 |
| * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain0. The master from domain3 can write to this register |
| */ |
| #define SRC_A53RCR0_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN0_SHIFT)) & SRC_A53RCR0_DOMAIN0_MASK) |
| #define SRC_A53RCR0_DOMAIN1_MASK (0x2000000U) |
| #define SRC_A53RCR0_DOMAIN1_SHIFT (25U) |
| /*! DOMAIN1 |
| * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain1. The master from domain3 can write to this register |
| */ |
| #define SRC_A53RCR0_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN1_SHIFT)) & SRC_A53RCR0_DOMAIN1_MASK) |
| #define SRC_A53RCR0_DOMAIN2_MASK (0x4000000U) |
| #define SRC_A53RCR0_DOMAIN2_SHIFT (26U) |
| /*! DOMAIN2 |
| * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain2. The master from domain3 can write to this register |
| */ |
| #define SRC_A53RCR0_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN2_SHIFT)) & SRC_A53RCR0_DOMAIN2_MASK) |
| #define SRC_A53RCR0_DOMAIN3_MASK (0x8000000U) |
| #define SRC_A53RCR0_DOMAIN3_SHIFT (27U) |
| /*! DOMAIN3 |
| * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain3. The master from domain3 can write to this register |
| */ |
| #define SRC_A53RCR0_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN3_SHIFT)) & SRC_A53RCR0_DOMAIN3_MASK) |
| #define SRC_A53RCR0_LOCK_MASK (0x40000000U) |
| #define SRC_A53RCR0_LOCK_SHIFT (30U) |
| /*! LOCK |
| * 0b0..[31] and [27:24] bits can be modified |
| * 0b1..[31] and [27:24] bits cannot be modified |
| */ |
| #define SRC_A53RCR0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_LOCK_SHIFT)) & SRC_A53RCR0_LOCK_MASK) |
| #define SRC_A53RCR0_DOM_EN_MASK (0x80000000U) |
| #define SRC_A53RCR0_DOM_EN_SHIFT (31U) |
| /*! DOM_EN |
| * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters |
| * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. |
| */ |
| #define SRC_A53RCR0_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOM_EN_SHIFT)) & SRC_A53RCR0_DOM_EN_MASK) |
| /*! @} */ |
| |
| /*! @name A53RCR1 - A53 Reset Control Register */ |
| /*! @{ */ |
| #define SRC_A53RCR1_A53_CORE0_ENABLE_MASK (0x1U) |
| #define SRC_A53RCR1_A53_CORE0_ENABLE_SHIFT (0U) |
| #define SRC_A53RCR1_A53_CORE0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE0_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE0_ENABLE_MASK) |
| #define SRC_A53RCR1_A53_CORE1_ENABLE_MASK (0x2U) |
| #define SRC_A53RCR1_A53_CORE1_ENABLE_SHIFT (1U) |
| /*! A53_CORE1_ENABLE |
| * 0b0..core1 is disabled |
| * 0b1..core1 is enabled |
| */ |
| #define SRC_A53RCR1_A53_CORE1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE1_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE1_ENABLE_MASK) |
| #define SRC_A53RCR1_A53_CORE2_ENABLE_MASK (0x4U) |
| #define SRC_A53RCR1_A53_CORE2_ENABLE_SHIFT (2U) |
| /*! A53_CORE2_ENABLE |
| * 0b0..core2 is disabled |
| * 0b1..core2 is enabled |
| */ |
| #define SRC_A53RCR1_A53_CORE2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE2_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE2_ENABLE_MASK) |
| #define SRC_A53RCR1_A53_CORE3_ENABLE_MASK (0x8U) |
| #define SRC_A53RCR1_A53_CORE3_ENABLE_SHIFT (3U) |
| /*! A53_CORE3_ENABLE |
| * 0b0..core3 is disabled |
| * 0b1..core3 is enabled |
| */ |
| #define SRC_A53RCR1_A53_CORE3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE3_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE3_ENABLE_MASK) |
| #define SRC_A53RCR1_A53_RST_SLOW_MASK (0x70U) |
| #define SRC_A53RCR1_A53_RST_SLOW_SHIFT (4U) |
| #define SRC_A53RCR1_A53_RST_SLOW(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_RST_SLOW_SHIFT)) & SRC_A53RCR1_A53_RST_SLOW_MASK) |
| #define SRC_A53RCR1_DOMAIN0_MASK (0x1000000U) |
| #define SRC_A53RCR1_DOMAIN0_SHIFT (24U) |
| /*! DOMAIN0 |
| * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain0. The master from domain3 can write to this register |
| */ |
| #define SRC_A53RCR1_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN0_SHIFT)) & SRC_A53RCR1_DOMAIN0_MASK) |
| #define SRC_A53RCR1_DOMAIN1_MASK (0x2000000U) |
| #define SRC_A53RCR1_DOMAIN1_SHIFT (25U) |
| /*! DOMAIN1 |
| * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain1. The master from domain3 can write to this register |
| */ |
| #define SRC_A53RCR1_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN1_SHIFT)) & SRC_A53RCR1_DOMAIN1_MASK) |
| #define SRC_A53RCR1_DOMAIN2_MASK (0x4000000U) |
| #define SRC_A53RCR1_DOMAIN2_SHIFT (26U) |
| /*! DOMAIN2 |
| * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain2. The master from domain3 can write to this register |
| */ |
| #define SRC_A53RCR1_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN2_SHIFT)) & SRC_A53RCR1_DOMAIN2_MASK) |
| #define SRC_A53RCR1_DOMAIN3_MASK (0x8000000U) |
| #define SRC_A53RCR1_DOMAIN3_SHIFT (27U) |
| /*! DOMAIN3 |
| * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain3. The master from domain3 can write to this register |
| */ |
| #define SRC_A53RCR1_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN3_SHIFT)) & SRC_A53RCR1_DOMAIN3_MASK) |
| #define SRC_A53RCR1_LOCK_MASK (0x40000000U) |
| #define SRC_A53RCR1_LOCK_SHIFT (30U) |
| /*! LOCK |
| * 0b0..[31] and [27:24] bits can be modified |
| * 0b1..[31] and [27:24] bits cannot be modified |
| */ |
| #define SRC_A53RCR1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_LOCK_SHIFT)) & SRC_A53RCR1_LOCK_MASK) |
| #define SRC_A53RCR1_DOM_EN_MASK (0x80000000U) |
| #define SRC_A53RCR1_DOM_EN_SHIFT (31U) |
| /*! DOM_EN |
| * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters |
| * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. |
| */ |
| #define SRC_A53RCR1_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOM_EN_SHIFT)) & SRC_A53RCR1_DOM_EN_MASK) |
| /*! @} */ |
| |
| /*! @name M4RCR - M4 Reset Control Register */ |
| /*! @{ */ |
| #define SRC_M4RCR_SW_M4C_NON_SCLR_RST_MASK (0x1U) |
| #define SRC_M4RCR_SW_M4C_NON_SCLR_RST_SHIFT (0U) |
| /*! SW_M4C_NON_SCLR_RST |
| * 0b0..do not assert M4 core reset |
| * 0b1..assert M4 core reset |
| */ |
| #define SRC_M4RCR_SW_M4C_NON_SCLR_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_SW_M4C_NON_SCLR_RST_SHIFT)) & SRC_M4RCR_SW_M4C_NON_SCLR_RST_MASK) |
| #define SRC_M4RCR_SW_M4C_RST_MASK (0x2U) |
| #define SRC_M4RCR_SW_M4C_RST_SHIFT (1U) |
| /*! SW_M4C_RST |
| * 0b0..do not assert M4 core reset |
| * 0b1..assert M4 core reset |
| */ |
| #define SRC_M4RCR_SW_M4C_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_SW_M4C_RST_SHIFT)) & SRC_M4RCR_SW_M4C_RST_MASK) |
| #define SRC_M4RCR_SW_M4P_RST_MASK (0x4U) |
| #define SRC_M4RCR_SW_M4P_RST_SHIFT (2U) |
| /*! SW_M4P_RST |
| * 0b0..do not assert M4 platform reset |
| * 0b1..assert M4 platform reset |
| */ |
| #define SRC_M4RCR_SW_M4P_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_SW_M4P_RST_SHIFT)) & SRC_M4RCR_SW_M4P_RST_MASK) |
| #define SRC_M4RCR_ENABLE_M4_MASK (0x8U) |
| #define SRC_M4RCR_ENABLE_M4_SHIFT (3U) |
| /*! ENABLE_M4 |
| * 0b0..M4 is disabled |
| * 0b1..M4 is enabled |
| */ |
| #define SRC_M4RCR_ENABLE_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_ENABLE_M4_SHIFT)) & SRC_M4RCR_ENABLE_M4_MASK) |
| #define SRC_M4RCR_MASK_WDOG3_RST_MASK (0xF0U) |
| #define SRC_M4RCR_MASK_WDOG3_RST_SHIFT (4U) |
| /*! MASK_WDOG3_RST |
| * 0b0101..wdog3_rst_b is masked |
| * 0b1010..wdog3_rst_b is not masked |
| */ |
| #define SRC_M4RCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_MASK_WDOG3_RST_SHIFT)) & SRC_M4RCR_MASK_WDOG3_RST_MASK) |
| #define SRC_M4RCR_WDOG3_RST_OPTION_M4_MASK (0x100U) |
| #define SRC_M4RCR_WDOG3_RST_OPTION_M4_SHIFT (8U) |
| /*! WDOG3_RST_OPTION_M4 |
| * 0b0..wdgo3_rst_b Reset M4 core only |
| * 0b1..Reset both M4 core and platform |
| */ |
| #define SRC_M4RCR_WDOG3_RST_OPTION_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_WDOG3_RST_OPTION_M4_SHIFT)) & SRC_M4RCR_WDOG3_RST_OPTION_M4_MASK) |
| #define SRC_M4RCR_WDOG3_RST_OPTION_MASK (0x200U) |
| #define SRC_M4RCR_WDOG3_RST_OPTION_SHIFT (9U) |
| /*! WDOG3_RST_OPTION |
| * 0b0..Wdog3_rst_b asserts M4 reset |
| * 0b1..Wdog3_rst_b asserts global reset |
| */ |
| #define SRC_M4RCR_WDOG3_RST_OPTION(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_WDOG3_RST_OPTION_SHIFT)) & SRC_M4RCR_WDOG3_RST_OPTION_MASK) |
| #define SRC_M4RCR_DOMAIN0_MASK (0x1000000U) |
| #define SRC_M4RCR_DOMAIN0_SHIFT (24U) |
| /*! DOMAIN0 |
| * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain0. The master from domain3 can write to this register |
| */ |
| #define SRC_M4RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_DOMAIN0_SHIFT)) & SRC_M4RCR_DOMAIN0_MASK) |
| #define SRC_M4RCR_DOMAIN1_MASK (0x2000000U) |
| #define SRC_M4RCR_DOMAIN1_SHIFT (25U) |
| /*! DOMAIN1 |
| * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain1. The master from domain3 can write to this register |
| */ |
| #define SRC_M4RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_DOMAIN1_SHIFT)) & SRC_M4RCR_DOMAIN1_MASK) |
| #define SRC_M4RCR_DOMAIN2_MASK (0x4000000U) |
| #define SRC_M4RCR_DOMAIN2_SHIFT (26U) |
| /*! DOMAIN2 |
| * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain2. The master from domain3 can write to this register |
| */ |
| #define SRC_M4RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_DOMAIN2_SHIFT)) & SRC_M4RCR_DOMAIN2_MASK) |
| #define SRC_M4RCR_DOMAIN3_MASK (0x8000000U) |
| #define SRC_M4RCR_DOMAIN3_SHIFT (27U) |
| /*! DOMAIN3 |
| * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain3. The master from domain3 can write to this register |
| */ |
| #define SRC_M4RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_DOMAIN3_SHIFT)) & SRC_M4RCR_DOMAIN3_MASK) |
| #define SRC_M4RCR_LOCK_MASK (0x40000000U) |
| #define SRC_M4RCR_LOCK_SHIFT (30U) |
| /*! LOCK |
| * 0b0..[31] and [27:24] bits can be modified |
| * 0b1..[31] and [27:24] bits cannot be modified |
| */ |
| #define SRC_M4RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_LOCK_SHIFT)) & SRC_M4RCR_LOCK_MASK) |
| #define SRC_M4RCR_DOM_EN_MASK (0x80000000U) |
| #define SRC_M4RCR_DOM_EN_SHIFT (31U) |
| /*! DOM_EN |
| * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters |
| * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. |
| */ |
| #define SRC_M4RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_M4RCR_DOM_EN_SHIFT)) & SRC_M4RCR_DOM_EN_MASK) |
| /*! @} */ |
| |
| /*! @name USBOPHY1_RCR - USB OTG PHY1 Reset Control Register */ |
| /*! @{ */ |
| #define SRC_USBOPHY1_RCR_OTG1_PHY_RESET_MASK (0x1U) |
| #define SRC_USBOPHY1_RCR_OTG1_PHY_RESET_SHIFT (0U) |
| /*! OTG1_PHY_RESET |
| * 0b0..Don't reset USB OTG1 PHY |
| * 0b1..Reset USB OTG1 PHY |
| */ |
| #define SRC_USBOPHY1_RCR_OTG1_PHY_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_OTG1_PHY_RESET_SHIFT)) & SRC_USBOPHY1_RCR_OTG1_PHY_RESET_MASK) |
| #define SRC_USBOPHY1_RCR_DOMAIN0_MASK (0x1000000U) |
| #define SRC_USBOPHY1_RCR_DOMAIN0_SHIFT (24U) |
| /*! DOMAIN0 |
| * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain0. The master from domain3 can write to this register |
| */ |
| #define SRC_USBOPHY1_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOMAIN0_SHIFT)) & SRC_USBOPHY1_RCR_DOMAIN0_MASK) |
| #define SRC_USBOPHY1_RCR_DOMAIN1_MASK (0x2000000U) |
| #define SRC_USBOPHY1_RCR_DOMAIN1_SHIFT (25U) |
| /*! DOMAIN1 |
| * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain1. The master from domain3 can write to this register |
| */ |
| #define SRC_USBOPHY1_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOMAIN1_SHIFT)) & SRC_USBOPHY1_RCR_DOMAIN1_MASK) |
| #define SRC_USBOPHY1_RCR_DOMAIN2_MASK (0x4000000U) |
| #define SRC_USBOPHY1_RCR_DOMAIN2_SHIFT (26U) |
| /*! DOMAIN2 |
| * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain2. The master from domain3 can write to this register |
| */ |
| #define SRC_USBOPHY1_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOMAIN2_SHIFT)) & SRC_USBOPHY1_RCR_DOMAIN2_MASK) |
| #define SRC_USBOPHY1_RCR_DOMAIN3_MASK (0x8000000U) |
| #define SRC_USBOPHY1_RCR_DOMAIN3_SHIFT (27U) |
| /*! DOMAIN3 |
| * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain3. The master from domain3 can write to this register |
| */ |
| #define SRC_USBOPHY1_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOMAIN3_SHIFT)) & SRC_USBOPHY1_RCR_DOMAIN3_MASK) |
| #define SRC_USBOPHY1_RCR_LOCK_MASK (0x40000000U) |
| #define SRC_USBOPHY1_RCR_LOCK_SHIFT (30U) |
| /*! LOCK |
| * 0b0..[31] and [27:24] bits can be modified |
| * 0b1..[31] and [27:24] bits cannot be modified |
| */ |
| #define SRC_USBOPHY1_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_LOCK_SHIFT)) & SRC_USBOPHY1_RCR_LOCK_MASK) |
| #define SRC_USBOPHY1_RCR_DOM_EN_MASK (0x80000000U) |
| #define SRC_USBOPHY1_RCR_DOM_EN_SHIFT (31U) |
| /*! DOM_EN |
| * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters |
| * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. |
| */ |
| #define SRC_USBOPHY1_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOM_EN_SHIFT)) & SRC_USBOPHY1_RCR_DOM_EN_MASK) |
| /*! @} */ |
| |
| /*! @name USBOPHY2_RCR - USB OTG PHY2 Reset Control Register */ |
| /*! @{ */ |
| #define SRC_USBOPHY2_RCR_OTG2_PHY_RESET_MASK (0x1U) |
| #define SRC_USBOPHY2_RCR_OTG2_PHY_RESET_SHIFT (0U) |
| /*! OTG2_PHY_RESET |
| * 0b0..Don't reset USB OTG2 PHY |
| * 0b1..Reset USB OTG2 PHY |
| */ |
| #define SRC_USBOPHY2_RCR_OTG2_PHY_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY2_RCR_OTG2_PHY_RESET_SHIFT)) & SRC_USBOPHY2_RCR_OTG2_PHY_RESET_MASK) |
| #define SRC_USBOPHY2_RCR_DOMAIN0_MASK (0x1000000U) |
| #define SRC_USBOPHY2_RCR_DOMAIN0_SHIFT (24U) |
| /*! DOMAIN0 |
| * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain0. The master from domain3 can write to this register |
| */ |
| #define SRC_USBOPHY2_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY2_RCR_DOMAIN0_SHIFT)) & SRC_USBOPHY2_RCR_DOMAIN0_MASK) |
| #define SRC_USBOPHY2_RCR_DOMAIN1_MASK (0x2000000U) |
| #define SRC_USBOPHY2_RCR_DOMAIN1_SHIFT (25U) |
| /*! DOMAIN1 |
| * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain1. The master from domain3 can write to this register |
| */ |
| #define SRC_USBOPHY2_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY2_RCR_DOMAIN1_SHIFT)) & SRC_USBOPHY2_RCR_DOMAIN1_MASK) |
| #define SRC_USBOPHY2_RCR_DOMAIN2_MASK (0x4000000U) |
| #define SRC_USBOPHY2_RCR_DOMAIN2_SHIFT (26U) |
| /*! DOMAIN2 |
| * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain2. The master from domain3 can write to this register |
| */ |
| #define SRC_USBOPHY2_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY2_RCR_DOMAIN2_SHIFT)) & SRC_USBOPHY2_RCR_DOMAIN2_MASK) |
| #define SRC_USBOPHY2_RCR_DOMAIN3_MASK (0x8000000U) |
| #define SRC_USBOPHY2_RCR_DOMAIN3_SHIFT (27U) |
| /*! DOMAIN3 |
| * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain3. The master from domain3 can write to this register |
| */ |
| #define SRC_USBOPHY2_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY2_RCR_DOMAIN3_SHIFT)) & SRC_USBOPHY2_RCR_DOMAIN3_MASK) |
| #define SRC_USBOPHY2_RCR_LOCK_MASK (0x40000000U) |
| #define SRC_USBOPHY2_RCR_LOCK_SHIFT (30U) |
| /*! LOCK |
| * 0b0..[31] and [27:24] bits can be modified |
| * 0b1..[31] and [27:24] bits cannot be modified |
| */ |
| #define SRC_USBOPHY2_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY2_RCR_LOCK_SHIFT)) & SRC_USBOPHY2_RCR_LOCK_MASK) |
| #define SRC_USBOPHY2_RCR_DOM_EN_MASK (0x80000000U) |
| #define SRC_USBOPHY2_RCR_DOM_EN_SHIFT (31U) |
| /*! DOM_EN |
| * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters |
| * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. |
| */ |
| #define SRC_USBOPHY2_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY2_RCR_DOM_EN_SHIFT)) & SRC_USBOPHY2_RCR_DOM_EN_MASK) |
| /*! @} */ |
| |
| /*! @name MIPIPHY_RCR - MIPI PHY Reset Control Register */ |
| /*! @{ */ |
| #define SRC_MIPIPHY_RCR_MIPI_DSI_RESET_BYTE_N_MASK (0x2U) |
| #define SRC_MIPIPHY_RCR_MIPI_DSI_RESET_BYTE_N_SHIFT (1U) |
| /*! MIPI_DSI_RESET_BYTE_N |
| * 0b0..Reset |
| * 0b1..Don't reset |
| */ |
| #define SRC_MIPIPHY_RCR_MIPI_DSI_RESET_BYTE_N(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_MIPI_DSI_RESET_BYTE_N_SHIFT)) & SRC_MIPIPHY_RCR_MIPI_DSI_RESET_BYTE_N_MASK) |
| #define SRC_MIPIPHY_RCR_MIPI_DSI_RESET_N_MASK (0x4U) |
| #define SRC_MIPIPHY_RCR_MIPI_DSI_RESET_N_SHIFT (2U) |
| /*! MIPI_DSI_RESET_N |
| * 0b0..Reset |
| * 0b1..Don't reset |
| */ |
| #define SRC_MIPIPHY_RCR_MIPI_DSI_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_MIPI_DSI_RESET_N_SHIFT)) & SRC_MIPIPHY_RCR_MIPI_DSI_RESET_N_MASK) |
| #define SRC_MIPIPHY_RCR_MIPI_DIS_DPI_RESET_N_MASK (0x8U) |
| #define SRC_MIPIPHY_RCR_MIPI_DIS_DPI_RESET_N_SHIFT (3U) |
| /*! MIPI_DIS_DPI_RESET_N |
| * 0b0..Reset |
| * 0b1..Don't reset |
| */ |
| #define SRC_MIPIPHY_RCR_MIPI_DIS_DPI_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_MIPI_DIS_DPI_RESET_N_SHIFT)) & SRC_MIPIPHY_RCR_MIPI_DIS_DPI_RESET_N_MASK) |
| #define SRC_MIPIPHY_RCR_MIPI_DIS_ESC_RESET_N_MASK (0x10U) |
| #define SRC_MIPIPHY_RCR_MIPI_DIS_ESC_RESET_N_SHIFT (4U) |
| /*! MIPI_DIS_ESC_RESET_N |
| * 0b0..Reset |
| * 0b1..Don't reset |
| */ |
| #define SRC_MIPIPHY_RCR_MIPI_DIS_ESC_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_MIPI_DIS_ESC_RESET_N_SHIFT)) & SRC_MIPIPHY_RCR_MIPI_DIS_ESC_RESET_N_MASK) |
| #define SRC_MIPIPHY_RCR_MIPI_DIS_PCLK_RESET_N_MASK (0x20U) |
| #define SRC_MIPIPHY_RCR_MIPI_DIS_PCLK_RESET_N_SHIFT (5U) |
| /*! MIPI_DIS_PCLK_RESET_N |
| * 0b0..Reset |
| * 0b1..Don't reset |
| */ |
| #define SRC_MIPIPHY_RCR_MIPI_DIS_PCLK_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_MIPI_DIS_PCLK_RESET_N_SHIFT)) & SRC_MIPIPHY_RCR_MIPI_DIS_PCLK_RESET_N_MASK) |
| #define SRC_MIPIPHY_RCR_DOMAIN0_MASK (0x1000000U) |
| #define SRC_MIPIPHY_RCR_DOMAIN0_SHIFT (24U) |
| /*! DOMAIN0 |
| * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain0. The master from domain3 can write to this register |
| */ |
| #define SRC_MIPIPHY_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOMAIN0_SHIFT)) & SRC_MIPIPHY_RCR_DOMAIN0_MASK) |
| #define SRC_MIPIPHY_RCR_DOMAIN1_MASK (0x2000000U) |
| #define SRC_MIPIPHY_RCR_DOMAIN1_SHIFT (25U) |
| /*! DOMAIN1 |
| * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain1. The master from domain3 can write to this register |
| */ |
| #define SRC_MIPIPHY_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOMAIN1_SHIFT)) & SRC_MIPIPHY_RCR_DOMAIN1_MASK) |
| #define SRC_MIPIPHY_RCR_DOMAIN2_MASK (0x4000000U) |
| #define SRC_MIPIPHY_RCR_DOMAIN2_SHIFT (26U) |
| /*! DOMAIN2 |
| * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain2. The master from domain3 can write to this register |
| */ |
| #define SRC_MIPIPHY_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOMAIN2_SHIFT)) & SRC_MIPIPHY_RCR_DOMAIN2_MASK) |
| #define SRC_MIPIPHY_RCR_DOMAIN3_MASK (0x8000000U) |
| #define SRC_MIPIPHY_RCR_DOMAIN3_SHIFT (27U) |
| /*! DOMAIN3 |
| * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain3. The master from domain3 can write to this register |
| */ |
| #define SRC_MIPIPHY_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOMAIN3_SHIFT)) & SRC_MIPIPHY_RCR_DOMAIN3_MASK) |
| #define SRC_MIPIPHY_RCR_LOCK_MASK (0x40000000U) |
| #define SRC_MIPIPHY_RCR_LOCK_SHIFT (30U) |
| /*! LOCK |
| * 0b0..[31] and [27:24] bits can be modified |
| * 0b1..[31] and [27:24] bits cannot be modified |
| */ |
| #define SRC_MIPIPHY_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_LOCK_SHIFT)) & SRC_MIPIPHY_RCR_LOCK_MASK) |
| #define SRC_MIPIPHY_RCR_DOM_EN_MASK (0x80000000U) |
| #define SRC_MIPIPHY_RCR_DOM_EN_SHIFT (31U) |
| /*! DOM_EN |
| * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters |
| * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. |
| */ |
| #define SRC_MIPIPHY_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOM_EN_SHIFT)) & SRC_MIPIPHY_RCR_DOM_EN_MASK) |
| /*! @} */ |
| |
| /*! @name PCIEPHY_RCR - PCIE PHY Reset Control Register */ |
| /*! @{ */ |
| #define SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_N_MASK (0x1U) |
| #define SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_N_SHIFT (0U) |
| #define SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_N_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_N_MASK) |
| #define SRC_PCIEPHY_RCR_PCIEPHY_G_RST_MASK (0x2U) |
| #define SRC_PCIEPHY_RCR_PCIEPHY_G_RST_SHIFT (1U) |
| #define SRC_PCIEPHY_RCR_PCIEPHY_G_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIEPHY_G_RST_SHIFT)) & SRC_PCIEPHY_RCR_PCIEPHY_G_RST_MASK) |
| #define SRC_PCIEPHY_RCR_PCIEPHY_BTN_MASK (0x4U) |
| #define SRC_PCIEPHY_RCR_PCIEPHY_BTN_SHIFT (2U) |
| #define SRC_PCIEPHY_RCR_PCIEPHY_BTN(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIEPHY_BTN_SHIFT)) & SRC_PCIEPHY_RCR_PCIEPHY_BTN_MASK) |
| #define SRC_PCIEPHY_RCR_PCIEPHY_PERST_MASK (0x8U) |
| #define SRC_PCIEPHY_RCR_PCIEPHY_PERST_SHIFT (3U) |
| #define SRC_PCIEPHY_RCR_PCIEPHY_PERST(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIEPHY_PERST_SHIFT)) & SRC_PCIEPHY_RCR_PCIEPHY_PERST_MASK) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_MASK (0x10U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_SHIFT (4U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_MASK) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_MASK (0x20U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_SHIFT (5U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_MASK) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_MASK (0x40U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_SHIFT (6U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_MASK) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_MASK (0x80U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_SHIFT (7U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_MASK) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_MASK (0x100U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_SHIFT (8U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_MASK) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_MASK (0x200U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_SHIFT (9U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_MASK) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_MASK (0x400U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_SHIFT (10U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_MASK) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_MASK (0x800U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_SHIFT (11U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_MASK) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_MASK (0x1000U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_SHIFT (12U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_MASK) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_MASK (0x4000U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_SHIFT (14U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_MASK) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG_MASK (0x8000U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG_SHIFT (15U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG_MASK) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING_MASK (0x10000U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING_SHIFT (16U) |
| #define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING_MASK) |
| #define SRC_PCIEPHY_RCR_DOMAIN0_MASK (0x1000000U) |
| #define SRC_PCIEPHY_RCR_DOMAIN0_SHIFT (24U) |
| /*! DOMAIN0 |
| * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain0. The master from domain3 can write to this register |
| */ |
| #define SRC_PCIEPHY_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOMAIN0_SHIFT)) & SRC_PCIEPHY_RCR_DOMAIN0_MASK) |
| #define SRC_PCIEPHY_RCR_DOMAIN1_MASK (0x2000000U) |
| #define SRC_PCIEPHY_RCR_DOMAIN1_SHIFT (25U) |
| /*! DOMAIN1 |
| * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain1. The master from domain3 can write to this register |
| */ |
| #define SRC_PCIEPHY_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOMAIN1_SHIFT)) & SRC_PCIEPHY_RCR_DOMAIN1_MASK) |
| #define SRC_PCIEPHY_RCR_DOMAIN2_MASK (0x4000000U) |
| #define SRC_PCIEPHY_RCR_DOMAIN2_SHIFT (26U) |
| /*! DOMAIN2 |
| * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain2. The master from domain3 can write to this register |
| */ |
| #define SRC_PCIEPHY_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOMAIN2_SHIFT)) & SRC_PCIEPHY_RCR_DOMAIN2_MASK) |
| #define SRC_PCIEPHY_RCR_DOMAIN3_MASK (0x8000000U) |
| #define SRC_PCIEPHY_RCR_DOMAIN3_SHIFT (27U) |
| /*! DOMAIN3 |
| * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain3. The master from domain3 can write to this register |
| */ |
| #define SRC_PCIEPHY_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOMAIN3_SHIFT)) & SRC_PCIEPHY_RCR_DOMAIN3_MASK) |
| #define SRC_PCIEPHY_RCR_LOCK_MASK (0x40000000U) |
| #define SRC_PCIEPHY_RCR_LOCK_SHIFT (30U) |
| /*! LOCK |
| * 0b0..[31] and [27:24] bits can be modified |
| * 0b1..[31] and [27:24] bits cannot be modified |
| */ |
| #define SRC_PCIEPHY_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_LOCK_SHIFT)) & SRC_PCIEPHY_RCR_LOCK_MASK) |
| #define SRC_PCIEPHY_RCR_DOM_EN_MASK (0x80000000U) |
| #define SRC_PCIEPHY_RCR_DOM_EN_SHIFT (31U) |
| /*! DOM_EN |
| * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters |
| * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. |
| */ |
| #define SRC_PCIEPHY_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOM_EN_SHIFT)) & SRC_PCIEPHY_RCR_DOM_EN_MASK) |
| /*! @} */ |
| |
| /*! @name HDMI_RCR - HDMI Reset Control Register */ |
| /*! @{ */ |
| #define SRC_HDMI_RCR_HDMI_PHY_APB_RESET_MASK (0x1U) |
| #define SRC_HDMI_RCR_HDMI_PHY_APB_RESET_SHIFT (0U) |
| #define SRC_HDMI_RCR_HDMI_PHY_APB_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_HDMI_PHY_APB_RESET_SHIFT)) & SRC_HDMI_RCR_HDMI_PHY_APB_RESET_MASK) |
| #define SRC_HDMI_RCR_DOMAIN0_MASK (0x1000000U) |
| #define SRC_HDMI_RCR_DOMAIN0_SHIFT (24U) |
| /*! DOMAIN0 |
| * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain0. The master from domain3 can write to this register |
| */ |
| #define SRC_HDMI_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOMAIN0_SHIFT)) & SRC_HDMI_RCR_DOMAIN0_MASK) |
| #define SRC_HDMI_RCR_DOMAIN1_MASK (0x2000000U) |
| #define SRC_HDMI_RCR_DOMAIN1_SHIFT (25U) |
| /*! DOMAIN1 |
| * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain1. The master from domain3 can write to this register |
| */ |
| #define SRC_HDMI_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOMAIN1_SHIFT)) & SRC_HDMI_RCR_DOMAIN1_MASK) |
| #define SRC_HDMI_RCR_DOMAIN2_MASK (0x4000000U) |
| #define SRC_HDMI_RCR_DOMAIN2_SHIFT (26U) |
| /*! DOMAIN2 |
| * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain2. The master from domain3 can write to this register |
| */ |
| #define SRC_HDMI_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOMAIN2_SHIFT)) & SRC_HDMI_RCR_DOMAIN2_MASK) |
| #define SRC_HDMI_RCR_DOMAIN3_MASK (0x8000000U) |
| #define SRC_HDMI_RCR_DOMAIN3_SHIFT (27U) |
| /*! DOMAIN3 |
| * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain3. The master from domain3 can write to this register |
| */ |
| #define SRC_HDMI_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOMAIN3_SHIFT)) & SRC_HDMI_RCR_DOMAIN3_MASK) |
| #define SRC_HDMI_RCR_LOCK_MASK (0x40000000U) |
| #define SRC_HDMI_RCR_LOCK_SHIFT (30U) |
| /*! LOCK |
| * 0b0..[31] and [27:24] bits can be modified |
| * 0b1..[31] and [27:24] bits cannot be modified |
| */ |
| #define SRC_HDMI_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_LOCK_SHIFT)) & SRC_HDMI_RCR_LOCK_MASK) |
| #define SRC_HDMI_RCR_DOM_EN_MASK (0x80000000U) |
| #define SRC_HDMI_RCR_DOM_EN_SHIFT (31U) |
| /*! DOM_EN |
| * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters |
| * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. |
| */ |
| #define SRC_HDMI_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOM_EN_SHIFT)) & SRC_HDMI_RCR_DOM_EN_MASK) |
| /*! @} */ |
| |
| /*! @name DISP_RCR - DISP Reset Control Register */ |
| /*! @{ */ |
| #define SRC_DISP_RCR_DISP_RESET_MASK (0x1U) |
| #define SRC_DISP_RCR_DISP_RESET_SHIFT (0U) |
| /*! DISP_RESET |
| * 0b0..Don't reset dispmix |
| * 0b1..Reset dispmix |
| */ |
| #define SRC_DISP_RCR_DISP_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DISP_RESET_SHIFT)) & SRC_DISP_RCR_DISP_RESET_MASK) |
| #define SRC_DISP_RCR_DOMAIN0_MASK (0x1000000U) |
| #define SRC_DISP_RCR_DOMAIN0_SHIFT (24U) |
| /*! DOMAIN0 |
| * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain0. The master from domain3 can write to this register |
| */ |
| #define SRC_DISP_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOMAIN0_SHIFT)) & SRC_DISP_RCR_DOMAIN0_MASK) |
| #define SRC_DISP_RCR_DOMAIN1_MASK (0x2000000U) |
| #define SRC_DISP_RCR_DOMAIN1_SHIFT (25U) |
| /*! DOMAIN1 |
| * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain1. The master from domain3 can write to this register |
| */ |
| #define SRC_DISP_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOMAIN1_SHIFT)) & SRC_DISP_RCR_DOMAIN1_MASK) |
| #define SRC_DISP_RCR_DOMAIN2_MASK (0x4000000U) |
| #define SRC_DISP_RCR_DOMAIN2_SHIFT (26U) |
| /*! DOMAIN2 |
| * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain2. The master from domain3 can write to this register |
| */ |
| #define SRC_DISP_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOMAIN2_SHIFT)) & SRC_DISP_RCR_DOMAIN2_MASK) |
| #define SRC_DISP_RCR_DOMAIN3_MASK (0x8000000U) |
| #define SRC_DISP_RCR_DOMAIN3_SHIFT (27U) |
| /*! DOMAIN3 |
| * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain3. The master from domain3 can write to this register |
| */ |
| #define SRC_DISP_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOMAIN3_SHIFT)) & SRC_DISP_RCR_DOMAIN3_MASK) |
| #define SRC_DISP_RCR_LOCK_MASK (0x40000000U) |
| #define SRC_DISP_RCR_LOCK_SHIFT (30U) |
| /*! LOCK |
| * 0b0..[31] and [27:24] bits can be modified |
| * 0b1..[31] and [27:24] bits cannot be modified |
| */ |
| #define SRC_DISP_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_LOCK_SHIFT)) & SRC_DISP_RCR_LOCK_MASK) |
| #define SRC_DISP_RCR_DOM_EN_MASK (0x80000000U) |
| #define SRC_DISP_RCR_DOM_EN_SHIFT (31U) |
| /*! DOM_EN |
| * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters |
| * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. |
| */ |
| #define SRC_DISP_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOM_EN_SHIFT)) & SRC_DISP_RCR_DOM_EN_MASK) |
| /*! @} */ |
| |
| /*! @name GPU_RCR - GPU Reset Control Register */ |
| /*! @{ */ |
| #define SRC_GPU_RCR_GPU_RESET_MASK (0x1U) |
| #define SRC_GPU_RCR_GPU_RESET_SHIFT (0U) |
| #define SRC_GPU_RCR_GPU_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_GPU_RESET_SHIFT)) & SRC_GPU_RCR_GPU_RESET_MASK) |
| #define SRC_GPU_RCR_DOMAIN0_MASK (0x1000000U) |
| #define SRC_GPU_RCR_DOMAIN0_SHIFT (24U) |
| /*! DOMAIN0 |
| * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain0. The master from domain3 can write to this register |
| */ |
| #define SRC_GPU_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN0_SHIFT)) & SRC_GPU_RCR_DOMAIN0_MASK) |
| #define SRC_GPU_RCR_DOMAIN1_MASK (0x2000000U) |
| #define SRC_GPU_RCR_DOMAIN1_SHIFT (25U) |
| /*! DOMAIN1 |
| * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain1. The master from domain3 can write to this register |
| */ |
| #define SRC_GPU_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN1_SHIFT)) & SRC_GPU_RCR_DOMAIN1_MASK) |
| #define SRC_GPU_RCR_DOMAIN2_MASK (0x4000000U) |
| #define SRC_GPU_RCR_DOMAIN2_SHIFT (26U) |
| /*! DOMAIN2 |
| * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain2. The master from domain3 can write to this register |
| */ |
| #define SRC_GPU_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN2_SHIFT)) & SRC_GPU_RCR_DOMAIN2_MASK) |
| #define SRC_GPU_RCR_DOMAIN3_MASK (0x8000000U) |
| #define SRC_GPU_RCR_DOMAIN3_SHIFT (27U) |
| /*! DOMAIN3 |
| * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain3. The master from domain3 can write to this register |
| */ |
| #define SRC_GPU_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN3_SHIFT)) & SRC_GPU_RCR_DOMAIN3_MASK) |
| #define SRC_GPU_RCR_LOCK_MASK (0x40000000U) |
| #define SRC_GPU_RCR_LOCK_SHIFT (30U) |
| /*! LOCK |
| * 0b0..[31] and [27:24] bits can be modified |
| * 0b1..[31] and [27:24] bits cannot be modified |
| */ |
| #define SRC_GPU_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_LOCK_SHIFT)) & SRC_GPU_RCR_LOCK_MASK) |
| #define SRC_GPU_RCR_DOM_EN_MASK (0x80000000U) |
| #define SRC_GPU_RCR_DOM_EN_SHIFT (31U) |
| /*! DOM_EN |
| * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters |
| * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. |
| */ |
| #define SRC_GPU_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOM_EN_SHIFT)) & SRC_GPU_RCR_DOM_EN_MASK) |
| /*! @} */ |
| |
| /*! @name VPU_RCR - VPU Reset Control Register */ |
| /*! @{ */ |
| #define SRC_VPU_RCR_VPU_RESET_MASK (0x1U) |
| #define SRC_VPU_RCR_VPU_RESET_SHIFT (0U) |
| #define SRC_VPU_RCR_VPU_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_VPU_RESET_SHIFT)) & SRC_VPU_RCR_VPU_RESET_MASK) |
| #define SRC_VPU_RCR_DOMAIN0_MASK (0x1000000U) |
| #define SRC_VPU_RCR_DOMAIN0_SHIFT (24U) |
| /*! DOMAIN0 |
| * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain0. The master from domain3 can write to this register |
| */ |
| #define SRC_VPU_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOMAIN0_SHIFT)) & SRC_VPU_RCR_DOMAIN0_MASK) |
| #define SRC_VPU_RCR_DOMAIN1_MASK (0x2000000U) |
| #define SRC_VPU_RCR_DOMAIN1_SHIFT (25U) |
| /*! DOMAIN1 |
| * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain1. The master from domain3 can write to this register |
| */ |
| #define SRC_VPU_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOMAIN1_SHIFT)) & SRC_VPU_RCR_DOMAIN1_MASK) |
| #define SRC_VPU_RCR_DOMAIN2_MASK (0x4000000U) |
| #define SRC_VPU_RCR_DOMAIN2_SHIFT (26U) |
| /*! DOMAIN2 |
| * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain2. The master from domain3 can write to this register |
| */ |
| #define SRC_VPU_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOMAIN2_SHIFT)) & SRC_VPU_RCR_DOMAIN2_MASK) |
| #define SRC_VPU_RCR_DOMAIN3_MASK (0x8000000U) |
| #define SRC_VPU_RCR_DOMAIN3_SHIFT (27U) |
| /*! DOMAIN3 |
| * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain3. The master from domain3 can write to this register |
| */ |
| #define SRC_VPU_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOMAIN3_SHIFT)) & SRC_VPU_RCR_DOMAIN3_MASK) |
| #define SRC_VPU_RCR_LOCK_MASK (0x40000000U) |
| #define SRC_VPU_RCR_LOCK_SHIFT (30U) |
| /*! LOCK |
| * 0b0..[31] and [27:24] bits can be modified |
| * 0b1..[31] and [27:24] bits cannot be modified |
| */ |
| #define SRC_VPU_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_LOCK_SHIFT)) & SRC_VPU_RCR_LOCK_MASK) |
| #define SRC_VPU_RCR_DOM_EN_MASK (0x80000000U) |
| #define SRC_VPU_RCR_DOM_EN_SHIFT (31U) |
| /*! DOM_EN |
| * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters |
| * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. |
| */ |
| #define SRC_VPU_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOM_EN_SHIFT)) & SRC_VPU_RCR_DOM_EN_MASK) |
| /*! @} */ |
| |
| /*! @name PCIE2_RCR - PCIE2 Reset Control Register */ |
| /*! @{ */ |
| #define SRC_PCIE2_RCR_PCIE_PHY_POWER_ON_RESET_N_MASK (0x1U) |
| #define SRC_PCIE2_RCR_PCIE_PHY_POWER_ON_RESET_N_SHIFT (0U) |
| #define SRC_PCIE2_RCR_PCIE_PHY_POWER_ON_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_PHY_POWER_ON_RESET_N_SHIFT)) & SRC_PCIE2_RCR_PCIE_PHY_POWER_ON_RESET_N_MASK) |
| #define SRC_PCIE2_RCR_PCIE_G_RST_MASK (0x2U) |
| #define SRC_PCIE2_RCR_PCIE_G_RST_SHIFT (1U) |
| #define SRC_PCIE2_RCR_PCIE_G_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_G_RST_SHIFT)) & SRC_PCIE2_RCR_PCIE_G_RST_MASK) |
| #define SRC_PCIE2_RCR_PCIE_BTN_MASK (0x4U) |
| #define SRC_PCIE2_RCR_PCIE_BTN_SHIFT (2U) |
| #define SRC_PCIE2_RCR_PCIE_BTN(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_BTN_SHIFT)) & SRC_PCIE2_RCR_PCIE_BTN_MASK) |
| #define SRC_PCIE2_RCR_PCIE_PERST_MASK (0x8U) |
| #define SRC_PCIE2_RCR_PCIE_PERST_SHIFT (3U) |
| #define SRC_PCIE2_RCR_PCIE_PERST(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_PERST_SHIFT)) & SRC_PCIE2_RCR_PCIE_PERST_MASK) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_CLK_REQ_MASK (0x10U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_CLK_REQ_SHIFT (4U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_CLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_CLK_REQ_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_CLK_REQ_MASK) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_RST_MASK (0x20U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_RST_SHIFT (5U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_RST_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_RST_MASK) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_EN_MASK (0x40U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_EN_SHIFT (6U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_EN_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_EN_MASK) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_READY_MASK (0x80U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_READY_SHIFT (7U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_READY(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_READY_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_READY_MASK) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_ENTER_MASK (0x100U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_ENTER_SHIFT (8U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_ENTER(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_ENTER_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_ENTER_MASK) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_EXIT_MASK (0x200U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_EXIT_SHIFT (9U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_EXIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_EXIT_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_EXIT_MASK) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_PME_MASK (0x400U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_PME_SHIFT (10U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_PME(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_PME_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_PME_MASK) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_TURNOFF_MASK (0x800U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_TURNOFF_SHIFT (11U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APPS_TURNOFF(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APPS_TURNOFF_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APPS_TURNOFF_MASK) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_CFG_L1_AUX_MASK (0x1000U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_CFG_L1_AUX_SHIFT (12U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_CFG_L1_AUX(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_CFG_L1_AUX_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_CFG_L1_AUX_MASK) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_SYS_INT_MASK (0x4000U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_SYS_INT_SHIFT (14U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_SYS_INT(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_SYS_INT_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_SYS_INT_MASK) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APP_UNLOCK_MSG_MASK (0x8000U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APP_UNLOCK_MSG_SHIFT (15U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APP_UNLOCK_MSG(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APP_UNLOCK_MSG_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APP_UNLOCK_MSG_MASK) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APP_XFER_PENDING_MASK (0x10000U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APP_XFER_PENDING_SHIFT (16U) |
| #define SRC_PCIE2_RCR_PCIE_CTRL_APP_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_PCIE_CTRL_APP_XFER_PENDING_SHIFT)) & SRC_PCIE2_RCR_PCIE_CTRL_APP_XFER_PENDING_MASK) |
| #define SRC_PCIE2_RCR_DOMAIN0_MASK (0x1000000U) |
| #define SRC_PCIE2_RCR_DOMAIN0_SHIFT (24U) |
| /*! DOMAIN0 |
| * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain0. The master from domain3 can write to this register |
| */ |
| #define SRC_PCIE2_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_DOMAIN0_SHIFT)) & SRC_PCIE2_RCR_DOMAIN0_MASK) |
| #define SRC_PCIE2_RCR_DOMAIN1_MASK (0x2000000U) |
| #define SRC_PCIE2_RCR_DOMAIN1_SHIFT (25U) |
| /*! DOMAIN1 |
| * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain1. The master from domain3 can write to this register |
| */ |
| #define SRC_PCIE2_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_DOMAIN1_SHIFT)) & SRC_PCIE2_RCR_DOMAIN1_MASK) |
| #define SRC_PCIE2_RCR_DOMAIN2_MASK (0x4000000U) |
| #define SRC_PCIE2_RCR_DOMAIN2_SHIFT (26U) |
| /*! DOMAIN2 |
| * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain2. The master from domain3 can write to this register |
| */ |
| #define SRC_PCIE2_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_DOMAIN2_SHIFT)) & SRC_PCIE2_RCR_DOMAIN2_MASK) |
| #define SRC_PCIE2_RCR_DOMAIN3_MASK (0x8000000U) |
| #define SRC_PCIE2_RCR_DOMAIN3_SHIFT (27U) |
| /*! DOMAIN3 |
| * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain3. The master from domain3 can write to this register |
| */ |
| #define SRC_PCIE2_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_DOMAIN3_SHIFT)) & SRC_PCIE2_RCR_DOMAIN3_MASK) |
| #define SRC_PCIE2_RCR_LOCK_MASK (0x40000000U) |
| #define SRC_PCIE2_RCR_LOCK_SHIFT (30U) |
| /*! LOCK |
| * 0b0..[31] and [27:24] bits can be modified |
| * 0b1..[31] and [27:24] bits cannot be modified |
| */ |
| #define SRC_PCIE2_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_LOCK_SHIFT)) & SRC_PCIE2_RCR_LOCK_MASK) |
| #define SRC_PCIE2_RCR_DOM_EN_MASK (0x80000000U) |
| #define SRC_PCIE2_RCR_DOM_EN_SHIFT (31U) |
| /*! DOM_EN |
| * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters |
| * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. |
| */ |
| #define SRC_PCIE2_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIE2_RCR_DOM_EN_SHIFT)) & SRC_PCIE2_RCR_DOM_EN_MASK) |
| /*! @} */ |
| |
| /*! @name MIPIPHY1_RCR - MIPI CSI1 PHY Reset Control Register */ |
| /*! @{ */ |
| #define SRC_MIPIPHY1_RCR_MIPI_CSI1_CORE_RESET_MASK (0x1U) |
| #define SRC_MIPIPHY1_RCR_MIPI_CSI1_CORE_RESET_SHIFT (0U) |
| #define SRC_MIPIPHY1_RCR_MIPI_CSI1_CORE_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_MIPI_CSI1_CORE_RESET_SHIFT)) & SRC_MIPIPHY1_RCR_MIPI_CSI1_CORE_RESET_MASK) |
| #define SRC_MIPIPHY1_RCR_MIPI_CSI1_PHY_REF_RESET_MASK (0x2U) |
| #define SRC_MIPIPHY1_RCR_MIPI_CSI1_PHY_REF_RESET_SHIFT (1U) |
| #define SRC_MIPIPHY1_RCR_MIPI_CSI1_PHY_REF_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_MIPI_CSI1_PHY_REF_RESET_SHIFT)) & SRC_MIPIPHY1_RCR_MIPI_CSI1_PHY_REF_RESET_MASK) |
| #define SRC_MIPIPHY1_RCR_MIPI_CSI1_ESC_RESET_MASK (0x4U) |
| #define SRC_MIPIPHY1_RCR_MIPI_CSI1_ESC_RESET_SHIFT (2U) |
| #define SRC_MIPIPHY1_RCR_MIPI_CSI1_ESC_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_MIPI_CSI1_ESC_RESET_SHIFT)) & SRC_MIPIPHY1_RCR_MIPI_CSI1_ESC_RESET_MASK) |
| #define SRC_MIPIPHY1_RCR_DOMAIN0_MASK (0x1000000U) |
| #define SRC_MIPIPHY1_RCR_DOMAIN0_SHIFT (24U) |
| /*! DOMAIN0 |
| * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain0. The master from domain3 can write to this register |
| */ |
| #define SRC_MIPIPHY1_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOMAIN0_SHIFT)) & SRC_MIPIPHY1_RCR_DOMAIN0_MASK) |
| #define SRC_MIPIPHY1_RCR_DOMAIN1_MASK (0x2000000U) |
| #define SRC_MIPIPHY1_RCR_DOMAIN1_SHIFT (25U) |
| /*! DOMAIN1 |
| * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain1. The master from domain3 can write to this register |
| */ |
| #define SRC_MIPIPHY1_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOMAIN1_SHIFT)) & SRC_MIPIPHY1_RCR_DOMAIN1_MASK) |
| #define SRC_MIPIPHY1_RCR_DOMAIN2_MASK (0x4000000U) |
| #define SRC_MIPIPHY1_RCR_DOMAIN2_SHIFT (26U) |
| /*! DOMAIN2 |
| * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain2. The master from domain3 can write to this register |
| */ |
| #define SRC_MIPIPHY1_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOMAIN2_SHIFT)) & SRC_MIPIPHY1_RCR_DOMAIN2_MASK) |
| #define SRC_MIPIPHY1_RCR_DOMAIN3_MASK (0x8000000U) |
| #define SRC_MIPIPHY1_RCR_DOMAIN3_SHIFT (27U) |
| /*! DOMAIN3 |
| * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain3. The master from domain3 can write to this register |
| */ |
| #define SRC_MIPIPHY1_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOMAIN3_SHIFT)) & SRC_MIPIPHY1_RCR_DOMAIN3_MASK) |
| #define SRC_MIPIPHY1_RCR_LOCK_MASK (0x40000000U) |
| #define SRC_MIPIPHY1_RCR_LOCK_SHIFT (30U) |
| /*! LOCK |
| * 0b0..[31] and [27:24] bits can be modified |
| * 0b1..[31] and [27:24] bits cannot be modified |
| */ |
| #define SRC_MIPIPHY1_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_LOCK_SHIFT)) & SRC_MIPIPHY1_RCR_LOCK_MASK) |
| #define SRC_MIPIPHY1_RCR_DOM_EN_MASK (0x80000000U) |
| #define SRC_MIPIPHY1_RCR_DOM_EN_SHIFT (31U) |
| /*! DOM_EN |
| * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters |
| * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. |
| */ |
| #define SRC_MIPIPHY1_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOM_EN_SHIFT)) & SRC_MIPIPHY1_RCR_DOM_EN_MASK) |
| /*! @} */ |
| |
| /*! @name MIPIPHY2_RCR - MIPI CSI2 PHY Reset Control Register */ |
| /*! @{ */ |
| #define SRC_MIPIPHY2_RCR_MIPI_CSI2_CORE_RESET_MASK (0x1U) |
| #define SRC_MIPIPHY2_RCR_MIPI_CSI2_CORE_RESET_SHIFT (0U) |
| #define SRC_MIPIPHY2_RCR_MIPI_CSI2_CORE_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_MIPI_CSI2_CORE_RESET_SHIFT)) & SRC_MIPIPHY2_RCR_MIPI_CSI2_CORE_RESET_MASK) |
| #define SRC_MIPIPHY2_RCR_MIPI_CSI2_PHY_REF_RESET_MASK (0x2U) |
| #define SRC_MIPIPHY2_RCR_MIPI_CSI2_PHY_REF_RESET_SHIFT (1U) |
| #define SRC_MIPIPHY2_RCR_MIPI_CSI2_PHY_REF_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_MIPI_CSI2_PHY_REF_RESET_SHIFT)) & SRC_MIPIPHY2_RCR_MIPI_CSI2_PHY_REF_RESET_MASK) |
| #define SRC_MIPIPHY2_RCR_MIPI_CSI2_ESC_RESET_MASK (0x4U) |
| #define SRC_MIPIPHY2_RCR_MIPI_CSI2_ESC_RESET_SHIFT (2U) |
| #define SRC_MIPIPHY2_RCR_MIPI_CSI2_ESC_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_MIPI_CSI2_ESC_RESET_SHIFT)) & SRC_MIPIPHY2_RCR_MIPI_CSI2_ESC_RESET_MASK) |
| #define SRC_MIPIPHY2_RCR_DOMAIN0_MASK (0x1000000U) |
| #define SRC_MIPIPHY2_RCR_DOMAIN0_SHIFT (24U) |
| /*! DOMAIN0 |
| * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain0. The master from domain3 can write to this register |
| */ |
| #define SRC_MIPIPHY2_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOMAIN0_SHIFT)) & SRC_MIPIPHY2_RCR_DOMAIN0_MASK) |
| #define SRC_MIPIPHY2_RCR_DOMAIN1_MASK (0x2000000U) |
| #define SRC_MIPIPHY2_RCR_DOMAIN1_SHIFT (25U) |
| /*! DOMAIN1 |
| * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain1. The master from domain3 can write to this register |
| */ |
| #define SRC_MIPIPHY2_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOMAIN1_SHIFT)) & SRC_MIPIPHY2_RCR_DOMAIN1_MASK) |
| #define SRC_MIPIPHY2_RCR_DOMAIN2_MASK (0x4000000U) |
| #define SRC_MIPIPHY2_RCR_DOMAIN2_SHIFT (26U) |
| /*! DOMAIN2 |
| * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain2. The master from domain3 can write to this register |
| */ |
| #define SRC_MIPIPHY2_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOMAIN2_SHIFT)) & SRC_MIPIPHY2_RCR_DOMAIN2_MASK) |
| #define SRC_MIPIPHY2_RCR_DOMAIN3_MASK (0x8000000U) |
| #define SRC_MIPIPHY2_RCR_DOMAIN3_SHIFT (27U) |
| /*! DOMAIN3 |
| * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain3. The master from domain3 can write to this register |
| */ |
| #define SRC_MIPIPHY2_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOMAIN3_SHIFT)) & SRC_MIPIPHY2_RCR_DOMAIN3_MASK) |
| #define SRC_MIPIPHY2_RCR_LOCK_MASK (0x40000000U) |
| #define SRC_MIPIPHY2_RCR_LOCK_SHIFT (30U) |
| /*! LOCK |
| * 0b0..[31] and [27:24] bits can be modified |
| * 0b1..[31] and [27:24] bits cannot be modified |
| */ |
| #define SRC_MIPIPHY2_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_LOCK_SHIFT)) & SRC_MIPIPHY2_RCR_LOCK_MASK) |
| #define SRC_MIPIPHY2_RCR_DOM_EN_MASK (0x80000000U) |
| #define SRC_MIPIPHY2_RCR_DOM_EN_SHIFT (31U) |
| /*! DOM_EN |
| * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters |
| * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. |
| */ |
| #define SRC_MIPIPHY2_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOM_EN_SHIFT)) & SRC_MIPIPHY2_RCR_DOM_EN_MASK) |
| /*! @} */ |
| |
| /*! @name SBMR1 - SRC Boot Mode Register 1 */ |
| /*! @{ */ |
| #define SRC_SBMR1_BOOT_CFG_MASK (0xFFFFFFFFU) |
| #define SRC_SBMR1_BOOT_CFG_SHIFT (0U) |
| #define SRC_SBMR1_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG_SHIFT)) & SRC_SBMR1_BOOT_CFG_MASK) |
| /*! @} */ |
| |
| /*! @name SRSR - SRC Reset Status Register */ |
| /*! @{ */ |
| #define SRC_SRSR_CSU_RESET_B_MASK (0x4U) |
| #define SRC_SRSR_CSU_RESET_B_SHIFT (2U) |
| /*! csu_reset_b |
| * 0b0..Reset is not a result of the csu_reset_b event. |
| * 0b1..Reset is a result of the csu_reset_b event. |
| */ |
| #define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK) |
| #define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U) |
| #define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U) |
| /*! ipp_user_reset_b |
| * 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. |
| * 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event. |
| */ |
| #define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK) |
| #define SRC_SRSR_WDOG1_RST_B_MASK (0x10U) |
| #define SRC_SRSR_WDOG1_RST_B_SHIFT (4U) |
| /*! wdog1_rst_b |
| * 0b0..Reset is not a result of the watchdog1 time-out event. |
| * 0b1..Reset is a result of the watchdog1 time-out event. |
| */ |
| #define SRC_SRSR_WDOG1_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG1_RST_B_SHIFT)) & SRC_SRSR_WDOG1_RST_B_MASK) |
| #define SRC_SRSR_JTAG_RST_B_MASK (0x20U) |
| #define SRC_SRSR_JTAG_RST_B_SHIFT (5U) |
| /*! jtag_rst_b |
| * 0b0..Reset is not a result of HIGH-Z reset from JTAG. |
| * 0b1..Reset is a result of HIGH-Z reset from JTAG. |
| */ |
| #define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK) |
| #define SRC_SRSR_JTAG_SW_RST_MASK (0x40U) |
| #define SRC_SRSR_JTAG_SW_RST_SHIFT (6U) |
| /*! jtag_sw_rst |
| * 0b0..Reset is not a result of software reset from JTAG. |
| * 0b1..Reset is a result of software reset from JTAG. |
| */ |
| #define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK) |
| #define SRC_SRSR_WDOG3_RST_B_MASK (0x80U) |
| #define SRC_SRSR_WDOG3_RST_B_SHIFT (7U) |
| /*! wdog3_rst_b |
| * 0b0..Reset is not a result of the watchdog3 time-out event. |
| * 0b1..Reset is a result of the watchdog3 time-out event. |
| */ |
| #define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK) |
| #define SRC_SRSR_WDOG4_RST_B_MASK (0x100U) |
| #define SRC_SRSR_WDOG4_RST_B_SHIFT (8U) |
| /*! wdog4_rst_b |
| * 0b0..Reset is not a result of the watchdog4 time-out event. |
| * 0b1..Reset is a result of the watchdog4 time-out event. |
| */ |
| #define SRC_SRSR_WDOG4_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_SHIFT)) & SRC_SRSR_WDOG4_RST_B_MASK) |
| #define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x200U) |
| #define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (9U) |
| /*! tempsense_rst_b |
| * 0b0..Reset is not a result of software reset from Temperature Sensor. |
| * 0b1..Reset is a result of software reset from Temperature Sensor. |
| */ |
| #define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK) |
| /*! @} */ |
| |
| /*! @name SISR - SRC Interrupt Status Register */ |
| /*! @{ */ |
| #define SRC_SISR_HSICPHY_PASSED_RESET_MASK (0x2U) |
| #define SRC_SISR_HSICPHY_PASSED_RESET_SHIFT (1U) |
| /*! HSICPHY_PASSED_RESET |
| * 0b0..Interrupt generated not due to HSIC PHY passed reset |
| * 0b1..Interrupt generated due to HSIC PHY passed reset |
| */ |
| #define SRC_SISR_HSICPHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_HSICPHY_PASSED_RESET_SHIFT)) & SRC_SISR_HSICPHY_PASSED_RESET_MASK) |
| #define SRC_SISR_OTGPHY1_PASSED_RESET_MASK (0x4U) |
| #define SRC_SISR_OTGPHY1_PASSED_RESET_SHIFT (2U) |
| /*! OTGPHY1_PASSED_RESET |
| * 0b0..Interrupt generated not due to OTG PHY1 passed reset |
| * 0b1..Interrupt generated due to OTG PHY1 passed reset |
| */ |
| #define SRC_SISR_OTGPHY1_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_OTGPHY1_PASSED_RESET_SHIFT)) & SRC_SISR_OTGPHY1_PASSED_RESET_MASK) |
| #define SRC_SISR_OTGPHY2_PASSED_RESET_MASK (0x8U) |
| #define SRC_SISR_OTGPHY2_PASSED_RESET_SHIFT (3U) |
| /*! OTGPHY2_PASSED_RESET |
| * 0b0..Interrupt generated not due to OTG PHY2 passed reset |
| * 0b1..Interrupt generated due to OTG PHY2 passed reset |
| */ |
| #define SRC_SISR_OTGPHY2_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_OTGPHY2_PASSED_RESET_SHIFT)) & SRC_SISR_OTGPHY2_PASSED_RESET_MASK) |
| #define SRC_SISR_MIPIPHY_PASSED_RESET_MASK (0x10U) |
| #define SRC_SISR_MIPIPHY_PASSED_RESET_SHIFT (4U) |
| /*! MIPIPHY_PASSED_RESET |
| * 0b0..Interrupt generated not due to MIPI PHY passed reset |
| * 0b1..Interrupt generated due to MIPI PHY passed reset |
| */ |
| #define SRC_SISR_MIPIPHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_MIPIPHY_PASSED_RESET_SHIFT)) & SRC_SISR_MIPIPHY_PASSED_RESET_MASK) |
| #define SRC_SISR_PCIE1_PHY_PASSED_RESET_MASK (0x20U) |
| #define SRC_SISR_PCIE1_PHY_PASSED_RESET_SHIFT (5U) |
| /*! PCIE1_PHY_PASSED_RESET |
| * 0b0..Interrupt generated not due to PCIE1 PHY passed reset |
| * 0b1..Interrupt generated due to PCIE1 PHY passed reset |
| */ |
| #define SRC_SISR_PCIE1_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_PCIE1_PHY_PASSED_RESET_SHIFT)) & SRC_SISR_PCIE1_PHY_PASSED_RESET_MASK) |
| #define SRC_SISR_HDMI_PASSED_RESET_MASK (0x40U) |
| #define SRC_SISR_HDMI_PASSED_RESET_SHIFT (6U) |
| /*! HDMI_PASSED_RESET |
| * 0b0..Interrupt generated not due to HDMI passed reset |
| * 0b1..Interrupt generated due to HDMI passed reset |
| */ |
| #define SRC_SISR_HDMI_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_HDMI_PASSED_RESET_SHIFT)) & SRC_SISR_HDMI_PASSED_RESET_MASK) |
| #define SRC_SISR_DISPLAY_PASSED_RESET_MASK (0x80U) |
| #define SRC_SISR_DISPLAY_PASSED_RESET_SHIFT (7U) |
| /*! DISPLAY_PASSED_RESET |
| * 0b0..Interrupt generated not due to DISPLAY passed reset |
| * 0b1..Interrupt generated due to DISPLAY passed reset |
| */ |
| #define SRC_SISR_DISPLAY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_DISPLAY_PASSED_RESET_SHIFT)) & SRC_SISR_DISPLAY_PASSED_RESET_MASK) |
| #define SRC_SISR_M4C_PASSED_RESET_MASK (0x100U) |
| #define SRC_SISR_M4C_PASSED_RESET_SHIFT (8U) |
| /*! M4C_PASSED_RESET |
| * 0b0..interrupt generated not due to m4 core reset |
| * 0b1..interrupt generated due to m4 core reset |
| */ |
| #define SRC_SISR_M4C_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_M4C_PASSED_RESET_SHIFT)) & SRC_SISR_M4C_PASSED_RESET_MASK) |
| #define SRC_SISR_M4P_PASSED_RESET_MASK (0x200U) |
| #define SRC_SISR_M4P_PASSED_RESET_SHIFT (9U) |
| /*! M4P_PASSED_RESET |
| * 0b0..interrupt generated not due to m4 platform reset |
| * 0b1..interrupt generated due to m4 platform reset |
| */ |
| #define SRC_SISR_M4P_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_M4P_PASSED_RESET_SHIFT)) & SRC_SISR_M4P_PASSED_RESET_MASK) |
| #define SRC_SISR_GPU_PASSED_RESET_MASK (0x400U) |
| #define SRC_SISR_GPU_PASSED_RESET_SHIFT (10U) |
| /*! GPU_PASSED_RESET |
| * 0b0..interrupt generated not due to GPU reset |
| * 0b1..interrupt generated due to GPU reset |
| */ |
| #define SRC_SISR_GPU_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_GPU_PASSED_RESET_SHIFT)) & SRC_SISR_GPU_PASSED_RESET_MASK) |
| #define SRC_SISR_VPU_PASSED_RESET_MASK (0x800U) |
| #define SRC_SISR_VPU_PASSED_RESET_SHIFT (11U) |
| /*! VPU_PASSED_RESET |
| * 0b0..interrupt generated not due to VPU reset |
| * 0b1..interrupt generated due to VPU reset |
| */ |
| #define SRC_SISR_VPU_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_VPU_PASSED_RESET_SHIFT)) & SRC_SISR_VPU_PASSED_RESET_MASK) |
| #define SRC_SISR_PCIE2_PHY_PASSED_RESET_MASK (0x1000U) |
| #define SRC_SISR_PCIE2_PHY_PASSED_RESET_SHIFT (12U) |
| /*! PCIE2_PHY_PASSED_RESET |
| * 0b0..interrupt generated not due to PCIE2 PHY reset |
| * 0b1..interrupt generated due to PCIE2 PHY reset |
| */ |
| #define SRC_SISR_PCIE2_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_PCIE2_PHY_PASSED_RESET_SHIFT)) & SRC_SISR_PCIE2_PHY_PASSED_RESET_MASK) |
| #define SRC_SISR_MIPI_CSI1_PHY_PASSED_RESET_MASK (0x2000U) |
| #define SRC_SISR_MIPI_CSI1_PHY_PASSED_RESET_SHIFT (13U) |
| /*! MIPI_CSI1_PHY_PASSED_RESET |
| * 0b0..interrupt generated not due to MIPI CSI1 PHY reset |
| * 0b1..interrupt generated due to MIPI CSI1 PHY reset |
| */ |
| #define SRC_SISR_MIPI_CSI1_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_MIPI_CSI1_PHY_PASSED_RESET_SHIFT)) & SRC_SISR_MIPI_CSI1_PHY_PASSED_RESET_MASK) |
| #define SRC_SISR_MIPI_CSI2_PHY_PASSED_RESET_MASK (0x4000U) |
| #define SRC_SISR_MIPI_CSI2_PHY_PASSED_RESET_SHIFT (14U) |
| /*! MIPI_CSI2_PHY_PASSED_RESET |
| * 0b0..interrupt generated not due to MIPI CSI2 PHY reset |
| * 0b1..interrupt generated due to MIPI CSI2 PHY reset |
| */ |
| #define SRC_SISR_MIPI_CSI2_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_MIPI_CSI2_PHY_PASSED_RESET_SHIFT)) & SRC_SISR_MIPI_CSI2_PHY_PASSED_RESET_MASK) |
| /*! @} */ |
| |
| /*! @name SIMR - SRC Interrupt Mask Register */ |
| /*! @{ */ |
| #define SRC_SIMR_MASK_HSICPHY_PASSED_RESET_MASK (0x2U) |
| #define SRC_SIMR_MASK_HSICPHY_PASSED_RESET_SHIFT (1U) |
| /*! MASK_HSICPHY_PASSED_RESET |
| * 0b0..do not mask interrupt due to HSIC PHY passed reset - interrupt will be created |
| * 0b1..mask interrupt due to HSIC PHY passed reset |
| */ |
| #define SRC_SIMR_MASK_HSICPHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_HSICPHY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_HSICPHY_PASSED_RESET_MASK) |
| #define SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_MASK (0x4U) |
| #define SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_SHIFT (2U) |
| /*! MASK_OTGPHY1_PASSED_RESET |
| * 0b0..do not mask interrupt due to OTG PHY1 passed reset - interrupt will be created |
| * 0b1..mask interrupt due to OTG PHY1 passed reset |
| */ |
| #define SRC_SIMR_MASK_OTGPHY1_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_MASK) |
| #define SRC_SIMR_MASK_OTGPHY2_PASSED_RESET_MASK (0x8U) |
| #define SRC_SIMR_MASK_OTGPHY2_PASSED_RESET_SHIFT (3U) |
| /*! MASK_OTGPHY2_PASSED_RESET |
| * 0b0..do not mask interrupt due to OTG PHY2 passed reset - interrupt will be created |
| * 0b1..mask interrupt due to OTG PHY2 passed reset |
| */ |
| #define SRC_SIMR_MASK_OTGPHY2_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_OTGPHY2_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_OTGPHY2_PASSED_RESET_MASK) |
| #define SRC_SIMR_MASK_MIPIPHY_PASSED_RESET_MASK (0x10U) |
| #define SRC_SIMR_MASK_MIPIPHY_PASSED_RESET_SHIFT (4U) |
| /*! MASK_MIPIPHY_PASSED_RESET |
| * 0b0..do not mask interrupt due to MIPI PHY passed reset - interrupt will be created |
| * 0b1..mask interrupt due to MIPI PHY passed reset |
| */ |
| #define SRC_SIMR_MASK_MIPIPHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_MIPIPHY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_MIPIPHY_PASSED_RESET_MASK) |
| #define SRC_SIMR_MASK_PCIE1_PHY_PASSED_RESET_MASK (0x20U) |
| #define SRC_SIMR_MASK_PCIE1_PHY_PASSED_RESET_SHIFT (5U) |
| /*! MASK_PCIE1_PHY_PASSED_RESET |
| * 0b0..do not mask interrupt due to PCIE1 PHY passed reset - interrupt will be created |
| * 0b1..mask interrupt due to PCIE1 PHY passed reset |
| */ |
| #define SRC_SIMR_MASK_PCIE1_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_PCIE1_PHY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_PCIE1_PHY_PASSED_RESET_MASK) |
| #define SRC_SIMR_MASK_HDMI_PASSED_RESET_MASK (0x40U) |
| #define SRC_SIMR_MASK_HDMI_PASSED_RESET_SHIFT (6U) |
| /*! MASK_HDMI_PASSED_RESET |
| * 0b0..do not mask interrupt due to HDMI passed reset - interrupt will be created |
| * 0b1..mask interrupt due to HDMI passed reset |
| */ |
| #define SRC_SIMR_MASK_HDMI_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_HDMI_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_HDMI_PASSED_RESET_MASK) |
| #define SRC_SIMR_MASK_DISPLAY_PASSED_RESET_MASK (0x80U) |
| #define SRC_SIMR_MASK_DISPLAY_PASSED_RESET_SHIFT (7U) |
| /*! MASK_DISPLAY_PASSED_RESET |
| * 0b0..do not mask interrupt due to HDMI passed reset - interrupt will be created |
| * 0b1..mask interrupt due to HDMI passed reset |
| */ |
| #define SRC_SIMR_MASK_DISPLAY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_DISPLAY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_DISPLAY_PASSED_RESET_MASK) |
| #define SRC_SIMR_MASK_M4C_PASSED_RESET_MASK (0x100U) |
| #define SRC_SIMR_MASK_M4C_PASSED_RESET_SHIFT (8U) |
| /*! MASK_M4C_PASSED_RESET |
| * 0b0..do not mask interrupt due to m4 core passed reset - interrupt will be created |
| * 0b1..mask interrupt due to m4 core passed reset |
| */ |
| #define SRC_SIMR_MASK_M4C_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_M4C_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_M4C_PASSED_RESET_MASK) |
| #define SRC_SIMR_MASK_M4P_PASSED_RESET_MASK (0x200U) |
| #define SRC_SIMR_MASK_M4P_PASSED_RESET_SHIFT (9U) |
| /*! MASK_M4P_PASSED_RESET |
| * 0b0..do not mask interrupt due to m4 platform passed reset - interrupt will be created |
| * 0b1..mask interrupt due to m4platform passed reset |
| */ |
| #define SRC_SIMR_MASK_M4P_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_M4P_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_M4P_PASSED_RESET_MASK) |
| #define SRC_SIMR_MASK_GPU_PASSED_RESET_MASK (0x400U) |
| #define SRC_SIMR_MASK_GPU_PASSED_RESET_SHIFT (10U) |
| /*! MASK_GPU_PASSED_RESET |
| * 0b0..do not mask interrupt due to GPU passed reset - interrupt will be created |
| * 0b1..mask interrupt due to GPU passed reset |
| */ |
| #define SRC_SIMR_MASK_GPU_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_GPU_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_GPU_PASSED_RESET_MASK) |
| #define SRC_SIMR_MASK_VPU_PASSED_RESET_MASK (0x800U) |
| #define SRC_SIMR_MASK_VPU_PASSED_RESET_SHIFT (11U) |
| /*! MASK_VPU_PASSED_RESET |
| * 0b0..do not mask interrupt due to VPU passed reset - interrupt will be created |
| * 0b1..mask interrupt due to VPU passed reset |
| */ |
| #define SRC_SIMR_MASK_VPU_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_VPU_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_VPU_PASSED_RESET_MASK) |
| #define SRC_SIMR_MASK_PCIE2_PHY_PASSED_RESET_MASK (0x1000U) |
| #define SRC_SIMR_MASK_PCIE2_PHY_PASSED_RESET_SHIFT (12U) |
| /*! MASK_PCIE2_PHY_PASSED_RESET |
| * 0b0..do not mask interrupt due to PCIE2 PHY passed reset - interrupt will be created |
| * 0b1..mask interrupt due to PCIE2 PHY passed reset |
| */ |
| #define SRC_SIMR_MASK_PCIE2_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_PCIE2_PHY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_PCIE2_PHY_PASSED_RESET_MASK) |
| #define SRC_SIMR_MASK_MIPI_CSI1_PHY_PASSED_RESET_MASK (0x2000U) |
| #define SRC_SIMR_MASK_MIPI_CSI1_PHY_PASSED_RESET_SHIFT (13U) |
| /*! MASK_MIPI_CSI1_PHY_PASSED_RESET |
| * 0b0..do not mask interrupt due to MIPI CSI1 PHY passed reset - interrupt will be created |
| * 0b1..mask interrupt due to MIPI CSI1 PHY passed reset |
| */ |
| #define SRC_SIMR_MASK_MIPI_CSI1_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_MIPI_CSI1_PHY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_MIPI_CSI1_PHY_PASSED_RESET_MASK) |
| #define SRC_SIMR_MASK_MIPI_CSI2_PHY_PASSED_RESET_MASK (0x4000U) |
| #define SRC_SIMR_MASK_MIPI_CSI2_PHY_PASSED_RESET_SHIFT (14U) |
| /*! MASK_MIPI_CSI2_PHY_PASSED_RESET |
| * 0b0..do not mask interrupt due to MIPI CSI2 PHY passed reset - interrupt will be created |
| * 0b1..mask interrupt due to MIPI CSI2 PHY passed reset |
| */ |
| #define SRC_SIMR_MASK_MIPI_CSI2_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_MIPI_CSI2_PHY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_MIPI_CSI2_PHY_PASSED_RESET_MASK) |
| /*! @} */ |
| |
| /*! @name SBMR2 - SRC Boot Mode Register 2 */ |
| /*! @{ */ |
| #define SRC_SBMR2_SEC_CONFIG_MASK (0x3U) |
| #define SRC_SBMR2_SEC_CONFIG_SHIFT (0U) |
| #define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK) |
| #define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U) |
| #define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U) |
| #define SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK) |
| #define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U) |
| #define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U) |
| #define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK) |
| #define SRC_SBMR2_FUSE_FORCE_COLD_BOOT_MASK (0x20U) |
| #define SRC_SBMR2_FUSE_FORCE_COLD_BOOT_SHIFT (5U) |
| #define SRC_SBMR2_FUSE_FORCE_COLD_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_FUSE_FORCE_COLD_BOOT_SHIFT)) & SRC_SBMR2_FUSE_FORCE_COLD_BOOT_MASK) |
| #define SRC_SBMR2_BMOD_MASK (0x3000000U) |
| #define SRC_SBMR2_BMOD_SHIFT (24U) |
| #define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK) |
| /*! @} */ |
| |
| /*! @name GPR - SRC General Purpose Register 1..SRC General Purpose Register 10 */ |
| /*! @{ */ |
| #define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU) |
| #define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U) |
| #define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK) |
| #define SRC_GPR_PERSISTENT_ARG1_MASK (0xFFFFFFFFU) |
| #define SRC_GPR_PERSISTENT_ARG1_SHIFT (0U) |
| #define SRC_GPR_PERSISTENT_ARG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG1_SHIFT)) & SRC_GPR_PERSISTENT_ARG1_MASK) |
| #define SRC_GPR_PERSISTENT_ARG2_MASK (0xFFFFFFFFU) |
| #define SRC_GPR_PERSISTENT_ARG2_SHIFT (0U) |
| #define SRC_GPR_PERSISTENT_ARG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG2_SHIFT)) & SRC_GPR_PERSISTENT_ARG2_MASK) |
| #define SRC_GPR_PERSISTENT_ARG3_MASK (0xFFFFFFFFU) |
| #define SRC_GPR_PERSISTENT_ARG3_SHIFT (0U) |
| #define SRC_GPR_PERSISTENT_ARG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG3_SHIFT)) & SRC_GPR_PERSISTENT_ARG3_MASK) |
| #define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU) |
| #define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U) |
| #define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK) |
| #define SRC_GPR_PERSISTENT_ENTRY1_MASK (0xFFFFFFFFU) |
| #define SRC_GPR_PERSISTENT_ENTRY1_SHIFT (0U) |
| #define SRC_GPR_PERSISTENT_ENTRY1(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY1_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY1_MASK) |
| #define SRC_GPR_PERSISTENT_ENTRY2_MASK (0xFFFFFFFFU) |
| #define SRC_GPR_PERSISTENT_ENTRY2_SHIFT (0U) |
| #define SRC_GPR_PERSISTENT_ENTRY2(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY2_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY2_MASK) |
| #define SRC_GPR_PERSISTENT_ENTRY3_MASK (0xFFFFFFFFU) |
| #define SRC_GPR_PERSISTENT_ENTRY3_SHIFT (0U) |
| #define SRC_GPR_PERSISTENT_ENTRY3(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY3_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY3_MASK) |
| /*! @} */ |
| |
| /* The count of SRC_GPR */ |
| #define SRC_GPR_COUNT (10U) |
| |
| /*! @name DDRC_RCR - SRC DDR Controller Reset Control Register */ |
| /*! @{ */ |
| #define SRC_DDRC_RCR_DDRC1_PRST_MASK (0x1U) |
| #define SRC_DDRC_RCR_DDRC1_PRST_SHIFT (0U) |
| /*! DDRC1_PRST |
| * 0b0..De-ssert DDR Controller preset and DDR PHY reset reset |
| * 0b1..Assert DDR Controller preset and DDR PHY reset |
| */ |
| #define SRC_DDRC_RCR_DDRC1_PRST(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PRST_SHIFT)) & SRC_DDRC_RCR_DDRC1_PRST_MASK) |
| #define SRC_DDRC_RCR_DDRC1_CORE_RST_MASK (0x2U) |
| #define SRC_DDRC_RCR_DDRC1_CORE_RST_SHIFT (1U) |
| /*! DDRC1_CORE_RST |
| * 0b0..De-ssert DDR controller aresetn and core_ddrc_rstn |
| * 0b1..Assert DDR Controller preset and DDR PHY reset |
| */ |
| #define SRC_DDRC_RCR_DDRC1_CORE_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_CORE_RST_SHIFT)) & SRC_DDRC_RCR_DDRC1_CORE_RST_MASK) |
| #define SRC_DDRC_RCR_DDRC1_PHY_RESET_MASK (0x4U) |
| #define SRC_DDRC_RCR_DDRC1_PHY_RESET_SHIFT (2U) |
| /*! DDRC1_PHY_RESET |
| * 0b0..De-ssert DDR controller |
| * 0b1..Assert DDR Controller |
| */ |
| #define SRC_DDRC_RCR_DDRC1_PHY_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PHY_RESET_SHIFT)) & SRC_DDRC_RCR_DDRC1_PHY_RESET_MASK) |
| #define SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_MASK (0x8U) |
| #define SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_SHIFT (3U) |
| /*! DDRC1_PHY_PWROKIN |
| * 0b0..De-ssert DDR controller |
| * 0b1..Assert DDR Controller |
| */ |
| #define SRC_DDRC_RCR_DDRC1_PHY_PWROKIN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_SHIFT)) & SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_MASK) |
| #define SRC_DDRC_RCR_DOMAIN0_MASK (0x1000000U) |
| #define SRC_DDRC_RCR_DOMAIN0_SHIFT (24U) |
| /*! DOMAIN0 |
| * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain0. The master from domain3 can write to this register |
| */ |
| #define SRC_DDRC_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN0_SHIFT)) & SRC_DDRC_RCR_DOMAIN0_MASK) |
| #define SRC_DDRC_RCR_DOMAIN1_MASK (0x2000000U) |
| #define SRC_DDRC_RCR_DOMAIN1_SHIFT (25U) |
| /*! DOMAIN1 |
| * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain1. The master from domain3 can write to this register |
| */ |
| #define SRC_DDRC_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN1_SHIFT)) & SRC_DDRC_RCR_DOMAIN1_MASK) |
| #define SRC_DDRC_RCR_DOMAIN2_MASK (0x4000000U) |
| #define SRC_DDRC_RCR_DOMAIN2_SHIFT (26U) |
| /*! DOMAIN2 |
| * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain2. The master from domain3 can write to this register |
| */ |
| #define SRC_DDRC_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN2_SHIFT)) & SRC_DDRC_RCR_DOMAIN2_MASK) |
| #define SRC_DDRC_RCR_DOMAIN3_MASK (0x8000000U) |
| #define SRC_DDRC_RCR_DOMAIN3_SHIFT (27U) |
| /*! DOMAIN3 |
| * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain3. The master from domain3 can write to this register |
| */ |
| #define SRC_DDRC_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN3_SHIFT)) & SRC_DDRC_RCR_DOMAIN3_MASK) |
| #define SRC_DDRC_RCR_LOCK_MASK (0x40000000U) |
| #define SRC_DDRC_RCR_LOCK_SHIFT (30U) |
| /*! LOCK |
| * 0b0..[31] and [27:24] bits can be modified |
| * 0b1..[31] and [27:24] bits cannot be modified |
| */ |
| #define SRC_DDRC_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_LOCK_SHIFT)) & SRC_DDRC_RCR_LOCK_MASK) |
| #define SRC_DDRC_RCR_DOM_EN_MASK (0x80000000U) |
| #define SRC_DDRC_RCR_DOM_EN_SHIFT (31U) |
| /*! DOM_EN |
| * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters |
| * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. |
| */ |
| #define SRC_DDRC_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOM_EN_SHIFT)) & SRC_DDRC_RCR_DOM_EN_MASK) |
| /*! @} */ |
| |
| /*! @name DDRC2_RCR - SRC DDRC2 Controller Reset Control Register */ |
| /*! @{ */ |
| #define SRC_DDRC2_RCR_DDRC2_PRST_MASK (0x1U) |
| #define SRC_DDRC2_RCR_DDRC2_PRST_SHIFT (0U) |
| /*! DDRC2_PRST |
| * 0b0..De-ssert DDRC2 Controller preset and DDR PHY reset reset |
| * 0b1..Assert DDRC2 Controller preset and DDR PHY reset |
| */ |
| #define SRC_DDRC2_RCR_DDRC2_PRST(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DDRC2_PRST_SHIFT)) & SRC_DDRC2_RCR_DDRC2_PRST_MASK) |
| #define SRC_DDRC2_RCR_DDRC2_CORE_RST_MASK (0x2U) |
| #define SRC_DDRC2_RCR_DDRC2_CORE_RST_SHIFT (1U) |
| /*! DDRC2_CORE_RST |
| * 0b0..De-ssert DDR controller aresetn and core_ddrc_rstn |
| * 0b1..Assert DDR Controller preset and DDR PHY reset |
| */ |
| #define SRC_DDRC2_RCR_DDRC2_CORE_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DDRC2_CORE_RST_SHIFT)) & SRC_DDRC2_RCR_DDRC2_CORE_RST_MASK) |
| #define SRC_DDRC2_RCR_DDRC1_PHY_RESET_MASK (0x4U) |
| #define SRC_DDRC2_RCR_DDRC1_PHY_RESET_SHIFT (2U) |
| /*! DDRC1_PHY_RESET |
| * 0b0..De-ssert DDR controller |
| * 0b1..Assert DDR Controller |
| */ |
| #define SRC_DDRC2_RCR_DDRC1_PHY_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DDRC1_PHY_RESET_SHIFT)) & SRC_DDRC2_RCR_DDRC1_PHY_RESET_MASK) |
| #define SRC_DDRC2_RCR_DDRC1_PHY_PWROKIN_MASK (0x8U) |
| #define SRC_DDRC2_RCR_DDRC1_PHY_PWROKIN_SHIFT (3U) |
| /*! DDRC1_PHY_PWROKIN |
| * 0b0..De-ssert DDR controller |
| * 0b1..Assert DDR Controller |
| */ |
| #define SRC_DDRC2_RCR_DDRC1_PHY_PWROKIN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DDRC1_PHY_PWROKIN_SHIFT)) & SRC_DDRC2_RCR_DDRC1_PHY_PWROKIN_MASK) |
| #define SRC_DDRC2_RCR_DOMAIN0_MASK (0x1000000U) |
| #define SRC_DDRC2_RCR_DOMAIN0_SHIFT (24U) |
| /*! DOMAIN0 |
| * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain0. The master from domain3 can write to this register |
| */ |
| #define SRC_DDRC2_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DOMAIN0_SHIFT)) & SRC_DDRC2_RCR_DOMAIN0_MASK) |
| #define SRC_DDRC2_RCR_DOMAIN1_MASK (0x2000000U) |
| #define SRC_DDRC2_RCR_DOMAIN1_SHIFT (25U) |
| /*! DOMAIN1 |
| * 0b0..This register is not assigned to domain1. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain1. The master from domain3 can write to this register |
| */ |
| #define SRC_DDRC2_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DOMAIN1_SHIFT)) & SRC_DDRC2_RCR_DOMAIN1_MASK) |
| #define SRC_DDRC2_RCR_DOMAIN2_MASK (0x4000000U) |
| #define SRC_DDRC2_RCR_DOMAIN2_SHIFT (26U) |
| /*! DOMAIN2 |
| * 0b0..This register is not assigned to domain2. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain2. The master from domain3 can write to this register |
| */ |
| #define SRC_DDRC2_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DOMAIN2_SHIFT)) & SRC_DDRC2_RCR_DOMAIN2_MASK) |
| #define SRC_DDRC2_RCR_DOMAIN3_MASK (0x8000000U) |
| #define SRC_DDRC2_RCR_DOMAIN3_SHIFT (27U) |
| /*! DOMAIN3 |
| * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register. |
| * 0b1..This register is assigned to domain3. The master from domain3 can write to this register |
| */ |
| #define SRC_DDRC2_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DOMAIN3_SHIFT)) & SRC_DDRC2_RCR_DOMAIN3_MASK) |
| #define SRC_DDRC2_RCR_LOCK_MASK (0x40000000U) |
| #define SRC_DDRC2_RCR_LOCK_SHIFT (30U) |
| /*! LOCK |
| * 0b0..[31] and [27:24] bits can be modified |
| * 0b1..[31] and [27:24] bits cannot be modified |
| */ |
| #define SRC_DDRC2_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_LOCK_SHIFT)) & SRC_DDRC2_RCR_LOCK_MASK) |
| #define SRC_DDRC2_RCR_DOM_EN_MASK (0x80000000U) |
| #define SRC_DDRC2_RCR_DOM_EN_SHIFT (31U) |
| /*! DOM_EN |
| * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters |
| * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by the masters from the domains specified in [27:24] area. |
| */ |
| #define SRC_DDRC2_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC2_RCR_DOM_EN_SHIFT)) & SRC_DDRC2_RCR_DOM_EN_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group SRC_Register_Masks */ |
| |
| |
| /* SRC - Peripheral instance base addresses */ |
| /** Peripheral SRC base address */ |
| #define SRC_BASE (0x30390000u) |
| /** Peripheral SRC base pointer */ |
| #define SRC ((SRC_Type *)SRC_BASE) |
| /** Array initializer of SRC peripheral base addresses */ |
| #define SRC_BASE_ADDRS { SRC_BASE } |
| /** Array initializer of SRC peripheral base pointers */ |
| #define SRC_BASE_PTRS { SRC } |
| /** Interrupt vectors for the SRC peripheral type */ |
| #define SRC_IRQS { SRC_IRQn } |
| #define SRC_COMBINED_IRQS { SRC_Combined_IRQn } |
| |
| /*! |
| * @} |
| */ /* end of group SRC_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- SUBSAM Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SUBSAM_Peripheral_Access_Layer SUBSAM Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** SUBSAM - Register Layout Typedef */ |
| typedef struct { |
| struct { /* offset: 0x0 */ |
| __IO uint32_t RW; /**< , offset: 0x0 */ |
| __IO uint32_t SET; /**< , offset: 0x4 */ |
| __IO uint32_t CLR; /**< , offset: 0x8 */ |
| __IO uint32_t TOG; /**< , offset: 0xC */ |
| } SS_SYS_CTRL; |
| struct { /* offset: 0x10 */ |
| __IO uint32_t RW; /**< , offset: 0x10 */ |
| __IO uint32_t SET; /**< , offset: 0x14 */ |
| __IO uint32_t CLR; /**< , offset: 0x18 */ |
| __IO uint32_t TOG; /**< , offset: 0x1C */ |
| } SS_DISPLAY; |
| struct { /* offset: 0x20 */ |
| __IO uint32_t RW; /**< , offset: 0x20 */ |
| __IO uint32_t SET; /**< , offset: 0x24 */ |
| __IO uint32_t CLR; /**< , offset: 0x28 */ |
| __IO uint32_t TOG; /**< , offset: 0x2C */ |
| } SS_HSYNC; |
| struct { /* offset: 0x30 */ |
| __IO uint32_t RW; /**< , offset: 0x30 */ |
| __IO uint32_t SET; /**< , offset: 0x34 */ |
| __IO uint32_t CLR; /**< , offset: 0x38 */ |
| __IO uint32_t TOG; /**< , offset: 0x3C */ |
| } SS_VSYNC; |
| struct { /* offset: 0x40 */ |
| __IO uint32_t RW; /**< , offset: 0x40 */ |
| __IO uint32_t SET; /**< , offset: 0x44 */ |
| __IO uint32_t CLR; /**< , offset: 0x48 */ |
| __IO uint32_t TOG; /**< , offset: 0x4C */ |
| } SS_DE_ULC; |
| struct { /* offset: 0x50 */ |
| __IO uint32_t RW; /**< , offset: 0x50 */ |
| __IO uint32_t SET; /**< , offset: 0x54 */ |
| __IO uint32_t CLR; /**< , offset: 0x58 */ |
| __IO uint32_t TOG; /**< , offset: 0x5C */ |
| } SS_DE_LRC; |
| struct { /* offset: 0x60 */ |
| __IO uint32_t RW; /**< , offset: 0x60 */ |
| __IO uint32_t SET; /**< , offset: 0x64 */ |
| __IO uint32_t CLR; /**< , offset: 0x68 */ |
| __IO uint32_t TOG; /**< , offset: 0x6C */ |
| } SS_MODE; |
| struct { /* offset: 0x70 */ |
| __IO uint32_t RW; /**< , offset: 0x70 */ |
| __IO uint32_t SET; /**< , offset: 0x74 */ |
| __IO uint32_t CLR; /**< , offset: 0x78 */ |
| __IO uint32_t TOG; /**< , offset: 0x7C */ |
| } SS_COEFF; |
| struct { /* offset: 0x80 */ |
| __IO uint32_t RW; /**< , offset: 0x80 */ |
| __IO uint32_t SET; /**< , offset: 0x84 */ |
| __IO uint32_t CLR; /**< , offset: 0x88 */ |
| __IO uint32_t TOG; /**< , offset: 0x8C */ |
| } SS_CLIP_CB; |
| struct { /* offset: 0x90 */ |
| __IO uint32_t RW; /**< , offset: 0x90 */ |
| __IO uint32_t SET; /**< , offset: 0x94 */ |
| __IO uint32_t CLR; /**< , offset: 0x98 */ |
| __IO uint32_t TOG; /**< , offset: 0x9C */ |
| } SS_CLIP_CR; |
| struct { /* offset: 0xA0 */ |
| __IO uint32_t RW; /**< , offset: 0xA0 */ |
| __IO uint32_t SET; /**< , offset: 0xA4 */ |
| __IO uint32_t CLR; /**< , offset: 0xA8 */ |
| __IO uint32_t TOG; /**< , offset: 0xAC */ |
| } SS_INTER_MODE; |
| __IO uint32_t SS_CHKSUM_CTRL; /**< , offset: 0xB0 */ |
| __IO uint32_t SS_CHKSUM_START; /**< , offset: 0xB4 */ |
| __IO uint32_t SS_CHKSUM_END; /**< , offset: 0xB8 */ |
| __I uint32_t SS_CHKSUM_DATA_LOW; /**< , offset: 0xBC */ |
| __IO uint32_t SS_CHKSUM_DATA_HIGH; /**< , offset: 0xC0 */ |
| } SUBSAM_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- SUBSAM Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SUBSAM_Register_Masks SUBSAM Register Masks |
| * @{ |
| */ |
| |
| /*! @name SS_SYS_CTRL - */ |
| /*! @{ */ |
| #define SUBSAM_SS_SYS_CTRL_RUN_EN_MASK (0x1U) |
| #define SUBSAM_SS_SYS_CTRL_RUN_EN_SHIFT (0U) |
| #define SUBSAM_SS_SYS_CTRL_RUN_EN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_SYS_CTRL_RUN_EN_SHIFT)) & SUBSAM_SS_SYS_CTRL_RUN_EN_MASK) |
| /*! @} */ |
| |
| /*! @name SS_DISPLAY - */ |
| /*! @{ */ |
| #define SUBSAM_SS_DISPLAY_LRC_X_MASK (0x1FFFU) |
| #define SUBSAM_SS_DISPLAY_LRC_X_SHIFT (0U) |
| #define SUBSAM_SS_DISPLAY_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_DISPLAY_LRC_X_SHIFT)) & SUBSAM_SS_DISPLAY_LRC_X_MASK) |
| #define SUBSAM_SS_DISPLAY_LRC_Y_MASK (0x1FFF0000U) |
| #define SUBSAM_SS_DISPLAY_LRC_Y_SHIFT (16U) |
| #define SUBSAM_SS_DISPLAY_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_DISPLAY_LRC_Y_SHIFT)) & SUBSAM_SS_DISPLAY_LRC_Y_MASK) |
| /*! @} */ |
| |
| /*! @name SS_HSYNC - */ |
| /*! @{ */ |
| #define SUBSAM_SS_HSYNC_START_MASK (0x1FFFU) |
| #define SUBSAM_SS_HSYNC_START_SHIFT (0U) |
| #define SUBSAM_SS_HSYNC_START(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_HSYNC_START_SHIFT)) & SUBSAM_SS_HSYNC_START_MASK) |
| #define SUBSAM_SS_HSYNC_END_MASK (0x1FFF0000U) |
| #define SUBSAM_SS_HSYNC_END_SHIFT (16U) |
| #define SUBSAM_SS_HSYNC_END(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_HSYNC_END_SHIFT)) & SUBSAM_SS_HSYNC_END_MASK) |
| #define SUBSAM_SS_HSYNC_POL_MASK (0x80000000U) |
| #define SUBSAM_SS_HSYNC_POL_SHIFT (31U) |
| #define SUBSAM_SS_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_HSYNC_POL_SHIFT)) & SUBSAM_SS_HSYNC_POL_MASK) |
| /*! @} */ |
| |
| /*! @name SS_VSYNC - */ |
| /*! @{ */ |
| #define SUBSAM_SS_VSYNC_START_MASK (0x1FFFU) |
| #define SUBSAM_SS_VSYNC_START_SHIFT (0U) |
| #define SUBSAM_SS_VSYNC_START(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_VSYNC_START_SHIFT)) & SUBSAM_SS_VSYNC_START_MASK) |
| #define SUBSAM_SS_VSYNC_END_MASK (0x1FFF0000U) |
| #define SUBSAM_SS_VSYNC_END_SHIFT (16U) |
| #define SUBSAM_SS_VSYNC_END(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_VSYNC_END_SHIFT)) & SUBSAM_SS_VSYNC_END_MASK) |
| #define SUBSAM_SS_VSYNC_POL_MASK (0x80000000U) |
| #define SUBSAM_SS_VSYNC_POL_SHIFT (31U) |
| #define SUBSAM_SS_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_VSYNC_POL_SHIFT)) & SUBSAM_SS_VSYNC_POL_MASK) |
| /*! @} */ |
| |
| /*! @name SS_DE_ULC - */ |
| /*! @{ */ |
| #define SUBSAM_SS_DE_ULC_ULC_X_MASK (0x1FFFU) |
| #define SUBSAM_SS_DE_ULC_ULC_X_SHIFT (0U) |
| #define SUBSAM_SS_DE_ULC_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_DE_ULC_ULC_X_SHIFT)) & SUBSAM_SS_DE_ULC_ULC_X_MASK) |
| #define SUBSAM_SS_DE_ULC_ULC_Y_MASK (0x1FFF0000U) |
| #define SUBSAM_SS_DE_ULC_ULC_Y_SHIFT (16U) |
| #define SUBSAM_SS_DE_ULC_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_DE_ULC_ULC_Y_SHIFT)) & SUBSAM_SS_DE_ULC_ULC_Y_MASK) |
| #define SUBSAM_SS_DE_ULC_POL_MASK (0x80000000U) |
| #define SUBSAM_SS_DE_ULC_POL_SHIFT (31U) |
| #define SUBSAM_SS_DE_ULC_POL(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_DE_ULC_POL_SHIFT)) & SUBSAM_SS_DE_ULC_POL_MASK) |
| /*! @} */ |
| |
| /*! @name SS_DE_LRC - */ |
| /*! @{ */ |
| #define SUBSAM_SS_DE_LRC_LRC_X_MASK (0x1FFFU) |
| #define SUBSAM_SS_DE_LRC_LRC_X_SHIFT (0U) |
| #define SUBSAM_SS_DE_LRC_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_DE_LRC_LRC_X_SHIFT)) & SUBSAM_SS_DE_LRC_LRC_X_MASK) |
| #define SUBSAM_SS_DE_LRC_LRC_Y_MASK (0x1FFF0000U) |
| #define SUBSAM_SS_DE_LRC_LRC_Y_SHIFT (16U) |
| #define SUBSAM_SS_DE_LRC_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_DE_LRC_LRC_Y_SHIFT)) & SUBSAM_SS_DE_LRC_LRC_Y_MASK) |
| /*! @} */ |
| |
| /*! @name SS_MODE - */ |
| /*! @{ */ |
| #define SUBSAM_SS_MODE_PIPE_MODE_MASK (0x3U) |
| #define SUBSAM_SS_MODE_PIPE_MODE_SHIFT (0U) |
| #define SUBSAM_SS_MODE_PIPE_MODE(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_MODE_PIPE_MODE_SHIFT)) & SUBSAM_SS_MODE_PIPE_MODE_MASK) |
| #define SUBSAM_SS_MODE_COMP_SEL0_OUT_MASK (0x300U) |
| #define SUBSAM_SS_MODE_COMP_SEL0_OUT_SHIFT (8U) |
| #define SUBSAM_SS_MODE_COMP_SEL0_OUT(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_MODE_COMP_SEL0_OUT_SHIFT)) & SUBSAM_SS_MODE_COMP_SEL0_OUT_MASK) |
| #define SUBSAM_SS_MODE_COMP_SEL1_OUT_MASK (0xC00U) |
| #define SUBSAM_SS_MODE_COMP_SEL1_OUT_SHIFT (10U) |
| #define SUBSAM_SS_MODE_COMP_SEL1_OUT(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_MODE_COMP_SEL1_OUT_SHIFT)) & SUBSAM_SS_MODE_COMP_SEL1_OUT_MASK) |
| #define SUBSAM_SS_MODE_COMP_SEL2_OUT_MASK (0x3000U) |
| #define SUBSAM_SS_MODE_COMP_SEL2_OUT_SHIFT (12U) |
| #define SUBSAM_SS_MODE_COMP_SEL2_OUT(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_MODE_COMP_SEL2_OUT_SHIFT)) & SUBSAM_SS_MODE_COMP_SEL2_OUT_MASK) |
| #define SUBSAM_SS_MODE_COMP_SEL0_IN_MASK (0x30000U) |
| #define SUBSAM_SS_MODE_COMP_SEL0_IN_SHIFT (16U) |
| #define SUBSAM_SS_MODE_COMP_SEL0_IN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_MODE_COMP_SEL0_IN_SHIFT)) & SUBSAM_SS_MODE_COMP_SEL0_IN_MASK) |
| #define SUBSAM_SS_MODE_COMP_SEL1_IN_MASK (0xC0000U) |
| #define SUBSAM_SS_MODE_COMP_SEL1_IN_SHIFT (18U) |
| #define SUBSAM_SS_MODE_COMP_SEL1_IN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_MODE_COMP_SEL1_IN_SHIFT)) & SUBSAM_SS_MODE_COMP_SEL1_IN_MASK) |
| #define SUBSAM_SS_MODE_COMP_SEL2_IN_MASK (0x300000U) |
| #define SUBSAM_SS_MODE_COMP_SEL2_IN_SHIFT (20U) |
| #define SUBSAM_SS_MODE_COMP_SEL2_IN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_MODE_COMP_SEL2_IN_SHIFT)) & SUBSAM_SS_MODE_COMP_SEL2_IN_MASK) |
| /*! @} */ |
| |
| /*! @name SS_COEFF - */ |
| /*! @{ */ |
| #define SUBSAM_SS_COEFF_HORIZ_A_MASK (0xFU) |
| #define SUBSAM_SS_COEFF_HORIZ_A_SHIFT (0U) |
| #define SUBSAM_SS_COEFF_HORIZ_A(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_HORIZ_A_SHIFT)) & SUBSAM_SS_COEFF_HORIZ_A_MASK) |
| #define SUBSAM_SS_COEFF_HORIZ_B_MASK (0xF0U) |
| #define SUBSAM_SS_COEFF_HORIZ_B_SHIFT (4U) |
| #define SUBSAM_SS_COEFF_HORIZ_B(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_HORIZ_B_SHIFT)) & SUBSAM_SS_COEFF_HORIZ_B_MASK) |
| #define SUBSAM_SS_COEFF_HORIZ_C_MASK (0xF00U) |
| #define SUBSAM_SS_COEFF_HORIZ_C_SHIFT (8U) |
| #define SUBSAM_SS_COEFF_HORIZ_C(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_HORIZ_C_SHIFT)) & SUBSAM_SS_COEFF_HORIZ_C_MASK) |
| #define SUBSAM_SS_COEFF_HORIZ_NORM_MASK (0x7000U) |
| #define SUBSAM_SS_COEFF_HORIZ_NORM_SHIFT (12U) |
| #define SUBSAM_SS_COEFF_HORIZ_NORM(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_HORIZ_NORM_SHIFT)) & SUBSAM_SS_COEFF_HORIZ_NORM_MASK) |
| #define SUBSAM_SS_COEFF_VERT_A_MASK (0xF0000U) |
| #define SUBSAM_SS_COEFF_VERT_A_SHIFT (16U) |
| #define SUBSAM_SS_COEFF_VERT_A(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_VERT_A_SHIFT)) & SUBSAM_SS_COEFF_VERT_A_MASK) |
| #define SUBSAM_SS_COEFF_VERT_B_MASK (0xF00000U) |
| #define SUBSAM_SS_COEFF_VERT_B_SHIFT (20U) |
| #define SUBSAM_SS_COEFF_VERT_B(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_VERT_B_SHIFT)) & SUBSAM_SS_COEFF_VERT_B_MASK) |
| #define SUBSAM_SS_COEFF_VERT_C_MASK (0xF000000U) |
| #define SUBSAM_SS_COEFF_VERT_C_SHIFT (24U) |
| #define SUBSAM_SS_COEFF_VERT_C(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_VERT_C_SHIFT)) & SUBSAM_SS_COEFF_VERT_C_MASK) |
| #define SUBSAM_SS_COEFF_VERT_NORM_MASK (0x70000000U) |
| #define SUBSAM_SS_COEFF_VERT_NORM_SHIFT (28U) |
| #define SUBSAM_SS_COEFF_VERT_NORM(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_COEFF_VERT_NORM_SHIFT)) & SUBSAM_SS_COEFF_VERT_NORM_MASK) |
| /*! @} */ |
| |
| /*! @name SS_CLIP_CB - */ |
| /*! @{ */ |
| #define SUBSAM_SS_CLIP_CB_MIN_MASK (0xFFFU) |
| #define SUBSAM_SS_CLIP_CB_MIN_SHIFT (0U) |
| #define SUBSAM_SS_CLIP_CB_MIN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CLIP_CB_MIN_SHIFT)) & SUBSAM_SS_CLIP_CB_MIN_MASK) |
| #define SUBSAM_SS_CLIP_CB_MAX_MASK (0xFFF0000U) |
| #define SUBSAM_SS_CLIP_CB_MAX_SHIFT (16U) |
| #define SUBSAM_SS_CLIP_CB_MAX(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CLIP_CB_MAX_SHIFT)) & SUBSAM_SS_CLIP_CB_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name SS_CLIP_CR - */ |
| /*! @{ */ |
| #define SUBSAM_SS_CLIP_CR_MIN_MASK (0xFFFU) |
| #define SUBSAM_SS_CLIP_CR_MIN_SHIFT (0U) |
| #define SUBSAM_SS_CLIP_CR_MIN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CLIP_CR_MIN_SHIFT)) & SUBSAM_SS_CLIP_CR_MIN_MASK) |
| #define SUBSAM_SS_CLIP_CR_MAX_MASK (0xFFF0000U) |
| #define SUBSAM_SS_CLIP_CR_MAX_SHIFT (16U) |
| #define SUBSAM_SS_CLIP_CR_MAX(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CLIP_CR_MAX_SHIFT)) & SUBSAM_SS_CLIP_CR_MAX_MASK) |
| /*! @} */ |
| |
| /*! @name SS_INTER_MODE - */ |
| /*! @{ */ |
| #define SUBSAM_SS_INTER_MODE_INT_EN_MASK (0x1U) |
| #define SUBSAM_SS_INTER_MODE_INT_EN_SHIFT (0U) |
| #define SUBSAM_SS_INTER_MODE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_INTER_MODE_INT_EN_SHIFT)) & SUBSAM_SS_INTER_MODE_INT_EN_MASK) |
| #define SUBSAM_SS_INTER_MODE_VSYNC_SHIFT_MASK (0x2U) |
| #define SUBSAM_SS_INTER_MODE_VSYNC_SHIFT_SHIFT (1U) |
| #define SUBSAM_SS_INTER_MODE_VSYNC_SHIFT(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_INTER_MODE_VSYNC_SHIFT_SHIFT)) & SUBSAM_SS_INTER_MODE_VSYNC_SHIFT_MASK) |
| /*! @} */ |
| |
| /*! @name SS_CHKSUM_CTRL - */ |
| /*! @{ */ |
| #define SUBSAM_SS_CHKSUM_CTRL_CHKSUM_EN_MASK (0x1U) |
| #define SUBSAM_SS_CHKSUM_CTRL_CHKSUM_EN_SHIFT (0U) |
| /*! CHKSUM_EN |
| * 0b0..Checksum is disabled. |
| * 0b1..Checksum is enabled. |
| */ |
| #define SUBSAM_SS_CHKSUM_CTRL_CHKSUM_EN(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_CTRL_CHKSUM_EN_SHIFT)) & SUBSAM_SS_CHKSUM_CTRL_CHKSUM_EN_MASK) |
| #define SUBSAM_SS_CHKSUM_CTRL_NUM_FRAMES_MASK (0xF0U) |
| #define SUBSAM_SS_CHKSUM_CTRL_NUM_FRAMES_SHIFT (4U) |
| /*! NUM_FRAMES |
| * 0b0000..Continuous mode. Output a checksum after each start trigger to end trigger process. |
| * 0b0001..Accumulate the cheksum over one complete frame. |
| * 0b0010..Accumulate the cheksum over two complete frames. |
| * 0b0011-0b1111..Accumulate the cheksum over NUM_FRAMES complete frames. |
| */ |
| #define SUBSAM_SS_CHKSUM_CTRL_NUM_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_CTRL_NUM_FRAMES_SHIFT)) & SUBSAM_SS_CHKSUM_CTRL_NUM_FRAMES_MASK) |
| /*! @} */ |
| |
| /*! @name SS_CHKSUM_START - */ |
| /*! @{ */ |
| #define SUBSAM_SS_CHKSUM_START_VCOUNT_START_MASK (0x1FFFU) |
| #define SUBSAM_SS_CHKSUM_START_VCOUNT_START_SHIFT (0U) |
| #define SUBSAM_SS_CHKSUM_START_VCOUNT_START(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_START_VCOUNT_START_SHIFT)) & SUBSAM_SS_CHKSUM_START_VCOUNT_START_MASK) |
| #define SUBSAM_SS_CHKSUM_START_HCOUNT_START_MASK (0x1FFF0000U) |
| #define SUBSAM_SS_CHKSUM_START_HCOUNT_START_SHIFT (16U) |
| #define SUBSAM_SS_CHKSUM_START_HCOUNT_START(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_START_HCOUNT_START_SHIFT)) & SUBSAM_SS_CHKSUM_START_HCOUNT_START_MASK) |
| /*! @} */ |
| |
| /*! @name SS_CHKSUM_END - */ |
| /*! @{ */ |
| #define SUBSAM_SS_CHKSUM_END_VCOUNT_END_MASK (0x1FFFU) |
| #define SUBSAM_SS_CHKSUM_END_VCOUNT_END_SHIFT (0U) |
| #define SUBSAM_SS_CHKSUM_END_VCOUNT_END(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_END_VCOUNT_END_SHIFT)) & SUBSAM_SS_CHKSUM_END_VCOUNT_END_MASK) |
| #define SUBSAM_SS_CHKSUM_END_HCOUNT_END_MASK (0x1FFF0000U) |
| #define SUBSAM_SS_CHKSUM_END_HCOUNT_END_SHIFT (16U) |
| #define SUBSAM_SS_CHKSUM_END_HCOUNT_END(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_END_HCOUNT_END_SHIFT)) & SUBSAM_SS_CHKSUM_END_HCOUNT_END_MASK) |
| /*! @} */ |
| |
| /*! @name SS_CHKSUM_DATA_LOW - */ |
| /*! @{ */ |
| #define SUBSAM_SS_CHKSUM_DATA_LOW_CHKSUM_RESULT_MASK (0xFFFFFFFFU) |
| #define SUBSAM_SS_CHKSUM_DATA_LOW_CHKSUM_RESULT_SHIFT (0U) |
| #define SUBSAM_SS_CHKSUM_DATA_LOW_CHKSUM_RESULT(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_DATA_LOW_CHKSUM_RESULT_SHIFT)) & SUBSAM_SS_CHKSUM_DATA_LOW_CHKSUM_RESULT_MASK) |
| /*! @} */ |
| |
| /*! @name SS_CHKSUM_DATA_HIGH - */ |
| /*! @{ */ |
| #define SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_RESULT_MASK (0x3FFU) |
| #define SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_RESULT_SHIFT (0U) |
| #define SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_RESULT(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_RESULT_SHIFT)) & SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_RESULT_MASK) |
| #define SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_VLD_MASK (0x80000000U) |
| #define SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_VLD_SHIFT (31U) |
| #define SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_VLD(x) (((uint32_t)(((uint32_t)(x)) << SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_VLD_SHIFT)) & SUBSAM_SS_CHKSUM_DATA_HIGH_CHKSUM_VLD_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group SUBSAM_Register_Masks */ |
| |
| |
| /* SUBSAM - Peripheral instance base addresses */ |
| /** Peripheral DCSS__SUBSAM base address */ |
| #define DCSS__SUBSAM_BASE (0x32E1B000u) |
| /** Peripheral DCSS__SUBSAM base pointer */ |
| #define DCSS__SUBSAM ((SUBSAM_Type *)DCSS__SUBSAM_BASE) |
| /** Array initializer of SUBSAM peripheral base addresses */ |
| #define SUBSAM_BASE_ADDRS { DCSS__SUBSAM_BASE } |
| /** Array initializer of SUBSAM peripheral base pointers */ |
| #define SUBSAM_BASE_PTRS { DCSS__SUBSAM } |
| |
| /*! |
| * @} |
| */ /* end of group SUBSAM_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- TMU Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup TMU_Peripheral_Access_Layer TMU Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** TMU - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t TMR; /**< TMU Mode register, offset: 0x0 */ |
| __I uint32_t TSR; /**< TMU Status register, offset: 0x4 */ |
| __IO uint32_t TMTMIR; /**< TMU Monitor Temperature Measurement Interval register, offset: 0x8 */ |
| uint8_t RESERVED_0[20]; |
| __IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x20 */ |
| __IO uint32_t TIDR; /**< TMU Interrupt Detect register, offset: 0x24 */ |
| __IO uint32_t TISCR; /**< TMU Interrupt Site Capture register, offset: 0x28 */ |
| __IO uint32_t TICSCR; /**< TMU Interrupt Critical Site Capture register, offset: 0x2C */ |
| uint8_t RESERVED_1[16]; |
| __I uint32_t TMHTCRH; /**< TMU Monitor High Temperature Capture register, offset: 0x40 */ |
| __I uint32_t TMHTCRL; /**< TMU Monitor Low Temperature Capture register, offset: 0x44 */ |
| uint8_t RESERVED_2[8]; |
| __IO uint32_t TMHTITR; /**< TMU Monitor High Temperature Immediate Threshold register, offset: 0x50 */ |
| __IO uint32_t TMHTATR; /**< TMU Monitor High Temperature Average threshold register, offset: 0x54 */ |
| __IO uint32_t TMHTACTR; /**< TMU Monitor High Temperature Average Critical Threshold register, offset: 0x58 */ |
| uint8_t RESERVED_3[36]; |
| __IO uint32_t TTCFGR; /**< TMU Temperature Configuration register, offset: 0x80 */ |
| __IO uint32_t TSCFGR; /**< TMU Sensor Configuration register, offset: 0x84 */ |
| uint8_t RESERVED_4[120]; |
| struct { /* offset: 0x100, array step: 0x10 */ |
| __I uint32_t TRITSR; /**< TMU Report Immediate Temperature Site register n, array offset: 0x100, array step: 0x10 */ |
| __I uint32_t TRATSR; /**< TMU Report Average Temperature Site register n, array offset: 0x104, array step: 0x10 */ |
| uint8_t RESERVED_0[8]; |
| } TRTSR[16]; |
| uint8_t RESERVED_5[2552]; |
| __I uint32_t IPBRR0; /**< IP Block Revision register 0, offset: 0xBF8 */ |
| uint8_t RESERVED_6[788]; |
| __IO uint32_t TTRCR[4]; /**< TMU Temperature Range n Control register, array offset: 0xF10, array step: 0x4 */ |
| } TMU_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- TMU Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup TMU_Register_Masks TMU Register Masks |
| * @{ |
| */ |
| |
| /*! @name TMR - TMU Mode register */ |
| /*! @{ */ |
| #define TMU_TMR_MSITE_MASK (0xFFFFU) |
| #define TMU_TMR_MSITE_SHIFT (0U) |
| #define TMU_TMR_MSITE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMR_MSITE_SHIFT)) & TMU_TMR_MSITE_MASK) |
| #define TMU_TMR_ALPF_MASK (0xC000000U) |
| #define TMU_TMR_ALPF_SHIFT (26U) |
| /*! ALPF |
| * 0b00..1.0 |
| * 0b01..0.5 |
| * 0b10..0.25 |
| * 0b11..0.125 |
| */ |
| #define TMU_TMR_ALPF(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMR_ALPF_SHIFT)) & TMU_TMR_ALPF_MASK) |
| #define TMU_TMR_ME_MASK (0x80000000U) |
| #define TMU_TMR_ME_SHIFT (31U) |
| /*! ME |
| * 0b0..No monitoring. Power saving mode. |
| * 0b1..Monitoring of sites as defined by MSITE. |
| */ |
| #define TMU_TMR_ME(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMR_ME_SHIFT)) & TMU_TMR_ME_MASK) |
| /*! @} */ |
| |
| /*! @name TSR - TMU Status register */ |
| /*! @{ */ |
| #define TMU_TSR_ORH_MASK (0x10000000U) |
| #define TMU_TSR_ORH_SHIFT (28U) |
| #define TMU_TSR_ORH(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSR_ORH_SHIFT)) & TMU_TSR_ORH_MASK) |
| #define TMU_TSR_ORL_MASK (0x20000000U) |
| #define TMU_TSR_ORL_SHIFT (29U) |
| #define TMU_TSR_ORL(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSR_ORL_SHIFT)) & TMU_TSR_ORL_MASK) |
| #define TMU_TSR_MIE_MASK (0x40000000U) |
| #define TMU_TSR_MIE_SHIFT (30U) |
| /*! MIE |
| * 0b0..Monitoring interval not exceeded. |
| * 0b1..Monitoring interval exceeded. The time required to perform measurement of all monitored sites has exceeded the monitoring interval as defined by TMTMIR. |
| */ |
| #define TMU_TSR_MIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSR_MIE_SHIFT)) & TMU_TSR_MIE_MASK) |
| /*! @} */ |
| |
| /*! @name TMTMIR - TMU Monitor Temperature Measurement Interval register */ |
| /*! @{ */ |
| #define TMU_TMTMIR_TMI_MASK (0xFU) |
| #define TMU_TMTMIR_TMI_SHIFT (0U) |
| #define TMU_TMTMIR_TMI(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMTMIR_TMI_SHIFT)) & TMU_TMTMIR_TMI_MASK) |
| /*! @} */ |
| |
| /*! @name TIER - TMU Interrupt Enable register */ |
| /*! @{ */ |
| #define TMU_TIER_ATCTEIE_MASK (0x20000000U) |
| #define TMU_TIER_ATCTEIE_SHIFT (29U) |
| /*! ATCTEIE |
| * 0b0..Disabled. |
| * 0b1..Interrupt enabled. Generate an interrupt if TIDR[ATCTE] is set. |
| */ |
| #define TMU_TIER_ATCTEIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ATCTEIE_SHIFT)) & TMU_TIER_ATCTEIE_MASK) |
| #define TMU_TIER_ATTEIE_MASK (0x40000000U) |
| #define TMU_TIER_ATTEIE_SHIFT (30U) |
| /*! ATTEIE |
| * 0b0..Disabled. |
| * 0b1..Interrupt enabled. Generate an interrupt if TIDR[ATTE] is set. |
| */ |
| #define TMU_TIER_ATTEIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ATTEIE_SHIFT)) & TMU_TIER_ATTEIE_MASK) |
| #define TMU_TIER_ITTEIE_MASK (0x80000000U) |
| #define TMU_TIER_ITTEIE_SHIFT (31U) |
| /*! ITTEIE |
| * 0b0..Disabled. |
| * 0b1..Interrupt enabled. Generate an interrupt if TIDR[ITTE] is set. |
| */ |
| #define TMU_TIER_ITTEIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ITTEIE_SHIFT)) & TMU_TIER_ITTEIE_MASK) |
| /*! @} */ |
| |
| /*! @name TIDR - TMU Interrupt Detect register */ |
| /*! @{ */ |
| #define TMU_TIDR_ATCTE_MASK (0x20000000U) |
| #define TMU_TIDR_ATCTE_SHIFT (29U) |
| /*! ATCTE |
| * 0b0..No threshold exceeded. |
| * 0b1..Average temperature critical threshold, as defined by TMHTACTR, has been exceeded by one or more monitored sites. The sites which has exceeded the threshold are captured in TICSCR[CASITE]. |
| */ |
| #define TMU_TIDR_ATCTE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ATCTE_SHIFT)) & TMU_TIDR_ATCTE_MASK) |
| #define TMU_TIDR_ATTE_MASK (0x40000000U) |
| #define TMU_TIDR_ATTE_SHIFT (30U) |
| /*! ATTE |
| * 0b0..No threshold exceeded. |
| * 0b1..Average temperature threshold, as defined by TMHTATR, has been exceeded by one or more monitored sites. The sites which has exceeded the threshold are captured in TISCR[ASITE]. |
| */ |
| #define TMU_TIDR_ATTE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ATTE_SHIFT)) & TMU_TIDR_ATTE_MASK) |
| #define TMU_TIDR_ITTE_MASK (0x80000000U) |
| #define TMU_TIDR_ITTE_SHIFT (31U) |
| /*! ITTE |
| * 0b0..No threshold exceeded. |
| * 0b1..Immediate temperature threshold, as defined by TMHTITR, has been exceeded by one or more monitored sites. This includes an out-of-range measured temperature above 125degree C. The sites which has exceeded the threshold are captured in TISCR[ISITE]. |
| */ |
| #define TMU_TIDR_ITTE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ITTE_SHIFT)) & TMU_TIDR_ITTE_MASK) |
| /*! @} */ |
| |
| /*! @name TISCR - TMU Interrupt Site Capture register */ |
| /*! @{ */ |
| #define TMU_TISCR_ASITE_MASK (0xFFFFU) |
| #define TMU_TISCR_ASITE_SHIFT (0U) |
| #define TMU_TISCR_ASITE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TISCR_ASITE_SHIFT)) & TMU_TISCR_ASITE_MASK) |
| #define TMU_TISCR_ISITE_MASK (0xFFFF0000U) |
| #define TMU_TISCR_ISITE_SHIFT (16U) |
| #define TMU_TISCR_ISITE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TISCR_ISITE_SHIFT)) & TMU_TISCR_ISITE_MASK) |
| /*! @} */ |
| |
| /*! @name TICSCR - TMU Interrupt Critical Site Capture register */ |
| /*! @{ */ |
| #define TMU_TICSCR_CASITE_MASK (0xFFFFU) |
| #define TMU_TICSCR_CASITE_SHIFT (0U) |
| #define TMU_TICSCR_CASITE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TICSCR_CASITE_SHIFT)) & TMU_TICSCR_CASITE_MASK) |
| /*! @} */ |
| |
| /*! @name TMHTCRH - TMU Monitor High Temperature Capture register */ |
| /*! @{ */ |
| #define TMU_TMHTCRH_TEMP_MASK (0xFFU) |
| #define TMU_TMHTCRH_TEMP_SHIFT (0U) |
| #define TMU_TMHTCRH_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTCRH_TEMP_SHIFT)) & TMU_TMHTCRH_TEMP_MASK) |
| #define TMU_TMHTCRH_V_MASK (0x80000000U) |
| #define TMU_TMHTCRH_V_SHIFT (31U) |
| /*! V |
| * 0b0..Temperature reading is not valid due to no measured temperature within the sensor range of 0-125 degree C for an enabled monitored site. |
| * 0b1..Temperature reading is valid. |
| */ |
| #define TMU_TMHTCRH_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTCRH_V_SHIFT)) & TMU_TMHTCRH_V_MASK) |
| /*! @} */ |
| |
| /*! @name TMHTCRL - TMU Monitor Low Temperature Capture register */ |
| /*! @{ */ |
| #define TMU_TMHTCRL_TEMP_MASK (0xFFU) |
| #define TMU_TMHTCRL_TEMP_SHIFT (0U) |
| #define TMU_TMHTCRL_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTCRL_TEMP_SHIFT)) & TMU_TMHTCRL_TEMP_MASK) |
| #define TMU_TMHTCRL_V_MASK (0x80000000U) |
| #define TMU_TMHTCRL_V_SHIFT (31U) |
| /*! V |
| * 0b0..Temperature reading is not valid due to no measured temperature within the sensor range of 0-125 degree C for an enabled monitored site. |
| * 0b1..Temperature reading is valid. |
| */ |
| #define TMU_TMHTCRL_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTCRL_V_SHIFT)) & TMU_TMHTCRL_V_MASK) |
| /*! @} */ |
| |
| /*! @name TMHTITR - TMU Monitor High Temperature Immediate Threshold register */ |
| /*! @{ */ |
| #define TMU_TMHTITR_TEMP_MASK (0xFFU) |
| #define TMU_TMHTITR_TEMP_SHIFT (0U) |
| #define TMU_TMHTITR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTITR_TEMP_SHIFT)) & TMU_TMHTITR_TEMP_MASK) |
| #define TMU_TMHTITR_EN_MASK (0x80000000U) |
| #define TMU_TMHTITR_EN_SHIFT (31U) |
| /*! EN |
| * 0b0..Disabled. |
| * 0b1..Threshold enabled. |
| */ |
| #define TMU_TMHTITR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTITR_EN_SHIFT)) & TMU_TMHTITR_EN_MASK) |
| /*! @} */ |
| |
| /*! @name TMHTATR - TMU Monitor High Temperature Average threshold register */ |
| /*! @{ */ |
| #define TMU_TMHTATR_TEMP_MASK (0xFFU) |
| #define TMU_TMHTATR_TEMP_SHIFT (0U) |
| #define TMU_TMHTATR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTATR_TEMP_SHIFT)) & TMU_TMHTATR_TEMP_MASK) |
| #define TMU_TMHTATR_EN_MASK (0x80000000U) |
| #define TMU_TMHTATR_EN_SHIFT (31U) |
| /*! EN |
| * 0b0..Disabled. |
| * 0b1..Threshold enabled. |
| */ |
| #define TMU_TMHTATR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTATR_EN_SHIFT)) & TMU_TMHTATR_EN_MASK) |
| /*! @} */ |
| |
| /*! @name TMHTACTR - TMU Monitor High Temperature Average Critical Threshold register */ |
| /*! @{ */ |
| #define TMU_TMHTACTR_TEMP_MASK (0xFFU) |
| #define TMU_TMHTACTR_TEMP_SHIFT (0U) |
| #define TMU_TMHTACTR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTACTR_TEMP_SHIFT)) & TMU_TMHTACTR_TEMP_MASK) |
| #define TMU_TMHTACTR_EN_MASK (0x80000000U) |
| #define TMU_TMHTACTR_EN_SHIFT (31U) |
| /*! EN |
| * 0b0..Disabled. |
| * 0b1..Threshold enabled. |
| */ |
| #define TMU_TMHTACTR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTACTR_EN_SHIFT)) & TMU_TMHTACTR_EN_MASK) |
| /*! @} */ |
| |
| /*! @name TTCFGR - TMU Temperature Configuration register */ |
| /*! @{ */ |
| #define TMU_TTCFGR_DATA_MASK (0xFFFFFFFFU) |
| #define TMU_TTCFGR_DATA_SHIFT (0U) |
| #define TMU_TTCFGR_DATA(x) (((uint32_t)(((uint32_t)(x)) << TMU_TTCFGR_DATA_SHIFT)) & TMU_TTCFGR_DATA_MASK) |
| /*! @} */ |
| |
| /*! @name TSCFGR - TMU Sensor Configuration register */ |
| /*! @{ */ |
| #define TMU_TSCFGR_DATA_MASK (0xFFFFFFFFU) |
| #define TMU_TSCFGR_DATA_SHIFT (0U) |
| #define TMU_TSCFGR_DATA(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSCFGR_DATA_SHIFT)) & TMU_TSCFGR_DATA_MASK) |
| /*! @} */ |
| |
| /*! @name TRITSR - TMU Report Immediate Temperature Site register n */ |
| /*! @{ */ |
| #define TMU_TRITSR_TEMP_MASK (0xFFU) |
| #define TMU_TRITSR_TEMP_SHIFT (0U) |
| #define TMU_TRITSR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_TEMP_SHIFT)) & TMU_TRITSR_TEMP_MASK) |
| #define TMU_TRITSR_V_MASK (0x80000000U) |
| #define TMU_TRITSR_V_SHIFT (31U) |
| /*! V |
| * 0b0..Not valid. Temperature out of sensor range or first measurement still pending. |
| * 0b1..Valid. |
| */ |
| #define TMU_TRITSR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_V_SHIFT)) & TMU_TRITSR_V_MASK) |
| /*! @} */ |
| |
| /* The count of TMU_TRITSR */ |
| #define TMU_TRITSR_COUNT (16U) |
| |
| /*! @name TRATSR - TMU Report Average Temperature Site register n */ |
| /*! @{ */ |
| #define TMU_TRATSR_TEMP_MASK (0xFFU) |
| #define TMU_TRATSR_TEMP_SHIFT (0U) |
| #define TMU_TRATSR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRATSR_TEMP_SHIFT)) & TMU_TRATSR_TEMP_MASK) |
| #define TMU_TRATSR_V_MASK (0x80000000U) |
| #define TMU_TRATSR_V_SHIFT (31U) |
| /*! V |
| * 0b0..Not valid. Temperature out of sensor range or first measurement still pending. |
| * 0b1..Valid. |
| */ |
| #define TMU_TRATSR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRATSR_V_SHIFT)) & TMU_TRATSR_V_MASK) |
| /*! @} */ |
| |
| /* The count of TMU_TRATSR */ |
| #define TMU_TRATSR_COUNT (16U) |
| |
| /*! @name IPBRR0 - IP Block Revision register 0 */ |
| /*! @{ */ |
| #define TMU_IPBRR0_IP_MN_MASK (0xFFU) |
| #define TMU_IPBRR0_IP_MN_SHIFT (0U) |
| #define TMU_IPBRR0_IP_MN(x) (((uint32_t)(((uint32_t)(x)) << TMU_IPBRR0_IP_MN_SHIFT)) & TMU_IPBRR0_IP_MN_MASK) |
| #define TMU_IPBRR0_IP_MJ_MASK (0xFF00U) |
| #define TMU_IPBRR0_IP_MJ_SHIFT (8U) |
| #define TMU_IPBRR0_IP_MJ(x) (((uint32_t)(((uint32_t)(x)) << TMU_IPBRR0_IP_MJ_SHIFT)) & TMU_IPBRR0_IP_MJ_MASK) |
| #define TMU_IPBRR0_IP_ID_MASK (0xFFFF0000U) |
| #define TMU_IPBRR0_IP_ID_SHIFT (16U) |
| #define TMU_IPBRR0_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TMU_IPBRR0_IP_ID_SHIFT)) & TMU_IPBRR0_IP_ID_MASK) |
| /*! @} */ |
| |
| /*! @name TTRCR - TMU Temperature Range n Control register */ |
| /*! @{ */ |
| #define TMU_TTRCR_TEMP_MASK (0xFFU) |
| #define TMU_TTRCR_TEMP_SHIFT (0U) |
| #define TMU_TTRCR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TTRCR_TEMP_SHIFT)) & TMU_TTRCR_TEMP_MASK) |
| #define TMU_TTRCR_CAL_PTS_MASK (0xF0000U) |
| #define TMU_TTRCR_CAL_PTS_SHIFT (16U) |
| #define TMU_TTRCR_CAL_PTS(x) (((uint32_t)(((uint32_t)(x)) << TMU_TTRCR_CAL_PTS_SHIFT)) & TMU_TTRCR_CAL_PTS_MASK) |
| /*! @} */ |
| |
| /* The count of TMU_TTRCR */ |
| #define TMU_TTRCR_COUNT (4U) |
| |
| |
| /*! |
| * @} |
| */ /* end of group TMU_Register_Masks */ |
| |
| |
| /* TMU - Peripheral instance base addresses */ |
| /** Peripheral TMU base address */ |
| #define TMU_BASE (0x30260000u) |
| /** Peripheral TMU base pointer */ |
| #define TMU ((TMU_Type *)TMU_BASE) |
| /** Array initializer of TMU peripheral base addresses */ |
| #define TMU_BASE_ADDRS { TMU_BASE } |
| /** Array initializer of TMU peripheral base pointers */ |
| #define TMU_BASE_PTRS { TMU } |
| |
| /*! |
| * @} |
| */ /* end of group TMU_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- UART Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** UART - Register Layout Typedef */ |
| typedef struct { |
| __I uint32_t URXD; /**< UART Receiver Register, offset: 0x0 */ |
| uint8_t RESERVED_0[60]; |
| __O uint32_t UTXD; /**< UART Transmitter Register, offset: 0x40 */ |
| uint8_t RESERVED_1[60]; |
| __IO uint32_t UCR1; /**< UART Control Register 1, offset: 0x80 */ |
| __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ |
| __IO uint32_t UCR3; /**< UART Control Register 3, offset: 0x88 */ |
| __IO uint32_t UCR4; /**< UART Control Register 4, offset: 0x8C */ |
| __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ |
| __IO uint32_t USR1; /**< UART Status Register 1, offset: 0x94 */ |
| __IO uint32_t USR2; /**< UART Status Register 2, offset: 0x98 */ |
| __IO uint32_t UESC; /**< UART Escape Character Register, offset: 0x9C */ |
| __IO uint32_t UTIM; /**< UART Escape Timer Register, offset: 0xA0 */ |
| __IO uint32_t UBIR; /**< UART BRM Incremental Register, offset: 0xA4 */ |
| __IO uint32_t UBMR; /**< UART BRM Modulator Register, offset: 0xA8 */ |
| __I uint32_t UBRC; /**< UART Baud Rate Count Register, offset: 0xAC */ |
| __IO uint32_t ONEMS; /**< UART One Millisecond Register, offset: 0xB0 */ |
| __IO uint32_t UTS; /**< UART Test Register, offset: 0xB4 */ |
| __IO uint32_t UMCR; /**< UART RS-485 Mode Control Register, offset: 0xB8 */ |
| } UART_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- UART Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup UART_Register_Masks UART Register Masks |
| * @{ |
| */ |
| |
| /*! @name URXD - UART Receiver Register */ |
| /*! @{ */ |
| #define UART_URXD_RX_DATA_MASK (0xFFU) |
| #define UART_URXD_RX_DATA_SHIFT (0U) |
| #define UART_URXD_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_RX_DATA_SHIFT)) & UART_URXD_RX_DATA_MASK) |
| #define UART_URXD_PRERR_MASK (0x400U) |
| #define UART_URXD_PRERR_SHIFT (10U) |
| /*! PRERR |
| * 0b0..= No parity error was detected for data in the RX_DATA field |
| * 0b1..= A parity error was detected for data in the RX_DATA field |
| */ |
| #define UART_URXD_PRERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_PRERR_SHIFT)) & UART_URXD_PRERR_MASK) |
| #define UART_URXD_BRK_MASK (0x800U) |
| #define UART_URXD_BRK_SHIFT (11U) |
| /*! BRK |
| * 0b0..The current character is not a BREAK character |
| * 0b1..The current character is a BREAK character |
| */ |
| #define UART_URXD_BRK(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_BRK_SHIFT)) & UART_URXD_BRK_MASK) |
| #define UART_URXD_FRMERR_MASK (0x1000U) |
| #define UART_URXD_FRMERR_SHIFT (12U) |
| /*! FRMERR |
| * 0b0..The current character has no framing error |
| * 0b1..The current character has a framing error |
| */ |
| #define UART_URXD_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_FRMERR_SHIFT)) & UART_URXD_FRMERR_MASK) |
| #define UART_URXD_OVRRUN_MASK (0x2000U) |
| #define UART_URXD_OVRRUN_SHIFT (13U) |
| /*! OVRRUN |
| * 0b0..No RxFIFO overrun was detected |
| * 0b1..A RxFIFO overrun was detected |
| */ |
| #define UART_URXD_OVRRUN(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_OVRRUN_SHIFT)) & UART_URXD_OVRRUN_MASK) |
| #define UART_URXD_ERR_MASK (0x4000U) |
| #define UART_URXD_ERR_SHIFT (14U) |
| /*! ERR |
| * 0b0..No error status was detected |
| * 0b1..An error status was detected |
| */ |
| #define UART_URXD_ERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_ERR_SHIFT)) & UART_URXD_ERR_MASK) |
| #define UART_URXD_CHARRDY_MASK (0x8000U) |
| #define UART_URXD_CHARRDY_SHIFT (15U) |
| /*! CHARRDY |
| * 0b0..Character in RX_DATA field and associated flags are invalid. |
| * 0b1..Character in RX_DATA field and associated flags valid and ready for reading. |
| */ |
| #define UART_URXD_CHARRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_CHARRDY_SHIFT)) & UART_URXD_CHARRDY_MASK) |
| /*! @} */ |
| |
| /*! @name UTXD - UART Transmitter Register */ |
| /*! @{ */ |
| #define UART_UTXD_TX_DATA_MASK (0xFFU) |
| #define UART_UTXD_TX_DATA_SHIFT (0U) |
| #define UART_UTXD_TX_DATA(x) (((uint32_t)(((uint32_t)(x)) << UART_UTXD_TX_DATA_SHIFT)) & UART_UTXD_TX_DATA_MASK) |
| /*! @} */ |
| |
| /*! @name UCR1 - UART Control Register 1 */ |
| /*! @{ */ |
| #define UART_UCR1_UARTEN_MASK (0x1U) |
| #define UART_UCR1_UARTEN_SHIFT (0U) |
| /*! UARTEN |
| * 0b0..Disable the UART |
| * 0b1..Enable the UART |
| */ |
| #define UART_UCR1_UARTEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_UARTEN_SHIFT)) & UART_UCR1_UARTEN_MASK) |
| #define UART_UCR1_DOZE_MASK (0x2U) |
| #define UART_UCR1_DOZE_SHIFT (1U) |
| /*! DOZE |
| * 0b0..The UART is enabled when in DOZE state |
| * 0b1..The UART is disabled when in DOZE state |
| */ |
| #define UART_UCR1_DOZE(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_DOZE_SHIFT)) & UART_UCR1_DOZE_MASK) |
| #define UART_UCR1_ATDMAEN_MASK (0x4U) |
| #define UART_UCR1_ATDMAEN_SHIFT (2U) |
| /*! ATDMAEN |
| * 0b0..Disable AGTIM DMA request |
| * 0b1..Enable AGTIM DMA request |
| */ |
| #define UART_UCR1_ATDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ATDMAEN_SHIFT)) & UART_UCR1_ATDMAEN_MASK) |
| #define UART_UCR1_TXDMAEN_MASK (0x8U) |
| #define UART_UCR1_TXDMAEN_SHIFT (3U) |
| /*! TXDMAEN |
| * 0b0..Disable transmit DMA request |
| * 0b1..Enable transmit DMA request |
| */ |
| #define UART_UCR1_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXDMAEN_SHIFT)) & UART_UCR1_TXDMAEN_MASK) |
| #define UART_UCR1_SNDBRK_MASK (0x10U) |
| #define UART_UCR1_SNDBRK_SHIFT (4U) |
| /*! SNDBRK |
| * 0b0..Do not send a BREAK character |
| * 0b1..Send a BREAK character (continuous 0s) |
| */ |
| #define UART_UCR1_SNDBRK(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_SNDBRK_SHIFT)) & UART_UCR1_SNDBRK_MASK) |
| #define UART_UCR1_RTSDEN_MASK (0x20U) |
| #define UART_UCR1_RTSDEN_SHIFT (5U) |
| /*! RTSDEN |
| * 0b0..Disable RTSD interrupt |
| * 0b1..Enable RTSD interrupt |
| */ |
| #define UART_UCR1_RTSDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RTSDEN_SHIFT)) & UART_UCR1_RTSDEN_MASK) |
| #define UART_UCR1_TXMPTYEN_MASK (0x40U) |
| #define UART_UCR1_TXMPTYEN_SHIFT (6U) |
| /*! TXMPTYEN |
| * 0b0..Disable the transmitter FIFO empty interrupt |
| * 0b1..Enable the transmitter FIFO empty interrupt |
| */ |
| #define UART_UCR1_TXMPTYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXMPTYEN_SHIFT)) & UART_UCR1_TXMPTYEN_MASK) |
| #define UART_UCR1_IREN_MASK (0x80U) |
| #define UART_UCR1_IREN_SHIFT (7U) |
| /*! IREN |
| * 0b0..Disable the IR interface |
| * 0b1..Enable the IR interface |
| */ |
| #define UART_UCR1_IREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IREN_SHIFT)) & UART_UCR1_IREN_MASK) |
| #define UART_UCR1_RXDMAEN_MASK (0x100U) |
| #define UART_UCR1_RXDMAEN_SHIFT (8U) |
| /*! RXDMAEN |
| * 0b0..Disable DMA request |
| * 0b1..Enable DMA request |
| */ |
| #define UART_UCR1_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RXDMAEN_SHIFT)) & UART_UCR1_RXDMAEN_MASK) |
| #define UART_UCR1_RRDYEN_MASK (0x200U) |
| #define UART_UCR1_RRDYEN_SHIFT (9U) |
| /*! RRDYEN |
| * 0b0..Disables the RRDY interrupt |
| * 0b1..Enables the RRDY interrupt |
| */ |
| #define UART_UCR1_RRDYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RRDYEN_SHIFT)) & UART_UCR1_RRDYEN_MASK) |
| #define UART_UCR1_ICD_MASK (0xC00U) |
| #define UART_UCR1_ICD_SHIFT (10U) |
| /*! ICD |
| * 0b00..Idle for more than 4 frames |
| * 0b01..Idle for more than 8 frames |
| * 0b10..Idle for more than 16 frames |
| * 0b11..Idle for more than 32 frames |
| */ |
| #define UART_UCR1_ICD(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ICD_SHIFT)) & UART_UCR1_ICD_MASK) |
| #define UART_UCR1_IDEN_MASK (0x1000U) |
| #define UART_UCR1_IDEN_SHIFT (12U) |
| /*! IDEN |
| * 0b0..Disable the IDLE interrupt |
| * 0b1..Enable the IDLE interrupt |
| */ |
| #define UART_UCR1_IDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IDEN_SHIFT)) & UART_UCR1_IDEN_MASK) |
| #define UART_UCR1_TRDYEN_MASK (0x2000U) |
| #define UART_UCR1_TRDYEN_SHIFT (13U) |
| /*! TRDYEN |
| * 0b0..Disable the transmitter ready interrupt |
| * 0b1..Enable the transmitter ready interrupt |
| */ |
| #define UART_UCR1_TRDYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TRDYEN_SHIFT)) & UART_UCR1_TRDYEN_MASK) |
| #define UART_UCR1_ADBR_MASK (0x4000U) |
| #define UART_UCR1_ADBR_SHIFT (14U) |
| /*! ADBR |
| * 0b0..Disable automatic detection of baud rate |
| * 0b1..Enable automatic detection of baud rate |
| */ |
| #define UART_UCR1_ADBR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADBR_SHIFT)) & UART_UCR1_ADBR_MASK) |
| #define UART_UCR1_ADEN_MASK (0x8000U) |
| #define UART_UCR1_ADEN_SHIFT (15U) |
| /*! ADEN |
| * 0b0..Disable the automatic baud rate detection interrupt |
| * 0b1..Enable the automatic baud rate detection interrupt |
| */ |
| #define UART_UCR1_ADEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADEN_SHIFT)) & UART_UCR1_ADEN_MASK) |
| /*! @} */ |
| |
| /*! @name UCR2 - UART Control Register 2 */ |
| /*! @{ */ |
| #define UART_UCR2_SRST_MASK (0x1U) |
| #define UART_UCR2_SRST_SHIFT (0U) |
| /*! SRST |
| * 0b0..Reset the transmit and receive state machines, all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC , URXD, UTXD and UTS[6-3]. |
| * 0b1..No reset |
| */ |
| #define UART_UCR2_SRST(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_SRST_SHIFT)) & UART_UCR2_SRST_MASK) |
| #define UART_UCR2_RXEN_MASK (0x2U) |
| #define UART_UCR2_RXEN_SHIFT (1U) |
| /*! RXEN |
| * 0b0..Disable the receiver |
| * 0b1..Enable the receiver |
| */ |
| #define UART_UCR2_RXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RXEN_SHIFT)) & UART_UCR2_RXEN_MASK) |
| #define UART_UCR2_TXEN_MASK (0x4U) |
| #define UART_UCR2_TXEN_SHIFT (2U) |
| /*! TXEN |
| * 0b0..Disable the transmitter |
| * 0b1..Enable the transmitter |
| */ |
| #define UART_UCR2_TXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_TXEN_SHIFT)) & UART_UCR2_TXEN_MASK) |
| #define UART_UCR2_ATEN_MASK (0x8U) |
| #define UART_UCR2_ATEN_SHIFT (3U) |
| /*! ATEN |
| * 0b0..AGTIM interrupt disabled |
| * 0b1..AGTIM interrupt enabled |
| */ |
| #define UART_UCR2_ATEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ATEN_SHIFT)) & UART_UCR2_ATEN_MASK) |
| #define UART_UCR2_RTSEN_MASK (0x10U) |
| #define UART_UCR2_RTSEN_SHIFT (4U) |
| /*! RTSEN |
| * 0b0..Disable request to send interrupt |
| * 0b1..Enable request to send interrupt |
| */ |
| #define UART_UCR2_RTSEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTSEN_SHIFT)) & UART_UCR2_RTSEN_MASK) |
| #define UART_UCR2_WS_MASK (0x20U) |
| #define UART_UCR2_WS_SHIFT (5U) |
| /*! WS |
| * 0b0..7-bit transmit and receive character length (not including START, STOP or PARITY bits) |
| * 0b1..8-bit transmit and receive character length (not including START, STOP or PARITY bits) |
| */ |
| #define UART_UCR2_WS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_WS_SHIFT)) & UART_UCR2_WS_MASK) |
| #define UART_UCR2_STPB_MASK (0x40U) |
| #define UART_UCR2_STPB_SHIFT (6U) |
| /*! STPB |
| * 0b0..The transmitter sends 1 stop bit. The receiver expects 1 or more stop bits. |
| * 0b1..The transmitter sends 2 stop bits. The receiver expects 2 or more stop bits. |
| */ |
| #define UART_UCR2_STPB(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_STPB_SHIFT)) & UART_UCR2_STPB_MASK) |
| #define UART_UCR2_PROE_MASK (0x80U) |
| #define UART_UCR2_PROE_SHIFT (7U) |
| /*! PROE |
| * 0b0..Even parity |
| * 0b1..Odd parity |
| */ |
| #define UART_UCR2_PROE(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PROE_SHIFT)) & UART_UCR2_PROE_MASK) |
| #define UART_UCR2_PREN_MASK (0x100U) |
| #define UART_UCR2_PREN_SHIFT (8U) |
| /*! PREN |
| * 0b0..Disable parity generator and checker |
| * 0b1..Enable parity generator and checker |
| */ |
| #define UART_UCR2_PREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PREN_SHIFT)) & UART_UCR2_PREN_MASK) |
| #define UART_UCR2_RTEC_MASK (0x600U) |
| #define UART_UCR2_RTEC_SHIFT (9U) |
| /*! RTEC |
| * 0b00..Trigger interrupt on a rising edge |
| * 0b01..Trigger interrupt on a falling edge |
| * 0b1x..Trigger interrupt on any edge |
| */ |
| #define UART_UCR2_RTEC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTEC_SHIFT)) & UART_UCR2_RTEC_MASK) |
| #define UART_UCR2_ESCEN_MASK (0x800U) |
| #define UART_UCR2_ESCEN_SHIFT (11U) |
| /*! ESCEN |
| * 0b0..Disable escape sequence detection |
| * 0b1..Enable escape sequence detection |
| */ |
| #define UART_UCR2_ESCEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCEN_SHIFT)) & UART_UCR2_ESCEN_MASK) |
| #define UART_UCR2_CTS_MASK (0x1000U) |
| #define UART_UCR2_CTS_SHIFT (12U) |
| /*! CTS |
| * 0b0..The CTS_B pin is high (inactive) |
| * 0b1..The CTS_B pin is low (active) |
| */ |
| #define UART_UCR2_CTS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTS_SHIFT)) & UART_UCR2_CTS_MASK) |
| #define UART_UCR2_CTSC_MASK (0x2000U) |
| #define UART_UCR2_CTSC_SHIFT (13U) |
| /*! CTSC |
| * 0b0..The CTS_B pin is controlled by the CTS bit |
| * 0b1..The CTS_B pin is controlled by the receiver |
| */ |
| #define UART_UCR2_CTSC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTSC_SHIFT)) & UART_UCR2_CTSC_MASK) |
| #define UART_UCR2_IRTS_MASK (0x4000U) |
| #define UART_UCR2_IRTS_SHIFT (14U) |
| /*! IRTS |
| * 0b0..Transmit only when the RTS pin is asserted |
| * 0b1..Ignore the RTS pin |
| */ |
| #define UART_UCR2_IRTS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_IRTS_SHIFT)) & UART_UCR2_IRTS_MASK) |
| #define UART_UCR2_ESCI_MASK (0x8000U) |
| #define UART_UCR2_ESCI_SHIFT (15U) |
| /*! ESCI |
| * 0b0..Disable the escape sequence interrupt |
| * 0b1..Enable the escape sequence interrupt |
| */ |
| #define UART_UCR2_ESCI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCI_SHIFT)) & UART_UCR2_ESCI_MASK) |
| /*! @} */ |
| |
| /*! @name UCR3 - UART Control Register 3 */ |
| /*! @{ */ |
| #define UART_UCR3_ACIEN_MASK (0x1U) |
| #define UART_UCR3_ACIEN_SHIFT (0U) |
| /*! ACIEN |
| * 0b0..ACST interrupt disabled |
| * 0b1..ACST interrupt enabled |
| */ |
| #define UART_UCR3_ACIEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ACIEN_SHIFT)) & UART_UCR3_ACIEN_MASK) |
| #define UART_UCR3_INVT_MASK (0x2U) |
| #define UART_UCR3_INVT_SHIFT (1U) |
| /*! INVT |
| * 0b0..TXD is not inverted |
| * 0b1..TXD is inverted |
| * 0b0..TXD Active low transmission |
| * 0b1..TXD Active high transmission |
| */ |
| #define UART_UCR3_INVT(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_INVT_SHIFT)) & UART_UCR3_INVT_MASK) |
| #define UART_UCR3_RXDMUXSEL_MASK (0x4U) |
| #define UART_UCR3_RXDMUXSEL_SHIFT (2U) |
| #define UART_UCR3_RXDMUXSEL(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDMUXSEL_SHIFT)) & UART_UCR3_RXDMUXSEL_MASK) |
| #define UART_UCR3_DTRDEN_MASK (0x8U) |
| #define UART_UCR3_DTRDEN_SHIFT (3U) |
| #define UART_UCR3_DTRDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTRDEN_SHIFT)) & UART_UCR3_DTRDEN_MASK) |
| #define UART_UCR3_AWAKEN_MASK (0x10U) |
| #define UART_UCR3_AWAKEN_SHIFT (4U) |
| /*! AWAKEN |
| * 0b0..Disable the AWAKE interrupt |
| * 0b1..Enable the AWAKE interrupt |
| */ |
| #define UART_UCR3_AWAKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AWAKEN_SHIFT)) & UART_UCR3_AWAKEN_MASK) |
| #define UART_UCR3_AIRINTEN_MASK (0x20U) |
| #define UART_UCR3_AIRINTEN_SHIFT (5U) |
| /*! AIRINTEN |
| * 0b0..Disable the AIRINT interrupt |
| * 0b1..Enable the AIRINT interrupt |
| */ |
| #define UART_UCR3_AIRINTEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AIRINTEN_SHIFT)) & UART_UCR3_AIRINTEN_MASK) |
| #define UART_UCR3_RXDSEN_MASK (0x40U) |
| #define UART_UCR3_RXDSEN_SHIFT (6U) |
| /*! RXDSEN |
| * 0b0..Disable the RXDS interrupt |
| * 0b1..Enable the RXDS interrupt |
| */ |
| #define UART_UCR3_RXDSEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDSEN_SHIFT)) & UART_UCR3_RXDSEN_MASK) |
| #define UART_UCR3_ADNIMP_MASK (0x80U) |
| #define UART_UCR3_ADNIMP_SHIFT (7U) |
| /*! ADNIMP |
| * 0b0..Autobaud detection new features selected |
| * 0b1..Keep old autobaud detection mechanism |
| */ |
| #define UART_UCR3_ADNIMP(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ADNIMP_SHIFT)) & UART_UCR3_ADNIMP_MASK) |
| #define UART_UCR3_RI_MASK (0x100U) |
| #define UART_UCR3_RI_SHIFT (8U) |
| #define UART_UCR3_RI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RI_SHIFT)) & UART_UCR3_RI_MASK) |
| #define UART_UCR3_DCD_MASK (0x200U) |
| #define UART_UCR3_DCD_SHIFT (9U) |
| #define UART_UCR3_DCD(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DCD_SHIFT)) & UART_UCR3_DCD_MASK) |
| #define UART_UCR3_DSR_MASK (0x400U) |
| #define UART_UCR3_DSR_SHIFT (10U) |
| #define UART_UCR3_DSR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DSR_SHIFT)) & UART_UCR3_DSR_MASK) |
| #define UART_UCR3_FRAERREN_MASK (0x800U) |
| #define UART_UCR3_FRAERREN_SHIFT (11U) |
| /*! FRAERREN |
| * 0b0..Disable the frame error interrupt |
| * 0b1..Enable the frame error interrupt |
| */ |
| #define UART_UCR3_FRAERREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_FRAERREN_SHIFT)) & UART_UCR3_FRAERREN_MASK) |
| #define UART_UCR3_PARERREN_MASK (0x1000U) |
| #define UART_UCR3_PARERREN_SHIFT (12U) |
| /*! PARERREN |
| * 0b0..Disable the parity error interrupt |
| * 0b1..Enable the parity error interrupt |
| */ |
| #define UART_UCR3_PARERREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_PARERREN_SHIFT)) & UART_UCR3_PARERREN_MASK) |
| #define UART_UCR3_DTREN_MASK (0x2000U) |
| #define UART_UCR3_DTREN_SHIFT (13U) |
| #define UART_UCR3_DTREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTREN_SHIFT)) & UART_UCR3_DTREN_MASK) |
| #define UART_UCR3_DPEC_MASK (0xC000U) |
| #define UART_UCR3_DPEC_SHIFT (14U) |
| #define UART_UCR3_DPEC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DPEC_SHIFT)) & UART_UCR3_DPEC_MASK) |
| /*! @} */ |
| |
| /*! @name UCR4 - UART Control Register 4 */ |
| /*! @{ */ |
| #define UART_UCR4_DREN_MASK (0x1U) |
| #define UART_UCR4_DREN_SHIFT (0U) |
| /*! DREN |
| * 0b0..Disable RDR interrupt |
| * 0b1..Enable RDR interrupt |
| */ |
| #define UART_UCR4_DREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_DREN_SHIFT)) & UART_UCR4_DREN_MASK) |
| #define UART_UCR4_OREN_MASK (0x2U) |
| #define UART_UCR4_OREN_SHIFT (1U) |
| /*! OREN |
| * 0b0..Disable ORE interrupt |
| * 0b1..Enable ORE interrupt |
| */ |
| #define UART_UCR4_OREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_OREN_SHIFT)) & UART_UCR4_OREN_MASK) |
| #define UART_UCR4_BKEN_MASK (0x4U) |
| #define UART_UCR4_BKEN_SHIFT (2U) |
| /*! BKEN |
| * 0b0..Disable the BRCD interrupt |
| * 0b1..Enable the BRCD interrupt |
| */ |
| #define UART_UCR4_BKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_BKEN_SHIFT)) & UART_UCR4_BKEN_MASK) |
| #define UART_UCR4_TCEN_MASK (0x8U) |
| #define UART_UCR4_TCEN_SHIFT (3U) |
| /*! TCEN |
| * 0b0..Disable TXDC interrupt |
| * 0b1..Enable TXDC interrupt |
| */ |
| #define UART_UCR4_TCEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_TCEN_SHIFT)) & UART_UCR4_TCEN_MASK) |
| #define UART_UCR4_LPBYP_MASK (0x10U) |
| #define UART_UCR4_LPBYP_SHIFT (4U) |
| /*! LPBYP |
| * 0b0..Low power features enabled |
| * 0b1..Low power features disabled |
| */ |
| #define UART_UCR4_LPBYP(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_LPBYP_SHIFT)) & UART_UCR4_LPBYP_MASK) |
| #define UART_UCR4_IRSC_MASK (0x20U) |
| #define UART_UCR4_IRSC_SHIFT (5U) |
| /*! IRSC |
| * 0b0..The vote logic uses the sampling clock (16x baud rate) for normal operation |
| * 0b1..The vote logic uses the UART reference clock |
| */ |
| #define UART_UCR4_IRSC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IRSC_SHIFT)) & UART_UCR4_IRSC_MASK) |
| #define UART_UCR4_IDDMAEN_MASK (0x40U) |
| #define UART_UCR4_IDDMAEN_SHIFT (6U) |
| /*! IDDMAEN |
| * 0b0..DMA IDLE interrupt disabled |
| * 0b1..DMA IDLE interrupt enabled |
| */ |
| #define UART_UCR4_IDDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IDDMAEN_SHIFT)) & UART_UCR4_IDDMAEN_MASK) |
| #define UART_UCR4_WKEN_MASK (0x80U) |
| #define UART_UCR4_WKEN_SHIFT (7U) |
| /*! WKEN |
| * 0b0..Disable the WAKE interrupt |
| * 0b1..Enable the WAKE interrupt |
| */ |
| #define UART_UCR4_WKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_WKEN_SHIFT)) & UART_UCR4_WKEN_MASK) |
| #define UART_UCR4_ENIRI_MASK (0x100U) |
| #define UART_UCR4_ENIRI_SHIFT (8U) |
| /*! ENIRI |
| * 0b0..Serial infrared Interrupt disabled |
| * 0b1..Serial infrared Interrupt enabled |
| */ |
| #define UART_UCR4_ENIRI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_ENIRI_SHIFT)) & UART_UCR4_ENIRI_MASK) |
| #define UART_UCR4_INVR_MASK (0x200U) |
| #define UART_UCR4_INVR_SHIFT (9U) |
| /*! INVR |
| * 0b0..RXD input is not inverted |
| * 0b1..RXD input is inverted |
| * 0b0..RXD active low detection |
| * 0b1..RXD active high detection |
| */ |
| #define UART_UCR4_INVR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_INVR_SHIFT)) & UART_UCR4_INVR_MASK) |
| #define UART_UCR4_CTSTL_MASK (0xFC00U) |
| #define UART_UCR4_CTSTL_SHIFT (10U) |
| /*! CTSTL |
| * 0b000000..0 characters received |
| * 0b000001..1 characters in the RxFIFO |
| * 0b100000..32 characters in the RxFIFO (maximum) |
| */ |
| #define UART_UCR4_CTSTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_CTSTL_SHIFT)) & UART_UCR4_CTSTL_MASK) |
| /*! @} */ |
| |
| /*! @name UFCR - UART FIFO Control Register */ |
| /*! @{ */ |
| #define UART_UFCR_RXTL_MASK (0x3FU) |
| #define UART_UFCR_RXTL_SHIFT (0U) |
| /*! RXTL |
| * 0b000000..0 characters received |
| * 0b000001..RxFIFO has 1 character |
| * 0b011111..RxFIFO has 31 characters |
| * 0b100000..RxFIFO has 32 characters (maximum) |
| */ |
| #define UART_UFCR_RXTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RXTL_SHIFT)) & UART_UFCR_RXTL_MASK) |
| #define UART_UFCR_DCEDTE_MASK (0x40U) |
| #define UART_UFCR_DCEDTE_SHIFT (6U) |
| /*! DCEDTE |
| * 0b0..DCE mode selected |
| * 0b1..DTE mode selected |
| */ |
| #define UART_UFCR_DCEDTE(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_DCEDTE_SHIFT)) & UART_UFCR_DCEDTE_MASK) |
| #define UART_UFCR_RFDIV_MASK (0x380U) |
| #define UART_UFCR_RFDIV_SHIFT (7U) |
| /*! RFDIV |
| * 0b000..Divide input clock by 6 |
| * 0b001..Divide input clock by 5 |
| * 0b010..Divide input clock by 4 |
| * 0b011..Divide input clock by 3 |
| * 0b100..Divide input clock by 2 |
| * 0b101..Divide input clock by 1 |
| * 0b110..Divide input clock by 7 |
| * 0b111..Reserved |
| */ |
| #define UART_UFCR_RFDIV(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RFDIV_SHIFT)) & UART_UFCR_RFDIV_MASK) |
| #define UART_UFCR_TXTL_MASK (0xFC00U) |
| #define UART_UFCR_TXTL_SHIFT (10U) |
| /*! TXTL |
| * 0b000000..Reserved |
| * 0b000001..Reserved |
| * 0b000010..TxFIFO has 2 or fewer characters |
| * 0b011111..TxFIFO has 31 or fewer characters |
| * 0b100000..TxFIFO has 32 characters (maximum) |
| */ |
| #define UART_UFCR_TXTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_TXTL_SHIFT)) & UART_UFCR_TXTL_MASK) |
| /*! @} */ |
| |
| /*! @name USR1 - UART Status Register 1 */ |
| /*! @{ */ |
| #define UART_USR1_SAD_MASK (0x8U) |
| #define UART_USR1_SAD_SHIFT (3U) |
| /*! SAD |
| * 0b0..No slave address detected |
| * 0b1..Slave address detected |
| */ |
| #define UART_USR1_SAD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_SAD_SHIFT)) & UART_USR1_SAD_MASK) |
| #define UART_USR1_AWAKE_MASK (0x10U) |
| #define UART_USR1_AWAKE_SHIFT (4U) |
| /*! AWAKE |
| * 0b0..No falling edge was detected on the RXD Serial pin |
| * 0b1..A falling edge was detected on the RXD Serial pin |
| */ |
| #define UART_USR1_AWAKE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AWAKE_SHIFT)) & UART_USR1_AWAKE_MASK) |
| #define UART_USR1_AIRINT_MASK (0x20U) |
| #define UART_USR1_AIRINT_SHIFT (5U) |
| /*! AIRINT |
| * 0b0..No pulse was detected on the RXD IrDA pin |
| * 0b1..A pulse was detected on the RXD IrDA pin |
| */ |
| #define UART_USR1_AIRINT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AIRINT_SHIFT)) & UART_USR1_AIRINT_MASK) |
| #define UART_USR1_RXDS_MASK (0x40U) |
| #define UART_USR1_RXDS_SHIFT (6U) |
| /*! RXDS |
| * 0b0..Receive in progress |
| * 0b1..Receiver is IDLE |
| */ |
| #define UART_USR1_RXDS(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RXDS_SHIFT)) & UART_USR1_RXDS_MASK) |
| #define UART_USR1_DTRD_MASK (0x80U) |
| #define UART_USR1_DTRD_SHIFT (7U) |
| #define UART_USR1_DTRD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_DTRD_SHIFT)) & UART_USR1_DTRD_MASK) |
| #define UART_USR1_AGTIM_MASK (0x100U) |
| #define UART_USR1_AGTIM_SHIFT (8U) |
| /*! AGTIM |
| * 0b0..AGTIM is not active |
| * 0b1..AGTIM is active (write 1 to clear) |
| */ |
| #define UART_USR1_AGTIM(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AGTIM_SHIFT)) & UART_USR1_AGTIM_MASK) |
| #define UART_USR1_RRDY_MASK (0x200U) |
| #define UART_USR1_RRDY_SHIFT (9U) |
| /*! RRDY |
| * 0b0..No character ready |
| * 0b1..Character(s) ready (interrupt posted) |
| */ |
| #define UART_USR1_RRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RRDY_SHIFT)) & UART_USR1_RRDY_MASK) |
| #define UART_USR1_FRAMERR_MASK (0x400U) |
| #define UART_USR1_FRAMERR_SHIFT (10U) |
| /*! FRAMERR |
| * 0b0..No frame error detected |
| * 0b1..Frame error detected (write 1 to clear) |
| */ |
| #define UART_USR1_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_FRAMERR_SHIFT)) & UART_USR1_FRAMERR_MASK) |
| #define UART_USR1_ESCF_MASK (0x800U) |
| #define UART_USR1_ESCF_SHIFT (11U) |
| /*! ESCF |
| * 0b0..No escape sequence detected |
| * 0b1..Escape sequence detected (write 1 to clear). |
| */ |
| #define UART_USR1_ESCF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_ESCF_SHIFT)) & UART_USR1_ESCF_MASK) |
| #define UART_USR1_RTSD_MASK (0x1000U) |
| #define UART_USR1_RTSD_SHIFT (12U) |
| /*! RTSD |
| * 0b0..RTS_B pin did not change state since last cleared |
| * 0b1..RTS_B pin changed state (write 1 to clear) |
| */ |
| #define UART_USR1_RTSD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSD_SHIFT)) & UART_USR1_RTSD_MASK) |
| #define UART_USR1_TRDY_MASK (0x2000U) |
| #define UART_USR1_TRDY_SHIFT (13U) |
| /*! TRDY |
| * 0b0..The transmitter does not require data |
| * 0b1..The transmitter requires data (interrupt posted) |
| */ |
| #define UART_USR1_TRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_TRDY_SHIFT)) & UART_USR1_TRDY_MASK) |
| #define UART_USR1_RTSS_MASK (0x4000U) |
| #define UART_USR1_RTSS_SHIFT (14U) |
| /*! RTSS |
| * 0b0..The RTS_B module input is high (inactive) |
| * 0b1..The RTS_B module input is low (active) |
| */ |
| #define UART_USR1_RTSS(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSS_SHIFT)) & UART_USR1_RTSS_MASK) |
| #define UART_USR1_PARITYERR_MASK (0x8000U) |
| #define UART_USR1_PARITYERR_SHIFT (15U) |
| /*! PARITYERR |
| * 0b0..No parity error detected |
| * 0b1..Parity error detected (write 1 to clear) |
| */ |
| #define UART_USR1_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_PARITYERR_SHIFT)) & UART_USR1_PARITYERR_MASK) |
| /*! @} */ |
| |
| /*! @name USR2 - UART Status Register 2 */ |
| /*! @{ */ |
| #define UART_USR2_RDR_MASK (0x1U) |
| #define UART_USR2_RDR_SHIFT (0U) |
| /*! RDR |
| * 0b0..No receive data ready |
| * 0b1..Receive data ready |
| */ |
| #define UART_USR2_RDR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RDR_SHIFT)) & UART_USR2_RDR_MASK) |
| #define UART_USR2_ORE_MASK (0x2U) |
| #define UART_USR2_ORE_SHIFT (1U) |
| /*! ORE |
| * 0b0..No overrun error |
| * 0b1..Overrun error (write 1 to clear) |
| */ |
| #define UART_USR2_ORE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ORE_SHIFT)) & UART_USR2_ORE_MASK) |
| #define UART_USR2_BRCD_MASK (0x4U) |
| #define UART_USR2_BRCD_SHIFT (2U) |
| /*! BRCD |
| * 0b0..No BREAK condition was detected |
| * 0b1..A BREAK condition was detected (write 1 to clear) |
| */ |
| #define UART_USR2_BRCD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_BRCD_SHIFT)) & UART_USR2_BRCD_MASK) |
| #define UART_USR2_TXDC_MASK (0x8U) |
| #define UART_USR2_TXDC_SHIFT (3U) |
| /*! TXDC |
| * 0b0..Transmit is incomplete |
| * 0b1..Transmit is complete |
| */ |
| #define UART_USR2_TXDC(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXDC_SHIFT)) & UART_USR2_TXDC_MASK) |
| #define UART_USR2_RTSF_MASK (0x10U) |
| #define UART_USR2_RTSF_SHIFT (4U) |
| /*! RTSF |
| * 0b0..Programmed edge not detected on RTS_B |
| * 0b1..Programmed edge detected on RTS_B (write 1 to clear) |
| */ |
| #define UART_USR2_RTSF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RTSF_SHIFT)) & UART_USR2_RTSF_MASK) |
| #define UART_USR2_DCDIN_MASK (0x20U) |
| #define UART_USR2_DCDIN_SHIFT (5U) |
| #define UART_USR2_DCDIN(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDIN_SHIFT)) & UART_USR2_DCDIN_MASK) |
| #define UART_USR2_DCDDELT_MASK (0x40U) |
| #define UART_USR2_DCDDELT_SHIFT (6U) |
| #define UART_USR2_DCDDELT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDDELT_SHIFT)) & UART_USR2_DCDDELT_MASK) |
| #define UART_USR2_WAKE_MASK (0x80U) |
| #define UART_USR2_WAKE_SHIFT (7U) |
| /*! WAKE |
| * 0b0..start bit not detected |
| * 0b1..start bit detected (write 1 to clear) |
| */ |
| #define UART_USR2_WAKE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_WAKE_SHIFT)) & UART_USR2_WAKE_MASK) |
| #define UART_USR2_IRINT_MASK (0x100U) |
| #define UART_USR2_IRINT_SHIFT (8U) |
| /*! IRINT |
| * 0b0..no edge detected |
| * 0b1..valid edge detected (write 1 to clear) |
| */ |
| #define UART_USR2_IRINT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_IRINT_SHIFT)) & UART_USR2_IRINT_MASK) |
| #define UART_USR2_RIIN_MASK (0x200U) |
| #define UART_USR2_RIIN_SHIFT (9U) |
| #define UART_USR2_RIIN(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIIN_SHIFT)) & UART_USR2_RIIN_MASK) |
| #define UART_USR2_RIDELT_MASK (0x400U) |
| #define UART_USR2_RIDELT_SHIFT (10U) |
| #define UART_USR2_RIDELT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIDELT_SHIFT)) & UART_USR2_RIDELT_MASK) |
| #define UART_USR2_ACST_MASK (0x800U) |
| #define UART_USR2_ACST_SHIFT (11U) |
| /*! ACST |
| * 0b0..Measurement of bit length not finished (in autobaud) |
| * 0b1..Measurement of bit length finished (in autobaud). (write 1 to clear) |
| */ |
| #define UART_USR2_ACST(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ACST_SHIFT)) & UART_USR2_ACST_MASK) |
| #define UART_USR2_IDLE_MASK (0x1000U) |
| #define UART_USR2_IDLE_SHIFT (12U) |
| /*! IDLE |
| * 0b0..No idle condition detected |
| * 0b1..Idle condition detected (write 1 to clear) |
| */ |
| #define UART_USR2_IDLE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_IDLE_SHIFT)) & UART_USR2_IDLE_MASK) |
| #define UART_USR2_DTRF_MASK (0x2000U) |
| #define UART_USR2_DTRF_SHIFT (13U) |
| #define UART_USR2_DTRF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DTRF_SHIFT)) & UART_USR2_DTRF_MASK) |
| #define UART_USR2_TXFE_MASK (0x4000U) |
| #define UART_USR2_TXFE_SHIFT (14U) |
| /*! TXFE |
| * 0b0..The transmit buffer (TxFIFO) is not empty |
| * 0b1..The transmit buffer (TxFIFO) is empty |
| */ |
| #define UART_USR2_TXFE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXFE_SHIFT)) & UART_USR2_TXFE_MASK) |
| #define UART_USR2_ADET_MASK (0x8000U) |
| #define UART_USR2_ADET_SHIFT (15U) |
| /*! ADET |
| * 0b0..ASCII "A" or "a" was not received |
| * 0b1..ASCII "A" or "a" was received (write 1 to clear) |
| */ |
| #define UART_USR2_ADET(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ADET_SHIFT)) & UART_USR2_ADET_MASK) |
| /*! @} */ |
| |
| /*! @name UESC - UART Escape Character Register */ |
| /*! @{ */ |
| #define UART_UESC_ESC_CHAR_MASK (0xFFU) |
| #define UART_UESC_ESC_CHAR_SHIFT (0U) |
| #define UART_UESC_ESC_CHAR(x) (((uint32_t)(((uint32_t)(x)) << UART_UESC_ESC_CHAR_SHIFT)) & UART_UESC_ESC_CHAR_MASK) |
| /*! @} */ |
| |
| /*! @name UTIM - UART Escape Timer Register */ |
| /*! @{ */ |
| #define UART_UTIM_TIM_MASK (0xFFFU) |
| #define UART_UTIM_TIM_SHIFT (0U) |
| #define UART_UTIM_TIM(x) (((uint32_t)(((uint32_t)(x)) << UART_UTIM_TIM_SHIFT)) & UART_UTIM_TIM_MASK) |
| /*! @} */ |
| |
| /*! @name UBIR - UART BRM Incremental Register */ |
| /*! @{ */ |
| #define UART_UBIR_INC_MASK (0xFFFFU) |
| #define UART_UBIR_INC_SHIFT (0U) |
| #define UART_UBIR_INC(x) (((uint32_t)(((uint32_t)(x)) << UART_UBIR_INC_SHIFT)) & UART_UBIR_INC_MASK) |
| /*! @} */ |
| |
| /*! @name UBMR - UART BRM Modulator Register */ |
| /*! @{ */ |
| #define UART_UBMR_MOD_MASK (0xFFFFU) |
| #define UART_UBMR_MOD_SHIFT (0U) |
| #define UART_UBMR_MOD(x) (((uint32_t)(((uint32_t)(x)) << UART_UBMR_MOD_SHIFT)) & UART_UBMR_MOD_MASK) |
| /*! @} */ |
| |
| /*! @name UBRC - UART Baud Rate Count Register */ |
| /*! @{ */ |
| #define UART_UBRC_BCNT_MASK (0xFFFFU) |
| #define UART_UBRC_BCNT_SHIFT (0U) |
| #define UART_UBRC_BCNT(x) (((uint32_t)(((uint32_t)(x)) << UART_UBRC_BCNT_SHIFT)) & UART_UBRC_BCNT_MASK) |
| /*! @} */ |
| |
| /*! @name ONEMS - UART One Millisecond Register */ |
| /*! @{ */ |
| #define UART_ONEMS_ONEMS_MASK (0xFFFFFFU) |
| #define UART_ONEMS_ONEMS_SHIFT (0U) |
| #define UART_ONEMS_ONEMS(x) (((uint32_t)(((uint32_t)(x)) << UART_ONEMS_ONEMS_SHIFT)) & UART_ONEMS_ONEMS_MASK) |
| /*! @} */ |
| |
| /*! @name UTS - UART Test Register */ |
| /*! @{ */ |
| #define UART_UTS_SOFTRST_MASK (0x1U) |
| #define UART_UTS_SOFTRST_SHIFT (0U) |
| /*! SOFTRST |
| * 0b0..Software reset inactive |
| * 0b1..Software reset active |
| */ |
| #define UART_UTS_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_SOFTRST_SHIFT)) & UART_UTS_SOFTRST_MASK) |
| #define UART_UTS_RXFULL_MASK (0x8U) |
| #define UART_UTS_RXFULL_SHIFT (3U) |
| /*! RXFULL |
| * 0b0..The RxFIFO is not full |
| * 0b1..The RxFIFO is full |
| */ |
| #define UART_UTS_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXFULL_SHIFT)) & UART_UTS_RXFULL_MASK) |
| #define UART_UTS_TXFULL_MASK (0x10U) |
| #define UART_UTS_TXFULL_SHIFT (4U) |
| /*! TXFULL |
| * 0b0..The TxFIFO is not full |
| * 0b1..The TxFIFO is full |
| */ |
| #define UART_UTS_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXFULL_SHIFT)) & UART_UTS_TXFULL_MASK) |
| #define UART_UTS_RXEMPTY_MASK (0x20U) |
| #define UART_UTS_RXEMPTY_SHIFT (5U) |
| /*! RXEMPTY |
| * 0b0..The RxFIFO is not empty |
| * 0b1..The RxFIFO is empty |
| */ |
| #define UART_UTS_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXEMPTY_SHIFT)) & UART_UTS_RXEMPTY_MASK) |
| #define UART_UTS_TXEMPTY_MASK (0x40U) |
| #define UART_UTS_TXEMPTY_SHIFT (6U) |
| /*! TXEMPTY |
| * 0b0..The TxFIFO is not empty |
| * 0b1..The TxFIFO is empty |
| */ |
| #define UART_UTS_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXEMPTY_SHIFT)) & UART_UTS_TXEMPTY_MASK) |
| #define UART_UTS_RXDBG_MASK (0x200U) |
| #define UART_UTS_RXDBG_SHIFT (9U) |
| /*! RXDBG |
| * 0b0..rx fifo read pointer does not increment |
| * 0b1..rx_fifo read pointer increments as normal |
| */ |
| #define UART_UTS_RXDBG(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXDBG_SHIFT)) & UART_UTS_RXDBG_MASK) |
| #define UART_UTS_LOOPIR_MASK (0x400U) |
| #define UART_UTS_LOOPIR_SHIFT (10U) |
| /*! LOOPIR |
| * 0b0..No IR loop |
| * 0b1..Connect IR transmitter to IR receiver |
| */ |
| #define UART_UTS_LOOPIR(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOPIR_SHIFT)) & UART_UTS_LOOPIR_MASK) |
| #define UART_UTS_DBGEN_MASK (0x800U) |
| #define UART_UTS_DBGEN_SHIFT (11U) |
| /*! DBGEN |
| * 0b0..UART will go into debug mode when debug_req is HIGH |
| * 0b1..UART will not go into debug mode even if debug_req is HIGH |
| */ |
| #define UART_UTS_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_DBGEN_SHIFT)) & UART_UTS_DBGEN_MASK) |
| #define UART_UTS_LOOP_MASK (0x1000U) |
| #define UART_UTS_LOOP_SHIFT (12U) |
| /*! LOOP |
| * 0b0..Normal receiver operation |
| * 0b1..Internally connect the transmitter output to the receiver input |
| */ |
| #define UART_UTS_LOOP(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOP_SHIFT)) & UART_UTS_LOOP_MASK) |
| #define UART_UTS_FRCPERR_MASK (0x2000U) |
| #define UART_UTS_FRCPERR_SHIFT (13U) |
| /*! FRCPERR |
| * 0b0..Generate normal parity |
| * 0b1..Generate inverted parity (error) |
| */ |
| #define UART_UTS_FRCPERR(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_FRCPERR_SHIFT)) & UART_UTS_FRCPERR_MASK) |
| /*! @} */ |
| |
| /*! @name UMCR - UART RS-485 Mode Control Register */ |
| /*! @{ */ |
| #define UART_UMCR_MDEN_MASK (0x1U) |
| #define UART_UMCR_MDEN_SHIFT (0U) |
| /*! MDEN |
| * 0b0..Normal RS-232 or IrDA mode, see for detail. |
| * 0b1..Enable RS-485 mode, see for detail |
| */ |
| #define UART_UMCR_MDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_MDEN_SHIFT)) & UART_UMCR_MDEN_MASK) |
| #define UART_UMCR_SLAM_MASK (0x2U) |
| #define UART_UMCR_SLAM_SHIFT (1U) |
| /*! SLAM |
| * 0b0..Select Normal Address Detect mode |
| * 0b1..Select Automatic Address Detect mode |
| */ |
| #define UART_UMCR_SLAM(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLAM_SHIFT)) & UART_UMCR_SLAM_MASK) |
| #define UART_UMCR_TXB8_MASK (0x4U) |
| #define UART_UMCR_TXB8_SHIFT (2U) |
| /*! TXB8 |
| * 0b0..0 will be transmitted as the RS485 9th data bit |
| * 0b1..1 will be transmitted as the RS485 9th data bit |
| */ |
| #define UART_UMCR_TXB8(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_TXB8_SHIFT)) & UART_UMCR_TXB8_MASK) |
| #define UART_UMCR_SADEN_MASK (0x8U) |
| #define UART_UMCR_SADEN_SHIFT (3U) |
| /*! SADEN |
| * 0b0..Disable RS-485 Slave Address Detected Interrupt |
| * 0b1..Enable RS-485 Slave Address Detected Interrupt |
| */ |
| #define UART_UMCR_SADEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SADEN_SHIFT)) & UART_UMCR_SADEN_MASK) |
| #define UART_UMCR_SLADDR_MASK (0xFF00U) |
| #define UART_UMCR_SLADDR_SHIFT (8U) |
| #define UART_UMCR_SLADDR(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLADDR_SHIFT)) & UART_UMCR_SLADDR_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group UART_Register_Masks */ |
| |
| |
| /* UART - Peripheral instance base addresses */ |
| /** Peripheral UART1 base address */ |
| #define UART1_BASE (0x30860000u) |
| /** Peripheral UART1 base pointer */ |
| #define UART1 ((UART_Type *)UART1_BASE) |
| /** Peripheral UART2 base address */ |
| #define UART2_BASE (0x30890000u) |
| /** Peripheral UART2 base pointer */ |
| #define UART2 ((UART_Type *)UART2_BASE) |
| /** Peripheral UART3 base address */ |
| #define UART3_BASE (0x30880000u) |
| /** Peripheral UART3 base pointer */ |
| #define UART3 ((UART_Type *)UART3_BASE) |
| /** Peripheral UART4 base address */ |
| #define UART4_BASE (0x30A60000u) |
| /** Peripheral UART4 base pointer */ |
| #define UART4 ((UART_Type *)UART4_BASE) |
| /** Array initializer of UART peripheral base addresses */ |
| #define UART_BASE_ADDRS { 0u, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE } |
| /** Array initializer of UART peripheral base pointers */ |
| #define UART_BASE_PTRS { (UART_Type *)0u, UART1, UART2, UART3, UART4 } |
| /** Interrupt vectors for the UART peripheral type */ |
| #define UART_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn, UART3_IRQn, UART4_IRQn } |
| |
| /*! |
| * @} |
| */ /* end of group UART_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- USDHC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** USDHC - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ |
| __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ |
| __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ |
| __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ |
| __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ |
| __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ |
| __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ |
| __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ |
| __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ |
| __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ |
| __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ |
| __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ |
| __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ |
| __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ |
| __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ |
| __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ |
| __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ |
| __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ |
| __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ |
| uint8_t RESERVED_0[4]; |
| __O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ |
| __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status Register, offset: 0x54 */ |
| __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ |
| uint8_t RESERVED_1[4]; |
| __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */ |
| __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */ |
| __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ |
| uint8_t RESERVED_2[4]; |
| __IO uint32_t STROBE_DLL_CTRL; /**< Strobe DLL Control, offset: 0x70 */ |
| __I uint32_t STROBE_DLL_STATUS; /**< Strobe DLL Status, offset: 0x74 */ |
| uint8_t RESERVED_3[72]; |
| __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ |
| __IO uint32_t MMC_BOOT; /**< MMC Boot Register, offset: 0xC4 */ |
| __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ |
| __IO uint32_t TUNING_CTRL; /**< Tuning Control Register, offset: 0xCC */ |
| } USDHC_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- USDHC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup USDHC_Register_Masks USDHC Register Masks |
| * @{ |
| */ |
| |
| /*! @name DS_ADDR - DMA System Address */ |
| /*! @{ */ |
| #define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFCU) |
| #define USDHC_DS_ADDR_DS_ADDR_SHIFT (2U) |
| #define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name BLK_ATT - Block Attributes */ |
| /*! @{ */ |
| #define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) |
| #define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) |
| /*! BLKSIZE |
| * 0b0000000001000..4096 Bytes |
| * 0b0001100100000..2048 Bytes |
| * 0b0000011001000..512 Bytes |
| * 0b0000000000100..4 Bytes |
| * 0b0000000000011..3 Bytes |
| * 0b0000000000010..2 Bytes |
| * 0b0000000000001..1 Byte |
| * 0b0000000000000..No data transfer |
| */ |
| #define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) |
| #define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) |
| #define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) |
| /*! BLKCNT |
| * 0b0000000000000010..2 blocks |
| * 0b0000000000000001..1 block |
| * 0b0000000000000000..Stop Count |
| */ |
| #define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) |
| /*! @} */ |
| |
| /*! @name CMD_ARG - Command Argument */ |
| /*! @{ */ |
| #define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) |
| #define USDHC_CMD_ARG_CMDARG_SHIFT (0U) |
| #define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) |
| /*! @} */ |
| |
| /*! @name CMD_XFR_TYP - Command Transfer Type */ |
| /*! @{ */ |
| #define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) |
| #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) |
| /*! RSPTYP - Response Type Select |
| * 0b00..No Response |
| * 0b01..Response Length 136 |
| * 0b10..Response Length 48 |
| * 0b11..Response Length 48, check Busy after response |
| */ |
| #define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) |
| #define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) |
| #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) |
| /*! CCCEN - Command CRC Check Enable |
| * 0b1..Enable |
| * 0b0..Disable |
| */ |
| #define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) |
| #define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) |
| #define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) |
| /*! CICEN - Command Index Check Enable |
| * 0b1..Enable |
| * 0b0..Disable |
| */ |
| #define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) |
| #define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) |
| #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) |
| /*! DPSEL - Data Present Select |
| * 0b1..Data Present |
| * 0b0..No Data Present |
| */ |
| #define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) |
| #define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) |
| #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) |
| /*! CMDTYP - Command Type |
| * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR |
| * 0b10..Resume CMD52 for writing Function Select in CCCR |
| * 0b01..Suspend CMD52 for writing Bus Suspend in CCCR |
| * 0b00..Normal Other commands |
| */ |
| #define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) |
| #define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) |
| #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) |
| #define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) |
| /*! @} */ |
| |
| /*! @name CMD_RSP0 - Command Response0 */ |
| /*! @{ */ |
| #define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) |
| #define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) |
| #define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) |
| /*! @} */ |
| |
| /*! @name CMD_RSP1 - Command Response1 */ |
| /*! @{ */ |
| #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) |
| #define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) |
| #define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) |
| /*! @} */ |
| |
| /*! @name CMD_RSP2 - Command Response2 */ |
| /*! @{ */ |
| #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) |
| #define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) |
| #define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) |
| /*! @} */ |
| |
| /*! @name CMD_RSP3 - Command Response3 */ |
| /*! @{ */ |
| #define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) |
| #define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) |
| #define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) |
| /*! @} */ |
| |
| /*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ |
| /*! @{ */ |
| #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) |
| #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) |
| #define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) |
| /*! @} */ |
| |
| /*! @name PRES_STATE - Present State */ |
| /*! @{ */ |
| #define USDHC_PRES_STATE_CIHB_MASK (0x1U) |
| #define USDHC_PRES_STATE_CIHB_SHIFT (0U) |
| /*! CIHB - Command Inhibit (CMD) |
| * 0b1..Cannot issue command |
| * 0b0..Can issue command using only CMD line |
| */ |
| #define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) |
| #define USDHC_PRES_STATE_CDIHB_MASK (0x2U) |
| #define USDHC_PRES_STATE_CDIHB_SHIFT (1U) |
| /*! CDIHB - Command Inhibit (DATA) |
| * 0b1..Cannot issue command which uses the DATA line |
| * 0b0..Can issue command which uses the DATA line |
| */ |
| #define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) |
| #define USDHC_PRES_STATE_DLA_MASK (0x4U) |
| #define USDHC_PRES_STATE_DLA_SHIFT (2U) |
| /*! DLA - Data Line Active |
| * 0b1..DATA Line Active |
| * 0b0..DATA Line Inactive |
| */ |
| #define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) |
| #define USDHC_PRES_STATE_SDSTB_MASK (0x8U) |
| #define USDHC_PRES_STATE_SDSTB_SHIFT (3U) |
| /*! SDSTB - SD Clock Stable |
| * 0b1..Clock is stable. |
| * 0b0..Clock is changing frequency and not stable. |
| */ |
| #define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) |
| #define USDHC_PRES_STATE_IPGOFF_MASK (0x10U) |
| #define USDHC_PRES_STATE_IPGOFF_SHIFT (4U) |
| /*! IPGOFF - IPG_CLK Gated Off Internally |
| * 0b1..IPG_CLK is gated off. |
| * 0b0..IPG_CLK is active. |
| */ |
| #define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK) |
| #define USDHC_PRES_STATE_HCKOFF_MASK (0x20U) |
| #define USDHC_PRES_STATE_HCKOFF_SHIFT (5U) |
| /*! HCKOFF - HCLK Gated Off Internally |
| * 0b1..HCLK is gated off. |
| * 0b0..HCLK is active. |
| */ |
| #define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK) |
| #define USDHC_PRES_STATE_PEROFF_MASK (0x40U) |
| #define USDHC_PRES_STATE_PEROFF_SHIFT (6U) |
| /*! PEROFF - IPG_PERCLK Gated Off Internally |
| * 0b1..IPG_PERCLK is gated off. |
| * 0b0..IPG_PERCLK is active. |
| */ |
| #define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK) |
| #define USDHC_PRES_STATE_SDOFF_MASK (0x80U) |
| #define USDHC_PRES_STATE_SDOFF_SHIFT (7U) |
| /*! SDOFF - SD Clock Gated Off Internally |
| * 0b1..SD Clock is gated off. |
| * 0b0..SD Clock is active. |
| */ |
| #define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK) |
| #define USDHC_PRES_STATE_WTA_MASK (0x100U) |
| #define USDHC_PRES_STATE_WTA_SHIFT (8U) |
| /*! WTA - Write Transfer Active |
| * 0b1..Transferring data |
| * 0b0..No valid data |
| */ |
| #define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) |
| #define USDHC_PRES_STATE_RTA_MASK (0x200U) |
| #define USDHC_PRES_STATE_RTA_SHIFT (9U) |
| /*! RTA - Read Transfer Active |
| * 0b1..Transferring data |
| * 0b0..No valid data |
| */ |
| #define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) |
| #define USDHC_PRES_STATE_BWEN_MASK (0x400U) |
| #define USDHC_PRES_STATE_BWEN_SHIFT (10U) |
| /*! BWEN - Buffer Write Enable |
| * 0b1..Write enable |
| * 0b0..Write disable |
| */ |
| #define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) |
| #define USDHC_PRES_STATE_BREN_MASK (0x800U) |
| #define USDHC_PRES_STATE_BREN_SHIFT (11U) |
| /*! BREN - Buffer Read Enable |
| * 0b1..Read enable |
| * 0b0..Read disable |
| */ |
| #define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) |
| #define USDHC_PRES_STATE_RTR_MASK (0x1000U) |
| #define USDHC_PRES_STATE_RTR_SHIFT (12U) |
| /*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode) |
| * 0b1..Sampling clock needs re-tuning |
| * 0b0..Fixed or well tuned sampling clock |
| */ |
| #define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) |
| #define USDHC_PRES_STATE_TSCD_MASK (0x8000U) |
| #define USDHC_PRES_STATE_TSCD_SHIFT (15U) |
| /*! TSCD - Tape Select Change Done |
| * 0b1..Delay cell select change is finished. |
| * 0b0..Delay cell select change is not finished. |
| */ |
| #define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) |
| #define USDHC_PRES_STATE_CINST_MASK (0x10000U) |
| #define USDHC_PRES_STATE_CINST_SHIFT (16U) |
| /*! CINST - Card Inserted |
| * 0b1..Card Inserted |
| * 0b0..Power on Reset or No Card |
| */ |
| #define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) |
| #define USDHC_PRES_STATE_CDPL_MASK (0x40000U) |
| #define USDHC_PRES_STATE_CDPL_SHIFT (18U) |
| /*! CDPL - Card Detect Pin Level |
| * 0b1..Card present (CD_B = 0) |
| * 0b0..No card present (CD_B = 1) |
| */ |
| #define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) |
| #define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) |
| #define USDHC_PRES_STATE_WPSPL_SHIFT (19U) |
| /*! WPSPL - Write Protect Switch Pin Level |
| * 0b1..Write enabled (WP = 0) |
| * 0b0..Write protected (WP = 1) |
| */ |
| #define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) |
| #define USDHC_PRES_STATE_CLSL_MASK (0x800000U) |
| #define USDHC_PRES_STATE_CLSL_SHIFT (23U) |
| #define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) |
| #define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) |
| #define USDHC_PRES_STATE_DLSL_SHIFT (24U) |
| #define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) |
| /*! @} */ |
| |
| /*! @name PROT_CTRL - Protocol Control */ |
| /*! @{ */ |
| #define USDHC_PROT_CTRL_LCTL_MASK (0x1U) |
| #define USDHC_PROT_CTRL_LCTL_SHIFT (0U) |
| /*! LCTL - LED Control |
| * 0b1..LED on |
| * 0b0..LED off |
| */ |
| #define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK) |
| #define USDHC_PROT_CTRL_DTW_MASK (0x6U) |
| #define USDHC_PROT_CTRL_DTW_SHIFT (1U) |
| /*! DTW - Data Transfer Width |
| * 0b10..8-bit mode |
| * 0b01..4-bit mode |
| * 0b00..1-bit mode |
| * 0b11..Reserved |
| */ |
| #define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) |
| #define USDHC_PROT_CTRL_D3CD_MASK (0x8U) |
| #define USDHC_PROT_CTRL_D3CD_SHIFT (3U) |
| /*! D3CD - DATA3 as Card Detection Pin |
| * 0b1..DATA3 as Card Detection Pin |
| * 0b0..DATA3 does not monitor Card Insertion |
| */ |
| #define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) |
| #define USDHC_PROT_CTRL_EMODE_MASK (0x30U) |
| #define USDHC_PROT_CTRL_EMODE_SHIFT (4U) |
| /*! EMODE - Endian Mode |
| * 0b00..Big Endian Mode |
| * 0b01..Half Word Big Endian Mode |
| * 0b10..Little Endian Mode |
| * 0b11..Reserved |
| */ |
| #define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) |
| #define USDHC_PROT_CTRL_CDTL_MASK (0x40U) |
| #define USDHC_PROT_CTRL_CDTL_SHIFT (6U) |
| /*! CDTL - Card Detect Test Level |
| * 0b1..Card Detect Test Level is 1, card inserted |
| * 0b0..Card Detect Test Level is 0, no card inserted |
| */ |
| #define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK) |
| #define USDHC_PROT_CTRL_CDSS_MASK (0x80U) |
| #define USDHC_PROT_CTRL_CDSS_SHIFT (7U) |
| /*! CDSS - Card Detect Signal Selection |
| * 0b1..Card Detection Test Level is selected (for test purpose). |
| * 0b0..Card Detection Level is selected (for normal purpose). |
| */ |
| #define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK) |
| #define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) |
| #define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) |
| /*! DMASEL - DMA Select |
| * 0b00..No DMA or Simple DMA is selected |
| * 0b01..ADMA1 is selected |
| * 0b10..ADMA2 is selected |
| * 0b11..reserved |
| */ |
| #define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) |
| #define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) |
| #define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) |
| /*! SABGREQ - Stop At Block Gap Request |
| * 0b1..Stop |
| * 0b0..Transfer |
| */ |
| #define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) |
| #define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) |
| #define USDHC_PROT_CTRL_CREQ_SHIFT (17U) |
| /*! CREQ - Continue Request |
| * 0b1..Restart |
| * 0b0..No effect |
| */ |
| #define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) |
| #define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) |
| #define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) |
| /*! RWCTL - Read Wait Control |
| * 0b1..Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set |
| * 0b0..Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set |
| */ |
| #define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) |
| #define USDHC_PROT_CTRL_IABG_MASK (0x80000U) |
| #define USDHC_PROT_CTRL_IABG_SHIFT (19U) |
| /*! IABG - Interrupt At Block Gap |
| * 0b1..Enabled |
| * 0b0..Disabled |
| */ |
| #define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) |
| #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) |
| #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) |
| #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) |
| #define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) |
| #define USDHC_PROT_CTRL_WECINT_SHIFT (24U) |
| /*! WECINT - Wakeup Event Enable On Card Interrupt |
| * 0b1..Enable |
| * 0b0..Disable |
| */ |
| #define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) |
| #define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) |
| #define USDHC_PROT_CTRL_WECINS_SHIFT (25U) |
| /*! WECINS - Wakeup Event Enable On SD Card Insertion |
| * 0b1..Enable |
| * 0b0..Disable |
| */ |
| #define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) |
| #define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) |
| #define USDHC_PROT_CTRL_WECRM_SHIFT (26U) |
| /*! WECRM - Wakeup Event Enable On SD Card Removal |
| * 0b1..Enable |
| * 0b0..Disable |
| */ |
| #define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) |
| #define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U) |
| #define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U) |
| /*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP |
| * 0bxx1..Burst length is enabled for INCR |
| * 0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16 |
| * 0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP |
| */ |
| #define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK) |
| #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) |
| #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) |
| /*! NON_EXACT_BLK_RD |
| * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. |
| * 0b0..The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read. |
| */ |
| #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) |
| /*! @} */ |
| |
| /*! @name SYS_CTRL - System Control */ |
| /*! @{ */ |
| #define USDHC_SYS_CTRL_DVS_MASK (0xF0U) |
| #define USDHC_SYS_CTRL_DVS_SHIFT (4U) |
| /*! DVS - Divisor |
| * 0b0000..Divide-by-1 |
| * 0b0001..Divide-by-2 |
| * 0b1110..Divide-by-15 |
| * 0b1111..Divide-by-16 |
| */ |
| #define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) |
| #define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) |
| #define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) |
| #define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) |
| #define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) |
| #define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) |
| /*! DTOCV - Data Timeout Counter Value |
| * 0b1111..SDCLK x 2 29 |
| * 0b1110..SDCLK x 2 28 |
| * 0b0001..SDCLK x 2 15 |
| * 0b0000..SDCLK x 2 14 |
| */ |
| #define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) |
| #define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) |
| #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) |
| #define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) |
| #define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) |
| #define USDHC_SYS_CTRL_RSTA_SHIFT (24U) |
| /*! RSTA - Software Reset For ALL |
| * 0b1..Reset |
| * 0b0..No Reset |
| */ |
| #define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) |
| #define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) |
| #define USDHC_SYS_CTRL_RSTC_SHIFT (25U) |
| /*! RSTC - Software Reset For CMD Line |
| * 0b1..Reset |
| * 0b0..No Reset |
| */ |
| #define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) |
| #define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) |
| #define USDHC_SYS_CTRL_RSTD_SHIFT (26U) |
| /*! RSTD - Software Reset For DATA Line |
| * 0b1..Reset |
| * 0b0..No Reset |
| */ |
| #define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) |
| #define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) |
| #define USDHC_SYS_CTRL_INITA_SHIFT (27U) |
| #define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) |
| #define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) |
| #define USDHC_SYS_CTRL_RSTT_SHIFT (28U) |
| #define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) |
| /*! @} */ |
| |
| /*! @name INT_STATUS - Interrupt Status */ |
| /*! @{ */ |
| #define USDHC_INT_STATUS_CC_MASK (0x1U) |
| #define USDHC_INT_STATUS_CC_SHIFT (0U) |
| /*! CC - Command Complete |
| * 0b1..Command complete |
| * 0b0..Command not complete |
| */ |
| #define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) |
| #define USDHC_INT_STATUS_TC_MASK (0x2U) |
| #define USDHC_INT_STATUS_TC_SHIFT (1U) |
| /*! TC - Transfer Complete |
| * 0b1..Transfer complete |
| * 0b0..Transfer not complete |
| */ |
| #define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) |
| #define USDHC_INT_STATUS_BGE_MASK (0x4U) |
| #define USDHC_INT_STATUS_BGE_SHIFT (2U) |
| /*! BGE - Block Gap Event |
| * 0b1..Transaction stopped at block gap |
| * 0b0..No block gap event |
| */ |
| #define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) |
| #define USDHC_INT_STATUS_DINT_MASK (0x8U) |
| #define USDHC_INT_STATUS_DINT_SHIFT (3U) |
| /*! DINT - DMA Interrupt |
| * 0b1..DMA Interrupt is generated |
| * 0b0..No DMA Interrupt |
| */ |
| #define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) |
| #define USDHC_INT_STATUS_BWR_MASK (0x10U) |
| #define USDHC_INT_STATUS_BWR_SHIFT (4U) |
| /*! BWR - Buffer Write Ready |
| * 0b1..Ready to write buffer: |
| * 0b0..Not ready to write buffer |
| */ |
| #define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) |
| #define USDHC_INT_STATUS_BRR_MASK (0x20U) |
| #define USDHC_INT_STATUS_BRR_SHIFT (5U) |
| /*! BRR - Buffer Read Ready |
| * 0b1..Ready to read buffer |
| * 0b0..Not ready to read buffer |
| */ |
| #define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) |
| #define USDHC_INT_STATUS_CINS_MASK (0x40U) |
| #define USDHC_INT_STATUS_CINS_SHIFT (6U) |
| /*! CINS - Card Insertion |
| * 0b1..Card inserted |
| * 0b0..Card state unstable or removed |
| */ |
| #define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) |
| #define USDHC_INT_STATUS_CRM_MASK (0x80U) |
| #define USDHC_INT_STATUS_CRM_SHIFT (7U) |
| /*! CRM - Card Removal |
| * 0b1..Card removed |
| * 0b0..Card state unstable or inserted |
| */ |
| #define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) |
| #define USDHC_INT_STATUS_CINT_MASK (0x100U) |
| #define USDHC_INT_STATUS_CINT_SHIFT (8U) |
| /*! CINT - Card Interrupt |
| * 0b1..Generate Card Interrupt |
| * 0b0..No Card Interrupt |
| */ |
| #define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) |
| #define USDHC_INT_STATUS_RTE_MASK (0x1000U) |
| #define USDHC_INT_STATUS_RTE_SHIFT (12U) |
| /*! RTE - Re-Tuning Event: (only for SD3.0 SDR104 mode) |
| * 0b1..Re-Tuning should be performed |
| * 0b0..Re-Tuning is not required |
| */ |
| #define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) |
| #define USDHC_INT_STATUS_TP_MASK (0x4000U) |
| #define USDHC_INT_STATUS_TP_SHIFT (14U) |
| #define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) |
| #define USDHC_INT_STATUS_CTOE_MASK (0x10000U) |
| #define USDHC_INT_STATUS_CTOE_SHIFT (16U) |
| /*! CTOE - Command Timeout Error |
| * 0b1..Time out |
| * 0b0..No Error |
| */ |
| #define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) |
| #define USDHC_INT_STATUS_CCE_MASK (0x20000U) |
| #define USDHC_INT_STATUS_CCE_SHIFT (17U) |
| /*! CCE - Command CRC Error |
| * 0b1..CRC Error Generated. |
| * 0b0..No Error |
| */ |
| #define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) |
| #define USDHC_INT_STATUS_CEBE_MASK (0x40000U) |
| #define USDHC_INT_STATUS_CEBE_SHIFT (18U) |
| /*! CEBE - Command End Bit Error |
| * 0b1..End Bit Error Generated |
| * 0b0..No Error |
| */ |
| #define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) |
| #define USDHC_INT_STATUS_CIE_MASK (0x80000U) |
| #define USDHC_INT_STATUS_CIE_SHIFT (19U) |
| /*! CIE - Command Index Error |
| * 0b1..Error |
| * 0b0..No Error |
| */ |
| #define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) |
| #define USDHC_INT_STATUS_DTOE_MASK (0x100000U) |
| #define USDHC_INT_STATUS_DTOE_SHIFT (20U) |
| /*! DTOE - Data Timeout Error |
| * 0b1..Time out |
| * 0b0..No Error |
| */ |
| #define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) |
| #define USDHC_INT_STATUS_DCE_MASK (0x200000U) |
| #define USDHC_INT_STATUS_DCE_SHIFT (21U) |
| /*! DCE - Data CRC Error |
| * 0b1..Error |
| * 0b0..No Error |
| */ |
| #define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) |
| #define USDHC_INT_STATUS_DEBE_MASK (0x400000U) |
| #define USDHC_INT_STATUS_DEBE_SHIFT (22U) |
| /*! DEBE - Data End Bit Error |
| * 0b1..Error |
| * 0b0..No Error |
| */ |
| #define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) |
| #define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) |
| #define USDHC_INT_STATUS_AC12E_SHIFT (24U) |
| /*! AC12E - Auto CMD12 Error |
| * 0b1..Error |
| * 0b0..No Error |
| */ |
| #define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) |
| #define USDHC_INT_STATUS_TNE_MASK (0x4000000U) |
| #define USDHC_INT_STATUS_TNE_SHIFT (26U) |
| #define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) |
| #define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) |
| #define USDHC_INT_STATUS_DMAE_SHIFT (28U) |
| /*! DMAE - DMA Error |
| * 0b1..Error |
| * 0b0..No Error |
| */ |
| #define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) |
| /*! @} */ |
| |
| /*! @name INT_STATUS_EN - Interrupt Status Enable */ |
| /*! @{ */ |
| #define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) |
| #define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) |
| /*! CCSEN - Command Complete Status Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) |
| #define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) |
| #define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) |
| /*! TCSEN - Transfer Complete Status Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) |
| #define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) |
| #define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) |
| /*! BGESEN - Block Gap Event Status Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) |
| #define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) |
| #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) |
| /*! DINTSEN - DMA Interrupt Status Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) |
| #define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) |
| #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) |
| /*! BWRSEN - Buffer Write Ready Status Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) |
| #define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) |
| #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) |
| /*! BRRSEN - Buffer Read Ready Status Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) |
| #define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) |
| #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) |
| /*! CINSSEN - Card Insertion Status Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) |
| #define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) |
| #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) |
| /*! CRMSEN - Card Removal Status Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) |
| #define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) |
| #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) |
| /*! CINTSEN - Card Interrupt Status Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) |
| #define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) |
| #define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) |
| /*! RTESEN - Re-Tuning Event Status Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) |
| #define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U) |
| #define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U) |
| /*! TPSEN - Tuning Pass Status Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) |
| #define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) |
| #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) |
| /*! CTOESEN - Command Timeout Error Status Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) |
| #define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) |
| #define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) |
| /*! CCESEN - Command CRC Error Status Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) |
| #define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) |
| #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) |
| /*! CEBESEN - Command End Bit Error Status Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) |
| #define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) |
| #define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) |
| /*! CIESEN - Command Index Error Status Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) |
| #define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) |
| #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) |
| /*! DTOESEN - Data Timeout Error Status Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) |
| #define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) |
| #define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) |
| /*! DCESEN - Data CRC Error Status Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) |
| #define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) |
| #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) |
| /*! DEBESEN - Data End Bit Error Status Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) |
| #define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) |
| #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) |
| /*! AC12ESEN - Auto CMD12 Error Status Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) |
| #define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) |
| #define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) |
| /*! TNESEN - Tuning Error Status Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) |
| #define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) |
| #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) |
| /*! DMAESEN - DMA Error Status Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) |
| /*! @} */ |
| |
| /*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ |
| /*! @{ */ |
| #define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) |
| #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) |
| /*! CCIEN - Command Complete Interrupt Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) |
| #define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) |
| #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) |
| /*! TCIEN - Transfer Complete Interrupt Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) |
| #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) |
| #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) |
| /*! BGEIEN - Block Gap Event Interrupt Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) |
| #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) |
| #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) |
| /*! DINTIEN - DMA Interrupt Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) |
| #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) |
| #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) |
| /*! BWRIEN - Buffer Write Ready Interrupt Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) |
| #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) |
| #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) |
| /*! BRRIEN - Buffer Read Ready Interrupt Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) |
| #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) |
| #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) |
| /*! CINSIEN - Card Insertion Interrupt Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) |
| #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) |
| #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) |
| /*! CRMIEN - Card Removal Interrupt Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) |
| #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) |
| #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) |
| /*! CINTIEN - Card Interrupt Interrupt Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) |
| #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) |
| #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) |
| /*! RTEIEN - Re-Tuning Event Interrupt Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) |
| #define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U) |
| #define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U) |
| /*! TPIEN - Tuning Pass Interrupt Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) |
| #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) |
| #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) |
| /*! CTOEIEN - Command Timeout Error Interrupt Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) |
| #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) |
| #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) |
| /*! CCEIEN - Command CRC Error Interrupt Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) |
| #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) |
| #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) |
| /*! CEBEIEN - Command End Bit Error Interrupt Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) |
| #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) |
| #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) |
| /*! CIEIEN - Command Index Error Interrupt Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) |
| #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) |
| #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) |
| /*! DTOEIEN - Data Timeout Error Interrupt Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) |
| #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) |
| #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) |
| /*! DCEIEN - Data CRC Error Interrupt Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) |
| #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) |
| #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) |
| /*! DEBEIEN - Data End Bit Error Interrupt Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) |
| #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) |
| #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) |
| /*! AC12EIEN - Auto CMD12 Error Interrupt Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) |
| #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) |
| #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) |
| /*! TNEIEN - Tuning Error Interrupt Enable |
| * 0b1..Enabled |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) |
| #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) |
| #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) |
| /*! DMAEIEN - DMA Error Interrupt Enable |
| * 0b1..Enable |
| * 0b0..Masked |
| */ |
| #define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) |
| /*! @} */ |
| |
| /*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ |
| /*! @{ */ |
| #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) |
| #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) |
| /*! AC12NE - Auto CMD12 Not Executed |
| * 0b1..Not executed |
| * 0b0..Executed |
| */ |
| #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) |
| #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) |
| #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) |
| /*! AC12TOE - Auto CMD12 / 23 Timeout Error |
| * 0b1..Time out |
| * 0b0..No error |
| */ |
| #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) |
| #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U) |
| #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U) |
| /*! AC12EBE - Auto CMD12 / 23 End Bit Error |
| * 0b1..End Bit Error Generated |
| * 0b0..No error |
| */ |
| #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) |
| #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U) |
| #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U) |
| /*! AC12CE - Auto CMD12 / 23 CRC Error |
| * 0b1..CRC Error Met in Auto CMD12/23 Response |
| * 0b0..No CRC error |
| */ |
| #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) |
| #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) |
| #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) |
| /*! AC12IE - Auto CMD12 / 23 Index Error |
| * 0b1..Error, the CMD index in response is not CMD12/23 |
| * 0b0..No error |
| */ |
| #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) |
| #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) |
| #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) |
| /*! CNIBAC12E - Command Not Issued By Auto CMD12 Error |
| * 0b1..Not Issued |
| * 0b0..No error |
| */ |
| #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) |
| #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) |
| #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) |
| #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) |
| #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) |
| #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) |
| /*! SMP_CLK_SEL - Sample Clock Select |
| * 0b1..Tuned clock is used to sample data |
| * 0b0..Fixed clock is used to sample data |
| */ |
| #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name HOST_CTRL_CAP - Host Controller Capabilities */ |
| /*! @{ */ |
| #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) |
| #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) |
| #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) |
| #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U) |
| #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U) |
| #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK) |
| #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) |
| #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) |
| #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) |
| #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U) |
| #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U) |
| #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK) |
| #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) |
| #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) |
| /*! USE_TUNING_SDR50 - Use Tuning for SDR50 |
| * 0b1..SDR50 requires tuning |
| * 0b0..SDR does not require tuning |
| */ |
| #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) |
| #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U) |
| #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U) |
| /*! RETUNING_MODE - Retuning Mode |
| * 0b00..Mode 1 |
| * 0b01..Mode 2 |
| * 0b10..Mode 3 |
| * 0b11..Reserved |
| */ |
| #define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK) |
| #define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) |
| #define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) |
| /*! MBL - Max Block Length |
| * 0b000..512 bytes |
| * 0b001..1024 bytes |
| * 0b010..2048 bytes |
| * 0b011..4096 bytes |
| */ |
| #define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) |
| #define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) |
| #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) |
| /*! ADMAS - ADMA Support |
| * 0b1..Advanced DMA Supported |
| * 0b0..Advanced DMA Not supported |
| */ |
| #define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) |
| #define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) |
| #define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) |
| /*! HSS - High Speed Support |
| * 0b1..High Speed Supported |
| * 0b0..High Speed Not Supported |
| */ |
| #define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) |
| #define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) |
| #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) |
| /*! DMAS - DMA Support |
| * 0b1..DMA Supported |
| * 0b0..DMA not supported |
| */ |
| #define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) |
| #define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) |
| #define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) |
| /*! SRS - Suspend / Resume Support |
| * 0b1..Supported |
| * 0b0..Not supported |
| */ |
| #define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) |
| #define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) |
| #define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) |
| /*! VS33 - Voltage Support 3.3V |
| * 0b1..3.3V supported |
| * 0b0..3.3V not supported |
| */ |
| #define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) |
| #define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) |
| #define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) |
| /*! VS30 - Voltage Support 3.0 V |
| * 0b1..3.0V supported |
| * 0b0..3.0V not supported |
| */ |
| #define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) |
| #define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) |
| #define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) |
| /*! VS18 - Voltage Support 1.8 V |
| * 0b1..1.8V supported |
| * 0b0..1.8V not supported |
| */ |
| #define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) |
| /*! @} */ |
| |
| /*! @name WTMK_LVL - Watermark Level */ |
| /*! @{ */ |
| #define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) |
| #define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) |
| #define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) |
| #define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U) |
| #define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U) |
| #define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK) |
| #define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) |
| #define USDHC_WTMK_LVL_WR_WML_SHIFT (16U) |
| #define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK) |
| #define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U) |
| #define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U) |
| #define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK) |
| /*! @} */ |
| |
| /*! @name MIX_CTRL - Mixer Control */ |
| /*! @{ */ |
| #define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) |
| #define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) |
| /*! DMAEN - DMA Enable |
| * 0b1..Enable |
| * 0b0..Disable |
| */ |
| #define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) |
| #define USDHC_MIX_CTRL_BCEN_MASK (0x2U) |
| #define USDHC_MIX_CTRL_BCEN_SHIFT (1U) |
| /*! BCEN - Block Count Enable |
| * 0b1..Enable |
| * 0b0..Disable |
| */ |
| #define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) |
| #define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) |
| #define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) |
| /*! AC12EN - Auto CMD12 Enable |
| * 0b1..Enable |
| * 0b0..Disable |
| */ |
| #define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) |
| #define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) |
| #define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) |
| #define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) |
| #define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) |
| #define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) |
| /*! DTDSEL - Data Transfer Direction Select |
| * 0b1..Read (Card to Host) |
| * 0b0..Write (Host to Card) |
| */ |
| #define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) |
| #define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) |
| #define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) |
| /*! MSBSEL - Multi / Single Block Select |
| * 0b1..Multiple Blocks |
| * 0b0..Single Block |
| */ |
| #define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) |
| #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) |
| #define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) |
| #define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) |
| #define USDHC_MIX_CTRL_AC23EN_MASK (0x80U) |
| #define USDHC_MIX_CTRL_AC23EN_SHIFT (7U) |
| #define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) |
| #define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) |
| #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) |
| /*! EXE_TUNE - Execute Tuning: (Only used for SD3.0, SDR104 mode) |
| * 0b1..Execute Tuning |
| * 0b0..Not Tuned or Tuning Completed |
| */ |
| #define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) |
| #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) |
| #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) |
| /*! SMP_CLK_SEL |
| * 0b1..Tuned clock is used to sample data / cmd |
| * 0b0..Fixed clock is used to sample data / cmd |
| */ |
| #define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) |
| #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) |
| #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) |
| /*! AUTO_TUNE_EN - Auto Tuning Enable (Only used for SD3.0, SDR104 mode) |
| * 0b1..Enable auto tuning |
| * 0b0..Disable auto tuning |
| */ |
| #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) |
| #define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) |
| #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) |
| /*! FBCLK_SEL - Feedback Clock Source Selection (Only used for SD3.0, SDR104 mode) |
| * 0b1..Feedback clock comes from the ipp_card_clk_out |
| * 0b0..Feedback clock comes from the loopback CLK |
| */ |
| #define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) |
| #define USDHC_MIX_CTRL_HS400_MODE_MASK (0x4000000U) |
| #define USDHC_MIX_CTRL_HS400_MODE_SHIFT (26U) |
| #define USDHC_MIX_CTRL_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK) |
| /*! @} */ |
| |
| /*! @name FORCE_EVENT - Force Event */ |
| /*! @{ */ |
| #define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) |
| #define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) |
| #define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) |
| #define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) |
| #define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) |
| #define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) |
| #define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) |
| #define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) |
| #define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) |
| #define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) |
| #define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) |
| #define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) |
| #define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) |
| #define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) |
| #define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) |
| #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) |
| #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) |
| #define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) |
| #define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) |
| #define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) |
| #define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) |
| #define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) |
| #define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) |
| #define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) |
| #define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) |
| #define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) |
| #define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) |
| #define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) |
| #define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) |
| #define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) |
| #define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) |
| #define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) |
| #define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) |
| #define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) |
| #define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) |
| #define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) |
| #define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) |
| #define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) |
| #define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) |
| #define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) |
| #define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) |
| #define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) |
| #define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U) |
| #define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U) |
| #define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK) |
| #define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) |
| #define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) |
| #define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) |
| #define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) |
| #define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) |
| #define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) |
| /*! @} */ |
| |
| /*! @name ADMA_ERR_STATUS - ADMA Error Status Register */ |
| /*! @{ */ |
| #define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) |
| #define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) |
| #define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) |
| #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) |
| #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) |
| /*! ADMALME - ADMA Length Mismatch Error |
| * 0b1..Error |
| * 0b0..No Error |
| */ |
| #define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) |
| #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) |
| #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) |
| /*! ADMADCE - ADMA Descritor Error |
| * 0b1..Error |
| * 0b0..No Error |
| */ |
| #define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) |
| /*! @} */ |
| |
| /*! @name ADMA_SYS_ADDR - ADMA System Address */ |
| /*! @{ */ |
| #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) |
| #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) |
| #define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name DLL_CTRL - DLL (Delay Line) Control */ |
| /*! @{ */ |
| #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) |
| #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) |
| #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) |
| #define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U) |
| #define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U) |
| #define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK) |
| #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) |
| #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) |
| #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK) |
| #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U) |
| #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U) |
| #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) |
| #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U) |
| #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U) |
| #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK) |
| #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) |
| #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) |
| #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK) |
| #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) |
| #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) |
| #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) |
| #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U) |
| #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U) |
| #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) |
| #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) |
| #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) |
| #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) |
| #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) |
| #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) |
| #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) |
| /*! @} */ |
| |
| /*! @name DLL_STATUS - DLL Status */ |
| /*! @{ */ |
| #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) |
| #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) |
| #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) |
| #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U) |
| #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U) |
| #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK) |
| #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU) |
| #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U) |
| #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) |
| #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) |
| #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) |
| #define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ |
| /*! @{ */ |
| #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) |
| #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) |
| /*! @} */ |
| |
| /*! @name STROBE_DLL_CTRL - Strobe DLL Control */ |
| /*! @{ */ |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x38U) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK (0x40U) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT (6U) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK (0x80U) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT (7U) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) |
| #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK) |
| /*! @} */ |
| |
| /*! @name STROBE_DLL_STATUS - Strobe DLL Status */ |
| /*! @{ */ |
| #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U) |
| #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U) |
| #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK) |
| #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U) |
| #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U) |
| #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK) |
| #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU) |
| #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U) |
| #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK) |
| #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U) |
| #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U) |
| #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK) |
| /*! @} */ |
| |
| /*! @name VEND_SPEC - Vendor Specific Register */ |
| /*! @{ */ |
| #define USDHC_VEND_SPEC_EXT_DMA_EN_MASK (0x1U) |
| #define USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT (0U) |
| /*! EXT_DMA_EN - External DMA Request Enable |
| * 0b0..In any scenario, uSDHC does not send out external DMA request. |
| * 0b1..When internal DMA is not active, the external DMA request will be sent out. |
| */ |
| #define USDHC_VEND_SPEC_EXT_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT)) & USDHC_VEND_SPEC_EXT_DMA_EN_MASK) |
| #define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) |
| #define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) |
| /*! VSELECT - Voltage Selection |
| * 0b1..Change the voltage to low voltage range, around 1.8 V |
| * 0b0..Change the voltage to high voltage range, around 3.0 V |
| */ |
| #define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) |
| #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U) |
| #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U) |
| /*! CONFLICT_CHK_EN - Conflict check enable. |
| * 0b0..Conflict check disable |
| * 0b1..Conflict check enable |
| */ |
| #define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK) |
| #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) |
| #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) |
| /*! AC12_WR_CHKBUSY_EN |
| * 0b0..Do not check busy after auto CMD12 for write data packet |
| * 0b1..Check busy after auto CMD12 for write data packet |
| */ |
| #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) |
| #define USDHC_VEND_SPEC_DAT3_CD_POL_MASK (0x10U) |
| #define USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT (4U) |
| /*! DAT3_CD_POL |
| * 0b0..Card detected when DATA3 is high. |
| * 0b1..Card detected when DATA3 is low. |
| */ |
| #define USDHC_VEND_SPEC_DAT3_CD_POL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT)) & USDHC_VEND_SPEC_DAT3_CD_POL_MASK) |
| #define USDHC_VEND_SPEC_CD_POL_MASK (0x20U) |
| #define USDHC_VEND_SPEC_CD_POL_SHIFT (5U) |
| /*! CD_POL |
| * 0b0..CD_B pin is low active. |
| * 0b1..CD_B pin is high active. |
| */ |
| #define USDHC_VEND_SPEC_CD_POL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CD_POL_SHIFT)) & USDHC_VEND_SPEC_CD_POL_MASK) |
| #define USDHC_VEND_SPEC_WP_POL_MASK (0x40U) |
| #define USDHC_VEND_SPEC_WP_POL_SHIFT (6U) |
| /*! WP_POL |
| * 0b0..WP pin is high active. |
| * 0b1..WP pin is low active. |
| */ |
| #define USDHC_VEND_SPEC_WP_POL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_WP_POL_SHIFT)) & USDHC_VEND_SPEC_WP_POL_MASK) |
| #define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK (0x80U) |
| #define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT (7U) |
| /*! CLKONJ_IN_ABORT |
| * 0b0..The CLK output is active when sending abort command while data is transmitting even if the internal FIFO is full (for read) or empty (for write). |
| * 0b1..The CLK output is inactive when sending abort command while data is transmitting if the internal FIFO is full (for read) or empty (for write). |
| */ |
| #define USDHC_VEND_SPEC_CLKONJ_IN_ABORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT)) & USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK) |
| #define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) |
| #define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) |
| /*! FRC_SDCLK_ON |
| * 0b0..CLK active or inactive is fully controlled by the hardware. |
| * 0b1..Force CLK active. |
| */ |
| #define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) |
| #define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK (0x800U) |
| #define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT (11U) |
| /*! IPG_CLK_SOFT_EN - IPG_CLK Software Enable |
| * 0b0..Gate off the IPG_CLK |
| * 0b1..Enable the IPG_CLK |
| */ |
| #define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK) |
| #define USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK (0x1000U) |
| #define USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT (12U) |
| /*! HCLK_SOFT_EN - AHB Clock Software Enable |
| * 0b0..Gate off the AHB clock. |
| * 0b1..Enable the AHB clock. |
| */ |
| #define USDHC_VEND_SPEC_HCLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK) |
| #define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK (0x2000U) |
| #define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT (13U) |
| /*! IPG_PERCLK_SOFT_EN - IPG_PERCLK Software Enable |
| * 0b0..Gate off the IPG_PERCLK |
| * 0b1..Enable the IPG_PERCLK |
| */ |
| #define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK) |
| #define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK (0x4000U) |
| #define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT (14U) |
| /*! CARD_CLK_SOFT_EN - Card Clock Software Enable |
| * 0b0..Gate off the sd_clk |
| * 0b1..Enable the sd_clk |
| */ |
| #define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK) |
| #define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) |
| #define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) |
| /*! CRC_CHK_DIS - CRC Check Disable |
| * 0b0..Check CRC16 for every read data packet and check CRC bits for every write data packet |
| * 0b1..Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet |
| */ |
| #define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) |
| #define USDHC_VEND_SPEC_INT_ST_VAL_MASK (0xFF0000U) |
| #define USDHC_VEND_SPEC_INT_ST_VAL_SHIFT (16U) |
| #define USDHC_VEND_SPEC_INT_ST_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_INT_ST_VAL_SHIFT)) & USDHC_VEND_SPEC_INT_ST_VAL_MASK) |
| #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) |
| #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) |
| /*! CMD_BYTE_EN |
| * 0b0..Disable |
| * 0b1..Enable |
| */ |
| #define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) |
| /*! @} */ |
| |
| /*! @name MMC_BOOT - MMC Boot Register */ |
| /*! @{ */ |
| #define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) |
| #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) |
| /*! DTOCV_ACK |
| * 0b0000..SDCLK x 2^13 |
| * 0b0001..SDCLK x 2^14 |
| * 0b0010..SDCLK x 2^15 |
| * 0b0011..SDCLK x 2^16 |
| * 0b0100..SDCLK x 2^17 |
| * 0b0101..SDCLK x 2^18 |
| * 0b0110..SDCLK x 2^19 |
| * 0b0111..SDCLK x 2^20 |
| * 0b1110..SDCLK x 2^27 |
| * 0b1111..SDCLK x 2^28 |
| */ |
| #define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) |
| #define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) |
| #define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) |
| /*! BOOT_ACK |
| * 0b0..No ack |
| * 0b1..Ack |
| */ |
| #define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) |
| #define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) |
| #define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) |
| /*! BOOT_MODE |
| * 0b0..Normal boot |
| * 0b1..Alternative boot |
| */ |
| #define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) |
| #define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) |
| #define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) |
| /*! BOOT_EN |
| * 0b0..Fast boot disable |
| * 0b1..Fast boot enable |
| */ |
| #define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) |
| #define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) |
| #define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) |
| #define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) |
| #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) |
| #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) |
| /*! DISABLE_TIME_OUT - Disable Time Out |
| * 0b0..Enable time out |
| * 0b1..Disable time out |
| */ |
| #define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) |
| #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) |
| #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) |
| #define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) |
| /*! @} */ |
| |
| /*! @name VEND_SPEC2 - Vendor Specific 2 Register */ |
| /*! @{ */ |
| #define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK (0x1U) |
| #define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT (0U) |
| /*! SDR104_TIMING_DIS |
| * 0b0..The timeout counter for Ncr changes to 80, Ncrc changes to 21. |
| * 0b1..The timeout counter for Ncr changes to 72, Ncrc changes to 15. |
| */ |
| #define USDHC_VEND_SPEC2_SDR104_TIMING_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK) |
| #define USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK (0x2U) |
| #define USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT (1U) |
| /*! SDR104_OE_DIS |
| * 0b0..Drive the CMD_OE / DATA_OE for one more clock cycle after the end bit. |
| * 0b1..Stop to drive the CMD_OE / DATA_OE at once after driving the end bit. |
| */ |
| #define USDHC_VEND_SPEC2_SDR104_OE_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK) |
| #define USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK (0x4U) |
| #define USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT (2U) |
| /*! SDR104_NSD_DIS |
| * 0b0..Enable the interrupt window 9 cycles later after the end of the I/O abort command (or CMD12) is sent. |
| * 0b1..Enable the interrupt window 5 cycles later after the end of the I/O abort command (or CMD12) is sent. |
| */ |
| #define USDHC_VEND_SPEC2_SDR104_NSD_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK) |
| #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) |
| #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) |
| /*! CARD_INT_D3_TEST - Card Interrupt Detection Test |
| * 0b0..Check the card interrupt only when DATA3 is high. |
| * 0b1..Check the card interrupt by ignoring the status of DATA3. |
| */ |
| #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) |
| #define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U) |
| #define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U) |
| /*! TUNING_8bit_EN |
| * 0b0..Tuning circuit only checks the DATA[3:0]. |
| * 0b1..Tuning circuit only checks the DATA0. |
| */ |
| #define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK) |
| #define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U) |
| #define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U) |
| #define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK) |
| #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) |
| #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) |
| /*! TUNING_CMD_EN |
| * 0b0..Auto tuning circuit does not check the CMD line. |
| * 0b1..Auto tuning circuit checks the CMD line. |
| */ |
| #define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) |
| #define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK (0x80U) |
| #define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT (7U) |
| /*! CARD_INT_AUTO_CLR_DIS |
| * 0b0..Card interrupt status bit (CINT) can be cleared when Card Interrupt status enable bit is 0. |
| * 0b1..Card interrupt status bit (CINT) can only be cleared by writting a 1 to CINT bit. |
| */ |
| #define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK) |
| #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U) |
| #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U) |
| #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK) |
| #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U) |
| #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U) |
| #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK) |
| /*! @} */ |
| |
| /*! @name TUNING_CTRL - Tuning Control Register */ |
| /*! @{ */ |
| #define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU) |
| #define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) |
| #define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) |
| #define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U) |
| #define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U) |
| #define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK) |
| #define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U) |
| #define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U) |
| #define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK) |
| #define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U) |
| #define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U) |
| #define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK) |
| #define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) |
| #define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) |
| #define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group USDHC_Register_Masks */ |
| |
| |
| /* USDHC - Peripheral instance base addresses */ |
| /** Peripheral uSDHC1 base address */ |
| #define uSDHC1_BASE (0x30B40000u) |
| /** Peripheral uSDHC1 base pointer */ |
| #define uSDHC1 ((USDHC_Type *)uSDHC1_BASE) |
| /** Peripheral uSDHC2 base address */ |
| #define uSDHC2_BASE (0x30B50000u) |
| /** Peripheral uSDHC2 base pointer */ |
| #define uSDHC2 ((USDHC_Type *)uSDHC2_BASE) |
| /** Array initializer of USDHC peripheral base addresses */ |
| #define USDHC_BASE_ADDRS { 0u, uSDHC1_BASE, uSDHC2_BASE } |
| /** Array initializer of USDHC peripheral base pointers */ |
| #define USDHC_BASE_PTRS { (USDHC_Type *)0u, uSDHC1, uSDHC2 } |
| /** Interrupt vectors for the USDHC peripheral type */ |
| #define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn } |
| |
| /*! |
| * @} |
| */ /* end of group USDHC_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- WDOG Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** WDOG - Register Layout Typedef */ |
| typedef struct { |
| __IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */ |
| __IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */ |
| __I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 */ |
| __IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */ |
| __IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */ |
| } WDOG_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- WDOG Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup WDOG_Register_Masks WDOG Register Masks |
| * @{ |
| */ |
| |
| /*! @name WCR - Watchdog Control Register */ |
| /*! @{ */ |
| #define WDOG_WCR_WDZST_MASK (0x1U) |
| #define WDOG_WCR_WDZST_SHIFT (0U) |
| /*! WDZST |
| * 0b0..Continue timer operation (Default). |
| * 0b1..Suspend the watchdog timer. |
| */ |
| #define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) |
| #define WDOG_WCR_WDBG_MASK (0x2U) |
| #define WDOG_WCR_WDBG_SHIFT (1U) |
| /*! WDBG |
| * 0b0..Continue WDOG timer operation (Default). |
| * 0b1..Suspend the watchdog timer. |
| */ |
| #define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) |
| #define WDOG_WCR_WDE_MASK (0x4U) |
| #define WDOG_WCR_WDE_SHIFT (2U) |
| /*! WDE |
| * 0b0..Disable the Watchdog (Default). |
| * 0b1..Enable the Watchdog. |
| */ |
| #define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) |
| #define WDOG_WCR_WDT_MASK (0x8U) |
| #define WDOG_WCR_WDT_SHIFT (3U) |
| /*! WDT |
| * 0b0..No effect on WDOG_B (Default). |
| * 0b1..Assert WDOG_B upon a Watchdog Time-out event. |
| */ |
| #define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) |
| #define WDOG_WCR_SRS_MASK (0x10U) |
| #define WDOG_WCR_SRS_SHIFT (4U) |
| /*! SRS |
| * 0b0..Assert system reset signal. |
| * 0b1..No effect on the system (Default). |
| */ |
| #define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) |
| #define WDOG_WCR_WDA_MASK (0x20U) |
| #define WDOG_WCR_WDA_SHIFT (5U) |
| /*! WDA |
| * 0b0..Assert WDOG_B output. |
| * 0b1..No effect on system (Default). |
| */ |
| #define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) |
| #define WDOG_WCR_SRE_MASK (0x40U) |
| #define WDOG_WCR_SRE_SHIFT (6U) |
| /*! SRE - Software Reset Extension. Required to be set to 1 when used in conjunction with the Software Reset Signal (SRS). |
| * 0b0..Reserved |
| * 0b1..This bit must be set to 1. |
| */ |
| #define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) |
| #define WDOG_WCR_WDW_MASK (0x80U) |
| #define WDOG_WCR_WDW_SHIFT (7U) |
| /*! WDW |
| * 0b0..Continue WDOG timer operation (Default). |
| * 0b1..Suspend WDOG timer operation. |
| */ |
| #define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) |
| #define WDOG_WCR_WT_MASK (0xFF00U) |
| #define WDOG_WCR_WT_SHIFT (8U) |
| /*! WT |
| * 0b00000000..- 0.5 Seconds (Default). |
| * 0b00000001..- 1.0 Seconds. |
| * 0b00000010..- 1.5 Seconds. |
| * 0b00000011..- 2.0 Seconds. |
| * 0b11111111..- 128 Seconds. |
| */ |
| #define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) |
| /*! @} */ |
| |
| /*! @name WSR - Watchdog Service Register */ |
| /*! @{ */ |
| #define WDOG_WSR_WSR_MASK (0xFFFFU) |
| #define WDOG_WSR_WSR_SHIFT (0U) |
| /*! WSR |
| * 0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR). |
| * 0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR). |
| */ |
| #define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) |
| /*! @} */ |
| |
| /*! @name WRSR - Watchdog Reset Status Register */ |
| /*! @{ */ |
| #define WDOG_WRSR_SFTW_MASK (0x1U) |
| #define WDOG_WRSR_SFTW_SHIFT (0U) |
| /*! SFTW |
| * 0b0..Reset is not the result of a software reset. |
| * 0b1..Reset is the result of a software reset. |
| */ |
| #define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) |
| #define WDOG_WRSR_TOUT_MASK (0x2U) |
| #define WDOG_WRSR_TOUT_SHIFT (1U) |
| /*! TOUT |
| * 0b0..Reset is not the result of a WDOG timeout. |
| * 0b1..Reset is the result of a WDOG timeout. |
| */ |
| #define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) |
| #define WDOG_WRSR_POR_MASK (0x10U) |
| #define WDOG_WRSR_POR_SHIFT (4U) |
| /*! POR |
| * 0b0..Reset is not the result of a power on reset. |
| * 0b1..Reset is the result of a power on reset. |
| */ |
| #define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) |
| /*! @} */ |
| |
| /*! @name WICR - Watchdog Interrupt Control Register */ |
| /*! @{ */ |
| #define WDOG_WICR_WICT_MASK (0xFFU) |
| #define WDOG_WICR_WICT_SHIFT (0U) |
| /*! WICT |
| * 0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. |
| * 0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. |
| * 0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). |
| * 0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds. |
| */ |
| #define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) |
| #define WDOG_WICR_WTIS_MASK (0x4000U) |
| #define WDOG_WICR_WTIS_SHIFT (14U) |
| /*! WTIS |
| * 0b0..No interrupt has occurred (Default). |
| * 0b1..Interrupt has occurred |
| */ |
| #define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) |
| #define WDOG_WICR_WIE_MASK (0x8000U) |
| #define WDOG_WICR_WIE_SHIFT (15U) |
| /*! WIE |
| * 0b0..Disable Interrupt (Default). |
| * 0b1..Enable Interrupt. |
| */ |
| #define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) |
| /*! @} */ |
| |
| /*! @name WMCR - Watchdog Miscellaneous Control Register */ |
| /*! @{ */ |
| #define WDOG_WMCR_PDE_MASK (0x1U) |
| #define WDOG_WMCR_PDE_SHIFT (0U) |
| /*! PDE |
| * 0b0..Power Down Counter of WDOG is disabled. |
| * 0b1..Power Down Counter of WDOG is enabled (Default). |
| */ |
| #define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group WDOG_Register_Masks */ |
| |
| |
| /* WDOG - Peripheral instance base addresses */ |
| /** Peripheral WDOG1 base address */ |
| #define WDOG1_BASE (0x30280000u) |
| /** Peripheral WDOG1 base pointer */ |
| #define WDOG1 ((WDOG_Type *)WDOG1_BASE) |
| /** Peripheral WDOG2 base address */ |
| #define WDOG2_BASE (0x30290000u) |
| /** Peripheral WDOG2 base pointer */ |
| #define WDOG2 ((WDOG_Type *)WDOG2_BASE) |
| /** Peripheral WDOG3 base address */ |
| #define WDOG3_BASE (0x302A0000u) |
| /** Peripheral WDOG3 base pointer */ |
| #define WDOG3 ((WDOG_Type *)WDOG3_BASE) |
| /** Array initializer of WDOG peripheral base addresses */ |
| #define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE, WDOG3_BASE } |
| /** Array initializer of WDOG peripheral base pointers */ |
| #define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2, WDOG3 } |
| /** Interrupt vectors for the WDOG peripheral type */ |
| #define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn, WDOG3_IRQn } |
| |
| /*! |
| * @} |
| */ /* end of group WDOG_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- WR_SCL Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup WR_SCL_Peripheral_Access_Layer WR_SCL Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** WR_SCL - Register Layout Typedef */ |
| typedef struct { |
| struct { /* offset: 0x0 */ |
| __IO uint32_t RW; /**< Control register for Context Loader., offset: 0x0 */ |
| __IO uint32_t SET; /**< Control register for Context Loader., offset: 0x4 */ |
| __IO uint32_t CLR; /**< Control register for Context Loader., offset: 0x8 */ |
| __IO uint32_t TOG; /**< Control register for Context Loader., offset: 0xC */ |
| } CTRL_STATUS; |
| __IO uint32_t BASE_ADDR; /**< Holds the base address, offset: 0x10 */ |
| __IO uint32_t PITCH; /**< Pitch, offset: 0x14 */ |
| } WR_SCL_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- WR_SCL Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup WR_SCL_Register_Masks WR_SCL Register Masks |
| * @{ |
| */ |
| |
| /*! @name CTRL_STATUS - Control register for Context Loader. */ |
| /*! @{ */ |
| #define WR_SCL_CTRL_STATUS_ENABLE_MASK (0x1U) |
| #define WR_SCL_CTRL_STATUS_ENABLE_SHIFT (0U) |
| #define WR_SCL_CTRL_STATUS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_ENABLE_SHIFT)) & WR_SCL_CTRL_STATUS_ENABLE_MASK) |
| #define WR_SCL_CTRL_STATUS_REPEAT_MASK (0x2U) |
| #define WR_SCL_CTRL_STATUS_REPEAT_SHIFT (1U) |
| #define WR_SCL_CTRL_STATUS_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_REPEAT_SHIFT)) & WR_SCL_CTRL_STATUS_REPEAT_MASK) |
| #define WR_SCL_CTRL_STATUS_BPP_MASK (0x1CU) |
| #define WR_SCL_CTRL_STATUS_BPP_SHIFT (2U) |
| #define WR_SCL_CTRL_STATUS_BPP(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_BPP_SHIFT)) & WR_SCL_CTRL_STATUS_BPP_MASK) |
| #define WR_SCL_CTRL_STATUS_T_SIZE_MASK (0x60U) |
| #define WR_SCL_CTRL_STATUS_T_SIZE_SHIFT (5U) |
| #define WR_SCL_CTRL_STATUS_T_SIZE(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_T_SIZE_SHIFT)) & WR_SCL_CTRL_STATUS_T_SIZE_MASK) |
| #define WR_SCL_CTRL_STATUS_P_SIZE_MASK (0x380U) |
| #define WR_SCL_CTRL_STATUS_P_SIZE_SHIFT (7U) |
| #define WR_SCL_CTRL_STATUS_P_SIZE(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_P_SIZE_SHIFT)) & WR_SCL_CTRL_STATUS_P_SIZE_MASK) |
| #define WR_SCL_CTRL_STATUS_P_FREQ_MASK (0x3FC00U) |
| #define WR_SCL_CTRL_STATUS_P_FREQ_SHIFT (10U) |
| #define WR_SCL_CTRL_STATUS_P_FREQ(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_P_FREQ_SHIFT)) & WR_SCL_CTRL_STATUS_P_FREQ_MASK) |
| #define WR_SCL_CTRL_STATUS_FIFO_SIZE_MASK (0x1FC0000U) |
| #define WR_SCL_CTRL_STATUS_FIFO_SIZE_SHIFT (18U) |
| #define WR_SCL_CTRL_STATUS_FIFO_SIZE(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_FIFO_SIZE_SHIFT)) & WR_SCL_CTRL_STATUS_FIFO_SIZE_MASK) |
| #define WR_SCL_CTRL_STATUS_FRAME_COMP_EN_MASK (0x10000000U) |
| #define WR_SCL_CTRL_STATUS_FRAME_COMP_EN_SHIFT (28U) |
| #define WR_SCL_CTRL_STATUS_FRAME_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_FRAME_COMP_EN_SHIFT)) & WR_SCL_CTRL_STATUS_FRAME_COMP_EN_MASK) |
| #define WR_SCL_CTRL_STATUS_FRAME_COMP_MASK (0x20000000U) |
| #define WR_SCL_CTRL_STATUS_FRAME_COMP_SHIFT (29U) |
| #define WR_SCL_CTRL_STATUS_FRAME_COMP(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_FRAME_COMP_SHIFT)) & WR_SCL_CTRL_STATUS_FRAME_COMP_MASK) |
| #define WR_SCL_CTRL_STATUS_WR_ERR_EN_MASK (0x40000000U) |
| #define WR_SCL_CTRL_STATUS_WR_ERR_EN_SHIFT (30U) |
| #define WR_SCL_CTRL_STATUS_WR_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_WR_ERR_EN_SHIFT)) & WR_SCL_CTRL_STATUS_WR_ERR_EN_MASK) |
| #define WR_SCL_CTRL_STATUS_WR_ERR_MASK (0x80000000U) |
| #define WR_SCL_CTRL_STATUS_WR_ERR_SHIFT (31U) |
| #define WR_SCL_CTRL_STATUS_WR_ERR(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_CTRL_STATUS_WR_ERR_SHIFT)) & WR_SCL_CTRL_STATUS_WR_ERR_MASK) |
| /*! @} */ |
| |
| /*! @name BASE_ADDR - Holds the base address */ |
| /*! @{ */ |
| #define WR_SCL_BASE_ADDR_BASE_ADDR_MASK (0xFFFFFFFFU) |
| #define WR_SCL_BASE_ADDR_BASE_ADDR_SHIFT (0U) |
| #define WR_SCL_BASE_ADDR_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_BASE_ADDR_BASE_ADDR_SHIFT)) & WR_SCL_BASE_ADDR_BASE_ADDR_MASK) |
| /*! @} */ |
| |
| /*! @name PITCH - Pitch */ |
| /*! @{ */ |
| #define WR_SCL_PITCH_PITCH_MASK (0xFFFFU) |
| #define WR_SCL_PITCH_PITCH_SHIFT (0U) |
| #define WR_SCL_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << WR_SCL_PITCH_PITCH_SHIFT)) & WR_SCL_PITCH_PITCH_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group WR_SCL_Register_Masks */ |
| |
| |
| /* WR_SCL - Peripheral instance base addresses */ |
| /** Peripheral DCSS__WR_SCL base address */ |
| #define DCSS__WR_SCL_BASE (0x32E21000u) |
| /** Peripheral DCSS__WR_SCL base pointer */ |
| #define DCSS__WR_SCL ((WR_SCL_Type *)DCSS__WR_SCL_BASE) |
| /** Array initializer of WR_SCL peripheral base addresses */ |
| #define WR_SCL_BASE_ADDRS { DCSS__WR_SCL_BASE } |
| /** Array initializer of WR_SCL peripheral base pointers */ |
| #define WR_SCL_BASE_PTRS { DCSS__WR_SCL } |
| |
| /*! |
| * @} |
| */ /* end of group WR_SCL_Peripheral_Access_Layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- XTALOSC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup XTALOSC_Peripheral_Access_Layer XTALOSC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** XTALOSC - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t OSC25M_CTL_CFG; /**< 25M Oscillator Control Configuration Register, offset: 0x0 */ |
| __IO uint32_t OSC25M_TEST_CFG; /**< 25M Oscillator Test Configuration Register, offset: 0x4 */ |
| uint8_t RESERVED_0[32760]; |
| __IO uint32_t OSC27M_CTL_CFG; /**< 27M Oscillator Control Configuration Register, offset: 0x8000 */ |
| __IO uint32_t OSC27M_TEST_CFG; /**< 27M Oscillator Test Configuration Register, offset: 0x8004 */ |
| } XTALOSC_Type; |
| |
| /* ---------------------------------------------------------------------------- |
| -- XTALOSC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup XTALOSC_Register_Masks XTALOSC Register Masks |
| * @{ |
| */ |
| |
| /*! @name OSC25M_CTL_CFG - 25M Oscillator Control Configuration Register */ |
| /*! @{ */ |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_ALC_CTL_MASK (0x4U) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_ALC_CTL_SHIFT (2U) |
| /*! OSC_ALC_CTL |
| * 0b0..Enable automatic level controller |
| * 0b1..Disable automatic level controller |
| */ |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_ALC_CTL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_ALC_CTL_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_ALC_CTL_MASK) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_HYST_CTL_MASK (0x8U) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_HYST_CTL_SHIFT (3U) |
| /*! OSC_HYST_CTL |
| * 0b0..Enable hysteresis control |
| * 0b1..Disable hysteresis control |
| */ |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_HYST_CTL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_HYST_CTL_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_HYST_CTL_MASK) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_GM_SEL_MASK (0x70U) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_GM_SEL_SHIFT (4U) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_GM_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_GM_SEL_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_GM_SEL_MASK) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_INT_STU_MASK (0x80U) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_INT_STU_SHIFT (7U) |
| /*! OSC_INT_STU |
| * 0b0..No oscillator clock interrupt occurred |
| * 0b1..Oscillator clock interrupt pending |
| */ |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_INT_STU(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_INT_STU_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_INT_STU_MASK) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_DIV_MASK (0x1F00U) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_DIV_SHIFT (8U) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_DIV_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_DIV_MASK) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_OK_BYPASS_MASK (0x2000U) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_OK_BYPASS_SHIFT (13U) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_OK_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_OK_BYPASS_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_OK_BYPASS_MASK) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_INT_MASK_MASK (0x8000U) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_INT_MASK_SHIFT (15U) |
| /*! OSC_INT_MASK |
| * 0b0..Crystal oscillator clock interrupt is masked |
| * 0b1..Crystal oscillator clock interrupt is enabled |
| */ |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_INT_MASK_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_INT_MASK_MASK) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_EOCV_MASK (0xFF0000U) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_EOCV_SHIFT (16U) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_EOCV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_EOCV_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_EOCV_MASK) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_GM_TST_SEL_MASK (0x40000000U) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_GM_TST_SEL_SHIFT (30U) |
| /*! OSC_GM_TST_SEL |
| * 0b0..Normal run mode |
| * 0b1..Enable test mode measurement of GM |
| */ |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_GM_TST_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_GM_TST_SEL_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_GM_TST_SEL_MASK) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_BYPSS_MASK (0x80000000U) |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_BYPSS_SHIFT (31U) |
| /*! OSC_BYPSS |
| * 0b0..Oscillator output is used as root clock. |
| * 0b1..EXTAL is used as root clock |
| */ |
| #define XTALOSC_OSC25M_CTL_CFG_OSC_BYPSS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_CTL_CFG_OSC_BYPSS_SHIFT)) & XTALOSC_OSC25M_CTL_CFG_OSC_BYPSS_MASK) |
| /*! @} */ |
| |
| /*! @name OSC25M_TEST_CFG - 25M Oscillator Test Configuration Register */ |
| /*! @{ */ |
| #define XTALOSC_OSC25M_TEST_CFG_XOSC_TESTEN_MASK (0x80000000U) |
| #define XTALOSC_OSC25M_TEST_CFG_XOSC_TESTEN_SHIFT (31U) |
| #define XTALOSC_OSC25M_TEST_CFG_XOSC_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC25M_TEST_CFG_XOSC_TESTEN_SHIFT)) & XTALOSC_OSC25M_TEST_CFG_XOSC_TESTEN_MASK) |
| /*! @} */ |
| |
| /*! @name OSC27M_CTL_CFG - 27M Oscillator Control Configuration Register */ |
| /*! @{ */ |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_ALC_CTL_MASK (0x4U) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_ALC_CTL_SHIFT (2U) |
| /*! OSC_ALC_CTL |
| * 0b0..Enable automatic level controller |
| * 0b1..Disable automatic level controller |
| */ |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_ALC_CTL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_ALC_CTL_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_ALC_CTL_MASK) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_HYST_CTL_MASK (0x8U) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_HYST_CTL_SHIFT (3U) |
| /*! OSC_HYST_CTL |
| * 0b0..Enable hysteresis control |
| * 0b1..Disable hysteresis control |
| */ |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_HYST_CTL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_HYST_CTL_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_HYST_CTL_MASK) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_GM_SEL_MASK (0x70U) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_GM_SEL_SHIFT (4U) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_GM_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_GM_SEL_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_GM_SEL_MASK) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_INT_STU_MASK (0x80U) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_INT_STU_SHIFT (7U) |
| /*! OSC_INT_STU |
| * 0b0..No oscillator clock interrupt occurred |
| * 0b1..Oscillator clock interrupt pending |
| */ |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_INT_STU(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_INT_STU_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_INT_STU_MASK) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_DIV_MASK (0x1F00U) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_DIV_SHIFT (8U) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_DIV_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_DIV_MASK) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_OK_BYPASS_MASK (0x2000U) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_OK_BYPASS_SHIFT (13U) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_OK_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_OK_BYPASS_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_OK_BYPASS_MASK) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_INT_MASK_MASK (0x8000U) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_INT_MASK_SHIFT (15U) |
| /*! OSC_INT_MASK |
| * 0b0..Crystal oscillator clock interrupt is masked |
| * 0b1..Crystal oscillator clock interrupt is enabled |
| */ |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_INT_MASK_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_INT_MASK_MASK) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_EOCV_MASK (0xFF0000U) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_EOCV_SHIFT (16U) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_EOCV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_EOCV_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_EOCV_MASK) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_GM_TST_SEL_MASK (0x40000000U) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_GM_TST_SEL_SHIFT (30U) |
| /*! OSC_GM_TST_SEL |
| * 0b0..Normal run mode |
| * 0b1..Enable test mode measurement of GM |
| */ |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_GM_TST_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_GM_TST_SEL_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_GM_TST_SEL_MASK) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_BYPSS_MASK (0x80000000U) |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_BYPSS_SHIFT (31U) |
| /*! OSC_BYPSS |
| * 0b0..Oscillator output is used as root clock. |
| * 0b1..EXTAL is used as root clock |
| */ |
| #define XTALOSC_OSC27M_CTL_CFG_OSC_BYPSS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_CTL_CFG_OSC_BYPSS_SHIFT)) & XTALOSC_OSC27M_CTL_CFG_OSC_BYPSS_MASK) |
| /*! @} */ |
| |
| /*! @name OSC27M_TEST_CFG - 27M Oscillator Test Configuration Register */ |
| /*! @{ */ |
| #define XTALOSC_OSC27M_TEST_CFG_XOSC_TESTEN_MASK (0x80000000U) |
| #define XTALOSC_OSC27M_TEST_CFG_XOSC_TESTEN_SHIFT (31U) |
| #define XTALOSC_OSC27M_TEST_CFG_XOSC_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_OSC27M_TEST_CFG_XOSC_TESTEN_SHIFT)) & XTALOSC_OSC27M_TEST_CFG_XOSC_TESTEN_MASK) |
| /*! @} */ |
| |
| |
| /*! |
| * @} |
| */ /* end of group XTALOSC_Register_Masks */ |
| |
| |
| /* XTALOSC - Peripheral instance base addresses */ |
| /** Peripheral XTALOSC base address */ |
| #define XTALOSC_BASE (0x30270000u) |
| /** Peripheral XTALOSC base pointer */ |
| #define XTALOSC ((XTALOSC_Type *)XTALOSC_BASE) |
| /** Array initializer of XTALOSC peripheral base addresses */ |
| #define XTALOSC_BASE_ADDRS { XTALOSC_BASE } |
| /** Array initializer of XTALOSC peripheral base pointers */ |
| #define XTALOSC_BASE_PTRS { XTALOSC } |
| |
| /*! |
| * @} |
| */ /* end of group XTALOSC_Peripheral_Access_Layer */ |
| |
| |
| /* |
| ** End of section using anonymous unions |
| */ |
| |
| #if defined(__ARMCC_VERSION) |
| #if (__ARMCC_VERSION >= 6010050) |
| #pragma clang diagnostic pop |
| #else |
| #pragma pop |
| #endif |
| #elif defined(__GNUC__) |
| /* leave anonymous unions enabled */ |
| #elif defined(__IAR_SYSTEMS_ICC__) |
| #pragma language=default |
| #else |
| #error Not supported compiler type |
| #endif |
| |
| /*! |
| * @} |
| */ /* end of group Peripheral_access_layer */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). |
| * @{ |
| */ |
| |
| #if defined(__ARMCC_VERSION) |
| #if (__ARMCC_VERSION >= 6010050) |
| #pragma clang system_header |
| #endif |
| #elif defined(__IAR_SYSTEMS_ICC__) |
| #pragma system_include |
| #endif |
| |
| /** |
| * @brief Mask and left-shift a bit field value for use in a register bit range. |
| * @param field Name of the register bit field. |
| * @param value Value of the bit field. |
| * @return Masked and shifted value. |
| */ |
| #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) |
| /** |
| * @brief Mask and right-shift a register value to extract a bit field value. |
| * @param field Name of the register bit field. |
| * @param value Value of the register. |
| * @return Masked and shifted bit field value. |
| */ |
| #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) |
| |
| /*! |
| * @} |
| */ /* end of group Bit_Field_Generic_Macros */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- SDK Compatibility |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SDK_Compatibility_Symbols SDK Compatibility |
| * @{ |
| */ |
| |
| /* No SDK compatibility issues. */ |
| |
| /*! |
| * @} |
| */ /* end of group SDK_Compatibility_Symbols */ |
| |
| |
| #endif /* _MIMX8MQ6_CM4_H_ */ |
| |
