Jean-Christophe PLAGNIOL-VILLARD | 23fa648 | 2012-02-27 11:19:34 +0100 | [diff] [blame] | 1 | Atmel AT91 device tree bindings. |
| 2 | ================================ |
| 3 | |
Alexandre Belloni | 02037a9 | 2014-09-15 18:15:59 +0200 | [diff] [blame] | 4 | Boards with a SoC of the Atmel AT91 or SMART family shall have the following |
| 5 | properties: |
| 6 | |
| 7 | Required root node properties: |
| 8 | compatible: must be one of: |
| 9 | * "atmel,at91rm9200" |
| 10 | |
| 11 | * "atmel,at91sam9" for SoCs using an ARM926EJ-S core, shall be extended with |
| 12 | the specific SoC family or compatible: |
| 13 | o "atmel,at91sam9260" |
| 14 | o "atmel,at91sam9261" |
| 15 | o "atmel,at91sam9263" |
| 16 | o "atmel,at91sam9x5" for the 5 series, shall be extended with the specific |
| 17 | SoC compatible: |
| 18 | - "atmel,at91sam9g15" |
| 19 | - "atmel,at91sam9g25" |
| 20 | - "atmel,at91sam9g35" |
| 21 | - "atmel,at91sam9x25" |
| 22 | - "atmel,at91sam9x35" |
| 23 | o "atmel,at91sam9g20" |
| 24 | o "atmel,at91sam9g45" |
| 25 | o "atmel,at91sam9n12" |
| 26 | o "atmel,at91sam9rl" |
Alexandre Belloni | 1d376df | 2015-01-13 19:12:25 +0100 | [diff] [blame] | 27 | o "atmel,at91sam9xe" |
Alexandre Belloni | 02037a9 | 2014-09-15 18:15:59 +0200 | [diff] [blame] | 28 | * "atmel,sama5" for SoCs using a Cortex-A5, shall be extended with the specific |
| 29 | SoC family: |
Nicolas Ferre | c268a74 | 2015-07-30 19:12:12 +0200 | [diff] [blame] | 30 | o "atmel,sama5d2" shall be extended with the specific SoC compatible: |
| 31 | - "atmel,sama5d27" |
Alexandre Belloni | 02037a9 | 2014-09-15 18:15:59 +0200 | [diff] [blame] | 32 | o "atmel,sama5d3" shall be extended with the specific SoC compatible: |
| 33 | - "atmel,sama5d31" |
| 34 | - "atmel,sama5d33" |
| 35 | - "atmel,sama5d34" |
| 36 | - "atmel,sama5d35" |
| 37 | - "atmel,sama5d36" |
| 38 | o "atmel,sama5d4" shall be extended with the specific SoC compatible: |
| 39 | - "atmel,sama5d41" |
| 40 | - "atmel,sama5d42" |
| 41 | - "atmel,sama5d43" |
| 42 | - "atmel,sama5d44" |
| 43 | |
Jean-Christophe PLAGNIOL-VILLARD | 23fa648 | 2012-02-27 11:19:34 +0100 | [diff] [blame] | 44 | PIT Timer required properties: |
| 45 | - compatible: Should be "atmel,at91sam9260-pit" |
| 46 | - reg: Should contain registers location and length |
| 47 | - interrupts: Should contain interrupt for the PIT which is the IRQ line |
| 48 | shared across all System Controller members. |
Nicolas Ferre | 3a61a5d | 2012-01-19 10:13:40 +0100 | [diff] [blame] | 49 | |
Joachim Eastwood | 454c46d | 2012-10-28 18:31:07 +0000 | [diff] [blame] | 50 | System Timer (ST) required properties: |
Alexandre Belloni | b595809 | 2015-03-12 13:07:25 +0100 | [diff] [blame] | 51 | - compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" |
Joachim Eastwood | 454c46d | 2012-10-28 18:31:07 +0000 | [diff] [blame] | 52 | - reg: Should contain registers location and length |
| 53 | - interrupts: Should contain interrupt for the ST which is the IRQ line |
| 54 | shared across all System Controller members. |
Alexandre Belloni | fe2edd9 | 2015-07-30 01:02:36 +0200 | [diff] [blame] | 55 | - clocks: phandle to input clock. |
Alexandre Belloni | b595809 | 2015-03-12 13:07:25 +0100 | [diff] [blame] | 56 | Its subnodes can be: |
| 57 | - watchdog: compatible should be "atmel,at91rm9200-wdt" |
Joachim Eastwood | 454c46d | 2012-10-28 18:31:07 +0000 | [diff] [blame] | 58 | |
Nicolas Ferre | 3a61a5d | 2012-01-19 10:13:40 +0100 | [diff] [blame] | 59 | TC/TCLIB Timer required properties: |
Josh Wu | 11930c5 | 2012-09-14 17:01:29 +0800 | [diff] [blame] | 60 | - compatible: Should be "atmel,<chip>-tcb". |
Nicolas Ferre | 3a61a5d | 2012-01-19 10:13:40 +0100 | [diff] [blame] | 61 | <chip> can be "at91rm9200" or "at91sam9x5" |
| 62 | - reg: Should contain registers location and length |
| 63 | - interrupts: Should contain all interrupts for the TC block |
| 64 | Note that you can specify several interrupt cells if the TC |
| 65 | block has one interrupt per channel. |
Boris BREZILLON | 864382d | 2013-12-17 16:47:14 +0100 | [diff] [blame] | 66 | - clock-names: tuple listing input clock names. |
Boris Brezillon | 0460056 | 2015-07-31 02:11:14 +0200 | [diff] [blame] | 67 | Required elements: "t0_clk", "slow_clk" |
Boris BREZILLON | 864382d | 2013-12-17 16:47:14 +0100 | [diff] [blame] | 68 | Optional elements: "t1_clk", "t2_clk" |
| 69 | - clocks: phandles to input clocks. |
Nicolas Ferre | 3a61a5d | 2012-01-19 10:13:40 +0100 | [diff] [blame] | 70 | |
| 71 | Examples: |
| 72 | |
| 73 | One interrupt per TC block: |
| 74 | tcb0: timer@fff7c000 { |
| 75 | compatible = "atmel,at91rm9200-tcb"; |
| 76 | reg = <0xfff7c000 0x100>; |
| 77 | interrupts = <18 4>; |
Boris BREZILLON | 864382d | 2013-12-17 16:47:14 +0100 | [diff] [blame] | 78 | clocks = <&tcb0_clk>; |
| 79 | clock-names = "t0_clk"; |
Nicolas Ferre | 3a61a5d | 2012-01-19 10:13:40 +0100 | [diff] [blame] | 80 | }; |
| 81 | |
| 82 | One interrupt per TC channel in a TC block: |
| 83 | tcb1: timer@fffdc000 { |
| 84 | compatible = "atmel,at91rm9200-tcb"; |
| 85 | reg = <0xfffdc000 0x100>; |
| 86 | interrupts = <26 4 27 4 28 4>; |
Boris BREZILLON | 864382d | 2013-12-17 16:47:14 +0100 | [diff] [blame] | 87 | clocks = <&tcb1_clk>; |
| 88 | clock-names = "t0_clk"; |
Nicolas Ferre | 3a61a5d | 2012-01-19 10:13:40 +0100 | [diff] [blame] | 89 | }; |
Jean-Christophe PLAGNIOL-VILLARD | c8082d3 | 2012-03-03 03:16:27 +0800 | [diff] [blame] | 90 | |
| 91 | RSTC Reset Controller required properties: |
| 92 | - compatible: Should be "atmel,<chip>-rstc". |
Josh Wu | 1ae25d6 | 2015-07-20 17:32:05 +0800 | [diff] [blame] | 93 | <chip> can be "at91sam9260" or "at91sam9g45" or "sama5d3" |
Jean-Christophe PLAGNIOL-VILLARD | c8082d3 | 2012-03-03 03:16:27 +0800 | [diff] [blame] | 94 | - reg: Should contain registers location and length |
Alexandre Belloni | fe2edd9 | 2015-07-30 01:02:36 +0200 | [diff] [blame] | 95 | - clocks: phandle to input clock. |
Jean-Christophe PLAGNIOL-VILLARD | c8082d3 | 2012-03-03 03:16:27 +0800 | [diff] [blame] | 96 | |
| 97 | Example: |
| 98 | |
| 99 | rstc@fffffd00 { |
| 100 | compatible = "atmel,at91sam9260-rstc"; |
| 101 | reg = <0xfffffd00 0x10>; |
Alexandre Belloni | fe2edd9 | 2015-07-30 01:02:36 +0200 | [diff] [blame] | 102 | clocks = <&clk32k>; |
Jean-Christophe PLAGNIOL-VILLARD | c8082d3 | 2012-03-03 03:16:27 +0800 | [diff] [blame] | 103 | }; |
Jean-Christophe PLAGNIOL-VILLARD | a7776ec | 2012-03-02 20:54:37 +0800 | [diff] [blame] | 104 | |
| 105 | RAMC SDRAM/DDR Controller required properties: |
Alexandre Belloni | 0506b29 | 2015-03-16 21:04:06 +0100 | [diff] [blame] | 106 | - compatible: Should be "atmel,at91rm9200-sdramc", "syscon" |
Nicolas Ferre | 20b4e4f | 2013-11-15 11:03:23 +0100 | [diff] [blame] | 107 | "atmel,at91sam9260-sdramc", |
Jean-Christophe PLAGNIOL-VILLARD | a7776ec | 2012-03-02 20:54:37 +0800 | [diff] [blame] | 108 | "atmel,at91sam9g45-ddramc", |
Alexandre Belloni | 017b552 | 2014-07-08 18:21:11 +0200 | [diff] [blame] | 109 | "atmel,sama5d3-ddramc", |
Jean-Christophe PLAGNIOL-VILLARD | a7776ec | 2012-03-02 20:54:37 +0800 | [diff] [blame] | 110 | - reg: Should contain registers location and length |
Jean-Christophe PLAGNIOL-VILLARD | a7776ec | 2012-03-02 20:54:37 +0800 | [diff] [blame] | 111 | |
| 112 | Examples: |
| 113 | |
| 114 | ramc0: ramc@ffffe800 { |
| 115 | compatible = "atmel,at91sam9g45-ddramc"; |
| 116 | reg = <0xffffe800 0x200>; |
| 117 | }; |
| 118 | |
Jean-Christophe PLAGNIOL-VILLARD | 82015c4 | 2012-03-02 21:01:00 +0800 | [diff] [blame] | 119 | SHDWC Shutdown Controller |
| 120 | |
| 121 | required properties: |
| 122 | - compatible: Should be "atmel,<chip>-shdwc". |
| 123 | <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5". |
| 124 | - reg: Should contain registers location and length |
Alexandre Belloni | fe2edd9 | 2015-07-30 01:02:36 +0200 | [diff] [blame] | 125 | - clocks: phandle to input clock. |
Jean-Christophe PLAGNIOL-VILLARD | 82015c4 | 2012-03-02 21:01:00 +0800 | [diff] [blame] | 126 | |
| 127 | optional properties: |
| 128 | - atmel,wakeup-mode: String, operation mode of the wakeup mode. |
| 129 | Supported values are: "none", "high", "low", "any". |
| 130 | - atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf). |
| 131 | |
| 132 | optional at91sam9260 properties: |
| 133 | - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. |
| 134 | |
| 135 | optional at91sam9rl properties: |
| 136 | - atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. |
| 137 | - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. |
| 138 | |
| 139 | optional at91sam9x5 properties: |
| 140 | - atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. |
| 141 | |
| 142 | Example: |
| 143 | |
Alexandre Belloni | fe2edd9 | 2015-07-30 01:02:36 +0200 | [diff] [blame] | 144 | shdwc@fffffd10 { |
| 145 | compatible = "atmel,at91sam9260-shdwc"; |
| 146 | reg = <0xfffffd10 0x10>; |
| 147 | clocks = <&clk32k>; |
Jean-Christophe PLAGNIOL-VILLARD | 82015c4 | 2012-03-02 21:01:00 +0800 | [diff] [blame] | 148 | }; |
Alexandre Belloni | cb282f7 | 2014-12-18 10:45:50 +0100 | [diff] [blame] | 149 | |
| 150 | Special Function Registers (SFR) |
| 151 | |
| 152 | Special Function Registers (SFR) manage specific aspects of the integrated |
| 153 | memory, bridge implementations, processor and other functionality not controlled |
| 154 | elsewhere. |
| 155 | |
| 156 | required properties: |
| 157 | - compatible: Should be "atmel,<chip>-sfr", "syscon". |
| 158 | <chip> can be "sama5d3" or "sama5d4". |
| 159 | - reg: Should contain registers location and length |
| 160 | |
| 161 | sfr@f0038000 { |
| 162 | compatible = "atmel,sama5d3-sfr", "syscon"; |
| 163 | reg = <0xf0038000 0x60>; |
| 164 | }; |