Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Pin controller and GPIO driver for Amlogic Meson8b. |
| 3 | * |
| 4 | * Copyright (C) 2015 Endless Mobile, Inc. |
| 5 | * Author: Carlo Caione <carlo@endlessm.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License |
| 9 | * version 2 as published by the Free Software Foundation. |
| 10 | * |
| 11 | * You should have received a copy of the GNU General Public License |
| 12 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 13 | */ |
| 14 | |
| 15 | #include <dt-bindings/gpio/meson8b-gpio.h> |
| 16 | #include "pinctrl-meson.h" |
Jerome Brunet | ce385aa | 2017-10-12 14:40:26 +0200 | [diff] [blame] | 17 | #include "pinctrl-meson8-pmx.h" |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 18 | |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 19 | static const struct pinctrl_pin_desc meson8b_cbus_pins[] = { |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 20 | MESON_PIN(GPIOX_0), |
| 21 | MESON_PIN(GPIOX_1), |
| 22 | MESON_PIN(GPIOX_2), |
| 23 | MESON_PIN(GPIOX_3), |
| 24 | MESON_PIN(GPIOX_4), |
| 25 | MESON_PIN(GPIOX_5), |
| 26 | MESON_PIN(GPIOX_6), |
| 27 | MESON_PIN(GPIOX_7), |
| 28 | MESON_PIN(GPIOX_8), |
| 29 | MESON_PIN(GPIOX_9), |
| 30 | MESON_PIN(GPIOX_10), |
| 31 | MESON_PIN(GPIOX_11), |
| 32 | MESON_PIN(GPIOX_16), |
| 33 | MESON_PIN(GPIOX_17), |
| 34 | MESON_PIN(GPIOX_18), |
| 35 | MESON_PIN(GPIOX_19), |
| 36 | MESON_PIN(GPIOX_20), |
| 37 | MESON_PIN(GPIOX_21), |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 38 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 39 | MESON_PIN(GPIOY_0), |
| 40 | MESON_PIN(GPIOY_1), |
| 41 | MESON_PIN(GPIOY_3), |
| 42 | MESON_PIN(GPIOY_6), |
| 43 | MESON_PIN(GPIOY_7), |
| 44 | MESON_PIN(GPIOY_8), |
| 45 | MESON_PIN(GPIOY_9), |
| 46 | MESON_PIN(GPIOY_10), |
| 47 | MESON_PIN(GPIOY_11), |
| 48 | MESON_PIN(GPIOY_12), |
| 49 | MESON_PIN(GPIOY_13), |
| 50 | MESON_PIN(GPIOY_14), |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 51 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 52 | MESON_PIN(GPIODV_9), |
| 53 | MESON_PIN(GPIODV_24), |
| 54 | MESON_PIN(GPIODV_25), |
| 55 | MESON_PIN(GPIODV_26), |
| 56 | MESON_PIN(GPIODV_27), |
| 57 | MESON_PIN(GPIODV_28), |
| 58 | MESON_PIN(GPIODV_29), |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 59 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 60 | MESON_PIN(GPIOH_0), |
| 61 | MESON_PIN(GPIOH_1), |
| 62 | MESON_PIN(GPIOH_2), |
| 63 | MESON_PIN(GPIOH_3), |
| 64 | MESON_PIN(GPIOH_4), |
| 65 | MESON_PIN(GPIOH_5), |
| 66 | MESON_PIN(GPIOH_6), |
| 67 | MESON_PIN(GPIOH_7), |
| 68 | MESON_PIN(GPIOH_8), |
| 69 | MESON_PIN(GPIOH_9), |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 70 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 71 | MESON_PIN(CARD_0), |
| 72 | MESON_PIN(CARD_1), |
| 73 | MESON_PIN(CARD_2), |
| 74 | MESON_PIN(CARD_3), |
| 75 | MESON_PIN(CARD_4), |
| 76 | MESON_PIN(CARD_5), |
| 77 | MESON_PIN(CARD_6), |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 78 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 79 | MESON_PIN(BOOT_0), |
| 80 | MESON_PIN(BOOT_1), |
| 81 | MESON_PIN(BOOT_2), |
| 82 | MESON_PIN(BOOT_3), |
| 83 | MESON_PIN(BOOT_4), |
| 84 | MESON_PIN(BOOT_5), |
| 85 | MESON_PIN(BOOT_6), |
| 86 | MESON_PIN(BOOT_7), |
| 87 | MESON_PIN(BOOT_8), |
| 88 | MESON_PIN(BOOT_9), |
| 89 | MESON_PIN(BOOT_10), |
| 90 | MESON_PIN(BOOT_11), |
| 91 | MESON_PIN(BOOT_12), |
| 92 | MESON_PIN(BOOT_13), |
| 93 | MESON_PIN(BOOT_14), |
| 94 | MESON_PIN(BOOT_15), |
| 95 | MESON_PIN(BOOT_16), |
| 96 | MESON_PIN(BOOT_17), |
| 97 | MESON_PIN(BOOT_18), |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 98 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 99 | MESON_PIN(DIF_0_P), |
| 100 | MESON_PIN(DIF_0_N), |
| 101 | MESON_PIN(DIF_1_P), |
| 102 | MESON_PIN(DIF_1_N), |
| 103 | MESON_PIN(DIF_2_P), |
| 104 | MESON_PIN(DIF_2_N), |
| 105 | MESON_PIN(DIF_3_P), |
| 106 | MESON_PIN(DIF_3_N), |
| 107 | MESON_PIN(DIF_4_P), |
| 108 | MESON_PIN(DIF_4_N), |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 109 | }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 110 | |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 111 | static const struct pinctrl_pin_desc meson8b_aobus_pins[] = { |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 112 | MESON_PIN(GPIOAO_0), |
| 113 | MESON_PIN(GPIOAO_1), |
| 114 | MESON_PIN(GPIOAO_2), |
| 115 | MESON_PIN(GPIOAO_3), |
| 116 | MESON_PIN(GPIOAO_4), |
| 117 | MESON_PIN(GPIOAO_5), |
| 118 | MESON_PIN(GPIOAO_6), |
| 119 | MESON_PIN(GPIOAO_7), |
| 120 | MESON_PIN(GPIOAO_8), |
| 121 | MESON_PIN(GPIOAO_9), |
| 122 | MESON_PIN(GPIOAO_10), |
| 123 | MESON_PIN(GPIOAO_11), |
| 124 | MESON_PIN(GPIOAO_12), |
| 125 | MESON_PIN(GPIOAO_13), |
Jerome Brunet | 6c9dc84 | 2017-06-08 21:37:50 +0200 | [diff] [blame] | 126 | |
| 127 | /* |
| 128 | * The following 2 pins are not mentionned in the public datasheet |
| 129 | * According to this datasheet, they can't be used with the gpio |
| 130 | * interrupt controller |
| 131 | */ |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 132 | MESON_PIN(GPIO_BSD_EN), |
| 133 | MESON_PIN(GPIO_TEST_N), |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 134 | }; |
| 135 | |
| 136 | /* bank X */ |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 137 | static const unsigned int sd_d0_a_pins[] = { GPIOX_0 }; |
| 138 | static const unsigned int sd_d1_a_pins[] = { GPIOX_1 }; |
| 139 | static const unsigned int sd_d2_a_pins[] = { GPIOX_2 }; |
| 140 | static const unsigned int sd_d3_a_pins[] = { GPIOX_3 }; |
| 141 | static const unsigned int sdxc_d0_0_a_pins[] = { GPIOX_4 }; |
| 142 | static const unsigned int sdxc_d47_a_pins[] = { GPIOX_4, GPIOX_5, |
| 143 | GPIOX_6, GPIOX_7 }; |
| 144 | static const unsigned int sdxc_d13_0_a_pins[] = { GPIOX_5, GPIOX_6, |
| 145 | GPIOX_7 }; |
| 146 | static const unsigned int sd_clk_a_pins[] = { GPIOX_8 }; |
| 147 | static const unsigned int sd_cmd_a_pins[] = { GPIOX_9 }; |
| 148 | static const unsigned int xtal_32k_out_pins[] = { GPIOX_10 }; |
| 149 | static const unsigned int xtal_24m_out_pins[] = { GPIOX_11 }; |
| 150 | static const unsigned int uart_tx_b0_pins[] = { GPIOX_16 }; |
| 151 | static const unsigned int uart_rx_b0_pins[] = { GPIOX_17 }; |
| 152 | static const unsigned int uart_cts_b0_pins[] = { GPIOX_18 }; |
| 153 | static const unsigned int uart_rts_b0_pins[] = { GPIOX_19 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 154 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 155 | static const unsigned int sdxc_d0_1_a_pins[] = { GPIOX_0 }; |
| 156 | static const unsigned int sdxc_d13_1_a_pins[] = { GPIOX_1, GPIOX_2, |
| 157 | GPIOX_3 }; |
| 158 | static const unsigned int pcm_out_a_pins[] = { GPIOX_4 }; |
| 159 | static const unsigned int pcm_in_a_pins[] = { GPIOX_5 }; |
| 160 | static const unsigned int pcm_fs_a_pins[] = { GPIOX_6 }; |
| 161 | static const unsigned int pcm_clk_a_pins[] = { GPIOX_7 }; |
| 162 | static const unsigned int sdxc_clk_a_pins[] = { GPIOX_8 }; |
| 163 | static const unsigned int sdxc_cmd_a_pins[] = { GPIOX_9 }; |
| 164 | static const unsigned int pwm_vs_0_pins[] = { GPIOX_10 }; |
| 165 | static const unsigned int pwm_e_pins[] = { GPIOX_10 }; |
| 166 | static const unsigned int pwm_vs_1_pins[] = { GPIOX_11 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 167 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 168 | static const unsigned int uart_tx_a_pins[] = { GPIOX_4 }; |
| 169 | static const unsigned int uart_rx_a_pins[] = { GPIOX_5 }; |
| 170 | static const unsigned int uart_cts_a_pins[] = { GPIOX_6 }; |
| 171 | static const unsigned int uart_rts_a_pins[] = { GPIOX_7 }; |
| 172 | static const unsigned int uart_tx_b1_pins[] = { GPIOX_8 }; |
| 173 | static const unsigned int uart_rx_b1_pins[] = { GPIOX_9 }; |
| 174 | static const unsigned int uart_cts_b1_pins[] = { GPIOX_10 }; |
| 175 | static const unsigned int uart_rts_b1_pins[] = { GPIOX_20 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 176 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 177 | static const unsigned int iso7816_0_clk_pins[] = { GPIOX_6 }; |
| 178 | static const unsigned int iso7816_0_data_pins[] = { GPIOX_7 }; |
| 179 | static const unsigned int spi_sclk_0_pins[] = { GPIOX_8 }; |
| 180 | static const unsigned int spi_miso_0_pins[] = { GPIOX_9 }; |
| 181 | static const unsigned int spi_mosi_0_pins[] = { GPIOX_10 }; |
| 182 | static const unsigned int iso7816_det_pins[] = { GPIOX_16 }; |
| 183 | static const unsigned int iso7816_reset_pins[] = { GPIOX_17 }; |
| 184 | static const unsigned int iso7816_1_clk_pins[] = { GPIOX_18 }; |
| 185 | static const unsigned int iso7816_1_data_pins[] = { GPIOX_19 }; |
| 186 | static const unsigned int spi_ss0_0_pins[] = { GPIOX_20 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 187 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 188 | static const unsigned int tsin_clk_b_pins[] = { GPIOX_8 }; |
| 189 | static const unsigned int tsin_sop_b_pins[] = { GPIOX_9 }; |
| 190 | static const unsigned int tsin_d0_b_pins[] = { GPIOX_10 }; |
| 191 | static const unsigned int pwm_b_pins[] = { GPIOX_11 }; |
| 192 | static const unsigned int i2c_sda_d0_pins[] = { GPIOX_16 }; |
| 193 | static const unsigned int i2c_sck_d0_pins[] = { GPIOX_17 }; |
| 194 | static const unsigned int tsin_d_valid_b_pins[] = { GPIOX_20 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 195 | |
| 196 | /* bank Y */ |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 197 | static const unsigned int tsin_d_valid_a_pins[] = { GPIOY_0 }; |
| 198 | static const unsigned int tsin_sop_a_pins[] = { GPIOY_1 }; |
| 199 | static const unsigned int tsin_d17_a_pins[] = { |
| 200 | GPIOY_6, GPIOY_7, GPIOY_10, GPIOY_11, GPIOY_12, GPIOY_13, GPIOY_14, |
| 201 | }; |
| 202 | static const unsigned int tsin_clk_a_pins[] = { GPIOY_8 }; |
| 203 | static const unsigned int tsin_d0_a_pins[] = { GPIOY_9 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 204 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 205 | static const unsigned int spdif_out_0_pins[] = { GPIOY_3 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 206 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 207 | static const unsigned int xtal_24m_pins[] = { GPIOY_3 }; |
| 208 | static const unsigned int iso7816_2_clk_pins[] = { GPIOY_13 }; |
| 209 | static const unsigned int iso7816_2_data_pins[] = { GPIOY_14 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 210 | |
| 211 | /* bank DV */ |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 212 | static const unsigned int pwm_d_pins[] = { GPIODV_28 }; |
| 213 | static const unsigned int pwm_c0_pins[] = { GPIODV_29 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 214 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 215 | static const unsigned int pwm_vs_2_pins[] = { GPIODV_9 }; |
| 216 | static const unsigned int pwm_vs_3_pins[] = { GPIODV_28 }; |
| 217 | static const unsigned int pwm_vs_4_pins[] = { GPIODV_29 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 218 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 219 | static const unsigned int xtal24_out_pins[] = { GPIODV_29 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 220 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 221 | static const unsigned int uart_tx_c_pins[] = { GPIODV_24 }; |
| 222 | static const unsigned int uart_rx_c_pins[] = { GPIODV_25 }; |
| 223 | static const unsigned int uart_cts_c_pins[] = { GPIODV_26 }; |
| 224 | static const unsigned int uart_rts_c_pins[] = { GPIODV_27 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 225 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 226 | static const unsigned int pwm_c1_pins[] = { GPIODV_9 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 227 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 228 | static const unsigned int i2c_sda_a_pins[] = { GPIODV_24 }; |
| 229 | static const unsigned int i2c_sck_a_pins[] = { GPIODV_25 }; |
| 230 | static const unsigned int i2c_sda_b0_pins[] = { GPIODV_26 }; |
| 231 | static const unsigned int i2c_sck_b0_pins[] = { GPIODV_27 }; |
| 232 | static const unsigned int i2c_sda_c0_pins[] = { GPIODV_28 }; |
| 233 | static const unsigned int i2c_sck_c0_pins[] = { GPIODV_29 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 234 | |
| 235 | /* bank H */ |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 236 | static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 }; |
| 237 | static const unsigned int hdmi_sda_pins[] = { GPIOH_1 }; |
| 238 | static const unsigned int hdmi_scl_pins[] = { GPIOH_2 }; |
| 239 | static const unsigned int hdmi_cec_0_pins[] = { GPIOH_3 }; |
| 240 | static const unsigned int eth_txd1_0_pins[] = { GPIOH_5 }; |
| 241 | static const unsigned int eth_txd0_0_pins[] = { GPIOH_6 }; |
| 242 | static const unsigned int clk_24m_out_pins[] = { GPIOH_9 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 243 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 244 | static const unsigned int spi_ss1_pins[] = { GPIOH_0 }; |
| 245 | static const unsigned int spi_ss2_pins[] = { GPIOH_1 }; |
| 246 | static const unsigned int spi_ss0_1_pins[] = { GPIOH_3 }; |
| 247 | static const unsigned int spi_miso_1_pins[] = { GPIOH_4 }; |
| 248 | static const unsigned int spi_mosi_1_pins[] = { GPIOH_5 }; |
| 249 | static const unsigned int spi_sclk_1_pins[] = { GPIOH_6 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 250 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 251 | static const unsigned int eth_txd3_pins[] = { GPIOH_7 }; |
| 252 | static const unsigned int eth_txd2_pins[] = { GPIOH_8 }; |
| 253 | static const unsigned int eth_tx_clk_pins[] = { GPIOH_9 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 254 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 255 | static const unsigned int i2c_sda_b1_pins[] = { GPIOH_3 }; |
| 256 | static const unsigned int i2c_sck_b1_pins[] = { GPIOH_4 }; |
| 257 | static const unsigned int i2c_sda_c1_pins[] = { GPIOH_5 }; |
| 258 | static const unsigned int i2c_sck_c1_pins[] = { GPIOH_6 }; |
| 259 | static const unsigned int i2c_sda_d1_pins[] = { GPIOH_7 }; |
| 260 | static const unsigned int i2c_sck_d1_pins[] = { GPIOH_8 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 261 | |
| 262 | /* bank BOOT */ |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 263 | static const unsigned int nand_io_pins[] = { |
| 264 | BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7 |
| 265 | }; |
| 266 | static const unsigned int nand_io_ce0_pins[] = { BOOT_8 }; |
| 267 | static const unsigned int nand_io_ce1_pins[] = { BOOT_9 }; |
| 268 | static const unsigned int nand_io_rb0_pins[] = { BOOT_10 }; |
| 269 | static const unsigned int nand_ale_pins[] = { BOOT_11 }; |
| 270 | static const unsigned int nand_cle_pins[] = { BOOT_12 }; |
| 271 | static const unsigned int nand_wen_clk_pins[] = { BOOT_13 }; |
| 272 | static const unsigned int nand_ren_clk_pins[] = { BOOT_14 }; |
| 273 | static const unsigned int nand_dqs_15_pins[] = { BOOT_15 }; |
| 274 | static const unsigned int nand_dqs_18_pins[] = { BOOT_18 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 275 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 276 | static const unsigned int sdxc_d0_c_pins[] = { BOOT_0}; |
| 277 | static const unsigned int sdxc_d13_c_pins[] = { BOOT_1, BOOT_2, |
| 278 | BOOT_3 }; |
| 279 | static const unsigned int sdxc_d47_c_pins[] = { BOOT_4, BOOT_5, |
| 280 | BOOT_6, BOOT_7 }; |
| 281 | static const unsigned int sdxc_clk_c_pins[] = { BOOT_8 }; |
| 282 | static const unsigned int sdxc_cmd_c_pins[] = { BOOT_10 }; |
| 283 | static const unsigned int nor_d_pins[] = { BOOT_11 }; |
| 284 | static const unsigned int nor_q_pins[] = { BOOT_12 }; |
| 285 | static const unsigned int nor_c_pins[] = { BOOT_13 }; |
| 286 | static const unsigned int nor_cs_pins[] = { BOOT_18 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 287 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 288 | static const unsigned int sd_d0_c_pins[] = { BOOT_0 }; |
| 289 | static const unsigned int sd_d1_c_pins[] = { BOOT_1 }; |
| 290 | static const unsigned int sd_d2_c_pins[] = { BOOT_2 }; |
| 291 | static const unsigned int sd_d3_c_pins[] = { BOOT_3 }; |
| 292 | static const unsigned int sd_cmd_c_pins[] = { BOOT_8 }; |
| 293 | static const unsigned int sd_clk_c_pins[] = { BOOT_10 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 294 | |
| 295 | /* bank CARD */ |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 296 | static const unsigned int sd_d1_b_pins[] = { CARD_0 }; |
| 297 | static const unsigned int sd_d0_b_pins[] = { CARD_1 }; |
| 298 | static const unsigned int sd_clk_b_pins[] = { CARD_2 }; |
| 299 | static const unsigned int sd_cmd_b_pins[] = { CARD_3 }; |
| 300 | static const unsigned int sd_d3_b_pins[] = { CARD_4 }; |
| 301 | static const unsigned int sd_d2_b_pins[] = { CARD_5 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 302 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 303 | static const unsigned int sdxc_d13_b_pins[] = { CARD_0, CARD_4, |
| 304 | CARD_5 }; |
| 305 | static const unsigned int sdxc_d0_b_pins[] = { CARD_1 }; |
| 306 | static const unsigned int sdxc_clk_b_pins[] = { CARD_2 }; |
| 307 | static const unsigned int sdxc_cmd_b_pins[] = { CARD_3 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 308 | |
| 309 | /* bank AO */ |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 310 | static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 }; |
| 311 | static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 }; |
| 312 | static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 }; |
| 313 | static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 }; |
| 314 | static const unsigned int i2c_mst_sck_ao_pins[] = { GPIOAO_4 }; |
| 315 | static const unsigned int i2c_mst_sda_ao_pins[] = { GPIOAO_5 }; |
| 316 | static const unsigned int clk_32k_in_out_pins[] = { GPIOAO_6 }; |
| 317 | static const unsigned int remote_input_pins[] = { GPIOAO_7 }; |
| 318 | static const unsigned int hdmi_cec_1_pins[] = { GPIOAO_12 }; |
| 319 | static const unsigned int ir_blaster_pins[] = { GPIOAO_13 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 320 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 321 | static const unsigned int pwm_c2_pins[] = { GPIOAO_3 }; |
| 322 | static const unsigned int i2c_sck_ao_pins[] = { GPIOAO_4 }; |
| 323 | static const unsigned int i2c_sda_ao_pins[] = { GPIOAO_5 }; |
| 324 | static const unsigned int ir_remote_out_pins[] = { GPIOAO_7 }; |
| 325 | static const unsigned int i2s_am_clk_out_pins[] = { GPIOAO_8 }; |
| 326 | static const unsigned int i2s_ao_clk_out_pins[] = { GPIOAO_9 }; |
| 327 | static const unsigned int i2s_lr_clk_out_pins[] = { GPIOAO_10 }; |
| 328 | static const unsigned int i2s_out_01_pins[] = { GPIOAO_11 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 329 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 330 | static const unsigned int uart_tx_ao_b0_pins[] = { GPIOAO_0 }; |
| 331 | static const unsigned int uart_rx_ao_b0_pins[] = { GPIOAO_1 }; |
| 332 | static const unsigned int uart_cts_ao_b_pins[] = { GPIOAO_2 }; |
| 333 | static const unsigned int uart_rts_ao_b_pins[] = { GPIOAO_3 }; |
| 334 | static const unsigned int uart_tx_ao_b1_pins[] = { GPIOAO_4 }; |
| 335 | static const unsigned int uart_rx_ao_b1_pins[] = { GPIOAO_5 }; |
| 336 | static const unsigned int spdif_out_1_pins[] = { GPIOAO_6 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 337 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 338 | static const unsigned int i2s_in_ch01_pins[] = { GPIOAO_6 }; |
| 339 | static const unsigned int i2s_ao_clk_in_pins[] = { GPIOAO_9 }; |
| 340 | static const unsigned int i2s_lr_clk_in_pins[] = { GPIOAO_10 }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 341 | |
| 342 | /* bank DIF */ |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 343 | static const unsigned int eth_rxd1_pins[] = { DIF_0_P }; |
| 344 | static const unsigned int eth_rxd0_pins[] = { DIF_0_N }; |
| 345 | static const unsigned int eth_rx_dv_pins[] = { DIF_1_P }; |
| 346 | static const unsigned int eth_rx_clk_pins[] = { DIF_1_N }; |
| 347 | static const unsigned int eth_txd0_1_pins[] = { DIF_2_P }; |
| 348 | static const unsigned int eth_txd1_1_pins[] = { DIF_2_N }; |
Martin Blumenstingl | 27d6de3 | 2019-01-12 13:59:13 +0100 | [diff] [blame] | 349 | static const unsigned int eth_rxd3_pins[] = { DIF_2_P }; |
| 350 | static const unsigned int eth_rxd2_pins[] = { DIF_2_N }; |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 351 | static const unsigned int eth_tx_en_pins[] = { DIF_3_P }; |
| 352 | static const unsigned int eth_ref_clk_pins[] = { DIF_3_N }; |
| 353 | static const unsigned int eth_mdc_pins[] = { DIF_4_P }; |
| 354 | static const unsigned int eth_mdio_en_pins[] = { DIF_4_N }; |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 355 | |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 356 | static struct meson_pmx_group meson8b_cbus_groups[] = { |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 357 | GPIO_GROUP(GPIOX_0), |
| 358 | GPIO_GROUP(GPIOX_1), |
| 359 | GPIO_GROUP(GPIOX_2), |
| 360 | GPIO_GROUP(GPIOX_3), |
| 361 | GPIO_GROUP(GPIOX_4), |
| 362 | GPIO_GROUP(GPIOX_5), |
| 363 | GPIO_GROUP(GPIOX_6), |
| 364 | GPIO_GROUP(GPIOX_7), |
| 365 | GPIO_GROUP(GPIOX_8), |
| 366 | GPIO_GROUP(GPIOX_9), |
| 367 | GPIO_GROUP(GPIOX_10), |
| 368 | GPIO_GROUP(GPIOX_11), |
| 369 | GPIO_GROUP(GPIOX_16), |
| 370 | GPIO_GROUP(GPIOX_17), |
| 371 | GPIO_GROUP(GPIOX_18), |
| 372 | GPIO_GROUP(GPIOX_19), |
| 373 | GPIO_GROUP(GPIOX_20), |
| 374 | GPIO_GROUP(GPIOX_21), |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 375 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 376 | GPIO_GROUP(GPIOY_0), |
| 377 | GPIO_GROUP(GPIOY_1), |
| 378 | GPIO_GROUP(GPIOY_3), |
| 379 | GPIO_GROUP(GPIOY_6), |
| 380 | GPIO_GROUP(GPIOY_7), |
| 381 | GPIO_GROUP(GPIOY_8), |
| 382 | GPIO_GROUP(GPIOY_9), |
| 383 | GPIO_GROUP(GPIOY_10), |
| 384 | GPIO_GROUP(GPIOY_11), |
| 385 | GPIO_GROUP(GPIOY_12), |
| 386 | GPIO_GROUP(GPIOY_13), |
| 387 | GPIO_GROUP(GPIOY_14), |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 388 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 389 | GPIO_GROUP(GPIODV_9), |
| 390 | GPIO_GROUP(GPIODV_24), |
| 391 | GPIO_GROUP(GPIODV_25), |
| 392 | GPIO_GROUP(GPIODV_26), |
| 393 | GPIO_GROUP(GPIODV_27), |
| 394 | GPIO_GROUP(GPIODV_28), |
| 395 | GPIO_GROUP(GPIODV_29), |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 396 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 397 | GPIO_GROUP(GPIOH_0), |
| 398 | GPIO_GROUP(GPIOH_1), |
| 399 | GPIO_GROUP(GPIOH_2), |
| 400 | GPIO_GROUP(GPIOH_3), |
| 401 | GPIO_GROUP(GPIOH_4), |
| 402 | GPIO_GROUP(GPIOH_5), |
| 403 | GPIO_GROUP(GPIOH_6), |
| 404 | GPIO_GROUP(GPIOH_7), |
| 405 | GPIO_GROUP(GPIOH_8), |
| 406 | GPIO_GROUP(GPIOH_9), |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 407 | |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 408 | GPIO_GROUP(DIF_0_P), |
| 409 | GPIO_GROUP(DIF_0_N), |
| 410 | GPIO_GROUP(DIF_1_P), |
| 411 | GPIO_GROUP(DIF_1_N), |
| 412 | GPIO_GROUP(DIF_2_P), |
| 413 | GPIO_GROUP(DIF_2_N), |
| 414 | GPIO_GROUP(DIF_3_P), |
| 415 | GPIO_GROUP(DIF_3_N), |
| 416 | GPIO_GROUP(DIF_4_P), |
| 417 | GPIO_GROUP(DIF_4_N), |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 418 | |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 419 | /* bank X */ |
| 420 | GROUP(sd_d0_a, 8, 5), |
| 421 | GROUP(sd_d1_a, 8, 4), |
| 422 | GROUP(sd_d2_a, 8, 3), |
| 423 | GROUP(sd_d3_a, 8, 2), |
| 424 | GROUP(sdxc_d0_0_a, 5, 29), |
| 425 | GROUP(sdxc_d47_a, 5, 12), |
| 426 | GROUP(sdxc_d13_0_a, 5, 28), |
| 427 | GROUP(sd_clk_a, 8, 1), |
| 428 | GROUP(sd_cmd_a, 8, 0), |
| 429 | GROUP(xtal_32k_out, 3, 22), |
| 430 | GROUP(xtal_24m_out, 3, 20), |
| 431 | GROUP(uart_tx_b0, 4, 9), |
| 432 | GROUP(uart_rx_b0, 4, 8), |
| 433 | GROUP(uart_cts_b0, 4, 7), |
| 434 | GROUP(uart_rts_b0, 4, 6), |
| 435 | GROUP(sdxc_d0_1_a, 5, 14), |
| 436 | GROUP(sdxc_d13_1_a, 5, 13), |
| 437 | GROUP(pcm_out_a, 3, 30), |
| 438 | GROUP(pcm_in_a, 3, 29), |
| 439 | GROUP(pcm_fs_a, 3, 28), |
| 440 | GROUP(pcm_clk_a, 3, 27), |
| 441 | GROUP(sdxc_clk_a, 5, 11), |
| 442 | GROUP(sdxc_cmd_a, 5, 10), |
| 443 | GROUP(pwm_vs_0, 7, 31), |
| 444 | GROUP(pwm_e, 9, 19), |
| 445 | GROUP(pwm_vs_1, 7, 30), |
| 446 | GROUP(uart_tx_a, 4, 17), |
| 447 | GROUP(uart_rx_a, 4, 16), |
| 448 | GROUP(uart_cts_a, 4, 15), |
| 449 | GROUP(uart_rts_a, 4, 14), |
| 450 | GROUP(uart_tx_b1, 6, 19), |
| 451 | GROUP(uart_rx_b1, 6, 18), |
| 452 | GROUP(uart_cts_b1, 6, 17), |
| 453 | GROUP(uart_rts_b1, 6, 16), |
| 454 | GROUP(iso7816_0_clk, 5, 9), |
| 455 | GROUP(iso7816_0_data, 5, 8), |
| 456 | GROUP(spi_sclk_0, 4, 22), |
| 457 | GROUP(spi_miso_0, 4, 24), |
| 458 | GROUP(spi_mosi_0, 4, 23), |
| 459 | GROUP(iso7816_det, 4, 21), |
| 460 | GROUP(iso7816_reset, 4, 20), |
| 461 | GROUP(iso7816_1_clk, 4, 19), |
| 462 | GROUP(iso7816_1_data, 4, 18), |
| 463 | GROUP(spi_ss0_0, 4, 25), |
| 464 | GROUP(tsin_clk_b, 3, 6), |
| 465 | GROUP(tsin_sop_b, 3, 7), |
| 466 | GROUP(tsin_d0_b, 3, 8), |
| 467 | GROUP(pwm_b, 2, 3), |
| 468 | GROUP(i2c_sda_d0, 4, 5), |
| 469 | GROUP(i2c_sck_d0, 4, 4), |
| 470 | GROUP(tsin_d_valid_b, 3, 9), |
| 471 | |
| 472 | /* bank Y */ |
| 473 | GROUP(tsin_d_valid_a, 3, 2), |
| 474 | GROUP(tsin_sop_a, 3, 1), |
| 475 | GROUP(tsin_d17_a, 3, 5), |
| 476 | GROUP(tsin_clk_a, 3, 0), |
| 477 | GROUP(tsin_d0_a, 3, 4), |
| 478 | GROUP(spdif_out_0, 1, 7), |
| 479 | GROUP(xtal_24m, 3, 18), |
| 480 | GROUP(iso7816_2_clk, 5, 7), |
| 481 | GROUP(iso7816_2_data, 5, 6), |
| 482 | |
| 483 | /* bank DV */ |
| 484 | GROUP(pwm_d, 3, 26), |
| 485 | GROUP(pwm_c0, 3, 25), |
| 486 | GROUP(pwm_vs_2, 7, 28), |
| 487 | GROUP(pwm_vs_3, 7, 27), |
| 488 | GROUP(pwm_vs_4, 7, 26), |
| 489 | GROUP(xtal24_out, 7, 25), |
| 490 | GROUP(uart_tx_c, 6, 23), |
| 491 | GROUP(uart_rx_c, 6, 22), |
| 492 | GROUP(uart_cts_c, 6, 21), |
| 493 | GROUP(uart_rts_c, 6, 20), |
| 494 | GROUP(pwm_c1, 3, 24), |
| 495 | GROUP(i2c_sda_a, 9, 31), |
| 496 | GROUP(i2c_sck_a, 9, 30), |
| 497 | GROUP(i2c_sda_b0, 9, 29), |
| 498 | GROUP(i2c_sck_b0, 9, 28), |
| 499 | GROUP(i2c_sda_c0, 9, 27), |
| 500 | GROUP(i2c_sck_c0, 9, 26), |
| 501 | |
| 502 | /* bank H */ |
| 503 | GROUP(hdmi_hpd, 1, 26), |
| 504 | GROUP(hdmi_sda, 1, 25), |
| 505 | GROUP(hdmi_scl, 1, 24), |
| 506 | GROUP(hdmi_cec_0, 1, 23), |
| 507 | GROUP(eth_txd1_0, 7, 21), |
| 508 | GROUP(eth_txd0_0, 7, 20), |
| 509 | GROUP(clk_24m_out, 4, 1), |
| 510 | GROUP(spi_ss1, 8, 11), |
| 511 | GROUP(spi_ss2, 8, 12), |
| 512 | GROUP(spi_ss0_1, 9, 13), |
| 513 | GROUP(spi_miso_1, 9, 12), |
| 514 | GROUP(spi_mosi_1, 9, 11), |
| 515 | GROUP(spi_sclk_1, 9, 10), |
| 516 | GROUP(eth_txd3, 6, 13), |
| 517 | GROUP(eth_txd2, 6, 12), |
| 518 | GROUP(eth_tx_clk, 6, 11), |
| 519 | GROUP(i2c_sda_b1, 5, 27), |
| 520 | GROUP(i2c_sck_b1, 5, 26), |
| 521 | GROUP(i2c_sda_c1, 5, 25), |
| 522 | GROUP(i2c_sck_c1, 5, 24), |
| 523 | GROUP(i2c_sda_d1, 4, 3), |
| 524 | GROUP(i2c_sck_d1, 4, 2), |
| 525 | |
| 526 | /* bank BOOT */ |
| 527 | GROUP(nand_io, 2, 26), |
| 528 | GROUP(nand_io_ce0, 2, 25), |
| 529 | GROUP(nand_io_ce1, 2, 24), |
| 530 | GROUP(nand_io_rb0, 2, 17), |
| 531 | GROUP(nand_ale, 2, 21), |
| 532 | GROUP(nand_cle, 2, 20), |
| 533 | GROUP(nand_wen_clk, 2, 19), |
| 534 | GROUP(nand_ren_clk, 2, 18), |
Martin Blumenstingl | 4781c22 | 2017-04-01 15:59:22 +0200 | [diff] [blame] | 535 | GROUP(nand_dqs_15, 2, 27), |
| 536 | GROUP(nand_dqs_18, 2, 28), |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 537 | GROUP(sdxc_d0_c, 4, 30), |
| 538 | GROUP(sdxc_d13_c, 4, 29), |
| 539 | GROUP(sdxc_d47_c, 4, 28), |
| 540 | GROUP(sdxc_clk_c, 7, 19), |
| 541 | GROUP(sdxc_cmd_c, 7, 18), |
| 542 | GROUP(nor_d, 5, 1), |
| 543 | GROUP(nor_q, 5, 3), |
| 544 | GROUP(nor_c, 5, 2), |
| 545 | GROUP(nor_cs, 5, 0), |
| 546 | GROUP(sd_d0_c, 6, 29), |
| 547 | GROUP(sd_d1_c, 6, 28), |
| 548 | GROUP(sd_d2_c, 6, 27), |
| 549 | GROUP(sd_d3_c, 6, 26), |
| 550 | GROUP(sd_cmd_c, 6, 30), |
| 551 | GROUP(sd_clk_c, 6, 31), |
| 552 | |
| 553 | /* bank CARD */ |
| 554 | GROUP(sd_d1_b, 2, 14), |
| 555 | GROUP(sd_d0_b, 2, 15), |
| 556 | GROUP(sd_clk_b, 2, 11), |
| 557 | GROUP(sd_cmd_b, 2, 10), |
| 558 | GROUP(sd_d3_b, 2, 12), |
| 559 | GROUP(sd_d2_b, 2, 13), |
| 560 | GROUP(sdxc_d13_b, 2, 6), |
| 561 | GROUP(sdxc_d0_b, 2, 7), |
| 562 | GROUP(sdxc_clk_b, 2, 5), |
| 563 | GROUP(sdxc_cmd_b, 2, 4), |
| 564 | |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 565 | /* bank DIF */ |
| 566 | GROUP(eth_rxd1, 6, 0), |
| 567 | GROUP(eth_rxd0, 6, 1), |
| 568 | GROUP(eth_rx_dv, 6, 2), |
| 569 | GROUP(eth_rx_clk, 6, 3), |
| 570 | GROUP(eth_txd0_1, 6, 4), |
| 571 | GROUP(eth_txd1_1, 6, 5), |
Alexander Müller | d6d5c12 | 2016-05-08 19:59:49 +0200 | [diff] [blame] | 572 | GROUP(eth_tx_en, 6, 6), |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 573 | GROUP(eth_ref_clk, 6, 8), |
| 574 | GROUP(eth_mdc, 6, 9), |
| 575 | GROUP(eth_mdio_en, 6, 10), |
Martin Blumenstingl | 27d6de3 | 2019-01-12 13:59:13 +0100 | [diff] [blame] | 576 | GROUP(eth_rxd3, 7, 22), |
| 577 | GROUP(eth_rxd2, 7, 23), |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 578 | }; |
| 579 | |
| 580 | static struct meson_pmx_group meson8b_aobus_groups[] = { |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 581 | GPIO_GROUP(GPIOAO_0), |
| 582 | GPIO_GROUP(GPIOAO_1), |
| 583 | GPIO_GROUP(GPIOAO_2), |
| 584 | GPIO_GROUP(GPIOAO_3), |
| 585 | GPIO_GROUP(GPIOAO_4), |
| 586 | GPIO_GROUP(GPIOAO_5), |
| 587 | GPIO_GROUP(GPIOAO_6), |
| 588 | GPIO_GROUP(GPIOAO_7), |
| 589 | GPIO_GROUP(GPIOAO_8), |
| 590 | GPIO_GROUP(GPIOAO_9), |
| 591 | GPIO_GROUP(GPIOAO_10), |
| 592 | GPIO_GROUP(GPIOAO_11), |
| 593 | GPIO_GROUP(GPIOAO_12), |
| 594 | GPIO_GROUP(GPIOAO_13), |
| 595 | GPIO_GROUP(GPIO_BSD_EN), |
| 596 | GPIO_GROUP(GPIO_TEST_N), |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 597 | |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 598 | /* bank AO */ |
| 599 | GROUP(uart_tx_ao_a, 0, 12), |
| 600 | GROUP(uart_rx_ao_a, 0, 11), |
| 601 | GROUP(uart_cts_ao_a, 0, 10), |
| 602 | GROUP(uart_rts_ao_a, 0, 9), |
| 603 | GROUP(i2c_mst_sck_ao, 0, 6), |
| 604 | GROUP(i2c_mst_sda_ao, 0, 5), |
| 605 | GROUP(clk_32k_in_out, 0, 18), |
| 606 | GROUP(remote_input, 0, 0), |
| 607 | GROUP(hdmi_cec_1, 0, 17), |
| 608 | GROUP(ir_blaster, 0, 31), |
| 609 | GROUP(pwm_c2, 0, 22), |
| 610 | GROUP(i2c_sck_ao, 0, 2), |
| 611 | GROUP(i2c_sda_ao, 0, 1), |
| 612 | GROUP(ir_remote_out, 0, 21), |
| 613 | GROUP(i2s_am_clk_out, 0, 30), |
| 614 | GROUP(i2s_ao_clk_out, 0, 29), |
| 615 | GROUP(i2s_lr_clk_out, 0, 28), |
| 616 | GROUP(i2s_out_01, 0, 27), |
| 617 | GROUP(uart_tx_ao_b0, 0, 26), |
| 618 | GROUP(uart_rx_ao_b0, 0, 25), |
| 619 | GROUP(uart_cts_ao_b, 0, 8), |
| 620 | GROUP(uart_rts_ao_b, 0, 7), |
| 621 | GROUP(uart_tx_ao_b1, 0, 24), |
| 622 | GROUP(uart_rx_ao_b1, 0, 23), |
| 623 | GROUP(spdif_out_1, 0, 16), |
| 624 | GROUP(i2s_in_ch01, 0, 13), |
| 625 | GROUP(i2s_ao_clk_in, 0, 15), |
| 626 | GROUP(i2s_lr_clk_in, 0, 14), |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 627 | }; |
| 628 | |
| 629 | static const char * const gpio_groups[] = { |
| 630 | "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", |
| 631 | "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", |
| 632 | "GPIOX_10", "GPIOX_11", "GPIOX_16", "GPIOX_17", "GPIOX_18", |
| 633 | "GPIOX_19", "GPIOX_20", "GPIOX_21", |
| 634 | |
| 635 | "GPIOY_0", "GPIOY_1", "GPIOY_3", "GPIOY_6", "GPIOY_7", |
| 636 | "GPIOY_8", "GPIOY_9", "GPIOY_10", "GPIOY_11", "GPIOY_12", |
| 637 | "GPIOY_13", "GPIOY_14", |
| 638 | |
| 639 | "GPIODV_9", "GPIODV_24", "GPIODV_25", "GPIODV_26", |
| 640 | "GPIODV_27", "GPIODV_28", "GPIODV_29", |
| 641 | |
| 642 | "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", |
| 643 | "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9", |
| 644 | |
| 645 | "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4", |
| 646 | "CARD_5", "CARD_6", |
| 647 | |
| 648 | "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4", |
| 649 | "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9", |
| 650 | "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", |
| 651 | "BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18", |
| 652 | |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 653 | "DIF_0_P", "DIF_0_N", "DIF_1_P", "DIF_1_N", |
| 654 | "DIF_2_P", "DIF_2_N", "DIF_3_P", "DIF_3_N", |
| 655 | "DIF_4_P", "DIF_4_N" |
| 656 | }; |
| 657 | |
Martin Blumenstingl | a41cd69 | 2018-12-09 20:50:51 +0100 | [diff] [blame] | 658 | static const char * const gpio_aobus_groups[] = { |
| 659 | "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", |
| 660 | "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", |
| 661 | "GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11", |
| 662 | "GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N" |
| 663 | }; |
| 664 | |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 665 | static const char * const sd_a_groups[] = { |
| 666 | "sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a", |
| 667 | "sd_cmd_a" |
| 668 | }; |
| 669 | |
| 670 | static const char * const sdxc_a_groups[] = { |
| 671 | "sdxc_d0_0_a", "sdxc_d13_0_a", "sdxc_d47_a", "sdxc_clk_a", |
Martin Blumenstingl | 13cb60c | 2019-02-09 02:01:01 +0100 | [diff] [blame] | 672 | "sdxc_cmd_a", "sdxc_d0_1_a", "sdxc_d13_1_a" |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 673 | }; |
| 674 | |
| 675 | static const char * const pcm_a_groups[] = { |
| 676 | "pcm_out_a", "pcm_in_a", "pcm_fs_a", "pcm_clk_a" |
| 677 | }; |
| 678 | |
| 679 | static const char * const uart_a_groups[] = { |
| 680 | "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a" |
| 681 | }; |
| 682 | |
| 683 | static const char * const uart_b_groups[] = { |
| 684 | "uart_tx_b0", "uart_rx_b0", "uart_cts_b0", "uart_rts_b0", |
| 685 | "uart_tx_b1", "uart_rx_b1", "uart_cts_b1", "uart_rts_b1" |
| 686 | }; |
| 687 | |
| 688 | static const char * const iso7816_groups[] = { |
| 689 | "iso7816_det", "iso7816_reset", "iso7816_0_clk", "iso7816_0_data", |
| 690 | "iso7816_1_clk", "iso7816_1_data", "iso7816_2_clk", "iso7816_2_data" |
| 691 | }; |
| 692 | |
| 693 | static const char * const i2c_d_groups[] = { |
| 694 | "i2c_sda_d0", "i2c_sck_d0", "i2c_sda_d1", "i2c_sck_d1" |
| 695 | }; |
| 696 | |
| 697 | static const char * const xtal_groups[] = { |
| 698 | "xtal_32k_out", "xtal_24m_out", "xtal_24m", "xtal24_out" |
| 699 | }; |
| 700 | |
| 701 | static const char * const uart_c_groups[] = { |
| 702 | "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c" |
| 703 | }; |
| 704 | |
| 705 | static const char * const i2c_c_groups[] = { |
| 706 | "i2c_sda_c0", "i2c_sck_c0", "i2c_sda_c1", "i2c_sck_c1" |
| 707 | }; |
| 708 | |
| 709 | static const char * const hdmi_groups[] = { |
Carlo Caione | ac1afc4 | 2016-03-01 23:04:33 +0100 | [diff] [blame] | 710 | "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec_0" |
| 711 | }; |
| 712 | |
| 713 | static const char * const hdmi_cec_groups[] = { |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 714 | "hdmi_cec_1" |
| 715 | }; |
| 716 | |
| 717 | static const char * const spi_groups[] = { |
| 718 | "spi_ss0_0", "spi_miso_0", "spi_mosi_0", "spi_sclk_0", |
| 719 | "spi_ss0_1", "spi_ss1", "spi_sclk_1", "spi_mosi_1", |
| 720 | "spi_miso_1", "spi_ss2" |
| 721 | }; |
| 722 | |
| 723 | static const char * const ethernet_groups[] = { |
| 724 | "eth_tx_clk", "eth_tx_en", "eth_txd1_0", "eth_txd1_1", |
| 725 | "eth_txd0_0", "eth_txd0_1", "eth_rx_clk", "eth_rx_dv", |
| 726 | "eth_rxd1", "eth_rxd0", "eth_mdio_en", "eth_mdc", "eth_ref_clk", |
Martin Blumenstingl | 27d6de3 | 2019-01-12 13:59:13 +0100 | [diff] [blame] | 727 | "eth_txd2", "eth_txd3", "eth_rxd3", "eth_rxd2" |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 728 | }; |
| 729 | |
| 730 | static const char * const i2c_a_groups[] = { |
| 731 | "i2c_sda_a", "i2c_sck_a", |
| 732 | }; |
| 733 | |
| 734 | static const char * const i2c_b_groups[] = { |
| 735 | "i2c_sda_b0", "i2c_sck_b0", "i2c_sda_b1", "i2c_sck_b1" |
| 736 | }; |
| 737 | |
| 738 | static const char * const sd_c_groups[] = { |
| 739 | "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c", |
| 740 | "sd_cmd_c", "sd_clk_c" |
| 741 | }; |
| 742 | |
| 743 | static const char * const sdxc_c_groups[] = { |
| 744 | "sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_cmd_c", |
| 745 | "sdxc_clk_c" |
| 746 | }; |
| 747 | |
| 748 | static const char * const nand_groups[] = { |
| 749 | "nand_io", "nand_io_ce0", "nand_io_ce1", |
| 750 | "nand_io_rb0", "nand_ale", "nand_cle", |
Martin Blumenstingl | 4781c22 | 2017-04-01 15:59:22 +0200 | [diff] [blame] | 751 | "nand_wen_clk", "nand_ren_clk", "nand_dqs_15", |
| 752 | "nand_dqs_18" |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 753 | }; |
| 754 | |
| 755 | static const char * const nor_groups[] = { |
| 756 | "nor_d", "nor_q", "nor_c", "nor_cs" |
| 757 | }; |
| 758 | |
| 759 | static const char * const sd_b_groups[] = { |
| 760 | "sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b", |
| 761 | "sd_d3_b", "sd_d2_b" |
| 762 | }; |
| 763 | |
| 764 | static const char * const sdxc_b_groups[] = { |
| 765 | "sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b" |
| 766 | }; |
| 767 | |
| 768 | static const char * const uart_ao_groups[] = { |
| 769 | "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a" |
| 770 | }; |
| 771 | |
| 772 | static const char * const remote_groups[] = { |
| 773 | "remote_input", "ir_blaster", "ir_remote_out" |
| 774 | }; |
| 775 | |
| 776 | static const char * const i2c_slave_ao_groups[] = { |
| 777 | "i2c_sck_ao", "i2c_sda_ao" |
| 778 | }; |
| 779 | |
| 780 | static const char * const uart_ao_b_groups[] = { |
| 781 | "uart_tx_ao_b0", "uart_rx_ao_b0", "uart_tx_ao_b1", "uart_rx_ao_b1", |
| 782 | "uart_cts_ao_b", "uart_rts_ao_b" |
| 783 | }; |
| 784 | |
| 785 | static const char * const i2c_mst_ao_groups[] = { |
| 786 | "i2c_mst_sck_ao", "i2c_mst_sda_ao" |
| 787 | }; |
| 788 | |
Carlo Caione | ac1afc4 | 2016-03-01 23:04:33 +0100 | [diff] [blame] | 789 | static const char * const clk_24m_groups[] = { |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 790 | "clk_24m_out" |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 791 | }; |
| 792 | |
Carlo Caione | ac1afc4 | 2016-03-01 23:04:33 +0100 | [diff] [blame] | 793 | static const char * const clk_32k_groups[] = { |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 794 | "clk_32k_in_out" |
Carlo Caione | ac1afc4 | 2016-03-01 23:04:33 +0100 | [diff] [blame] | 795 | }; |
| 796 | |
| 797 | static const char * const spdif_0_groups[] = { |
| 798 | "spdif_out_0" |
| 799 | }; |
| 800 | |
| 801 | static const char * const spdif_1_groups[] = { |
| 802 | "spdif_out_1" |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 803 | }; |
| 804 | |
| 805 | static const char * const i2s_groups[] = { |
| 806 | "i2s_am_clk_out", "i2s_ao_clk_out", "i2s_lr_clk_out", |
| 807 | "i2s_out_01", "i2s_in_ch01", "i2s_ao_clk_in", |
| 808 | "i2s_lr_clk_in" |
| 809 | }; |
| 810 | |
| 811 | static const char * const pwm_b_groups[] = { |
| 812 | "pwm_b" |
| 813 | }; |
| 814 | |
| 815 | static const char * const pwm_c_groups[] = { |
Carlo Caione | ac1afc4 | 2016-03-01 23:04:33 +0100 | [diff] [blame] | 816 | "pwm_c0", "pwm_c1" |
| 817 | }; |
| 818 | |
| 819 | static const char * const pwm_c_ao_groups[] = { |
| 820 | "pwm_c2" |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 821 | }; |
| 822 | |
| 823 | static const char * const pwm_d_groups[] = { |
| 824 | "pwm_d" |
| 825 | }; |
| 826 | |
| 827 | static const char * const pwm_e_groups[] = { |
| 828 | "pwm_e" |
| 829 | }; |
| 830 | |
| 831 | static const char * const pwm_vs_groups[] = { |
| 832 | "pwm_vs_0", "pwm_vs_1", "pwm_vs_2", |
| 833 | "pwm_vs_3", "pwm_vs_4" |
| 834 | }; |
| 835 | |
| 836 | static const char * const tsin_a_groups[] = { |
| 837 | "tsin_d0_a", "tsin_d17_a", "tsin_clk_a", "tsin_sop_a", |
| 838 | "tsin_d_valid_a" |
| 839 | }; |
| 840 | |
| 841 | static const char * const tsin_b_groups[] = { |
| 842 | "tsin_d0_b", "tsin_clk_b", "tsin_sop_b", "tsin_d_valid_b" |
| 843 | }; |
| 844 | |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 845 | static struct meson_pmx_func meson8b_cbus_functions[] = { |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 846 | FUNCTION(gpio), |
| 847 | FUNCTION(sd_a), |
| 848 | FUNCTION(sdxc_a), |
| 849 | FUNCTION(pcm_a), |
| 850 | FUNCTION(uart_a), |
| 851 | FUNCTION(uart_b), |
| 852 | FUNCTION(iso7816), |
| 853 | FUNCTION(i2c_d), |
| 854 | FUNCTION(xtal), |
| 855 | FUNCTION(uart_c), |
| 856 | FUNCTION(i2c_c), |
| 857 | FUNCTION(hdmi), |
| 858 | FUNCTION(spi), |
| 859 | FUNCTION(ethernet), |
| 860 | FUNCTION(i2c_a), |
| 861 | FUNCTION(i2c_b), |
| 862 | FUNCTION(sd_c), |
| 863 | FUNCTION(sdxc_c), |
| 864 | FUNCTION(nand), |
| 865 | FUNCTION(nor), |
| 866 | FUNCTION(sd_b), |
| 867 | FUNCTION(sdxc_b), |
Carlo Caione | ac1afc4 | 2016-03-01 23:04:33 +0100 | [diff] [blame] | 868 | FUNCTION(spdif_0), |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 869 | FUNCTION(pwm_b), |
| 870 | FUNCTION(pwm_c), |
| 871 | FUNCTION(pwm_d), |
| 872 | FUNCTION(pwm_e), |
| 873 | FUNCTION(pwm_vs), |
| 874 | FUNCTION(tsin_a), |
| 875 | FUNCTION(tsin_b), |
Carlo Caione | ac1afc4 | 2016-03-01 23:04:33 +0100 | [diff] [blame] | 876 | FUNCTION(clk_24m), |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 877 | }; |
| 878 | |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 879 | static struct meson_pmx_func meson8b_aobus_functions[] = { |
Martin Blumenstingl | a41cd69 | 2018-12-09 20:50:51 +0100 | [diff] [blame] | 880 | FUNCTION(gpio_aobus), |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 881 | FUNCTION(uart_ao), |
| 882 | FUNCTION(uart_ao_b), |
| 883 | FUNCTION(i2c_slave_ao), |
| 884 | FUNCTION(i2c_mst_ao), |
| 885 | FUNCTION(i2s), |
| 886 | FUNCTION(remote), |
| 887 | FUNCTION(clk_32k), |
| 888 | FUNCTION(pwm_c_ao), |
| 889 | FUNCTION(spdif_1), |
| 890 | FUNCTION(hdmi_cec), |
| 891 | }; |
| 892 | |
| 893 | static struct meson_bank meson8b_cbus_banks[] = { |
Martin Blumenstingl | 55af415 | 2018-02-25 12:38:53 +0100 | [diff] [blame] | 894 | /* name first last irq pullen pull dir out in */ |
| 895 | BANK("X0..11", GPIOX_0, GPIOX_11, 97, 108, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), |
| 896 | BANK("X16..21", GPIOX_16, GPIOX_21, 113, 118, 4, 16, 4, 16, 0, 16, 1, 16, 2, 16), |
| 897 | BANK("Y0..1", GPIOY_0, GPIOY_1, 80, 81, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), |
| 898 | BANK("Y3", GPIOY_3, GPIOY_3, 83, 83, 3, 3, 3, 3, 3, 3, 4, 3, 5, 3), |
| 899 | BANK("Y6..14", GPIOY_6, GPIOY_14, 86, 94, 3, 6, 3, 6, 3, 6, 4, 6, 5, 6), |
| 900 | BANK("DV9", GPIODV_9, GPIODV_9, 59, 59, 0, 9, 0, 9, 7, 9, 8, 9, 9, 9), |
| 901 | BANK("DV24..29", GPIODV_24, GPIODV_29, 74, 79, 0, 24, 0, 24, 7, 24, 8, 24, 9, 24), |
| 902 | BANK("H", GPIOH_0, GPIOH_9, 14, 23, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), |
| 903 | BANK("CARD", CARD_0, CARD_6, 43, 49, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), |
| 904 | BANK("BOOT", BOOT_0, BOOT_18, 24, 42, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), |
Jerome Brunet | 6c9dc84 | 2017-06-08 21:37:50 +0200 | [diff] [blame] | 905 | |
| 906 | /* |
| 907 | * The following bank is not mentionned in the public datasheet |
| 908 | * There is no information whether it can be used with the gpio |
| 909 | * interrupt controller |
| 910 | */ |
Martin Blumenstingl | 55af415 | 2018-02-25 12:38:53 +0100 | [diff] [blame] | 911 | BANK("DIF", DIF_0_P, DIF_4_N, -1, -1, 5, 8, 5, 8, 12, 12, 13, 12, 14, 12), |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 912 | }; |
| 913 | |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 914 | static struct meson_bank meson8b_aobus_banks[] = { |
Jerome Brunet | 634e40b | 2017-09-20 15:39:20 +0200 | [diff] [blame] | 915 | /* name first lastc irq pullen pull dir out in */ |
Jerome Brunet | c4b25ef | 2018-10-29 16:13:40 +0100 | [diff] [blame] | 916 | BANK("AO", GPIOAO_0, GPIO_TEST_N, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0), |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 917 | }; |
| 918 | |
Jerome Brunet | 277d14e | 2017-10-12 14:40:25 +0200 | [diff] [blame] | 919 | static struct meson_pinctrl_data meson8b_cbus_pinctrl_data = { |
Beniamino Galvani | db80f0e | 2016-08-13 19:41:18 +0200 | [diff] [blame] | 920 | .name = "cbus-banks", |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 921 | .pins = meson8b_cbus_pins, |
| 922 | .groups = meson8b_cbus_groups, |
| 923 | .funcs = meson8b_cbus_functions, |
Beniamino Galvani | db80f0e | 2016-08-13 19:41:18 +0200 | [diff] [blame] | 924 | .banks = meson8b_cbus_banks, |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 925 | .num_pins = ARRAY_SIZE(meson8b_cbus_pins), |
| 926 | .num_groups = ARRAY_SIZE(meson8b_cbus_groups), |
| 927 | .num_funcs = ARRAY_SIZE(meson8b_cbus_functions), |
Beniamino Galvani | db80f0e | 2016-08-13 19:41:18 +0200 | [diff] [blame] | 928 | .num_banks = ARRAY_SIZE(meson8b_cbus_banks), |
Jerome Brunet | ce385aa | 2017-10-12 14:40:26 +0200 | [diff] [blame] | 929 | .pmx_ops = &meson8_pmx_ops, |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 930 | }; |
| 931 | |
Jerome Brunet | 277d14e | 2017-10-12 14:40:25 +0200 | [diff] [blame] | 932 | static struct meson_pinctrl_data meson8b_aobus_pinctrl_data = { |
Beniamino Galvani | db80f0e | 2016-08-13 19:41:18 +0200 | [diff] [blame] | 933 | .name = "aobus-banks", |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 934 | .pins = meson8b_aobus_pins, |
| 935 | .groups = meson8b_aobus_groups, |
| 936 | .funcs = meson8b_aobus_functions, |
Beniamino Galvani | db80f0e | 2016-08-13 19:41:18 +0200 | [diff] [blame] | 937 | .banks = meson8b_aobus_banks, |
Carlo Caione | 9dab186 | 2016-03-01 23:04:34 +0100 | [diff] [blame] | 938 | .num_pins = ARRAY_SIZE(meson8b_aobus_pins), |
| 939 | .num_groups = ARRAY_SIZE(meson8b_aobus_groups), |
| 940 | .num_funcs = ARRAY_SIZE(meson8b_aobus_functions), |
Beniamino Galvani | db80f0e | 2016-08-13 19:41:18 +0200 | [diff] [blame] | 941 | .num_banks = ARRAY_SIZE(meson8b_aobus_banks), |
Jerome Brunet | ce385aa | 2017-10-12 14:40:26 +0200 | [diff] [blame] | 942 | .pmx_ops = &meson8_pmx_ops, |
Carlo Caione | 0fefcb6 | 2015-03-29 12:56:42 +0200 | [diff] [blame] | 943 | }; |
Jerome Brunet | 277d14e | 2017-10-12 14:40:25 +0200 | [diff] [blame] | 944 | |
| 945 | static const struct of_device_id meson8b_pinctrl_dt_match[] = { |
| 946 | { |
| 947 | .compatible = "amlogic,meson8b-cbus-pinctrl", |
| 948 | .data = &meson8b_cbus_pinctrl_data, |
| 949 | }, |
| 950 | { |
| 951 | .compatible = "amlogic,meson8b-aobus-pinctrl", |
| 952 | .data = &meson8b_aobus_pinctrl_data, |
| 953 | }, |
| 954 | { }, |
| 955 | }; |
| 956 | |
| 957 | static struct platform_driver meson8b_pinctrl_driver = { |
| 958 | .probe = meson_pinctrl_probe, |
| 959 | .driver = { |
| 960 | .name = "meson8b-pinctrl", |
| 961 | .of_match_table = meson8b_pinctrl_dt_match, |
| 962 | }, |
| 963 | }; |
| 964 | builtin_platform_driver(meson8b_pinctrl_driver); |