Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2007-2009 ST-Ericsson AB |
| 3 | * License terms: GNU General Public License (GPL) version 2 |
| 4 | * ST DDC I2C master mode driver, used in e.g. U300 series platforms. |
| 5 | * Author: Linus Walleij <linus.walleij@stericsson.com> |
| 6 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> |
| 7 | */ |
| 8 | #include <linux/init.h> |
| 9 | #include <linux/module.h> |
| 10 | #include <linux/platform_device.h> |
| 11 | #include <linux/delay.h> |
| 12 | #include <linux/i2c.h> |
| 13 | #include <linux/spinlock.h> |
| 14 | #include <linux/completion.h> |
| 15 | #include <linux/err.h> |
| 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/clk.h> |
| 18 | #include <linux/io.h> |
| 19 | |
| 20 | /* the name of this kernel module */ |
| 21 | #define NAME "stu300" |
| 22 | |
| 23 | /* CR (Control Register) 8bit (R/W) */ |
| 24 | #define I2C_CR (0x00000000) |
| 25 | #define I2C_CR_RESET_VALUE (0x00) |
| 26 | #define I2C_CR_RESET_UMASK (0x00) |
| 27 | #define I2C_CR_DDC1_ENABLE (0x80) |
| 28 | #define I2C_CR_TRANS_ENABLE (0x40) |
| 29 | #define I2C_CR_PERIPHERAL_ENABLE (0x20) |
| 30 | #define I2C_CR_DDC2B_ENABLE (0x10) |
| 31 | #define I2C_CR_START_ENABLE (0x08) |
| 32 | #define I2C_CR_ACK_ENABLE (0x04) |
| 33 | #define I2C_CR_STOP_ENABLE (0x02) |
| 34 | #define I2C_CR_INTERRUPT_ENABLE (0x01) |
| 35 | /* SR1 (Status Register 1) 8bit (R/-) */ |
| 36 | #define I2C_SR1 (0x00000004) |
| 37 | #define I2C_SR1_RESET_VALUE (0x00) |
| 38 | #define I2C_SR1_RESET_UMASK (0x00) |
| 39 | #define I2C_SR1_EVF_IND (0x80) |
| 40 | #define I2C_SR1_ADD10_IND (0x40) |
| 41 | #define I2C_SR1_TRA_IND (0x20) |
| 42 | #define I2C_SR1_BUSY_IND (0x10) |
| 43 | #define I2C_SR1_BTF_IND (0x08) |
| 44 | #define I2C_SR1_ADSL_IND (0x04) |
| 45 | #define I2C_SR1_MSL_IND (0x02) |
| 46 | #define I2C_SR1_SB_IND (0x01) |
| 47 | /* SR2 (Status Register 2) 8bit (R/-) */ |
| 48 | #define I2C_SR2 (0x00000008) |
| 49 | #define I2C_SR2_RESET_VALUE (0x00) |
| 50 | #define I2C_SR2_RESET_UMASK (0x40) |
| 51 | #define I2C_SR2_MASK (0xBF) |
| 52 | #define I2C_SR2_SCLFAL_IND (0x80) |
| 53 | #define I2C_SR2_ENDAD_IND (0x20) |
| 54 | #define I2C_SR2_AF_IND (0x10) |
| 55 | #define I2C_SR2_STOPF_IND (0x08) |
| 56 | #define I2C_SR2_ARLO_IND (0x04) |
| 57 | #define I2C_SR2_BERR_IND (0x02) |
| 58 | #define I2C_SR2_DDC2BF_IND (0x01) |
| 59 | /* CCR (Clock Control Register) 8bit (R/W) */ |
| 60 | #define I2C_CCR (0x0000000C) |
| 61 | #define I2C_CCR_RESET_VALUE (0x00) |
| 62 | #define I2C_CCR_RESET_UMASK (0x00) |
| 63 | #define I2C_CCR_MASK (0xFF) |
| 64 | #define I2C_CCR_FMSM (0x80) |
| 65 | #define I2C_CCR_CC_MASK (0x7F) |
| 66 | /* OAR1 (Own Address Register 1) 8bit (R/W) */ |
| 67 | #define I2C_OAR1 (0x00000010) |
| 68 | #define I2C_OAR1_RESET_VALUE (0x00) |
| 69 | #define I2C_OAR1_RESET_UMASK (0x00) |
| 70 | #define I2C_OAR1_ADD_MASK (0xFF) |
| 71 | /* OAR2 (Own Address Register 2) 8bit (R/W) */ |
| 72 | #define I2C_OAR2 (0x00000014) |
| 73 | #define I2C_OAR2_RESET_VALUE (0x40) |
| 74 | #define I2C_OAR2_RESET_UMASK (0x19) |
| 75 | #define I2C_OAR2_MASK (0xE6) |
| 76 | #define I2C_OAR2_FR_25_10MHZ (0x00) |
| 77 | #define I2C_OAR2_FR_10_1667MHZ (0x20) |
| 78 | #define I2C_OAR2_FR_1667_2667MHZ (0x40) |
| 79 | #define I2C_OAR2_FR_2667_40MHZ (0x60) |
| 80 | #define I2C_OAR2_FR_40_5333MHZ (0x80) |
| 81 | #define I2C_OAR2_FR_5333_66MHZ (0xA0) |
| 82 | #define I2C_OAR2_FR_66_80MHZ (0xC0) |
| 83 | #define I2C_OAR2_FR_80_100MHZ (0xE0) |
| 84 | #define I2C_OAR2_FR_MASK (0xE0) |
| 85 | #define I2C_OAR2_ADD_MASK (0x06) |
| 86 | /* DR (Data Register) 8bit (R/W) */ |
| 87 | #define I2C_DR (0x00000018) |
| 88 | #define I2C_DR_RESET_VALUE (0x00) |
| 89 | #define I2C_DR_RESET_UMASK (0xFF) |
| 90 | #define I2C_DR_D_MASK (0xFF) |
| 91 | /* ECCR (Extended Clock Control Register) 8bit (R/W) */ |
| 92 | #define I2C_ECCR (0x0000001C) |
| 93 | #define I2C_ECCR_RESET_VALUE (0x00) |
| 94 | #define I2C_ECCR_RESET_UMASK (0xE0) |
| 95 | #define I2C_ECCR_MASK (0x1F) |
| 96 | #define I2C_ECCR_CC_MASK (0x1F) |
| 97 | |
| 98 | /* |
| 99 | * These events are more or less responses to commands |
| 100 | * sent into the hardware, presumably reflecting the state |
| 101 | * of an internal state machine. |
| 102 | */ |
| 103 | enum stu300_event { |
| 104 | STU300_EVENT_NONE = 0, |
| 105 | STU300_EVENT_1, |
| 106 | STU300_EVENT_2, |
| 107 | STU300_EVENT_3, |
| 108 | STU300_EVENT_4, |
| 109 | STU300_EVENT_5, |
| 110 | STU300_EVENT_6, |
| 111 | STU300_EVENT_7, |
| 112 | STU300_EVENT_8, |
| 113 | STU300_EVENT_9 |
| 114 | }; |
| 115 | |
| 116 | enum stu300_error { |
| 117 | STU300_ERROR_NONE = 0, |
| 118 | STU300_ERROR_ACKNOWLEDGE_FAILURE, |
| 119 | STU300_ERROR_BUS_ERROR, |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 120 | STU300_ERROR_ARBITRATION_LOST, |
| 121 | STU300_ERROR_UNKNOWN |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 122 | }; |
| 123 | |
| 124 | /* timeout waiting for the controller to respond */ |
| 125 | #define STU300_TIMEOUT (msecs_to_jiffies(1000)) |
| 126 | |
| 127 | /* |
| 128 | * The number of address send athemps tried before giving up. |
| 129 | * If the first one failes it seems like 5 to 8 attempts are required. |
| 130 | */ |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 131 | #define NUM_ADDR_RESEND_ATTEMPTS 12 |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 132 | |
| 133 | /* I2C clock speed, in Hz 0-400kHz*/ |
| 134 | static unsigned int scl_frequency = 100000; |
| 135 | module_param(scl_frequency, uint, 0644); |
| 136 | |
| 137 | /** |
| 138 | * struct stu300_dev - the stu300 driver state holder |
| 139 | * @pdev: parent platform device |
| 140 | * @adapter: corresponding I2C adapter |
| 141 | * @phybase: location of I/O area in memory |
| 142 | * @physize: size of I/O area in memory |
| 143 | * @clk: hardware block clock |
| 144 | * @irq: assigned interrupt line |
| 145 | * @cmd_issue_lock: this locks the following cmd_ variables |
| 146 | * @cmd_complete: acknowledge completion for an I2C command |
| 147 | * @cmd_event: expected event coming in as a response to a command |
| 148 | * @cmd_err: error code as response to a command |
| 149 | * @speed: current bus speed in Hz |
| 150 | * @msg_index: index of current message |
| 151 | * @msg_len: length of current message |
| 152 | */ |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 153 | |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 154 | struct stu300_dev { |
| 155 | struct platform_device *pdev; |
| 156 | struct i2c_adapter adapter; |
| 157 | resource_size_t phybase; |
| 158 | resource_size_t physize; |
| 159 | void __iomem *virtbase; |
| 160 | struct clk *clk; |
| 161 | int irq; |
| 162 | spinlock_t cmd_issue_lock; |
| 163 | struct completion cmd_complete; |
| 164 | enum stu300_event cmd_event; |
| 165 | enum stu300_error cmd_err; |
| 166 | unsigned int speed; |
| 167 | int msg_index; |
| 168 | int msg_len; |
| 169 | }; |
| 170 | |
| 171 | /* Local forward function declarations */ |
| 172 | static int stu300_init_hw(struct stu300_dev *dev); |
| 173 | |
| 174 | /* |
| 175 | * The block needs writes in both MSW and LSW in order |
| 176 | * for all data lines to reach their destination. |
| 177 | */ |
| 178 | static inline void stu300_wr8(u32 value, void __iomem *address) |
| 179 | { |
| 180 | writel((value << 16) | value, address); |
| 181 | } |
| 182 | |
| 183 | /* |
| 184 | * This merely masks off the duplicates which appear |
| 185 | * in bytes 1-3. You _MUST_ use 32-bit bus access on this |
| 186 | * device, else it will not work. |
| 187 | */ |
| 188 | static inline u32 stu300_r8(void __iomem *address) |
| 189 | { |
| 190 | return readl(address) & 0x000000FFU; |
| 191 | } |
| 192 | |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 193 | static void stu300_irq_enable(struct stu300_dev *dev) |
| 194 | { |
| 195 | u32 val; |
| 196 | val = stu300_r8(dev->virtbase + I2C_CR); |
| 197 | val |= I2C_CR_INTERRUPT_ENABLE; |
| 198 | /* Twice paranoia (possible HW glitch) */ |
| 199 | stu300_wr8(val, dev->virtbase + I2C_CR); |
| 200 | stu300_wr8(val, dev->virtbase + I2C_CR); |
| 201 | } |
| 202 | |
| 203 | static void stu300_irq_disable(struct stu300_dev *dev) |
| 204 | { |
| 205 | u32 val; |
| 206 | val = stu300_r8(dev->virtbase + I2C_CR); |
| 207 | val &= ~I2C_CR_INTERRUPT_ENABLE; |
| 208 | /* Twice paranoia (possible HW glitch) */ |
| 209 | stu300_wr8(val, dev->virtbase + I2C_CR); |
| 210 | stu300_wr8(val, dev->virtbase + I2C_CR); |
| 211 | } |
| 212 | |
| 213 | |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 214 | /* |
| 215 | * Tells whether a certain event or events occurred in |
| 216 | * response to a command. The events represent states in |
| 217 | * the internal state machine of the hardware. The events |
| 218 | * are not very well described in the hardware |
| 219 | * documentation and can only be treated as abstract state |
| 220 | * machine states. |
| 221 | * |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 222 | * @ret 0 = event has not occurred or unknown error, any |
| 223 | * other value means the correct event occurred or an error. |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 224 | */ |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 225 | |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 226 | static int stu300_event_occurred(struct stu300_dev *dev, |
| 227 | enum stu300_event mr_event) { |
| 228 | u32 status1; |
| 229 | u32 status2; |
| 230 | |
| 231 | /* What event happened? */ |
| 232 | status1 = stu300_r8(dev->virtbase + I2C_SR1); |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 233 | |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 234 | if (!(status1 & I2C_SR1_EVF_IND)) |
| 235 | /* No event at all */ |
| 236 | return 0; |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 237 | |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 238 | status2 = stu300_r8(dev->virtbase + I2C_SR2); |
| 239 | |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 240 | /* Block any multiple interrupts */ |
| 241 | stu300_irq_disable(dev); |
| 242 | |
| 243 | /* Check for errors first */ |
| 244 | if (status2 & I2C_SR2_AF_IND) { |
| 245 | dev->cmd_err = STU300_ERROR_ACKNOWLEDGE_FAILURE; |
| 246 | return 1; |
| 247 | } else if (status2 & I2C_SR2_BERR_IND) { |
| 248 | dev->cmd_err = STU300_ERROR_BUS_ERROR; |
| 249 | return 1; |
| 250 | } else if (status2 & I2C_SR2_ARLO_IND) { |
| 251 | dev->cmd_err = STU300_ERROR_ARBITRATION_LOST; |
| 252 | return 1; |
| 253 | } |
| 254 | |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 255 | switch (mr_event) { |
| 256 | case STU300_EVENT_1: |
| 257 | if (status1 & I2C_SR1_ADSL_IND) |
| 258 | return 1; |
| 259 | break; |
| 260 | case STU300_EVENT_2: |
| 261 | case STU300_EVENT_3: |
| 262 | case STU300_EVENT_7: |
| 263 | case STU300_EVENT_8: |
| 264 | if (status1 & I2C_SR1_BTF_IND) { |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 265 | return 1; |
| 266 | } |
| 267 | break; |
| 268 | case STU300_EVENT_4: |
| 269 | if (status2 & I2C_SR2_STOPF_IND) |
| 270 | return 1; |
| 271 | break; |
| 272 | case STU300_EVENT_5: |
| 273 | if (status1 & I2C_SR1_SB_IND) |
| 274 | /* Clear start bit */ |
| 275 | return 1; |
| 276 | break; |
| 277 | case STU300_EVENT_6: |
| 278 | if (status2 & I2C_SR2_ENDAD_IND) { |
| 279 | /* First check for any errors */ |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 280 | return 1; |
| 281 | } |
| 282 | break; |
| 283 | case STU300_EVENT_9: |
| 284 | if (status1 & I2C_SR1_ADD10_IND) |
| 285 | return 1; |
| 286 | break; |
| 287 | default: |
| 288 | break; |
| 289 | } |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 290 | /* If we get here, we're on thin ice. |
| 291 | * Here we are in a status where we have |
| 292 | * gotten a response that does not match |
| 293 | * what we requested. |
| 294 | */ |
| 295 | dev->cmd_err = STU300_ERROR_UNKNOWN; |
| 296 | dev_err(&dev->pdev->dev, |
| 297 | "Unhandled interrupt! %d sr1: 0x%x sr2: 0x%x\n", |
| 298 | mr_event, status1, status2); |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 299 | return 0; |
| 300 | } |
| 301 | |
| 302 | static irqreturn_t stu300_irh(int irq, void *data) |
| 303 | { |
| 304 | struct stu300_dev *dev = data; |
| 305 | int res; |
| 306 | |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 307 | /* Just make sure that the block is clocked */ |
| 308 | clk_enable(dev->clk); |
| 309 | |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 310 | /* See if this was what we were waiting for */ |
| 311 | spin_lock(&dev->cmd_issue_lock); |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 312 | |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 313 | res = stu300_event_occurred(dev, dev->cmd_event); |
| 314 | if (res || dev->cmd_err != STU300_ERROR_NONE) |
| 315 | complete(&dev->cmd_complete); |
| 316 | |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 317 | spin_unlock(&dev->cmd_issue_lock); |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 318 | |
| 319 | clk_disable(dev->clk); |
| 320 | |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 321 | return IRQ_HANDLED; |
| 322 | } |
| 323 | |
| 324 | /* |
| 325 | * Sends a command and then waits for the bits masked by *flagmask* |
| 326 | * to go high or low by IRQ awaiting. |
| 327 | */ |
| 328 | static int stu300_start_and_await_event(struct stu300_dev *dev, |
| 329 | u8 cr_value, |
| 330 | enum stu300_event mr_event) |
| 331 | { |
| 332 | int ret; |
| 333 | |
| 334 | if (unlikely(irqs_disabled())) { |
| 335 | /* TODO: implement polling for this case if need be. */ |
| 336 | WARN(1, "irqs are disabled, cannot poll for event\n"); |
| 337 | return -EIO; |
| 338 | } |
| 339 | |
| 340 | /* Lock command issue, fill in an event we wait for */ |
| 341 | spin_lock_irq(&dev->cmd_issue_lock); |
| 342 | init_completion(&dev->cmd_complete); |
| 343 | dev->cmd_err = STU300_ERROR_NONE; |
| 344 | dev->cmd_event = mr_event; |
| 345 | spin_unlock_irq(&dev->cmd_issue_lock); |
| 346 | |
| 347 | /* Turn on interrupt, send command and wait. */ |
| 348 | cr_value |= I2C_CR_INTERRUPT_ENABLE; |
| 349 | stu300_wr8(cr_value, dev->virtbase + I2C_CR); |
| 350 | ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, |
| 351 | STU300_TIMEOUT); |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 352 | if (ret < 0) { |
| 353 | dev_err(&dev->pdev->dev, |
| 354 | "wait_for_completion_interruptible_timeout() " |
| 355 | "returned %d waiting for event %04x\n", ret, mr_event); |
| 356 | return ret; |
| 357 | } |
| 358 | |
| 359 | if (ret == 0) { |
| 360 | dev_err(&dev->pdev->dev, "controller timed out " |
| 361 | "waiting for event %d, reinit hardware\n", mr_event); |
| 362 | (void) stu300_init_hw(dev); |
| 363 | return -ETIMEDOUT; |
| 364 | } |
| 365 | |
| 366 | if (dev->cmd_err != STU300_ERROR_NONE) { |
| 367 | dev_err(&dev->pdev->dev, "controller (start) " |
| 368 | "error %d waiting for event %d, reinit hardware\n", |
| 369 | dev->cmd_err, mr_event); |
| 370 | (void) stu300_init_hw(dev); |
| 371 | return -EIO; |
| 372 | } |
| 373 | |
| 374 | return 0; |
| 375 | } |
| 376 | |
| 377 | /* |
| 378 | * This waits for a flag to be set, if it is not set on entry, an interrupt is |
| 379 | * configured to wait for the flag using a completion. |
| 380 | */ |
| 381 | static int stu300_await_event(struct stu300_dev *dev, |
| 382 | enum stu300_event mr_event) |
| 383 | { |
| 384 | int ret; |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 385 | |
| 386 | if (unlikely(irqs_disabled())) { |
| 387 | /* TODO: implement polling for this case if need be. */ |
| 388 | dev_err(&dev->pdev->dev, "irqs are disabled on this " |
| 389 | "system!\n"); |
| 390 | return -EIO; |
| 391 | } |
| 392 | |
| 393 | /* Is it already here? */ |
| 394 | spin_lock_irq(&dev->cmd_issue_lock); |
| 395 | dev->cmd_err = STU300_ERROR_NONE; |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 396 | dev->cmd_event = mr_event; |
| 397 | |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 398 | init_completion(&dev->cmd_complete); |
| 399 | |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 400 | /* Turn on the I2C interrupt for current operation */ |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 401 | stu300_irq_enable(dev); |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 402 | |
| 403 | /* Unlock the command block and wait for the event to occur */ |
| 404 | spin_unlock_irq(&dev->cmd_issue_lock); |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 405 | |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 406 | ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, |
| 407 | STU300_TIMEOUT); |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 408 | if (ret < 0) { |
| 409 | dev_err(&dev->pdev->dev, |
| 410 | "wait_for_completion_interruptible_timeout()" |
| 411 | "returned %d waiting for event %04x\n", ret, mr_event); |
| 412 | return ret; |
| 413 | } |
| 414 | |
| 415 | if (ret == 0) { |
| 416 | if (mr_event != STU300_EVENT_6) { |
| 417 | dev_err(&dev->pdev->dev, "controller " |
| 418 | "timed out waiting for event %d, reinit " |
| 419 | "hardware\n", mr_event); |
| 420 | (void) stu300_init_hw(dev); |
| 421 | } |
| 422 | return -ETIMEDOUT; |
| 423 | } |
| 424 | |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 425 | if (dev->cmd_err != STU300_ERROR_NONE) { |
| 426 | if (mr_event != STU300_EVENT_6) { |
| 427 | dev_err(&dev->pdev->dev, "controller " |
| 428 | "error (await_event) %d waiting for event %d, " |
| 429 | "reinit hardware\n", dev->cmd_err, mr_event); |
| 430 | (void) stu300_init_hw(dev); |
| 431 | } |
| 432 | return -EIO; |
| 433 | } |
| 434 | |
| 435 | return 0; |
| 436 | } |
| 437 | |
| 438 | /* |
| 439 | * Waits for the busy bit to go low by repeated polling. |
| 440 | */ |
| 441 | #define BUSY_RELEASE_ATTEMPTS 10 |
| 442 | static int stu300_wait_while_busy(struct stu300_dev *dev) |
| 443 | { |
| 444 | unsigned long timeout; |
| 445 | int i; |
| 446 | |
| 447 | for (i = 0; i < BUSY_RELEASE_ATTEMPTS; i++) { |
| 448 | timeout = jiffies + STU300_TIMEOUT; |
| 449 | |
| 450 | while (!time_after(jiffies, timeout)) { |
| 451 | /* Is not busy? */ |
| 452 | if ((stu300_r8(dev->virtbase + I2C_SR1) & |
| 453 | I2C_SR1_BUSY_IND) == 0) |
| 454 | return 0; |
| 455 | msleep(1); |
| 456 | } |
| 457 | |
| 458 | dev_err(&dev->pdev->dev, "transaction timed out " |
| 459 | "waiting for device to be free (not busy). " |
| 460 | "Attempt: %d\n", i+1); |
| 461 | |
| 462 | dev_err(&dev->pdev->dev, "base address = " |
| 463 | "0x%08x, reinit hardware\n", (u32) dev->virtbase); |
| 464 | |
| 465 | (void) stu300_init_hw(dev); |
| 466 | } |
| 467 | |
| 468 | dev_err(&dev->pdev->dev, "giving up after %d attempts " |
| 469 | "to reset the bus.\n", BUSY_RELEASE_ATTEMPTS); |
| 470 | |
| 471 | return -ETIMEDOUT; |
| 472 | } |
| 473 | |
| 474 | struct stu300_clkset { |
| 475 | unsigned long rate; |
| 476 | u32 setting; |
| 477 | }; |
| 478 | |
| 479 | static const struct stu300_clkset stu300_clktable[] = { |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 480 | { 0, 0xFFU }, |
| 481 | { 2500000, I2C_OAR2_FR_25_10MHZ }, |
| 482 | { 10000000, I2C_OAR2_FR_10_1667MHZ }, |
| 483 | { 16670000, I2C_OAR2_FR_1667_2667MHZ }, |
| 484 | { 26670000, I2C_OAR2_FR_2667_40MHZ }, |
| 485 | { 40000000, I2C_OAR2_FR_40_5333MHZ }, |
| 486 | { 53330000, I2C_OAR2_FR_5333_66MHZ }, |
| 487 | { 66000000, I2C_OAR2_FR_66_80MHZ }, |
| 488 | { 80000000, I2C_OAR2_FR_80_100MHZ }, |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 489 | { 100000000, 0xFFU }, |
| 490 | }; |
| 491 | |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 492 | |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 493 | static int stu300_set_clk(struct stu300_dev *dev, unsigned long clkrate) |
| 494 | { |
| 495 | |
| 496 | u32 val; |
| 497 | int i = 0; |
| 498 | |
| 499 | /* Locate the apropriate clock setting */ |
| 500 | while (i < ARRAY_SIZE(stu300_clktable) && |
| 501 | stu300_clktable[i].rate < clkrate) |
| 502 | i++; |
| 503 | |
| 504 | if (stu300_clktable[i].setting == 0xFFU) { |
| 505 | dev_err(&dev->pdev->dev, "too %s clock rate requested " |
| 506 | "(%lu Hz).\n", i ? "high" : "low", clkrate); |
| 507 | return -EINVAL; |
| 508 | } |
| 509 | |
| 510 | stu300_wr8(stu300_clktable[i].setting, |
| 511 | dev->virtbase + I2C_OAR2); |
| 512 | |
| 513 | dev_dbg(&dev->pdev->dev, "Clock rate %lu Hz, I2C bus speed %d Hz " |
| 514 | "virtbase %p\n", clkrate, dev->speed, dev->virtbase); |
| 515 | |
| 516 | if (dev->speed > 100000) |
| 517 | /* Fast Mode I2C */ |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 518 | val = ((clkrate/dev->speed) - 9)/3 + 1; |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 519 | else |
| 520 | /* Standard Mode I2C */ |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 521 | val = ((clkrate/dev->speed) - 7)/2 + 1; |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 522 | |
| 523 | /* According to spec the divider must be > 2 */ |
| 524 | if (val < 0x002) { |
| 525 | dev_err(&dev->pdev->dev, "too low clock rate (%lu Hz).\n", |
| 526 | clkrate); |
| 527 | return -EINVAL; |
| 528 | } |
| 529 | |
| 530 | /* We have 12 bits clock divider only! */ |
| 531 | if (val & 0xFFFFF000U) { |
| 532 | dev_err(&dev->pdev->dev, "too high clock rate (%lu Hz).\n", |
| 533 | clkrate); |
| 534 | return -EINVAL; |
| 535 | } |
| 536 | |
| 537 | if (dev->speed > 100000) { |
| 538 | /* CC6..CC0 */ |
| 539 | stu300_wr8((val & I2C_CCR_CC_MASK) | I2C_CCR_FMSM, |
| 540 | dev->virtbase + I2C_CCR); |
| 541 | dev_dbg(&dev->pdev->dev, "set clock divider to 0x%08x, " |
| 542 | "Fast Mode I2C\n", val); |
| 543 | } else { |
| 544 | /* CC6..CC0 */ |
| 545 | stu300_wr8((val & I2C_CCR_CC_MASK), |
| 546 | dev->virtbase + I2C_CCR); |
| 547 | dev_dbg(&dev->pdev->dev, "set clock divider to " |
| 548 | "0x%08x, Standard Mode I2C\n", val); |
| 549 | } |
| 550 | |
| 551 | /* CC11..CC7 */ |
| 552 | stu300_wr8(((val >> 7) & 0x1F), |
| 553 | dev->virtbase + I2C_ECCR); |
| 554 | |
| 555 | return 0; |
| 556 | } |
| 557 | |
| 558 | |
| 559 | static int stu300_init_hw(struct stu300_dev *dev) |
| 560 | { |
| 561 | u32 dummy; |
| 562 | unsigned long clkrate; |
| 563 | int ret; |
| 564 | |
| 565 | /* Disable controller */ |
| 566 | stu300_wr8(0x00, dev->virtbase + I2C_CR); |
| 567 | /* |
| 568 | * Set own address to some default value (0x00). |
| 569 | * We do not support slave mode anyway. |
| 570 | */ |
| 571 | stu300_wr8(0x00, dev->virtbase + I2C_OAR1); |
| 572 | /* |
| 573 | * The I2C controller only operates properly in 26 MHz but we |
| 574 | * program this driver as if we didn't know. This will also set the two |
| 575 | * high bits of the own address to zero as well. |
| 576 | * There is no known hardware issue with running in 13 MHz |
| 577 | * However, speeds over 200 kHz are not used. |
| 578 | */ |
| 579 | clkrate = clk_get_rate(dev->clk); |
| 580 | ret = stu300_set_clk(dev, clkrate); |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 581 | |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 582 | if (ret) |
| 583 | return ret; |
| 584 | /* |
| 585 | * Enable block, do it TWICE (hardware glitch) |
| 586 | * Setting bit 7 can enable DDC mode. (Not used currently.) |
| 587 | */ |
| 588 | stu300_wr8(I2C_CR_PERIPHERAL_ENABLE, |
| 589 | dev->virtbase + I2C_CR); |
| 590 | stu300_wr8(I2C_CR_PERIPHERAL_ENABLE, |
| 591 | dev->virtbase + I2C_CR); |
| 592 | /* Make a dummy read of the status register SR1 & SR2 */ |
| 593 | dummy = stu300_r8(dev->virtbase + I2C_SR2); |
| 594 | dummy = stu300_r8(dev->virtbase + I2C_SR1); |
| 595 | |
| 596 | return 0; |
| 597 | } |
| 598 | |
| 599 | |
| 600 | |
| 601 | /* Send slave address. */ |
| 602 | static int stu300_send_address(struct stu300_dev *dev, |
| 603 | struct i2c_msg *msg, int resend) |
| 604 | { |
| 605 | u32 val; |
| 606 | int ret; |
| 607 | |
| 608 | if (msg->flags & I2C_M_TEN) |
| 609 | /* This is probably how 10 bit addresses look */ |
| 610 | val = (0xf0 | (((u32) msg->addr & 0x300) >> 7)) & |
| 611 | I2C_DR_D_MASK; |
| 612 | else |
| 613 | val = ((msg->addr << 1) & I2C_DR_D_MASK); |
| 614 | |
| 615 | if (msg->flags & I2C_M_RD) { |
| 616 | /* This is the direction bit */ |
| 617 | val |= 0x01; |
| 618 | if (resend) |
| 619 | dev_dbg(&dev->pdev->dev, "read resend\n"); |
| 620 | } else if (resend) |
| 621 | dev_dbg(&dev->pdev->dev, "write resend\n"); |
| 622 | stu300_wr8(val, dev->virtbase + I2C_DR); |
| 623 | |
| 624 | /* For 10bit addressing, await 10bit request (EVENT 9) */ |
| 625 | if (msg->flags & I2C_M_TEN) { |
| 626 | ret = stu300_await_event(dev, STU300_EVENT_9); |
| 627 | /* |
| 628 | * The slave device wants a 10bit address, send the rest |
| 629 | * of the bits (the LSBits) |
| 630 | */ |
| 631 | val = msg->addr & I2C_DR_D_MASK; |
| 632 | /* This clears "event 9" */ |
| 633 | stu300_wr8(val, dev->virtbase + I2C_DR); |
| 634 | if (ret != 0) |
| 635 | return ret; |
| 636 | } |
| 637 | /* FIXME: Why no else here? two events for 10bit? |
| 638 | * Await event 6 (normal) or event 9 (10bit) |
| 639 | */ |
| 640 | |
| 641 | if (resend) |
| 642 | dev_dbg(&dev->pdev->dev, "await event 6\n"); |
| 643 | ret = stu300_await_event(dev, STU300_EVENT_6); |
| 644 | |
| 645 | /* |
| 646 | * Clear any pending EVENT 6 no matter what happend during |
| 647 | * await_event. |
| 648 | */ |
| 649 | val = stu300_r8(dev->virtbase + I2C_CR); |
| 650 | val |= I2C_CR_PERIPHERAL_ENABLE; |
| 651 | stu300_wr8(val, dev->virtbase + I2C_CR); |
| 652 | |
| 653 | return ret; |
| 654 | } |
| 655 | |
| 656 | static int stu300_xfer_msg(struct i2c_adapter *adap, |
| 657 | struct i2c_msg *msg, int stop) |
| 658 | { |
| 659 | u32 cr; |
| 660 | u32 val; |
| 661 | u32 i; |
| 662 | int ret; |
| 663 | int attempts = 0; |
| 664 | struct stu300_dev *dev = i2c_get_adapdata(adap); |
| 665 | |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 666 | clk_enable(dev->clk); |
| 667 | |
| 668 | /* Remove this if (0) to trace each and every message. */ |
| 669 | if (0) { |
| 670 | dev_dbg(&dev->pdev->dev, "I2C message to: 0x%04x, len: %d, " |
| 671 | "flags: 0x%04x, stop: %d\n", |
| 672 | msg->addr, msg->len, msg->flags, stop); |
| 673 | } |
| 674 | |
| 675 | /* Zero-length messages are not supported by this hardware */ |
| 676 | if (msg->len == 0) { |
| 677 | ret = -EINVAL; |
| 678 | goto exit_disable; |
| 679 | } |
| 680 | |
| 681 | /* |
| 682 | * For some reason, sending the address sometimes fails when running |
| 683 | * on the 13 MHz clock. No interrupt arrives. This is a work around, |
| 684 | * which tries to restart and send the address up to 10 times before |
| 685 | * really giving up. Usually 5 to 8 attempts are enough. |
| 686 | */ |
| 687 | do { |
| 688 | if (attempts) |
| 689 | dev_dbg(&dev->pdev->dev, "wait while busy\n"); |
| 690 | /* Check that the bus is free, or wait until some timeout */ |
| 691 | ret = stu300_wait_while_busy(dev); |
| 692 | if (ret != 0) |
| 693 | goto exit_disable; |
| 694 | |
| 695 | if (attempts) |
| 696 | dev_dbg(&dev->pdev->dev, "re-int hw\n"); |
| 697 | /* |
| 698 | * According to ST, there is no problem if the clock is |
| 699 | * changed between 13 and 26 MHz during a transfer. |
| 700 | */ |
| 701 | ret = stu300_init_hw(dev); |
| 702 | if (ret) |
| 703 | goto exit_disable; |
| 704 | |
| 705 | /* Send a start condition */ |
| 706 | cr = I2C_CR_PERIPHERAL_ENABLE; |
| 707 | /* Setting the START bit puts the block in master mode */ |
| 708 | if (!(msg->flags & I2C_M_NOSTART)) |
| 709 | cr |= I2C_CR_START_ENABLE; |
| 710 | if ((msg->flags & I2C_M_RD) && (msg->len > 1)) |
| 711 | /* On read more than 1 byte, we need ack. */ |
| 712 | cr |= I2C_CR_ACK_ENABLE; |
| 713 | /* Check that it gets through */ |
| 714 | if (!(msg->flags & I2C_M_NOSTART)) { |
| 715 | if (attempts) |
| 716 | dev_dbg(&dev->pdev->dev, "send start event\n"); |
| 717 | ret = stu300_start_and_await_event(dev, cr, |
| 718 | STU300_EVENT_5); |
| 719 | } |
| 720 | |
| 721 | if (attempts) |
| 722 | dev_dbg(&dev->pdev->dev, "send address\n"); |
| 723 | |
| 724 | if (ret == 0) |
| 725 | /* Send address */ |
| 726 | ret = stu300_send_address(dev, msg, attempts != 0); |
| 727 | |
| 728 | if (ret != 0) { |
| 729 | attempts++; |
| 730 | dev_dbg(&dev->pdev->dev, "failed sending address, " |
| 731 | "retrying. Attempt: %d msg_index: %d/%d\n", |
| 732 | attempts, dev->msg_index, dev->msg_len); |
| 733 | } |
| 734 | |
| 735 | } while (ret != 0 && attempts < NUM_ADDR_RESEND_ATTEMPTS); |
| 736 | |
| 737 | if (attempts < NUM_ADDR_RESEND_ATTEMPTS && attempts > 0) { |
| 738 | dev_dbg(&dev->pdev->dev, "managed to get address " |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 739 | "through after %d attempts\n", attempts); |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 740 | } else if (attempts == NUM_ADDR_RESEND_ATTEMPTS) { |
| 741 | dev_dbg(&dev->pdev->dev, "I give up, tried %d times " |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 742 | "to resend address.\n", |
| 743 | NUM_ADDR_RESEND_ATTEMPTS); |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 744 | goto exit_disable; |
| 745 | } |
| 746 | |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 747 | |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 748 | if (msg->flags & I2C_M_RD) { |
| 749 | /* READ: we read the actual bytes one at a time */ |
| 750 | for (i = 0; i < msg->len; i++) { |
| 751 | if (i == msg->len-1) { |
| 752 | /* |
| 753 | * Disable ACK and set STOP condition before |
| 754 | * reading last byte |
| 755 | */ |
| 756 | val = I2C_CR_PERIPHERAL_ENABLE; |
| 757 | |
| 758 | if (stop) |
| 759 | val |= I2C_CR_STOP_ENABLE; |
| 760 | |
| 761 | stu300_wr8(val, |
| 762 | dev->virtbase + I2C_CR); |
| 763 | } |
| 764 | /* Wait for this byte... */ |
| 765 | ret = stu300_await_event(dev, STU300_EVENT_7); |
| 766 | if (ret != 0) |
| 767 | goto exit_disable; |
| 768 | /* This clears event 7 */ |
| 769 | msg->buf[i] = (u8) stu300_r8(dev->virtbase + I2C_DR); |
| 770 | } |
| 771 | } else { |
| 772 | /* WRITE: we send the actual bytes one at a time */ |
| 773 | for (i = 0; i < msg->len; i++) { |
| 774 | /* Write the byte */ |
| 775 | stu300_wr8(msg->buf[i], |
| 776 | dev->virtbase + I2C_DR); |
| 777 | /* Check status */ |
| 778 | ret = stu300_await_event(dev, STU300_EVENT_8); |
| 779 | /* Next write to DR will clear event 8 */ |
| 780 | if (ret != 0) { |
| 781 | dev_err(&dev->pdev->dev, "error awaiting " |
| 782 | "event 8 (%d)\n", ret); |
| 783 | goto exit_disable; |
| 784 | } |
| 785 | } |
| 786 | /* Check NAK */ |
| 787 | if (!(msg->flags & I2C_M_IGNORE_NAK)) { |
| 788 | if (stu300_r8(dev->virtbase + I2C_SR2) & |
| 789 | I2C_SR2_AF_IND) { |
| 790 | dev_err(&dev->pdev->dev, "I2C payload " |
| 791 | "send returned NAK!\n"); |
| 792 | ret = -EIO; |
| 793 | goto exit_disable; |
| 794 | } |
| 795 | } |
| 796 | if (stop) { |
| 797 | /* Send stop condition */ |
| 798 | val = I2C_CR_PERIPHERAL_ENABLE; |
| 799 | val |= I2C_CR_STOP_ENABLE; |
| 800 | stu300_wr8(val, dev->virtbase + I2C_CR); |
| 801 | } |
| 802 | } |
| 803 | |
| 804 | /* Check that the bus is free, or wait until some timeout occurs */ |
| 805 | ret = stu300_wait_while_busy(dev); |
| 806 | if (ret != 0) { |
| 807 | dev_err(&dev->pdev->dev, "timout waiting for transfer " |
| 808 | "to commence.\n"); |
| 809 | goto exit_disable; |
| 810 | } |
| 811 | |
| 812 | /* Dummy read status registers */ |
| 813 | val = stu300_r8(dev->virtbase + I2C_SR2); |
| 814 | val = stu300_r8(dev->virtbase + I2C_SR1); |
| 815 | ret = 0; |
| 816 | |
| 817 | exit_disable: |
| 818 | /* Disable controller */ |
| 819 | stu300_wr8(0x00, dev->virtbase + I2C_CR); |
| 820 | clk_disable(dev->clk); |
| 821 | return ret; |
| 822 | } |
| 823 | |
| 824 | static int stu300_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, |
| 825 | int num) |
| 826 | { |
| 827 | int ret = -1; |
| 828 | int i; |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 829 | |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 830 | struct stu300_dev *dev = i2c_get_adapdata(adap); |
| 831 | dev->msg_len = num; |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 832 | |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 833 | for (i = 0; i < num; i++) { |
| 834 | /* |
| 835 | * Another driver appears to send stop for each message, |
| 836 | * here we only do that for the last message. Possibly some |
| 837 | * peripherals require this behaviour, then their drivers |
| 838 | * have to send single messages in order to get "stop" for |
| 839 | * each message. |
| 840 | */ |
| 841 | dev->msg_index = i; |
| 842 | |
| 843 | ret = stu300_xfer_msg(adap, &msgs[i], (i == (num - 1))); |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 844 | |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 845 | if (ret != 0) { |
| 846 | num = ret; |
| 847 | break; |
| 848 | } |
| 849 | } |
| 850 | |
| 851 | return num; |
| 852 | } |
| 853 | |
| 854 | static u32 stu300_func(struct i2c_adapter *adap) |
| 855 | { |
| 856 | /* This is the simplest thing you can think of... */ |
| 857 | return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR; |
| 858 | } |
| 859 | |
| 860 | static const struct i2c_algorithm stu300_algo = { |
| 861 | .master_xfer = stu300_xfer, |
| 862 | .functionality = stu300_func, |
| 863 | }; |
| 864 | |
| 865 | static int __init |
| 866 | stu300_probe(struct platform_device *pdev) |
| 867 | { |
| 868 | struct stu300_dev *dev; |
| 869 | struct i2c_adapter *adap; |
| 870 | struct resource *res; |
| 871 | int bus_nr; |
| 872 | int ret = 0; |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 873 | char clk_name[] = "I2C0"; |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 874 | |
| 875 | dev = kzalloc(sizeof(struct stu300_dev), GFP_KERNEL); |
| 876 | if (!dev) { |
| 877 | dev_err(&pdev->dev, "could not allocate device struct\n"); |
| 878 | ret = -ENOMEM; |
| 879 | goto err_no_devmem; |
| 880 | } |
| 881 | |
| 882 | bus_nr = pdev->id; |
Linus Walleij | c37faaf | 2009-08-13 22:14:23 +0200 | [diff] [blame] | 883 | clk_name[3] += (char)bus_nr; |
| 884 | dev->clk = clk_get(&pdev->dev, clk_name); |
Linus Walleij | 18904c0 | 2009-06-13 21:51:34 +0200 | [diff] [blame] | 885 | if (IS_ERR(dev->clk)) { |
| 886 | ret = PTR_ERR(dev->clk); |
| 887 | dev_err(&pdev->dev, "could not retrieve i2c bus clock\n"); |
| 888 | goto err_no_clk; |
| 889 | } |
| 890 | |
| 891 | dev->pdev = pdev; |
| 892 | platform_set_drvdata(pdev, dev); |
| 893 | |
| 894 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 895 | if (!res) { |
| 896 | ret = -ENOENT; |
| 897 | goto err_no_resource; |
| 898 | } |
| 899 | |
| 900 | dev->phybase = res->start; |
| 901 | dev->physize = resource_size(res); |
| 902 | |
| 903 | if (request_mem_region(dev->phybase, dev->physize, |
| 904 | NAME " I/O Area") == NULL) { |
| 905 | ret = -EBUSY; |
| 906 | goto err_no_ioregion; |
| 907 | } |
| 908 | |
| 909 | dev->virtbase = ioremap(dev->phybase, dev->physize); |
| 910 | dev_dbg(&pdev->dev, "initialize bus device I2C%d on virtual " |
| 911 | "base %p\n", bus_nr, dev->virtbase); |
| 912 | if (!dev->virtbase) { |
| 913 | ret = -ENOMEM; |
| 914 | goto err_no_ioremap; |
| 915 | } |
| 916 | |
| 917 | dev->irq = platform_get_irq(pdev, 0); |
| 918 | if (request_irq(dev->irq, stu300_irh, IRQF_DISABLED, |
| 919 | NAME, dev)) { |
| 920 | ret = -EIO; |
| 921 | goto err_no_irq; |
| 922 | } |
| 923 | |
| 924 | dev->speed = scl_frequency; |
| 925 | |
| 926 | clk_enable(dev->clk); |
| 927 | ret = stu300_init_hw(dev); |
| 928 | clk_disable(dev->clk); |
| 929 | |
| 930 | if (ret != 0) { |
| 931 | dev_err(&dev->pdev->dev, "error initializing hardware.\n"); |
| 932 | goto err_init_hw; |
| 933 | } |
| 934 | |
| 935 | /* IRQ event handling initialization */ |
| 936 | spin_lock_init(&dev->cmd_issue_lock); |
| 937 | dev->cmd_event = STU300_EVENT_NONE; |
| 938 | dev->cmd_err = STU300_ERROR_NONE; |
| 939 | |
| 940 | adap = &dev->adapter; |
| 941 | adap->owner = THIS_MODULE; |
| 942 | /* DDC class but actually often used for more generic I2C */ |
| 943 | adap->class = I2C_CLASS_DDC; |
| 944 | strncpy(adap->name, "ST Microelectronics DDC I2C adapter", |
| 945 | sizeof(adap->name)); |
| 946 | adap->nr = bus_nr; |
| 947 | adap->algo = &stu300_algo; |
| 948 | adap->dev.parent = &pdev->dev; |
| 949 | i2c_set_adapdata(adap, dev); |
| 950 | |
| 951 | /* i2c device drivers may be active on return from add_adapter() */ |
| 952 | ret = i2c_add_numbered_adapter(adap); |
| 953 | if (ret) { |
| 954 | dev_err(&dev->pdev->dev, "failure adding ST Micro DDC " |
| 955 | "I2C adapter\n"); |
| 956 | goto err_add_adapter; |
| 957 | } |
| 958 | return 0; |
| 959 | |
| 960 | err_add_adapter: |
| 961 | err_init_hw: |
| 962 | free_irq(dev->irq, dev); |
| 963 | err_no_irq: |
| 964 | iounmap(dev->virtbase); |
| 965 | err_no_ioremap: |
| 966 | release_mem_region(dev->phybase, dev->physize); |
| 967 | err_no_ioregion: |
| 968 | platform_set_drvdata(pdev, NULL); |
| 969 | err_no_resource: |
| 970 | clk_put(dev->clk); |
| 971 | err_no_clk: |
| 972 | kfree(dev); |
| 973 | err_no_devmem: |
| 974 | dev_err(&pdev->dev, "failed to add " NAME " adapter: %d\n", |
| 975 | pdev->id); |
| 976 | return ret; |
| 977 | } |
| 978 | |
| 979 | #ifdef CONFIG_PM |
| 980 | static int stu300_suspend(struct platform_device *pdev, pm_message_t state) |
| 981 | { |
| 982 | struct stu300_dev *dev = platform_get_drvdata(pdev); |
| 983 | |
| 984 | /* Turn off everything */ |
| 985 | stu300_wr8(0x00, dev->virtbase + I2C_CR); |
| 986 | return 0; |
| 987 | } |
| 988 | |
| 989 | static int stu300_resume(struct platform_device *pdev) |
| 990 | { |
| 991 | int ret = 0; |
| 992 | struct stu300_dev *dev = platform_get_drvdata(pdev); |
| 993 | |
| 994 | clk_enable(dev->clk); |
| 995 | ret = stu300_init_hw(dev); |
| 996 | clk_disable(dev->clk); |
| 997 | |
| 998 | if (ret != 0) |
| 999 | dev_err(&pdev->dev, "error re-initializing hardware.\n"); |
| 1000 | return ret; |
| 1001 | } |
| 1002 | #else |
| 1003 | #define stu300_suspend NULL |
| 1004 | #define stu300_resume NULL |
| 1005 | #endif |
| 1006 | |
| 1007 | static int __exit |
| 1008 | stu300_remove(struct platform_device *pdev) |
| 1009 | { |
| 1010 | struct stu300_dev *dev = platform_get_drvdata(pdev); |
| 1011 | |
| 1012 | i2c_del_adapter(&dev->adapter); |
| 1013 | /* Turn off everything */ |
| 1014 | stu300_wr8(0x00, dev->virtbase + I2C_CR); |
| 1015 | free_irq(dev->irq, dev); |
| 1016 | iounmap(dev->virtbase); |
| 1017 | release_mem_region(dev->phybase, dev->physize); |
| 1018 | clk_put(dev->clk); |
| 1019 | platform_set_drvdata(pdev, NULL); |
| 1020 | kfree(dev); |
| 1021 | return 0; |
| 1022 | } |
| 1023 | |
| 1024 | static struct platform_driver stu300_i2c_driver = { |
| 1025 | .driver = { |
| 1026 | .name = NAME, |
| 1027 | .owner = THIS_MODULE, |
| 1028 | }, |
| 1029 | .remove = __exit_p(stu300_remove), |
| 1030 | .suspend = stu300_suspend, |
| 1031 | .resume = stu300_resume, |
| 1032 | |
| 1033 | }; |
| 1034 | |
| 1035 | static int __init stu300_init(void) |
| 1036 | { |
| 1037 | return platform_driver_probe(&stu300_i2c_driver, stu300_probe); |
| 1038 | } |
| 1039 | |
| 1040 | static void __exit stu300_exit(void) |
| 1041 | { |
| 1042 | platform_driver_unregister(&stu300_i2c_driver); |
| 1043 | } |
| 1044 | |
| 1045 | /* |
| 1046 | * The systems using this bus often have very basic devices such |
| 1047 | * as regulators on the I2C bus, so this needs to be loaded early. |
| 1048 | * Therefore it is registered in the subsys_initcall(). |
| 1049 | */ |
| 1050 | subsys_initcall(stu300_init); |
| 1051 | module_exit(stu300_exit); |
| 1052 | |
| 1053 | MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); |
| 1054 | MODULE_DESCRIPTION("ST Micro DDC I2C adapter (" NAME ")"); |
| 1055 | MODULE_LICENSE("GPL"); |
| 1056 | MODULE_ALIAS("platform:" NAME); |