Ville Syrjälä | 7ff89ca | 2017-02-07 20:33:05 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2006-2017 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | #include "intel_drv.h" |
| 25 | |
| 26 | /** |
| 27 | * DOC: CDCLK / RAWCLK |
| 28 | * |
| 29 | * The display engine uses several different clocks to do its work. There |
| 30 | * are two main clocks involved that aren't directly related to the actual |
| 31 | * pixel clock or any symbol/bit clock of the actual output port. These |
| 32 | * are the core display clock (CDCLK) and RAWCLK. |
| 33 | * |
| 34 | * CDCLK clocks most of the display pipe logic, and thus its frequency |
| 35 | * must be high enough to support the rate at which pixels are flowing |
| 36 | * through the pipes. Downscaling must also be accounted as that increases |
| 37 | * the effective pixel rate. |
| 38 | * |
| 39 | * On several platforms the CDCLK frequency can be changed dynamically |
| 40 | * to minimize power consumption for a given display configuration. |
| 41 | * Typically changes to the CDCLK frequency require all the display pipes |
| 42 | * to be shut down while the frequency is being changed. |
| 43 | * |
| 44 | * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. |
| 45 | * DMC will not change the active CDCLK frequency however, so that part |
| 46 | * will still be performed by the driver directly. |
| 47 | * |
| 48 | * RAWCLK is a fixed frequency clock, often used by various auxiliary |
| 49 | * blocks such as AUX CH or backlight PWM. Hence the only thing we |
| 50 | * really need to know about RAWCLK is its frequency so that various |
| 51 | * dividers can be programmed correctly. |
| 52 | */ |
| 53 | |
| 54 | static int fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv) |
| 55 | { |
| 56 | return 133333; |
| 57 | } |
| 58 | |
| 59 | static int fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv) |
| 60 | { |
| 61 | return 200000; |
| 62 | } |
| 63 | |
| 64 | static int fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv) |
| 65 | { |
| 66 | return 266667; |
| 67 | } |
| 68 | |
| 69 | static int fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv) |
| 70 | { |
| 71 | return 333333; |
| 72 | } |
| 73 | |
| 74 | static int fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv) |
| 75 | { |
| 76 | return 400000; |
| 77 | } |
| 78 | |
| 79 | static int fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv) |
| 80 | { |
| 81 | return 450000; |
| 82 | } |
| 83 | |
| 84 | static int i85x_get_cdclk(struct drm_i915_private *dev_priv) |
| 85 | { |
| 86 | struct pci_dev *pdev = dev_priv->drm.pdev; |
| 87 | u16 hpllcc = 0; |
| 88 | |
| 89 | /* |
| 90 | * 852GM/852GMV only supports 133 MHz and the HPLLCC |
| 91 | * encoding is different :( |
| 92 | * FIXME is this the right way to detect 852GM/852GMV? |
| 93 | */ |
| 94 | if (pdev->revision == 0x1) |
| 95 | return 133333; |
| 96 | |
| 97 | pci_bus_read_config_word(pdev->bus, |
| 98 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); |
| 99 | |
| 100 | /* Assume that the hardware is in the high speed state. This |
| 101 | * should be the default. |
| 102 | */ |
| 103 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
| 104 | case GC_CLOCK_133_200: |
| 105 | case GC_CLOCK_133_200_2: |
| 106 | case GC_CLOCK_100_200: |
| 107 | return 200000; |
| 108 | case GC_CLOCK_166_250: |
| 109 | return 250000; |
| 110 | case GC_CLOCK_100_133: |
| 111 | return 133333; |
| 112 | case GC_CLOCK_133_266: |
| 113 | case GC_CLOCK_133_266_2: |
| 114 | case GC_CLOCK_166_266: |
| 115 | return 266667; |
| 116 | } |
| 117 | |
| 118 | /* Shouldn't happen */ |
| 119 | return 0; |
| 120 | } |
| 121 | |
| 122 | static int i915gm_get_cdclk(struct drm_i915_private *dev_priv) |
| 123 | { |
| 124 | struct pci_dev *pdev = dev_priv->drm.pdev; |
| 125 | u16 gcfgc = 0; |
| 126 | |
| 127 | pci_read_config_word(pdev, GCFGC, &gcfgc); |
| 128 | |
| 129 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
| 130 | return 133333; |
| 131 | |
| 132 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
| 133 | case GC_DISPLAY_CLOCK_333_320_MHZ: |
| 134 | return 333333; |
| 135 | default: |
| 136 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
| 137 | return 190000; |
| 138 | } |
| 139 | } |
| 140 | |
| 141 | static int i945gm_get_cdclk(struct drm_i915_private *dev_priv) |
| 142 | { |
| 143 | struct pci_dev *pdev = dev_priv->drm.pdev; |
| 144 | u16 gcfgc = 0; |
| 145 | |
| 146 | pci_read_config_word(pdev, GCFGC, &gcfgc); |
| 147 | |
| 148 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
| 149 | return 133333; |
| 150 | |
| 151 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
| 152 | case GC_DISPLAY_CLOCK_333_320_MHZ: |
| 153 | return 320000; |
| 154 | default: |
| 155 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
| 156 | return 200000; |
| 157 | } |
| 158 | } |
| 159 | |
| 160 | static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) |
| 161 | { |
| 162 | static const unsigned int blb_vco[8] = { |
| 163 | [0] = 3200000, |
| 164 | [1] = 4000000, |
| 165 | [2] = 5333333, |
| 166 | [3] = 4800000, |
| 167 | [4] = 6400000, |
| 168 | }; |
| 169 | static const unsigned int pnv_vco[8] = { |
| 170 | [0] = 3200000, |
| 171 | [1] = 4000000, |
| 172 | [2] = 5333333, |
| 173 | [3] = 4800000, |
| 174 | [4] = 2666667, |
| 175 | }; |
| 176 | static const unsigned int cl_vco[8] = { |
| 177 | [0] = 3200000, |
| 178 | [1] = 4000000, |
| 179 | [2] = 5333333, |
| 180 | [3] = 6400000, |
| 181 | [4] = 3333333, |
| 182 | [5] = 3566667, |
| 183 | [6] = 4266667, |
| 184 | }; |
| 185 | static const unsigned int elk_vco[8] = { |
| 186 | [0] = 3200000, |
| 187 | [1] = 4000000, |
| 188 | [2] = 5333333, |
| 189 | [3] = 4800000, |
| 190 | }; |
| 191 | static const unsigned int ctg_vco[8] = { |
| 192 | [0] = 3200000, |
| 193 | [1] = 4000000, |
| 194 | [2] = 5333333, |
| 195 | [3] = 6400000, |
| 196 | [4] = 2666667, |
| 197 | [5] = 4266667, |
| 198 | }; |
| 199 | const unsigned int *vco_table; |
| 200 | unsigned int vco; |
| 201 | uint8_t tmp = 0; |
| 202 | |
| 203 | /* FIXME other chipsets? */ |
| 204 | if (IS_GM45(dev_priv)) |
| 205 | vco_table = ctg_vco; |
| 206 | else if (IS_G4X(dev_priv)) |
| 207 | vco_table = elk_vco; |
| 208 | else if (IS_I965GM(dev_priv)) |
| 209 | vco_table = cl_vco; |
| 210 | else if (IS_PINEVIEW(dev_priv)) |
| 211 | vco_table = pnv_vco; |
| 212 | else if (IS_G33(dev_priv)) |
| 213 | vco_table = blb_vco; |
| 214 | else |
| 215 | return 0; |
| 216 | |
| 217 | tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); |
| 218 | |
| 219 | vco = vco_table[tmp & 0x7]; |
| 220 | if (vco == 0) |
| 221 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); |
| 222 | else |
| 223 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); |
| 224 | |
| 225 | return vco; |
| 226 | } |
| 227 | |
| 228 | static int g33_get_cdclk(struct drm_i915_private *dev_priv) |
| 229 | { |
| 230 | struct pci_dev *pdev = dev_priv->drm.pdev; |
| 231 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; |
| 232 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; |
| 233 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; |
| 234 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; |
| 235 | const uint8_t *div_table; |
| 236 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv); |
| 237 | uint16_t tmp = 0; |
| 238 | |
| 239 | pci_read_config_word(pdev, GCFGC, &tmp); |
| 240 | |
| 241 | cdclk_sel = (tmp >> 4) & 0x7; |
| 242 | |
| 243 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) |
| 244 | goto fail; |
| 245 | |
| 246 | switch (vco) { |
| 247 | case 3200000: |
| 248 | div_table = div_3200; |
| 249 | break; |
| 250 | case 4000000: |
| 251 | div_table = div_4000; |
| 252 | break; |
| 253 | case 4800000: |
| 254 | div_table = div_4800; |
| 255 | break; |
| 256 | case 5333333: |
| 257 | div_table = div_5333; |
| 258 | break; |
| 259 | default: |
| 260 | goto fail; |
| 261 | } |
| 262 | |
| 263 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); |
| 264 | |
| 265 | fail: |
| 266 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", |
| 267 | vco, tmp); |
| 268 | return 190476; |
| 269 | } |
| 270 | |
| 271 | static int pnv_get_cdclk(struct drm_i915_private *dev_priv) |
| 272 | { |
| 273 | struct pci_dev *pdev = dev_priv->drm.pdev; |
| 274 | u16 gcfgc = 0; |
| 275 | |
| 276 | pci_read_config_word(pdev, GCFGC, &gcfgc); |
| 277 | |
| 278 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
| 279 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: |
| 280 | return 266667; |
| 281 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
| 282 | return 333333; |
| 283 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
| 284 | return 444444; |
| 285 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
| 286 | return 200000; |
| 287 | default: |
| 288 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); |
| 289 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: |
| 290 | return 133333; |
| 291 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
| 292 | return 166667; |
| 293 | } |
| 294 | } |
| 295 | |
| 296 | static int i965gm_get_cdclk(struct drm_i915_private *dev_priv) |
| 297 | { |
| 298 | struct pci_dev *pdev = dev_priv->drm.pdev; |
| 299 | static const uint8_t div_3200[] = { 16, 10, 8 }; |
| 300 | static const uint8_t div_4000[] = { 20, 12, 10 }; |
| 301 | static const uint8_t div_5333[] = { 24, 16, 14 }; |
| 302 | const uint8_t *div_table; |
| 303 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv); |
| 304 | uint16_t tmp = 0; |
| 305 | |
| 306 | pci_read_config_word(pdev, GCFGC, &tmp); |
| 307 | |
| 308 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; |
| 309 | |
| 310 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) |
| 311 | goto fail; |
| 312 | |
| 313 | switch (vco) { |
| 314 | case 3200000: |
| 315 | div_table = div_3200; |
| 316 | break; |
| 317 | case 4000000: |
| 318 | div_table = div_4000; |
| 319 | break; |
| 320 | case 5333333: |
| 321 | div_table = div_5333; |
| 322 | break; |
| 323 | default: |
| 324 | goto fail; |
| 325 | } |
| 326 | |
| 327 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); |
| 328 | |
| 329 | fail: |
| 330 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", |
| 331 | vco, tmp); |
| 332 | return 200000; |
| 333 | } |
| 334 | |
| 335 | static int gm45_get_cdclk(struct drm_i915_private *dev_priv) |
| 336 | { |
| 337 | struct pci_dev *pdev = dev_priv->drm.pdev; |
| 338 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv); |
| 339 | uint16_t tmp = 0; |
| 340 | |
| 341 | pci_read_config_word(pdev, GCFGC, &tmp); |
| 342 | |
| 343 | cdclk_sel = (tmp >> 12) & 0x1; |
| 344 | |
| 345 | switch (vco) { |
| 346 | case 2666667: |
| 347 | case 4000000: |
| 348 | case 5333333: |
| 349 | return cdclk_sel ? 333333 : 222222; |
| 350 | case 3200000: |
| 351 | return cdclk_sel ? 320000 : 228571; |
| 352 | default: |
| 353 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", |
| 354 | vco, tmp); |
| 355 | return 222222; |
| 356 | } |
| 357 | } |
| 358 | |
| 359 | static int hsw_get_cdclk(struct drm_i915_private *dev_priv) |
| 360 | { |
| 361 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
| 362 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; |
| 363 | |
| 364 | if (lcpll & LCPLL_CD_SOURCE_FCLK) |
| 365 | return 800000; |
| 366 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
| 367 | return 450000; |
| 368 | else if (freq == LCPLL_CLK_FREQ_450) |
| 369 | return 450000; |
| 370 | else if (IS_HSW_ULT(dev_priv)) |
| 371 | return 337500; |
| 372 | else |
| 373 | return 540000; |
| 374 | } |
| 375 | |
| 376 | static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, |
| 377 | int max_pixclk) |
| 378 | { |
| 379 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? |
| 380 | 333333 : 320000; |
| 381 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
| 382 | |
| 383 | /* |
| 384 | * We seem to get an unstable or solid color picture at 200MHz. |
| 385 | * Not sure what's wrong. For now use 200MHz only when all pipes |
| 386 | * are off. |
| 387 | */ |
| 388 | if (!IS_CHERRYVIEW(dev_priv) && |
| 389 | max_pixclk > freq_320*limit/100) |
| 390 | return 400000; |
| 391 | else if (max_pixclk > 266667*limit/100) |
| 392 | return freq_320; |
| 393 | else if (max_pixclk > 0) |
| 394 | return 266667; |
| 395 | else |
| 396 | return 200000; |
| 397 | } |
| 398 | |
| 399 | static int vlv_get_cdclk(struct drm_i915_private *dev_priv) |
| 400 | { |
| 401 | return vlv_get_cck_clock_hpll(dev_priv, "cdclk", |
| 402 | CCK_DISPLAY_CLOCK_CONTROL); |
| 403 | } |
| 404 | |
| 405 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
| 406 | { |
| 407 | unsigned int credits, default_credits; |
| 408 | |
| 409 | if (IS_CHERRYVIEW(dev_priv)) |
| 410 | default_credits = PFI_CREDIT(12); |
| 411 | else |
| 412 | default_credits = PFI_CREDIT(8); |
| 413 | |
| 414 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
| 415 | /* CHV suggested value is 31 or 63 */ |
| 416 | if (IS_CHERRYVIEW(dev_priv)) |
| 417 | credits = PFI_CREDIT_63; |
| 418 | else |
| 419 | credits = PFI_CREDIT(15); |
| 420 | } else { |
| 421 | credits = default_credits; |
| 422 | } |
| 423 | |
| 424 | /* |
| 425 | * WA - write default credits before re-programming |
| 426 | * FIXME: should we also set the resend bit here? |
| 427 | */ |
| 428 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | |
| 429 | default_credits); |
| 430 | |
| 431 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | |
| 432 | credits | PFI_CREDIT_RESEND); |
| 433 | |
| 434 | /* |
| 435 | * FIXME is this guaranteed to clear |
| 436 | * immediately or should we poll for it? |
| 437 | */ |
| 438 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); |
| 439 | } |
| 440 | |
| 441 | static void vlv_set_cdclk(struct drm_device *dev, int cdclk) |
| 442 | { |
| 443 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 444 | u32 val, cmd; |
| 445 | |
| 446 | WARN_ON(dev_priv->display.get_cdclk(dev_priv) != dev_priv->cdclk_freq); |
| 447 | |
| 448 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
| 449 | cmd = 2; |
| 450 | else if (cdclk == 266667) |
| 451 | cmd = 1; |
| 452 | else |
| 453 | cmd = 0; |
| 454 | |
| 455 | mutex_lock(&dev_priv->rps.hw_lock); |
| 456 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
| 457 | val &= ~DSPFREQGUAR_MASK; |
| 458 | val |= (cmd << DSPFREQGUAR_SHIFT); |
| 459 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); |
| 460 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & |
| 461 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), |
| 462 | 50)) { |
| 463 | DRM_ERROR("timed out waiting for CDclk change\n"); |
| 464 | } |
| 465 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 466 | |
| 467 | mutex_lock(&dev_priv->sb_lock); |
| 468 | |
| 469 | if (cdclk == 400000) { |
| 470 | u32 divider; |
| 471 | |
| 472 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, |
| 473 | cdclk) - 1; |
| 474 | |
| 475 | /* adjust cdclk divider */ |
| 476 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
| 477 | val &= ~CCK_FREQUENCY_VALUES; |
| 478 | val |= divider; |
| 479 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); |
| 480 | |
| 481 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & |
| 482 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
| 483 | 50)) |
| 484 | DRM_ERROR("timed out waiting for CDclk change\n"); |
| 485 | } |
| 486 | |
| 487 | /* adjust self-refresh exit latency value */ |
| 488 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); |
| 489 | val &= ~0x7f; |
| 490 | |
| 491 | /* |
| 492 | * For high bandwidth configs, we set a higher latency in the bunit |
| 493 | * so that the core display fetch happens in time to avoid underruns. |
| 494 | */ |
| 495 | if (cdclk == 400000) |
| 496 | val |= 4500 / 250; /* 4.5 usec */ |
| 497 | else |
| 498 | val |= 3000 / 250; /* 3.0 usec */ |
| 499 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); |
| 500 | |
| 501 | mutex_unlock(&dev_priv->sb_lock); |
| 502 | |
| 503 | intel_update_cdclk(dev_priv); |
| 504 | } |
| 505 | |
| 506 | static void chv_set_cdclk(struct drm_device *dev, int cdclk) |
| 507 | { |
| 508 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 509 | u32 val, cmd; |
| 510 | |
| 511 | WARN_ON(dev_priv->display.get_cdclk(dev_priv) != dev_priv->cdclk_freq); |
| 512 | |
| 513 | switch (cdclk) { |
| 514 | case 333333: |
| 515 | case 320000: |
| 516 | case 266667: |
| 517 | case 200000: |
| 518 | break; |
| 519 | default: |
| 520 | MISSING_CASE(cdclk); |
| 521 | return; |
| 522 | } |
| 523 | |
| 524 | /* |
| 525 | * Specs are full of misinformation, but testing on actual |
| 526 | * hardware has shown that we just need to write the desired |
| 527 | * CCK divider into the Punit register. |
| 528 | */ |
| 529 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
| 530 | |
| 531 | mutex_lock(&dev_priv->rps.hw_lock); |
| 532 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
| 533 | val &= ~DSPFREQGUAR_MASK_CHV; |
| 534 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); |
| 535 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); |
| 536 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & |
| 537 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), |
| 538 | 50)) { |
| 539 | DRM_ERROR("timed out waiting for CDclk change\n"); |
| 540 | } |
| 541 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 542 | |
| 543 | intel_update_cdclk(dev_priv); |
| 544 | } |
| 545 | |
| 546 | static int bdw_calc_cdclk(int max_pixclk) |
| 547 | { |
| 548 | if (max_pixclk > 540000) |
| 549 | return 675000; |
| 550 | else if (max_pixclk > 450000) |
| 551 | return 540000; |
| 552 | else if (max_pixclk > 337500) |
| 553 | return 450000; |
| 554 | else |
| 555 | return 337500; |
| 556 | } |
| 557 | |
| 558 | static int bdw_get_cdclk(struct drm_i915_private *dev_priv) |
| 559 | { |
| 560 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
| 561 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; |
| 562 | |
| 563 | if (lcpll & LCPLL_CD_SOURCE_FCLK) |
| 564 | return 800000; |
| 565 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
| 566 | return 450000; |
| 567 | else if (freq == LCPLL_CLK_FREQ_450) |
| 568 | return 450000; |
| 569 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) |
| 570 | return 540000; |
| 571 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) |
| 572 | return 337500; |
| 573 | else |
| 574 | return 675000; |
| 575 | } |
| 576 | |
| 577 | static void bdw_set_cdclk(struct drm_device *dev, int cdclk) |
| 578 | { |
| 579 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 580 | uint32_t val, data; |
| 581 | int ret; |
| 582 | |
| 583 | if (WARN((I915_READ(LCPLL_CTL) & |
| 584 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | |
| 585 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | |
| 586 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | |
| 587 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, |
| 588 | "trying to change cdclk frequency with cdclk not enabled\n")) |
| 589 | return; |
| 590 | |
| 591 | mutex_lock(&dev_priv->rps.hw_lock); |
| 592 | ret = sandybridge_pcode_write(dev_priv, |
| 593 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); |
| 594 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 595 | if (ret) { |
| 596 | DRM_ERROR("failed to inform pcode about cdclk change\n"); |
| 597 | return; |
| 598 | } |
| 599 | |
| 600 | val = I915_READ(LCPLL_CTL); |
| 601 | val |= LCPLL_CD_SOURCE_FCLK; |
| 602 | I915_WRITE(LCPLL_CTL, val); |
| 603 | |
| 604 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
| 605 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) |
| 606 | DRM_ERROR("Switching to FCLK failed\n"); |
| 607 | |
| 608 | val = I915_READ(LCPLL_CTL); |
| 609 | val &= ~LCPLL_CLK_FREQ_MASK; |
| 610 | |
| 611 | switch (cdclk) { |
| 612 | case 450000: |
| 613 | val |= LCPLL_CLK_FREQ_450; |
| 614 | data = 0; |
| 615 | break; |
| 616 | case 540000: |
| 617 | val |= LCPLL_CLK_FREQ_54O_BDW; |
| 618 | data = 1; |
| 619 | break; |
| 620 | case 337500: |
| 621 | val |= LCPLL_CLK_FREQ_337_5_BDW; |
| 622 | data = 2; |
| 623 | break; |
| 624 | case 675000: |
| 625 | val |= LCPLL_CLK_FREQ_675_BDW; |
| 626 | data = 3; |
| 627 | break; |
| 628 | default: |
| 629 | WARN(1, "invalid cdclk frequency\n"); |
| 630 | return; |
| 631 | } |
| 632 | |
| 633 | I915_WRITE(LCPLL_CTL, val); |
| 634 | |
| 635 | val = I915_READ(LCPLL_CTL); |
| 636 | val &= ~LCPLL_CD_SOURCE_FCLK; |
| 637 | I915_WRITE(LCPLL_CTL, val); |
| 638 | |
| 639 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
| 640 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
| 641 | DRM_ERROR("Switching back to LCPLL failed\n"); |
| 642 | |
| 643 | mutex_lock(&dev_priv->rps.hw_lock); |
| 644 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); |
| 645 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 646 | |
| 647 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); |
| 648 | |
| 649 | intel_update_cdclk(dev_priv); |
| 650 | |
| 651 | WARN(cdclk != dev_priv->cdclk_freq, |
| 652 | "cdclk requested %d kHz but got %d kHz\n", |
| 653 | cdclk, dev_priv->cdclk_freq); |
| 654 | } |
| 655 | |
| 656 | static int skl_calc_cdclk(int max_pixclk, int vco) |
| 657 | { |
| 658 | if (vco == 8640000) { |
| 659 | if (max_pixclk > 540000) |
| 660 | return 617143; |
| 661 | else if (max_pixclk > 432000) |
| 662 | return 540000; |
| 663 | else if (max_pixclk > 308571) |
| 664 | return 432000; |
| 665 | else |
| 666 | return 308571; |
| 667 | } else { |
| 668 | if (max_pixclk > 540000) |
| 669 | return 675000; |
| 670 | else if (max_pixclk > 450000) |
| 671 | return 540000; |
| 672 | else if (max_pixclk > 337500) |
| 673 | return 450000; |
| 674 | else |
| 675 | return 337500; |
| 676 | } |
| 677 | } |
| 678 | |
| 679 | static void skl_dpll0_update(struct drm_i915_private *dev_priv) |
| 680 | { |
| 681 | u32 val; |
| 682 | |
| 683 | dev_priv->cdclk_pll.ref = 24000; |
| 684 | dev_priv->cdclk_pll.vco = 0; |
| 685 | |
| 686 | val = I915_READ(LCPLL1_CTL); |
| 687 | if ((val & LCPLL_PLL_ENABLE) == 0) |
| 688 | return; |
| 689 | |
| 690 | if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) |
| 691 | return; |
| 692 | |
| 693 | val = I915_READ(DPLL_CTRL1); |
| 694 | |
| 695 | if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | |
| 696 | DPLL_CTRL1_SSC(SKL_DPLL0) | |
| 697 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != |
| 698 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) |
| 699 | return; |
| 700 | |
| 701 | switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { |
| 702 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): |
| 703 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): |
| 704 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): |
| 705 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): |
| 706 | dev_priv->cdclk_pll.vco = 8100000; |
| 707 | break; |
| 708 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): |
| 709 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): |
| 710 | dev_priv->cdclk_pll.vco = 8640000; |
| 711 | break; |
| 712 | default: |
| 713 | MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); |
| 714 | break; |
| 715 | } |
| 716 | } |
| 717 | |
| 718 | static int skl_get_cdclk(struct drm_i915_private *dev_priv) |
| 719 | { |
| 720 | u32 cdctl; |
| 721 | |
| 722 | skl_dpll0_update(dev_priv); |
| 723 | |
| 724 | if (dev_priv->cdclk_pll.vco == 0) |
| 725 | return dev_priv->cdclk_pll.ref; |
| 726 | |
| 727 | cdctl = I915_READ(CDCLK_CTL); |
| 728 | |
| 729 | if (dev_priv->cdclk_pll.vco == 8640000) { |
| 730 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
| 731 | case CDCLK_FREQ_450_432: |
| 732 | return 432000; |
| 733 | case CDCLK_FREQ_337_308: |
| 734 | return 308571; |
| 735 | case CDCLK_FREQ_540: |
| 736 | return 540000; |
| 737 | case CDCLK_FREQ_675_617: |
| 738 | return 617143; |
| 739 | default: |
| 740 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
| 741 | } |
| 742 | } else { |
| 743 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
| 744 | case CDCLK_FREQ_450_432: |
| 745 | return 450000; |
| 746 | case CDCLK_FREQ_337_308: |
| 747 | return 337500; |
| 748 | case CDCLK_FREQ_540: |
| 749 | return 540000; |
| 750 | case CDCLK_FREQ_675_617: |
| 751 | return 675000; |
| 752 | default: |
| 753 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
| 754 | } |
| 755 | } |
| 756 | |
| 757 | return dev_priv->cdclk_pll.ref; |
| 758 | } |
| 759 | |
| 760 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ |
| 761 | static int skl_cdclk_decimal(int cdclk) |
| 762 | { |
| 763 | return DIV_ROUND_CLOSEST(cdclk - 1000, 500); |
| 764 | } |
| 765 | |
| 766 | static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, |
| 767 | int vco) |
| 768 | { |
| 769 | bool changed = dev_priv->skl_preferred_vco_freq != vco; |
| 770 | |
| 771 | dev_priv->skl_preferred_vco_freq = vco; |
| 772 | |
| 773 | if (changed) |
| 774 | intel_update_max_cdclk(dev_priv); |
| 775 | } |
| 776 | |
| 777 | static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) |
| 778 | { |
| 779 | int min_cdclk = skl_calc_cdclk(0, vco); |
| 780 | u32 val; |
| 781 | |
| 782 | WARN_ON(vco != 8100000 && vco != 8640000); |
| 783 | |
| 784 | /* select the minimum CDCLK before enabling DPLL 0 */ |
| 785 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); |
| 786 | I915_WRITE(CDCLK_CTL, val); |
| 787 | POSTING_READ(CDCLK_CTL); |
| 788 | |
| 789 | /* |
| 790 | * We always enable DPLL0 with the lowest link rate possible, but still |
| 791 | * taking into account the VCO required to operate the eDP panel at the |
| 792 | * desired frequency. The usual DP link rates operate with a VCO of |
| 793 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. |
| 794 | * The modeset code is responsible for the selection of the exact link |
| 795 | * rate later on, with the constraint of choosing a frequency that |
| 796 | * works with vco. |
| 797 | */ |
| 798 | val = I915_READ(DPLL_CTRL1); |
| 799 | |
| 800 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | |
| 801 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); |
| 802 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); |
| 803 | if (vco == 8640000) |
| 804 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
| 805 | SKL_DPLL0); |
| 806 | else |
| 807 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, |
| 808 | SKL_DPLL0); |
| 809 | |
| 810 | I915_WRITE(DPLL_CTRL1, val); |
| 811 | POSTING_READ(DPLL_CTRL1); |
| 812 | |
| 813 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); |
| 814 | |
| 815 | if (intel_wait_for_register(dev_priv, |
| 816 | LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, |
| 817 | 5)) |
| 818 | DRM_ERROR("DPLL0 not locked\n"); |
| 819 | |
| 820 | dev_priv->cdclk_pll.vco = vco; |
| 821 | |
| 822 | /* We'll want to keep using the current vco from now on. */ |
| 823 | skl_set_preferred_cdclk_vco(dev_priv, vco); |
| 824 | } |
| 825 | |
| 826 | static void skl_dpll0_disable(struct drm_i915_private *dev_priv) |
| 827 | { |
| 828 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); |
| 829 | if (intel_wait_for_register(dev_priv, |
| 830 | LCPLL1_CTL, LCPLL_PLL_LOCK, 0, |
| 831 | 1)) |
| 832 | DRM_ERROR("Couldn't disable DPLL0\n"); |
| 833 | |
| 834 | dev_priv->cdclk_pll.vco = 0; |
| 835 | } |
| 836 | |
| 837 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, |
| 838 | int cdclk, int vco) |
| 839 | { |
| 840 | u32 freq_select, pcu_ack; |
| 841 | int ret; |
| 842 | |
| 843 | WARN_ON((cdclk == 24000) != (vco == 0)); |
| 844 | |
| 845 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", |
| 846 | cdclk, vco); |
| 847 | |
| 848 | mutex_lock(&dev_priv->rps.hw_lock); |
| 849 | ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, |
| 850 | SKL_CDCLK_PREPARE_FOR_CHANGE, |
| 851 | SKL_CDCLK_READY_FOR_CHANGE, |
| 852 | SKL_CDCLK_READY_FOR_CHANGE, 3); |
| 853 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 854 | if (ret) { |
| 855 | DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n", |
| 856 | ret); |
| 857 | return; |
| 858 | } |
| 859 | |
| 860 | /* set CDCLK_CTL */ |
| 861 | switch (cdclk) { |
| 862 | case 450000: |
| 863 | case 432000: |
| 864 | freq_select = CDCLK_FREQ_450_432; |
| 865 | pcu_ack = 1; |
| 866 | break; |
| 867 | case 540000: |
| 868 | freq_select = CDCLK_FREQ_540; |
| 869 | pcu_ack = 2; |
| 870 | break; |
| 871 | case 308571: |
| 872 | case 337500: |
| 873 | default: |
| 874 | freq_select = CDCLK_FREQ_337_308; |
| 875 | pcu_ack = 0; |
| 876 | break; |
| 877 | case 617143: |
| 878 | case 675000: |
| 879 | freq_select = CDCLK_FREQ_675_617; |
| 880 | pcu_ack = 3; |
| 881 | break; |
| 882 | } |
| 883 | |
| 884 | if (dev_priv->cdclk_pll.vco != 0 && |
| 885 | dev_priv->cdclk_pll.vco != vco) |
| 886 | skl_dpll0_disable(dev_priv); |
| 887 | |
| 888 | if (dev_priv->cdclk_pll.vco != vco) |
| 889 | skl_dpll0_enable(dev_priv, vco); |
| 890 | |
| 891 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); |
| 892 | POSTING_READ(CDCLK_CTL); |
| 893 | |
| 894 | /* inform PCU of the change */ |
| 895 | mutex_lock(&dev_priv->rps.hw_lock); |
| 896 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); |
| 897 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 898 | |
| 899 | intel_update_cdclk(dev_priv); |
| 900 | } |
| 901 | |
| 902 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
| 903 | { |
| 904 | uint32_t cdctl, expected; |
| 905 | |
| 906 | /* |
| 907 | * check if the pre-os initialized the display |
| 908 | * There is SWF18 scratchpad register defined which is set by the |
| 909 | * pre-os which can be used by the OS drivers to check the status |
| 910 | */ |
| 911 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) |
| 912 | goto sanitize; |
| 913 | |
| 914 | intel_update_cdclk(dev_priv); |
| 915 | /* Is PLL enabled and locked ? */ |
| 916 | if (dev_priv->cdclk_pll.vco == 0 || |
| 917 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) |
| 918 | goto sanitize; |
| 919 | |
| 920 | /* DPLL okay; verify the cdclock |
| 921 | * |
| 922 | * Noticed in some instances that the freq selection is correct but |
| 923 | * decimal part is programmed wrong from BIOS where pre-os does not |
| 924 | * enable display. Verify the same as well. |
| 925 | */ |
| 926 | cdctl = I915_READ(CDCLK_CTL); |
| 927 | expected = (cdctl & CDCLK_FREQ_SEL_MASK) | |
| 928 | skl_cdclk_decimal(dev_priv->cdclk_freq); |
| 929 | if (cdctl == expected) |
| 930 | /* All well; nothing to sanitize */ |
| 931 | return; |
| 932 | |
| 933 | sanitize: |
| 934 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); |
| 935 | |
| 936 | /* force cdclk programming */ |
| 937 | dev_priv->cdclk_freq = 0; |
| 938 | /* force full PLL disable + enable */ |
| 939 | dev_priv->cdclk_pll.vco = -1; |
| 940 | } |
| 941 | |
| 942 | /** |
| 943 | * skl_init_cdclk - Initialize CDCLK on SKL |
| 944 | * @dev_priv: i915 device |
| 945 | * |
| 946 | * Initialize CDCLK for SKL and derivatives. This is generally |
| 947 | * done only during the display core initialization sequence, |
| 948 | * after which the DMC will take care of turning CDCLK off/on |
| 949 | * as needed. |
| 950 | */ |
| 951 | void skl_init_cdclk(struct drm_i915_private *dev_priv) |
| 952 | { |
| 953 | int cdclk, vco; |
| 954 | |
| 955 | skl_sanitize_cdclk(dev_priv); |
| 956 | |
| 957 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) { |
| 958 | /* |
| 959 | * Use the current vco as our initial |
| 960 | * guess as to what the preferred vco is. |
| 961 | */ |
| 962 | if (dev_priv->skl_preferred_vco_freq == 0) |
| 963 | skl_set_preferred_cdclk_vco(dev_priv, |
| 964 | dev_priv->cdclk_pll.vco); |
| 965 | return; |
| 966 | } |
| 967 | |
| 968 | vco = dev_priv->skl_preferred_vco_freq; |
| 969 | if (vco == 0) |
| 970 | vco = 8100000; |
| 971 | cdclk = skl_calc_cdclk(0, vco); |
| 972 | |
| 973 | skl_set_cdclk(dev_priv, cdclk, vco); |
| 974 | } |
| 975 | |
| 976 | /** |
| 977 | * skl_uninit_cdclk - Uninitialize CDCLK on SKL |
| 978 | * @dev_priv: i915 device |
| 979 | * |
| 980 | * Uninitialize CDCLK for SKL and derivatives. This is done only |
| 981 | * during the display core uninitialization sequence. |
| 982 | */ |
| 983 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) |
| 984 | { |
| 985 | skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0); |
| 986 | } |
| 987 | |
| 988 | static int bxt_calc_cdclk(int max_pixclk) |
| 989 | { |
| 990 | if (max_pixclk > 576000) |
| 991 | return 624000; |
| 992 | else if (max_pixclk > 384000) |
| 993 | return 576000; |
| 994 | else if (max_pixclk > 288000) |
| 995 | return 384000; |
| 996 | else if (max_pixclk > 144000) |
| 997 | return 288000; |
| 998 | else |
| 999 | return 144000; |
| 1000 | } |
| 1001 | |
| 1002 | static int glk_calc_cdclk(int max_pixclk) |
| 1003 | { |
| 1004 | if (max_pixclk > 2 * 158400) |
| 1005 | return 316800; |
| 1006 | else if (max_pixclk > 2 * 79200) |
| 1007 | return 158400; |
| 1008 | else |
| 1009 | return 79200; |
| 1010 | } |
| 1011 | |
| 1012 | static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
| 1013 | { |
| 1014 | int ratio; |
| 1015 | |
| 1016 | if (cdclk == dev_priv->cdclk_pll.ref) |
| 1017 | return 0; |
| 1018 | |
| 1019 | switch (cdclk) { |
| 1020 | default: |
| 1021 | MISSING_CASE(cdclk); |
| 1022 | case 144000: |
| 1023 | case 288000: |
| 1024 | case 384000: |
| 1025 | case 576000: |
| 1026 | ratio = 60; |
| 1027 | break; |
| 1028 | case 624000: |
| 1029 | ratio = 65; |
| 1030 | break; |
| 1031 | } |
| 1032 | |
| 1033 | return dev_priv->cdclk_pll.ref * ratio; |
| 1034 | } |
| 1035 | |
| 1036 | static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
| 1037 | { |
| 1038 | int ratio; |
| 1039 | |
| 1040 | if (cdclk == dev_priv->cdclk_pll.ref) |
| 1041 | return 0; |
| 1042 | |
| 1043 | switch (cdclk) { |
| 1044 | default: |
| 1045 | MISSING_CASE(cdclk); |
| 1046 | case 79200: |
| 1047 | case 158400: |
| 1048 | case 316800: |
| 1049 | ratio = 33; |
| 1050 | break; |
| 1051 | } |
| 1052 | |
| 1053 | return dev_priv->cdclk_pll.ref * ratio; |
| 1054 | } |
| 1055 | |
| 1056 | static void bxt_de_pll_update(struct drm_i915_private *dev_priv) |
| 1057 | { |
| 1058 | u32 val; |
| 1059 | |
| 1060 | dev_priv->cdclk_pll.ref = 19200; |
| 1061 | dev_priv->cdclk_pll.vco = 0; |
| 1062 | |
| 1063 | val = I915_READ(BXT_DE_PLL_ENABLE); |
| 1064 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) |
| 1065 | return; |
| 1066 | |
| 1067 | if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) |
| 1068 | return; |
| 1069 | |
| 1070 | val = I915_READ(BXT_DE_PLL_CTL); |
| 1071 | dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) * |
| 1072 | dev_priv->cdclk_pll.ref; |
| 1073 | } |
| 1074 | |
| 1075 | static int bxt_get_cdclk(struct drm_i915_private *dev_priv) |
| 1076 | { |
| 1077 | u32 divider; |
| 1078 | int div, vco; |
| 1079 | |
| 1080 | bxt_de_pll_update(dev_priv); |
| 1081 | |
| 1082 | vco = dev_priv->cdclk_pll.vco; |
| 1083 | if (vco == 0) |
| 1084 | return dev_priv->cdclk_pll.ref; |
| 1085 | |
| 1086 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; |
| 1087 | |
| 1088 | switch (divider) { |
| 1089 | case BXT_CDCLK_CD2X_DIV_SEL_1: |
| 1090 | div = 2; |
| 1091 | break; |
| 1092 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: |
| 1093 | WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); |
| 1094 | div = 3; |
| 1095 | break; |
| 1096 | case BXT_CDCLK_CD2X_DIV_SEL_2: |
| 1097 | div = 4; |
| 1098 | break; |
| 1099 | case BXT_CDCLK_CD2X_DIV_SEL_4: |
| 1100 | div = 8; |
| 1101 | break; |
| 1102 | default: |
| 1103 | MISSING_CASE(divider); |
| 1104 | return dev_priv->cdclk_pll.ref; |
| 1105 | } |
| 1106 | |
| 1107 | return DIV_ROUND_CLOSEST(vco, div); |
| 1108 | } |
| 1109 | |
| 1110 | static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) |
| 1111 | { |
| 1112 | I915_WRITE(BXT_DE_PLL_ENABLE, 0); |
| 1113 | |
| 1114 | /* Timeout 200us */ |
| 1115 | if (intel_wait_for_register(dev_priv, |
| 1116 | BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0, |
| 1117 | 1)) |
| 1118 | DRM_ERROR("timeout waiting for DE PLL unlock\n"); |
| 1119 | |
| 1120 | dev_priv->cdclk_pll.vco = 0; |
| 1121 | } |
| 1122 | |
| 1123 | static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) |
| 1124 | { |
| 1125 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref); |
| 1126 | u32 val; |
| 1127 | |
| 1128 | val = I915_READ(BXT_DE_PLL_CTL); |
| 1129 | val &= ~BXT_DE_PLL_RATIO_MASK; |
| 1130 | val |= BXT_DE_PLL_RATIO(ratio); |
| 1131 | I915_WRITE(BXT_DE_PLL_CTL, val); |
| 1132 | |
| 1133 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); |
| 1134 | |
| 1135 | /* Timeout 200us */ |
| 1136 | if (intel_wait_for_register(dev_priv, |
| 1137 | BXT_DE_PLL_ENABLE, |
| 1138 | BXT_DE_PLL_LOCK, |
| 1139 | BXT_DE_PLL_LOCK, |
| 1140 | 1)) |
| 1141 | DRM_ERROR("timeout waiting for DE PLL lock\n"); |
| 1142 | |
| 1143 | dev_priv->cdclk_pll.vco = vco; |
| 1144 | } |
| 1145 | |
Ville Syrjälä | 8f0cfa4 | 2017-01-20 20:21:57 +0200 | [diff] [blame^] | 1146 | static void bxt_set_cdclk(struct drm_i915_private *dev_priv, |
| 1147 | int cdclk, int vco) |
Ville Syrjälä | 7ff89ca | 2017-02-07 20:33:05 +0200 | [diff] [blame] | 1148 | { |
| 1149 | u32 val, divider; |
Ville Syrjälä | 8f0cfa4 | 2017-01-20 20:21:57 +0200 | [diff] [blame^] | 1150 | int ret; |
Ville Syrjälä | 7ff89ca | 2017-02-07 20:33:05 +0200 | [diff] [blame] | 1151 | |
| 1152 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", |
| 1153 | cdclk, vco); |
| 1154 | |
| 1155 | /* cdclk = vco / 2 / div{1,1.5,2,4} */ |
| 1156 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { |
| 1157 | case 8: |
| 1158 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; |
| 1159 | break; |
| 1160 | case 4: |
| 1161 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; |
| 1162 | break; |
| 1163 | case 3: |
| 1164 | WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); |
| 1165 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; |
| 1166 | break; |
| 1167 | case 2: |
| 1168 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
| 1169 | break; |
| 1170 | default: |
| 1171 | WARN_ON(cdclk != dev_priv->cdclk_pll.ref); |
| 1172 | WARN_ON(vco != 0); |
| 1173 | |
| 1174 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
| 1175 | break; |
| 1176 | } |
| 1177 | |
| 1178 | /* Inform power controller of upcoming frequency change */ |
| 1179 | mutex_lock(&dev_priv->rps.hw_lock); |
| 1180 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
| 1181 | 0x80000000); |
| 1182 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 1183 | |
| 1184 | if (ret) { |
| 1185 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", |
| 1186 | ret, cdclk); |
| 1187 | return; |
| 1188 | } |
| 1189 | |
| 1190 | if (dev_priv->cdclk_pll.vco != 0 && |
| 1191 | dev_priv->cdclk_pll.vco != vco) |
| 1192 | bxt_de_pll_disable(dev_priv); |
| 1193 | |
| 1194 | if (dev_priv->cdclk_pll.vco != vco) |
| 1195 | bxt_de_pll_enable(dev_priv, vco); |
| 1196 | |
| 1197 | val = divider | skl_cdclk_decimal(cdclk); |
| 1198 | /* |
| 1199 | * FIXME if only the cd2x divider needs changing, it could be done |
| 1200 | * without shutting off the pipe (if only one pipe is active). |
| 1201 | */ |
| 1202 | val |= BXT_CDCLK_CD2X_PIPE_NONE; |
| 1203 | /* |
| 1204 | * Disable SSA Precharge when CD clock frequency < 500 MHz, |
| 1205 | * enable otherwise. |
| 1206 | */ |
| 1207 | if (cdclk >= 500000) |
| 1208 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; |
| 1209 | I915_WRITE(CDCLK_CTL, val); |
| 1210 | |
| 1211 | mutex_lock(&dev_priv->rps.hw_lock); |
| 1212 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
| 1213 | DIV_ROUND_UP(cdclk, 25000)); |
| 1214 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 1215 | |
| 1216 | if (ret) { |
| 1217 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", |
| 1218 | ret, cdclk); |
| 1219 | return; |
| 1220 | } |
| 1221 | |
| 1222 | intel_update_cdclk(dev_priv); |
| 1223 | } |
| 1224 | |
| 1225 | static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) |
| 1226 | { |
| 1227 | u32 cdctl, expected; |
| 1228 | |
| 1229 | intel_update_cdclk(dev_priv); |
| 1230 | |
| 1231 | if (dev_priv->cdclk_pll.vco == 0 || |
| 1232 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) |
| 1233 | goto sanitize; |
| 1234 | |
| 1235 | /* DPLL okay; verify the cdclock |
| 1236 | * |
| 1237 | * Some BIOS versions leave an incorrect decimal frequency value and |
| 1238 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, |
| 1239 | * so sanitize this register. |
| 1240 | */ |
| 1241 | cdctl = I915_READ(CDCLK_CTL); |
| 1242 | /* |
| 1243 | * Let's ignore the pipe field, since BIOS could have configured the |
| 1244 | * dividers both synching to an active pipe, or asynchronously |
| 1245 | * (PIPE_NONE). |
| 1246 | */ |
| 1247 | cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; |
| 1248 | |
| 1249 | expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | |
| 1250 | skl_cdclk_decimal(dev_priv->cdclk_freq); |
| 1251 | /* |
| 1252 | * Disable SSA Precharge when CD clock frequency < 500 MHz, |
| 1253 | * enable otherwise. |
| 1254 | */ |
| 1255 | if (dev_priv->cdclk_freq >= 500000) |
| 1256 | expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; |
| 1257 | |
| 1258 | if (cdctl == expected) |
| 1259 | /* All well; nothing to sanitize */ |
| 1260 | return; |
| 1261 | |
| 1262 | sanitize: |
| 1263 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); |
| 1264 | |
| 1265 | /* force cdclk programming */ |
| 1266 | dev_priv->cdclk_freq = 0; |
| 1267 | |
| 1268 | /* force full PLL disable + enable */ |
| 1269 | dev_priv->cdclk_pll.vco = -1; |
| 1270 | } |
| 1271 | |
| 1272 | /** |
| 1273 | * bxt_init_cdclk - Initialize CDCLK on BXT |
| 1274 | * @dev_priv: i915 device |
| 1275 | * |
| 1276 | * Initialize CDCLK for BXT and derivatives. This is generally |
| 1277 | * done only during the display core initialization sequence, |
| 1278 | * after which the DMC will take care of turning CDCLK off/on |
| 1279 | * as needed. |
| 1280 | */ |
| 1281 | void bxt_init_cdclk(struct drm_i915_private *dev_priv) |
| 1282 | { |
Ville Syrjälä | 8f0cfa4 | 2017-01-20 20:21:57 +0200 | [diff] [blame^] | 1283 | int cdclk, vco; |
Ville Syrjälä | 7ff89ca | 2017-02-07 20:33:05 +0200 | [diff] [blame] | 1284 | |
| 1285 | bxt_sanitize_cdclk(dev_priv); |
| 1286 | |
| 1287 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) |
| 1288 | return; |
| 1289 | |
| 1290 | /* |
| 1291 | * FIXME: |
| 1292 | * - The initial CDCLK needs to be read from VBT. |
| 1293 | * Need to make this change after VBT has changes for BXT. |
| 1294 | */ |
Ville Syrjälä | 8f0cfa4 | 2017-01-20 20:21:57 +0200 | [diff] [blame^] | 1295 | if (IS_GEMINILAKE(dev_priv)) { |
Ville Syrjälä | 7ff89ca | 2017-02-07 20:33:05 +0200 | [diff] [blame] | 1296 | cdclk = glk_calc_cdclk(0); |
Ville Syrjälä | 8f0cfa4 | 2017-01-20 20:21:57 +0200 | [diff] [blame^] | 1297 | vco = glk_de_pll_vco(dev_priv, cdclk); |
| 1298 | } else { |
Ville Syrjälä | 7ff89ca | 2017-02-07 20:33:05 +0200 | [diff] [blame] | 1299 | cdclk = bxt_calc_cdclk(0); |
Ville Syrjälä | 8f0cfa4 | 2017-01-20 20:21:57 +0200 | [diff] [blame^] | 1300 | vco = bxt_de_pll_vco(dev_priv, cdclk); |
| 1301 | } |
Ville Syrjälä | 7ff89ca | 2017-02-07 20:33:05 +0200 | [diff] [blame] | 1302 | |
Ville Syrjälä | 8f0cfa4 | 2017-01-20 20:21:57 +0200 | [diff] [blame^] | 1303 | bxt_set_cdclk(dev_priv, cdclk, vco); |
Ville Syrjälä | 7ff89ca | 2017-02-07 20:33:05 +0200 | [diff] [blame] | 1304 | } |
| 1305 | |
| 1306 | /** |
| 1307 | * bxt_uninit_cdclk - Uninitialize CDCLK on BXT |
| 1308 | * @dev_priv: i915 device |
| 1309 | * |
| 1310 | * Uninitialize CDCLK for BXT and derivatives. This is done only |
| 1311 | * during the display core uninitialization sequence. |
| 1312 | */ |
| 1313 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) |
| 1314 | { |
Ville Syrjälä | 8f0cfa4 | 2017-01-20 20:21:57 +0200 | [diff] [blame^] | 1315 | bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0); |
Ville Syrjälä | 7ff89ca | 2017-02-07 20:33:05 +0200 | [diff] [blame] | 1316 | } |
| 1317 | |
| 1318 | static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, |
| 1319 | int pixel_rate) |
| 1320 | { |
| 1321 | struct drm_i915_private *dev_priv = |
| 1322 | to_i915(crtc_state->base.crtc->dev); |
| 1323 | |
| 1324 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ |
| 1325 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
| 1326 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
| 1327 | |
| 1328 | /* BSpec says "Do not use DisplayPort with CDCLK less than |
| 1329 | * 432 MHz, audio enabled, port width x4, and link rate |
| 1330 | * HBR2 (5.4 GHz), or else there may be audio corruption or |
| 1331 | * screen corruption." |
| 1332 | */ |
| 1333 | if (intel_crtc_has_dp_encoder(crtc_state) && |
| 1334 | crtc_state->has_audio && |
| 1335 | crtc_state->port_clock >= 540000 && |
| 1336 | crtc_state->lane_count == 4) |
| 1337 | pixel_rate = max(432000, pixel_rate); |
| 1338 | |
| 1339 | return pixel_rate; |
| 1340 | } |
| 1341 | |
| 1342 | /* compute the max rate for new configuration */ |
| 1343 | static int intel_max_pixel_rate(struct drm_atomic_state *state) |
| 1344 | { |
| 1345 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
| 1346 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
| 1347 | struct drm_crtc *crtc; |
| 1348 | struct drm_crtc_state *cstate; |
| 1349 | struct intel_crtc_state *crtc_state; |
| 1350 | unsigned int max_pixel_rate = 0, i; |
| 1351 | enum pipe pipe; |
| 1352 | |
| 1353 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
| 1354 | sizeof(intel_state->min_pixclk)); |
| 1355 | |
| 1356 | for_each_crtc_in_state(state, crtc, cstate, i) { |
| 1357 | int pixel_rate; |
| 1358 | |
| 1359 | crtc_state = to_intel_crtc_state(cstate); |
| 1360 | if (!crtc_state->base.enable) { |
| 1361 | intel_state->min_pixclk[i] = 0; |
| 1362 | continue; |
| 1363 | } |
| 1364 | |
| 1365 | pixel_rate = crtc_state->pixel_rate; |
| 1366 | |
| 1367 | if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv)) |
| 1368 | pixel_rate = |
| 1369 | bdw_adjust_min_pipe_pixel_rate(crtc_state, |
| 1370 | pixel_rate); |
| 1371 | |
| 1372 | intel_state->min_pixclk[i] = pixel_rate; |
| 1373 | } |
| 1374 | |
| 1375 | for_each_pipe(dev_priv, pipe) |
| 1376 | max_pixel_rate = max(intel_state->min_pixclk[pipe], |
| 1377 | max_pixel_rate); |
| 1378 | |
| 1379 | return max_pixel_rate; |
| 1380 | } |
| 1381 | |
| 1382 | static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state) |
| 1383 | { |
| 1384 | struct drm_device *dev = state->dev; |
| 1385 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 1386 | int max_pixclk = intel_max_pixel_rate(state); |
| 1387 | struct intel_atomic_state *intel_state = |
| 1388 | to_intel_atomic_state(state); |
| 1389 | |
| 1390 | intel_state->cdclk = intel_state->dev_cdclk = |
| 1391 | vlv_calc_cdclk(dev_priv, max_pixclk); |
| 1392 | |
| 1393 | if (!intel_state->active_crtcs) |
| 1394 | intel_state->dev_cdclk = vlv_calc_cdclk(dev_priv, 0); |
| 1395 | |
| 1396 | return 0; |
| 1397 | } |
| 1398 | |
| 1399 | static void vlv_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
| 1400 | { |
| 1401 | struct drm_device *dev = old_state->dev; |
| 1402 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 1403 | struct intel_atomic_state *old_intel_state = |
| 1404 | to_intel_atomic_state(old_state); |
| 1405 | unsigned int req_cdclk = old_intel_state->dev_cdclk; |
| 1406 | |
| 1407 | /* |
| 1408 | * FIXME: We can end up here with all power domains off, yet |
| 1409 | * with a CDCLK frequency other than the minimum. To account |
| 1410 | * for this take the PIPE-A power domain, which covers the HW |
| 1411 | * blocks needed for the following programming. This can be |
| 1412 | * removed once it's guaranteed that we get here either with |
| 1413 | * the minimum CDCLK set, or the required power domains |
| 1414 | * enabled. |
| 1415 | */ |
| 1416 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); |
| 1417 | |
| 1418 | if (IS_CHERRYVIEW(dev_priv)) |
| 1419 | chv_set_cdclk(dev, req_cdclk); |
| 1420 | else |
| 1421 | vlv_set_cdclk(dev, req_cdclk); |
| 1422 | |
| 1423 | vlv_program_pfi_credits(dev_priv); |
| 1424 | |
| 1425 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
| 1426 | } |
| 1427 | |
| 1428 | static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state) |
| 1429 | { |
| 1430 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
| 1431 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
| 1432 | int max_pixclk = intel_max_pixel_rate(state); |
| 1433 | int cdclk; |
| 1434 | |
| 1435 | /* |
| 1436 | * FIXME should also account for plane ratio |
| 1437 | * once 64bpp pixel formats are supported. |
| 1438 | */ |
| 1439 | cdclk = bdw_calc_cdclk(max_pixclk); |
| 1440 | |
| 1441 | if (cdclk > dev_priv->max_cdclk_freq) { |
| 1442 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
| 1443 | cdclk, dev_priv->max_cdclk_freq); |
| 1444 | return -EINVAL; |
| 1445 | } |
| 1446 | |
| 1447 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
| 1448 | if (!intel_state->active_crtcs) |
| 1449 | intel_state->dev_cdclk = bdw_calc_cdclk(0); |
| 1450 | |
| 1451 | return 0; |
| 1452 | } |
| 1453 | |
| 1454 | static void bdw_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
| 1455 | { |
| 1456 | struct drm_device *dev = old_state->dev; |
| 1457 | struct intel_atomic_state *old_intel_state = |
| 1458 | to_intel_atomic_state(old_state); |
| 1459 | unsigned int req_cdclk = old_intel_state->dev_cdclk; |
| 1460 | |
| 1461 | bdw_set_cdclk(dev, req_cdclk); |
| 1462 | } |
| 1463 | |
| 1464 | static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) |
| 1465 | { |
| 1466 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
| 1467 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
| 1468 | const int max_pixclk = intel_max_pixel_rate(state); |
| 1469 | int vco = intel_state->cdclk_pll_vco; |
| 1470 | int cdclk; |
| 1471 | |
| 1472 | /* |
| 1473 | * FIXME should also account for plane ratio |
| 1474 | * once 64bpp pixel formats are supported. |
| 1475 | */ |
| 1476 | cdclk = skl_calc_cdclk(max_pixclk, vco); |
| 1477 | |
| 1478 | /* |
| 1479 | * FIXME move the cdclk caclulation to |
| 1480 | * compute_config() so we can fail gracegully. |
| 1481 | */ |
| 1482 | if (cdclk > dev_priv->max_cdclk_freq) { |
| 1483 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
| 1484 | cdclk, dev_priv->max_cdclk_freq); |
| 1485 | cdclk = dev_priv->max_cdclk_freq; |
| 1486 | } |
| 1487 | |
| 1488 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
| 1489 | if (!intel_state->active_crtcs) |
| 1490 | intel_state->dev_cdclk = skl_calc_cdclk(0, vco); |
| 1491 | |
| 1492 | return 0; |
| 1493 | } |
| 1494 | |
| 1495 | static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
| 1496 | { |
| 1497 | struct drm_i915_private *dev_priv = to_i915(old_state->dev); |
| 1498 | struct intel_atomic_state *intel_state = |
| 1499 | to_intel_atomic_state(old_state); |
| 1500 | unsigned int req_cdclk = intel_state->dev_cdclk; |
| 1501 | unsigned int req_vco = intel_state->cdclk_pll_vco; |
| 1502 | |
| 1503 | skl_set_cdclk(dev_priv, req_cdclk, req_vco); |
| 1504 | } |
| 1505 | |
| 1506 | static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) |
| 1507 | { |
| 1508 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
| 1509 | int max_pixclk = intel_max_pixel_rate(state); |
| 1510 | struct intel_atomic_state *intel_state = |
| 1511 | to_intel_atomic_state(state); |
| 1512 | int cdclk; |
| 1513 | |
| 1514 | if (IS_GEMINILAKE(dev_priv)) |
| 1515 | cdclk = glk_calc_cdclk(max_pixclk); |
| 1516 | else |
| 1517 | cdclk = bxt_calc_cdclk(max_pixclk); |
| 1518 | |
| 1519 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
| 1520 | |
| 1521 | if (!intel_state->active_crtcs) { |
| 1522 | if (IS_GEMINILAKE(dev_priv)) |
| 1523 | cdclk = glk_calc_cdclk(0); |
| 1524 | else |
| 1525 | cdclk = bxt_calc_cdclk(0); |
| 1526 | |
| 1527 | intel_state->dev_cdclk = cdclk; |
| 1528 | } |
| 1529 | |
| 1530 | return 0; |
| 1531 | } |
| 1532 | |
| 1533 | static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
| 1534 | { |
Ville Syrjälä | 8f0cfa4 | 2017-01-20 20:21:57 +0200 | [diff] [blame^] | 1535 | struct drm_i915_private *dev_priv = to_i915(old_state->dev); |
Ville Syrjälä | 7ff89ca | 2017-02-07 20:33:05 +0200 | [diff] [blame] | 1536 | struct intel_atomic_state *old_intel_state = |
| 1537 | to_intel_atomic_state(old_state); |
| 1538 | unsigned int req_cdclk = old_intel_state->dev_cdclk; |
Ville Syrjälä | 8f0cfa4 | 2017-01-20 20:21:57 +0200 | [diff] [blame^] | 1539 | unsigned int req_vco; |
Ville Syrjälä | 7ff89ca | 2017-02-07 20:33:05 +0200 | [diff] [blame] | 1540 | |
Ville Syrjälä | 8f0cfa4 | 2017-01-20 20:21:57 +0200 | [diff] [blame^] | 1541 | if (IS_GEMINILAKE(dev_priv)) |
| 1542 | req_vco = glk_de_pll_vco(dev_priv, req_cdclk); |
| 1543 | else |
| 1544 | req_vco = bxt_de_pll_vco(dev_priv, req_cdclk); |
| 1545 | |
| 1546 | bxt_set_cdclk(dev_priv, req_cdclk, req_vco); |
Ville Syrjälä | 7ff89ca | 2017-02-07 20:33:05 +0200 | [diff] [blame] | 1547 | } |
| 1548 | |
| 1549 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
| 1550 | { |
| 1551 | int max_cdclk_freq = dev_priv->max_cdclk_freq; |
| 1552 | |
| 1553 | if (IS_GEMINILAKE(dev_priv)) |
| 1554 | return 2 * max_cdclk_freq; |
| 1555 | else if (INTEL_INFO(dev_priv)->gen >= 9 || |
| 1556 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
| 1557 | return max_cdclk_freq; |
| 1558 | else if (IS_CHERRYVIEW(dev_priv)) |
| 1559 | return max_cdclk_freq*95/100; |
| 1560 | else if (INTEL_INFO(dev_priv)->gen < 4) |
| 1561 | return 2*max_cdclk_freq*90/100; |
| 1562 | else |
| 1563 | return max_cdclk_freq*90/100; |
| 1564 | } |
| 1565 | |
| 1566 | /** |
| 1567 | * intel_update_max_cdclk - Determine the maximum support CDCLK frequency |
| 1568 | * @dev_priv: i915 device |
| 1569 | * |
| 1570 | * Determine the maximum CDCLK frequency the platform supports, and also |
| 1571 | * derive the maximum dot clock frequency the maximum CDCLK frequency |
| 1572 | * allows. |
| 1573 | */ |
| 1574 | void intel_update_max_cdclk(struct drm_i915_private *dev_priv) |
| 1575 | { |
| 1576 | if (IS_GEN9_BC(dev_priv)) { |
| 1577 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
| 1578 | int max_cdclk, vco; |
| 1579 | |
| 1580 | vco = dev_priv->skl_preferred_vco_freq; |
| 1581 | WARN_ON(vco != 8100000 && vco != 8640000); |
| 1582 | |
| 1583 | /* |
| 1584 | * Use the lower (vco 8640) cdclk values as a |
| 1585 | * first guess. skl_calc_cdclk() will correct it |
| 1586 | * if the preferred vco is 8100 instead. |
| 1587 | */ |
| 1588 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) |
| 1589 | max_cdclk = 617143; |
| 1590 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) |
| 1591 | max_cdclk = 540000; |
| 1592 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) |
| 1593 | max_cdclk = 432000; |
| 1594 | else |
| 1595 | max_cdclk = 308571; |
| 1596 | |
| 1597 | dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); |
| 1598 | } else if (IS_GEMINILAKE(dev_priv)) { |
| 1599 | dev_priv->max_cdclk_freq = 316800; |
| 1600 | } else if (IS_BROXTON(dev_priv)) { |
| 1601 | dev_priv->max_cdclk_freq = 624000; |
| 1602 | } else if (IS_BROADWELL(dev_priv)) { |
| 1603 | /* |
| 1604 | * FIXME with extra cooling we can allow |
| 1605 | * 540 MHz for ULX and 675 Mhz for ULT. |
| 1606 | * How can we know if extra cooling is |
| 1607 | * available? PCI ID, VTB, something else? |
| 1608 | */ |
| 1609 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
| 1610 | dev_priv->max_cdclk_freq = 450000; |
| 1611 | else if (IS_BDW_ULX(dev_priv)) |
| 1612 | dev_priv->max_cdclk_freq = 450000; |
| 1613 | else if (IS_BDW_ULT(dev_priv)) |
| 1614 | dev_priv->max_cdclk_freq = 540000; |
| 1615 | else |
| 1616 | dev_priv->max_cdclk_freq = 675000; |
| 1617 | } else if (IS_CHERRYVIEW(dev_priv)) { |
| 1618 | dev_priv->max_cdclk_freq = 320000; |
| 1619 | } else if (IS_VALLEYVIEW(dev_priv)) { |
| 1620 | dev_priv->max_cdclk_freq = 400000; |
| 1621 | } else { |
| 1622 | /* otherwise assume cdclk is fixed */ |
| 1623 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; |
| 1624 | } |
| 1625 | |
| 1626 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
| 1627 | |
| 1628 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
| 1629 | dev_priv->max_cdclk_freq); |
| 1630 | |
| 1631 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", |
| 1632 | dev_priv->max_dotclk_freq); |
| 1633 | } |
| 1634 | |
| 1635 | /** |
| 1636 | * intel_update_cdclk - Determine the current CDCLK frequency |
| 1637 | * @dev_priv: i915 device |
| 1638 | * |
| 1639 | * Determine the current CDCLK frequency. |
| 1640 | */ |
| 1641 | void intel_update_cdclk(struct drm_i915_private *dev_priv) |
| 1642 | { |
| 1643 | dev_priv->cdclk_freq = dev_priv->display.get_cdclk(dev_priv); |
| 1644 | |
| 1645 | if (INTEL_GEN(dev_priv) >= 9) |
| 1646 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", |
| 1647 | dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco, |
| 1648 | dev_priv->cdclk_pll.ref); |
| 1649 | else |
| 1650 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", |
| 1651 | dev_priv->cdclk_freq); |
| 1652 | |
| 1653 | /* |
| 1654 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): |
| 1655 | * Programmng [sic] note: bit[9:2] should be programmed to the number |
| 1656 | * of cdclk that generates 4MHz reference clock freq which is used to |
| 1657 | * generate GMBus clock. This will vary with the cdclk freq. |
| 1658 | */ |
| 1659 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
| 1660 | I915_WRITE(GMBUSFREQ_VLV, |
| 1661 | DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
| 1662 | } |
| 1663 | |
| 1664 | static int pch_rawclk(struct drm_i915_private *dev_priv) |
| 1665 | { |
| 1666 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
| 1667 | } |
| 1668 | |
| 1669 | static int vlv_hrawclk(struct drm_i915_private *dev_priv) |
| 1670 | { |
| 1671 | /* RAWCLK_FREQ_VLV register updated from power well code */ |
| 1672 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
| 1673 | CCK_DISPLAY_REF_CLOCK_CONTROL); |
| 1674 | } |
| 1675 | |
| 1676 | static int g4x_hrawclk(struct drm_i915_private *dev_priv) |
| 1677 | { |
| 1678 | uint32_t clkcfg; |
| 1679 | |
| 1680 | /* hrawclock is 1/4 the FSB frequency */ |
| 1681 | clkcfg = I915_READ(CLKCFG); |
| 1682 | switch (clkcfg & CLKCFG_FSB_MASK) { |
| 1683 | case CLKCFG_FSB_400: |
| 1684 | return 100000; |
| 1685 | case CLKCFG_FSB_533: |
| 1686 | return 133333; |
| 1687 | case CLKCFG_FSB_667: |
| 1688 | return 166667; |
| 1689 | case CLKCFG_FSB_800: |
| 1690 | return 200000; |
| 1691 | case CLKCFG_FSB_1067: |
| 1692 | return 266667; |
| 1693 | case CLKCFG_FSB_1333: |
| 1694 | return 333333; |
| 1695 | /* these two are just a guess; one of them might be right */ |
| 1696 | case CLKCFG_FSB_1600: |
| 1697 | case CLKCFG_FSB_1600_ALT: |
| 1698 | return 400000; |
| 1699 | default: |
| 1700 | return 133333; |
| 1701 | } |
| 1702 | } |
| 1703 | |
| 1704 | /** |
| 1705 | * intel_update_rawclk - Determine the current RAWCLK frequency |
| 1706 | * @dev_priv: i915 device |
| 1707 | * |
| 1708 | * Determine the current RAWCLK frequency. RAWCLK is a fixed |
| 1709 | * frequency clock so this needs to done only once. |
| 1710 | */ |
| 1711 | void intel_update_rawclk(struct drm_i915_private *dev_priv) |
| 1712 | { |
| 1713 | if (HAS_PCH_SPLIT(dev_priv)) |
| 1714 | dev_priv->rawclk_freq = pch_rawclk(dev_priv); |
| 1715 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
| 1716 | dev_priv->rawclk_freq = vlv_hrawclk(dev_priv); |
| 1717 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) |
| 1718 | dev_priv->rawclk_freq = g4x_hrawclk(dev_priv); |
| 1719 | else |
| 1720 | /* no rawclk on other platforms, or no need to know it */ |
| 1721 | return; |
| 1722 | |
| 1723 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); |
| 1724 | } |
| 1725 | |
| 1726 | /** |
| 1727 | * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks |
| 1728 | * @dev_priv: i915 device |
| 1729 | */ |
| 1730 | void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) |
| 1731 | { |
| 1732 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
| 1733 | dev_priv->display.modeset_commit_cdclk = |
| 1734 | vlv_modeset_commit_cdclk; |
| 1735 | dev_priv->display.modeset_calc_cdclk = |
| 1736 | vlv_modeset_calc_cdclk; |
| 1737 | } else if (IS_BROADWELL(dev_priv)) { |
| 1738 | dev_priv->display.modeset_commit_cdclk = |
| 1739 | bdw_modeset_commit_cdclk; |
| 1740 | dev_priv->display.modeset_calc_cdclk = |
| 1741 | bdw_modeset_calc_cdclk; |
| 1742 | } else if (IS_GEN9_LP(dev_priv)) { |
| 1743 | dev_priv->display.modeset_commit_cdclk = |
| 1744 | bxt_modeset_commit_cdclk; |
| 1745 | dev_priv->display.modeset_calc_cdclk = |
| 1746 | bxt_modeset_calc_cdclk; |
| 1747 | } else if (IS_GEN9_BC(dev_priv)) { |
| 1748 | dev_priv->display.modeset_commit_cdclk = |
| 1749 | skl_modeset_commit_cdclk; |
| 1750 | dev_priv->display.modeset_calc_cdclk = |
| 1751 | skl_modeset_calc_cdclk; |
| 1752 | } |
| 1753 | |
| 1754 | if (IS_GEN9_BC(dev_priv)) |
| 1755 | dev_priv->display.get_cdclk = skl_get_cdclk; |
| 1756 | else if (IS_GEN9_LP(dev_priv)) |
| 1757 | dev_priv->display.get_cdclk = bxt_get_cdclk; |
| 1758 | else if (IS_BROADWELL(dev_priv)) |
| 1759 | dev_priv->display.get_cdclk = bdw_get_cdclk; |
| 1760 | else if (IS_HASWELL(dev_priv)) |
| 1761 | dev_priv->display.get_cdclk = hsw_get_cdclk; |
| 1762 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
| 1763 | dev_priv->display.get_cdclk = vlv_get_cdclk; |
| 1764 | else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) |
| 1765 | dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; |
| 1766 | else if (IS_GEN5(dev_priv)) |
| 1767 | dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; |
| 1768 | else if (IS_GM45(dev_priv)) |
| 1769 | dev_priv->display.get_cdclk = gm45_get_cdclk; |
| 1770 | else if (IS_G4X(dev_priv)) |
| 1771 | dev_priv->display.get_cdclk = g33_get_cdclk; |
| 1772 | else if (IS_I965GM(dev_priv)) |
| 1773 | dev_priv->display.get_cdclk = i965gm_get_cdclk; |
| 1774 | else if (IS_I965G(dev_priv)) |
| 1775 | dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; |
| 1776 | else if (IS_PINEVIEW(dev_priv)) |
| 1777 | dev_priv->display.get_cdclk = pnv_get_cdclk; |
| 1778 | else if (IS_G33(dev_priv)) |
| 1779 | dev_priv->display.get_cdclk = g33_get_cdclk; |
| 1780 | else if (IS_I945GM(dev_priv)) |
| 1781 | dev_priv->display.get_cdclk = i945gm_get_cdclk; |
| 1782 | else if (IS_I945G(dev_priv)) |
| 1783 | dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; |
| 1784 | else if (IS_I915GM(dev_priv)) |
| 1785 | dev_priv->display.get_cdclk = i915gm_get_cdclk; |
| 1786 | else if (IS_I915G(dev_priv)) |
| 1787 | dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk; |
| 1788 | else if (IS_I865G(dev_priv)) |
| 1789 | dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk; |
| 1790 | else if (IS_I85X(dev_priv)) |
| 1791 | dev_priv->display.get_cdclk = i85x_get_cdclk; |
| 1792 | else if (IS_I845G(dev_priv)) |
| 1793 | dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk; |
| 1794 | else { /* 830 */ |
| 1795 | WARN(!IS_I830(dev_priv), |
| 1796 | "Unknown platform. Assuming 133 MHz CDCLK\n"); |
| 1797 | dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; |
| 1798 | } |
| 1799 | } |